From ef756314dfcc6a7a7f60593630571701fa99579c Mon Sep 17 00:00:00 2001 From: Simone Manoni Date: Tue, 9 Dec 2025 11:33:02 +0100 Subject: [PATCH 1/5] Fix SG lint fatal error in axi dep --- hw/ips/axi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ips/axi b/hw/ips/axi index dff1de6..038e2a8 160000 --- a/hw/ips/axi +++ b/hw/ips/axi @@ -1 +1 @@ -Subproject commit dff1de6f48c3588c798e91e78e2f753bc24cf01d +Subproject commit 038e2a8fd849426bddc37dc02a4ee2934a977cab From 33707e7d1cd1617567b10456d90beb3f63445f23 Mon Sep 17 00:00:00 2001 From: Simone Manoni Date: Thu, 11 Dec 2025 11:54:40 +0100 Subject: [PATCH 2/5] Add python script to CI fix --- Makefile | 62 ++++++++++++++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/Makefile b/Makefile index 0404a77..1b35191 100644 --- a/Makefile +++ b/Makefile @@ -137,9 +137,13 @@ gen: update-serial-link # Questa $(BENDER) script flist-plus $(BENDER_SIM_TARGETS) $(BENDER_BASE_TARGETS) > sim/gen/sim.f sed -i 's?$(ROOT_DIR)?\$$CPROOT?g' sim/gen/sim.f + sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' sim/gen/sim.f + # Verilator $(BENDER) script verilator $(BENDER_BASE_TARGETS) > sim/gen/veri.f sed -i 's?$(ROOT_DIR)?\$$ROOT?g' sim/gen/veri.f + sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' sim/gen/veri.f + # Vivado $(BENDER) script vivado $(BENDER_BASE_TARGETS) --define PULP_FPGA_EMUL > fpga/gen/vivado.tcl $(BENDER) script vivado $(BENDER_BASE_TARGETS) --define PULP_FPGA_EMUL --only-includes --no-simset > fpga/gen/vivado_includes.tcl @@ -149,6 +153,7 @@ gen: update-serial-link if [[ -d nonfree ]]; then \ $(BENDER) script flist-plus $(BENDER_SYNTH_TARGETS) $(BENDER_BASE_TARGETS) > nonfree/gen/synopsys.f; \ sed -i 's?$(ROOT_DIR)?\$$CPROOT?g' nonfree/gen/synopsys.f; \ + sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' nonfree/gen/synopsys.f; \ fi .PHONY: update-serial-link @@ -269,13 +274,13 @@ vcs-simc: # Slang # SLANG ?= oseda slang -SLANG_DIR ?= $(ROOT_DIR)/lint +SLANG_DIR ?= $(ROOT_DIR)/util/lint/slang SLANG_PARSE_LOG ?= $(SLANG_DIR)/parse.log SLANG_LINT_LOG ?= $(SLANG_DIR)/lint.log SLANG_ELAB_LOG ?= $(SLANG_DIR)/elab.log -SV_FLIST ?= $(SLANG_DIR)/cp.flist +SV_FLIST ?= cp.flist -SLANG_FLAGS := -f cp.flist --timescale=1ns/1ns --top pms_top +SLANG_FLAGS := -f ../../../cp.flist --timescale=1ns/1ns --top pms_top SLANG_FLAGS += -G SIM_STDOUT=0 -G USE_CLUSTER=1 -G CORE_TYPE=0 -G RISCY_FPU=1 SLANG_FLAGS += --relax-enum-conversions --allow-use-before-declare -Wno-error=duplicate-definition @@ -283,12 +288,13 @@ BENDER_LINT_TARGETS += -t lint_pms FORCE: -$(SV_FLIST): $(ROOT_DIR)/Bender.yml $(ROOT_DIR)/Bender.lock - mkdir -p lint - $(BENDER) script flist-plus $(BENDER_LINT_TARGETS) $(BENDER_SYNTH_TARGETS) $(BENDER_BASE_TARGETS) -D SYNTHESIS > $@ +$(SV_FLIST): FORCE $(ROOT_DIR)/Bender.yml $(ROOT_DIR)/Bender.lock + $(BENDER) script flist-plus $(BENDER_BASE_TARGETS) -t synthesis -D SYNTHESIS > $@ sed -i 's?$(ROOT_DIR)?\$$CPROOT?g' $@ + sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' $@ $(SLANG_PARSE_LOG): FORCE $(SV_FLIST) + mkdir -p $(SLANG_DIR) @cd $(SLANG_DIR) && CPROOT=$(ROOT_DIR) $(SLANG) $(SLANG_FLAGS) --parse-only 2>&1 | tee $@ @echo "Slang parsing logged at: $@" @@ -319,13 +325,17 @@ cp-slang-all: cp-slang-flist cp-slang-parse cp-slang-lint cp-slang-elaborate # Spyglass # SNPS_SG ?= spyglass-2022.06 +SG_DIR ?= $(ROOT_DIR)/util/lint/spyglass +# Remove axi_cdc.sv coming from axi_slice_dc directory to void duplicate module definitions gen_sg_script: - mkdir -p spyglass/tmp - $(BENDER) script verilator $(BENDER_BASE_TARGETS) -D SYNTHESIS > lint/files + mkdir -p $(SG_DIR) + $(BENDER) script verilator $(BENDER_BASE_TARGETS) -D SYNTHESIS > $(SG_DIR)/cp_sg.f + sed -i 's?$(ROOT_DIR)?\$$CPROOT?g' $(SG_DIR)/cp_sg.f + sed -i '/axi_slice_dc\/.*axi_cdc\.sv/d' $(SG_DIR)/cp_sg.f -cp-sg-lint: gen_sg_script lint/func.sgdc lint/run_lint.tcl - cd lint; $(SNPS_SG) sg_shell -tcl run_lint.tcl +cp-sg-lint: gen_sg_script + cd $(SG_DIR) && CPROOT=$(ROOT_DIR) $(SNPS_SG) sg_shell -tcl run_sg_lint.tcl # DPI libraries # @@ -465,7 +475,7 @@ $(TEST_DIR)/runtime-tests/riscv_tests_soc: $(TEST_DIR)/runtime-tests test-rt-periph: source env/env.sh; \ touch $(TEST_DIR)/runtime-tests/simplified-periph-runtime.xml; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 7200 --yaml --max-procs 2 \ -o simplified-periph-runtime.xml periph-tests.yaml @@ -473,7 +483,7 @@ test-rt-periph: ## Run only ml tests on pulp-runtime test-rt-ml: $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-ml.xml ml-tests.yaml @@ -481,7 +491,7 @@ test-rt-ml: $(TEST_DIR)/runtime-tests ## Run only riscv tests on pulp-runtime test-rt-riscv: $(TEST_DIR)/runtime-tests $(TEST_DIR)/runtime-tests/riscv_tests_soc source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-riscv.xml riscv-tests.yaml @@ -489,7 +499,7 @@ test-rt-riscv: $(TEST_DIR)/runtime-tests $(TEST_DIR)/runtime-tests/riscv_tests_s ## Run only sequential tests on pulp-runtime test-rt-seq-bare: $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-sequential.xml sequential-bare-tests.yaml @@ -497,7 +507,7 @@ test-rt-seq-bare: $(TEST_DIR)/runtime-tests ## Run only parallel tests on pulp-runtime test-rt-par-bare: $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-parallel.xml parallel-bare-tests.yaml @@ -505,7 +515,7 @@ test-rt-par-bare: $(TEST_DIR)/runtime-tests ## Run control pulp tests on pulp-runtime test-rt-control-pulp: $(TEST_DIR)/control-pulp-tests source env/env.sh; \ - cd $(TEST_DIR)/control-pulp-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/control-pulp-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-control-pulp.xml control-pulp-tests.yaml @@ -513,7 +523,7 @@ test-rt-control-pulp: $(TEST_DIR)/control-pulp-tests ## Run tcdm tests on pulp-runtime test-rt-tcdm: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-tcdm.xml tcdm-tests.yaml @@ -521,7 +531,7 @@ test-rt-tcdm: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests ## Run soc_interconnect tests on pulp-runtime test-rt-soc-interconnect: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-soc-interconnect.xml soc-interconnect-tests.yaml @@ -529,7 +539,7 @@ test-rt-soc-interconnect: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests ## Run mchan tests on pulp-runtime test-rt-mchan: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-mchan.xml mchan-tests.yaml @@ -537,7 +547,7 @@ test-rt-mchan: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests ## Run idma tests on pulp-runtime test-rt-idma: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-mchan.xml idma-tests.yaml @@ -545,7 +555,7 @@ test-rt-idma: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests ## Run coremark tests on pulp-runtime test-rt-coremark: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-coremark.xml coremark-tests.yaml @@ -553,7 +563,7 @@ test-rt-coremark: $(PULP_RUNTIME) $(TEST_DIR)/runtime-tests ## Run performance counters sample test on pulp-runtime test-rt-perfcounters: $(TEST_DIR)/runtime-tests source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) --proc-verbose -v \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) --proc-verbose -v \ --report-junit -t 3600 --yaml --max-procs 2 \ -o runtime-perf-counters.xml perf-counters-tests.yaml @@ -561,28 +571,28 @@ test-rt-perfcounters: $(TEST_DIR)/runtime-tests ## Run tests to measure clock cycles required to receive data from the outside of the PMS (with and without DMA) test-rx-mchan: source env/env.sh; \ - cd $(TEST_DIR)/control-pulp-tests/sensors_transfers && $(BWRUNTEST) \ + cd $(TEST_DIR)/control-pulp-tests/sensors_transfers && python $(BWRUNTEST) \ --proc-verbose -v --report-junit -t 9800 --yaml -o sensors-tests.xml sensors-tests.yaml .PHONY: test-rx-idma ## Run tests to measure clock cycles required to receive data from the outside of the PMS (with and without DMA) in the cluster test-rx-idma: source env/env.sh; \ - cd $(TEST_DIR)/control-pulp-tests/pvt_sensors_idma_cl && $(BWRUNTEST) \ + cd $(TEST_DIR)/control-pulp-tests/pvt_sensors_idma_cl && python $(BWRUNTEST) \ --proc-verbose -v --report-junit -t 9800 --yaml -o sensors-tests.xml sensors-tests.yaml .PHONY: test-avs ## Run tests with AVS bus test-avs: source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests/peripherals/avs && $(BWRUNTEST) \ + cd $(TEST_DIR)/runtime-tests/peripherals/avs && python $(BWRUNTEST) \ --proc-verbose -v --report-junit -t 9800 --yaml -o avs-tests.xml avs-tests.yaml .PHONY: test-i2c-slv-irq ## Run tests with I2C slv with itnerrupt notification for end of transfer test-i2c-slv-irq: source env/env.sh; \ - cd $(TEST_DIR)/runtime-tests && $(BWRUNTEST) \ + cd $(TEST_DIR)/runtime-tests && python $(BWRUNTEST) \ --proc-verbose -v --report-junit -t 9800 --yaml -o i2c-slv-tests.xml i2c-slv-tests.yaml .PHONY: test-axislv From 3f575e6508fa90cf2e9a3d93717d256b1b505db5 Mon Sep 17 00:00:00 2001 From: Simone Manoni Date: Fri, 12 Dec 2025 12:05:32 +0100 Subject: [PATCH 3/5] Add SG lint scripts and patch CP for SG fatal issues --- Bender.yml | 2 - hw/pulp/control_pulp.sv | 3 + hw/pulp/pms_top.sv | 6 +- util/lint/spyglass/cp_sg.f | 1311 ++++++++++++++++++++++++++++ util/lint/spyglass/func.sgdc | 11 + util/lint/spyglass/run_sg_lint.tcl | 45 + 6 files changed, 1373 insertions(+), 5 deletions(-) create mode 100644 util/lint/spyglass/cp_sg.f create mode 100644 util/lint/spyglass/func.sgdc create mode 100644 util/lint/spyglass/run_sg_lint.tcl diff --git a/Bender.yml b/Bender.yml index 79a2e36..8232348 100644 --- a/Bender.yml +++ b/Bender.yml @@ -82,8 +82,6 @@ sources: - hw/ips/tech_cells_generic/src/deprecated/pad_functional.sv - hw/ips/tech_cells_generic/src/deprecated/pulp_buffer.sv - hw/ips/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv - - hw/ips/tech_cells_generic/src/tc_pwr.sv - - hw/ips/tech_cells_generic/test/tb_tc_sram.sv - hw/ips/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv - hw/ips/tech_cells_generic/src/deprecated/cluster_clk_cells.sv - hw/ips/tech_cells_generic/src/deprecated/pulp_clk_cells.sv diff --git a/hw/pulp/control_pulp.sv b/hw/pulp/control_pulp.sv index dfdf70f..47bce5b 100644 --- a/hw/pulp/control_pulp.sv +++ b/hw/pulp/control_pulp.sv @@ -642,6 +642,9 @@ module control_pulp import control_pulp_pkg::*; #( // Tie d2d link ports assign d2d_clk_o = '0; assign d2d_data_o = '0; + assign apb_serial_link_bus.prdata = '0; + assign apb_serial_link_bus.pready = 1'b0; + assign apb_serial_link_bus.pslverr = 1'b0; end // diff --git a/hw/pulp/pms_top.sv b/hw/pulp/pms_top.sv index b9c76d8..46a0246 100644 --- a/hw/pulp/pms_top.sv +++ b/hw/pulp/pms_top.sv @@ -59,9 +59,9 @@ module pms_top import pms_top_pkg::*; #( // D2D link parameter int unsigned USE_D2D = 0, parameter int unsigned USE_D2D_DELAY_LINE = 0, - parameter int unsigned D2D_NUM_CHANNELS = 0, - parameter int unsigned D2D_NUM_LANES = 0, - parameter int unsigned D2D_NUM_CREDITS = 0 + parameter int unsigned D2D_NUM_CHANNELS = 1, + parameter int unsigned D2D_NUM_LANES = 1, + parameter int unsigned D2D_NUM_CREDITS = 1 ) ( diff --git a/util/lint/spyglass/cp_sg.f b/util/lint/spyglass/cp_sg.f new file mode 100644 index 0000000..c387c02 --- /dev/null +++ b/util/lint/spyglass/cp_sg.f @@ -0,0 +1,1311 @@ + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_sram.sv +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_sram_impl.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_clk.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/cluster_clk_cells.sv +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/pulp_clk_cells.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/common_cells/src/binary_to_gray.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/common_cells/src/cb_filter_pkg.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/common_cells/src/cc_onehot.sv +$CPROOT/hw/ips/common_cells/src/cf_math_pkg.sv +$CPROOT/hw/ips/common_cells/src/clk_int_div.sv +$CPROOT/hw/ips/common_cells/src/delta_counter.sv +$CPROOT/hw/ips/common_cells/src/ecc_pkg.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_tx.sv +$CPROOT/hw/ips/common_cells/src/exp_backoff.sv +$CPROOT/hw/ips/common_cells/src/fifo_v3.sv +$CPROOT/hw/ips/common_cells/src/gray_to_binary.sv +$CPROOT/hw/ips/common_cells/src/isochronous_4phase_handshake.sv +$CPROOT/hw/ips/common_cells/src/isochronous_spill_register.sv +$CPROOT/hw/ips/common_cells/src/lfsr.sv +$CPROOT/hw/ips/common_cells/src/lfsr_16bit.sv +$CPROOT/hw/ips/common_cells/src/lfsr_8bit.sv +$CPROOT/hw/ips/common_cells/src/mv_filter.sv +$CPROOT/hw/ips/common_cells/src/onehot_to_bin.sv +$CPROOT/hw/ips/common_cells/src/plru_tree.sv +$CPROOT/hw/ips/common_cells/src/popcount.sv +$CPROOT/hw/ips/common_cells/src/rr_arb_tree.sv +$CPROOT/hw/ips/common_cells/src/rstgen_bypass.sv +$CPROOT/hw/ips/common_cells/src/serial_deglitch.sv +$CPROOT/hw/ips/common_cells/src/shift_reg.sv +$CPROOT/hw/ips/common_cells/src/shift_reg_gated.sv +$CPROOT/hw/ips/common_cells/src/spill_register_flushable.sv +$CPROOT/hw/ips/common_cells/src/stream_demux.sv +$CPROOT/hw/ips/common_cells/src/stream_filter.sv +$CPROOT/hw/ips/common_cells/src/stream_fork.sv +$CPROOT/hw/ips/common_cells/src/stream_intf.sv +$CPROOT/hw/ips/common_cells/src/stream_join.sv +$CPROOT/hw/ips/common_cells/src/stream_mux.sv +$CPROOT/hw/ips/common_cells/src/stream_throttle.sv +$CPROOT/hw/ips/common_cells/src/sub_per_hash.sv +$CPROOT/hw/ips/common_cells/src/sync.sv +$CPROOT/hw/ips/common_cells/src/sync_wedge.sv +$CPROOT/hw/ips/common_cells/src/unread.sv +$CPROOT/hw/ips/common_cells/src/read.sv +$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr_pkg.sv +$CPROOT/hw/ips/common_cells/src/addr_decode_napot.sv +$CPROOT/hw/ips/common_cells/src/cdc_2phase.sv +$CPROOT/hw/ips/common_cells/src/cdc_4phase.sv +$CPROOT/hw/ips/common_cells/src/addr_decode.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/common_cells/src/cb_filter.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/common_cells/src/cdc_fifo_2phase.sv +$CPROOT/hw/ips/common_cells/src/counter.sv +$CPROOT/hw/ips/common_cells/src/ecc_decode.sv +$CPROOT/hw/ips/common_cells/src/ecc_encode.sv +$CPROOT/hw/ips/common_cells/src/edge_detect.sv +$CPROOT/hw/ips/common_cells/src/lzc.sv +$CPROOT/hw/ips/common_cells/src/max_counter.sv +$CPROOT/hw/ips/common_cells/src/rstgen.sv +$CPROOT/hw/ips/common_cells/src/spill_register.sv +$CPROOT/hw/ips/common_cells/src/stream_delay.sv +$CPROOT/hw/ips/common_cells/src/stream_fifo.sv +$CPROOT/hw/ips/common_cells/src/stream_fork_dynamic.sv +$CPROOT/hw/ips/common_cells/src/clk_mux_glitch_free.sv +$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr.sv +$CPROOT/hw/ips/common_cells/src/cdc_fifo_gray.sv +$CPROOT/hw/ips/common_cells/src/fall_through_register.sv +$CPROOT/hw/ips/common_cells/src/id_queue.sv +$CPROOT/hw/ips/common_cells/src/stream_to_mem.sv +$CPROOT/hw/ips/common_cells/src/stream_arbiter_flushable.sv +$CPROOT/hw/ips/common_cells/src/stream_fifo_optimal_wrap.sv +$CPROOT/hw/ips/common_cells/src/stream_register.sv +$CPROOT/hw/ips/common_cells/src/stream_xbar.sv +$CPROOT/hw/ips/common_cells/src/cdc_fifo_gray_clearable.sv +$CPROOT/hw/ips/common_cells/src/cdc_2phase_clearable.sv +$CPROOT/hw/ips/common_cells/src/mem_to_banks.sv +$CPROOT/hw/ips/common_cells/src/stream_arbiter.sv +$CPROOT/hw/ips/common_cells/src/stream_omega_net.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clock_divider_counter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clk_div.sv +$CPROOT/hw/ips/common_cells/src/deprecated/find_first_one.sv +$CPROOT/hw/ips/common_cells/src/deprecated/generic_LFSR_8bit.sv +$CPROOT/hw/ips/common_cells/src/deprecated/generic_fifo.sv +$CPROOT/hw/ips/common_cells/src/deprecated/prioarbiter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/pulp_sync.sv +$CPROOT/hw/ips/common_cells/src/deprecated/pulp_sync_wedge.sv +$CPROOT/hw/ips/common_cells/src/deprecated/rrarbiter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clock_divider.sv +$CPROOT/hw/ips/common_cells/src/deprecated/fifo_v2.sv +$CPROOT/hw/ips/common_cells/src/deprecated/fifo_v1.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_ack.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_rx.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/control_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/apb/src/apb_intf.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/axi/src/axi_pkg.sv +$CPROOT/hw/ips/axi/src/axi_intf.sv +$CPROOT/hw/ips/axi/src/axi_atop_filter.sv +$CPROOT/hw/ips/axi/src/axi_burst_splitter.sv +$CPROOT/hw/ips/axi/src/axi_bus_compare.sv +$CPROOT/hw/ips/axi/src/axi_cdc_dst.sv +$CPROOT/hw/ips/axi/src/axi_cdc_src.sv +$CPROOT/hw/ips/axi/src/axi_cut.sv +$CPROOT/hw/ips/axi/src/axi_delayer.sv +$CPROOT/hw/ips/axi/src/axi_demux.sv +$CPROOT/hw/ips/axi/src/axi_dw_downsizer.sv +$CPROOT/hw/ips/axi/src/axi_dw_upsizer.sv +$CPROOT/hw/ips/axi/src/axi_fifo.sv +$CPROOT/hw/ips/axi/src/axi_id_remap.sv +$CPROOT/hw/ips/axi/src/axi_id_prepend.sv +$CPROOT/hw/ips/axi/src/axi_isolate.sv +$CPROOT/hw/ips/axi/src/axi_join.sv +$CPROOT/hw/ips/axi/src/axi_lite_demux.sv +$CPROOT/hw/ips/axi/src/axi_lite_dw_converter.sv +$CPROOT/hw/ips/axi/src/axi_lite_from_mem.sv +$CPROOT/hw/ips/axi/src/axi_lite_join.sv +$CPROOT/hw/ips/axi/src/axi_lite_lfsr.sv +$CPROOT/hw/ips/axi/src/axi_lite_mailbox.sv +$CPROOT/hw/ips/axi/src/axi_lite_mux.sv +$CPROOT/hw/ips/axi/src/axi_lite_regs.sv +$CPROOT/hw/ips/axi/src/axi_lite_to_apb.sv +$CPROOT/hw/ips/axi/src/axi_lite_to_axi.sv +$CPROOT/hw/ips/axi/src/axi_modify_address.sv +$CPROOT/hw/ips/axi/src/axi_mux.sv +$CPROOT/hw/ips/axi/src/axi_rw_join.sv +$CPROOT/hw/ips/axi/src/axi_rw_split.sv +$CPROOT/hw/ips/axi/src/axi_serializer.sv +$CPROOT/hw/ips/axi/src/axi_slave_compare.sv +$CPROOT/hw/ips/axi/src/axi_throttle.sv +$CPROOT/hw/ips/axi/src/axi_to_mem.sv +$CPROOT/hw/ips/axi/src/axi_cdc.sv +$CPROOT/hw/ips/axi/src/axi_err_slv.sv +$CPROOT/hw/ips/axi/src/axi_dw_converter.sv +$CPROOT/hw/ips/axi/src/axi_from_mem.sv +$CPROOT/hw/ips/axi/src/axi_id_serialize.sv +$CPROOT/hw/ips/axi/src/axi_lfsr.sv +$CPROOT/hw/ips/axi/src/axi_multicut.sv +$CPROOT/hw/ips/axi/src/axi_to_axi_lite.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_banked.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_interleaved.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_split.sv +$CPROOT/hw/ips/axi/src/axi_iw_converter.sv +$CPROOT/hw/ips/axi/src/axi_lite_xbar.sv +$CPROOT/hw/ips/axi/src/axi_xbar.sv +$CPROOT/hw/ips/axi/src/axi_xp.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/fpnew/src/fpnew_pkg.sv +$CPROOT/hw/ips/fpnew/src/fpnew_cast_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_classifier.sv +$CPROOT/hw/ips/fpnew/src/fpnew_divsqrt_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_fma.sv +$CPROOT/hw/ips/fpnew/src/fpnew_fma_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_noncomp.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_block.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_fmt_slice.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_multifmt_slice.sv +$CPROOT/hw/ips/fpnew/src/fpnew_rounding.sv +$CPROOT/hw/ips/fpnew/src/fpnew_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/axi_node/src/apb_regs_top.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_AR.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_AW.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_BR.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_BW.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_DW.sv +$CPROOT/hw/ips/axi_node/src/axi_AR_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_ArbitrationTree.sv +$CPROOT/hw/ips/axi_node/src/axi_AW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_BR_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_BW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_DW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_FanInPrimitive_Req.sv +$CPROOT/hw/ips/axi_node/src/axi_multiplexer.sv +$CPROOT/hw/ips/axi_node/src/axi_node.sv +$CPROOT/hw/ips/axi_node/src/axi_node_intf_wrap.sv +$CPROOT/hw/ips/axi_node/src/axi_node_wrap_with_slices.sv +$CPROOT/hw/ips/axi_node/src/axi_regs_top.sv +$CPROOT/hw/ips/axi_node/src/axi_request_block.sv +$CPROOT/hw/ips/axi_node/src/axi_response_block.sv +$CPROOT/hw/ips/axi_node/src/axi_RR_Flag_Req.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/axi_slice/src/axi_single_slice.sv +$CPROOT/hw/ips/axi_slice/src/axi_ar_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_aw_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_b_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_r_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_slice.sv +$CPROOT/hw/ips/axi_slice/src/axi_w_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_slice_wrap.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/cv32e40p/bhv ++incdir+$CPROOT/hw/ips/cv32e40p/rtl/include +$CPROOT/hw/ips/cv32e40p/rtl/include/cv32e40p_apu_core_pkg.sv +$CPROOT/hw/ips/cv32e40p/rtl/include/cv32e40p_fpu_pkg.sv +$CPROOT/hw/ips/cv32e40p/rtl/include/cv32e40p_pkg.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_alu.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_alu_div.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_aligner.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_compressed_decoder.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_controller.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_cs_registers.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_decoder.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_int_controller.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_ex_stage.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_fifo.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_hwloop_regs.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_id_stage.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_if_stage.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_load_store_unit.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_mult.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_prefetch_buffer.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_prefetch_controller.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_obi_interface.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_core.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_apu_disp.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_popcnt.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_ff_one.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_sleep_unit.sv +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_shadow_controller.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/cv32e40p/bhv ++incdir+$CPROOT/hw/ips/cv32e40p/rtl/include +$CPROOT/hw/ips/cv32e40p/rtl/cv32e40p_register_file_ff.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/cv32e40p/bhv ++incdir+$CPROOT/hw/ips/cv32e40p/rtl/include +$CPROOT/hw/ips/cv32e40p/bhv/cv32e40p_sim_clock_gate.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/icache-intc/Req_Arb_Node_icache_intc.sv +$CPROOT/hw/ips/icache-intc/Resp_Arb_Node_icache_intc.sv +$CPROOT/hw/ips/icache-intc/lint_mux.sv +$CPROOT/hw/ips/icache-intc/DistributedArbitrationNetwork_Req_icache_intc.sv +$CPROOT/hw/ips/icache-intc/DistributedArbitrationNetwork_Resp_icache_intc.sv +$CPROOT/hw/ips/icache-intc/RoutingBlock_Req_icache_intc.sv +$CPROOT/hw/ips/icache-intc/RoutingBlock_2ch_Req_icache_intc.sv +$CPROOT/hw/ips/icache-intc/RoutingBlock_Resp_icache_intc.sv +$CPROOT/hw/ips/icache-intc/icache_intc.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/register_interface/src/reg_intf.sv +$CPROOT/hw/ips/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv +$CPROOT/hw/ips/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv +$CPROOT/hw/ips/register_interface/src/apb_to_reg.sv +$CPROOT/hw/ips/register_interface/src/axi_to_reg.sv +$CPROOT/hw/ips/register_interface/src/periph_to_reg.sv +$CPROOT/hw/ips/register_interface/src/reg_cdc.sv +$CPROOT/hw/ips/register_interface/src/reg_demux.sv +$CPROOT/hw/ips/register_interface/src/reg_err_slv.sv +$CPROOT/hw/ips/register_interface/src/reg_mux.sv +$CPROOT/hw/ips/register_interface/src/reg_to_apb.sv +$CPROOT/hw/ips/register_interface/src/reg_to_mem.sv +$CPROOT/hw/ips/register_interface/src/reg_uniform.sv +$CPROOT/hw/ips/register_interface/src/reg_to_tlul.sv +$CPROOT/hw/ips/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv +$CPROOT/hw/ips/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv +$CPROOT/hw/ips/register_interface/src/axi_lite_to_reg.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_test_wrap.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_64b_multi_port_read_32b_1row.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_multi_port_read_1row.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_all.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_all_test_wrap.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_be.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_ff.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_latch.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1r_1w_1row.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_128b_multi_port_read_32b.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_64b_multi_port_read_32b.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_64b_1r_32b.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_multi_port_read_be.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_1w_multi_port_read.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_2r_1w_asymm.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_2r_1w_asymm_test_wrap.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_2r_2w.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_3r_2w.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_3r_2w_be.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_multi_way_1w_64b_multi_port_read_32b.sv +$CPROOT/hw/ips/scm/latch_scm/register_file_multi_way_1w_multi_port_read.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/udma_core/rtl +$CPROOT/hw/ips/udma_core/rtl/common/io_clk_gen.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_event_counter.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_generic_fifo.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_shiftreg.sv +$CPROOT/hw/ips/udma_core/rtl/common/udma_apb_if.sv +$CPROOT/hw/ips/udma_core/rtl/common/udma_clk_div_cnt.sv +$CPROOT/hw/ips/udma_core/rtl/common/udma_ctrl.sv +$CPROOT/hw/ips/udma_core/rtl/common/udma_dc_fifo.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_arbiter.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_ch_addrgen.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_tx_fifo.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_tx_fifo_dc.sv +$CPROOT/hw/ips/udma_core/rtl/common/io_tx_fifo_mark.sv +$CPROOT/hw/ips/udma_core/rtl/common/udma_clkgen.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_tx_channels.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_stream_unit.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_rx_channels.sv +$CPROOT/hw/ips/udma_core/rtl/core/udma_core.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/adv_dbg_if/rtl +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_axi_biu.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_axi_module.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_lint_biu.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_lint_module.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_crc32.v +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_or1k_biu.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_or1k_module.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_or1k_status_reg.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_top.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/bytefifo.v +$CPROOT/hw/ips/adv_dbg_if/rtl/syncflop.v +$CPROOT/hw/ips/adv_dbg_if/rtl/syncreg.v +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_tap_top.v +$CPROOT/hw/ips/adv_dbg_if/rtl/adv_dbg_if.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_axionly_top.sv +$CPROOT/hw/ips/adv_dbg_if/rtl/adbg_lintonly_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/apb2per/apb2per.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/apb_adv_timer/rtl +$CPROOT/hw/ips/apb_adv_timer/rtl/adv_timer_apb_if.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/comparator.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/input_stage.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/lut_4x4.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/out_filter.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/prescaler.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/timer_cntrl.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/up_down_counter.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/timer_module.sv +$CPROOT/hw/ips/apb_adv_timer/rtl/apb_adv_timer.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/apb_gpio/rtl/apb_gpio.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/apb_node/src/apb_node.sv +$CPROOT/hw/ips/apb_node/src/apb_node_wrap.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/axi2per/axi2per_req_channel.sv +$CPROOT/hw/ips/axi2per/axi2per_res_channel.sv +$CPROOT/hw/ips/axi2per/axi2per.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include +$CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_master.sv +$CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_slave.sv +$CPROOT/hw/ips/axi_slice_dc/src/dc_data_buffer.sv +$CPROOT/hw/ips/axi_slice_dc/src/dc_full_detector.v +$CPROOT/hw/ips/axi_slice_dc/src/dc_synchronizer.v +$CPROOT/hw/ips/axi_slice_dc/src/dc_token_ring_fifo_din.v +$CPROOT/hw/ips/axi_slice_dc/src/dc_token_ring_fifo_dout.v +$CPROOT/hw/ips/axi_slice_dc/src/dc_token_ring.v +$CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_master_wrap.sv +$CPROOT/hw/ips/axi_slice_dc/src/axi_slice_dc_slave_wrap.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/clic/src/clic_reg_pkg.sv +$CPROOT/hw/ips/clic/src/clic_reg_top.sv +$CPROOT/hw/ips/clic/src/clic_reg_adapter.sv +$CPROOT/hw/ips/clic/src/clic_gateway.sv +$CPROOT/hw/ips/clic/src/clic_target.sv +$CPROOT/hw/ips/clic/src/clic.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/addr_dec_resp_mux.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/amo_shim.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/variable_latency_interconnect/addr_decoder.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/xbar.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/variable_latency_interconnect/simplex_xbar.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/clos_net.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/bfly_net.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/variable_latency_interconnect/full_duplex_xbar.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_bfly_net.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/FanInPrimitive_Req.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/ArbitrationTree.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/MUX2_REQ.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/AddressDecoder_Resp.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/TestAndSet.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/RequestBlock2CH.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/RequestBlock1CH.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/FanInPrimitive_Resp.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/ResponseTree.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/ResponseBlock.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/AddressDecoder_Req.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/TCDM_PIPE_REQ.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/TCDM_PIPE_RESP.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco/priority_Flag_Req.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/ArbitrationTree_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/RR_Flag_Req_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/MUX2_REQ_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/RequestBlock1CH_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/RequestBlock2CH_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/ResponseBlock_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/ResponseTree_PE.sv +$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco/XBAR_PE.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/cluster_peripherals/cluster_control_unit/cluster_control_unit.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/cluster_peripherals/event_unit/include +$CPROOT/hw/ips/cluster_peripherals/event_unit/HW_barrier_logic.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/event_unit_arbiter.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/event_unit_mux.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/event_unit_sm.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/interrupt_mask.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/HW_barrier.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/event_unit_input.sv +$CPROOT/hw/ips/cluster_peripherals/event_unit/event_unit.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/mp_icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/new_icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/pri_icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/icache_ctrl_unit/sp_icache_ctrl_unit.sv +$CPROOT/hw/ips/cluster_peripherals/mmu_config_unit/mmu_config_unit.sv +$CPROOT/hw/ips/cluster_peripherals/perf_counters_unit/perf_counters_unit.sv +$CPROOT/hw/ips/cluster_peripherals/tcdm_pipe_unit/tcdm_pipe_unit.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/event_unit_flex/rtl +$CPROOT/hw/ips/event_unit_flex/rtl/event_unit_core.sv +$CPROOT/hw/ips/event_unit_flex/rtl/hw_barrier_unit.sv +$CPROOT/hw/ips/event_unit_flex/rtl/hw_dispatch.sv +$CPROOT/hw/ips/event_unit_flex/rtl/hw_mutex_unit.sv +$CPROOT/hw/ips/event_unit_flex/rtl/interc_sw_evt_trig.sv +$CPROOT/hw/ips/event_unit_flex/rtl/soc_periph_fifo.sv +$CPROOT/hw/ips/event_unit_flex/rtl/event_unit_interface_mux.sv +$CPROOT/hw/ips/event_unit_flex/rtl/event_unit_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/fpu_interco/FP_WRAP/fp_iter_divsqrt_msv_wrapper_2_STAGE.sv +$CPROOT/hw/ips/fpu_interco/FP_WRAP/fpnew_wrapper.sv +$CPROOT/hw/ips/fpu_interco/RTL/AddressDecoder_Resp_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/FanInPrimitive_Req_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/FanInPrimitive_Resp_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/FPU_clock_gating.sv +$CPROOT/hw/ips/fpu_interco/RTL/fpu_demux.sv +$CPROOT/hw/ips/fpu_interco/RTL/LFSR_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/optimal_alloc.sv +$CPROOT/hw/ips/fpu_interco/RTL/RR_Flag_Req_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/AddressDecoder_Req_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/ArbitrationTree_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/RequestBlock_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/ResponseTree_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/ResponseBlock_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/XBAR_FPU.sv +$CPROOT/hw/ips/fpu_interco/RTL/shared_fpu_cluster.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/hier-icache/CTRL_UNIT/hier_icache_ctrl_unit.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/icache_data_sram_wrap.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/icache_tag_sram_wrap.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/ram_ws_rs_data_scm.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/RefillTracker_4.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/REP_buffer_4.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/pri_icache_controller.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/refill_arbiter.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/register_file_1w_multi_port_read_ff.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/register_file_1w_multi_port_read_latch.sv +$CPROOT/hw/ips/hier-icache/CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/icache_controller.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv +$CPROOT/hw/ips/hier-icache/RTL/L1.5_CACHE/share_icache.sv +$CPROOT/hw/ips/hier-icache/RTL/L1_CACHE/pri_icache.sv +$CPROOT/hw/ips/hier-icache/RTL/TOP/icache_hier_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/jtag_pulp/src/bscell.sv +$CPROOT/hw/ips/jtag_pulp/src/jtag_axi_wrap.sv +$CPROOT/hw/ips/jtag_pulp/src/jtag_enable.sv +$CPROOT/hw/ips/jtag_pulp/src/jtag_enable_synch.sv +$CPROOT/hw/ips/jtag_pulp/src/jtagreg.sv +$CPROOT/hw/ips/jtag_pulp/src/jtag_rst_synch.sv +$CPROOT/hw/ips/jtag_pulp/src/jtag_sync.sv +$CPROOT/hw/ips/jtag_pulp/src/tap_top.v + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/l2_tcdm_demux.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/lint_2_apb.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/lint_2_axi.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/axi_2_lint/axi64_2_lint32.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/axi_2_lint/axi_read_ctrl.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/axi_2_lint/axi_write_ctrl.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/axi_2_lint/lint64_to_32.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/AddressDecoder_Req_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/AddressDecoder_Resp_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/ArbitrationTree_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/FanInPrimitive_Req_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/FanInPrimitive_Resp_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/MUX2_REQ_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/RequestBlock_L2_1CH.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/RequestBlock_L2_2CH.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/ResponseBlock_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/ResponseTree_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/RR_Flag_Req_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_L2/XBAR_L2.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/AddressDecoder_Req_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/AddressDecoder_Resp_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/ArbitrationTree_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/FanInPrimitive_Req_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/FanInPrimitive_Resp_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/MUX2_REQ_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/RequestBlock1CH_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/RequestBlock2CH_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/ResponseBlock_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/ResponseTree_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/RR_Flag_Req_BRIDGE.sv +$CPROOT/hw/ips/l2_tcdm_hybrid_interco/RTL/XBAR_BRIDGE/XBAR_BRIDGE.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/mchan/rtl/include +$CPROOT/hw/ips/mchan/rtl/misc/mchan_arbiter.sv +$CPROOT/hw/ips/mchan/rtl/misc/mchan_arb_primitive.sv +$CPROOT/hw/ips/mchan/rtl/misc/mchan_rr_flag_req.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/ctrl_fsm.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/ctrl_if.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/ctrl_unit.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/synch_unit.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/trans_allocator.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/trans_queue.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/trans_arbiter_wrap.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/trans_unpack.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/twd_trans_queue.sv +$CPROOT/hw/ips/mchan/rtl/ctrl_unit/twd_trans_splitter.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_ar_buffer.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_aw_buffer.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_b_buffer.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_buffer.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_opc_buf.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_r_buffer.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_rx_if.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_tid_gen.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_tx_if.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_unit.sv +$CPROOT/hw/ips/mchan/rtl/ext_unit/ext_w_buffer.sv +$CPROOT/hw/ips/mchan/rtl/tcdm_unit/tcdm_cmd_unpack.sv +$CPROOT/hw/ips/mchan/rtl/tcdm_unit/tcdm_rx_if.sv +$CPROOT/hw/ips/mchan/rtl/tcdm_unit/tcdm_synch.sv +$CPROOT/hw/ips/mchan/rtl/tcdm_unit/tcdm_tx_if.sv +$CPROOT/hw/ips/mchan/rtl/tcdm_unit/tcdm_unit.sv +$CPROOT/hw/ips/mchan/rtl/trans_unit/trans_aligner.sv +$CPROOT/hw/ips/mchan/rtl/trans_unit/trans_buffers.sv +$CPROOT/hw/ips/mchan/rtl/trans_unit/trans_unit.sv +$CPROOT/hw/ips/mchan/rtl/top/mchan.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/per2axi/src/per2axi_busy_unit.sv +$CPROOT/hw/ips/per2axi/src/per2axi_req_channel.sv +$CPROOT/hw/ips/per2axi/src/per2axi_res_channel.sv +$CPROOT/hw/ips/per2axi/src/per2axi.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/riscv-dbg/src/dm_pkg.sv +$CPROOT/hw/ips/riscv-dbg/debug_rom/debug_rom.sv +$CPROOT/hw/ips/riscv-dbg/debug_rom/debug_rom_one_scratch.sv +$CPROOT/hw/ips/riscv-dbg/src/dm_csrs.sv +$CPROOT/hw/ips/riscv-dbg/src/dm_mem.sv +$CPROOT/hw/ips/riscv-dbg/src/dmi_cdc.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/riscv-dbg/src/dmi_jtag_tap.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/riscv-dbg/src/dm_sba.sv +$CPROOT/hw/ips/riscv-dbg/src/dm_top.sv +$CPROOT/hw/ips/riscv-dbg/src/dmi_jtag.sv +$CPROOT/hw/ips/riscv-dbg/src/dm_obi_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/timer_unit/rtl/timer_unit_counter.sv +$CPROOT/hw/ips/timer_unit/rtl/timer_unit_counter_presc.sv +$CPROOT/hw/ips/timer_unit/rtl/apb_timer_unit.sv +$CPROOT/hw/ips/timer_unit/rtl/timer_unit.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/udma_filter/rtl/udma_filter_au.sv +$CPROOT/hw/ips/udma_filter/rtl/udma_filter_bincu.sv +$CPROOT/hw/ips/udma_filter/rtl/udma_filter_reg_if.sv +$CPROOT/hw/ips/udma_filter/rtl/udma_filter_rx_dataout.sv +$CPROOT/hw/ips/udma_filter/rtl/udma_filter_tx_datafetch.sv +$CPROOT/hw/ips/udma_filter/rtl/udma_filter.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/udma_i2c/rtl +$CPROOT/hw/ips/udma_i2c/rtl/udma_i2c_bus_ctrl.sv +$CPROOT/hw/ips/udma_i2c/rtl/udma_i2c_reg_if.sv +$CPROOT/hw/ips/udma_i2c/rtl/udma_i2c_control.sv +$CPROOT/hw/ips/udma_i2c/rtl/udma_i2c_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/udma_qspi/rtl +$CPROOT/hw/ips/udma_qspi/rtl/udma_spim_ctrl.sv +$CPROOT/hw/ips/udma_qspi/rtl/udma_spim_reg_if.sv +$CPROOT/hw/ips/udma_qspi/rtl/udma_spim_txrx.sv +$CPROOT/hw/ips/udma_qspi/rtl/udma_spim_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/udma_uart/rtl/udma_uart_reg_if.sv +$CPROOT/hw/ips/udma_uart/rtl/udma_uart_rx.sv +$CPROOT/hw/ips/udma_uart/rtl/udma_uart_tx.sv +$CPROOT/hw/ips/udma_uart/rtl/udma_uart_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/axi2mem/axi2mem.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/axi_apb_i2c_slave/src/axi_apb_i2c_slave.sv +$CPROOT/hw/ips/axi_apb_i2c_slave/src/i2cslave.sv +$CPROOT/hw/ips/axi_apb_i2c_slave/src/i2csend.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_pkg.sv +$CPROOT/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_top.sv +$CPROOT/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/axi_spi_slave/axi_spi_slave_wrap.sv +$CPROOT/hw/ips/axi_spi_slave/axi_spi_slave.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_axi_plug.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_cmd_parser.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_controller.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_dc_fifo.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_regs.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_rx.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_syncro.sv +$CPROOT/hw/ips/axi_spi_slave/spi_slave_tx.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/pkg/control_pulp_pkg.sv +$CPROOT/hw/pkg/pms_top_pkg.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/frontends/idma_transfer_id_gen.sv +$CPROOT/hw/ips/idma/src/idma_pkg.sv +$CPROOT/hw/ips/idma/src/idma_stream_fifo.sv +$CPROOT/hw/ips/idma/src/idma_buffer.sv +$CPROOT/hw/ips/idma/src/idma_error_handler.sv +$CPROOT/hw/ips/idma/src/idma_channel_coupler.sv +$CPROOT/hw/ips/idma/src/idma_axi_transport_layer.sv +$CPROOT/hw/ips/idma/src/idma_axi_lite_transport_layer.sv +$CPROOT/hw/ips/idma/src/idma_obi_transport_layer.sv +$CPROOT/hw/ips/idma/src/idma_legalizer.sv +$CPROOT/hw/ips/idma/src/idma_backend.sv +$CPROOT/hw/ips/idma/src/legacy/axi_dma_backend.sv +$CPROOT/hw/ips/idma/src/legacy/midends/idma_2D_midend.sv +$CPROOT/hw/ips/idma/src/midends/idma_nd_midend.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv +$CPROOT/hw/ips/idma/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv +$CPROOT/hw/ips/idma/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv +$CPROOT/hw/ips/idma/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv +$CPROOT/hw/ips/idma/src/frontends/register_64bit/idma_reg64_frontend.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/frontends/desc64/idma_desc64_reg_pkg.sv +$CPROOT/hw/ips/idma/src/frontends/desc64/idma_desc64_reg_top.sv +$CPROOT/hw/ips/idma/src/frontends/desc64/idma_desc64_shared_counter.sv +$CPROOT/hw/ips/idma/src/frontends/desc64/idma_desc64_reg_wrapper.sv +$CPROOT/hw/ips/idma/src/frontends/desc64/idma_desc64_top.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/systems/pulpopen/dmac_wrap_cl_idma.sv +$CPROOT/hw/ips/idma/src/systems/pulpopen/dmac_wrap_fc_idma.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/idma/src/synth_wrapper/idma_backend_synth.sv +$CPROOT/hw/ips/idma/src/synth_wrapper/idma_lite_backend_synth.sv +$CPROOT/hw/ips/idma/src/synth_wrapper/idma_obi_backend_synth.sv +$CPROOT/hw/ips/idma/src/synth_wrapper/idma_nd_backend_synth.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/pulp_cluster/packages/pulp_cluster_package.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_bus_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_clock_gate.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_event_map.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_timer_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/dmac_wrap_mchan.sv +$CPROOT/hw/ips/pulp_cluster/rtl/instr_width_converter.sv +$CPROOT/hw/ips/pulp_cluster/rtl/axi2per_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/per2axi_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/periph_demux.sv +$CPROOT/hw/ips/pulp_cluster/rtl/per_demux_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/periph_FIFO.sv +$CPROOT/hw/ips/pulp_cluster/rtl/tcdm_bank.sv +$CPROOT/hw/ips/pulp_cluster/rtl/tcdm_banks_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/xbar_pe_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_interconnect_wrap.sv +$CPROOT/hw/ips/pulp_cluster/rtl/cluster_peripherals.sv +$CPROOT/hw/ips/pulp_cluster/rtl/core_demux.sv + ++define+TRACE_EXECUTION ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/pulp_cluster/rtl/core_region.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include +$CPROOT/hw/ips/pulp_cluster/rtl/pulp_cluster.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/pulp_soc/rtl/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/pkg_soc_interconnect.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/axi64_2_lint32_wrap.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/lint_2_axi_wrap.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/contiguous_crossbar.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/interleaved_crossbar.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/tcdm_demux.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/boot_rom.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/asic_autogen_rom.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/l2_ram_bank_interleaved.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/l2_ram_bank_private.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/l2_ram_multi_bank.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/lint_jtag_wrap.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/periph_bus_wrap.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_event_arbiter.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_event_generator.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_event_queue.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/tcdm_error_slave.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_interconnect_wrap.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/soc_peripherals.sv +$CPROOT/hw/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/pulp_soc/rtl/udma_subsystem/udma_subsystem.sv + ++define+TRACE_EXECUTION ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/pulp_soc/rtl/fc/fc_demux.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/fc_subsystem.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/cv32e40p_fp_wrapper.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/event_to_level_int.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_clkdiv.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_soc_ctrl.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/memory_models.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/pulp_interfaces.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/glitch_free_clk_mux.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/tcdm_arbiter_2x1.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/obi_pulp_adapter.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include +$CPROOT/hw/ips/pulp_soc/rtl/components/glitch_free_clk_mux.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_dummy.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include ++incdir+$CPROOT/hw/ips/serial_link/src/axis/include +$CPROOT/hw/ips/serial_link/src/regs/serial_link_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_delay_line_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_delay_line_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_delay_line_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_delay_line_reg_top.sv +$CPROOT/hw/ips/serial_link/src/serial_link_pkg.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/stream_chopper.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/stream_dechopper.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/channel_despread_sfr.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/channel_spread_sfr.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/serial_link_channel_allocator.sv +$CPROOT/hw/ips/serial_link/src/serial_link_network.sv +$CPROOT/hw/ips/serial_link/src/serial_link_data_link.sv +$CPROOT/hw/ips/serial_link/src/serial_link_physical.sv +$CPROOT/hw/ips/serial_link/src/serial_link_physical_delay_line.sv +$CPROOT/hw/ips/serial_link/src/serial_link.sv +$CPROOT/hw/ips/serial_link/src/serial_link_wrapper.sv +$CPROOT/hw/ips/serial_link/src/serial_link_occamy_wrapper.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/register_interface/include ++incdir+$CPROOT/hw/ips/serial_link/src/axis/include +$CPROOT/hw/ips/serial_link/src/serial_link_synth_wrapper.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS +$CPROOT/hw/ips/wdt/src/counter_wdt.sv +$CPROOT/hw/ips/wdt/src/ovf_detect.sv +$CPROOT/hw/ips/wdt/src/wdt.sv + ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+TARGET_VERILATOR ++define+SYNTHESIS ++incdir+$CPROOT/hw/includes ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/register_interface/include ++incdir+$CPROOT/hw/ips/serial_link/src/axis/include +$CPROOT/hw/pulp/jtag_tap_top.sv +$CPROOT/hw/pulp/pad_control.sv +$CPROOT/hw/pulp/system_clk_rst_gen.sv +$CPROOT/hw/pulp/cluster_domain.sv +$CPROOT/hw/pulp/soc_domain.sv +$CPROOT/hw/pulp/control_pulp.sv +$CPROOT/hw/pulp/pms_top.sv +$CPROOT/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv +$CPROOT/hw/pulp/pms_top_fpga_behav.sv +$CPROOT/hw/pulp/control_pulp_fpga.sv + diff --git a/util/lint/spyglass/func.sgdc b/util/lint/spyglass/func.sgdc new file mode 100644 index 0000000..df9a86b --- /dev/null +++ b/util/lint/spyglass/func.sgdc @@ -0,0 +1,11 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +current_design pms_top +test_mode -name "pms_top.dft_test_mode_i" -value "0" +reset -name "rst_ni" -async -value 0 +reset -name "jtag_trst_ni" -async -value 0 +clock -name "sys_clk_i" -period 1.25 -domain sys_clk_domain +clock -name "ref_clk_i" -period 10.0 -domain ref_clk_domain +quasi_static -name "s_clk_mux_sel" \ No newline at end of file diff --git a/util/lint/spyglass/run_sg_lint.tcl b/util/lint/spyglass/run_sg_lint.tcl new file mode 100644 index 0000000..6175f9f --- /dev/null +++ b/util/lint/spyglass/run_sg_lint.tcl @@ -0,0 +1,45 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +set PROJECT pms +set TIMESTAMP [exec date +%Y%m%d_%H%M%S] + +# Add ignored files to this list +#set IgnoredFiles [list [exec bender path cva6]/core/include/axi_intf.sv] + +new_project sg_projects/${PROJECT}_${TIMESTAMP} +current_methodology $env(SPYGLASS_HOME)/GuideWare/latest/block/rtl_handoff + +# Ignore re-defined files +#foreach file $IgnoredFiles { +# set_option ignorefile $file +#} + +# Read the RTL +read_file -type sourcelist cp_sg.f + +# Read constraints +read_file -type sgdc func.sgdc + +# Set options +set_option enableSV12 yes +set_option language_mode mixed +set_option designread_disable_flatten no +set_option mthresh 32768 +set_option top pms_top + +# Link Design +current_design pms_top +compile_design + +# Set lint_rtl goal and run +current_goal lint/lint_rtl +run_goal + +# Create a link to the results +exec rm -rf sg_projects/${PROJECT} +exec ln -sf ${PROJECT}_${TIMESTAMP} sg_projects/${PROJECT} + +# Ciao! +exit -save \ No newline at end of file From a007a4cda7da72fe96b188debf0b7f3f5eecde9e Mon Sep 17 00:00:00 2001 From: Simone Manoni Date: Fri, 16 Jan 2026 11:09:55 +0100 Subject: [PATCH 4/5] Add SG lint to CI jobs --- .gitlab-ci.yml | 10 +- cp.flist | 712 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 721 insertions(+), 1 deletion(-) create mode 100644 cp.flist diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 403a538..a98a42b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -66,8 +66,16 @@ slang: stage: lint script: - make cp-slang-all - - (! grep -n "error:" lint/elab.log) + - (! grep -n "error:" util/lint/slang/elab.log) +spyglass: + extends: .base + stage: lint + script: + - make cp-sg-lint + - (! grep -n "Fatal" util/lint/spyglass/sg_projects/pms/pms_top/Design_Read/spyglass_reports/moresimple.rpt) + - (! grep -n "Fatal" util/lint/spyglass/sg_projects/pms/pms_top/lint/lint_rtl/spyglass_reports/moresimple.rpt) + artifacts: name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA" paths: diff --git a/cp.flist b/cp.flist new file mode 100644 index 0000000..930bb0c --- /dev/null +++ b/cp.flist @@ -0,0 +1,712 @@ ++incdir+$CPROOT/hw/includes ++incdir+$CPROOT/hw/ips/adv_dbg_if/rtl ++incdir+$CPROOT/hw/ips/apb_adv_timer/rtl ++incdir+$CPROOT/hw/ips/axi/include ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/low_latency_interco ++incdir+$CPROOT/hw/ips/cluster_interconnect/rtl/peripheral_interco ++incdir+$CPROOT/hw/ips/cluster_peripherals/event_unit/include ++incdir+$CPROOT/hw/ips/common_cells/include ++incdir+$CPROOT/hw/ips/cv32e40p/bhv ++incdir+$CPROOT/hw/ips/cv32e40p/rtl/include ++incdir+$CPROOT/hw/ips/event_unit_flex/rtl ++incdir+$CPROOT/hw/ips/idma/src/include ++incdir+$CPROOT/hw/ips/mchan/rtl/include ++incdir+$CPROOT/hw/ips/pulp_soc/rtl/include ++incdir+$CPROOT/hw/ips/register_interface/include ++incdir+$CPROOT/hw/ips/serial_link/src/axis/include ++incdir+$CPROOT/hw/ips/udma_core/rtl ++incdir+$CPROOT/hw/ips/udma_i2c/rtl ++incdir+$CPROOT/hw/ips/udma_qspi/rtl ++define+TRACE_EXECUTION ++define+TARGET_CV32E40P_USE_FF_REGFILE ++define+TARGET_FLIST ++define+TARGET_PULP ++define+TARGET_RTL ++define+TARGET_SYNTHESIS ++define+SYNTHESIS +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_sram.sv +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_sram_impl.sv +$CPROOT/hw/ips/tech_cells_generic/src/rtl/tc_clk.sv +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/cluster_clk_cells.sv +$CPROOT/hw/ips/tech_cells_generic/src/deprecated/pulp_clk_cells.sv +$CPROOT/hw/ips/common_cells/src/binary_to_gray.sv +$CPROOT/hw/ips/common_cells/src/cb_filter_pkg.sv +$CPROOT/hw/ips/common_cells/src/cc_onehot.sv +$CPROOT/hw/ips/common_cells/src/cf_math_pkg.sv +$CPROOT/hw/ips/common_cells/src/clk_int_div.sv +$CPROOT/hw/ips/common_cells/src/delta_counter.sv +$CPROOT/hw/ips/common_cells/src/ecc_pkg.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_tx.sv +$CPROOT/hw/ips/common_cells/src/exp_backoff.sv +$CPROOT/hw/ips/common_cells/src/fifo_v3.sv +$CPROOT/hw/ips/common_cells/src/gray_to_binary.sv +$CPROOT/hw/ips/common_cells/src/isochronous_4phase_handshake.sv +$CPROOT/hw/ips/common_cells/src/isochronous_spill_register.sv +$CPROOT/hw/ips/common_cells/src/lfsr.sv +$CPROOT/hw/ips/common_cells/src/lfsr_16bit.sv +$CPROOT/hw/ips/common_cells/src/lfsr_8bit.sv +$CPROOT/hw/ips/common_cells/src/mv_filter.sv +$CPROOT/hw/ips/common_cells/src/onehot_to_bin.sv +$CPROOT/hw/ips/common_cells/src/plru_tree.sv +$CPROOT/hw/ips/common_cells/src/popcount.sv +$CPROOT/hw/ips/common_cells/src/rr_arb_tree.sv +$CPROOT/hw/ips/common_cells/src/rstgen_bypass.sv +$CPROOT/hw/ips/common_cells/src/serial_deglitch.sv +$CPROOT/hw/ips/common_cells/src/shift_reg.sv +$CPROOT/hw/ips/common_cells/src/shift_reg_gated.sv +$CPROOT/hw/ips/common_cells/src/spill_register_flushable.sv +$CPROOT/hw/ips/common_cells/src/stream_demux.sv +$CPROOT/hw/ips/common_cells/src/stream_filter.sv +$CPROOT/hw/ips/common_cells/src/stream_fork.sv +$CPROOT/hw/ips/common_cells/src/stream_intf.sv +$CPROOT/hw/ips/common_cells/src/stream_join.sv +$CPROOT/hw/ips/common_cells/src/stream_mux.sv +$CPROOT/hw/ips/common_cells/src/stream_throttle.sv +$CPROOT/hw/ips/common_cells/src/sub_per_hash.sv +$CPROOT/hw/ips/common_cells/src/sync.sv +$CPROOT/hw/ips/common_cells/src/sync_wedge.sv +$CPROOT/hw/ips/common_cells/src/unread.sv +$CPROOT/hw/ips/common_cells/src/read.sv +$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr_pkg.sv +$CPROOT/hw/ips/common_cells/src/addr_decode_napot.sv +$CPROOT/hw/ips/common_cells/src/cdc_2phase.sv +$CPROOT/hw/ips/common_cells/src/cdc_4phase.sv +$CPROOT/hw/ips/common_cells/src/addr_decode.sv +$CPROOT/hw/ips/common_cells/src/cb_filter.sv +$CPROOT/hw/ips/common_cells/src/cdc_fifo_2phase.sv +$CPROOT/hw/ips/common_cells/src/counter.sv +$CPROOT/hw/ips/common_cells/src/ecc_decode.sv +$CPROOT/hw/ips/common_cells/src/ecc_encode.sv +$CPROOT/hw/ips/common_cells/src/edge_detect.sv +$CPROOT/hw/ips/common_cells/src/lzc.sv +$CPROOT/hw/ips/common_cells/src/max_counter.sv +$CPROOT/hw/ips/common_cells/src/rstgen.sv +$CPROOT/hw/ips/common_cells/src/spill_register.sv +$CPROOT/hw/ips/common_cells/src/stream_delay.sv +$CPROOT/hw/ips/common_cells/src/stream_fifo.sv +$CPROOT/hw/ips/common_cells/src/stream_fork_dynamic.sv +$CPROOT/hw/ips/common_cells/src/clk_mux_glitch_free.sv +$CPROOT/hw/ips/common_cells/src/cdc_reset_ctrlr.sv +$CPROOT/hw/ips/common_cells/src/cdc_fifo_gray.sv +$CPROOT/hw/ips/common_cells/src/fall_through_register.sv +$CPROOT/hw/ips/common_cells/src/id_queue.sv +$CPROOT/hw/ips/common_cells/src/stream_to_mem.sv +$CPROOT/hw/ips/common_cells/src/stream_arbiter_flushable.sv +$CPROOT/hw/ips/common_cells/src/stream_fifo_optimal_wrap.sv +$CPROOT/hw/ips/common_cells/src/stream_register.sv +$CPROOT/hw/ips/common_cells/src/stream_xbar.sv +$CPROOT/hw/ips/common_cells/src/cdc_fifo_gray_clearable.sv +$CPROOT/hw/ips/common_cells/src/cdc_2phase_clearable.sv +$CPROOT/hw/ips/common_cells/src/mem_to_banks.sv +$CPROOT/hw/ips/common_cells/src/stream_arbiter.sv +$CPROOT/hw/ips/common_cells/src/stream_omega_net.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clock_divider_counter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clk_div.sv +$CPROOT/hw/ips/common_cells/src/deprecated/find_first_one.sv +$CPROOT/hw/ips/common_cells/src/deprecated/generic_LFSR_8bit.sv +$CPROOT/hw/ips/common_cells/src/deprecated/generic_fifo.sv +$CPROOT/hw/ips/common_cells/src/deprecated/prioarbiter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/pulp_sync.sv +$CPROOT/hw/ips/common_cells/src/deprecated/pulp_sync_wedge.sv +$CPROOT/hw/ips/common_cells/src/deprecated/rrarbiter.sv +$CPROOT/hw/ips/common_cells/src/deprecated/clock_divider.sv +$CPROOT/hw/ips/common_cells/src/deprecated/fifo_v2.sv +$CPROOT/hw/ips/common_cells/src/deprecated/fifo_v1.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_ack.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator.sv +$CPROOT/hw/ips/common_cells/src/edge_propagator_rx.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/control_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +$CPROOT/hw/ips/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv +$CPROOT/hw/ips/apb/src/apb_intf.sv +$CPROOT/hw/ips/axi/src/axi_pkg.sv +$CPROOT/hw/ips/axi/src/axi_intf.sv +$CPROOT/hw/ips/axi/src/axi_atop_filter.sv +$CPROOT/hw/ips/axi/src/axi_burst_splitter.sv +$CPROOT/hw/ips/axi/src/axi_bus_compare.sv +$CPROOT/hw/ips/axi/src/axi_cdc_dst.sv +$CPROOT/hw/ips/axi/src/axi_cdc_src.sv +$CPROOT/hw/ips/axi/src/axi_cut.sv +$CPROOT/hw/ips/axi/src/axi_delayer.sv +$CPROOT/hw/ips/axi/src/axi_demux.sv +$CPROOT/hw/ips/axi/src/axi_dw_downsizer.sv +$CPROOT/hw/ips/axi/src/axi_dw_upsizer.sv +$CPROOT/hw/ips/axi/src/axi_fifo.sv +$CPROOT/hw/ips/axi/src/axi_id_remap.sv +$CPROOT/hw/ips/axi/src/axi_id_prepend.sv +$CPROOT/hw/ips/axi/src/axi_isolate.sv +$CPROOT/hw/ips/axi/src/axi_join.sv +$CPROOT/hw/ips/axi/src/axi_lite_demux.sv +$CPROOT/hw/ips/axi/src/axi_lite_dw_converter.sv +$CPROOT/hw/ips/axi/src/axi_lite_from_mem.sv +$CPROOT/hw/ips/axi/src/axi_lite_join.sv +$CPROOT/hw/ips/axi/src/axi_lite_lfsr.sv +$CPROOT/hw/ips/axi/src/axi_lite_mailbox.sv +$CPROOT/hw/ips/axi/src/axi_lite_mux.sv +$CPROOT/hw/ips/axi/src/axi_lite_regs.sv +$CPROOT/hw/ips/axi/src/axi_lite_to_apb.sv +$CPROOT/hw/ips/axi/src/axi_lite_to_axi.sv +$CPROOT/hw/ips/axi/src/axi_modify_address.sv +$CPROOT/hw/ips/axi/src/axi_mux.sv +$CPROOT/hw/ips/axi/src/axi_rw_join.sv +$CPROOT/hw/ips/axi/src/axi_rw_split.sv +$CPROOT/hw/ips/axi/src/axi_serializer.sv +$CPROOT/hw/ips/axi/src/axi_slave_compare.sv +$CPROOT/hw/ips/axi/src/axi_throttle.sv +$CPROOT/hw/ips/axi/src/axi_to_mem.sv +$CPROOT/hw/ips/axi/src/axi_cdc.sv +$CPROOT/hw/ips/axi/src/axi_err_slv.sv +$CPROOT/hw/ips/axi/src/axi_dw_converter.sv +$CPROOT/hw/ips/axi/src/axi_from_mem.sv +$CPROOT/hw/ips/axi/src/axi_id_serialize.sv +$CPROOT/hw/ips/axi/src/axi_lfsr.sv +$CPROOT/hw/ips/axi/src/axi_multicut.sv +$CPROOT/hw/ips/axi/src/axi_to_axi_lite.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_banked.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_interleaved.sv +$CPROOT/hw/ips/axi/src/axi_to_mem_split.sv +$CPROOT/hw/ips/axi/src/axi_iw_converter.sv +$CPROOT/hw/ips/axi/src/axi_lite_xbar.sv +$CPROOT/hw/ips/axi/src/axi_xbar.sv +$CPROOT/hw/ips/axi/src/axi_xp.sv +$CPROOT/hw/ips/fpnew/src/fpnew_pkg.sv +$CPROOT/hw/ips/fpnew/src/fpnew_cast_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_classifier.sv +$CPROOT/hw/ips/fpnew/src/fpnew_divsqrt_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_fma.sv +$CPROOT/hw/ips/fpnew/src/fpnew_fma_multi.sv +$CPROOT/hw/ips/fpnew/src/fpnew_noncomp.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_block.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_fmt_slice.sv +$CPROOT/hw/ips/fpnew/src/fpnew_opgroup_multifmt_slice.sv +$CPROOT/hw/ips/fpnew/src/fpnew_rounding.sv +$CPROOT/hw/ips/fpnew/src/fpnew_top.sv +$CPROOT/hw/ips/axi_node/src/apb_regs_top.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_AR.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_AW.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_BR.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_BW.sv +$CPROOT/hw/ips/axi_node/src/axi_address_decoder_DW.sv +$CPROOT/hw/ips/axi_node/src/axi_AR_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_ArbitrationTree.sv +$CPROOT/hw/ips/axi_node/src/axi_AW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_BR_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_BW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_DW_allocator.sv +$CPROOT/hw/ips/axi_node/src/axi_FanInPrimitive_Req.sv +$CPROOT/hw/ips/axi_node/src/axi_multiplexer.sv +$CPROOT/hw/ips/axi_node/src/axi_node.sv +$CPROOT/hw/ips/axi_node/src/axi_node_intf_wrap.sv +$CPROOT/hw/ips/axi_node/src/axi_node_wrap_with_slices.sv +$CPROOT/hw/ips/axi_node/src/axi_regs_top.sv +$CPROOT/hw/ips/axi_node/src/axi_request_block.sv +$CPROOT/hw/ips/axi_node/src/axi_response_block.sv +$CPROOT/hw/ips/axi_node/src/axi_RR_Flag_Req.sv +$CPROOT/hw/ips/axi_slice/src/axi_single_slice.sv +$CPROOT/hw/ips/axi_slice/src/axi_ar_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_aw_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_b_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_r_buffer.sv +$CPROOT/hw/ips/axi_slice/src/axi_slice.sv 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+$CPROOT/hw/ips/pulp_soc/rtl/udma_subsystem/udma_subsystem.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/fc_demux.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/fc_subsystem.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/cv32e40p_fp_wrapper.sv +$CPROOT/hw/ips/pulp_soc/rtl/fc/event_to_level_int.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_clkdiv.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_soc_ctrl.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/memory_models.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/pulp_interfaces.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/glitch_free_clk_mux.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/tcdm_arbiter_2x1.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/obi_pulp_adapter.sv +$CPROOT/hw/ips/pulp_soc/rtl/components/apb_dummy.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_delay_line_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_delay_line_reg_top.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_delay_line_reg_pkg.sv +$CPROOT/hw/ips/serial_link/src/regs/serial_link_single_channel_delay_line_reg_top.sv +$CPROOT/hw/ips/serial_link/src/serial_link_pkg.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/stream_chopper.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/stream_dechopper.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/channel_despread_sfr.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/channel_spread_sfr.sv +$CPROOT/hw/ips/serial_link/src/channel_allocator/serial_link_channel_allocator.sv +$CPROOT/hw/ips/serial_link/src/serial_link_network.sv +$CPROOT/hw/ips/serial_link/src/serial_link_data_link.sv +$CPROOT/hw/ips/serial_link/src/serial_link_physical.sv +$CPROOT/hw/ips/serial_link/src/serial_link_physical_delay_line.sv +$CPROOT/hw/ips/serial_link/src/serial_link.sv +$CPROOT/hw/ips/serial_link/src/serial_link_wrapper.sv +$CPROOT/hw/ips/serial_link/src/serial_link_occamy_wrapper.sv +$CPROOT/hw/ips/serial_link/src/serial_link_synth_wrapper.sv +$CPROOT/hw/ips/wdt/src/counter_wdt.sv +$CPROOT/hw/ips/wdt/src/ovf_detect.sv +$CPROOT/hw/ips/wdt/src/wdt.sv +$CPROOT/hw/pulp/jtag_tap_top.sv +$CPROOT/hw/pulp/pad_control.sv +$CPROOT/hw/pulp/system_clk_rst_gen.sv +$CPROOT/hw/pulp/cluster_domain.sv +$CPROOT/hw/pulp/soc_domain.sv +$CPROOT/hw/pulp/control_pulp.sv +$CPROOT/hw/pulp/pms_top.sv +$CPROOT/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv +$CPROOT/hw/pulp/pms_top_fpga_behav.sv +$CPROOT/hw/pulp/control_pulp_fpga.sv + From 9bed58951351403edea62593908abdea0359cf76 Mon Sep 17 00:00:00 2001 From: Simone Manoni Date: Thu, 29 Jan 2026 00:53:37 +0100 Subject: [PATCH 5/5] Bump updated and fixed pcf version --- sw/pcf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/pcf b/sw/pcf index 47b5ee8..4fa63fe 160000 --- a/sw/pcf +++ b/sw/pcf @@ -1 +1 @@ -Subproject commit 47b5ee8df4684b1f5a901ce66a2ac18119c89ab1 +Subproject commit 4fa63feda4d8f4ad79d8a29dac2259f057fdeca9