diff --git a/boot.scr b/boot.scr new file mode 100644 index 0000000..ff0857b Binary files /dev/null and b/boot.scr differ diff --git a/fpga/control_pulp-txilzu9eg/constraints/zcu102_peripherals.xdc b/fpga/control_pulp-txilzu9eg/constraints/zcu102_peripherals.xdc index bbaa414..751e9d3 100644 --- a/fpga/control_pulp-txilzu9eg/constraints/zcu102_peripherals.xdc +++ b/fpga/control_pulp-txilzu9eg/constraints/zcu102_peripherals.xdc @@ -171,9 +171,20 @@ set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports pad_pms0_st set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports pad_pms0_strap_3_0] -### JTAG +### JTAG ON PMOD 0 set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i_0] set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i_0] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o_0] set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i_0] set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni_0] + +# BOOTMODE SELECTION FROM SW13 ON ZCU102 +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports pad_bootsel0] +set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS33} [get_ports pad_bootsel1] +set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS33} [get_ports pad_bootsel_valid] +set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS33} [get_ports pad_fc_fetch_en] +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports pad_fc_fetch_en_valid] + +# MAILBOX TEST INTERRUPT SIGNALS ON PMOD 1 +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports pad_doorbell_irq] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports pad_completion_irq] \ No newline at end of file diff --git a/fpga/control_pulp-txilzu9eg/constraints/zcu102_timing.xdc b/fpga/control_pulp-txilzu9eg/constraints/zcu102_timing.xdc index 2b3460f..c900c2b 100644 --- a/fpga/control_pulp-txilzu9eg/constraints/zcu102_timing.xdc +++ b/fpga/control_pulp-txilzu9eg/constraints/zcu102_timing.xdc @@ -1,4 +1,4 @@ -// Timing constraints +# Timing constraints # JTAG create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports jtag_tck_i_0] @@ -6,46 +6,34 @@ set_input_jitter tck 1.000 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_0] # minimize routing delay -set_input_delay -clock tck -clock_fall 5.000 [get_ports jtag_tdi_0] -set_input_delay -clock tck -clock_fall 5.000 [get_ports jtag_tms_0] -set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo_0] set_max_delay -to [get_ports jtag_tdo_o_0] 20.000 set_max_delay -from [get_ports jtag_tms_i_0] 20.000 set_max_delay -from [get_ports jtag_tdi_i_0] 20.000 # JTAG CDC -set_max_delay -datapath_only \ - -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] \ - -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] \ - 20.000 -set_max_delay -datapath_only \ - -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] \ - -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000 -set_max_delay -datapath_only \ - -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] \ - -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # Timers -set_false_path -to [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_cluster_domain/cluster_i/cluster_peripherals_i/cluster_timer_wrap_i/timer_unit_i/s_ref_clk0_reg/D] # Periphs -set_false_path -to [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_spim_gen[*].i_spim/u_spictrl/i_edgeprop/sync_a_reg[*]/D] +set_false_path -to [get_pins {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_spim_gen[*].i_spim/u_spictrl/i_edgeprop/sync_a_reg[*]/D}] # CDC FIFOs in UDMA -set_max_delay 50.000 -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/D] -set_max_delay 50.000 -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*i_sync/*reg*/D] +set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/D] 50.000 +set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/C] 50.000 +set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*i_sync/*reg*/D] 50.000 +set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*reg*/D] 50.000 # reset signal -set_false_path -from [get_pins {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_cluster_domain/cluster_i/rstgen_i/i_rstgen_bypass/synch_regs_q_reg[*]/C}] # Set ASYNC_REG attribute for ff synchronizers to place them closer together and # increase MTBF -set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*] +set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[0]}] +set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[1]}] +set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[2]}] set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*] -set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*] # Create asynchronous clock group between slow-clk and SoC clock. Those clocks # are considered asynchronously and proper synchronization regs are in place @@ -57,3 +45,4 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins control_ ### Create asynchronous clock group between JTAG TCK and SoC clock. set_clock_groups -asynchronous -group [get_clocks tck] -group [get_clocks -of_objects [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_system_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcme4_adv_inst/CLKOUT0]] + diff --git a/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv b/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv index d03c0c5..99121c8 100644 --- a/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv +++ b/fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv @@ -226,6 +226,9 @@ module pad_frame_fpga import control_pulp_pkg::*; ( input logic [1:0] out_cpu_socket_id_i, input logic [3:0] out_cpu_strap_i, + input logic out_doorbell, + input logic out_completion, + // PMB PADS INOUT WIRES inout wire pad_pmb_vr1_pms0_sda, @@ -319,6 +322,20 @@ module pad_frame_fpga import control_pulp_pkg::*; ( inout wire pad_uart1_pms0_rxd, inout wire pad_uart1_pms0_txd, + inout wire pad_bootsel0, + inout wire pad_bootsel1, + inout wire pad_bootsel_valid, + inout wire pad_fc_fetch_en, + inout wire pad_fc_fetch_en_valid, + + inout wire pad_doorbell_irq, + inout wire pad_completion_irq, + + output logic [1:0] bootsel_o, + output logic bootsel_valid_o, + output logic fc_fetch_en_o, + output logic fc_fetch_en_valid_o, + input logic [31:0][5:0] pad_cfg_i ); @@ -414,4 +431,16 @@ module pad_frame_fpga import control_pulp_pkg::*; ( pad_functional_pu padinst_uart1_pms0_rxd( .OEN(~oe_uart1_rxd_i ), .I(out_uart1_rxd_i ), .O(in_uart1_rxd_o ), .PAD(pad_uart1_pms0_rxd ), .PEN(1'b0 )); pad_functional_pu padinst_uart1_pms0_txd( .OEN(~oe_uart1_txd_i ), .I(out_uart1_txd_i ), .O(in_uart1_txd_o ), .PAD(pad_uart1_pms0_txd ), .PEN(1'b0 )); + + // BOOT SELECTION SIGNALS + pad_functional_pd padinst_pad_bootsel0 ( .OEN(1'b1), .I(), .O(bootsel_o[0]), .PAD(pad_bootsel0), .PEN(1'b0 )); + pad_functional_pd padinst_pad_bootsel1 ( .OEN(1'b1), .I(), .O(bootsel_o[1]), .PAD(pad_bootsel1), .PEN(1'b0 )); + pad_functional_pd padinst_pad_bootsel_valid ( .OEN(1'b1), .I(), .O(bootsel_valid_o), .PAD(pad_bootsel_valid), .PEN(1'b0 )); + pad_functional_pd padinst_pad_fc_fetch_en ( .OEN(1'b1), .I(), .O(fc_fetch_en_o), .PAD(pad_fc_fetch_en), .PEN(1'b0 )); + pad_functional_pd padinst_pad_fc_fetch_en_valid ( .OEN(1'b1), .I(), .O(fc_fetch_en_valid_o), .PAD(pad_fc_fetch_en_valid), .PEN(1'b0 )); + + // TEST INTERRUPT SIGNALS + pad_functional_pd padinst_pad_doorbell_irq ( .OEN(1'b0), .I(out_doorbell), .O(), .PAD(pad_doorbell_irq), .PEN(1'b0 )); + pad_functional_pd padinst_pad_completion_irq ( .OEN(1'b0), .I(out_completion), .O(), .PAD(pad_completion_irq), .PEN(1'b0 )); + endmodule diff --git a/fpga/control_pulp-txilzu9eg/rtl/pms_top_fpga.v b/fpga/control_pulp-txilzu9eg/rtl/pms_top_fpga.v index 25d65bb..caff3c5 100644 --- a/fpga/control_pulp-txilzu9eg/rtl/pms_top_fpga.v +++ b/fpga/control_pulp-txilzu9eg/rtl/pms_top_fpga.v @@ -192,8 +192,21 @@ module pms_top_fpga ( // UART PADS INOUT WIRES inout wire pad_uart1_pms0_rxd, - inout wire pad_uart1_pms0_txd + inout wire pad_uart1_pms0_txd, + // BOOT SELECTION INOUT WIRES + inout wire pad_bootsel0, + inout wire pad_bootsel1, + inout wire pad_bootsel_valid, + inout wire pad_fc_fetch_en, + inout wire pad_fc_fetch_en_valid, + + // MAILBOX COMPLETION INTERRUPT OUTPUT WIRE + output wire out_completion_irq, + + // TEST INTERRUPT SIGNALS + inout wire pad_completion_irq, + inout wire pad_doorbell_irq ); // SIM_STDOUT default is: @@ -343,10 +356,10 @@ module pms_top_fpga ( .ref_clk_i ( ref_clk ), .sys_clk_i ( /*sys_clk_i*/ ), // unconnected for FPGA .rst_ni ( pad_reset ), //active_low - .bootsel_valid_i ( 1'b0 ), //0 -> memory-mapped reg - .bootsel_i ( 3'b0 ), //has no effect if bootsel_valid == 0 - .fc_fetch_en_valid_i ( 1'b0 ), //0 -> memory-mapped reg - .fc_fetch_en_i ( 1'b0 ), //has no effect if fetch_en_valid == 0 + // .bootsel_valid_i ( 1'b0 ), //0 -> memory-mapped reg + // .bootsel_i ( 3'b0 ), //has no effect if bootsel_valid == 0 + // .fc_fetch_en_valid_i ( 1'b0 ), //0 -> memory-mapped reg + // .fc_fetch_en_i ( 1'b0 ), //has no effect if fetch_en_valid == 0 .jtag_tdo_o ( jtag_tdo_o ), .jtag_tck_i ( jtag_tck_i ), .jtag_tdi_i ( jtag_tdi_i ), @@ -435,7 +448,15 @@ module pms_top_fpga ( .pad_pms0_strap_0 ( pad_pms0_strap_0 ), .pad_pms0_strap_1 ( pad_pms0_strap_1 ), .pad_pms0_strap_2 ( pad_pms0_strap_2 ), - .pad_pms0_strap_3 ( pad_pms0_strap_3 ) + .pad_pms0_strap_3 ( pad_pms0_strap_3 ), + .pad_bootsel0 ( pad_bootsel0 ), + .pad_bootsel1 ( pad_bootsel1 ), + .pad_bootsel_valid ( pad_bootsel_valid ), + .pad_fc_fetch_en ( pad_fc_fetch_en ), + .pad_fc_fetch_en_valid ( pad_fc_fetch_en_valid ), + .pad_completion_irq ( pad_completion_irq ), + .pad_doorbell_irq ( pad_doorbell_irq ), + .out_completion_irq ( out_completion_irq ) ); diff --git a/fpga/control_pulp-txilzu9eg/tcl/control_pulp_exilzcu102.tcl b/fpga/control_pulp-txilzu9eg/tcl/control_pulp_exilzcu102.tcl index 1d3a626..deadd78 100644 --- a/fpga/control_pulp-txilzu9eg/tcl/control_pulp_exilzcu102.tcl +++ b/fpga/control_pulp-txilzu9eg/tcl/control_pulp_exilzcu102.tcl @@ -82,6 +82,11 @@ connect_bd_intf_net [get_bd_intf_pins i_pms_top_fpga/pl_axi_slv] \ connect_bd_net [get_bd_pins i_pms_top_fpga/soc_clk_o] [get_bd_pins i_zynq_ps/maxihpm0_fpd_aclk] connect_bd_net [get_bd_pins i_pms_top_fpga/soc_clk_o] [get_bd_pins i_zynq_ps/saxihp0_fpd_aclk] + +# connect Completion interrupt from PL to PS +connect_bd_net [get_bd_pins i_pms_top_fpga/out_completion_irq] [get_bd_pins i_zynq_ps/pl_ps_irq0] + + # make pad pins external source tcl/zcu102_pins_bd.tcl diff --git a/fpga/control_pulp-txilzu9eg/tcl/zcu102_pins_bd.tcl b/fpga/control_pulp-txilzu9eg/tcl/zcu102_pins_bd.tcl index 047c8bb..f885385 100644 --- a/fpga/control_pulp-txilzu9eg/tcl/zcu102_pins_bd.tcl +++ b/fpga/control_pulp-txilzu9eg/tcl/zcu102_pins_bd.tcl @@ -84,4 +84,11 @@ make_bd_pins_external \ [get_bd_pins i_pms_top_fpga/jtag_tdi_i] \ [get_bd_pins i_pms_top_fpga/jtag_tdo_o] \ [get_bd_pins i_pms_top_fpga/jtag_tck_i] \ - [get_bd_pins i_pms_top_fpga/jtag_trst_ni] + [get_bd_pins i_pms_top_fpga/jtag_trst_ni] \ + [get_bd_pins i_pms_top_fpga/pad_bootsel0] \ + [get_bd_pins i_pms_top_fpga/pad_bootsel1] \ + [get_bd_pins i_pms_top_fpga/pad_bootsel_valid] \ + [get_bd_pins i_pms_top_fpga/pad_fc_fetch_en] \ + [get_bd_pins i_pms_top_fpga/pad_fc_fetch_en_valid] \ + [get_bd_pins i_pms_top_fpga/pad_doorbell_irq] \ + [get_bd_pins i_pms_top_fpga/pad_completion_irq] diff --git a/fpga/linux/board/xilzcu102/control_pulp.dtsi b/fpga/linux/board/xilzcu102/control_pulp.dtsi index 22caa03..8e41ee5 100644 --- a/fpga/linux/board/xilzcu102/control_pulp.dtsi +++ b/fpga/linux/board/xilzcu102/control_pulp.dtsi @@ -1,36 +1,89 @@ -/* #include "xilinx/zynqmp-zcu102.dts" */ - -/ { - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* contiguous L3 memory for PULP: last 128MiB of DRAM */ - pulp_reserved: pulp_l3_mem@78000000 { - compatible = "pulp,bigpulp"; - no-map; - reg = <0x0 0x78000000 0x0 0x8000000>; +/ { //space after / is needed + firmware{ + scmi { + compatible ="arm,scmi"; + mboxes = <&mhu_bdr 0 &mhu_bdr 0>; + mbox-names = "tx","rx"; + shmem = <&scp_scmi_mem>; + #address-cells = <1>; + #size-cells = <0>; + + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + // scmi_reset: protocol@16 { + // reg = <0x16>; + // #reset-cells = <1>; + // }; + + // scmi_volt: protocol@17 { + // reg = <0x17>; + // #clock-cells = <1>; + // }; + }; }; - /* Ensure serial terminal is enabled at boot. */ - chosen { - bootargs = "earlycon clk_ignore_unused console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait"; - stdout-path = "serial0:115200n8"; - }; +};//root node has to stay here (if amba is included in this node -> syntax error) + +&cpu0 { + clocks = <&scmi_clk 0>; + power-domains = <&scmi_devpd 0>; }; -&amba { - pulp: pulp@a0000000 { - memory-region = <&pulp_reserved>; - compatible = "pulp,bigpulp"; - reg = <0x0 0xa0000000 0x0 0x10000000>; - iommus = <&smmu 0x280>, <&smmu 0x281>, <&smmu 0x282>; /* FIXME: check this */ - }; +&cpu1 { + clocks = <&scmi_clk 0>; + power-domains = <&scmi_devpd 0>; }; -/* FIXME: test why this hangs */ -/*&smmu { - status = "okay"; -};*/ +&cpu2 { + clocks = <&scmi_clk 0>; + power-domains = <&scmi_devpd 0>; +}; + +&cpu3 { + clocks = <&scmi_clk 0>; + power-domains = <&scmi_devpd 0>; +}; + +&amba{ + scmi_sram: sram@A6000000{ + compatible = "mmio-sram"; + reg = <0x0 0xA6000000 0x0 0xA0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xA6000000 0xA0>; + + scp_scmi_mem: scp-shmem@0{ + compatible = "arm,scmi-shmem"; + reg = <0x0 0xA0>; + }; + }; + + mhu_bdr: mhu@A60000A0{ + #mbox-cells = <1>; + compatible = "arm,mhu", "arm,primecell"; + clock-names = "clk_apb"; + reg = <0x0 0xA60000A0 0x0 0x18>; + interrupt-parent = <&gic>; + interrupts = <0 89 1>, + <0 91 1>, + <0 92 1>; + interrupt-names = "mhu_bdr"; + clocks = <&zynqmp_clk 31>; + }; +}; \ No newline at end of file diff --git a/fpga/linux/configs/har_exilzcu102_defconfig b/fpga/linux/configs/har_exilzcu102_defconfig index b81edb9..a4315ee 100644 --- a/fpga/linux/configs/har_exilzcu102_defconfig +++ b/fpga/linux/configs/har_exilzcu102_defconfig @@ -10,15 +10,17 @@ BR2_TOOLCHAIN_EXTERNAL_CUSTOM_GLIBC=y BR2_TOOLCHAIN_EXTERNAL_CXX=y BR2_TARGET_GENERIC_HOSTNAME="zynqmp" BR2_TARGET_GENERIC_ISSUE="Welcome to ZynqMP" -BR2_TARGET_GENERIC_ROOT_PASSWD="change-this-root-pw" +BR2_TARGET_GENERIC_ROOT_PASSWD="pms-root" BR2_SYSTEM_BIN_SH_BASH=y BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_CPULP_PATH)/board/common/overlay/" BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_CPULP_PATH)/board/common/post_build.sh $(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/post_build.sh" BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/post_image.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_GIT=y -BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git" -BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2019.2.01" +# BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git" +# BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2019.2.01" +BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Antoniodv/linux-xlnx.git" +BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="linux-scmi" BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/kernel_config" BR2_LINUX_KERNEL_DTS_SUPPORT=y @@ -42,6 +44,6 @@ BR2_PACKAGE_HOST_DOSFSTOOLS=y BR2_PACKAGE_HOST_GENIMAGE=y BR2_PACKAGE_HOST_MTOOLS=y BR2_PACKAGE_PMSCTL=y -BR2_PACKAGE_PMSRST=y +BR2_PACKAGE_PMSRST BR2_PACKAGE_HOST_ZYNQ_MKBOOTIMAGE=y BR2_CPULP_BITSTREAM="$(BR2_EXTERNAL_CPULP_PATH)/../output/pms.bit" diff --git a/fpga/linux/mhu_test/.gitignore b/fpga/linux/mhu_test/.gitignore new file mode 100644 index 0000000..c465a1b --- /dev/null +++ b/fpga/linux/mhu_test/.gitignore @@ -0,0 +1 @@ +pmsctl diff --git a/fpga/linux/mhu_test/Makefile b/fpga/linux/mhu_test/Makefile new file mode 100644 index 0000000..4fbef94 --- /dev/null +++ b/fpga/linux/mhu_test/Makefile @@ -0,0 +1,35 @@ +# Copyright 2021 ETH Zurich +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 +# Author: Robert Balas (balasr@iis.ee.ethz.ch) + +CXX=aarch64-none-linux-gnu-g++ +C=aarch64-none-linux-gnu-gcc + +all: mhu_test setspeed + +mhu_test: mhu_test.cc $(wildcard physmem/inc/*) + $(CXX) -std=c++11 -Wall -I. $(CXXFLAGS) $(CPPFLAGS) $< -o $@; + +setspeed: setspeed.c $(wildcard physmem/inc/*) + $(C) -std=c11 -Wall -I. $(CFLAGS) $(CPPFLAGS) $< -o $@; + + + +.PHONY: clean + +clean: + $(RM) setspeed + $(RM) mhu_test diff --git a/fpga/linux/mhu_test/mhu_test.cc b/fpga/linux/mhu_test/mhu_test.cc new file mode 100644 index 0000000..bab6e53 --- /dev/null +++ b/fpga/linux/mhu_test/mhu_test.cc @@ -0,0 +1,88 @@ +// Copyright 2023 ETH Zurich and University of Bologna +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Robert Balas +// Alessandro Ottaviano +/*Basic test to write to a specific address in the scmi mailbox from ARM cores in Zynq Soc*/ + + +#include +#include +#include +#include +#include +#include +#include "physmem/inc/physmem.hpp" + +void printUsage(const char* programName) { + std::cout << "Usage: " << programName << " \n"; + std::cout << " : Offset from base address 0xA6000000 (in hex without 0x prefix)\n"; + std::cout << " : Value to write to the address (in hex without 0x prefix)\n"; + std::cout << "Example: " << programName << " 20 00000001\n"; +} + +bool parseHexValue(const std::string& str, std::uint32_t& value) { + std::istringstream iss(str); + iss >> std::hex >> value; + return !iss.fail(); +} + +int main(int argc, char* argv[]) { + std::cout << "Application started...\n"; + + // Check command line arguments + if (argc != 3) { + std::cout << "Error: Invalid number of arguments.\n"; + printUsage(argv[0]); + return 1; + } + + // Parse offset address and payload from arguments + std::uint32_t offsetAddress; + std::uint32_t payload; + + if (!parseHexValue(argv[1], offsetAddress)) { + std::cout << "Error: Invalid address offset format. Use hex format without 0x prefix.\n"; + printUsage(argv[0]); + return 1; + } + + if (!parseHexValue(argv[2], payload)) { + std::cout << "Error: Invalid message value format. Use hex format without 0x prefix.\n"; + printUsage(argv[0]); + return 1; + } + + // Base address of the SCMI mailbox + const std::uint32_t baseAddress = 0xA6000000; + + // Map the physical memory + PhysMem scmi_mailbox(baseAddress, 0x1FFFFFFF); + + // Calculate the absolute address + std::uint32_t absoluteAddress = baseAddress + offsetAddress; + + std::cout << "Writing to address: 0x" << std::hex << absoluteAddress + << " (Base + 0x" << offsetAddress << ")\n"; + std::cout << "Writing value: 0x" << std::hex << payload << "\n"; + + // Write the payload to the specified address + scmi_mailbox.write_u32(absoluteAddress, payload); + + std::cout << "Write operation completed.\n"; + + return 0; +} \ No newline at end of file diff --git a/fpga/linux/mhu_test/physmem/.gitignore b/fpga/linux/mhu_test/physmem/.gitignore new file mode 100644 index 0000000..d232807 --- /dev/null +++ b/fpga/linux/mhu_test/physmem/.gitignore @@ -0,0 +1,3 @@ +/example +example.cc +tmp_stim \ No newline at end of file diff --git a/fpga/linux/mhu_test/physmem/README.md b/fpga/linux/mhu_test/physmem/README.md new file mode 100644 index 0000000..e4ec83d --- /dev/null +++ b/fpga/linux/mhu_test/physmem/README.md @@ -0,0 +1,28 @@ +# Physical Memory Accessing Library (Header-Only) for Linux + +This header-only library provides a simple means to access physical memory on +Linux, without having to `mmap` with the correct flags, dealing with `volatile` +pointers, and the like. + +The API is [documented in the header file](./inc/physmem.hpp) in Doxygen syntax. + +## Usage + +Minimal C++ example application: +```cpp +#include "physmem.hpp" + +int main() { + PhysMem mem(0x10002000, 0x1000); // map 4 KiB starting at 0x10002000 + mem.write_u32(0x10002020, 0x37703770); // write to 0x10002020 + return 0; +} +``` +Compile with at least C++11 enabled and add the `inc/` directory in this folder +to the include paths. + +The [`Makefile`](./Makefile) and [`example.cc`](./example.cc) in this directory +contain a more complete example. + +When cross-compiling, ensure that the `CXX` environment variable is set to the +C++ compiler for the target. diff --git a/fpga/linux/mhu_test/physmem/inc/aixlog.hpp b/fpga/linux/mhu_test/physmem/inc/aixlog.hpp new file mode 100644 index 0000000..491f33c --- /dev/null +++ b/fpga/linux/mhu_test/physmem/inc/aixlog.hpp @@ -0,0 +1,1233 @@ +/*** + __ __ _ _ __ __ ___ + / _\ ( )( \/ )( ) / \ / __) + / \ )( ) ( / (_/\( O )( (_ \ + \_/\_/(__)(_/\_)\____/ \__/ \___/ + version 1.4.0 + https://github.com/badaix/aixlog + + This file is part of aixlog + Copyright (C) 2017-2020 Johannes Pohl + + This software may be modified and distributed under the terms + of the MIT license. See the LICENSE file for details. +***/ + +/// inspired by "eater": +/// https://stackoverflow.com/questions/2638654/redirect-c-stdclog-to-syslog-on-unix + +#ifndef AIX_LOG_HPP +#define AIX_LOG_HPP + +#ifndef _WIN32 +#define HAS_SYSLOG_ 1 +#endif + +#ifdef __APPLE__ +#ifdef __MAC_OS_X_VERSION_MAX_ALLOWED +#if __MAC_OS_X_VERSION_MAX_ALLOWED >= 1012 +#define HAS_APPLE_UNIFIED_LOG_ 1 +#endif +#endif +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __ANDROID__ +#include +#endif + +#ifdef _WIN32 +#include +// ERROR macro is defined in Windows header +// To avoid conflict between these macro and declaration of ERROR / DEBUG in SEVERITY enum +// We save macro and undef it +#pragma push_macro("ERROR") +#pragma push_macro("DEBUG") +#undef ERROR +#undef DEBUG +#endif + +#ifdef HAS_APPLE_UNIFIED_LOG_ +#include +#endif + +#ifdef HAS_SYSLOG_ +#include +#endif + +#ifdef __ANDROID__ +// fix for bug "Android NDK __func__ definition is inconsistent with glibc and C++99" +// https://bugs.chromium.org/p/chromium/issues/detail?id=631489 +#ifdef __GNUC__ +#define AIXLOG_INTERNAL__FUNC __FUNCTION__ +#else +#define AIXLOG_INTERNAL__FUNC __func__ +#endif +#else +#define AIXLOG_INTERNAL__FUNC __func__ +#endif + +/// Internal helper macros (exposed, but shouldn't be used directly) +#define AIXLOG_INTERNAL__LOG_SEVERITY(SEVERITY_) std::clog << static_cast(SEVERITY_) << TAG() +#define AIXLOG_INTERNAL__LOG_SEVERITY_TAG(SEVERITY_, TAG_) std::clog << static_cast(SEVERITY_) << TAG(TAG_) + +#define AIXLOG_INTERNAL__ONE_COLOR(FG_) AixLog::Color::FG_ +#define AIXLOG_INTERNAL__TWO_COLOR(FG_, BG_) AixLog::TextColor(AixLog::Color::FG_, AixLog::Color::BG_) + +// https://stackoverflow.com/questions/3046889/optional-parameters-with-c-macros +#define AIXLOG_INTERNAL__VAR_PARM(PARAM1_, PARAM2_, FUNC_, ...) FUNC_ +#define AIXLOG_INTERNAL__LOG_MACRO_CHOOSER(...) AIXLOG_INTERNAL__VAR_PARM(__VA_ARGS__, AIXLOG_INTERNAL__LOG_SEVERITY_TAG, AIXLOG_INTERNAL__LOG_SEVERITY, ) +#define AIXLOG_INTERNAL__COLOR_MACRO_CHOOSER(...) AIXLOG_INTERNAL__VAR_PARM(__VA_ARGS__, AIXLOG_INTERNAL__TWO_COLOR, AIXLOG_INTERNAL__ONE_COLOR, ) + +/// External logger macros +// usage: LOG(SEVERITY) or LOG(SEVERITY, TAG) +// e.g.: LOG(NOTICE) or LOG(NOTICE, "my tag") +#ifndef WIN32 +#define LOG(...) AIXLOG_INTERNAL__LOG_MACRO_CHOOSER(__VA_ARGS__)(__VA_ARGS__) << TIMESTAMP << FUNC +#endif + +// usage: COLOR(TEXT_COLOR, BACKGROUND_COLOR) or COLOR(TEXT_COLOR) +// e.g.: COLOR(yellow, blue) or COLOR(red) +#define COLOR(...) AIXLOG_INTERNAL__COLOR_MACRO_CHOOSER(__VA_ARGS__)(__VA_ARGS__) + +#define FUNC AixLog::Function(AIXLOG_INTERNAL__FUNC, __FILE__, __LINE__) +#define TAG AixLog::Tag +#define COND AixLog::Conditional +#define TIMESTAMP AixLog::Timestamp(std::chrono::system_clock::now()) + + +// stijnvdb: sorry! :) LOG(SEV, "tag") was not working for Windows and I couldn't figure out how to fix it for windows without potentially breaking everything +// else... +// https://stackoverflow.com/questions/3046889/optional-parameters-with-c-macros (Jason Deng) +#ifdef WIN32 +#define LOG_2(severity, tag) AIXLOG_INTERNAL__LOG_SEVERITY_TAG(severity, tag) +#define LOG_1(severity) AIXLOG_INTERNAL__LOG_SEVERITY(severity) +#define LOG_0() LOG_1(0) + +#define FUNC_CHOOSER(_f1, _f2, _f3, ...) _f3 +#define FUNC_RECOMPOSER(argsWithParentheses) FUNC_CHOOSER argsWithParentheses +#define CHOOSE_FROM_ARG_COUNT(...) FUNC_RECOMPOSER((__VA_ARGS__, LOG_2, LOG_1, FUNC_, ...)) +#define MACRO_CHOOSER(...) CHOOSE_FROM_ARG_COUNT(__VA_ARGS__()) +#define LOG(...) MACRO_CHOOSER(__VA_ARGS__)(__VA_ARGS__) << TIMESTAMP << FUNC +#endif + +/** + * @brief + * Severity of the log message + */ +enum SEVERITY +{ + TRACE = 0, + DEBUG = 1, + INFO = 2, + NOTICE = 3, + WARNING = 4, + ERROR = 5, + FATAL = 6 +}; + +namespace AixLog +{ + +/** + * @brief + * Severity of the log message + * + * Mandatory parameter for the LOG macro + */ +enum class Severity : std::int8_t +{ + // Mapping table from AixLog to other loggers. Boost is just for information. + // https://chromium.googlesource.com/chromium/mini_chromium/+/master/base/logging.cc + // + // Aixlog Boost Syslog Android macOS EventLog Syslog Desc + // + // trace trace DEBUG VERBOSE DEBUG INFORMATION + // debug debug DEBUG DEBUG DEBUG INFORMATION debug-level message + // info info INFO INFO INFO SUCCESS informational message + // notice NOTICE INFO INFO SUCCESS normal, but significant, condition + // warning warning WARNING WARN DEFAULT WARNING warning conditions + // error error ERROR ERROR ERROR ERROR error conditions + // fatal fatal CRIT FATAL FAULT ERROR critical conditions + // ALERT action must be taken immediately + // EMERG system is unusable + + trace = SEVERITY::TRACE, + debug = SEVERITY::DEBUG, + info = SEVERITY::INFO, + notice = SEVERITY::NOTICE, + warning = SEVERITY::WARNING, + error = SEVERITY::ERROR, + fatal = SEVERITY::FATAL +}; + + +static Severity to_severity(std::string severity, Severity def = Severity::info) +{ + std::transform(severity.begin(), severity.end(), severity.begin(), [](unsigned char c) { return std::tolower(c); }); + if (severity == "trace") + return Severity::trace; + else if (severity == "debug") + return Severity::debug; + else if (severity == "info") + return Severity::info; + else if (severity == "notice") + return Severity::notice; + else if (severity == "warning") + return Severity::warning; + else if (severity == "error") + return Severity::error; + else if (severity == "fatal") + return Severity::fatal; + else + return def; +} + + +static std::string to_string(Severity logSeverity) +{ + switch (logSeverity) + { + case Severity::trace: + return "Trace"; + case Severity::debug: + return "Debug"; + case Severity::info: + return "Info"; + case Severity::notice: + return "Notice"; + case Severity::warning: + return "Warn"; + case Severity::error: + return "Error"; + case Severity::fatal: + return "Fatal"; + default: + std::stringstream ss; + ss << static_cast(logSeverity); + return ss.str(); + } +} + +/** + * @brief + * Color constants used for console colors + */ +enum class Color +{ + none = 0, + NONE = 0, + black = 1, + BLACK = 1, + red = 2, + RED = 2, + green = 3, + GREEN = 3, + yellow = 4, + YELLOW = 4, + blue = 5, + BLUE = 5, + magenta = 6, + MAGENTA = 6, + cyan = 7, + CYAN = 7, + white = 8, + WHITE = 8 +}; + +/** + * @brief + * Encapsulation of foreground and background color + */ +struct TextColor +{ + TextColor(Color foreground = Color::none, Color background = Color::none) : foreground(foreground), background(background) + { + } + + Color foreground; + Color background; +}; + +/** + * @brief + * For Conditional logging of a log line + */ +struct Conditional +{ + Conditional() : Conditional(true) + { + } + + Conditional(bool value) : is_true_(value) + { + } + + void set(bool value) + { + is_true_ = value; + } + + bool is_true() const + { + return is_true_; + } + +private: + bool is_true_; +}; + +/** + * @brief + * Timestamp of a log line + * + * to_string will convert the time stamp into a string, using the strftime syntax + */ +struct Timestamp +{ + using time_point_sys_clock = std::chrono::time_point; + + Timestamp(std::nullptr_t) : is_null_(true) + { + } + + Timestamp() : Timestamp(nullptr) + { + } + + Timestamp(const time_point_sys_clock& time_point) : time_point(time_point), is_null_(false) + { + } + + Timestamp(time_point_sys_clock&& time_point) : time_point(std::move(time_point)), is_null_(false) + { + } + + virtual ~Timestamp() = default; + + explicit operator bool() const + { + return !is_null_; + } + + /// strftime format + proprietary "#ms" for milliseconds + std::string to_string(const std::string& format = "%Y-%m-%d %H-%M-%S.#ms") const + { + std::time_t now_c = std::chrono::system_clock::to_time_t(time_point); + struct ::tm now_tm = localtime_xp(now_c); + char buffer[256]; + strftime(buffer, sizeof buffer, format.c_str(), &now_tm); + std::string result(buffer); + size_t pos = result.find("#ms"); + if (pos != std::string::npos) + { + int ms_part = std::chrono::time_point_cast(time_point).time_since_epoch().count() % 1000; + char ms_str[4]; + if (snprintf(ms_str, 4, "%03d", ms_part) >= 0) + result.replace(pos, 3, ms_str); + } + return result; + } + + time_point_sys_clock time_point; + +private: + bool is_null_; + + inline std::tm localtime_xp(std::time_t timer) const + { + std::tm bt; +#if defined(__unix__) + localtime_r(&timer, &bt); +#elif defined(_MSC_VER) + localtime_s(&bt, &timer); +#else + static std::mutex mtx; + std::lock_guard lock(mtx); + bt = *std::localtime(&timer); +#endif + return bt; + } +}; + +/** + * @brief + * Tag (string) for log line + */ +struct Tag +{ + Tag(std::nullptr_t) : text(""), is_null_(true) + { + } + + Tag() : Tag(nullptr) + { + } + + Tag(const char* text) : text(text), is_null_(false) + { + } + + Tag(const std::string& text) : text(text), is_null_(false) + { + } + + Tag(std::string&& text) : text(std::move(text)), is_null_(false) + { + } + + virtual ~Tag() = default; + + explicit operator bool() const + { + return !is_null_; + } + + bool operator<(const Tag& other) const + { + return (text < other.text); + } + + std::string text; + +private: + bool is_null_; +}; + +/** + * @brief + * Capture function, file and line number of the log line + */ +struct Function +{ + Function(const std::string& name, const std::string& file, size_t line) : name(name), file(file), line(line), is_null_(false) + { + } + + Function(std::string&& name, std::string&& file, size_t line) : name(std::move(name)), file(std::move(file)), line(line), is_null_(false) + { + } + + Function(std::nullptr_t) : name(""), file(""), line(0), is_null_(true) + { + } + + Function() : Function(nullptr) + { + } + + virtual ~Function() = default; + + explicit operator bool() const + { + return !is_null_; + } + + std::string name; + std::string file; + size_t line; + +private: + bool is_null_; +}; + +/** + * @brief + * Collection of a log line's meta data + */ +struct Metadata +{ + Metadata() : severity(Severity::trace), tag(nullptr), function(nullptr), timestamp(nullptr) + { + } + + Severity severity; + Tag tag; + Function function; + Timestamp timestamp; +}; + + +class Filter +{ +public: + Filter() + { + } + + Filter(Severity severity) + { + add_filter(severity); + } + + bool match(const Metadata& metadata) const + { + if (tag_filter_.empty()) + return true; + + auto iter = tag_filter_.find(metadata.tag); + if (iter != tag_filter_.end()) + return (metadata.severity >= iter->second); + + iter = tag_filter_.find("*"); + if (iter != tag_filter_.end()) + return (metadata.severity >= iter->second); + + return false; + } + + void add_filter(const Tag& tag, Severity severity) + { + tag_filter_[tag] = severity; + } + + void add_filter(Severity severity) + { + tag_filter_["*"] = severity; + } + + void add_filter(const std::string& filter) + { + auto pos = filter.find(":"); + if (pos != std::string::npos) + add_filter(filter.substr(0, pos), to_severity(filter.substr(pos + 1))); + else + add_filter(to_severity(filter)); + } + +private: + std::map tag_filter_; +}; + + +/** + * @brief + * Abstract log sink + * + * All log sinks must inherit from this Sink + */ +struct Sink +{ + Sink(const Filter& filter) : filter(filter) + { + } + + virtual ~Sink() = default; + + virtual void log(const Metadata& metadata, const std::string& message) = 0; + + Filter filter; +}; + +/// ostream operators << for the meta data structs +static std::ostream& operator<<(std::ostream& os, const Severity& log_severity); +static std::ostream& operator<<(std::ostream& os, const Timestamp& timestamp); +static std::ostream& operator<<(std::ostream& os, const Tag& tag); +static std::ostream& operator<<(std::ostream& os, const Function& function); +static std::ostream& operator<<(std::ostream& os, const Conditional& conditional); +static std::ostream& operator<<(std::ostream& os, const Color& color); +static std::ostream& operator<<(std::ostream& os, const TextColor& text_color); + +using log_sink_ptr = std::shared_ptr; + +/** + * @brief + * Main Logger class with "Log::init" + * + * Don't use it directly, but call once "Log::init" with your log sink instances. + * The Log class will simply redirect clog to itself (as a streambuf) and + * forward whatever went to clog to the log sink instances + */ +class Log : public std::basic_streambuf> +{ +public: + static Log& instance() + { + static Log instance_; + return instance_; + } + + /// Without "init" every LOG(X) will simply go to clog + static void init(const std::vector log_sinks = {}) + { + Log::instance().log_sinks_.clear(); + + for (const auto& sink : log_sinks) + Log::instance().add_logsink(sink); + } + + template + static std::shared_ptr init(Ts&&... params) + { + std::shared_ptr sink = Log::instance().add_logsink(std::forward(params)...); + init({sink}); + return sink; + } + + template + std::shared_ptr add_logsink(Ts&&... params) + { + std::lock_guard lock(mutex_); + static_assert(std::is_base_of::type>::value, "type T must be a Sink"); + std::shared_ptr sink = std::make_shared(std::forward(params)...); + log_sinks_.push_back(sink); + return sink; + } + + void add_logsink(const log_sink_ptr& sink) + { + std::lock_guard lock(mutex_); + log_sinks_.push_back(sink); + } + + void remove_logsink(const log_sink_ptr& sink) + { + std::lock_guard lock(mutex_); + log_sinks_.erase(std::remove(log_sinks_.begin(), log_sinks_.end(), sink), log_sinks_.end()); + } + +protected: + Log() noexcept : last_buffer_(nullptr) + { + std::clog.rdbuf(this); + std::clog << Severity() << Tag() << Function() << Conditional() << AixLog::Color::NONE << std::flush; + } + + virtual ~Log() + { + sync(); + } + + int sync() override + { + std::lock_guard lock(mutex_); + if (!get_stream().str().empty()) + { + if (conditional_.is_true()) + { + for (const auto& sink : log_sinks_) + { + if (sink->filter.match(metadata_)) + sink->log(metadata_, get_stream().str()); + } + } + get_stream().str(""); + get_stream().clear(); + } + + return 0; + } + + int overflow(int c) override + { + std::lock_guard lock(mutex_); + if (c != EOF) + { + if (c == '\n') + sync(); + else + get_stream() << static_cast(c); + } + else + { + sync(); + } + return c; + } + +private: + friend std::ostream& operator<<(std::ostream& os, const Severity& log_severity); + friend std::ostream& operator<<(std::ostream& os, const Timestamp& timestamp); + friend std::ostream& operator<<(std::ostream& os, const Tag& tag); + friend std::ostream& operator<<(std::ostream& os, const Function& function); + friend std::ostream& operator<<(std::ostream& os, const Conditional& conditional); + + std::stringstream& get_stream() + { + auto id = std::this_thread::get_id(); + if ((last_buffer_ == nullptr) || (last_id_ != id)) + { + last_id_ = id; + last_buffer_ = &(buffer_[id]); + } + return *last_buffer_; + } + + std::map buffer_; + std::thread::id last_id_; + std::stringstream* last_buffer_ = nullptr; + Metadata metadata_; + Conditional conditional_; + std::vector log_sinks_; + std::recursive_mutex mutex_; +}; + +/** + * @brief + * Null log sink + * + * Discards all log messages + */ +struct SinkNull : public Sink +{ + SinkNull() : Sink(Filter()) + { + } + + void log(const Metadata& /*metadata*/, const std::string& /*message*/) override + { + } +}; + + +/** + * @brief + * Abstract log sink with support for formatting log message + * + * "format" in the c'tor defines a log pattern. + * For every log message, these placeholders will be substituded: + * - strftime syntax is used to format the logging time stamp (%Y, %m, %d, ...) + * - #ms: milliseconds part of the logging time stamp with leading zeros + * - #severity: log severity + * - #tag_func: the log tag. If empty, the function + * - #tag: the log tag + * - #function: the function + * - #message: the log message + */ +struct SinkFormat : public Sink +{ + SinkFormat(const Filter& filter, const std::string& format) : Sink(filter), format_(format) + { + } + + virtual void set_format(const std::string& format) + { + format_ = format; + } + + void log(const Metadata& metadata, const std::string& message) override = 0; + +protected: + virtual void do_log(std::ostream& stream, const Metadata& metadata, const std::string& message) const + { + std::string result = format_; + if (metadata.timestamp) + result = metadata.timestamp.to_string(result); + + size_t pos = result.find("#severity"); + if (pos != std::string::npos) + result.replace(pos, 9, to_string(metadata.severity)); + + pos = result.find("#color_severity"); + if (pos != std::string::npos) + { + std::stringstream ss; + ss << TextColor(Color::RED) << to_string(metadata.severity) << TextColor(Color::NONE); + result.replace(pos, 15, ss.str()); + } + + pos = result.find("#tag_func"); + if (pos != std::string::npos) + result.replace(pos, 9, metadata.tag ? metadata.tag.text : (metadata.function ? metadata.function.name : "log")); + + pos = result.find("#tag"); + if (pos != std::string::npos) + result.replace(pos, 4, metadata.tag ? metadata.tag.text : ""); + + pos = result.find("#function"); + if (pos != std::string::npos) + result.replace(pos, 9, metadata.function ? metadata.function.name : ""); + + pos = result.find("#message"); + if (pos != std::string::npos) + { + result.replace(pos, 8, message); + stream << result << std::endl; + } + else + { + if (result.empty() || (result.back() == ' ')) + stream << result << message << std::endl; + else + stream << result << " " << message << std::endl; + } + } + + std::string format_; +}; + +/** + * @brief + * Formatted logging to cout + */ +struct SinkCout : public SinkFormat +{ + SinkCout(const Filter& filter, const std::string& format = "%Y-%m-%d %H-%M-%S.#ms [#severity] (#tag_func)") : SinkFormat(filter, format) + { + } + + void log(const Metadata& metadata, const std::string& message) override + { + do_log(std::cout, metadata, message); + } +}; + +/** + * @brief + * Formatted logging to cerr + */ +struct SinkCerr : public SinkFormat +{ + SinkCerr(const Filter& filter, const std::string& format = "%Y-%m-%d %H-%M-%S.#ms [#severity] (#tag_func)") : SinkFormat(filter, format) + { + } + + void log(const Metadata& metadata, const std::string& message) override + { + do_log(std::cerr, metadata, message); + } +}; + +/** + * @brief + * Formatted logging to file + */ +struct SinkFile : public SinkFormat +{ + SinkFile(const Filter& filter, const std::string& filename, const std::string& format = "%Y-%m-%d %H-%M-%S.#ms [#severity] (#tag_func)") + : SinkFormat(filter, format) + { + ofs.open(filename.c_str(), std::ofstream::out | std::ofstream::trunc); + } + + ~SinkFile() override + { + ofs.close(); + } + + void log(const Metadata& metadata, const std::string& message) override + { + do_log(ofs, metadata, message); + } + +protected: + mutable std::ofstream ofs; +}; + +#ifdef _WIN32 +/** + * @brief + * Windows: Logging to OutputDebugString + * + * Not tested due to unavailability of Windows + */ +struct SinkOutputDebugString : public Sink +{ + SinkOutputDebugString(const Filter& filter) : Sink(filter) + { + } + + void log(const Metadata& metadata, const std::string& message) override + { + std::wstring wide = std::wstring(message.begin(), message.end()); + OutputDebugString(wide.c_str()); + } +}; +#endif + +#ifdef HAS_APPLE_UNIFIED_LOG_ +/** + * @brief + * macOS: Logging to Apples system logger + */ +struct SinkUnifiedLogging : public Sink +{ + SinkUnifiedLogging(const Filter& filter) : Sink(filter) + { + } + + os_log_type_t get_os_log_type(Severity severity) const + { + // https://developer.apple.com/documentation/os/os_log_type_t?language=objc + switch (severity) + { + case Severity::trace: + case Severity::debug: + return OS_LOG_TYPE_DEBUG; + case Severity::info: + case Severity::notice: + return OS_LOG_TYPE_INFO; + case Severity::warning: + return OS_LOG_TYPE_DEFAULT; + case Severity::error: + return OS_LOG_TYPE_ERROR; + case Severity::fatal: + return OS_LOG_TYPE_FAULT; + default: + return OS_LOG_TYPE_DEFAULT; + } + } + + void log(const Metadata& metadata, const std::string& message) override + { + os_log_with_type(OS_LOG_DEFAULT, get_os_log_type(metadata.severity), "%{public}s", message.c_str()); + } +}; +#endif + +#ifdef HAS_SYSLOG_ +/** + * @brief + * UNIX: Logging to syslog + */ +struct SinkSyslog : public Sink +{ + SinkSyslog(const char* ident, const Filter& filter) : Sink(filter) + { + openlog(ident, LOG_PID, LOG_USER); + } + + ~SinkSyslog() override + { + closelog(); + } + + int get_syslog_priority(Severity severity) const + { + // http://unix.superglobalmegacorp.com/Net2/newsrc/sys/syslog.h.html + switch (severity) + { + case Severity::trace: + case Severity::debug: + return LOG_DEBUG; + case Severity::info: + return LOG_INFO; + case Severity::notice: + return LOG_NOTICE; + case Severity::warning: + return LOG_WARNING; + case Severity::error: + return LOG_ERR; + case Severity::fatal: + return LOG_CRIT; + default: + return LOG_INFO; + } + } + + void log(const Metadata& metadata, const std::string& message) override + { + syslog(get_syslog_priority(metadata.severity), "%s", message.c_str()); + } +}; +#endif + +#ifdef __ANDROID__ +/** + * @brief + * Android: Logging to android log + * + * Use logcat to read the logs + */ +struct SinkAndroid : public Sink +{ + SinkAndroid(const std::string& ident, const Filter& filter) : Sink(filter), ident_(ident) + { + } + + android_LogPriority get_android_prio(Severity severity) const + { + // https://developer.android.com/ndk/reference/log_8h.html + switch (severity) + { + case Severity::trace: + return ANDROID_LOG_VERBOSE; + case Severity::debug: + return ANDROID_LOG_DEBUG; + case Severity::info: + case Severity::notice: + return ANDROID_LOG_INFO; + case Severity::warning: + return ANDROID_LOG_WARN; + case Severity::error: + return ANDROID_LOG_ERROR; + case Severity::fatal: + return ANDROID_LOG_FATAL; + default: + return ANDROID_LOG_UNKNOWN; + } + } + + void log(const Metadata& metadata, const std::string& message) override + { + std::string tag = metadata.tag ? metadata.tag.text : (metadata.function ? metadata.function.name : ""); + std::string log_tag; + if (!ident_.empty() && !tag.empty()) + log_tag = ident_ + "." + tag; + else if (!ident_.empty()) + log_tag = ident_; + else if (!tag.empty()) + log_tag = tag; + else + log_tag = "log"; + + __android_log_write(get_android_prio(metadata.severity), log_tag.c_str(), message.c_str()); + } + +protected: + std::string ident_; +}; +#endif + +#ifdef _WIN32 +/** + * @brief + * Windows: Logging to event logger + * + * Not tested due to unavailability of Windows + */ +struct SinkEventLog : public Sink +{ + SinkEventLog(const std::string& ident, const Filter& filter) : Sink(filter) + { + std::wstring wide = std::wstring(ident.begin(), ident.end()); // stijnvdb: RegisterEventSource expands to RegisterEventSourceW which takes wchar_t + event_log = RegisterEventSource(NULL, wide.c_str()); + } + + WORD get_type(Severity severity) const + { + // https://msdn.microsoft.com/de-de/library/windows/desktop/aa363679(v=vs.85).aspx + switch (severity) + { + case Severity::trace: + case Severity::debug: + return EVENTLOG_INFORMATION_TYPE; + case Severity::info: + case Severity::notice: + return EVENTLOG_SUCCESS; + case Severity::warning: + return EVENTLOG_WARNING_TYPE; + case Severity::error: + case Severity::fatal: + return EVENTLOG_ERROR_TYPE; + default: + return EVENTLOG_INFORMATION_TYPE; + } + } + + void log(const Metadata& metadata, const std::string& message) override + { + std::wstring wide = std::wstring(message.begin(), message.end()); + // We need this temp variable because we cannot take address of rValue + const wchar_t* c_str = wide.c_str(); + + ReportEvent(event_log, get_type(metadata.severity), 0, 0, NULL, 1, 0, &c_str, NULL); + } + +protected: + HANDLE event_log; +}; +#endif + +/** + * @brief + * Log to the system's native sys logger + * + * - Android: Android log + * - macOS: unified log + * - Windows: event log + * - Unix: syslog + */ +struct SinkNative : public Sink +{ + SinkNative(const std::string& ident, const Filter& filter) : Sink(filter), log_sink_(nullptr), ident_(ident) + { +#ifdef __ANDROID__ + log_sink_ = std::make_shared(ident_, filter); +#elif HAS_APPLE_UNIFIED_LOG_ + log_sink_ = std::make_shared(filter); +#elif _WIN32 + log_sink_ = std::make_shared(ident, filter); +#elif HAS_SYSLOG_ + log_sink_ = std::make_shared(ident_.c_str(), filter); +#else + /// will not throw or something. Use "get_logger()" to check for success + log_sink_ = nullptr; +#endif + } + + virtual log_sink_ptr get_logger() + { + return log_sink_; + } + + void log(const Metadata& metadata, const std::string& message) override + { + if (log_sink_ != nullptr) + log_sink_->log(metadata, message); + } + +protected: + log_sink_ptr log_sink_; + std::string ident_; +}; + +/** + * @brief + * Forward log messages to a callback function + * + * Pass the callback function to the c'tor. + * This can be any function that matches the signature of "callback_fun" + * Might also be a lambda function + */ +struct SinkCallback : public Sink +{ + using callback_fun = std::function; + + SinkCallback(const Filter& filter, callback_fun callback) : Sink(filter), callback_(callback) + { + } + + void log(const Metadata& metadata, const std::string& message) override + { + if (callback_) + callback_(metadata, message); + } + +private: + callback_fun callback_; +}; + +/** + * @brief + * ostream << operator for "Severity" + * + * Severity must be the first thing that is logged into clog, since it will reset the loggers metadata. + */ +static std::ostream& operator<<(std::ostream& os, const Severity& log_severity) +{ + Log* log = dynamic_cast(os.rdbuf()); + if (log != nullptr) + { + std::lock_guard lock(log->mutex_); + if (log->metadata_.severity != log_severity) + { + log->sync(); + log->metadata_.severity = log_severity; + log->metadata_.timestamp = nullptr; + log->metadata_.tag = nullptr; + log->metadata_.function = nullptr; + log->conditional_.set(true); + } + } + else + { + os << to_string(log_severity); + } + return os; +} + +static std::ostream& operator<<(std::ostream& os, const Timestamp& timestamp) +{ + Log* log = dynamic_cast(os.rdbuf()); + if (log != nullptr) + { + std::lock_guard lock(log->mutex_); + log->metadata_.timestamp = timestamp; + } + else if (timestamp) + { + os << timestamp.to_string(); + } + return os; +} + +static std::ostream& operator<<(std::ostream& os, const Tag& tag) +{ + Log* log = dynamic_cast(os.rdbuf()); + if (log != nullptr) + { + std::lock_guard lock(log->mutex_); + log->metadata_.tag = tag; + } + else if (tag) + { + os << tag.text; + } + return os; +} + +static std::ostream& operator<<(std::ostream& os, const Function& function) +{ + Log* log = dynamic_cast(os.rdbuf()); + if (log != nullptr) + { + std::lock_guard lock(log->mutex_); + log->metadata_.function = function; + } + else if (function) + { + os << function.name; + } + return os; +} + +static std::ostream& operator<<(std::ostream& os, const Conditional& conditional) +{ + Log* log = dynamic_cast(os.rdbuf()); + if (log != nullptr) + { + std::lock_guard lock(log->mutex_); + log->conditional_.set(conditional.is_true()); + } + return os; +} + +static std::ostream& operator<<(std::ostream& os, const TextColor& text_color) +{ + os << "\033["; + if ((text_color.foreground == Color::none) && (text_color.background == Color::none)) + os << "0"; // reset colors if no params + + if (text_color.foreground != Color::none) + { + os << 29 + static_cast(text_color.foreground); + if (text_color.background != Color::none) + os << ";"; + } + if (text_color.background != Color::none) + os << 39 + static_cast(text_color.background); + os << "m"; + + return os; +} + +static std::ostream& operator<<(std::ostream& os, const Color& color) +{ + os << TextColor(color); + return os; +} + +} // namespace AixLog + +#ifdef _WIN32 +// We restore the ERROR Windows macro +#pragma pop_macro("ERROR") +#pragma pop_macro("DEBUG") +#endif + +#endif // AIX_LOG_HPP diff --git a/fpga/linux/mhu_test/physmem/inc/physmem.hpp b/fpga/linux/mhu_test/physmem/inc/physmem.hpp new file mode 100644 index 0000000..90ddd3f --- /dev/null +++ b/fpga/linux/mhu_test/physmem/inc/physmem.hpp @@ -0,0 +1,479 @@ +/** Copyright (c) 2020 ETH Zurich, University of Bologna + * SPDX-License-Identifier: Apache-2.0 + * + * Header-Only Library for Physical Memory Accessing on Linux + * + * Author: Andreas Kurth + */ + +#ifndef HERO_PHYSMEM_H_ +#define HERO_PHYSMEM_H_ + +#include // open() +#include // mmap(), munmap() +#include // close(), sysconf() + +#include // errno +#include // std::strerror() +#include +#include + +#include "aixlog.hpp" +#include "string_format.hpp" + +class PhysMem { + public: + /** Map a physical memory region and make it accessible for reads and writes. + + \param base_addr Physical base address of the mapping; must be a multiple of the OS page + size + \param n_bytes Number of bytes in the mapping + + Throws an `std::invalid_argument` exception if `base_addr` is not aligned to the OS page size. + Throws an `std::runtime_error` exception if `/dev/mem` cannot be opened in read-write mode or + if the call to `mmap()` fails. + */ + PhysMem(const uintptr_t base_addr, const size_t n_bytes) + : PhysMem(base_addr, n_bytes, false){ + // Delegate implementation to protected constructor (see below) with `mock_only` + // argument set to `false`. + }; + + ~PhysMem() { + // If this object only mocked physical memory accesses, the destructor has nothing to do. + if (this->mock_only) { + return; + } + + const int res = munmap(const_cast(this->map_ptr), this->n_bytes); + LOG(DEBUG) << "Unmapped memory." << std::endl; + if (res == -1) { + LOG(ERROR) << "'munmap' failed!" << std::endl; + } + close(this->fd); + LOG(DEBUG) << "Closed '/dev/mem'." << std::endl; + } + + /** Read from a physical address in the mapped memory region. + + \param phys_addr Physical address to be read from + \return The read value. + + Throws an `std::invalid_argument` exception if `phys_addr` is not in the mapped memory + region. + */ + template + T read(const uintptr_t phys_addr) const { + this->validate_addr(phys_addr); + + if (this->mock_only) { + LOG(DEBUG) << "Would read"; + } else { + LOG(DEBUG) << "Reading"; + } + LOG(DEBUG) << " from 0x" << std::hex << phys_addr << "." << std::endl; + + // If this object only mocks physical memory accesses, return before the actual read. + if (this->mock_only) { + return 0; + } + + const T value = *reinterpret_cast(this->rel_ptr(phys_addr)); + LOG(DEBUG) << "Read 0x" << std::hex << static_cast(value) << "." << std::endl; + return value; + } + + /** Read an unsigned 64-bit value from a physical address in the mapped memory region. + + See `read()` member function for the documentation. + */ + uint64_t read_u64(const uintptr_t phys_addr) const { return this->read(phys_addr); } + + /** Read an unsigned 32-bit value from a physical address in the mapped memory region. + + See `read()` member function for the documentation. + */ + uint32_t read_u32(const uintptr_t phys_addr) const { return this->read(phys_addr); } + + /** Read an unsigned 16-bit value from a physical address in the mapped memory region. + + See `read()` member function for the documentation. + */ + uint16_t read_u16(const uintptr_t phys_addr) const { return this->read(phys_addr); } + + /** Read an unsigned 8-bit value from a physical address in the mapped memory region. + + See `read()` member function for the documentation. + */ + uint8_t read_u8(const uintptr_t phys_addr) const { return this->read(phys_addr); } + + /** Write to a physical address in the mapped memory region. + + \param phys_addr Physical address to be written to + \param value Value to write + + Throws an `std::invalid_argument` exception if `phys_addr` is not in the mapped memory region. + */ + template + void write(const uintptr_t phys_addr, const T value) { + this->validate_addr(phys_addr); + + if (this->mock_only) { + LOG(DEBUG) << "Would write"; + } else { + LOG(DEBUG) << "Writing"; + } + LOG(DEBUG) << " 0x" << std::hex << static_cast(value) << " to 0x" << phys_addr + << "." << std::endl; + + // If this object only mocks physical memory accesses, return before the actual write. + if (this->mock_only) { + return; + } + + *reinterpret_cast(this->rel_ptr(phys_addr)) = value; + } + + /** Write an unsigned 64-bit value to a physical address in the mapped memory region. + + See `write()` member function for the documentation. + */ + void write_u64(const uintptr_t phys_addr, const uint64_t value) { + this->write(phys_addr, value); + } + + /** Write an unsigned 32-bit value to a physical address in the mapped memory region. + + See `write()` member function for the documentation. + */ + void write_u32(const uintptr_t phys_addr, const uint32_t value) { + this->write(phys_addr, value); + } + + /** Write an unsigned 16-bit value to a physical address in the mapped memory region. + + See `write()` member function for the documentation. + */ + void write_u16(const uintptr_t phys_addr, const uint16_t value) { + this->write(phys_addr, value); + } + + /** Write an unsigned 8-bit value to a physical address in the mapped memory region. + + See `write()` member function for the documentation. + */ + void write_u8(const uintptr_t phys_addr, const uint8_t value) { + this->write(phys_addr, value); + } + + /** Determine if a physical address is in the mapped memory region. + + \param phys_addr Physical address + \return `true` if `phys_addr` is in the mapped memory region; + `false` if it is not. + */ + bool maps_addr(const uintptr_t phys_addr) const { + return (phys_addr >= this->base_addr) && (phys_addr < this->base_addr + this->n_bytes); + } + + /** Determine if a physical address range is entirely in the mapped memory region. + + \param phys_addr Physical address that is the start of the address range + \param n_bytes Number of bytes in the address range + \return `true` if every address in the interval [phys_addr, phys_addr+n_bytes) is + in the mapped memory region; `false` otherwise. + */ + bool maps_addr_range(const uintptr_t phys_addr, const size_t n_bytes) const { + return this->maps_addr(phys_addr) && this->maps_addr(phys_addr + n_bytes - 1); + } + + /** Sets each byte in an address range to a given value. + + This function does *not* necessarily perform byte-wise stores! In particular, this function + may write multiple bytes at once if alignment and total number of bytes permit. + + \param phys_addr First physical address to write to + \param val Byte value to write + \param n_bytes Number of bytes that shall be written + + Throws an `std::invalid_argument` exception if an address in the interval + [phys_addr, phys_addr+n_bytes) is not mapped. + */ + void set(const uintptr_t phys_addr, const uint8_t val, size_t n_bytes) { + this->validate_addr_range(phys_addr, n_bytes); + + if (this->mock_only) { + LOG(DEBUG) << "Would set"; + } else { + LOG(DEBUG) << "Setting"; + } + LOG(DEBUG) << " all bytes in address range " + << string_format("[0x%p, 0x%p] to 0x%02x.", phys_addr, phys_addr + n_bytes - 1, val) + << std::endl; + + // If this object only mocks physical memory accesses, return before the actual writes. + if (this->mock_only) { + return; + } + + // If necessary, write a few bytes until the address is 64-bit aligned. + volatile uint8_t* ptr = reinterpret_cast(this->rel_ptr(phys_addr)); + while (reinterpret_cast(ptr) % 8 != 0 && n_bytes > 0) { + *ptr++ = val; + n_bytes--; + } + // Then write as much as possible with 64-bit accesses. + volatile uint64_t* ptr64 = reinterpret_cast(ptr); + while (n_bytes > 7) { + *ptr64++ = u64_from_u8(val, val, val, val, val, val, val, val); + n_bytes -= 8; + } + // Write remainder with 8-bit accesses. + volatile uint8_t* ptr8 = reinterpret_cast(ptr64); + while (n_bytes > 0) { + *ptr8++ = val; + n_bytes--; + } + } + + /** Copy buffer to the physical memory region. + + \param phys_addr First physical address to write to. + \param src Iterator into the source buffer. This iterator must be able to provide + `n_bytes` bytes. The iterator will be incremented `n_bytes-1` times, and + if it goes out of bounds during an increment, undefined behavior occurs. + \param n_bytes Number of bytes to write. + + Throws an `std::invalid_argument` exception if an address in the interval + [phys_addr, phys_addr+n_bytes) is not mapped. When this exception is thrown, this function + has not accessed the physical memory region. + */ + void copy_to(const uintptr_t phys_addr, std::vector::const_iterator src, + size_t n_bytes) { + this->validate_addr_range(phys_addr, n_bytes); + + if (this->mock_only) { + LOG(DEBUG) << "Would write"; + } else { + LOG(DEBUG) << "Writing"; + } + LOG(DEBUG) << " to address range " + << string_format("[0x%p, 0x%p].", phys_addr, phys_addr + n_bytes - 1) << std::endl; + + // If this object only mocks physical memory accesses, return before the actual writes. + if (this->mock_only) { + return; + } + + // If necessary, write a few bytes until the address is 64-bit aligned. + volatile uint8_t* ptr = reinterpret_cast(this->rel_ptr(phys_addr)); + while (reinterpret_cast(ptr) % 8 != 0 && n_bytes > 0) { + *ptr++ = *src++; + n_bytes--; + } + // Then write as much as possible with 64-bit accesses. + volatile uint64_t* ptr64 = reinterpret_cast(ptr); + while (n_bytes > 7) { + *ptr64++ = u64_from_u8(*src++, *src++, *src++, *src++, *src++, *src++, *src++, *src++); + n_bytes -= 8; + } + // Write remainder with 8-bit accesses. + volatile uint8_t* ptr8 = reinterpret_cast(ptr64); + while (n_bytes > 0) { + *ptr8++ = *src++; + n_bytes--; + } + } + + /** Copy from the physical memory region into a buffer. + + \param phys_addr First physical address to read from. + \param dst Destination buffer. This function reserves `n_bytes` in this + `std::vector`, so a pre-reservation is not necessary. + \param n_bytes Number of bytes to read. + + Throws an `std::invalid_argument` exception if an address in the interval + [phys_addr, phys_addr+n_bytes) is not mapped. When this exception is thrown, this function + has not accessed the physical memory region and has not reserved capacity in `dst`. + */ + void copy_from(const uintptr_t phys_addr, std::vector& dst, size_t n_bytes) const { + this->validate_addr_range(phys_addr, n_bytes); + + if (this->mock_only) { + LOG(DEBUG) << "Would read"; + } else { + LOG(DEBUG) << "Reading"; + } + LOG(DEBUG) << " from address range " + << string_format("[0x%p, 0x%p].", phys_addr, phys_addr + n_bytes - 1) << std::endl; + + // Reserve memory in destination buffer. + dst.reserve(n_bytes); + + // If this object only mocks physical memory accesses, return before the actual reads. + if (this->mock_only) { + return; + } + + // If necessary, read a few bytes until the address is 64-bit aligned. + const volatile uint8_t* ptr = + reinterpret_cast(this->rel_ptr(phys_addr)); + while (reinterpret_cast(ptr) % 8 != 0 && n_bytes > 0) { + dst.push_back(static_cast(*ptr++)); + n_bytes--; + } + // Then read as much as possible with 64-bit accesses. + const volatile uint64_t* ptr64 = reinterpret_cast(ptr); + while (n_bytes > 7) { + const uint64_t val = *ptr64++; + dst.push_back((val >> 0) & 0xFF); + dst.push_back((val >> 8) & 0xFF); + dst.push_back((val >> 16) & 0xFF); + dst.push_back((val >> 24) & 0xFF); + dst.push_back((val >> 32) & 0xFF); + dst.push_back((val >> 40) & 0xFF); + dst.push_back((val >> 48) & 0xFF); + dst.push_back((val >> 56) & 0xFF); + n_bytes -= 8; + } + // Read remainder with 8-bit accesses. + const volatile uint8_t* ptr8 = reinterpret_cast(ptr64); + while (n_bytes > 0) { + dst.push_back(static_cast(*ptr8++)); + n_bytes--; + } + } + + protected: + /** Internal constructor of a physical memory mapping. This contains the actual constructor + implementation and takes the following parameter in addition to the public `PhysMem` + constructor: + + \param mock_only Whether this only mocks a physical memory mapping (see documentation of + `MockPhysMem` for details). + */ + PhysMem(const uintptr_t base_addr, const size_t n_bytes, const bool mock_only) + : base_addr(base_addr), n_bytes(n_bytes), map_mask(n_bytes - 1), mock_only(mock_only) { + // Initialize logging library. This should actually not be done in the constructor, because + // creating two `PhysMem` objects now probably corrupts logging. However, if `AixLog` is not + // initialized at all, it unconditionally prints every message and does not format them + // properly. So we would burden the user to initialize the logging library for using this + // class, which is unintuitive as well. Maybe this should be replaced by a better header-only + // logging library; but I know none. + // + // To increase logging verbosity, change to `AixLog::Severity::debug` or lower. + if (mock_only) { + AixLog::Log::init(AixLog::Severity::debug); + } else { + AixLog::Log::init(AixLog::Severity::warning); + } + + // Ensure that base address is a multiple of the OS page size. + const size_t page_size = sysconf(_SC_PAGE_SIZE); + if (base_addr % page_size != 0) { + throw std::invalid_argument(string_format( + "'base_addr' (%p) is not aligned with OS page size (%d B)", base_addr, page_size)); + } + + // If this object only mocks physical memory accesses, print an info message and exit the + // constructor early. + if (mock_only) { + LOG(INFO) << "Mock-only PhysMem. Would map 0x" << std::hex << n_bytes + << " bytes starting at 0x" << base_addr << "." << std::endl; + return; + } + + // Open a file descriptor into `/dev/mem`. + this->fd = open("/dev/mem", O_RDWR | O_SYNC); + if (this->fd == -1) { + throw std::runtime_error( + string_format("Could not open '/dev/mem': '%s'!", std::strerror(errno))); + } + LOG(DEBUG) << "Opened '/dev/mem' with fd=" << this->fd << "." << std::endl; + + // Map the specified physical memory region. + this->map_ptr = mmap(0, this->n_bytes, PROT_READ | PROT_WRITE, MAP_SHARED, fd, + this->base_addr & ~this->map_mask); + if (this->map_ptr == reinterpret_cast(-1)) { + throw std::runtime_error(string_format("'mmap' failed: '%s'!", std::strerror(errno))); + } + LOG(DEBUG) << "Memory mapped at address " << const_cast(this->map_ptr) << "." + << std::endl; + }; + + private: + /** The file descriptor returned by `open`. */ + int fd; + /** The `base_addr` and `n_bytes` given to the constructor. */ + const uintptr_t base_addr; + const size_t n_bytes; + /** Bitmask that selects the LSBs within `n_bytes`. */ + const size_t map_mask; + /** The pointer returned by `mmap`. */ + volatile void* map_ptr; + /** Whether this object only mocks physical memory accesses. */ + const bool mock_only; + + /** Get relative pointer in the virtual address space that can be used to access a physical + address. + + \param phys_addr Physical address + \return Virtual address pointer that corresponds to the physical address. + */ + inline volatile void* rel_ptr(const uintptr_t phys_addr) const { + if (this->mock_only) { + throw std::runtime_error("method undefined for mock PhysMem"); + } + const uintptr_t offset = phys_addr & this->map_mask; + const uintptr_t rel_addr = reinterpret_cast(this->map_ptr) + offset; + return reinterpret_cast(rel_addr); + } + + /** Validate that a physical address is in the mapped memory region. + + Throws an `std::invalid_argument` exception if that is not the case. + */ + inline void validate_addr(const uintptr_t phys_addr) const { + if (!this->maps_addr(phys_addr)) { + throw std::invalid_argument(string_format("Address %p is not mapped!", phys_addr)); + } + } + + /** Validate that a physical address range is in the mapped memory region. + + Throws an `std::invalid_argument` exception if that is not the case. + */ + inline void validate_addr_range(const uintptr_t phys_addr, const size_t n_bytes) const { + if (!this->maps_addr_range(phys_addr, n_bytes)) { + throw std::invalid_argument( + string_format("Address range [%p,%p) is not mapped!", phys_addr, phys_addr + n_bytes)); + } + } + + static inline uint64_t u64_from_u8(const uint8_t byte0, const uint8_t byte1, const uint8_t byte2, + const uint8_t byte3, const uint8_t byte4, const uint8_t byte5, + const uint8_t byte6, const uint8_t byte7) { + return (static_cast(byte0) << 0) | (static_cast(byte1) << 8) | + (static_cast(byte2) << 16) | (static_cast(byte3) << 24) | + (static_cast(byte4) << 32) | (static_cast(byte5) << 40) | + (static_cast(byte6) << 48) | (static_cast(byte7) << 56); + } +}; + +class MockPhysMem : public PhysMem { + public: + /** Mock mapping a physical memory region. This does *not* map or access any physical memory, but + it prints the addresses of all calls to the `read()` and `write()` member functions. This can + be useful for the validation of a program that accesses physical memory without risking any + memory corruption or undesired side effects. + + - This class inherits the entire public API from `PhysMem`, so it is documented there. + - `write()` additionally prints the value that would be written. + - `read()` always returns `0` and does not print a value (since the value that would be read + is obviously unknown). + */ + MockPhysMem(const uintptr_t base_addr, const size_t n_bytes) + : PhysMem(base_addr, n_bytes, true){}; +}; + +#endif // HERO_PHYSMEM_H_ diff --git a/fpga/linux/mhu_test/physmem/inc/string_format.hpp b/fpga/linux/mhu_test/physmem/inc/string_format.hpp new file mode 100644 index 0000000..36055b7 --- /dev/null +++ b/fpga/linux/mhu_test/physmem/inc/string_format.hpp @@ -0,0 +1,25 @@ +/** Copyright (c) 2015 iFreilicht + * SPDX-License-Identifier: CC0-1.0 + * Source: https://stackoverflow.com/a/26221725 + * + * C++11-compatible String Formatting + */ + +#ifndef HERO_STRING_FORMAT_H_ +#define HERO_STRING_FORMAT_H_ + +#include +#include +#include + +template +std::string string_format( const std::string& format, Args ... args ) +{ + size_t size = snprintf( nullptr, 0, format.c_str(), args ... ) + 1; // Extra space for '\0' + if( size <= 0 ){ throw std::runtime_error( "Error during formatting." ); } + std::unique_ptr buf( new char[ size ] ); + snprintf( buf.get(), size, format.c_str(), args ... ); + return std::string( buf.get(), buf.get() + size - 1 ); // We don't want the '\0' inside +} + +#endif // HERO_STRING_FORMAT_H_ diff --git a/fpga/linux/mhu_test/setspeed.c b/fpga/linux/mhu_test/setspeed.c new file mode 100644 index 0000000..5f57120 --- /dev/null +++ b/fpga/linux/mhu_test/setspeed.c @@ -0,0 +1,15 @@ +#include +#include + +#define MAX_LEN 10 + +int main(int argc, char *argv[]) { + FILE *fp; + fp = fopen("/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed", "w"); + if(fp == NULL){ + printf("error opening file"); + return 0; + } + fprintf(fp, "%s", argv[1]); + return 1; +} diff --git a/fpga/linux/petalinux/zcu102.sh b/fpga/linux/petalinux/zcu102.sh index 3a391c6..230476f 100755 --- a/fpga/linux/petalinux/zcu102.sh +++ b/fpga/linux/petalinux/zcu102.sh @@ -19,6 +19,7 @@ # Robert Balas # Alessandro Ottaviano + THIS_DIR=$(dirname "$(readlink -f "${BASH_SOURCE[0]}")") set -e @@ -40,30 +41,44 @@ readonly TARGET=zcu102 cd `pwd -P` +echo "create proj" # create project if [ ! -d "$TARGET" ]; then $PETALINUX_VER petalinux-create -t project -n "$TARGET" --template zynqMP fi cd "$TARGET" -# initialize and set necessary configuration from config and local config -$PETALINUX_VER petalinux-config --oldconfig --get-hw-description "../../../control_pulp-txilzu9eg/control_pulp-txilzu9eg/control_pulp-txilzu9eg.sdk" +#initialize and set necessary configuration from config and local config +$PETALINUX_VER petalinux-config --defconfig scmi_defconfig --get-hw-description "$THIS_DIR/../../control_pulp-txilzu9eg/control_pulp-txilzu9eg/control_pulp-txilzu9eg.sdk" + +cd build mkdir -p components/ext_sources cd components/ext_sources if [ ! -d "linux-xlnx" ]; then - git clone --depth 1 --single-branch --branch xilinx-v2019.2.01 git://github.com/Xilinx/linux-xlnx.git + git clone --depth 1 --single-branch --branch linux-scmi git://github.com/Antoniodv/linux-xlnx fi cd linux-xlnx -git checkout tags/xilinx-v2019.2.01 -cd ../../../ +# write kernel configuration +sed -i "s/plnx_kernel.cfg/scmi_plnx_kernel.cfg/" $THIS_DIR/zcu102/project-spec/meta-plnx-generated/recipes-kernel/linux/linux-xlnx_%.bbappend + +echo " ====== KERNEL CONFIG WRITTEN ======" + +# add new command and then set it as default (so that if bootcmd is called in boot.scr, it works normally) +sed -i '/PSSERIAL0 /a\ "run_script_cmd=load mmc 0:1 $loadaddr boot.scr; source $loadaddr\\0" \\' $THIS_DIR/zcu102/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h +sed -i 's/#define CONFIG_BOOTCOMMAND "run default_bootcmd"/#define CONFIG_BOOTCOMMAND "run run_script_cmd"/' $THIS_DIR/zcu102/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h + +echo " ====== CONTROL PULP AUTOFLASH COMMAND CREATED ======" + if [[ ! -f "$THIS_DIR/../board/xilzcu102/control_pulp.dtsi" ]]; then echo "error: control_pulp.dtsi not found" exit 1 fi +cd $THIS_DIR/zcu102 + echo " /include/ \"system-conf.dtsi\" /include/ \"$THIS_DIR/../board/xilzcu102/control_pulp.dtsi\" @@ -71,6 +86,10 @@ echo " }; " > project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi + +echo " ====== DTSI SOURCED ====== " + + # start build set +e $PETALINUX_VER petalinux-build @@ -78,6 +97,8 @@ echo "First build might fail, this is expected..." set -e mkdir -p build/tmp/work/aarch64-xilinx-linux/external-hdf/1.0-r0/git/plnx_aarch64/ cp project-spec/hw-description/system.hdf build/tmp/work/aarch64-xilinx-linux/external-hdf/1.0-r0/git/plnx_aarch64/ + + $PETALINUX_VER petalinux-build mkdir -p build/tmp/work/aarch64-xilinx-linux/external-hdf/1.0-r0/git/plnx_aarch64/ @@ -87,6 +108,9 @@ if [ ! -f regs.init ]; then echo ".set. 0xFF41A040 = 0x3;" > regs.init fi +echo " ====== PETALINUX BUILD DONE ====== " + + # add bitstream from local config if [ -f "$THIS_DIR/../../output/pms.bit" ]; then cp "$THIS_DIR/../../output/pms.bit" "control_pulp_exil${TARGET}_wrapper.bit" diff --git a/fpga/linux/petalinux/zcu102/project-spec/configs/config b/fpga/linux/petalinux/zcu102/project-spec/configs/config index e31b26b..e5848e1 100644 --- a/fpga/linux/petalinux/zcu102/project-spec/configs/config +++ b/fpga/linux/petalinux/zcu102/project-spec/configs/config @@ -28,6 +28,7 @@ CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC=y # CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT_LOCAL_SRC_PATH="${TOPDIR}/../components/ext_sources/linux-xlnx" + # # Auto Config Settings # @@ -280,4 +281,59 @@ CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/r # User Layers # CONFIG_USER_LAYER_0="" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait" diff --git a/fpga/linux/pmsctl/Makefile b/fpga/linux/pmsctl/Makefile index e995986..ada11c8 100644 --- a/fpga/linux/pmsctl/Makefile +++ b/fpga/linux/pmsctl/Makefile @@ -16,12 +16,18 @@ # Author: Robert Balas (balasr@iis.ee.ethz.ch) CXX=aarch64-none-linux-gnu-g++ +C=aarch64-none-linux-gnu-gcc -all: pmsctl +all: pmsctl scmictl pmsctl: pmsctl.cc $(wildcard physmem/inc/*) $(CXX) -std=c++11 -Wall -I. $(CXXFLAGS) $(CPPFLAGS) $< -o $@; +scmictl: scmictl.cc $(wildcard physmem/inc/*) + $(CXX) -std=c++11 -Wall -I. $(CXXFLAGS) $(CPPFLAGS) $< -o $@; .PHONY: clean + clean: $(RM) pmsctl + $(RM) scmictl + diff --git a/fpga/linux/pmsctl/pmsctl.cc b/fpga/linux/pmsctl/pmsctl.cc index 33fae92..4d318e8 100644 --- a/fpga/linux/pmsctl/pmsctl.cc +++ b/fpga/linux/pmsctl/pmsctl.cc @@ -67,7 +67,7 @@ int main() { // 2. load L2 std::cout << "Load L2 memory from stimuli file \n"; - int i = 0; + std::string line; std::ifstream myfile; myfile.open("stim.txt"); diff --git a/fpga/linux/pmsrst/pmsrst.c b/fpga/linux/pmsrst/pmsrst.c deleted file mode 100644 index aac3489..0000000 --- a/fpga/linux/pmsrst/pmsrst.c +++ /dev/null @@ -1,30 +0,0 @@ -#include -#include - -#define RST_ACTIVE_LOW 0x80000000 - -int main() { - - volatile int err = 0; - volatile int value = 0; - - printf("Read reset value of the PL\r\n"); - system("devmem 0xFF0A0054 w"); - - printf("Assert reset for the PL\r\n"); - system("devmem 0xFF0A0054 32 0x00000000"); - - printf("Release reset for the PL\r\n"); - system("devmem 0xFF0A0054 32 0x80000000"); - - printf("Read reset value of the PL\r\n"); - FILE *output = popen("devmem 0xFF0A0054 w", "r"); - fscanf(output, "0x%08x", &value); - pclose(output); - - if (value != RST_ACTIVE_LOW) { - err++; - } - - return err; -} diff --git a/hw/ips/axi_scmi_mailbox/Makefile b/hw/ips/axi_scmi_mailbox/Makefile index 7e58f85..478a648 100644 --- a/hw/ips/axi_scmi_mailbox/Makefile +++ b/hw/ips/axi_scmi_mailbox/Makefile @@ -5,20 +5,24 @@ # Generate C header file -NUM_CHANNELS = 64 +PYTHON_VER = python3.6 + +NUM_CHANNELS = 1 REGTOOL=../register_interface/vendor/lowrisc_opentitan/util/regtool.py -all: rtl/axi_scmi_mailbox.sv scmi.hjson headers +all: rtl/axi_scmi_mailbox.sv scmi.hjson headers registers rtl/axi_scmi_mailbox.sv: rtl/axi_scmi_mailbox.sv.tpl - python3.6 scmi.py -s $(NUM_CHANNELS) < $< > $@ + $(PYTHON_VER) scmi.py -s $(NUM_CHANNELS) < $< > $@ scmi.hjson: scmi.hjson.tpl - python3.6 scmi.py -s $(NUM_CHANNELS) < $< > $@ + $(PYTHON_VER) scmi.py -s $(NUM_CHANNELS) < $< > $@ headers: scmi.h scmi.h: scmi.hjson $(REGTOOL) --cdefines $< > $@ +registers: scmi.hjson + $(REGTOOL) -r -t rtl/ $< diff --git a/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv b/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv index 305e157..b083f35 100644 --- a/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv +++ b/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv @@ -74,134 +74,8 @@ module axi_scmi_mailbox scmi_reg_pkg::scmi_reg2hw_t reg2hw; - assign irq_doorbell_o[0] = reg2hw.doorbell_c0.intr.q; - assign irq_completion_o[0] = reg2hw.completion_interrupt_c0.intr.q; - assign irq_doorbell_o[1] = reg2hw.doorbell_c1.intr.q; - assign irq_completion_o[1] = reg2hw.completion_interrupt_c1.intr.q; - assign irq_doorbell_o[2] = reg2hw.doorbell_c2.intr.q; - assign irq_completion_o[2] = reg2hw.completion_interrupt_c2.intr.q; - assign irq_doorbell_o[3] = reg2hw.doorbell_c3.intr.q; - assign irq_completion_o[3] = reg2hw.completion_interrupt_c3.intr.q; - assign irq_doorbell_o[4] = reg2hw.doorbell_c4.intr.q; - assign irq_completion_o[4] = reg2hw.completion_interrupt_c4.intr.q; - assign irq_doorbell_o[5] = reg2hw.doorbell_c5.intr.q; - assign irq_completion_o[5] = reg2hw.completion_interrupt_c5.intr.q; - assign irq_doorbell_o[6] = reg2hw.doorbell_c6.intr.q; - assign irq_completion_o[6] = reg2hw.completion_interrupt_c6.intr.q; - assign irq_doorbell_o[7] = reg2hw.doorbell_c7.intr.q; - assign irq_completion_o[7] = reg2hw.completion_interrupt_c7.intr.q; - assign irq_doorbell_o[8] = reg2hw.doorbell_c8.intr.q; - assign irq_completion_o[8] = reg2hw.completion_interrupt_c8.intr.q; - assign irq_doorbell_o[9] = reg2hw.doorbell_c9.intr.q; - assign irq_completion_o[9] = reg2hw.completion_interrupt_c9.intr.q; - assign irq_doorbell_o[10] = reg2hw.doorbell_c10.intr.q; - assign irq_completion_o[10] = reg2hw.completion_interrupt_c10.intr.q; - assign irq_doorbell_o[11] = reg2hw.doorbell_c11.intr.q; - assign irq_completion_o[11] = reg2hw.completion_interrupt_c11.intr.q; - assign irq_doorbell_o[12] = reg2hw.doorbell_c12.intr.q; - assign irq_completion_o[12] = reg2hw.completion_interrupt_c12.intr.q; - assign irq_doorbell_o[13] = reg2hw.doorbell_c13.intr.q; - assign irq_completion_o[13] = reg2hw.completion_interrupt_c13.intr.q; - assign irq_doorbell_o[14] = reg2hw.doorbell_c14.intr.q; - assign irq_completion_o[14] = reg2hw.completion_interrupt_c14.intr.q; - assign irq_doorbell_o[15] = reg2hw.doorbell_c15.intr.q; - assign irq_completion_o[15] = reg2hw.completion_interrupt_c15.intr.q; - assign irq_doorbell_o[16] = reg2hw.doorbell_c16.intr.q; - assign irq_completion_o[16] = reg2hw.completion_interrupt_c16.intr.q; - assign irq_doorbell_o[17] = reg2hw.doorbell_c17.intr.q; - assign irq_completion_o[17] = reg2hw.completion_interrupt_c17.intr.q; - assign irq_doorbell_o[18] = reg2hw.doorbell_c18.intr.q; - assign irq_completion_o[18] = reg2hw.completion_interrupt_c18.intr.q; - assign irq_doorbell_o[19] = reg2hw.doorbell_c19.intr.q; - assign irq_completion_o[19] = reg2hw.completion_interrupt_c19.intr.q; - assign irq_doorbell_o[20] = reg2hw.doorbell_c20.intr.q; - assign irq_completion_o[20] = reg2hw.completion_interrupt_c20.intr.q; - assign irq_doorbell_o[21] = reg2hw.doorbell_c21.intr.q; - assign irq_completion_o[21] = reg2hw.completion_interrupt_c21.intr.q; - assign irq_doorbell_o[22] = reg2hw.doorbell_c22.intr.q; - assign irq_completion_o[22] = reg2hw.completion_interrupt_c22.intr.q; - assign irq_doorbell_o[23] = reg2hw.doorbell_c23.intr.q; - assign irq_completion_o[23] = reg2hw.completion_interrupt_c23.intr.q; - assign irq_doorbell_o[24] = reg2hw.doorbell_c24.intr.q; - assign irq_completion_o[24] = reg2hw.completion_interrupt_c24.intr.q; - assign irq_doorbell_o[25] = reg2hw.doorbell_c25.intr.q; - assign irq_completion_o[25] = reg2hw.completion_interrupt_c25.intr.q; - assign irq_doorbell_o[26] = reg2hw.doorbell_c26.intr.q; - assign irq_completion_o[26] = reg2hw.completion_interrupt_c26.intr.q; - assign irq_doorbell_o[27] = reg2hw.doorbell_c27.intr.q; - assign irq_completion_o[27] = reg2hw.completion_interrupt_c27.intr.q; - assign irq_doorbell_o[28] = reg2hw.doorbell_c28.intr.q; - assign irq_completion_o[28] = reg2hw.completion_interrupt_c28.intr.q; - assign irq_doorbell_o[29] = reg2hw.doorbell_c29.intr.q; - assign irq_completion_o[29] = reg2hw.completion_interrupt_c29.intr.q; - assign irq_doorbell_o[30] = reg2hw.doorbell_c30.intr.q; - assign irq_completion_o[30] = reg2hw.completion_interrupt_c30.intr.q; - assign irq_doorbell_o[31] = reg2hw.doorbell_c31.intr.q; - assign irq_completion_o[31] = reg2hw.completion_interrupt_c31.intr.q; - assign irq_doorbell_o[32] = reg2hw.doorbell_c32.intr.q; - assign irq_completion_o[32] = reg2hw.completion_interrupt_c32.intr.q; - assign irq_doorbell_o[33] = reg2hw.doorbell_c33.intr.q; - assign irq_completion_o[33] = reg2hw.completion_interrupt_c33.intr.q; - assign irq_doorbell_o[34] = reg2hw.doorbell_c34.intr.q; - assign irq_completion_o[34] = reg2hw.completion_interrupt_c34.intr.q; - assign irq_doorbell_o[35] = reg2hw.doorbell_c35.intr.q; - assign irq_completion_o[35] = reg2hw.completion_interrupt_c35.intr.q; - assign irq_doorbell_o[36] = reg2hw.doorbell_c36.intr.q; - assign irq_completion_o[36] = reg2hw.completion_interrupt_c36.intr.q; - assign irq_doorbell_o[37] = reg2hw.doorbell_c37.intr.q; - assign irq_completion_o[37] = reg2hw.completion_interrupt_c37.intr.q; - assign irq_doorbell_o[38] = reg2hw.doorbell_c38.intr.q; - assign irq_completion_o[38] = reg2hw.completion_interrupt_c38.intr.q; - assign irq_doorbell_o[39] = reg2hw.doorbell_c39.intr.q; - assign irq_completion_o[39] = reg2hw.completion_interrupt_c39.intr.q; - assign irq_doorbell_o[40] = reg2hw.doorbell_c40.intr.q; - assign irq_completion_o[40] = reg2hw.completion_interrupt_c40.intr.q; - assign irq_doorbell_o[41] = reg2hw.doorbell_c41.intr.q; - assign irq_completion_o[41] = reg2hw.completion_interrupt_c41.intr.q; - assign irq_doorbell_o[42] = reg2hw.doorbell_c42.intr.q; - assign irq_completion_o[42] = reg2hw.completion_interrupt_c42.intr.q; - assign irq_doorbell_o[43] = reg2hw.doorbell_c43.intr.q; - assign irq_completion_o[43] = reg2hw.completion_interrupt_c43.intr.q; - assign irq_doorbell_o[44] = reg2hw.doorbell_c44.intr.q; - assign irq_completion_o[44] = reg2hw.completion_interrupt_c44.intr.q; - assign irq_doorbell_o[45] = reg2hw.doorbell_c45.intr.q; - assign irq_completion_o[45] = reg2hw.completion_interrupt_c45.intr.q; - assign irq_doorbell_o[46] = reg2hw.doorbell_c46.intr.q; - assign irq_completion_o[46] = reg2hw.completion_interrupt_c46.intr.q; - assign irq_doorbell_o[47] = reg2hw.doorbell_c47.intr.q; - assign irq_completion_o[47] = reg2hw.completion_interrupt_c47.intr.q; - assign irq_doorbell_o[48] = reg2hw.doorbell_c48.intr.q; - assign irq_completion_o[48] = reg2hw.completion_interrupt_c48.intr.q; - assign irq_doorbell_o[49] = reg2hw.doorbell_c49.intr.q; - assign irq_completion_o[49] = reg2hw.completion_interrupt_c49.intr.q; - assign irq_doorbell_o[50] = reg2hw.doorbell_c50.intr.q; - assign irq_completion_o[50] = reg2hw.completion_interrupt_c50.intr.q; - assign irq_doorbell_o[51] = reg2hw.doorbell_c51.intr.q; - assign irq_completion_o[51] = reg2hw.completion_interrupt_c51.intr.q; - assign irq_doorbell_o[52] = reg2hw.doorbell_c52.intr.q; - assign irq_completion_o[52] = reg2hw.completion_interrupt_c52.intr.q; - assign irq_doorbell_o[53] = reg2hw.doorbell_c53.intr.q; - assign irq_completion_o[53] = reg2hw.completion_interrupt_c53.intr.q; - assign irq_doorbell_o[54] = reg2hw.doorbell_c54.intr.q; - assign irq_completion_o[54] = reg2hw.completion_interrupt_c54.intr.q; - assign irq_doorbell_o[55] = reg2hw.doorbell_c55.intr.q; - assign irq_completion_o[55] = reg2hw.completion_interrupt_c55.intr.q; - assign irq_doorbell_o[56] = reg2hw.doorbell_c56.intr.q; - assign irq_completion_o[56] = reg2hw.completion_interrupt_c56.intr.q; - assign irq_doorbell_o[57] = reg2hw.doorbell_c57.intr.q; - assign irq_completion_o[57] = reg2hw.completion_interrupt_c57.intr.q; - assign irq_doorbell_o[58] = reg2hw.doorbell_c58.intr.q; - assign irq_completion_o[58] = reg2hw.completion_interrupt_c58.intr.q; - assign irq_doorbell_o[59] = reg2hw.doorbell_c59.intr.q; - assign irq_completion_o[59] = reg2hw.completion_interrupt_c59.intr.q; - assign irq_doorbell_o[60] = reg2hw.doorbell_c60.intr.q; - assign irq_completion_o[60] = reg2hw.completion_interrupt_c60.intr.q; - assign irq_doorbell_o[61] = reg2hw.doorbell_c61.intr.q; - assign irq_completion_o[61] = reg2hw.completion_interrupt_c61.intr.q; - assign irq_doorbell_o[62] = reg2hw.doorbell_c62.intr.q; - assign irq_completion_o[62] = reg2hw.completion_interrupt_c62.intr.q; - assign irq_doorbell_o[63] = reg2hw.doorbell_c63.intr.q; - assign irq_completion_o[63] = reg2hw.completion_interrupt_c63.intr.q; + assign irq_doorbell_o[0] = |(reg2hw.doorbell_c0.q); + assign irq_completion_o[0] = |(reg2hw.completion_interrupt_c0.q); scmi_reg_top #( .reg_req_t(reg_req_t), diff --git a/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv.tpl b/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv.tpl index 6832084..5911a4f 100644 --- a/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv.tpl +++ b/hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv.tpl @@ -75,8 +75,8 @@ module axi_scmi_mailbox scmi_reg_pkg::scmi_reg2hw_t reg2hw; % for i in range(src): - assign irq_doorbell_o[${i}] = reg2hw.doorbell_c${i}.intr.q; - assign irq_completion_o[${i}] = reg2hw.completion_interrupt_c${i}.intr.q; + assign irq_doorbell_o[${i}] = |(reg2hw.doorbell_c${i}.q); + assign irq_completion_o[${i}] = |(reg2hw.completion_interrupt_c${i}.q); % endfor scmi_reg_top #( diff --git a/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_pkg.sv b/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_pkg.sv index 1ab4f24..a593dd2 100644 --- a/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_pkg.sv +++ b/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_pkg.sv @@ -7,4427 +7,69 @@ package scmi_reg_pkg; // Address widths within the block - parameter int BlockAw = 13; + parameter int BlockAw = 8; //////////////////////////// // Typedefs for registers // //////////////////////////// typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; + logic [31:0] q; } scmi_reg2hw_doorbell_c0_reg_t; typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; + logic [31:0] q; } scmi_reg2hw_completion_interrupt_c0_reg_t; - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c1_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c1_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c2_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c2_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c3_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c3_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c4_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c4_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c5_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c5_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c6_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c6_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c7_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c7_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c8_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c8_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c9_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c9_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c10_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c10_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c11_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c11_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c12_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c12_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c13_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c13_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c14_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c14_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c15_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c15_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c16_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c16_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c17_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c17_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c18_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c18_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c19_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c19_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c20_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c20_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c21_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c21_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c22_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c22_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c23_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c23_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c24_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c24_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c25_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c25_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c26_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c26_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c27_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c27_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c28_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c28_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c29_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c29_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c30_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c30_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c31_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c31_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c32_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c32_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c33_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c33_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c34_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c34_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c35_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c35_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c36_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c36_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c37_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c37_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c38_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c38_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c39_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c39_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c40_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c40_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c41_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c41_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c42_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c42_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c43_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c43_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c44_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c44_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c45_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c45_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c46_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c46_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c47_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c47_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c48_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c48_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c49_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c49_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c50_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c50_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c51_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c51_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c52_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c52_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c53_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c53_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c54_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c54_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c55_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c55_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c56_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c56_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c57_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c57_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c58_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c58_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c59_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c59_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c60_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c60_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c61_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c61_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c62_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c62_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c63_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c63_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c64_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c64_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c65_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c65_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c66_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c66_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c67_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c67_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c68_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c68_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c69_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c69_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c70_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c70_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c71_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c71_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c72_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c72_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c73_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c73_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c74_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c74_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c75_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c75_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c76_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c76_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c77_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c77_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c78_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c78_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c79_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c79_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c80_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c80_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c81_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c81_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c82_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c82_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c83_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c83_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c84_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c84_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c85_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c85_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c86_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c86_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c87_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c87_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c88_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c88_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c89_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c89_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c90_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c90_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c91_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c91_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c92_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c92_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c93_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c93_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c94_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c94_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c95_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c95_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c96_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c96_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c97_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c97_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c98_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c98_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c99_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c99_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c100_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c100_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c101_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c101_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c102_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c102_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c103_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c103_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c104_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c104_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c105_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c105_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c106_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c106_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c107_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c107_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c108_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c108_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c109_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c109_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c110_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c110_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c111_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c111_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c112_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c112_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c113_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c113_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c114_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c114_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c115_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c115_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c116_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c116_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c117_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c117_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c118_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c118_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c119_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c119_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c120_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c120_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c121_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c121_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c122_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c122_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c123_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c123_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c124_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c124_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c125_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c125_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c126_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c126_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c127_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c127_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c128_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c128_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c129_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c129_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c130_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c130_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c131_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c131_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c132_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c132_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c133_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c133_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c134_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c134_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c135_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c135_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c136_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c136_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c137_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c137_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c138_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c138_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c139_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c139_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c140_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c140_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c141_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c141_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c142_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c142_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c143_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c143_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c144_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c144_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c145_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c145_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_doorbell_c146_reg_t; - - typedef struct packed { - struct packed { - logic q; - } intr; - struct packed { - logic [30:0] q; - } preserve_mask; - } scmi_reg2hw_completion_interrupt_c146_reg_t; - // Register -> HW type typedef struct packed { - scmi_reg2hw_doorbell_c0_reg_t doorbell_c0; // [9407:9376] - scmi_reg2hw_completion_interrupt_c0_reg_t completion_interrupt_c0; // [9375:9344] - scmi_reg2hw_doorbell_c1_reg_t doorbell_c1; // [9343:9312] - scmi_reg2hw_completion_interrupt_c1_reg_t completion_interrupt_c1; // [9311:9280] - scmi_reg2hw_doorbell_c2_reg_t doorbell_c2; // [9279:9248] - scmi_reg2hw_completion_interrupt_c2_reg_t completion_interrupt_c2; // [9247:9216] - scmi_reg2hw_doorbell_c3_reg_t doorbell_c3; // [9215:9184] - scmi_reg2hw_completion_interrupt_c3_reg_t completion_interrupt_c3; // [9183:9152] - scmi_reg2hw_doorbell_c4_reg_t doorbell_c4; // [9151:9120] - scmi_reg2hw_completion_interrupt_c4_reg_t completion_interrupt_c4; // [9119:9088] - scmi_reg2hw_doorbell_c5_reg_t doorbell_c5; // [9087:9056] - scmi_reg2hw_completion_interrupt_c5_reg_t completion_interrupt_c5; // [9055:9024] - scmi_reg2hw_doorbell_c6_reg_t doorbell_c6; // [9023:8992] - scmi_reg2hw_completion_interrupt_c6_reg_t completion_interrupt_c6; // [8991:8960] - scmi_reg2hw_doorbell_c7_reg_t doorbell_c7; // [8959:8928] - scmi_reg2hw_completion_interrupt_c7_reg_t completion_interrupt_c7; // [8927:8896] - scmi_reg2hw_doorbell_c8_reg_t doorbell_c8; // [8895:8864] - scmi_reg2hw_completion_interrupt_c8_reg_t completion_interrupt_c8; // [8863:8832] - scmi_reg2hw_doorbell_c9_reg_t doorbell_c9; // [8831:8800] - scmi_reg2hw_completion_interrupt_c9_reg_t completion_interrupt_c9; // [8799:8768] - scmi_reg2hw_doorbell_c10_reg_t doorbell_c10; // [8767:8736] - scmi_reg2hw_completion_interrupt_c10_reg_t completion_interrupt_c10; // [8735:8704] - scmi_reg2hw_doorbell_c11_reg_t doorbell_c11; // [8703:8672] - scmi_reg2hw_completion_interrupt_c11_reg_t completion_interrupt_c11; // [8671:8640] - scmi_reg2hw_doorbell_c12_reg_t doorbell_c12; // [8639:8608] - scmi_reg2hw_completion_interrupt_c12_reg_t completion_interrupt_c12; // [8607:8576] - scmi_reg2hw_doorbell_c13_reg_t doorbell_c13; // [8575:8544] - scmi_reg2hw_completion_interrupt_c13_reg_t completion_interrupt_c13; // [8543:8512] - scmi_reg2hw_doorbell_c14_reg_t doorbell_c14; // [8511:8480] - scmi_reg2hw_completion_interrupt_c14_reg_t completion_interrupt_c14; // [8479:8448] - scmi_reg2hw_doorbell_c15_reg_t doorbell_c15; // [8447:8416] - scmi_reg2hw_completion_interrupt_c15_reg_t completion_interrupt_c15; // [8415:8384] - scmi_reg2hw_doorbell_c16_reg_t doorbell_c16; // [8383:8352] - scmi_reg2hw_completion_interrupt_c16_reg_t completion_interrupt_c16; // [8351:8320] - scmi_reg2hw_doorbell_c17_reg_t doorbell_c17; // [8319:8288] - scmi_reg2hw_completion_interrupt_c17_reg_t completion_interrupt_c17; // [8287:8256] - scmi_reg2hw_doorbell_c18_reg_t doorbell_c18; // [8255:8224] - scmi_reg2hw_completion_interrupt_c18_reg_t completion_interrupt_c18; // [8223:8192] - scmi_reg2hw_doorbell_c19_reg_t doorbell_c19; // [8191:8160] - scmi_reg2hw_completion_interrupt_c19_reg_t completion_interrupt_c19; // [8159:8128] - scmi_reg2hw_doorbell_c20_reg_t doorbell_c20; // [8127:8096] - scmi_reg2hw_completion_interrupt_c20_reg_t completion_interrupt_c20; // [8095:8064] - scmi_reg2hw_doorbell_c21_reg_t doorbell_c21; // [8063:8032] - scmi_reg2hw_completion_interrupt_c21_reg_t completion_interrupt_c21; // [8031:8000] - scmi_reg2hw_doorbell_c22_reg_t doorbell_c22; // [7999:7968] - scmi_reg2hw_completion_interrupt_c22_reg_t completion_interrupt_c22; // [7967:7936] - scmi_reg2hw_doorbell_c23_reg_t doorbell_c23; // [7935:7904] - scmi_reg2hw_completion_interrupt_c23_reg_t completion_interrupt_c23; // [7903:7872] - scmi_reg2hw_doorbell_c24_reg_t doorbell_c24; // [7871:7840] - scmi_reg2hw_completion_interrupt_c24_reg_t completion_interrupt_c24; // [7839:7808] - scmi_reg2hw_doorbell_c25_reg_t doorbell_c25; // [7807:7776] - scmi_reg2hw_completion_interrupt_c25_reg_t completion_interrupt_c25; // [7775:7744] - scmi_reg2hw_doorbell_c26_reg_t doorbell_c26; // [7743:7712] - scmi_reg2hw_completion_interrupt_c26_reg_t completion_interrupt_c26; // [7711:7680] - scmi_reg2hw_doorbell_c27_reg_t doorbell_c27; // [7679:7648] - scmi_reg2hw_completion_interrupt_c27_reg_t completion_interrupt_c27; // [7647:7616] - scmi_reg2hw_doorbell_c28_reg_t doorbell_c28; // [7615:7584] - scmi_reg2hw_completion_interrupt_c28_reg_t completion_interrupt_c28; // [7583:7552] - scmi_reg2hw_doorbell_c29_reg_t doorbell_c29; // [7551:7520] - scmi_reg2hw_completion_interrupt_c29_reg_t completion_interrupt_c29; // [7519:7488] - scmi_reg2hw_doorbell_c30_reg_t doorbell_c30; // [7487:7456] - scmi_reg2hw_completion_interrupt_c30_reg_t completion_interrupt_c30; // [7455:7424] - scmi_reg2hw_doorbell_c31_reg_t doorbell_c31; // [7423:7392] - scmi_reg2hw_completion_interrupt_c31_reg_t completion_interrupt_c31; // [7391:7360] - scmi_reg2hw_doorbell_c32_reg_t doorbell_c32; // [7359:7328] - scmi_reg2hw_completion_interrupt_c32_reg_t completion_interrupt_c32; // [7327:7296] - scmi_reg2hw_doorbell_c33_reg_t doorbell_c33; // [7295:7264] - scmi_reg2hw_completion_interrupt_c33_reg_t completion_interrupt_c33; // [7263:7232] - scmi_reg2hw_doorbell_c34_reg_t doorbell_c34; // [7231:7200] - scmi_reg2hw_completion_interrupt_c34_reg_t completion_interrupt_c34; // [7199:7168] - scmi_reg2hw_doorbell_c35_reg_t doorbell_c35; // [7167:7136] - scmi_reg2hw_completion_interrupt_c35_reg_t completion_interrupt_c35; // [7135:7104] - scmi_reg2hw_doorbell_c36_reg_t doorbell_c36; // [7103:7072] - scmi_reg2hw_completion_interrupt_c36_reg_t completion_interrupt_c36; // [7071:7040] - scmi_reg2hw_doorbell_c37_reg_t doorbell_c37; // [7039:7008] - scmi_reg2hw_completion_interrupt_c37_reg_t completion_interrupt_c37; // [7007:6976] - scmi_reg2hw_doorbell_c38_reg_t doorbell_c38; // [6975:6944] - scmi_reg2hw_completion_interrupt_c38_reg_t completion_interrupt_c38; // [6943:6912] - scmi_reg2hw_doorbell_c39_reg_t doorbell_c39; // [6911:6880] - scmi_reg2hw_completion_interrupt_c39_reg_t completion_interrupt_c39; // [6879:6848] - scmi_reg2hw_doorbell_c40_reg_t doorbell_c40; // [6847:6816] - scmi_reg2hw_completion_interrupt_c40_reg_t completion_interrupt_c40; // [6815:6784] - scmi_reg2hw_doorbell_c41_reg_t doorbell_c41; // [6783:6752] - scmi_reg2hw_completion_interrupt_c41_reg_t completion_interrupt_c41; // [6751:6720] - scmi_reg2hw_doorbell_c42_reg_t doorbell_c42; // [6719:6688] - scmi_reg2hw_completion_interrupt_c42_reg_t completion_interrupt_c42; // [6687:6656] - scmi_reg2hw_doorbell_c43_reg_t doorbell_c43; // [6655:6624] - scmi_reg2hw_completion_interrupt_c43_reg_t completion_interrupt_c43; // [6623:6592] - scmi_reg2hw_doorbell_c44_reg_t doorbell_c44; // [6591:6560] - scmi_reg2hw_completion_interrupt_c44_reg_t completion_interrupt_c44; // [6559:6528] - scmi_reg2hw_doorbell_c45_reg_t doorbell_c45; // [6527:6496] - scmi_reg2hw_completion_interrupt_c45_reg_t completion_interrupt_c45; // [6495:6464] - scmi_reg2hw_doorbell_c46_reg_t doorbell_c46; // [6463:6432] - scmi_reg2hw_completion_interrupt_c46_reg_t completion_interrupt_c46; // [6431:6400] - scmi_reg2hw_doorbell_c47_reg_t doorbell_c47; // [6399:6368] - scmi_reg2hw_completion_interrupt_c47_reg_t completion_interrupt_c47; // [6367:6336] - scmi_reg2hw_doorbell_c48_reg_t doorbell_c48; // [6335:6304] - scmi_reg2hw_completion_interrupt_c48_reg_t completion_interrupt_c48; // [6303:6272] - scmi_reg2hw_doorbell_c49_reg_t doorbell_c49; // [6271:6240] - scmi_reg2hw_completion_interrupt_c49_reg_t completion_interrupt_c49; // [6239:6208] - scmi_reg2hw_doorbell_c50_reg_t doorbell_c50; // [6207:6176] - scmi_reg2hw_completion_interrupt_c50_reg_t completion_interrupt_c50; // [6175:6144] - scmi_reg2hw_doorbell_c51_reg_t doorbell_c51; // [6143:6112] - scmi_reg2hw_completion_interrupt_c51_reg_t completion_interrupt_c51; // [6111:6080] - scmi_reg2hw_doorbell_c52_reg_t doorbell_c52; // [6079:6048] - scmi_reg2hw_completion_interrupt_c52_reg_t completion_interrupt_c52; // [6047:6016] - scmi_reg2hw_doorbell_c53_reg_t doorbell_c53; // [6015:5984] - scmi_reg2hw_completion_interrupt_c53_reg_t completion_interrupt_c53; // [5983:5952] - scmi_reg2hw_doorbell_c54_reg_t doorbell_c54; // [5951:5920] - scmi_reg2hw_completion_interrupt_c54_reg_t completion_interrupt_c54; // [5919:5888] - scmi_reg2hw_doorbell_c55_reg_t doorbell_c55; // [5887:5856] - scmi_reg2hw_completion_interrupt_c55_reg_t completion_interrupt_c55; // [5855:5824] - scmi_reg2hw_doorbell_c56_reg_t doorbell_c56; // [5823:5792] - scmi_reg2hw_completion_interrupt_c56_reg_t completion_interrupt_c56; // [5791:5760] - scmi_reg2hw_doorbell_c57_reg_t doorbell_c57; // [5759:5728] - scmi_reg2hw_completion_interrupt_c57_reg_t completion_interrupt_c57; // [5727:5696] - scmi_reg2hw_doorbell_c58_reg_t doorbell_c58; // [5695:5664] - scmi_reg2hw_completion_interrupt_c58_reg_t completion_interrupt_c58; // [5663:5632] - scmi_reg2hw_doorbell_c59_reg_t doorbell_c59; // [5631:5600] - scmi_reg2hw_completion_interrupt_c59_reg_t completion_interrupt_c59; // [5599:5568] - scmi_reg2hw_doorbell_c60_reg_t doorbell_c60; // [5567:5536] - scmi_reg2hw_completion_interrupt_c60_reg_t completion_interrupt_c60; // [5535:5504] - scmi_reg2hw_doorbell_c61_reg_t doorbell_c61; // [5503:5472] - scmi_reg2hw_completion_interrupt_c61_reg_t completion_interrupt_c61; // [5471:5440] - scmi_reg2hw_doorbell_c62_reg_t doorbell_c62; // [5439:5408] - scmi_reg2hw_completion_interrupt_c62_reg_t completion_interrupt_c62; // [5407:5376] - scmi_reg2hw_doorbell_c63_reg_t doorbell_c63; // [5375:5344] - scmi_reg2hw_completion_interrupt_c63_reg_t completion_interrupt_c63; // [5343:5312] - scmi_reg2hw_doorbell_c64_reg_t doorbell_c64; // [5311:5280] - scmi_reg2hw_completion_interrupt_c64_reg_t completion_interrupt_c64; // [5279:5248] - scmi_reg2hw_doorbell_c65_reg_t doorbell_c65; // [5247:5216] - scmi_reg2hw_completion_interrupt_c65_reg_t completion_interrupt_c65; // [5215:5184] - scmi_reg2hw_doorbell_c66_reg_t doorbell_c66; // [5183:5152] - scmi_reg2hw_completion_interrupt_c66_reg_t completion_interrupt_c66; // [5151:5120] - scmi_reg2hw_doorbell_c67_reg_t doorbell_c67; // [5119:5088] - scmi_reg2hw_completion_interrupt_c67_reg_t completion_interrupt_c67; // [5087:5056] - scmi_reg2hw_doorbell_c68_reg_t doorbell_c68; // [5055:5024] - scmi_reg2hw_completion_interrupt_c68_reg_t completion_interrupt_c68; // [5023:4992] - scmi_reg2hw_doorbell_c69_reg_t doorbell_c69; // [4991:4960] - scmi_reg2hw_completion_interrupt_c69_reg_t completion_interrupt_c69; // [4959:4928] - scmi_reg2hw_doorbell_c70_reg_t doorbell_c70; // [4927:4896] - scmi_reg2hw_completion_interrupt_c70_reg_t completion_interrupt_c70; // [4895:4864] - scmi_reg2hw_doorbell_c71_reg_t doorbell_c71; // [4863:4832] - scmi_reg2hw_completion_interrupt_c71_reg_t completion_interrupt_c71; // [4831:4800] - scmi_reg2hw_doorbell_c72_reg_t doorbell_c72; // [4799:4768] - scmi_reg2hw_completion_interrupt_c72_reg_t completion_interrupt_c72; // [4767:4736] - scmi_reg2hw_doorbell_c73_reg_t doorbell_c73; // [4735:4704] - scmi_reg2hw_completion_interrupt_c73_reg_t completion_interrupt_c73; // [4703:4672] - scmi_reg2hw_doorbell_c74_reg_t doorbell_c74; // [4671:4640] - scmi_reg2hw_completion_interrupt_c74_reg_t completion_interrupt_c74; // [4639:4608] - scmi_reg2hw_doorbell_c75_reg_t doorbell_c75; // [4607:4576] - scmi_reg2hw_completion_interrupt_c75_reg_t completion_interrupt_c75; // [4575:4544] - scmi_reg2hw_doorbell_c76_reg_t doorbell_c76; // [4543:4512] - scmi_reg2hw_completion_interrupt_c76_reg_t completion_interrupt_c76; // [4511:4480] - scmi_reg2hw_doorbell_c77_reg_t doorbell_c77; // [4479:4448] - scmi_reg2hw_completion_interrupt_c77_reg_t completion_interrupt_c77; // [4447:4416] - scmi_reg2hw_doorbell_c78_reg_t doorbell_c78; // [4415:4384] - scmi_reg2hw_completion_interrupt_c78_reg_t completion_interrupt_c78; // [4383:4352] - scmi_reg2hw_doorbell_c79_reg_t doorbell_c79; // [4351:4320] - scmi_reg2hw_completion_interrupt_c79_reg_t completion_interrupt_c79; // [4319:4288] - scmi_reg2hw_doorbell_c80_reg_t doorbell_c80; // [4287:4256] - scmi_reg2hw_completion_interrupt_c80_reg_t completion_interrupt_c80; // [4255:4224] - scmi_reg2hw_doorbell_c81_reg_t doorbell_c81; // [4223:4192] - scmi_reg2hw_completion_interrupt_c81_reg_t completion_interrupt_c81; // [4191:4160] - scmi_reg2hw_doorbell_c82_reg_t doorbell_c82; // [4159:4128] - scmi_reg2hw_completion_interrupt_c82_reg_t completion_interrupt_c82; // [4127:4096] - scmi_reg2hw_doorbell_c83_reg_t doorbell_c83; // [4095:4064] - scmi_reg2hw_completion_interrupt_c83_reg_t completion_interrupt_c83; // [4063:4032] - scmi_reg2hw_doorbell_c84_reg_t doorbell_c84; // [4031:4000] - scmi_reg2hw_completion_interrupt_c84_reg_t completion_interrupt_c84; // [3999:3968] - scmi_reg2hw_doorbell_c85_reg_t doorbell_c85; // [3967:3936] - scmi_reg2hw_completion_interrupt_c85_reg_t completion_interrupt_c85; // [3935:3904] - scmi_reg2hw_doorbell_c86_reg_t doorbell_c86; // [3903:3872] - scmi_reg2hw_completion_interrupt_c86_reg_t completion_interrupt_c86; // [3871:3840] - scmi_reg2hw_doorbell_c87_reg_t doorbell_c87; // [3839:3808] - scmi_reg2hw_completion_interrupt_c87_reg_t completion_interrupt_c87; // [3807:3776] - scmi_reg2hw_doorbell_c88_reg_t doorbell_c88; // [3775:3744] - scmi_reg2hw_completion_interrupt_c88_reg_t completion_interrupt_c88; // [3743:3712] - scmi_reg2hw_doorbell_c89_reg_t doorbell_c89; // [3711:3680] - scmi_reg2hw_completion_interrupt_c89_reg_t completion_interrupt_c89; // [3679:3648] - scmi_reg2hw_doorbell_c90_reg_t doorbell_c90; // [3647:3616] - scmi_reg2hw_completion_interrupt_c90_reg_t completion_interrupt_c90; // [3615:3584] - scmi_reg2hw_doorbell_c91_reg_t doorbell_c91; // [3583:3552] - scmi_reg2hw_completion_interrupt_c91_reg_t completion_interrupt_c91; // [3551:3520] - scmi_reg2hw_doorbell_c92_reg_t doorbell_c92; // [3519:3488] - scmi_reg2hw_completion_interrupt_c92_reg_t completion_interrupt_c92; // [3487:3456] - scmi_reg2hw_doorbell_c93_reg_t doorbell_c93; // [3455:3424] - scmi_reg2hw_completion_interrupt_c93_reg_t completion_interrupt_c93; // [3423:3392] - scmi_reg2hw_doorbell_c94_reg_t doorbell_c94; // [3391:3360] - scmi_reg2hw_completion_interrupt_c94_reg_t completion_interrupt_c94; // [3359:3328] - scmi_reg2hw_doorbell_c95_reg_t doorbell_c95; // [3327:3296] - scmi_reg2hw_completion_interrupt_c95_reg_t completion_interrupt_c95; // [3295:3264] - scmi_reg2hw_doorbell_c96_reg_t doorbell_c96; // [3263:3232] - scmi_reg2hw_completion_interrupt_c96_reg_t completion_interrupt_c96; // [3231:3200] - scmi_reg2hw_doorbell_c97_reg_t doorbell_c97; // [3199:3168] - scmi_reg2hw_completion_interrupt_c97_reg_t completion_interrupt_c97; // [3167:3136] - scmi_reg2hw_doorbell_c98_reg_t doorbell_c98; // [3135:3104] - scmi_reg2hw_completion_interrupt_c98_reg_t completion_interrupt_c98; // [3103:3072] - scmi_reg2hw_doorbell_c99_reg_t doorbell_c99; // [3071:3040] - scmi_reg2hw_completion_interrupt_c99_reg_t completion_interrupt_c99; // [3039:3008] - scmi_reg2hw_doorbell_c100_reg_t doorbell_c100; // [3007:2976] - scmi_reg2hw_completion_interrupt_c100_reg_t completion_interrupt_c100; // [2975:2944] - scmi_reg2hw_doorbell_c101_reg_t doorbell_c101; // [2943:2912] - scmi_reg2hw_completion_interrupt_c101_reg_t completion_interrupt_c101; // [2911:2880] - scmi_reg2hw_doorbell_c102_reg_t doorbell_c102; // [2879:2848] - scmi_reg2hw_completion_interrupt_c102_reg_t completion_interrupt_c102; // [2847:2816] - scmi_reg2hw_doorbell_c103_reg_t doorbell_c103; // [2815:2784] - scmi_reg2hw_completion_interrupt_c103_reg_t completion_interrupt_c103; // [2783:2752] - scmi_reg2hw_doorbell_c104_reg_t doorbell_c104; // [2751:2720] - scmi_reg2hw_completion_interrupt_c104_reg_t completion_interrupt_c104; // [2719:2688] - scmi_reg2hw_doorbell_c105_reg_t doorbell_c105; // [2687:2656] - scmi_reg2hw_completion_interrupt_c105_reg_t completion_interrupt_c105; // [2655:2624] - scmi_reg2hw_doorbell_c106_reg_t doorbell_c106; // [2623:2592] - scmi_reg2hw_completion_interrupt_c106_reg_t completion_interrupt_c106; // [2591:2560] - scmi_reg2hw_doorbell_c107_reg_t doorbell_c107; // [2559:2528] - scmi_reg2hw_completion_interrupt_c107_reg_t completion_interrupt_c107; // [2527:2496] - scmi_reg2hw_doorbell_c108_reg_t doorbell_c108; // [2495:2464] - scmi_reg2hw_completion_interrupt_c108_reg_t completion_interrupt_c108; // [2463:2432] - scmi_reg2hw_doorbell_c109_reg_t doorbell_c109; // [2431:2400] - scmi_reg2hw_completion_interrupt_c109_reg_t completion_interrupt_c109; // [2399:2368] - scmi_reg2hw_doorbell_c110_reg_t doorbell_c110; // [2367:2336] - scmi_reg2hw_completion_interrupt_c110_reg_t completion_interrupt_c110; // [2335:2304] - scmi_reg2hw_doorbell_c111_reg_t doorbell_c111; // [2303:2272] - scmi_reg2hw_completion_interrupt_c111_reg_t completion_interrupt_c111; // [2271:2240] - scmi_reg2hw_doorbell_c112_reg_t doorbell_c112; // [2239:2208] - scmi_reg2hw_completion_interrupt_c112_reg_t completion_interrupt_c112; // [2207:2176] - scmi_reg2hw_doorbell_c113_reg_t doorbell_c113; // [2175:2144] - scmi_reg2hw_completion_interrupt_c113_reg_t completion_interrupt_c113; // [2143:2112] - scmi_reg2hw_doorbell_c114_reg_t doorbell_c114; // [2111:2080] - scmi_reg2hw_completion_interrupt_c114_reg_t completion_interrupt_c114; // [2079:2048] - scmi_reg2hw_doorbell_c115_reg_t doorbell_c115; // [2047:2016] - scmi_reg2hw_completion_interrupt_c115_reg_t completion_interrupt_c115; // [2015:1984] - scmi_reg2hw_doorbell_c116_reg_t doorbell_c116; // [1983:1952] - scmi_reg2hw_completion_interrupt_c116_reg_t completion_interrupt_c116; // [1951:1920] - scmi_reg2hw_doorbell_c117_reg_t doorbell_c117; // [1919:1888] - scmi_reg2hw_completion_interrupt_c117_reg_t completion_interrupt_c117; // [1887:1856] - scmi_reg2hw_doorbell_c118_reg_t doorbell_c118; // [1855:1824] - scmi_reg2hw_completion_interrupt_c118_reg_t completion_interrupt_c118; // [1823:1792] - scmi_reg2hw_doorbell_c119_reg_t doorbell_c119; // [1791:1760] - scmi_reg2hw_completion_interrupt_c119_reg_t completion_interrupt_c119; // [1759:1728] - scmi_reg2hw_doorbell_c120_reg_t doorbell_c120; // [1727:1696] - scmi_reg2hw_completion_interrupt_c120_reg_t completion_interrupt_c120; // [1695:1664] - scmi_reg2hw_doorbell_c121_reg_t doorbell_c121; // [1663:1632] - scmi_reg2hw_completion_interrupt_c121_reg_t completion_interrupt_c121; // [1631:1600] - scmi_reg2hw_doorbell_c122_reg_t doorbell_c122; // [1599:1568] - scmi_reg2hw_completion_interrupt_c122_reg_t completion_interrupt_c122; // [1567:1536] - scmi_reg2hw_doorbell_c123_reg_t doorbell_c123; // [1535:1504] - scmi_reg2hw_completion_interrupt_c123_reg_t completion_interrupt_c123; // [1503:1472] - scmi_reg2hw_doorbell_c124_reg_t doorbell_c124; // [1471:1440] - scmi_reg2hw_completion_interrupt_c124_reg_t completion_interrupt_c124; // [1439:1408] - scmi_reg2hw_doorbell_c125_reg_t doorbell_c125; // [1407:1376] - scmi_reg2hw_completion_interrupt_c125_reg_t completion_interrupt_c125; // [1375:1344] - scmi_reg2hw_doorbell_c126_reg_t doorbell_c126; // [1343:1312] - scmi_reg2hw_completion_interrupt_c126_reg_t completion_interrupt_c126; // [1311:1280] - scmi_reg2hw_doorbell_c127_reg_t doorbell_c127; // [1279:1248] - scmi_reg2hw_completion_interrupt_c127_reg_t completion_interrupt_c127; // [1247:1216] - scmi_reg2hw_doorbell_c128_reg_t doorbell_c128; // [1215:1184] - scmi_reg2hw_completion_interrupt_c128_reg_t completion_interrupt_c128; // [1183:1152] - scmi_reg2hw_doorbell_c129_reg_t doorbell_c129; // [1151:1120] - scmi_reg2hw_completion_interrupt_c129_reg_t completion_interrupt_c129; // [1119:1088] - scmi_reg2hw_doorbell_c130_reg_t doorbell_c130; // [1087:1056] - scmi_reg2hw_completion_interrupt_c130_reg_t completion_interrupt_c130; // [1055:1024] - scmi_reg2hw_doorbell_c131_reg_t doorbell_c131; // [1023:992] - scmi_reg2hw_completion_interrupt_c131_reg_t completion_interrupt_c131; // [991:960] - scmi_reg2hw_doorbell_c132_reg_t doorbell_c132; // [959:928] - scmi_reg2hw_completion_interrupt_c132_reg_t completion_interrupt_c132; // [927:896] - scmi_reg2hw_doorbell_c133_reg_t doorbell_c133; // [895:864] - scmi_reg2hw_completion_interrupt_c133_reg_t completion_interrupt_c133; // [863:832] - scmi_reg2hw_doorbell_c134_reg_t doorbell_c134; // [831:800] - scmi_reg2hw_completion_interrupt_c134_reg_t completion_interrupt_c134; // [799:768] - scmi_reg2hw_doorbell_c135_reg_t doorbell_c135; // [767:736] - scmi_reg2hw_completion_interrupt_c135_reg_t completion_interrupt_c135; // [735:704] - scmi_reg2hw_doorbell_c136_reg_t doorbell_c136; // [703:672] - scmi_reg2hw_completion_interrupt_c136_reg_t completion_interrupt_c136; // [671:640] - scmi_reg2hw_doorbell_c137_reg_t doorbell_c137; // [639:608] - scmi_reg2hw_completion_interrupt_c137_reg_t completion_interrupt_c137; // [607:576] - scmi_reg2hw_doorbell_c138_reg_t doorbell_c138; // [575:544] - scmi_reg2hw_completion_interrupt_c138_reg_t completion_interrupt_c138; // [543:512] - scmi_reg2hw_doorbell_c139_reg_t doorbell_c139; // [511:480] - scmi_reg2hw_completion_interrupt_c139_reg_t completion_interrupt_c139; // [479:448] - scmi_reg2hw_doorbell_c140_reg_t doorbell_c140; // [447:416] - scmi_reg2hw_completion_interrupt_c140_reg_t completion_interrupt_c140; // [415:384] - scmi_reg2hw_doorbell_c141_reg_t doorbell_c141; // [383:352] - scmi_reg2hw_completion_interrupt_c141_reg_t completion_interrupt_c141; // [351:320] - scmi_reg2hw_doorbell_c142_reg_t doorbell_c142; // [319:288] - scmi_reg2hw_completion_interrupt_c142_reg_t completion_interrupt_c142; // [287:256] - scmi_reg2hw_doorbell_c143_reg_t doorbell_c143; // [255:224] - scmi_reg2hw_completion_interrupt_c143_reg_t completion_interrupt_c143; // [223:192] - scmi_reg2hw_doorbell_c144_reg_t doorbell_c144; // [191:160] - scmi_reg2hw_completion_interrupt_c144_reg_t completion_interrupt_c144; // [159:128] - scmi_reg2hw_doorbell_c145_reg_t doorbell_c145; // [127:96] - scmi_reg2hw_completion_interrupt_c145_reg_t completion_interrupt_c145; // [95:64] - scmi_reg2hw_doorbell_c146_reg_t doorbell_c146; // [63:32] - scmi_reg2hw_completion_interrupt_c146_reg_t completion_interrupt_c146; // [31:0] + scmi_reg2hw_doorbell_c0_reg_t doorbell_c0; // [63:32] + scmi_reg2hw_completion_interrupt_c0_reg_t completion_interrupt_c0; // [31:0] } scmi_reg2hw_t; // Register offsets - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C0_OFFSET = 13'h 0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C0_OFFSET = 13'h 4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C0_OFFSET = 13'h 8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C0_OFFSET = 13'h c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C0_OFFSET = 13'h 10; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C0_OFFSET = 13'h 14; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C0_OFFSET = 13'h 18; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C0_OFFSET = 13'h 1c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C0_OFFSET = 13'h 20; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C0_OFFSET = 13'h 24; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C1_OFFSET = 13'h 28; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C1_OFFSET = 13'h 2c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C1_OFFSET = 13'h 30; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C1_OFFSET = 13'h 34; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C1_OFFSET = 13'h 38; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C1_OFFSET = 13'h 3c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C1_OFFSET = 13'h 40; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C1_OFFSET = 13'h 44; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C1_OFFSET = 13'h 48; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C1_OFFSET = 13'h 4c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C2_OFFSET = 13'h 50; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C2_OFFSET = 13'h 54; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C2_OFFSET = 13'h 58; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C2_OFFSET = 13'h 5c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C2_OFFSET = 13'h 60; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C2_OFFSET = 13'h 64; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C2_OFFSET = 13'h 68; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C2_OFFSET = 13'h 6c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C2_OFFSET = 13'h 70; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C2_OFFSET = 13'h 74; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C3_OFFSET = 13'h 78; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C3_OFFSET = 13'h 7c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C3_OFFSET = 13'h 80; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C3_OFFSET = 13'h 84; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C3_OFFSET = 13'h 88; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C3_OFFSET = 13'h 8c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C3_OFFSET = 13'h 90; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C3_OFFSET = 13'h 94; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C3_OFFSET = 13'h 98; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C3_OFFSET = 13'h 9c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C4_OFFSET = 13'h a0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C4_OFFSET = 13'h a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C4_OFFSET = 13'h a8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C4_OFFSET = 13'h ac; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C4_OFFSET = 13'h b0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C4_OFFSET = 13'h b4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C4_OFFSET = 13'h b8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C4_OFFSET = 13'h bc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C4_OFFSET = 13'h c0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C4_OFFSET = 13'h c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C5_OFFSET = 13'h c8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C5_OFFSET = 13'h cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C5_OFFSET = 13'h d0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C5_OFFSET = 13'h d4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C5_OFFSET = 13'h d8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C5_OFFSET = 13'h dc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C5_OFFSET = 13'h e0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C5_OFFSET = 13'h e4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C5_OFFSET = 13'h e8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C5_OFFSET = 13'h ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C6_OFFSET = 13'h f0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C6_OFFSET = 13'h f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C6_OFFSET = 13'h f8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C6_OFFSET = 13'h fc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C6_OFFSET = 13'h 100; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C6_OFFSET = 13'h 104; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C6_OFFSET = 13'h 108; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C6_OFFSET = 13'h 10c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C6_OFFSET = 13'h 110; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C6_OFFSET = 13'h 114; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C7_OFFSET = 13'h 118; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C7_OFFSET = 13'h 11c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C7_OFFSET = 13'h 120; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C7_OFFSET = 13'h 124; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C7_OFFSET = 13'h 128; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C7_OFFSET = 13'h 12c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C7_OFFSET = 13'h 130; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C7_OFFSET = 13'h 134; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C7_OFFSET = 13'h 138; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C7_OFFSET = 13'h 13c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C8_OFFSET = 13'h 140; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C8_OFFSET = 13'h 144; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C8_OFFSET = 13'h 148; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C8_OFFSET = 13'h 14c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C8_OFFSET = 13'h 150; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C8_OFFSET = 13'h 154; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C8_OFFSET = 13'h 158; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C8_OFFSET = 13'h 15c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C8_OFFSET = 13'h 160; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C8_OFFSET = 13'h 164; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C9_OFFSET = 13'h 168; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C9_OFFSET = 13'h 16c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C9_OFFSET = 13'h 170; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C9_OFFSET = 13'h 174; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C9_OFFSET = 13'h 178; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C9_OFFSET = 13'h 17c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C9_OFFSET = 13'h 180; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C9_OFFSET = 13'h 184; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C9_OFFSET = 13'h 188; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C9_OFFSET = 13'h 18c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C10_OFFSET = 13'h 190; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C10_OFFSET = 13'h 194; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C10_OFFSET = 13'h 198; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C10_OFFSET = 13'h 19c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C10_OFFSET = 13'h 1a0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C10_OFFSET = 13'h 1a4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C10_OFFSET = 13'h 1a8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C10_OFFSET = 13'h 1ac; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C10_OFFSET = 13'h 1b0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C10_OFFSET = 13'h 1b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C11_OFFSET = 13'h 1b8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C11_OFFSET = 13'h 1bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C11_OFFSET = 13'h 1c0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C11_OFFSET = 13'h 1c4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C11_OFFSET = 13'h 1c8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C11_OFFSET = 13'h 1cc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C11_OFFSET = 13'h 1d0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C11_OFFSET = 13'h 1d4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C11_OFFSET = 13'h 1d8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C11_OFFSET = 13'h 1dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C12_OFFSET = 13'h 1e0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C12_OFFSET = 13'h 1e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C12_OFFSET = 13'h 1e8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C12_OFFSET = 13'h 1ec; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C12_OFFSET = 13'h 1f0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C12_OFFSET = 13'h 1f4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C12_OFFSET = 13'h 1f8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C12_OFFSET = 13'h 1fc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C12_OFFSET = 13'h 200; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C12_OFFSET = 13'h 204; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C13_OFFSET = 13'h 208; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C13_OFFSET = 13'h 20c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C13_OFFSET = 13'h 210; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C13_OFFSET = 13'h 214; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C13_OFFSET = 13'h 218; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C13_OFFSET = 13'h 21c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C13_OFFSET = 13'h 220; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C13_OFFSET = 13'h 224; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C13_OFFSET = 13'h 228; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C13_OFFSET = 13'h 22c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C14_OFFSET = 13'h 230; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C14_OFFSET = 13'h 234; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C14_OFFSET = 13'h 238; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C14_OFFSET = 13'h 23c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C14_OFFSET = 13'h 240; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C14_OFFSET = 13'h 244; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C14_OFFSET = 13'h 248; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C14_OFFSET = 13'h 24c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C14_OFFSET = 13'h 250; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C14_OFFSET = 13'h 254; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C15_OFFSET = 13'h 258; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C15_OFFSET = 13'h 25c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C15_OFFSET = 13'h 260; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C15_OFFSET = 13'h 264; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C15_OFFSET = 13'h 268; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C15_OFFSET = 13'h 26c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C15_OFFSET = 13'h 270; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C15_OFFSET = 13'h 274; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C15_OFFSET = 13'h 278; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C15_OFFSET = 13'h 27c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C16_OFFSET = 13'h 280; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C16_OFFSET = 13'h 284; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C16_OFFSET = 13'h 288; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C16_OFFSET = 13'h 28c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C16_OFFSET = 13'h 290; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C16_OFFSET = 13'h 294; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C16_OFFSET = 13'h 298; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C16_OFFSET = 13'h 29c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C16_OFFSET = 13'h 2a0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C16_OFFSET = 13'h 2a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C17_OFFSET = 13'h 2a8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C17_OFFSET = 13'h 2ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C17_OFFSET = 13'h 2b0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C17_OFFSET = 13'h 2b4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C17_OFFSET = 13'h 2b8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C17_OFFSET = 13'h 2bc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C17_OFFSET = 13'h 2c0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C17_OFFSET = 13'h 2c4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C17_OFFSET = 13'h 2c8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C17_OFFSET = 13'h 2cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C18_OFFSET = 13'h 2d0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C18_OFFSET = 13'h 2d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C18_OFFSET = 13'h 2d8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C18_OFFSET = 13'h 2dc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C18_OFFSET = 13'h 2e0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C18_OFFSET = 13'h 2e4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C18_OFFSET = 13'h 2e8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C18_OFFSET = 13'h 2ec; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C18_OFFSET = 13'h 2f0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C18_OFFSET = 13'h 2f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C19_OFFSET = 13'h 2f8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C19_OFFSET = 13'h 2fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C19_OFFSET = 13'h 300; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C19_OFFSET = 13'h 304; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C19_OFFSET = 13'h 308; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C19_OFFSET = 13'h 30c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C19_OFFSET = 13'h 310; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C19_OFFSET = 13'h 314; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C19_OFFSET = 13'h 318; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C19_OFFSET = 13'h 31c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C20_OFFSET = 13'h 320; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C20_OFFSET = 13'h 324; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C20_OFFSET = 13'h 328; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C20_OFFSET = 13'h 32c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C20_OFFSET = 13'h 330; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C20_OFFSET = 13'h 334; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C20_OFFSET = 13'h 338; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C20_OFFSET = 13'h 33c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C20_OFFSET = 13'h 340; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C20_OFFSET = 13'h 344; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C21_OFFSET = 13'h 348; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C21_OFFSET = 13'h 34c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C21_OFFSET = 13'h 350; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C21_OFFSET = 13'h 354; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C21_OFFSET = 13'h 358; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C21_OFFSET = 13'h 35c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C21_OFFSET = 13'h 360; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C21_OFFSET = 13'h 364; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C21_OFFSET = 13'h 368; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C21_OFFSET = 13'h 36c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C22_OFFSET = 13'h 370; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C22_OFFSET = 13'h 374; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C22_OFFSET = 13'h 378; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C22_OFFSET = 13'h 37c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C22_OFFSET = 13'h 380; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C22_OFFSET = 13'h 384; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C22_OFFSET = 13'h 388; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C22_OFFSET = 13'h 38c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C22_OFFSET = 13'h 390; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C22_OFFSET = 13'h 394; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C23_OFFSET = 13'h 398; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C23_OFFSET = 13'h 39c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C23_OFFSET = 13'h 3a0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C23_OFFSET = 13'h 3a4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C23_OFFSET = 13'h 3a8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C23_OFFSET = 13'h 3ac; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C23_OFFSET = 13'h 3b0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C23_OFFSET = 13'h 3b4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C23_OFFSET = 13'h 3b8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C23_OFFSET = 13'h 3bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C24_OFFSET = 13'h 3c0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C24_OFFSET = 13'h 3c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C24_OFFSET = 13'h 3c8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C24_OFFSET = 13'h 3cc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C24_OFFSET = 13'h 3d0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C24_OFFSET = 13'h 3d4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C24_OFFSET = 13'h 3d8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C24_OFFSET = 13'h 3dc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C24_OFFSET = 13'h 3e0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C24_OFFSET = 13'h 3e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C25_OFFSET = 13'h 3e8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C25_OFFSET = 13'h 3ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C25_OFFSET = 13'h 3f0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C25_OFFSET = 13'h 3f4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C25_OFFSET = 13'h 3f8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C25_OFFSET = 13'h 3fc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C25_OFFSET = 13'h 400; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C25_OFFSET = 13'h 404; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C25_OFFSET = 13'h 408; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C25_OFFSET = 13'h 40c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C26_OFFSET = 13'h 410; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C26_OFFSET = 13'h 414; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C26_OFFSET = 13'h 418; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C26_OFFSET = 13'h 41c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C26_OFFSET = 13'h 420; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C26_OFFSET = 13'h 424; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C26_OFFSET = 13'h 428; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C26_OFFSET = 13'h 42c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C26_OFFSET = 13'h 430; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C26_OFFSET = 13'h 434; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C27_OFFSET = 13'h 438; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C27_OFFSET = 13'h 43c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C27_OFFSET = 13'h 440; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C27_OFFSET = 13'h 444; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C27_OFFSET = 13'h 448; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C27_OFFSET = 13'h 44c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C27_OFFSET = 13'h 450; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C27_OFFSET = 13'h 454; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C27_OFFSET = 13'h 458; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C27_OFFSET = 13'h 45c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C28_OFFSET = 13'h 460; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C28_OFFSET = 13'h 464; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C28_OFFSET = 13'h 468; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C28_OFFSET = 13'h 46c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C28_OFFSET = 13'h 470; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C28_OFFSET = 13'h 474; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C28_OFFSET = 13'h 478; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C28_OFFSET = 13'h 47c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C28_OFFSET = 13'h 480; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C28_OFFSET = 13'h 484; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C29_OFFSET = 13'h 488; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C29_OFFSET = 13'h 48c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C29_OFFSET = 13'h 490; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C29_OFFSET = 13'h 494; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C29_OFFSET = 13'h 498; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C29_OFFSET = 13'h 49c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C29_OFFSET = 13'h 4a0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C29_OFFSET = 13'h 4a4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C29_OFFSET = 13'h 4a8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C29_OFFSET = 13'h 4ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C30_OFFSET = 13'h 4b0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C30_OFFSET = 13'h 4b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C30_OFFSET = 13'h 4b8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C30_OFFSET = 13'h 4bc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C30_OFFSET = 13'h 4c0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C30_OFFSET = 13'h 4c4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C30_OFFSET = 13'h 4c8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C30_OFFSET = 13'h 4cc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C30_OFFSET = 13'h 4d0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C30_OFFSET = 13'h 4d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C31_OFFSET = 13'h 4d8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C31_OFFSET = 13'h 4dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C31_OFFSET = 13'h 4e0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C31_OFFSET = 13'h 4e4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C31_OFFSET = 13'h 4e8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C31_OFFSET = 13'h 4ec; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C31_OFFSET = 13'h 4f0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C31_OFFSET = 13'h 4f4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C31_OFFSET = 13'h 4f8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C31_OFFSET = 13'h 4fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C32_OFFSET = 13'h 500; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C32_OFFSET = 13'h 504; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C32_OFFSET = 13'h 508; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C32_OFFSET = 13'h 50c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C32_OFFSET = 13'h 510; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C32_OFFSET = 13'h 514; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C32_OFFSET = 13'h 518; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C32_OFFSET = 13'h 51c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C32_OFFSET = 13'h 520; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C32_OFFSET = 13'h 524; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C33_OFFSET = 13'h 528; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C33_OFFSET = 13'h 52c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C33_OFFSET = 13'h 530; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C33_OFFSET = 13'h 534; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C33_OFFSET = 13'h 538; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C33_OFFSET = 13'h 53c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C33_OFFSET = 13'h 540; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C33_OFFSET = 13'h 544; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C33_OFFSET = 13'h 548; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C33_OFFSET = 13'h 54c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C34_OFFSET = 13'h 550; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C34_OFFSET = 13'h 554; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C34_OFFSET = 13'h 558; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C34_OFFSET = 13'h 55c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C34_OFFSET = 13'h 560; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C34_OFFSET = 13'h 564; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C34_OFFSET = 13'h 568; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C34_OFFSET = 13'h 56c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C34_OFFSET = 13'h 570; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C34_OFFSET = 13'h 574; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C35_OFFSET = 13'h 578; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C35_OFFSET = 13'h 57c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C35_OFFSET = 13'h 580; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C35_OFFSET = 13'h 584; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C35_OFFSET = 13'h 588; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C35_OFFSET = 13'h 58c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C35_OFFSET = 13'h 590; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C35_OFFSET = 13'h 594; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C35_OFFSET = 13'h 598; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C35_OFFSET = 13'h 59c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C36_OFFSET = 13'h 5a0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C36_OFFSET = 13'h 5a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C36_OFFSET = 13'h 5a8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C36_OFFSET = 13'h 5ac; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C36_OFFSET = 13'h 5b0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C36_OFFSET = 13'h 5b4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C36_OFFSET = 13'h 5b8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C36_OFFSET = 13'h 5bc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C36_OFFSET = 13'h 5c0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C36_OFFSET = 13'h 5c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C37_OFFSET = 13'h 5c8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C37_OFFSET = 13'h 5cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C37_OFFSET = 13'h 5d0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C37_OFFSET = 13'h 5d4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C37_OFFSET = 13'h 5d8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C37_OFFSET = 13'h 5dc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C37_OFFSET = 13'h 5e0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C37_OFFSET = 13'h 5e4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C37_OFFSET = 13'h 5e8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C37_OFFSET = 13'h 5ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C38_OFFSET = 13'h 5f0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C38_OFFSET = 13'h 5f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C38_OFFSET = 13'h 5f8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C38_OFFSET = 13'h 5fc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C38_OFFSET = 13'h 600; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C38_OFFSET = 13'h 604; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C38_OFFSET = 13'h 608; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C38_OFFSET = 13'h 60c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C38_OFFSET = 13'h 610; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C38_OFFSET = 13'h 614; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C39_OFFSET = 13'h 618; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C39_OFFSET = 13'h 61c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C39_OFFSET = 13'h 620; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C39_OFFSET = 13'h 624; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C39_OFFSET = 13'h 628; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C39_OFFSET = 13'h 62c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C39_OFFSET = 13'h 630; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C39_OFFSET = 13'h 634; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C39_OFFSET = 13'h 638; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C39_OFFSET = 13'h 63c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C40_OFFSET = 13'h 640; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C40_OFFSET = 13'h 644; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C40_OFFSET = 13'h 648; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C40_OFFSET = 13'h 64c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C40_OFFSET = 13'h 650; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C40_OFFSET = 13'h 654; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C40_OFFSET = 13'h 658; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C40_OFFSET = 13'h 65c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C40_OFFSET = 13'h 660; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C40_OFFSET = 13'h 664; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C41_OFFSET = 13'h 668; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C41_OFFSET = 13'h 66c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C41_OFFSET = 13'h 670; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C41_OFFSET = 13'h 674; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C41_OFFSET = 13'h 678; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C41_OFFSET = 13'h 67c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C41_OFFSET = 13'h 680; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C41_OFFSET = 13'h 684; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C41_OFFSET = 13'h 688; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C41_OFFSET = 13'h 68c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C42_OFFSET = 13'h 690; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C42_OFFSET = 13'h 694; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C42_OFFSET = 13'h 698; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C42_OFFSET = 13'h 69c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C42_OFFSET = 13'h 6a0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C42_OFFSET = 13'h 6a4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C42_OFFSET = 13'h 6a8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C42_OFFSET = 13'h 6ac; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C42_OFFSET = 13'h 6b0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C42_OFFSET = 13'h 6b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C43_OFFSET = 13'h 6b8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C43_OFFSET = 13'h 6bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C43_OFFSET = 13'h 6c0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C43_OFFSET = 13'h 6c4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C43_OFFSET = 13'h 6c8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C43_OFFSET = 13'h 6cc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C43_OFFSET = 13'h 6d0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C43_OFFSET = 13'h 6d4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C43_OFFSET = 13'h 6d8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C43_OFFSET = 13'h 6dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C44_OFFSET = 13'h 6e0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C44_OFFSET = 13'h 6e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C44_OFFSET = 13'h 6e8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C44_OFFSET = 13'h 6ec; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C44_OFFSET = 13'h 6f0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C44_OFFSET = 13'h 6f4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C44_OFFSET = 13'h 6f8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C44_OFFSET = 13'h 6fc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C44_OFFSET = 13'h 700; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C44_OFFSET = 13'h 704; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C45_OFFSET = 13'h 708; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C45_OFFSET = 13'h 70c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C45_OFFSET = 13'h 710; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C45_OFFSET = 13'h 714; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C45_OFFSET = 13'h 718; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C45_OFFSET = 13'h 71c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C45_OFFSET = 13'h 720; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C45_OFFSET = 13'h 724; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C45_OFFSET = 13'h 728; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C45_OFFSET = 13'h 72c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C46_OFFSET = 13'h 730; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C46_OFFSET = 13'h 734; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C46_OFFSET = 13'h 738; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C46_OFFSET = 13'h 73c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C46_OFFSET = 13'h 740; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C46_OFFSET = 13'h 744; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C46_OFFSET = 13'h 748; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C46_OFFSET = 13'h 74c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C46_OFFSET = 13'h 750; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C46_OFFSET = 13'h 754; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C47_OFFSET = 13'h 758; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C47_OFFSET = 13'h 75c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C47_OFFSET = 13'h 760; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C47_OFFSET = 13'h 764; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C47_OFFSET = 13'h 768; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C47_OFFSET = 13'h 76c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C47_OFFSET = 13'h 770; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C47_OFFSET = 13'h 774; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C47_OFFSET = 13'h 778; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C47_OFFSET = 13'h 77c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C48_OFFSET = 13'h 780; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C48_OFFSET = 13'h 784; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C48_OFFSET = 13'h 788; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C48_OFFSET = 13'h 78c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C48_OFFSET = 13'h 790; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C48_OFFSET = 13'h 794; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C48_OFFSET = 13'h 798; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C48_OFFSET = 13'h 79c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C48_OFFSET = 13'h 7a0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C48_OFFSET = 13'h 7a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C49_OFFSET = 13'h 7a8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C49_OFFSET = 13'h 7ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C49_OFFSET = 13'h 7b0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C49_OFFSET = 13'h 7b4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C49_OFFSET = 13'h 7b8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C49_OFFSET = 13'h 7bc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C49_OFFSET = 13'h 7c0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C49_OFFSET = 13'h 7c4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C49_OFFSET = 13'h 7c8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C49_OFFSET = 13'h 7cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C50_OFFSET = 13'h 7d0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C50_OFFSET = 13'h 7d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C50_OFFSET = 13'h 7d8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C50_OFFSET = 13'h 7dc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C50_OFFSET = 13'h 7e0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C50_OFFSET = 13'h 7e4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C50_OFFSET = 13'h 7e8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C50_OFFSET = 13'h 7ec; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C50_OFFSET = 13'h 7f0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C50_OFFSET = 13'h 7f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C51_OFFSET = 13'h 7f8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C51_OFFSET = 13'h 7fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C51_OFFSET = 13'h 800; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C51_OFFSET = 13'h 804; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C51_OFFSET = 13'h 808; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C51_OFFSET = 13'h 80c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C51_OFFSET = 13'h 810; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C51_OFFSET = 13'h 814; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C51_OFFSET = 13'h 818; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C51_OFFSET = 13'h 81c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C52_OFFSET = 13'h 820; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C52_OFFSET = 13'h 824; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C52_OFFSET = 13'h 828; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C52_OFFSET = 13'h 82c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C52_OFFSET = 13'h 830; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C52_OFFSET = 13'h 834; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C52_OFFSET = 13'h 838; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C52_OFFSET = 13'h 83c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C52_OFFSET = 13'h 840; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C52_OFFSET = 13'h 844; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C53_OFFSET = 13'h 848; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C53_OFFSET = 13'h 84c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C53_OFFSET = 13'h 850; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C53_OFFSET = 13'h 854; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C53_OFFSET = 13'h 858; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C53_OFFSET = 13'h 85c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C53_OFFSET = 13'h 860; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C53_OFFSET = 13'h 864; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C53_OFFSET = 13'h 868; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C53_OFFSET = 13'h 86c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C54_OFFSET = 13'h 870; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C54_OFFSET = 13'h 874; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C54_OFFSET = 13'h 878; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C54_OFFSET = 13'h 87c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C54_OFFSET = 13'h 880; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C54_OFFSET = 13'h 884; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C54_OFFSET = 13'h 888; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C54_OFFSET = 13'h 88c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C54_OFFSET = 13'h 890; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C54_OFFSET = 13'h 894; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C55_OFFSET = 13'h 898; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C55_OFFSET = 13'h 89c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C55_OFFSET = 13'h 8a0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C55_OFFSET = 13'h 8a4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C55_OFFSET = 13'h 8a8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C55_OFFSET = 13'h 8ac; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C55_OFFSET = 13'h 8b0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C55_OFFSET = 13'h 8b4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C55_OFFSET = 13'h 8b8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C55_OFFSET = 13'h 8bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C56_OFFSET = 13'h 8c0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C56_OFFSET = 13'h 8c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C56_OFFSET = 13'h 8c8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C56_OFFSET = 13'h 8cc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C56_OFFSET = 13'h 8d0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C56_OFFSET = 13'h 8d4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C56_OFFSET = 13'h 8d8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C56_OFFSET = 13'h 8dc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C56_OFFSET = 13'h 8e0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C56_OFFSET = 13'h 8e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C57_OFFSET = 13'h 8e8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C57_OFFSET = 13'h 8ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C57_OFFSET = 13'h 8f0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C57_OFFSET = 13'h 8f4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C57_OFFSET = 13'h 8f8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C57_OFFSET = 13'h 8fc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C57_OFFSET = 13'h 900; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C57_OFFSET = 13'h 904; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C57_OFFSET = 13'h 908; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C57_OFFSET = 13'h 90c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C58_OFFSET = 13'h 910; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C58_OFFSET = 13'h 914; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C58_OFFSET = 13'h 918; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C58_OFFSET = 13'h 91c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C58_OFFSET = 13'h 920; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C58_OFFSET = 13'h 924; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C58_OFFSET = 13'h 928; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C58_OFFSET = 13'h 92c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C58_OFFSET = 13'h 930; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C58_OFFSET = 13'h 934; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C59_OFFSET = 13'h 938; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C59_OFFSET = 13'h 93c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C59_OFFSET = 13'h 940; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C59_OFFSET = 13'h 944; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C59_OFFSET = 13'h 948; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C59_OFFSET = 13'h 94c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C59_OFFSET = 13'h 950; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C59_OFFSET = 13'h 954; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C59_OFFSET = 13'h 958; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C59_OFFSET = 13'h 95c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C60_OFFSET = 13'h 960; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C60_OFFSET = 13'h 964; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C60_OFFSET = 13'h 968; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C60_OFFSET = 13'h 96c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C60_OFFSET = 13'h 970; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C60_OFFSET = 13'h 974; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C60_OFFSET = 13'h 978; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C60_OFFSET = 13'h 97c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C60_OFFSET = 13'h 980; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C60_OFFSET = 13'h 984; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C61_OFFSET = 13'h 988; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C61_OFFSET = 13'h 98c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C61_OFFSET = 13'h 990; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C61_OFFSET = 13'h 994; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C61_OFFSET = 13'h 998; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C61_OFFSET = 13'h 99c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C61_OFFSET = 13'h 9a0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C61_OFFSET = 13'h 9a4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C61_OFFSET = 13'h 9a8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C61_OFFSET = 13'h 9ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C62_OFFSET = 13'h 9b0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C62_OFFSET = 13'h 9b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C62_OFFSET = 13'h 9b8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C62_OFFSET = 13'h 9bc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C62_OFFSET = 13'h 9c0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C62_OFFSET = 13'h 9c4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C62_OFFSET = 13'h 9c8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C62_OFFSET = 13'h 9cc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C62_OFFSET = 13'h 9d0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C62_OFFSET = 13'h 9d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C63_OFFSET = 13'h 9d8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C63_OFFSET = 13'h 9dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C63_OFFSET = 13'h 9e0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C63_OFFSET = 13'h 9e4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C63_OFFSET = 13'h 9e8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C63_OFFSET = 13'h 9ec; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C63_OFFSET = 13'h 9f0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C63_OFFSET = 13'h 9f4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C63_OFFSET = 13'h 9f8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C63_OFFSET = 13'h 9fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C64_OFFSET = 13'h a00; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C64_OFFSET = 13'h a04; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C64_OFFSET = 13'h a08; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C64_OFFSET = 13'h a0c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C64_OFFSET = 13'h a10; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C64_OFFSET = 13'h a14; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C64_OFFSET = 13'h a18; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C64_OFFSET = 13'h a1c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C64_OFFSET = 13'h a20; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C64_OFFSET = 13'h a24; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C65_OFFSET = 13'h a28; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C65_OFFSET = 13'h a2c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C65_OFFSET = 13'h a30; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C65_OFFSET = 13'h a34; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C65_OFFSET = 13'h a38; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C65_OFFSET = 13'h a3c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C65_OFFSET = 13'h a40; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C65_OFFSET = 13'h a44; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C65_OFFSET = 13'h a48; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C65_OFFSET = 13'h a4c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C66_OFFSET = 13'h a50; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C66_OFFSET = 13'h a54; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C66_OFFSET = 13'h a58; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C66_OFFSET = 13'h a5c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C66_OFFSET = 13'h a60; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C66_OFFSET = 13'h a64; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C66_OFFSET = 13'h a68; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C66_OFFSET = 13'h a6c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C66_OFFSET = 13'h a70; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C66_OFFSET = 13'h a74; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C67_OFFSET = 13'h a78; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C67_OFFSET = 13'h a7c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C67_OFFSET = 13'h a80; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C67_OFFSET = 13'h a84; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C67_OFFSET = 13'h a88; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C67_OFFSET = 13'h a8c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C67_OFFSET = 13'h a90; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C67_OFFSET = 13'h a94; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C67_OFFSET = 13'h a98; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C67_OFFSET = 13'h a9c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C68_OFFSET = 13'h aa0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C68_OFFSET = 13'h aa4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C68_OFFSET = 13'h aa8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C68_OFFSET = 13'h aac; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C68_OFFSET = 13'h ab0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C68_OFFSET = 13'h ab4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C68_OFFSET = 13'h ab8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C68_OFFSET = 13'h abc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C68_OFFSET = 13'h ac0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C68_OFFSET = 13'h ac4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C69_OFFSET = 13'h ac8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C69_OFFSET = 13'h acc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C69_OFFSET = 13'h ad0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C69_OFFSET = 13'h ad4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C69_OFFSET = 13'h ad8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C69_OFFSET = 13'h adc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C69_OFFSET = 13'h ae0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C69_OFFSET = 13'h ae4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C69_OFFSET = 13'h ae8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C69_OFFSET = 13'h aec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C70_OFFSET = 13'h af0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C70_OFFSET = 13'h af4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C70_OFFSET = 13'h af8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C70_OFFSET = 13'h afc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C70_OFFSET = 13'h b00; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C70_OFFSET = 13'h b04; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C70_OFFSET = 13'h b08; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C70_OFFSET = 13'h b0c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C70_OFFSET = 13'h b10; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C70_OFFSET = 13'h b14; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C71_OFFSET = 13'h b18; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C71_OFFSET = 13'h b1c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C71_OFFSET = 13'h b20; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C71_OFFSET = 13'h b24; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C71_OFFSET = 13'h b28; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C71_OFFSET = 13'h b2c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C71_OFFSET = 13'h b30; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C71_OFFSET = 13'h b34; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C71_OFFSET = 13'h b38; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C71_OFFSET = 13'h b3c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C72_OFFSET = 13'h b40; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C72_OFFSET = 13'h b44; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C72_OFFSET = 13'h b48; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C72_OFFSET = 13'h b4c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C72_OFFSET = 13'h b50; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C72_OFFSET = 13'h b54; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C72_OFFSET = 13'h b58; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C72_OFFSET = 13'h b5c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C72_OFFSET = 13'h b60; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C72_OFFSET = 13'h b64; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C73_OFFSET = 13'h b68; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C73_OFFSET = 13'h b6c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C73_OFFSET = 13'h b70; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C73_OFFSET = 13'h b74; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C73_OFFSET = 13'h b78; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C73_OFFSET = 13'h b7c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C73_OFFSET = 13'h b80; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C73_OFFSET = 13'h b84; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C73_OFFSET = 13'h b88; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C73_OFFSET = 13'h b8c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C74_OFFSET = 13'h b90; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C74_OFFSET = 13'h b94; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C74_OFFSET = 13'h b98; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C74_OFFSET = 13'h b9c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C74_OFFSET = 13'h ba0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C74_OFFSET = 13'h ba4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C74_OFFSET = 13'h ba8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C74_OFFSET = 13'h bac; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C74_OFFSET = 13'h bb0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C74_OFFSET = 13'h bb4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C75_OFFSET = 13'h bb8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C75_OFFSET = 13'h bbc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C75_OFFSET = 13'h bc0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C75_OFFSET = 13'h bc4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C75_OFFSET = 13'h bc8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C75_OFFSET = 13'h bcc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C75_OFFSET = 13'h bd0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C75_OFFSET = 13'h bd4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C75_OFFSET = 13'h bd8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C75_OFFSET = 13'h bdc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C76_OFFSET = 13'h be0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C76_OFFSET = 13'h be4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C76_OFFSET = 13'h be8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C76_OFFSET = 13'h bec; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C76_OFFSET = 13'h bf0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C76_OFFSET = 13'h bf4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C76_OFFSET = 13'h bf8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C76_OFFSET = 13'h bfc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C76_OFFSET = 13'h c00; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C76_OFFSET = 13'h c04; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C77_OFFSET = 13'h c08; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C77_OFFSET = 13'h c0c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C77_OFFSET = 13'h c10; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C77_OFFSET = 13'h c14; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C77_OFFSET = 13'h c18; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C77_OFFSET = 13'h c1c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C77_OFFSET = 13'h c20; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C77_OFFSET = 13'h c24; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C77_OFFSET = 13'h c28; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C77_OFFSET = 13'h c2c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C78_OFFSET = 13'h c30; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C78_OFFSET = 13'h c34; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C78_OFFSET = 13'h c38; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C78_OFFSET = 13'h c3c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C78_OFFSET = 13'h c40; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C78_OFFSET = 13'h c44; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C78_OFFSET = 13'h c48; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C78_OFFSET = 13'h c4c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C78_OFFSET = 13'h c50; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C78_OFFSET = 13'h c54; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C79_OFFSET = 13'h c58; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C79_OFFSET = 13'h c5c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C79_OFFSET = 13'h c60; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C79_OFFSET = 13'h c64; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C79_OFFSET = 13'h c68; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C79_OFFSET = 13'h c6c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C79_OFFSET = 13'h c70; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C79_OFFSET = 13'h c74; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C79_OFFSET = 13'h c78; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C79_OFFSET = 13'h c7c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C80_OFFSET = 13'h c80; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C80_OFFSET = 13'h c84; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C80_OFFSET = 13'h c88; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C80_OFFSET = 13'h c8c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C80_OFFSET = 13'h c90; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C80_OFFSET = 13'h c94; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C80_OFFSET = 13'h c98; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C80_OFFSET = 13'h c9c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C80_OFFSET = 13'h ca0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C80_OFFSET = 13'h ca4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C81_OFFSET = 13'h ca8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C81_OFFSET = 13'h cac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C81_OFFSET = 13'h cb0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C81_OFFSET = 13'h cb4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C81_OFFSET = 13'h cb8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C81_OFFSET = 13'h cbc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C81_OFFSET = 13'h cc0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C81_OFFSET = 13'h cc4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C81_OFFSET = 13'h cc8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C81_OFFSET = 13'h ccc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C82_OFFSET = 13'h cd0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C82_OFFSET = 13'h cd4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C82_OFFSET = 13'h cd8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C82_OFFSET = 13'h cdc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C82_OFFSET = 13'h ce0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C82_OFFSET = 13'h ce4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C82_OFFSET = 13'h ce8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C82_OFFSET = 13'h cec; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C82_OFFSET = 13'h cf0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C82_OFFSET = 13'h cf4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C83_OFFSET = 13'h cf8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C83_OFFSET = 13'h cfc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C83_OFFSET = 13'h d00; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C83_OFFSET = 13'h d04; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C83_OFFSET = 13'h d08; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C83_OFFSET = 13'h d0c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C83_OFFSET = 13'h d10; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C83_OFFSET = 13'h d14; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C83_OFFSET = 13'h d18; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C83_OFFSET = 13'h d1c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C84_OFFSET = 13'h d20; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C84_OFFSET = 13'h d24; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C84_OFFSET = 13'h d28; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C84_OFFSET = 13'h d2c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C84_OFFSET = 13'h d30; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C84_OFFSET = 13'h d34; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C84_OFFSET = 13'h d38; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C84_OFFSET = 13'h d3c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C84_OFFSET = 13'h d40; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C84_OFFSET = 13'h d44; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C85_OFFSET = 13'h d48; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C85_OFFSET = 13'h d4c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C85_OFFSET = 13'h d50; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C85_OFFSET = 13'h d54; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C85_OFFSET = 13'h d58; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C85_OFFSET = 13'h d5c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C85_OFFSET = 13'h d60; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C85_OFFSET = 13'h d64; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C85_OFFSET = 13'h d68; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C85_OFFSET = 13'h d6c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C86_OFFSET = 13'h d70; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C86_OFFSET = 13'h d74; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C86_OFFSET = 13'h d78; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C86_OFFSET = 13'h d7c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C86_OFFSET = 13'h d80; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C86_OFFSET = 13'h d84; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C86_OFFSET = 13'h d88; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C86_OFFSET = 13'h d8c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C86_OFFSET = 13'h d90; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C86_OFFSET = 13'h d94; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C87_OFFSET = 13'h d98; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C87_OFFSET = 13'h d9c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C87_OFFSET = 13'h da0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C87_OFFSET = 13'h da4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C87_OFFSET = 13'h da8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C87_OFFSET = 13'h dac; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C87_OFFSET = 13'h db0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C87_OFFSET = 13'h db4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C87_OFFSET = 13'h db8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C87_OFFSET = 13'h dbc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C88_OFFSET = 13'h dc0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C88_OFFSET = 13'h dc4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C88_OFFSET = 13'h dc8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C88_OFFSET = 13'h dcc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C88_OFFSET = 13'h dd0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C88_OFFSET = 13'h dd4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C88_OFFSET = 13'h dd8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C88_OFFSET = 13'h ddc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C88_OFFSET = 13'h de0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C88_OFFSET = 13'h de4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C89_OFFSET = 13'h de8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C89_OFFSET = 13'h dec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C89_OFFSET = 13'h df0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C89_OFFSET = 13'h df4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C89_OFFSET = 13'h df8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C89_OFFSET = 13'h dfc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C89_OFFSET = 13'h e00; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C89_OFFSET = 13'h e04; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C89_OFFSET = 13'h e08; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C89_OFFSET = 13'h e0c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C90_OFFSET = 13'h e10; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C90_OFFSET = 13'h e14; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C90_OFFSET = 13'h e18; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C90_OFFSET = 13'h e1c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C90_OFFSET = 13'h e20; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C90_OFFSET = 13'h e24; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C90_OFFSET = 13'h e28; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C90_OFFSET = 13'h e2c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C90_OFFSET = 13'h e30; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C90_OFFSET = 13'h e34; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C91_OFFSET = 13'h e38; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C91_OFFSET = 13'h e3c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C91_OFFSET = 13'h e40; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C91_OFFSET = 13'h e44; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C91_OFFSET = 13'h e48; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C91_OFFSET = 13'h e4c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C91_OFFSET = 13'h e50; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C91_OFFSET = 13'h e54; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C91_OFFSET = 13'h e58; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C91_OFFSET = 13'h e5c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C92_OFFSET = 13'h e60; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C92_OFFSET = 13'h e64; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C92_OFFSET = 13'h e68; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C92_OFFSET = 13'h e6c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C92_OFFSET = 13'h e70; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C92_OFFSET = 13'h e74; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C92_OFFSET = 13'h e78; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C92_OFFSET = 13'h e7c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C92_OFFSET = 13'h e80; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C92_OFFSET = 13'h e84; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C93_OFFSET = 13'h e88; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C93_OFFSET = 13'h e8c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C93_OFFSET = 13'h e90; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C93_OFFSET = 13'h e94; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C93_OFFSET = 13'h e98; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C93_OFFSET = 13'h e9c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C93_OFFSET = 13'h ea0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C93_OFFSET = 13'h ea4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C93_OFFSET = 13'h ea8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C93_OFFSET = 13'h eac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C94_OFFSET = 13'h eb0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C94_OFFSET = 13'h eb4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C94_OFFSET = 13'h eb8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C94_OFFSET = 13'h ebc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C94_OFFSET = 13'h ec0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C94_OFFSET = 13'h ec4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C94_OFFSET = 13'h ec8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C94_OFFSET = 13'h ecc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C94_OFFSET = 13'h ed0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C94_OFFSET = 13'h ed4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C95_OFFSET = 13'h ed8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C95_OFFSET = 13'h edc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C95_OFFSET = 13'h ee0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C95_OFFSET = 13'h ee4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C95_OFFSET = 13'h ee8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C95_OFFSET = 13'h eec; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C95_OFFSET = 13'h ef0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C95_OFFSET = 13'h ef4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C95_OFFSET = 13'h ef8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C95_OFFSET = 13'h efc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C96_OFFSET = 13'h f00; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C96_OFFSET = 13'h f04; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C96_OFFSET = 13'h f08; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C96_OFFSET = 13'h f0c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C96_OFFSET = 13'h f10; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C96_OFFSET = 13'h f14; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C96_OFFSET = 13'h f18; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C96_OFFSET = 13'h f1c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C96_OFFSET = 13'h f20; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C96_OFFSET = 13'h f24; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C97_OFFSET = 13'h f28; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C97_OFFSET = 13'h f2c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C97_OFFSET = 13'h f30; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C97_OFFSET = 13'h f34; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C97_OFFSET = 13'h f38; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C97_OFFSET = 13'h f3c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C97_OFFSET = 13'h f40; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C97_OFFSET = 13'h f44; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C97_OFFSET = 13'h f48; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C97_OFFSET = 13'h f4c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C98_OFFSET = 13'h f50; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C98_OFFSET = 13'h f54; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C98_OFFSET = 13'h f58; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C98_OFFSET = 13'h f5c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C98_OFFSET = 13'h f60; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C98_OFFSET = 13'h f64; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C98_OFFSET = 13'h f68; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C98_OFFSET = 13'h f6c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C98_OFFSET = 13'h f70; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C98_OFFSET = 13'h f74; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C99_OFFSET = 13'h f78; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C99_OFFSET = 13'h f7c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C99_OFFSET = 13'h f80; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C99_OFFSET = 13'h f84; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C99_OFFSET = 13'h f88; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C99_OFFSET = 13'h f8c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C99_OFFSET = 13'h f90; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C99_OFFSET = 13'h f94; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C99_OFFSET = 13'h f98; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C99_OFFSET = 13'h f9c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C100_OFFSET = 13'h fa0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C100_OFFSET = 13'h fa4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C100_OFFSET = 13'h fa8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C100_OFFSET = 13'h fac; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C100_OFFSET = 13'h fb0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C100_OFFSET = 13'h fb4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C100_OFFSET = 13'h fb8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C100_OFFSET = 13'h fbc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C100_OFFSET = 13'h fc0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C100_OFFSET = 13'h fc4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C101_OFFSET = 13'h fc8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C101_OFFSET = 13'h fcc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C101_OFFSET = 13'h fd0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C101_OFFSET = 13'h fd4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C101_OFFSET = 13'h fd8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C101_OFFSET = 13'h fdc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C101_OFFSET = 13'h fe0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C101_OFFSET = 13'h fe4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C101_OFFSET = 13'h fe8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C101_OFFSET = 13'h fec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C102_OFFSET = 13'h ff0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C102_OFFSET = 13'h ff4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C102_OFFSET = 13'h ff8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C102_OFFSET = 13'h ffc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C102_OFFSET = 13'h 1000; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C102_OFFSET = 13'h 1004; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C102_OFFSET = 13'h 1008; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C102_OFFSET = 13'h 100c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C102_OFFSET = 13'h 1010; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C102_OFFSET = 13'h 1014; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C103_OFFSET = 13'h 1018; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C103_OFFSET = 13'h 101c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C103_OFFSET = 13'h 1020; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C103_OFFSET = 13'h 1024; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C103_OFFSET = 13'h 1028; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C103_OFFSET = 13'h 102c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C103_OFFSET = 13'h 1030; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C103_OFFSET = 13'h 1034; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C103_OFFSET = 13'h 1038; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C103_OFFSET = 13'h 103c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C104_OFFSET = 13'h 1040; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C104_OFFSET = 13'h 1044; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C104_OFFSET = 13'h 1048; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C104_OFFSET = 13'h 104c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C104_OFFSET = 13'h 1050; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C104_OFFSET = 13'h 1054; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C104_OFFSET = 13'h 1058; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C104_OFFSET = 13'h 105c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C104_OFFSET = 13'h 1060; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C104_OFFSET = 13'h 1064; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C105_OFFSET = 13'h 1068; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C105_OFFSET = 13'h 106c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C105_OFFSET = 13'h 1070; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C105_OFFSET = 13'h 1074; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C105_OFFSET = 13'h 1078; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C105_OFFSET = 13'h 107c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C105_OFFSET = 13'h 1080; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C105_OFFSET = 13'h 1084; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C105_OFFSET = 13'h 1088; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C105_OFFSET = 13'h 108c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C106_OFFSET = 13'h 1090; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C106_OFFSET = 13'h 1094; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C106_OFFSET = 13'h 1098; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C106_OFFSET = 13'h 109c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C106_OFFSET = 13'h 10a0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C106_OFFSET = 13'h 10a4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C106_OFFSET = 13'h 10a8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C106_OFFSET = 13'h 10ac; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C106_OFFSET = 13'h 10b0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C106_OFFSET = 13'h 10b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C107_OFFSET = 13'h 10b8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C107_OFFSET = 13'h 10bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C107_OFFSET = 13'h 10c0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C107_OFFSET = 13'h 10c4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C107_OFFSET = 13'h 10c8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C107_OFFSET = 13'h 10cc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C107_OFFSET = 13'h 10d0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C107_OFFSET = 13'h 10d4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C107_OFFSET = 13'h 10d8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C107_OFFSET = 13'h 10dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C108_OFFSET = 13'h 10e0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C108_OFFSET = 13'h 10e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C108_OFFSET = 13'h 10e8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C108_OFFSET = 13'h 10ec; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C108_OFFSET = 13'h 10f0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C108_OFFSET = 13'h 10f4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C108_OFFSET = 13'h 10f8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C108_OFFSET = 13'h 10fc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C108_OFFSET = 13'h 1100; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C108_OFFSET = 13'h 1104; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C109_OFFSET = 13'h 1108; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C109_OFFSET = 13'h 110c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C109_OFFSET = 13'h 1110; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C109_OFFSET = 13'h 1114; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C109_OFFSET = 13'h 1118; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C109_OFFSET = 13'h 111c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C109_OFFSET = 13'h 1120; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C109_OFFSET = 13'h 1124; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C109_OFFSET = 13'h 1128; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C109_OFFSET = 13'h 112c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C110_OFFSET = 13'h 1130; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C110_OFFSET = 13'h 1134; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C110_OFFSET = 13'h 1138; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C110_OFFSET = 13'h 113c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C110_OFFSET = 13'h 1140; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C110_OFFSET = 13'h 1144; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C110_OFFSET = 13'h 1148; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C110_OFFSET = 13'h 114c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C110_OFFSET = 13'h 1150; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C110_OFFSET = 13'h 1154; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C111_OFFSET = 13'h 1158; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C111_OFFSET = 13'h 115c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C111_OFFSET = 13'h 1160; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C111_OFFSET = 13'h 1164; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C111_OFFSET = 13'h 1168; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C111_OFFSET = 13'h 116c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C111_OFFSET = 13'h 1170; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C111_OFFSET = 13'h 1174; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C111_OFFSET = 13'h 1178; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C111_OFFSET = 13'h 117c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C112_OFFSET = 13'h 1180; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C112_OFFSET = 13'h 1184; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C112_OFFSET = 13'h 1188; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C112_OFFSET = 13'h 118c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C112_OFFSET = 13'h 1190; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C112_OFFSET = 13'h 1194; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C112_OFFSET = 13'h 1198; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C112_OFFSET = 13'h 119c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C112_OFFSET = 13'h 11a0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C112_OFFSET = 13'h 11a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C113_OFFSET = 13'h 11a8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C113_OFFSET = 13'h 11ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C113_OFFSET = 13'h 11b0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C113_OFFSET = 13'h 11b4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C113_OFFSET = 13'h 11b8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C113_OFFSET = 13'h 11bc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C113_OFFSET = 13'h 11c0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C113_OFFSET = 13'h 11c4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C113_OFFSET = 13'h 11c8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C113_OFFSET = 13'h 11cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C114_OFFSET = 13'h 11d0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C114_OFFSET = 13'h 11d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C114_OFFSET = 13'h 11d8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C114_OFFSET = 13'h 11dc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C114_OFFSET = 13'h 11e0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C114_OFFSET = 13'h 11e4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C114_OFFSET = 13'h 11e8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C114_OFFSET = 13'h 11ec; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C114_OFFSET = 13'h 11f0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C114_OFFSET = 13'h 11f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C115_OFFSET = 13'h 11f8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C115_OFFSET = 13'h 11fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C115_OFFSET = 13'h 1200; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C115_OFFSET = 13'h 1204; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C115_OFFSET = 13'h 1208; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C115_OFFSET = 13'h 120c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C115_OFFSET = 13'h 1210; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C115_OFFSET = 13'h 1214; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C115_OFFSET = 13'h 1218; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C115_OFFSET = 13'h 121c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C116_OFFSET = 13'h 1220; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C116_OFFSET = 13'h 1224; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C116_OFFSET = 13'h 1228; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C116_OFFSET = 13'h 122c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C116_OFFSET = 13'h 1230; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C116_OFFSET = 13'h 1234; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C116_OFFSET = 13'h 1238; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C116_OFFSET = 13'h 123c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C116_OFFSET = 13'h 1240; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C116_OFFSET = 13'h 1244; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C117_OFFSET = 13'h 1248; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C117_OFFSET = 13'h 124c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C117_OFFSET = 13'h 1250; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C117_OFFSET = 13'h 1254; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C117_OFFSET = 13'h 1258; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C117_OFFSET = 13'h 125c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C117_OFFSET = 13'h 1260; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C117_OFFSET = 13'h 1264; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C117_OFFSET = 13'h 1268; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C117_OFFSET = 13'h 126c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C118_OFFSET = 13'h 1270; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C118_OFFSET = 13'h 1274; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C118_OFFSET = 13'h 1278; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C118_OFFSET = 13'h 127c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C118_OFFSET = 13'h 1280; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C118_OFFSET = 13'h 1284; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C118_OFFSET = 13'h 1288; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C118_OFFSET = 13'h 128c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C118_OFFSET = 13'h 1290; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C118_OFFSET = 13'h 1294; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C119_OFFSET = 13'h 1298; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C119_OFFSET = 13'h 129c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C119_OFFSET = 13'h 12a0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C119_OFFSET = 13'h 12a4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C119_OFFSET = 13'h 12a8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C119_OFFSET = 13'h 12ac; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C119_OFFSET = 13'h 12b0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C119_OFFSET = 13'h 12b4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C119_OFFSET = 13'h 12b8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C119_OFFSET = 13'h 12bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C120_OFFSET = 13'h 12c0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C120_OFFSET = 13'h 12c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C120_OFFSET = 13'h 12c8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C120_OFFSET = 13'h 12cc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C120_OFFSET = 13'h 12d0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C120_OFFSET = 13'h 12d4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C120_OFFSET = 13'h 12d8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C120_OFFSET = 13'h 12dc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C120_OFFSET = 13'h 12e0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C120_OFFSET = 13'h 12e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C121_OFFSET = 13'h 12e8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C121_OFFSET = 13'h 12ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C121_OFFSET = 13'h 12f0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C121_OFFSET = 13'h 12f4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C121_OFFSET = 13'h 12f8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C121_OFFSET = 13'h 12fc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C121_OFFSET = 13'h 1300; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C121_OFFSET = 13'h 1304; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C121_OFFSET = 13'h 1308; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C121_OFFSET = 13'h 130c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C122_OFFSET = 13'h 1310; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C122_OFFSET = 13'h 1314; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C122_OFFSET = 13'h 1318; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C122_OFFSET = 13'h 131c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C122_OFFSET = 13'h 1320; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C122_OFFSET = 13'h 1324; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C122_OFFSET = 13'h 1328; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C122_OFFSET = 13'h 132c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C122_OFFSET = 13'h 1330; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C122_OFFSET = 13'h 1334; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C123_OFFSET = 13'h 1338; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C123_OFFSET = 13'h 133c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C123_OFFSET = 13'h 1340; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C123_OFFSET = 13'h 1344; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C123_OFFSET = 13'h 1348; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C123_OFFSET = 13'h 134c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C123_OFFSET = 13'h 1350; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C123_OFFSET = 13'h 1354; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C123_OFFSET = 13'h 1358; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C123_OFFSET = 13'h 135c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C124_OFFSET = 13'h 1360; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C124_OFFSET = 13'h 1364; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C124_OFFSET = 13'h 1368; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C124_OFFSET = 13'h 136c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C124_OFFSET = 13'h 1370; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C124_OFFSET = 13'h 1374; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C124_OFFSET = 13'h 1378; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C124_OFFSET = 13'h 137c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C124_OFFSET = 13'h 1380; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C124_OFFSET = 13'h 1384; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C125_OFFSET = 13'h 1388; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C125_OFFSET = 13'h 138c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C125_OFFSET = 13'h 1390; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C125_OFFSET = 13'h 1394; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C125_OFFSET = 13'h 1398; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C125_OFFSET = 13'h 139c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C125_OFFSET = 13'h 13a0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C125_OFFSET = 13'h 13a4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C125_OFFSET = 13'h 13a8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C125_OFFSET = 13'h 13ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C126_OFFSET = 13'h 13b0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C126_OFFSET = 13'h 13b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C126_OFFSET = 13'h 13b8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C126_OFFSET = 13'h 13bc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C126_OFFSET = 13'h 13c0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C126_OFFSET = 13'h 13c4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C126_OFFSET = 13'h 13c8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C126_OFFSET = 13'h 13cc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C126_OFFSET = 13'h 13d0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C126_OFFSET = 13'h 13d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C127_OFFSET = 13'h 13d8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C127_OFFSET = 13'h 13dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C127_OFFSET = 13'h 13e0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C127_OFFSET = 13'h 13e4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C127_OFFSET = 13'h 13e8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C127_OFFSET = 13'h 13ec; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C127_OFFSET = 13'h 13f0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C127_OFFSET = 13'h 13f4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C127_OFFSET = 13'h 13f8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C127_OFFSET = 13'h 13fc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C128_OFFSET = 13'h 1400; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C128_OFFSET = 13'h 1404; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C128_OFFSET = 13'h 1408; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C128_OFFSET = 13'h 140c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C128_OFFSET = 13'h 1410; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C128_OFFSET = 13'h 1414; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C128_OFFSET = 13'h 1418; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C128_OFFSET = 13'h 141c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C128_OFFSET = 13'h 1420; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C128_OFFSET = 13'h 1424; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C129_OFFSET = 13'h 1428; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C129_OFFSET = 13'h 142c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C129_OFFSET = 13'h 1430; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C129_OFFSET = 13'h 1434; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C129_OFFSET = 13'h 1438; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C129_OFFSET = 13'h 143c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C129_OFFSET = 13'h 1440; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C129_OFFSET = 13'h 1444; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C129_OFFSET = 13'h 1448; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C129_OFFSET = 13'h 144c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C130_OFFSET = 13'h 1450; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C130_OFFSET = 13'h 1454; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C130_OFFSET = 13'h 1458; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C130_OFFSET = 13'h 145c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C130_OFFSET = 13'h 1460; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C130_OFFSET = 13'h 1464; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C130_OFFSET = 13'h 1468; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C130_OFFSET = 13'h 146c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C130_OFFSET = 13'h 1470; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C130_OFFSET = 13'h 1474; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C131_OFFSET = 13'h 1478; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C131_OFFSET = 13'h 147c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C131_OFFSET = 13'h 1480; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C131_OFFSET = 13'h 1484; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C131_OFFSET = 13'h 1488; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C131_OFFSET = 13'h 148c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C131_OFFSET = 13'h 1490; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C131_OFFSET = 13'h 1494; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C131_OFFSET = 13'h 1498; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C131_OFFSET = 13'h 149c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C132_OFFSET = 13'h 14a0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C132_OFFSET = 13'h 14a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C132_OFFSET = 13'h 14a8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C132_OFFSET = 13'h 14ac; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C132_OFFSET = 13'h 14b0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C132_OFFSET = 13'h 14b4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C132_OFFSET = 13'h 14b8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C132_OFFSET = 13'h 14bc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C132_OFFSET = 13'h 14c0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C132_OFFSET = 13'h 14c4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C133_OFFSET = 13'h 14c8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C133_OFFSET = 13'h 14cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C133_OFFSET = 13'h 14d0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C133_OFFSET = 13'h 14d4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C133_OFFSET = 13'h 14d8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C133_OFFSET = 13'h 14dc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C133_OFFSET = 13'h 14e0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C133_OFFSET = 13'h 14e4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C133_OFFSET = 13'h 14e8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C133_OFFSET = 13'h 14ec; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C134_OFFSET = 13'h 14f0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C134_OFFSET = 13'h 14f4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C134_OFFSET = 13'h 14f8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C134_OFFSET = 13'h 14fc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C134_OFFSET = 13'h 1500; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C134_OFFSET = 13'h 1504; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C134_OFFSET = 13'h 1508; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C134_OFFSET = 13'h 150c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C134_OFFSET = 13'h 1510; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C134_OFFSET = 13'h 1514; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C135_OFFSET = 13'h 1518; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C135_OFFSET = 13'h 151c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C135_OFFSET = 13'h 1520; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C135_OFFSET = 13'h 1524; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C135_OFFSET = 13'h 1528; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C135_OFFSET = 13'h 152c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C135_OFFSET = 13'h 1530; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C135_OFFSET = 13'h 1534; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C135_OFFSET = 13'h 1538; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C135_OFFSET = 13'h 153c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C136_OFFSET = 13'h 1540; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C136_OFFSET = 13'h 1544; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C136_OFFSET = 13'h 1548; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C136_OFFSET = 13'h 154c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C136_OFFSET = 13'h 1550; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C136_OFFSET = 13'h 1554; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C136_OFFSET = 13'h 1558; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C136_OFFSET = 13'h 155c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C136_OFFSET = 13'h 1560; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C136_OFFSET = 13'h 1564; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C137_OFFSET = 13'h 1568; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C137_OFFSET = 13'h 156c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C137_OFFSET = 13'h 1570; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C137_OFFSET = 13'h 1574; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C137_OFFSET = 13'h 1578; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C137_OFFSET = 13'h 157c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C137_OFFSET = 13'h 1580; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C137_OFFSET = 13'h 1584; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C137_OFFSET = 13'h 1588; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C137_OFFSET = 13'h 158c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C138_OFFSET = 13'h 1590; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C138_OFFSET = 13'h 1594; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C138_OFFSET = 13'h 1598; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C138_OFFSET = 13'h 159c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C138_OFFSET = 13'h 15a0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C138_OFFSET = 13'h 15a4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C138_OFFSET = 13'h 15a8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C138_OFFSET = 13'h 15ac; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C138_OFFSET = 13'h 15b0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C138_OFFSET = 13'h 15b4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C139_OFFSET = 13'h 15b8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C139_OFFSET = 13'h 15bc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C139_OFFSET = 13'h 15c0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C139_OFFSET = 13'h 15c4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C139_OFFSET = 13'h 15c8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C139_OFFSET = 13'h 15cc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C139_OFFSET = 13'h 15d0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C139_OFFSET = 13'h 15d4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C139_OFFSET = 13'h 15d8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C139_OFFSET = 13'h 15dc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C140_OFFSET = 13'h 15e0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C140_OFFSET = 13'h 15e4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C140_OFFSET = 13'h 15e8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C140_OFFSET = 13'h 15ec; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C140_OFFSET = 13'h 15f0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C140_OFFSET = 13'h 15f4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C140_OFFSET = 13'h 15f8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C140_OFFSET = 13'h 15fc; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C140_OFFSET = 13'h 1600; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C140_OFFSET = 13'h 1604; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C141_OFFSET = 13'h 1608; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C141_OFFSET = 13'h 160c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C141_OFFSET = 13'h 1610; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C141_OFFSET = 13'h 1614; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C141_OFFSET = 13'h 1618; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C141_OFFSET = 13'h 161c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C141_OFFSET = 13'h 1620; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C141_OFFSET = 13'h 1624; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C141_OFFSET = 13'h 1628; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C141_OFFSET = 13'h 162c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C142_OFFSET = 13'h 1630; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C142_OFFSET = 13'h 1634; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C142_OFFSET = 13'h 1638; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C142_OFFSET = 13'h 163c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C142_OFFSET = 13'h 1640; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C142_OFFSET = 13'h 1644; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C142_OFFSET = 13'h 1648; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C142_OFFSET = 13'h 164c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C142_OFFSET = 13'h 1650; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C142_OFFSET = 13'h 1654; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C143_OFFSET = 13'h 1658; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C143_OFFSET = 13'h 165c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C143_OFFSET = 13'h 1660; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C143_OFFSET = 13'h 1664; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C143_OFFSET = 13'h 1668; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C143_OFFSET = 13'h 166c; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C143_OFFSET = 13'h 1670; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C143_OFFSET = 13'h 1674; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C143_OFFSET = 13'h 1678; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C143_OFFSET = 13'h 167c; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C144_OFFSET = 13'h 1680; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C144_OFFSET = 13'h 1684; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C144_OFFSET = 13'h 1688; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C144_OFFSET = 13'h 168c; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C144_OFFSET = 13'h 1690; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C144_OFFSET = 13'h 1694; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C144_OFFSET = 13'h 1698; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C144_OFFSET = 13'h 169c; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C144_OFFSET = 13'h 16a0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C144_OFFSET = 13'h 16a4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C145_OFFSET = 13'h 16a8; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C145_OFFSET = 13'h 16ac; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C145_OFFSET = 13'h 16b0; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C145_OFFSET = 13'h 16b4; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C145_OFFSET = 13'h 16b8; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C145_OFFSET = 13'h 16bc; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C145_OFFSET = 13'h 16c0; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C145_OFFSET = 13'h 16c4; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C145_OFFSET = 13'h 16c8; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C145_OFFSET = 13'h 16cc; - parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C146_OFFSET = 13'h 16d0; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C146_OFFSET = 13'h 16d4; - parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C146_OFFSET = 13'h 16d8; - parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C146_OFFSET = 13'h 16dc; - parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C146_OFFSET = 13'h 16e0; - parameter logic [BlockAw-1:0] SCMI_LENGTH_C146_OFFSET = 13'h 16e4; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C146_OFFSET = 13'h 16e8; - parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C146_OFFSET = 13'h 16ec; - parameter logic [BlockAw-1:0] SCMI_DOORBELL_C146_OFFSET = 13'h 16f0; - parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C146_OFFSET = 13'h 16f4; + parameter logic [BlockAw-1:0] SCMI_RESERVED_1_C0_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] SCMI_CHANNEL_STATUS_C0_OFFSET = 8'h 4; + parameter logic [BlockAw-1:0] SCMI_RESERVED_2_C0_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] SCMI_RESERVED_3_C0_OFFSET = 8'h c; + parameter logic [BlockAw-1:0] SCMI_CHANNEL_FLAGS_C0_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] SCMI_LENGTH_C0_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_HEADER_C0_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_0_C0_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_1_C0_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_2_C0_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_3_C0_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_4_C0_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_5_C0_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_6_C0_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_7_C0_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_8_C0_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_9_C0_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_10_C0_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_11_C0_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_12_C0_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_13_C0_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_14_C0_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_15_C0_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_16_C0_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_17_C0_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_18_C0_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_19_C0_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_20_C0_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_21_C0_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_22_C0_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_23_C0_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_24_C0_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_25_C0_OFFSET = 8'h 80; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_26_C0_OFFSET = 8'h 84; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_27_C0_OFFSET = 8'h 88; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_28_C0_OFFSET = 8'h 8c; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_29_C0_OFFSET = 8'h 90; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_30_C0_OFFSET = 8'h 94; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_31_C0_OFFSET = 8'h 98; + parameter logic [BlockAw-1:0] SCMI_MESSAGE_PAYLOAD_32_C0_OFFSET = 8'h 9c; + parameter logic [BlockAw-1:0] SCMI_DOORBELL_C0_OFFSET = 8'h a0; + parameter logic [BlockAw-1:0] SCMI_COMPLETION_INTERRUPT_C0_OFFSET = 8'h a4; // Register index typedef enum int { @@ -4438,2943 +80,87 @@ package scmi_reg_pkg; SCMI_CHANNEL_FLAGS_C0, SCMI_LENGTH_C0, SCMI_MESSAGE_HEADER_C0, + SCMI_MESSAGE_PAYLOAD_0_C0, SCMI_MESSAGE_PAYLOAD_1_C0, + SCMI_MESSAGE_PAYLOAD_2_C0, + SCMI_MESSAGE_PAYLOAD_3_C0, + SCMI_MESSAGE_PAYLOAD_4_C0, + SCMI_MESSAGE_PAYLOAD_5_C0, + SCMI_MESSAGE_PAYLOAD_6_C0, + SCMI_MESSAGE_PAYLOAD_7_C0, + SCMI_MESSAGE_PAYLOAD_8_C0, + SCMI_MESSAGE_PAYLOAD_9_C0, + SCMI_MESSAGE_PAYLOAD_10_C0, + SCMI_MESSAGE_PAYLOAD_11_C0, + SCMI_MESSAGE_PAYLOAD_12_C0, + SCMI_MESSAGE_PAYLOAD_13_C0, + SCMI_MESSAGE_PAYLOAD_14_C0, + SCMI_MESSAGE_PAYLOAD_15_C0, + SCMI_MESSAGE_PAYLOAD_16_C0, + SCMI_MESSAGE_PAYLOAD_17_C0, + SCMI_MESSAGE_PAYLOAD_18_C0, + SCMI_MESSAGE_PAYLOAD_19_C0, + SCMI_MESSAGE_PAYLOAD_20_C0, + SCMI_MESSAGE_PAYLOAD_21_C0, + SCMI_MESSAGE_PAYLOAD_22_C0, + SCMI_MESSAGE_PAYLOAD_23_C0, + SCMI_MESSAGE_PAYLOAD_24_C0, + SCMI_MESSAGE_PAYLOAD_25_C0, + SCMI_MESSAGE_PAYLOAD_26_C0, + SCMI_MESSAGE_PAYLOAD_27_C0, + SCMI_MESSAGE_PAYLOAD_28_C0, + SCMI_MESSAGE_PAYLOAD_29_C0, + SCMI_MESSAGE_PAYLOAD_30_C0, + SCMI_MESSAGE_PAYLOAD_31_C0, + SCMI_MESSAGE_PAYLOAD_32_C0, SCMI_DOORBELL_C0, - SCMI_COMPLETION_INTERRUPT_C0, - SCMI_RESERVED_1_C1, - SCMI_CHANNEL_STATUS_C1, - SCMI_RESERVED_2_C1, - SCMI_RESERVED_3_C1, - SCMI_CHANNEL_FLAGS_C1, - SCMI_LENGTH_C1, - SCMI_MESSAGE_HEADER_C1, - SCMI_MESSAGE_PAYLOAD_1_C1, - SCMI_DOORBELL_C1, - SCMI_COMPLETION_INTERRUPT_C1, - SCMI_RESERVED_1_C2, - SCMI_CHANNEL_STATUS_C2, - SCMI_RESERVED_2_C2, - SCMI_RESERVED_3_C2, - SCMI_CHANNEL_FLAGS_C2, - SCMI_LENGTH_C2, - SCMI_MESSAGE_HEADER_C2, - SCMI_MESSAGE_PAYLOAD_1_C2, - SCMI_DOORBELL_C2, - SCMI_COMPLETION_INTERRUPT_C2, - SCMI_RESERVED_1_C3, - SCMI_CHANNEL_STATUS_C3, - SCMI_RESERVED_2_C3, - SCMI_RESERVED_3_C3, - SCMI_CHANNEL_FLAGS_C3, - SCMI_LENGTH_C3, - SCMI_MESSAGE_HEADER_C3, - SCMI_MESSAGE_PAYLOAD_1_C3, - SCMI_DOORBELL_C3, - SCMI_COMPLETION_INTERRUPT_C3, - SCMI_RESERVED_1_C4, - SCMI_CHANNEL_STATUS_C4, - SCMI_RESERVED_2_C4, - SCMI_RESERVED_3_C4, - SCMI_CHANNEL_FLAGS_C4, - SCMI_LENGTH_C4, - SCMI_MESSAGE_HEADER_C4, - SCMI_MESSAGE_PAYLOAD_1_C4, - SCMI_DOORBELL_C4, - SCMI_COMPLETION_INTERRUPT_C4, - SCMI_RESERVED_1_C5, - SCMI_CHANNEL_STATUS_C5, - SCMI_RESERVED_2_C5, - SCMI_RESERVED_3_C5, - SCMI_CHANNEL_FLAGS_C5, - SCMI_LENGTH_C5, - SCMI_MESSAGE_HEADER_C5, - SCMI_MESSAGE_PAYLOAD_1_C5, - SCMI_DOORBELL_C5, - SCMI_COMPLETION_INTERRUPT_C5, - SCMI_RESERVED_1_C6, - SCMI_CHANNEL_STATUS_C6, - SCMI_RESERVED_2_C6, - SCMI_RESERVED_3_C6, - SCMI_CHANNEL_FLAGS_C6, - SCMI_LENGTH_C6, - SCMI_MESSAGE_HEADER_C6, - SCMI_MESSAGE_PAYLOAD_1_C6, - SCMI_DOORBELL_C6, - SCMI_COMPLETION_INTERRUPT_C6, - SCMI_RESERVED_1_C7, - SCMI_CHANNEL_STATUS_C7, - SCMI_RESERVED_2_C7, - SCMI_RESERVED_3_C7, - SCMI_CHANNEL_FLAGS_C7, - SCMI_LENGTH_C7, - SCMI_MESSAGE_HEADER_C7, - SCMI_MESSAGE_PAYLOAD_1_C7, - SCMI_DOORBELL_C7, - SCMI_COMPLETION_INTERRUPT_C7, - SCMI_RESERVED_1_C8, - SCMI_CHANNEL_STATUS_C8, - SCMI_RESERVED_2_C8, - SCMI_RESERVED_3_C8, - SCMI_CHANNEL_FLAGS_C8, - SCMI_LENGTH_C8, - SCMI_MESSAGE_HEADER_C8, - SCMI_MESSAGE_PAYLOAD_1_C8, - SCMI_DOORBELL_C8, - SCMI_COMPLETION_INTERRUPT_C8, - SCMI_RESERVED_1_C9, - SCMI_CHANNEL_STATUS_C9, - SCMI_RESERVED_2_C9, - SCMI_RESERVED_3_C9, - SCMI_CHANNEL_FLAGS_C9, - SCMI_LENGTH_C9, - SCMI_MESSAGE_HEADER_C9, - SCMI_MESSAGE_PAYLOAD_1_C9, - SCMI_DOORBELL_C9, - SCMI_COMPLETION_INTERRUPT_C9, - SCMI_RESERVED_1_C10, - SCMI_CHANNEL_STATUS_C10, - SCMI_RESERVED_2_C10, - SCMI_RESERVED_3_C10, - SCMI_CHANNEL_FLAGS_C10, - SCMI_LENGTH_C10, - SCMI_MESSAGE_HEADER_C10, - SCMI_MESSAGE_PAYLOAD_1_C10, - SCMI_DOORBELL_C10, - SCMI_COMPLETION_INTERRUPT_C10, - SCMI_RESERVED_1_C11, - SCMI_CHANNEL_STATUS_C11, - SCMI_RESERVED_2_C11, - SCMI_RESERVED_3_C11, - SCMI_CHANNEL_FLAGS_C11, - SCMI_LENGTH_C11, - SCMI_MESSAGE_HEADER_C11, - SCMI_MESSAGE_PAYLOAD_1_C11, - SCMI_DOORBELL_C11, - SCMI_COMPLETION_INTERRUPT_C11, - SCMI_RESERVED_1_C12, - SCMI_CHANNEL_STATUS_C12, - SCMI_RESERVED_2_C12, - SCMI_RESERVED_3_C12, - SCMI_CHANNEL_FLAGS_C12, - SCMI_LENGTH_C12, - SCMI_MESSAGE_HEADER_C12, - SCMI_MESSAGE_PAYLOAD_1_C12, - SCMI_DOORBELL_C12, - SCMI_COMPLETION_INTERRUPT_C12, - SCMI_RESERVED_1_C13, - SCMI_CHANNEL_STATUS_C13, - SCMI_RESERVED_2_C13, - SCMI_RESERVED_3_C13, - SCMI_CHANNEL_FLAGS_C13, - SCMI_LENGTH_C13, - SCMI_MESSAGE_HEADER_C13, - SCMI_MESSAGE_PAYLOAD_1_C13, - SCMI_DOORBELL_C13, - SCMI_COMPLETION_INTERRUPT_C13, - SCMI_RESERVED_1_C14, - SCMI_CHANNEL_STATUS_C14, - SCMI_RESERVED_2_C14, - SCMI_RESERVED_3_C14, - SCMI_CHANNEL_FLAGS_C14, - SCMI_LENGTH_C14, - SCMI_MESSAGE_HEADER_C14, - SCMI_MESSAGE_PAYLOAD_1_C14, - SCMI_DOORBELL_C14, - SCMI_COMPLETION_INTERRUPT_C14, - SCMI_RESERVED_1_C15, - SCMI_CHANNEL_STATUS_C15, - SCMI_RESERVED_2_C15, - SCMI_RESERVED_3_C15, - SCMI_CHANNEL_FLAGS_C15, - SCMI_LENGTH_C15, - SCMI_MESSAGE_HEADER_C15, - SCMI_MESSAGE_PAYLOAD_1_C15, - SCMI_DOORBELL_C15, - SCMI_COMPLETION_INTERRUPT_C15, - SCMI_RESERVED_1_C16, - SCMI_CHANNEL_STATUS_C16, - SCMI_RESERVED_2_C16, - SCMI_RESERVED_3_C16, - SCMI_CHANNEL_FLAGS_C16, - SCMI_LENGTH_C16, - SCMI_MESSAGE_HEADER_C16, - SCMI_MESSAGE_PAYLOAD_1_C16, - SCMI_DOORBELL_C16, - SCMI_COMPLETION_INTERRUPT_C16, - SCMI_RESERVED_1_C17, - SCMI_CHANNEL_STATUS_C17, - SCMI_RESERVED_2_C17, - SCMI_RESERVED_3_C17, - SCMI_CHANNEL_FLAGS_C17, - SCMI_LENGTH_C17, - SCMI_MESSAGE_HEADER_C17, - SCMI_MESSAGE_PAYLOAD_1_C17, - SCMI_DOORBELL_C17, - SCMI_COMPLETION_INTERRUPT_C17, - SCMI_RESERVED_1_C18, - SCMI_CHANNEL_STATUS_C18, - SCMI_RESERVED_2_C18, - SCMI_RESERVED_3_C18, - SCMI_CHANNEL_FLAGS_C18, - SCMI_LENGTH_C18, - SCMI_MESSAGE_HEADER_C18, - SCMI_MESSAGE_PAYLOAD_1_C18, - SCMI_DOORBELL_C18, - SCMI_COMPLETION_INTERRUPT_C18, - SCMI_RESERVED_1_C19, - SCMI_CHANNEL_STATUS_C19, - SCMI_RESERVED_2_C19, - SCMI_RESERVED_3_C19, - SCMI_CHANNEL_FLAGS_C19, - SCMI_LENGTH_C19, - SCMI_MESSAGE_HEADER_C19, - SCMI_MESSAGE_PAYLOAD_1_C19, - SCMI_DOORBELL_C19, - SCMI_COMPLETION_INTERRUPT_C19, - SCMI_RESERVED_1_C20, - SCMI_CHANNEL_STATUS_C20, - SCMI_RESERVED_2_C20, - SCMI_RESERVED_3_C20, - SCMI_CHANNEL_FLAGS_C20, - SCMI_LENGTH_C20, - SCMI_MESSAGE_HEADER_C20, - SCMI_MESSAGE_PAYLOAD_1_C20, - SCMI_DOORBELL_C20, - SCMI_COMPLETION_INTERRUPT_C20, - SCMI_RESERVED_1_C21, - SCMI_CHANNEL_STATUS_C21, - SCMI_RESERVED_2_C21, - SCMI_RESERVED_3_C21, - SCMI_CHANNEL_FLAGS_C21, - SCMI_LENGTH_C21, - SCMI_MESSAGE_HEADER_C21, - SCMI_MESSAGE_PAYLOAD_1_C21, - SCMI_DOORBELL_C21, - SCMI_COMPLETION_INTERRUPT_C21, - SCMI_RESERVED_1_C22, - SCMI_CHANNEL_STATUS_C22, - SCMI_RESERVED_2_C22, - SCMI_RESERVED_3_C22, - SCMI_CHANNEL_FLAGS_C22, - SCMI_LENGTH_C22, - SCMI_MESSAGE_HEADER_C22, - SCMI_MESSAGE_PAYLOAD_1_C22, - SCMI_DOORBELL_C22, - SCMI_COMPLETION_INTERRUPT_C22, - SCMI_RESERVED_1_C23, - SCMI_CHANNEL_STATUS_C23, - SCMI_RESERVED_2_C23, - SCMI_RESERVED_3_C23, - SCMI_CHANNEL_FLAGS_C23, - SCMI_LENGTH_C23, - SCMI_MESSAGE_HEADER_C23, - SCMI_MESSAGE_PAYLOAD_1_C23, - SCMI_DOORBELL_C23, - SCMI_COMPLETION_INTERRUPT_C23, - SCMI_RESERVED_1_C24, - SCMI_CHANNEL_STATUS_C24, - SCMI_RESERVED_2_C24, - SCMI_RESERVED_3_C24, - SCMI_CHANNEL_FLAGS_C24, - SCMI_LENGTH_C24, - SCMI_MESSAGE_HEADER_C24, - SCMI_MESSAGE_PAYLOAD_1_C24, - SCMI_DOORBELL_C24, - SCMI_COMPLETION_INTERRUPT_C24, - SCMI_RESERVED_1_C25, - SCMI_CHANNEL_STATUS_C25, - SCMI_RESERVED_2_C25, - SCMI_RESERVED_3_C25, - SCMI_CHANNEL_FLAGS_C25, - SCMI_LENGTH_C25, - SCMI_MESSAGE_HEADER_C25, - SCMI_MESSAGE_PAYLOAD_1_C25, - SCMI_DOORBELL_C25, - SCMI_COMPLETION_INTERRUPT_C25, - SCMI_RESERVED_1_C26, - SCMI_CHANNEL_STATUS_C26, - SCMI_RESERVED_2_C26, - SCMI_RESERVED_3_C26, - SCMI_CHANNEL_FLAGS_C26, - SCMI_LENGTH_C26, - SCMI_MESSAGE_HEADER_C26, - SCMI_MESSAGE_PAYLOAD_1_C26, - SCMI_DOORBELL_C26, - SCMI_COMPLETION_INTERRUPT_C26, - SCMI_RESERVED_1_C27, - SCMI_CHANNEL_STATUS_C27, - SCMI_RESERVED_2_C27, - SCMI_RESERVED_3_C27, - SCMI_CHANNEL_FLAGS_C27, - SCMI_LENGTH_C27, - SCMI_MESSAGE_HEADER_C27, - SCMI_MESSAGE_PAYLOAD_1_C27, - SCMI_DOORBELL_C27, - SCMI_COMPLETION_INTERRUPT_C27, - SCMI_RESERVED_1_C28, - SCMI_CHANNEL_STATUS_C28, - SCMI_RESERVED_2_C28, - SCMI_RESERVED_3_C28, - SCMI_CHANNEL_FLAGS_C28, - SCMI_LENGTH_C28, - SCMI_MESSAGE_HEADER_C28, - SCMI_MESSAGE_PAYLOAD_1_C28, - SCMI_DOORBELL_C28, - SCMI_COMPLETION_INTERRUPT_C28, - SCMI_RESERVED_1_C29, - SCMI_CHANNEL_STATUS_C29, - SCMI_RESERVED_2_C29, - SCMI_RESERVED_3_C29, - SCMI_CHANNEL_FLAGS_C29, - SCMI_LENGTH_C29, - SCMI_MESSAGE_HEADER_C29, - SCMI_MESSAGE_PAYLOAD_1_C29, - SCMI_DOORBELL_C29, - SCMI_COMPLETION_INTERRUPT_C29, - SCMI_RESERVED_1_C30, - SCMI_CHANNEL_STATUS_C30, - SCMI_RESERVED_2_C30, - SCMI_RESERVED_3_C30, - SCMI_CHANNEL_FLAGS_C30, - SCMI_LENGTH_C30, - SCMI_MESSAGE_HEADER_C30, - SCMI_MESSAGE_PAYLOAD_1_C30, - SCMI_DOORBELL_C30, - SCMI_COMPLETION_INTERRUPT_C30, - SCMI_RESERVED_1_C31, - SCMI_CHANNEL_STATUS_C31, - SCMI_RESERVED_2_C31, - SCMI_RESERVED_3_C31, - SCMI_CHANNEL_FLAGS_C31, - SCMI_LENGTH_C31, - SCMI_MESSAGE_HEADER_C31, - SCMI_MESSAGE_PAYLOAD_1_C31, - SCMI_DOORBELL_C31, - SCMI_COMPLETION_INTERRUPT_C31, - SCMI_RESERVED_1_C32, - SCMI_CHANNEL_STATUS_C32, - SCMI_RESERVED_2_C32, - SCMI_RESERVED_3_C32, - SCMI_CHANNEL_FLAGS_C32, - SCMI_LENGTH_C32, - SCMI_MESSAGE_HEADER_C32, - SCMI_MESSAGE_PAYLOAD_1_C32, - SCMI_DOORBELL_C32, - SCMI_COMPLETION_INTERRUPT_C32, - SCMI_RESERVED_1_C33, - SCMI_CHANNEL_STATUS_C33, - SCMI_RESERVED_2_C33, - SCMI_RESERVED_3_C33, - SCMI_CHANNEL_FLAGS_C33, - SCMI_LENGTH_C33, - SCMI_MESSAGE_HEADER_C33, - SCMI_MESSAGE_PAYLOAD_1_C33, - SCMI_DOORBELL_C33, - SCMI_COMPLETION_INTERRUPT_C33, - SCMI_RESERVED_1_C34, - SCMI_CHANNEL_STATUS_C34, - SCMI_RESERVED_2_C34, - SCMI_RESERVED_3_C34, - SCMI_CHANNEL_FLAGS_C34, - SCMI_LENGTH_C34, - SCMI_MESSAGE_HEADER_C34, - SCMI_MESSAGE_PAYLOAD_1_C34, - SCMI_DOORBELL_C34, - SCMI_COMPLETION_INTERRUPT_C34, - SCMI_RESERVED_1_C35, - SCMI_CHANNEL_STATUS_C35, - SCMI_RESERVED_2_C35, - SCMI_RESERVED_3_C35, - SCMI_CHANNEL_FLAGS_C35, - SCMI_LENGTH_C35, - SCMI_MESSAGE_HEADER_C35, - SCMI_MESSAGE_PAYLOAD_1_C35, - SCMI_DOORBELL_C35, - SCMI_COMPLETION_INTERRUPT_C35, - SCMI_RESERVED_1_C36, - SCMI_CHANNEL_STATUS_C36, - SCMI_RESERVED_2_C36, - SCMI_RESERVED_3_C36, - SCMI_CHANNEL_FLAGS_C36, - SCMI_LENGTH_C36, - SCMI_MESSAGE_HEADER_C36, - SCMI_MESSAGE_PAYLOAD_1_C36, - SCMI_DOORBELL_C36, - SCMI_COMPLETION_INTERRUPT_C36, - SCMI_RESERVED_1_C37, - SCMI_CHANNEL_STATUS_C37, - SCMI_RESERVED_2_C37, - SCMI_RESERVED_3_C37, - SCMI_CHANNEL_FLAGS_C37, - SCMI_LENGTH_C37, - SCMI_MESSAGE_HEADER_C37, - SCMI_MESSAGE_PAYLOAD_1_C37, - SCMI_DOORBELL_C37, - SCMI_COMPLETION_INTERRUPT_C37, - SCMI_RESERVED_1_C38, - SCMI_CHANNEL_STATUS_C38, - SCMI_RESERVED_2_C38, - SCMI_RESERVED_3_C38, - SCMI_CHANNEL_FLAGS_C38, - SCMI_LENGTH_C38, - SCMI_MESSAGE_HEADER_C38, - SCMI_MESSAGE_PAYLOAD_1_C38, - SCMI_DOORBELL_C38, - SCMI_COMPLETION_INTERRUPT_C38, - SCMI_RESERVED_1_C39, - SCMI_CHANNEL_STATUS_C39, - SCMI_RESERVED_2_C39, - SCMI_RESERVED_3_C39, - SCMI_CHANNEL_FLAGS_C39, - SCMI_LENGTH_C39, - SCMI_MESSAGE_HEADER_C39, - SCMI_MESSAGE_PAYLOAD_1_C39, - SCMI_DOORBELL_C39, - SCMI_COMPLETION_INTERRUPT_C39, - SCMI_RESERVED_1_C40, - SCMI_CHANNEL_STATUS_C40, - SCMI_RESERVED_2_C40, - SCMI_RESERVED_3_C40, - SCMI_CHANNEL_FLAGS_C40, - SCMI_LENGTH_C40, - SCMI_MESSAGE_HEADER_C40, - SCMI_MESSAGE_PAYLOAD_1_C40, - SCMI_DOORBELL_C40, - SCMI_COMPLETION_INTERRUPT_C40, - SCMI_RESERVED_1_C41, - SCMI_CHANNEL_STATUS_C41, - SCMI_RESERVED_2_C41, - SCMI_RESERVED_3_C41, - SCMI_CHANNEL_FLAGS_C41, - SCMI_LENGTH_C41, - SCMI_MESSAGE_HEADER_C41, - SCMI_MESSAGE_PAYLOAD_1_C41, - SCMI_DOORBELL_C41, - SCMI_COMPLETION_INTERRUPT_C41, - SCMI_RESERVED_1_C42, - SCMI_CHANNEL_STATUS_C42, - SCMI_RESERVED_2_C42, - SCMI_RESERVED_3_C42, - SCMI_CHANNEL_FLAGS_C42, - SCMI_LENGTH_C42, - SCMI_MESSAGE_HEADER_C42, - SCMI_MESSAGE_PAYLOAD_1_C42, - SCMI_DOORBELL_C42, - SCMI_COMPLETION_INTERRUPT_C42, - SCMI_RESERVED_1_C43, - SCMI_CHANNEL_STATUS_C43, - SCMI_RESERVED_2_C43, - SCMI_RESERVED_3_C43, - SCMI_CHANNEL_FLAGS_C43, - SCMI_LENGTH_C43, - SCMI_MESSAGE_HEADER_C43, - SCMI_MESSAGE_PAYLOAD_1_C43, - SCMI_DOORBELL_C43, - SCMI_COMPLETION_INTERRUPT_C43, - SCMI_RESERVED_1_C44, - SCMI_CHANNEL_STATUS_C44, - SCMI_RESERVED_2_C44, - SCMI_RESERVED_3_C44, - SCMI_CHANNEL_FLAGS_C44, - SCMI_LENGTH_C44, - SCMI_MESSAGE_HEADER_C44, - SCMI_MESSAGE_PAYLOAD_1_C44, - SCMI_DOORBELL_C44, - SCMI_COMPLETION_INTERRUPT_C44, - SCMI_RESERVED_1_C45, - SCMI_CHANNEL_STATUS_C45, - SCMI_RESERVED_2_C45, - SCMI_RESERVED_3_C45, - SCMI_CHANNEL_FLAGS_C45, - SCMI_LENGTH_C45, - SCMI_MESSAGE_HEADER_C45, - SCMI_MESSAGE_PAYLOAD_1_C45, - SCMI_DOORBELL_C45, - SCMI_COMPLETION_INTERRUPT_C45, - SCMI_RESERVED_1_C46, - SCMI_CHANNEL_STATUS_C46, - SCMI_RESERVED_2_C46, - SCMI_RESERVED_3_C46, - SCMI_CHANNEL_FLAGS_C46, - SCMI_LENGTH_C46, - SCMI_MESSAGE_HEADER_C46, - SCMI_MESSAGE_PAYLOAD_1_C46, - SCMI_DOORBELL_C46, - SCMI_COMPLETION_INTERRUPT_C46, - SCMI_RESERVED_1_C47, - SCMI_CHANNEL_STATUS_C47, - SCMI_RESERVED_2_C47, - SCMI_RESERVED_3_C47, - SCMI_CHANNEL_FLAGS_C47, - SCMI_LENGTH_C47, - SCMI_MESSAGE_HEADER_C47, - SCMI_MESSAGE_PAYLOAD_1_C47, - SCMI_DOORBELL_C47, - SCMI_COMPLETION_INTERRUPT_C47, - SCMI_RESERVED_1_C48, - SCMI_CHANNEL_STATUS_C48, - SCMI_RESERVED_2_C48, - SCMI_RESERVED_3_C48, - SCMI_CHANNEL_FLAGS_C48, - SCMI_LENGTH_C48, - SCMI_MESSAGE_HEADER_C48, - SCMI_MESSAGE_PAYLOAD_1_C48, - SCMI_DOORBELL_C48, - SCMI_COMPLETION_INTERRUPT_C48, - SCMI_RESERVED_1_C49, - SCMI_CHANNEL_STATUS_C49, - SCMI_RESERVED_2_C49, - SCMI_RESERVED_3_C49, - SCMI_CHANNEL_FLAGS_C49, - SCMI_LENGTH_C49, - SCMI_MESSAGE_HEADER_C49, - SCMI_MESSAGE_PAYLOAD_1_C49, - SCMI_DOORBELL_C49, - SCMI_COMPLETION_INTERRUPT_C49, - SCMI_RESERVED_1_C50, - SCMI_CHANNEL_STATUS_C50, - SCMI_RESERVED_2_C50, - SCMI_RESERVED_3_C50, - SCMI_CHANNEL_FLAGS_C50, - SCMI_LENGTH_C50, - SCMI_MESSAGE_HEADER_C50, - SCMI_MESSAGE_PAYLOAD_1_C50, - SCMI_DOORBELL_C50, - SCMI_COMPLETION_INTERRUPT_C50, - SCMI_RESERVED_1_C51, - SCMI_CHANNEL_STATUS_C51, - SCMI_RESERVED_2_C51, - SCMI_RESERVED_3_C51, - SCMI_CHANNEL_FLAGS_C51, - SCMI_LENGTH_C51, - SCMI_MESSAGE_HEADER_C51, - SCMI_MESSAGE_PAYLOAD_1_C51, - SCMI_DOORBELL_C51, - SCMI_COMPLETION_INTERRUPT_C51, - SCMI_RESERVED_1_C52, - SCMI_CHANNEL_STATUS_C52, - SCMI_RESERVED_2_C52, - SCMI_RESERVED_3_C52, - SCMI_CHANNEL_FLAGS_C52, - SCMI_LENGTH_C52, - SCMI_MESSAGE_HEADER_C52, - SCMI_MESSAGE_PAYLOAD_1_C52, - SCMI_DOORBELL_C52, - SCMI_COMPLETION_INTERRUPT_C52, - SCMI_RESERVED_1_C53, - SCMI_CHANNEL_STATUS_C53, - SCMI_RESERVED_2_C53, - SCMI_RESERVED_3_C53, - SCMI_CHANNEL_FLAGS_C53, - SCMI_LENGTH_C53, - SCMI_MESSAGE_HEADER_C53, - SCMI_MESSAGE_PAYLOAD_1_C53, - SCMI_DOORBELL_C53, - SCMI_COMPLETION_INTERRUPT_C53, - SCMI_RESERVED_1_C54, - SCMI_CHANNEL_STATUS_C54, - SCMI_RESERVED_2_C54, - SCMI_RESERVED_3_C54, - SCMI_CHANNEL_FLAGS_C54, - SCMI_LENGTH_C54, - SCMI_MESSAGE_HEADER_C54, - SCMI_MESSAGE_PAYLOAD_1_C54, - SCMI_DOORBELL_C54, - SCMI_COMPLETION_INTERRUPT_C54, - SCMI_RESERVED_1_C55, - SCMI_CHANNEL_STATUS_C55, - SCMI_RESERVED_2_C55, - SCMI_RESERVED_3_C55, - SCMI_CHANNEL_FLAGS_C55, - SCMI_LENGTH_C55, - SCMI_MESSAGE_HEADER_C55, - SCMI_MESSAGE_PAYLOAD_1_C55, - SCMI_DOORBELL_C55, - SCMI_COMPLETION_INTERRUPT_C55, - SCMI_RESERVED_1_C56, - SCMI_CHANNEL_STATUS_C56, - SCMI_RESERVED_2_C56, - SCMI_RESERVED_3_C56, - SCMI_CHANNEL_FLAGS_C56, - SCMI_LENGTH_C56, - SCMI_MESSAGE_HEADER_C56, - SCMI_MESSAGE_PAYLOAD_1_C56, - SCMI_DOORBELL_C56, - SCMI_COMPLETION_INTERRUPT_C56, - SCMI_RESERVED_1_C57, - SCMI_CHANNEL_STATUS_C57, - SCMI_RESERVED_2_C57, - SCMI_RESERVED_3_C57, - SCMI_CHANNEL_FLAGS_C57, - SCMI_LENGTH_C57, - SCMI_MESSAGE_HEADER_C57, - SCMI_MESSAGE_PAYLOAD_1_C57, - SCMI_DOORBELL_C57, - SCMI_COMPLETION_INTERRUPT_C57, - SCMI_RESERVED_1_C58, - SCMI_CHANNEL_STATUS_C58, - SCMI_RESERVED_2_C58, - SCMI_RESERVED_3_C58, - SCMI_CHANNEL_FLAGS_C58, - SCMI_LENGTH_C58, - SCMI_MESSAGE_HEADER_C58, - SCMI_MESSAGE_PAYLOAD_1_C58, - SCMI_DOORBELL_C58, - SCMI_COMPLETION_INTERRUPT_C58, - SCMI_RESERVED_1_C59, - SCMI_CHANNEL_STATUS_C59, - SCMI_RESERVED_2_C59, - SCMI_RESERVED_3_C59, - SCMI_CHANNEL_FLAGS_C59, - SCMI_LENGTH_C59, - SCMI_MESSAGE_HEADER_C59, - SCMI_MESSAGE_PAYLOAD_1_C59, - SCMI_DOORBELL_C59, - SCMI_COMPLETION_INTERRUPT_C59, - SCMI_RESERVED_1_C60, - SCMI_CHANNEL_STATUS_C60, - SCMI_RESERVED_2_C60, - SCMI_RESERVED_3_C60, - SCMI_CHANNEL_FLAGS_C60, - SCMI_LENGTH_C60, - SCMI_MESSAGE_HEADER_C60, - SCMI_MESSAGE_PAYLOAD_1_C60, - SCMI_DOORBELL_C60, - SCMI_COMPLETION_INTERRUPT_C60, - SCMI_RESERVED_1_C61, - SCMI_CHANNEL_STATUS_C61, - SCMI_RESERVED_2_C61, - SCMI_RESERVED_3_C61, - SCMI_CHANNEL_FLAGS_C61, - SCMI_LENGTH_C61, - SCMI_MESSAGE_HEADER_C61, - SCMI_MESSAGE_PAYLOAD_1_C61, - SCMI_DOORBELL_C61, - SCMI_COMPLETION_INTERRUPT_C61, - SCMI_RESERVED_1_C62, - SCMI_CHANNEL_STATUS_C62, - SCMI_RESERVED_2_C62, - SCMI_RESERVED_3_C62, - SCMI_CHANNEL_FLAGS_C62, - SCMI_LENGTH_C62, - SCMI_MESSAGE_HEADER_C62, - SCMI_MESSAGE_PAYLOAD_1_C62, - SCMI_DOORBELL_C62, - SCMI_COMPLETION_INTERRUPT_C62, - SCMI_RESERVED_1_C63, - SCMI_CHANNEL_STATUS_C63, - SCMI_RESERVED_2_C63, - SCMI_RESERVED_3_C63, - SCMI_CHANNEL_FLAGS_C63, - SCMI_LENGTH_C63, - SCMI_MESSAGE_HEADER_C63, - SCMI_MESSAGE_PAYLOAD_1_C63, - SCMI_DOORBELL_C63, - SCMI_COMPLETION_INTERRUPT_C63, - SCMI_RESERVED_1_C64, - SCMI_CHANNEL_STATUS_C64, - SCMI_RESERVED_2_C64, - SCMI_RESERVED_3_C64, - SCMI_CHANNEL_FLAGS_C64, - SCMI_LENGTH_C64, - SCMI_MESSAGE_HEADER_C64, - SCMI_MESSAGE_PAYLOAD_1_C64, - SCMI_DOORBELL_C64, - SCMI_COMPLETION_INTERRUPT_C64, - SCMI_RESERVED_1_C65, - SCMI_CHANNEL_STATUS_C65, - SCMI_RESERVED_2_C65, - SCMI_RESERVED_3_C65, - SCMI_CHANNEL_FLAGS_C65, - SCMI_LENGTH_C65, - SCMI_MESSAGE_HEADER_C65, - SCMI_MESSAGE_PAYLOAD_1_C65, - SCMI_DOORBELL_C65, - SCMI_COMPLETION_INTERRUPT_C65, - SCMI_RESERVED_1_C66, - SCMI_CHANNEL_STATUS_C66, - SCMI_RESERVED_2_C66, - SCMI_RESERVED_3_C66, - SCMI_CHANNEL_FLAGS_C66, - SCMI_LENGTH_C66, - SCMI_MESSAGE_HEADER_C66, - SCMI_MESSAGE_PAYLOAD_1_C66, - SCMI_DOORBELL_C66, - SCMI_COMPLETION_INTERRUPT_C66, - SCMI_RESERVED_1_C67, - SCMI_CHANNEL_STATUS_C67, - SCMI_RESERVED_2_C67, - SCMI_RESERVED_3_C67, - SCMI_CHANNEL_FLAGS_C67, - SCMI_LENGTH_C67, - SCMI_MESSAGE_HEADER_C67, - SCMI_MESSAGE_PAYLOAD_1_C67, - SCMI_DOORBELL_C67, - SCMI_COMPLETION_INTERRUPT_C67, - SCMI_RESERVED_1_C68, - SCMI_CHANNEL_STATUS_C68, - SCMI_RESERVED_2_C68, - SCMI_RESERVED_3_C68, - SCMI_CHANNEL_FLAGS_C68, - SCMI_LENGTH_C68, - SCMI_MESSAGE_HEADER_C68, - SCMI_MESSAGE_PAYLOAD_1_C68, - SCMI_DOORBELL_C68, - SCMI_COMPLETION_INTERRUPT_C68, - SCMI_RESERVED_1_C69, - SCMI_CHANNEL_STATUS_C69, - SCMI_RESERVED_2_C69, - SCMI_RESERVED_3_C69, - SCMI_CHANNEL_FLAGS_C69, - SCMI_LENGTH_C69, - SCMI_MESSAGE_HEADER_C69, - SCMI_MESSAGE_PAYLOAD_1_C69, - SCMI_DOORBELL_C69, - SCMI_COMPLETION_INTERRUPT_C69, - SCMI_RESERVED_1_C70, - SCMI_CHANNEL_STATUS_C70, - SCMI_RESERVED_2_C70, - SCMI_RESERVED_3_C70, - SCMI_CHANNEL_FLAGS_C70, - SCMI_LENGTH_C70, - SCMI_MESSAGE_HEADER_C70, - SCMI_MESSAGE_PAYLOAD_1_C70, - SCMI_DOORBELL_C70, - SCMI_COMPLETION_INTERRUPT_C70, - SCMI_RESERVED_1_C71, - SCMI_CHANNEL_STATUS_C71, - SCMI_RESERVED_2_C71, - SCMI_RESERVED_3_C71, - SCMI_CHANNEL_FLAGS_C71, - SCMI_LENGTH_C71, - SCMI_MESSAGE_HEADER_C71, - SCMI_MESSAGE_PAYLOAD_1_C71, - SCMI_DOORBELL_C71, - SCMI_COMPLETION_INTERRUPT_C71, - SCMI_RESERVED_1_C72, - SCMI_CHANNEL_STATUS_C72, - SCMI_RESERVED_2_C72, - SCMI_RESERVED_3_C72, - SCMI_CHANNEL_FLAGS_C72, - SCMI_LENGTH_C72, - SCMI_MESSAGE_HEADER_C72, - SCMI_MESSAGE_PAYLOAD_1_C72, - SCMI_DOORBELL_C72, - SCMI_COMPLETION_INTERRUPT_C72, - SCMI_RESERVED_1_C73, - SCMI_CHANNEL_STATUS_C73, - SCMI_RESERVED_2_C73, - SCMI_RESERVED_3_C73, - SCMI_CHANNEL_FLAGS_C73, - SCMI_LENGTH_C73, - SCMI_MESSAGE_HEADER_C73, - SCMI_MESSAGE_PAYLOAD_1_C73, - SCMI_DOORBELL_C73, - SCMI_COMPLETION_INTERRUPT_C73, - SCMI_RESERVED_1_C74, - SCMI_CHANNEL_STATUS_C74, - SCMI_RESERVED_2_C74, - SCMI_RESERVED_3_C74, - SCMI_CHANNEL_FLAGS_C74, - SCMI_LENGTH_C74, - SCMI_MESSAGE_HEADER_C74, - SCMI_MESSAGE_PAYLOAD_1_C74, - SCMI_DOORBELL_C74, - SCMI_COMPLETION_INTERRUPT_C74, - SCMI_RESERVED_1_C75, - SCMI_CHANNEL_STATUS_C75, - SCMI_RESERVED_2_C75, - SCMI_RESERVED_3_C75, - SCMI_CHANNEL_FLAGS_C75, - SCMI_LENGTH_C75, - SCMI_MESSAGE_HEADER_C75, - SCMI_MESSAGE_PAYLOAD_1_C75, - SCMI_DOORBELL_C75, - SCMI_COMPLETION_INTERRUPT_C75, - SCMI_RESERVED_1_C76, - SCMI_CHANNEL_STATUS_C76, - SCMI_RESERVED_2_C76, - SCMI_RESERVED_3_C76, - SCMI_CHANNEL_FLAGS_C76, - SCMI_LENGTH_C76, - SCMI_MESSAGE_HEADER_C76, - SCMI_MESSAGE_PAYLOAD_1_C76, - SCMI_DOORBELL_C76, - SCMI_COMPLETION_INTERRUPT_C76, - SCMI_RESERVED_1_C77, - SCMI_CHANNEL_STATUS_C77, - SCMI_RESERVED_2_C77, - SCMI_RESERVED_3_C77, - SCMI_CHANNEL_FLAGS_C77, - SCMI_LENGTH_C77, - SCMI_MESSAGE_HEADER_C77, - SCMI_MESSAGE_PAYLOAD_1_C77, - SCMI_DOORBELL_C77, - SCMI_COMPLETION_INTERRUPT_C77, - SCMI_RESERVED_1_C78, - SCMI_CHANNEL_STATUS_C78, - SCMI_RESERVED_2_C78, - SCMI_RESERVED_3_C78, - SCMI_CHANNEL_FLAGS_C78, - SCMI_LENGTH_C78, - SCMI_MESSAGE_HEADER_C78, - SCMI_MESSAGE_PAYLOAD_1_C78, - SCMI_DOORBELL_C78, - SCMI_COMPLETION_INTERRUPT_C78, - SCMI_RESERVED_1_C79, - SCMI_CHANNEL_STATUS_C79, - SCMI_RESERVED_2_C79, - SCMI_RESERVED_3_C79, - SCMI_CHANNEL_FLAGS_C79, - SCMI_LENGTH_C79, - SCMI_MESSAGE_HEADER_C79, - SCMI_MESSAGE_PAYLOAD_1_C79, - SCMI_DOORBELL_C79, - SCMI_COMPLETION_INTERRUPT_C79, - SCMI_RESERVED_1_C80, - SCMI_CHANNEL_STATUS_C80, - SCMI_RESERVED_2_C80, - SCMI_RESERVED_3_C80, - SCMI_CHANNEL_FLAGS_C80, - SCMI_LENGTH_C80, - SCMI_MESSAGE_HEADER_C80, - SCMI_MESSAGE_PAYLOAD_1_C80, - SCMI_DOORBELL_C80, - SCMI_COMPLETION_INTERRUPT_C80, - SCMI_RESERVED_1_C81, - SCMI_CHANNEL_STATUS_C81, - SCMI_RESERVED_2_C81, - SCMI_RESERVED_3_C81, - SCMI_CHANNEL_FLAGS_C81, - SCMI_LENGTH_C81, - SCMI_MESSAGE_HEADER_C81, - SCMI_MESSAGE_PAYLOAD_1_C81, - SCMI_DOORBELL_C81, - SCMI_COMPLETION_INTERRUPT_C81, - SCMI_RESERVED_1_C82, - SCMI_CHANNEL_STATUS_C82, - SCMI_RESERVED_2_C82, - SCMI_RESERVED_3_C82, - SCMI_CHANNEL_FLAGS_C82, - SCMI_LENGTH_C82, - SCMI_MESSAGE_HEADER_C82, - SCMI_MESSAGE_PAYLOAD_1_C82, - SCMI_DOORBELL_C82, - SCMI_COMPLETION_INTERRUPT_C82, - SCMI_RESERVED_1_C83, - SCMI_CHANNEL_STATUS_C83, - SCMI_RESERVED_2_C83, - SCMI_RESERVED_3_C83, - SCMI_CHANNEL_FLAGS_C83, - SCMI_LENGTH_C83, - SCMI_MESSAGE_HEADER_C83, - SCMI_MESSAGE_PAYLOAD_1_C83, - SCMI_DOORBELL_C83, - SCMI_COMPLETION_INTERRUPT_C83, - SCMI_RESERVED_1_C84, - SCMI_CHANNEL_STATUS_C84, - SCMI_RESERVED_2_C84, - SCMI_RESERVED_3_C84, - SCMI_CHANNEL_FLAGS_C84, - SCMI_LENGTH_C84, - SCMI_MESSAGE_HEADER_C84, - SCMI_MESSAGE_PAYLOAD_1_C84, - SCMI_DOORBELL_C84, - SCMI_COMPLETION_INTERRUPT_C84, - SCMI_RESERVED_1_C85, - SCMI_CHANNEL_STATUS_C85, - SCMI_RESERVED_2_C85, - SCMI_RESERVED_3_C85, - SCMI_CHANNEL_FLAGS_C85, - SCMI_LENGTH_C85, - SCMI_MESSAGE_HEADER_C85, - SCMI_MESSAGE_PAYLOAD_1_C85, - SCMI_DOORBELL_C85, - SCMI_COMPLETION_INTERRUPT_C85, - SCMI_RESERVED_1_C86, - SCMI_CHANNEL_STATUS_C86, - SCMI_RESERVED_2_C86, - SCMI_RESERVED_3_C86, - SCMI_CHANNEL_FLAGS_C86, - SCMI_LENGTH_C86, - SCMI_MESSAGE_HEADER_C86, - SCMI_MESSAGE_PAYLOAD_1_C86, - SCMI_DOORBELL_C86, - SCMI_COMPLETION_INTERRUPT_C86, - SCMI_RESERVED_1_C87, - SCMI_CHANNEL_STATUS_C87, - SCMI_RESERVED_2_C87, - SCMI_RESERVED_3_C87, - SCMI_CHANNEL_FLAGS_C87, - SCMI_LENGTH_C87, - SCMI_MESSAGE_HEADER_C87, - SCMI_MESSAGE_PAYLOAD_1_C87, - SCMI_DOORBELL_C87, - SCMI_COMPLETION_INTERRUPT_C87, - SCMI_RESERVED_1_C88, - SCMI_CHANNEL_STATUS_C88, - SCMI_RESERVED_2_C88, - SCMI_RESERVED_3_C88, - SCMI_CHANNEL_FLAGS_C88, - SCMI_LENGTH_C88, - SCMI_MESSAGE_HEADER_C88, - SCMI_MESSAGE_PAYLOAD_1_C88, - SCMI_DOORBELL_C88, - SCMI_COMPLETION_INTERRUPT_C88, - SCMI_RESERVED_1_C89, - SCMI_CHANNEL_STATUS_C89, - SCMI_RESERVED_2_C89, - SCMI_RESERVED_3_C89, - SCMI_CHANNEL_FLAGS_C89, - SCMI_LENGTH_C89, - SCMI_MESSAGE_HEADER_C89, - SCMI_MESSAGE_PAYLOAD_1_C89, - SCMI_DOORBELL_C89, - SCMI_COMPLETION_INTERRUPT_C89, - SCMI_RESERVED_1_C90, - SCMI_CHANNEL_STATUS_C90, - SCMI_RESERVED_2_C90, - SCMI_RESERVED_3_C90, - SCMI_CHANNEL_FLAGS_C90, - SCMI_LENGTH_C90, - SCMI_MESSAGE_HEADER_C90, - SCMI_MESSAGE_PAYLOAD_1_C90, - SCMI_DOORBELL_C90, - SCMI_COMPLETION_INTERRUPT_C90, - SCMI_RESERVED_1_C91, - SCMI_CHANNEL_STATUS_C91, - SCMI_RESERVED_2_C91, - SCMI_RESERVED_3_C91, - SCMI_CHANNEL_FLAGS_C91, - SCMI_LENGTH_C91, - SCMI_MESSAGE_HEADER_C91, - SCMI_MESSAGE_PAYLOAD_1_C91, - SCMI_DOORBELL_C91, - SCMI_COMPLETION_INTERRUPT_C91, - SCMI_RESERVED_1_C92, - SCMI_CHANNEL_STATUS_C92, - SCMI_RESERVED_2_C92, - SCMI_RESERVED_3_C92, - SCMI_CHANNEL_FLAGS_C92, - SCMI_LENGTH_C92, - SCMI_MESSAGE_HEADER_C92, - SCMI_MESSAGE_PAYLOAD_1_C92, - SCMI_DOORBELL_C92, - SCMI_COMPLETION_INTERRUPT_C92, - SCMI_RESERVED_1_C93, - SCMI_CHANNEL_STATUS_C93, - SCMI_RESERVED_2_C93, - SCMI_RESERVED_3_C93, - SCMI_CHANNEL_FLAGS_C93, - SCMI_LENGTH_C93, - SCMI_MESSAGE_HEADER_C93, - SCMI_MESSAGE_PAYLOAD_1_C93, - SCMI_DOORBELL_C93, - SCMI_COMPLETION_INTERRUPT_C93, - SCMI_RESERVED_1_C94, - SCMI_CHANNEL_STATUS_C94, - SCMI_RESERVED_2_C94, - SCMI_RESERVED_3_C94, - SCMI_CHANNEL_FLAGS_C94, - SCMI_LENGTH_C94, - SCMI_MESSAGE_HEADER_C94, - SCMI_MESSAGE_PAYLOAD_1_C94, - SCMI_DOORBELL_C94, - SCMI_COMPLETION_INTERRUPT_C94, - SCMI_RESERVED_1_C95, - SCMI_CHANNEL_STATUS_C95, - SCMI_RESERVED_2_C95, - SCMI_RESERVED_3_C95, - SCMI_CHANNEL_FLAGS_C95, - SCMI_LENGTH_C95, - SCMI_MESSAGE_HEADER_C95, - SCMI_MESSAGE_PAYLOAD_1_C95, - SCMI_DOORBELL_C95, - SCMI_COMPLETION_INTERRUPT_C95, - SCMI_RESERVED_1_C96, - SCMI_CHANNEL_STATUS_C96, - SCMI_RESERVED_2_C96, - SCMI_RESERVED_3_C96, - SCMI_CHANNEL_FLAGS_C96, - SCMI_LENGTH_C96, - SCMI_MESSAGE_HEADER_C96, - SCMI_MESSAGE_PAYLOAD_1_C96, - SCMI_DOORBELL_C96, - SCMI_COMPLETION_INTERRUPT_C96, - SCMI_RESERVED_1_C97, - SCMI_CHANNEL_STATUS_C97, - SCMI_RESERVED_2_C97, - SCMI_RESERVED_3_C97, - SCMI_CHANNEL_FLAGS_C97, - SCMI_LENGTH_C97, - SCMI_MESSAGE_HEADER_C97, - SCMI_MESSAGE_PAYLOAD_1_C97, - SCMI_DOORBELL_C97, - SCMI_COMPLETION_INTERRUPT_C97, - SCMI_RESERVED_1_C98, - SCMI_CHANNEL_STATUS_C98, - SCMI_RESERVED_2_C98, - SCMI_RESERVED_3_C98, - SCMI_CHANNEL_FLAGS_C98, - SCMI_LENGTH_C98, - SCMI_MESSAGE_HEADER_C98, - SCMI_MESSAGE_PAYLOAD_1_C98, - SCMI_DOORBELL_C98, - SCMI_COMPLETION_INTERRUPT_C98, - SCMI_RESERVED_1_C99, - SCMI_CHANNEL_STATUS_C99, - SCMI_RESERVED_2_C99, - SCMI_RESERVED_3_C99, - SCMI_CHANNEL_FLAGS_C99, - SCMI_LENGTH_C99, - SCMI_MESSAGE_HEADER_C99, - SCMI_MESSAGE_PAYLOAD_1_C99, - SCMI_DOORBELL_C99, - SCMI_COMPLETION_INTERRUPT_C99, - SCMI_RESERVED_1_C100, - SCMI_CHANNEL_STATUS_C100, - SCMI_RESERVED_2_C100, - SCMI_RESERVED_3_C100, - SCMI_CHANNEL_FLAGS_C100, - SCMI_LENGTH_C100, - SCMI_MESSAGE_HEADER_C100, - SCMI_MESSAGE_PAYLOAD_1_C100, - SCMI_DOORBELL_C100, - SCMI_COMPLETION_INTERRUPT_C100, - SCMI_RESERVED_1_C101, - SCMI_CHANNEL_STATUS_C101, - SCMI_RESERVED_2_C101, - SCMI_RESERVED_3_C101, - SCMI_CHANNEL_FLAGS_C101, - SCMI_LENGTH_C101, - SCMI_MESSAGE_HEADER_C101, - SCMI_MESSAGE_PAYLOAD_1_C101, - SCMI_DOORBELL_C101, - SCMI_COMPLETION_INTERRUPT_C101, - SCMI_RESERVED_1_C102, - SCMI_CHANNEL_STATUS_C102, - SCMI_RESERVED_2_C102, - SCMI_RESERVED_3_C102, - SCMI_CHANNEL_FLAGS_C102, - SCMI_LENGTH_C102, - SCMI_MESSAGE_HEADER_C102, - SCMI_MESSAGE_PAYLOAD_1_C102, - SCMI_DOORBELL_C102, - SCMI_COMPLETION_INTERRUPT_C102, - SCMI_RESERVED_1_C103, - SCMI_CHANNEL_STATUS_C103, - SCMI_RESERVED_2_C103, - SCMI_RESERVED_3_C103, - SCMI_CHANNEL_FLAGS_C103, - SCMI_LENGTH_C103, - SCMI_MESSAGE_HEADER_C103, - SCMI_MESSAGE_PAYLOAD_1_C103, - SCMI_DOORBELL_C103, - SCMI_COMPLETION_INTERRUPT_C103, - SCMI_RESERVED_1_C104, - SCMI_CHANNEL_STATUS_C104, - SCMI_RESERVED_2_C104, - SCMI_RESERVED_3_C104, - SCMI_CHANNEL_FLAGS_C104, - SCMI_LENGTH_C104, - SCMI_MESSAGE_HEADER_C104, - SCMI_MESSAGE_PAYLOAD_1_C104, - SCMI_DOORBELL_C104, - SCMI_COMPLETION_INTERRUPT_C104, - SCMI_RESERVED_1_C105, - SCMI_CHANNEL_STATUS_C105, - SCMI_RESERVED_2_C105, - SCMI_RESERVED_3_C105, - SCMI_CHANNEL_FLAGS_C105, - SCMI_LENGTH_C105, - SCMI_MESSAGE_HEADER_C105, - SCMI_MESSAGE_PAYLOAD_1_C105, - SCMI_DOORBELL_C105, - SCMI_COMPLETION_INTERRUPT_C105, - SCMI_RESERVED_1_C106, - SCMI_CHANNEL_STATUS_C106, - SCMI_RESERVED_2_C106, - SCMI_RESERVED_3_C106, - SCMI_CHANNEL_FLAGS_C106, - SCMI_LENGTH_C106, - SCMI_MESSAGE_HEADER_C106, - SCMI_MESSAGE_PAYLOAD_1_C106, - SCMI_DOORBELL_C106, - SCMI_COMPLETION_INTERRUPT_C106, - SCMI_RESERVED_1_C107, - SCMI_CHANNEL_STATUS_C107, - SCMI_RESERVED_2_C107, - SCMI_RESERVED_3_C107, - SCMI_CHANNEL_FLAGS_C107, - SCMI_LENGTH_C107, - SCMI_MESSAGE_HEADER_C107, - SCMI_MESSAGE_PAYLOAD_1_C107, - SCMI_DOORBELL_C107, - SCMI_COMPLETION_INTERRUPT_C107, - SCMI_RESERVED_1_C108, - SCMI_CHANNEL_STATUS_C108, - SCMI_RESERVED_2_C108, - SCMI_RESERVED_3_C108, - SCMI_CHANNEL_FLAGS_C108, - SCMI_LENGTH_C108, - SCMI_MESSAGE_HEADER_C108, - SCMI_MESSAGE_PAYLOAD_1_C108, - SCMI_DOORBELL_C108, - SCMI_COMPLETION_INTERRUPT_C108, - SCMI_RESERVED_1_C109, - SCMI_CHANNEL_STATUS_C109, - SCMI_RESERVED_2_C109, - SCMI_RESERVED_3_C109, - SCMI_CHANNEL_FLAGS_C109, - SCMI_LENGTH_C109, - SCMI_MESSAGE_HEADER_C109, - SCMI_MESSAGE_PAYLOAD_1_C109, - SCMI_DOORBELL_C109, - SCMI_COMPLETION_INTERRUPT_C109, - SCMI_RESERVED_1_C110, - SCMI_CHANNEL_STATUS_C110, - SCMI_RESERVED_2_C110, - SCMI_RESERVED_3_C110, - SCMI_CHANNEL_FLAGS_C110, - SCMI_LENGTH_C110, - SCMI_MESSAGE_HEADER_C110, - SCMI_MESSAGE_PAYLOAD_1_C110, - SCMI_DOORBELL_C110, - SCMI_COMPLETION_INTERRUPT_C110, - SCMI_RESERVED_1_C111, - SCMI_CHANNEL_STATUS_C111, - SCMI_RESERVED_2_C111, - SCMI_RESERVED_3_C111, - SCMI_CHANNEL_FLAGS_C111, - SCMI_LENGTH_C111, - SCMI_MESSAGE_HEADER_C111, - SCMI_MESSAGE_PAYLOAD_1_C111, - SCMI_DOORBELL_C111, - SCMI_COMPLETION_INTERRUPT_C111, - SCMI_RESERVED_1_C112, - SCMI_CHANNEL_STATUS_C112, - SCMI_RESERVED_2_C112, - SCMI_RESERVED_3_C112, - SCMI_CHANNEL_FLAGS_C112, - SCMI_LENGTH_C112, - SCMI_MESSAGE_HEADER_C112, - SCMI_MESSAGE_PAYLOAD_1_C112, - SCMI_DOORBELL_C112, - SCMI_COMPLETION_INTERRUPT_C112, - SCMI_RESERVED_1_C113, - SCMI_CHANNEL_STATUS_C113, - SCMI_RESERVED_2_C113, - SCMI_RESERVED_3_C113, - SCMI_CHANNEL_FLAGS_C113, - SCMI_LENGTH_C113, - SCMI_MESSAGE_HEADER_C113, - SCMI_MESSAGE_PAYLOAD_1_C113, - SCMI_DOORBELL_C113, - SCMI_COMPLETION_INTERRUPT_C113, - SCMI_RESERVED_1_C114, - SCMI_CHANNEL_STATUS_C114, - SCMI_RESERVED_2_C114, - SCMI_RESERVED_3_C114, - SCMI_CHANNEL_FLAGS_C114, - SCMI_LENGTH_C114, - SCMI_MESSAGE_HEADER_C114, - SCMI_MESSAGE_PAYLOAD_1_C114, - SCMI_DOORBELL_C114, - SCMI_COMPLETION_INTERRUPT_C114, - SCMI_RESERVED_1_C115, - SCMI_CHANNEL_STATUS_C115, - SCMI_RESERVED_2_C115, - SCMI_RESERVED_3_C115, - SCMI_CHANNEL_FLAGS_C115, - SCMI_LENGTH_C115, - SCMI_MESSAGE_HEADER_C115, - SCMI_MESSAGE_PAYLOAD_1_C115, - SCMI_DOORBELL_C115, - SCMI_COMPLETION_INTERRUPT_C115, - SCMI_RESERVED_1_C116, - SCMI_CHANNEL_STATUS_C116, - SCMI_RESERVED_2_C116, - SCMI_RESERVED_3_C116, - SCMI_CHANNEL_FLAGS_C116, - SCMI_LENGTH_C116, - SCMI_MESSAGE_HEADER_C116, - SCMI_MESSAGE_PAYLOAD_1_C116, - SCMI_DOORBELL_C116, - SCMI_COMPLETION_INTERRUPT_C116, - SCMI_RESERVED_1_C117, - SCMI_CHANNEL_STATUS_C117, - SCMI_RESERVED_2_C117, - SCMI_RESERVED_3_C117, - SCMI_CHANNEL_FLAGS_C117, - SCMI_LENGTH_C117, - SCMI_MESSAGE_HEADER_C117, - SCMI_MESSAGE_PAYLOAD_1_C117, - SCMI_DOORBELL_C117, - SCMI_COMPLETION_INTERRUPT_C117, - SCMI_RESERVED_1_C118, - SCMI_CHANNEL_STATUS_C118, - SCMI_RESERVED_2_C118, - SCMI_RESERVED_3_C118, - SCMI_CHANNEL_FLAGS_C118, - SCMI_LENGTH_C118, - SCMI_MESSAGE_HEADER_C118, - SCMI_MESSAGE_PAYLOAD_1_C118, - SCMI_DOORBELL_C118, - SCMI_COMPLETION_INTERRUPT_C118, - SCMI_RESERVED_1_C119, - SCMI_CHANNEL_STATUS_C119, - SCMI_RESERVED_2_C119, - SCMI_RESERVED_3_C119, - SCMI_CHANNEL_FLAGS_C119, - SCMI_LENGTH_C119, - SCMI_MESSAGE_HEADER_C119, - SCMI_MESSAGE_PAYLOAD_1_C119, - SCMI_DOORBELL_C119, - SCMI_COMPLETION_INTERRUPT_C119, - SCMI_RESERVED_1_C120, - SCMI_CHANNEL_STATUS_C120, - SCMI_RESERVED_2_C120, - SCMI_RESERVED_3_C120, - SCMI_CHANNEL_FLAGS_C120, - SCMI_LENGTH_C120, - SCMI_MESSAGE_HEADER_C120, - SCMI_MESSAGE_PAYLOAD_1_C120, - SCMI_DOORBELL_C120, - SCMI_COMPLETION_INTERRUPT_C120, - SCMI_RESERVED_1_C121, - SCMI_CHANNEL_STATUS_C121, - SCMI_RESERVED_2_C121, - SCMI_RESERVED_3_C121, - SCMI_CHANNEL_FLAGS_C121, - SCMI_LENGTH_C121, - SCMI_MESSAGE_HEADER_C121, - SCMI_MESSAGE_PAYLOAD_1_C121, - SCMI_DOORBELL_C121, - SCMI_COMPLETION_INTERRUPT_C121, - SCMI_RESERVED_1_C122, - SCMI_CHANNEL_STATUS_C122, - SCMI_RESERVED_2_C122, - SCMI_RESERVED_3_C122, - SCMI_CHANNEL_FLAGS_C122, - SCMI_LENGTH_C122, - SCMI_MESSAGE_HEADER_C122, - SCMI_MESSAGE_PAYLOAD_1_C122, - SCMI_DOORBELL_C122, - SCMI_COMPLETION_INTERRUPT_C122, - SCMI_RESERVED_1_C123, - SCMI_CHANNEL_STATUS_C123, - SCMI_RESERVED_2_C123, - SCMI_RESERVED_3_C123, - SCMI_CHANNEL_FLAGS_C123, - SCMI_LENGTH_C123, - SCMI_MESSAGE_HEADER_C123, - SCMI_MESSAGE_PAYLOAD_1_C123, - SCMI_DOORBELL_C123, - SCMI_COMPLETION_INTERRUPT_C123, - SCMI_RESERVED_1_C124, - SCMI_CHANNEL_STATUS_C124, - SCMI_RESERVED_2_C124, - SCMI_RESERVED_3_C124, - SCMI_CHANNEL_FLAGS_C124, - SCMI_LENGTH_C124, - SCMI_MESSAGE_HEADER_C124, - SCMI_MESSAGE_PAYLOAD_1_C124, - SCMI_DOORBELL_C124, - SCMI_COMPLETION_INTERRUPT_C124, - SCMI_RESERVED_1_C125, - SCMI_CHANNEL_STATUS_C125, - SCMI_RESERVED_2_C125, - SCMI_RESERVED_3_C125, - SCMI_CHANNEL_FLAGS_C125, - SCMI_LENGTH_C125, - SCMI_MESSAGE_HEADER_C125, - SCMI_MESSAGE_PAYLOAD_1_C125, - SCMI_DOORBELL_C125, - SCMI_COMPLETION_INTERRUPT_C125, - SCMI_RESERVED_1_C126, - SCMI_CHANNEL_STATUS_C126, - SCMI_RESERVED_2_C126, - SCMI_RESERVED_3_C126, - SCMI_CHANNEL_FLAGS_C126, - SCMI_LENGTH_C126, - SCMI_MESSAGE_HEADER_C126, - SCMI_MESSAGE_PAYLOAD_1_C126, - SCMI_DOORBELL_C126, - SCMI_COMPLETION_INTERRUPT_C126, - SCMI_RESERVED_1_C127, - SCMI_CHANNEL_STATUS_C127, - SCMI_RESERVED_2_C127, - SCMI_RESERVED_3_C127, - SCMI_CHANNEL_FLAGS_C127, - SCMI_LENGTH_C127, - SCMI_MESSAGE_HEADER_C127, - SCMI_MESSAGE_PAYLOAD_1_C127, - SCMI_DOORBELL_C127, - SCMI_COMPLETION_INTERRUPT_C127, - SCMI_RESERVED_1_C128, - SCMI_CHANNEL_STATUS_C128, - SCMI_RESERVED_2_C128, - SCMI_RESERVED_3_C128, - SCMI_CHANNEL_FLAGS_C128, - SCMI_LENGTH_C128, - SCMI_MESSAGE_HEADER_C128, - SCMI_MESSAGE_PAYLOAD_1_C128, - SCMI_DOORBELL_C128, - SCMI_COMPLETION_INTERRUPT_C128, - SCMI_RESERVED_1_C129, - SCMI_CHANNEL_STATUS_C129, - SCMI_RESERVED_2_C129, - SCMI_RESERVED_3_C129, - SCMI_CHANNEL_FLAGS_C129, - SCMI_LENGTH_C129, - SCMI_MESSAGE_HEADER_C129, - SCMI_MESSAGE_PAYLOAD_1_C129, - SCMI_DOORBELL_C129, - SCMI_COMPLETION_INTERRUPT_C129, - SCMI_RESERVED_1_C130, - SCMI_CHANNEL_STATUS_C130, - SCMI_RESERVED_2_C130, - SCMI_RESERVED_3_C130, - SCMI_CHANNEL_FLAGS_C130, - SCMI_LENGTH_C130, - SCMI_MESSAGE_HEADER_C130, - SCMI_MESSAGE_PAYLOAD_1_C130, - SCMI_DOORBELL_C130, - SCMI_COMPLETION_INTERRUPT_C130, - SCMI_RESERVED_1_C131, - SCMI_CHANNEL_STATUS_C131, - SCMI_RESERVED_2_C131, - SCMI_RESERVED_3_C131, - SCMI_CHANNEL_FLAGS_C131, - SCMI_LENGTH_C131, - SCMI_MESSAGE_HEADER_C131, - SCMI_MESSAGE_PAYLOAD_1_C131, - SCMI_DOORBELL_C131, - SCMI_COMPLETION_INTERRUPT_C131, - SCMI_RESERVED_1_C132, - SCMI_CHANNEL_STATUS_C132, - SCMI_RESERVED_2_C132, - SCMI_RESERVED_3_C132, - SCMI_CHANNEL_FLAGS_C132, - SCMI_LENGTH_C132, - SCMI_MESSAGE_HEADER_C132, - SCMI_MESSAGE_PAYLOAD_1_C132, - SCMI_DOORBELL_C132, - SCMI_COMPLETION_INTERRUPT_C132, - SCMI_RESERVED_1_C133, - SCMI_CHANNEL_STATUS_C133, - SCMI_RESERVED_2_C133, - SCMI_RESERVED_3_C133, - SCMI_CHANNEL_FLAGS_C133, - SCMI_LENGTH_C133, - SCMI_MESSAGE_HEADER_C133, - SCMI_MESSAGE_PAYLOAD_1_C133, - SCMI_DOORBELL_C133, - SCMI_COMPLETION_INTERRUPT_C133, - SCMI_RESERVED_1_C134, - SCMI_CHANNEL_STATUS_C134, - SCMI_RESERVED_2_C134, - SCMI_RESERVED_3_C134, - SCMI_CHANNEL_FLAGS_C134, - SCMI_LENGTH_C134, - SCMI_MESSAGE_HEADER_C134, - SCMI_MESSAGE_PAYLOAD_1_C134, - SCMI_DOORBELL_C134, - SCMI_COMPLETION_INTERRUPT_C134, - SCMI_RESERVED_1_C135, - SCMI_CHANNEL_STATUS_C135, - SCMI_RESERVED_2_C135, - SCMI_RESERVED_3_C135, - SCMI_CHANNEL_FLAGS_C135, - SCMI_LENGTH_C135, - SCMI_MESSAGE_HEADER_C135, - SCMI_MESSAGE_PAYLOAD_1_C135, - SCMI_DOORBELL_C135, - SCMI_COMPLETION_INTERRUPT_C135, - SCMI_RESERVED_1_C136, - SCMI_CHANNEL_STATUS_C136, - SCMI_RESERVED_2_C136, - SCMI_RESERVED_3_C136, - SCMI_CHANNEL_FLAGS_C136, - SCMI_LENGTH_C136, - SCMI_MESSAGE_HEADER_C136, - SCMI_MESSAGE_PAYLOAD_1_C136, - SCMI_DOORBELL_C136, - SCMI_COMPLETION_INTERRUPT_C136, - SCMI_RESERVED_1_C137, - SCMI_CHANNEL_STATUS_C137, - SCMI_RESERVED_2_C137, - SCMI_RESERVED_3_C137, - SCMI_CHANNEL_FLAGS_C137, - SCMI_LENGTH_C137, - SCMI_MESSAGE_HEADER_C137, - SCMI_MESSAGE_PAYLOAD_1_C137, - SCMI_DOORBELL_C137, - SCMI_COMPLETION_INTERRUPT_C137, - SCMI_RESERVED_1_C138, - SCMI_CHANNEL_STATUS_C138, - SCMI_RESERVED_2_C138, - SCMI_RESERVED_3_C138, - SCMI_CHANNEL_FLAGS_C138, - SCMI_LENGTH_C138, - SCMI_MESSAGE_HEADER_C138, - SCMI_MESSAGE_PAYLOAD_1_C138, - SCMI_DOORBELL_C138, - SCMI_COMPLETION_INTERRUPT_C138, - SCMI_RESERVED_1_C139, - SCMI_CHANNEL_STATUS_C139, - SCMI_RESERVED_2_C139, - SCMI_RESERVED_3_C139, - SCMI_CHANNEL_FLAGS_C139, - SCMI_LENGTH_C139, - SCMI_MESSAGE_HEADER_C139, - SCMI_MESSAGE_PAYLOAD_1_C139, - SCMI_DOORBELL_C139, - SCMI_COMPLETION_INTERRUPT_C139, - SCMI_RESERVED_1_C140, - SCMI_CHANNEL_STATUS_C140, - SCMI_RESERVED_2_C140, - SCMI_RESERVED_3_C140, - SCMI_CHANNEL_FLAGS_C140, - SCMI_LENGTH_C140, - SCMI_MESSAGE_HEADER_C140, - SCMI_MESSAGE_PAYLOAD_1_C140, - SCMI_DOORBELL_C140, - SCMI_COMPLETION_INTERRUPT_C140, - SCMI_RESERVED_1_C141, - SCMI_CHANNEL_STATUS_C141, - SCMI_RESERVED_2_C141, - SCMI_RESERVED_3_C141, - SCMI_CHANNEL_FLAGS_C141, - SCMI_LENGTH_C141, - SCMI_MESSAGE_HEADER_C141, - SCMI_MESSAGE_PAYLOAD_1_C141, - SCMI_DOORBELL_C141, - SCMI_COMPLETION_INTERRUPT_C141, - SCMI_RESERVED_1_C142, - SCMI_CHANNEL_STATUS_C142, - SCMI_RESERVED_2_C142, - SCMI_RESERVED_3_C142, - SCMI_CHANNEL_FLAGS_C142, - SCMI_LENGTH_C142, - SCMI_MESSAGE_HEADER_C142, - SCMI_MESSAGE_PAYLOAD_1_C142, - SCMI_DOORBELL_C142, - SCMI_COMPLETION_INTERRUPT_C142, - SCMI_RESERVED_1_C143, - SCMI_CHANNEL_STATUS_C143, - SCMI_RESERVED_2_C143, - SCMI_RESERVED_3_C143, - SCMI_CHANNEL_FLAGS_C143, - SCMI_LENGTH_C143, - SCMI_MESSAGE_HEADER_C143, - SCMI_MESSAGE_PAYLOAD_1_C143, - SCMI_DOORBELL_C143, - SCMI_COMPLETION_INTERRUPT_C143, - SCMI_RESERVED_1_C144, - SCMI_CHANNEL_STATUS_C144, - SCMI_RESERVED_2_C144, - SCMI_RESERVED_3_C144, - SCMI_CHANNEL_FLAGS_C144, - SCMI_LENGTH_C144, - SCMI_MESSAGE_HEADER_C144, - SCMI_MESSAGE_PAYLOAD_1_C144, - SCMI_DOORBELL_C144, - SCMI_COMPLETION_INTERRUPT_C144, - SCMI_RESERVED_1_C145, - SCMI_CHANNEL_STATUS_C145, - SCMI_RESERVED_2_C145, - SCMI_RESERVED_3_C145, - SCMI_CHANNEL_FLAGS_C145, - SCMI_LENGTH_C145, - SCMI_MESSAGE_HEADER_C145, - SCMI_MESSAGE_PAYLOAD_1_C145, - SCMI_DOORBELL_C145, - SCMI_COMPLETION_INTERRUPT_C145, - SCMI_RESERVED_1_C146, - SCMI_CHANNEL_STATUS_C146, - SCMI_RESERVED_2_C146, - SCMI_RESERVED_3_C146, - SCMI_CHANNEL_FLAGS_C146, - SCMI_LENGTH_C146, - SCMI_MESSAGE_HEADER_C146, - SCMI_MESSAGE_PAYLOAD_1_C146, - SCMI_DOORBELL_C146, - SCMI_COMPLETION_INTERRUPT_C146 + SCMI_COMPLETION_INTERRUPT_C0 } scmi_id_e; // Register width information to check illegal writes - parameter logic [3:0] SCMI_PERMIT [1470] = '{ - 4'b 1111, // index[ 0] SCMI_RESERVED_1_C0 - 4'b 1111, // index[ 1] SCMI_CHANNEL_STATUS_C0 - 4'b 1111, // index[ 2] SCMI_RESERVED_2_C0 - 4'b 1111, // index[ 3] SCMI_RESERVED_3_C0 - 4'b 1111, // index[ 4] SCMI_CHANNEL_FLAGS_C0 - 4'b 1111, // index[ 5] SCMI_LENGTH_C0 - 4'b 1111, // index[ 6] SCMI_MESSAGE_HEADER_C0 - 4'b 1111, // index[ 7] SCMI_MESSAGE_PAYLOAD_1_C0 - 4'b 1111, // index[ 8] SCMI_DOORBELL_C0 - 4'b 1111, // index[ 9] SCMI_COMPLETION_INTERRUPT_C0 - 4'b 1111, // index[ 10] SCMI_RESERVED_1_C1 - 4'b 1111, // index[ 11] SCMI_CHANNEL_STATUS_C1 - 4'b 1111, // index[ 12] SCMI_RESERVED_2_C1 - 4'b 1111, // index[ 13] SCMI_RESERVED_3_C1 - 4'b 1111, // index[ 14] SCMI_CHANNEL_FLAGS_C1 - 4'b 1111, // index[ 15] SCMI_LENGTH_C1 - 4'b 1111, // index[ 16] SCMI_MESSAGE_HEADER_C1 - 4'b 1111, // index[ 17] SCMI_MESSAGE_PAYLOAD_1_C1 - 4'b 1111, // index[ 18] SCMI_DOORBELL_C1 - 4'b 1111, // index[ 19] SCMI_COMPLETION_INTERRUPT_C1 - 4'b 1111, // index[ 20] SCMI_RESERVED_1_C2 - 4'b 1111, // index[ 21] SCMI_CHANNEL_STATUS_C2 - 4'b 1111, // index[ 22] SCMI_RESERVED_2_C2 - 4'b 1111, // index[ 23] SCMI_RESERVED_3_C2 - 4'b 1111, // index[ 24] SCMI_CHANNEL_FLAGS_C2 - 4'b 1111, // index[ 25] SCMI_LENGTH_C2 - 4'b 1111, // index[ 26] SCMI_MESSAGE_HEADER_C2 - 4'b 1111, // index[ 27] SCMI_MESSAGE_PAYLOAD_1_C2 - 4'b 1111, // index[ 28] SCMI_DOORBELL_C2 - 4'b 1111, // index[ 29] SCMI_COMPLETION_INTERRUPT_C2 - 4'b 1111, // index[ 30] SCMI_RESERVED_1_C3 - 4'b 1111, // index[ 31] SCMI_CHANNEL_STATUS_C3 - 4'b 1111, // index[ 32] SCMI_RESERVED_2_C3 - 4'b 1111, // index[ 33] SCMI_RESERVED_3_C3 - 4'b 1111, // index[ 34] SCMI_CHANNEL_FLAGS_C3 - 4'b 1111, // index[ 35] SCMI_LENGTH_C3 - 4'b 1111, // index[ 36] SCMI_MESSAGE_HEADER_C3 - 4'b 1111, // index[ 37] SCMI_MESSAGE_PAYLOAD_1_C3 - 4'b 1111, // index[ 38] SCMI_DOORBELL_C3 - 4'b 1111, // index[ 39] SCMI_COMPLETION_INTERRUPT_C3 - 4'b 1111, // index[ 40] SCMI_RESERVED_1_C4 - 4'b 1111, // index[ 41] SCMI_CHANNEL_STATUS_C4 - 4'b 1111, // index[ 42] SCMI_RESERVED_2_C4 - 4'b 1111, // index[ 43] SCMI_RESERVED_3_C4 - 4'b 1111, // index[ 44] SCMI_CHANNEL_FLAGS_C4 - 4'b 1111, // index[ 45] SCMI_LENGTH_C4 - 4'b 1111, // index[ 46] SCMI_MESSAGE_HEADER_C4 - 4'b 1111, // index[ 47] SCMI_MESSAGE_PAYLOAD_1_C4 - 4'b 1111, // index[ 48] SCMI_DOORBELL_C4 - 4'b 1111, // index[ 49] SCMI_COMPLETION_INTERRUPT_C4 - 4'b 1111, // index[ 50] SCMI_RESERVED_1_C5 - 4'b 1111, // index[ 51] SCMI_CHANNEL_STATUS_C5 - 4'b 1111, // index[ 52] SCMI_RESERVED_2_C5 - 4'b 1111, // index[ 53] SCMI_RESERVED_3_C5 - 4'b 1111, // index[ 54] SCMI_CHANNEL_FLAGS_C5 - 4'b 1111, // index[ 55] SCMI_LENGTH_C5 - 4'b 1111, // index[ 56] SCMI_MESSAGE_HEADER_C5 - 4'b 1111, // index[ 57] SCMI_MESSAGE_PAYLOAD_1_C5 - 4'b 1111, // index[ 58] SCMI_DOORBELL_C5 - 4'b 1111, // index[ 59] SCMI_COMPLETION_INTERRUPT_C5 - 4'b 1111, // index[ 60] SCMI_RESERVED_1_C6 - 4'b 1111, // index[ 61] SCMI_CHANNEL_STATUS_C6 - 4'b 1111, // index[ 62] SCMI_RESERVED_2_C6 - 4'b 1111, // index[ 63] SCMI_RESERVED_3_C6 - 4'b 1111, // index[ 64] SCMI_CHANNEL_FLAGS_C6 - 4'b 1111, // index[ 65] SCMI_LENGTH_C6 - 4'b 1111, // index[ 66] SCMI_MESSAGE_HEADER_C6 - 4'b 1111, // index[ 67] SCMI_MESSAGE_PAYLOAD_1_C6 - 4'b 1111, // index[ 68] SCMI_DOORBELL_C6 - 4'b 1111, // index[ 69] SCMI_COMPLETION_INTERRUPT_C6 - 4'b 1111, // index[ 70] SCMI_RESERVED_1_C7 - 4'b 1111, // index[ 71] SCMI_CHANNEL_STATUS_C7 - 4'b 1111, // index[ 72] SCMI_RESERVED_2_C7 - 4'b 1111, // index[ 73] SCMI_RESERVED_3_C7 - 4'b 1111, // index[ 74] SCMI_CHANNEL_FLAGS_C7 - 4'b 1111, // index[ 75] SCMI_LENGTH_C7 - 4'b 1111, // index[ 76] SCMI_MESSAGE_HEADER_C7 - 4'b 1111, // index[ 77] SCMI_MESSAGE_PAYLOAD_1_C7 - 4'b 1111, // index[ 78] SCMI_DOORBELL_C7 - 4'b 1111, // index[ 79] SCMI_COMPLETION_INTERRUPT_C7 - 4'b 1111, // index[ 80] SCMI_RESERVED_1_C8 - 4'b 1111, // index[ 81] SCMI_CHANNEL_STATUS_C8 - 4'b 1111, // index[ 82] SCMI_RESERVED_2_C8 - 4'b 1111, // index[ 83] SCMI_RESERVED_3_C8 - 4'b 1111, // index[ 84] SCMI_CHANNEL_FLAGS_C8 - 4'b 1111, // index[ 85] SCMI_LENGTH_C8 - 4'b 1111, // index[ 86] SCMI_MESSAGE_HEADER_C8 - 4'b 1111, // index[ 87] SCMI_MESSAGE_PAYLOAD_1_C8 - 4'b 1111, // index[ 88] SCMI_DOORBELL_C8 - 4'b 1111, // index[ 89] SCMI_COMPLETION_INTERRUPT_C8 - 4'b 1111, // index[ 90] SCMI_RESERVED_1_C9 - 4'b 1111, // index[ 91] SCMI_CHANNEL_STATUS_C9 - 4'b 1111, // index[ 92] SCMI_RESERVED_2_C9 - 4'b 1111, // index[ 93] SCMI_RESERVED_3_C9 - 4'b 1111, // index[ 94] SCMI_CHANNEL_FLAGS_C9 - 4'b 1111, // index[ 95] SCMI_LENGTH_C9 - 4'b 1111, // index[ 96] SCMI_MESSAGE_HEADER_C9 - 4'b 1111, // index[ 97] SCMI_MESSAGE_PAYLOAD_1_C9 - 4'b 1111, // index[ 98] SCMI_DOORBELL_C9 - 4'b 1111, // index[ 99] SCMI_COMPLETION_INTERRUPT_C9 - 4'b 1111, // index[ 100] SCMI_RESERVED_1_C10 - 4'b 1111, // index[ 101] SCMI_CHANNEL_STATUS_C10 - 4'b 1111, // index[ 102] SCMI_RESERVED_2_C10 - 4'b 1111, // index[ 103] SCMI_RESERVED_3_C10 - 4'b 1111, // index[ 104] SCMI_CHANNEL_FLAGS_C10 - 4'b 1111, // index[ 105] SCMI_LENGTH_C10 - 4'b 1111, // index[ 106] SCMI_MESSAGE_HEADER_C10 - 4'b 1111, // index[ 107] SCMI_MESSAGE_PAYLOAD_1_C10 - 4'b 1111, // index[ 108] SCMI_DOORBELL_C10 - 4'b 1111, // index[ 109] SCMI_COMPLETION_INTERRUPT_C10 - 4'b 1111, // index[ 110] SCMI_RESERVED_1_C11 - 4'b 1111, // index[ 111] SCMI_CHANNEL_STATUS_C11 - 4'b 1111, // index[ 112] SCMI_RESERVED_2_C11 - 4'b 1111, // index[ 113] SCMI_RESERVED_3_C11 - 4'b 1111, // index[ 114] SCMI_CHANNEL_FLAGS_C11 - 4'b 1111, // index[ 115] SCMI_LENGTH_C11 - 4'b 1111, // index[ 116] SCMI_MESSAGE_HEADER_C11 - 4'b 1111, // index[ 117] SCMI_MESSAGE_PAYLOAD_1_C11 - 4'b 1111, // index[ 118] SCMI_DOORBELL_C11 - 4'b 1111, // index[ 119] SCMI_COMPLETION_INTERRUPT_C11 - 4'b 1111, // index[ 120] SCMI_RESERVED_1_C12 - 4'b 1111, // index[ 121] SCMI_CHANNEL_STATUS_C12 - 4'b 1111, // index[ 122] SCMI_RESERVED_2_C12 - 4'b 1111, // index[ 123] SCMI_RESERVED_3_C12 - 4'b 1111, // index[ 124] SCMI_CHANNEL_FLAGS_C12 - 4'b 1111, // index[ 125] SCMI_LENGTH_C12 - 4'b 1111, // index[ 126] SCMI_MESSAGE_HEADER_C12 - 4'b 1111, // index[ 127] SCMI_MESSAGE_PAYLOAD_1_C12 - 4'b 1111, // index[ 128] SCMI_DOORBELL_C12 - 4'b 1111, // index[ 129] SCMI_COMPLETION_INTERRUPT_C12 - 4'b 1111, // index[ 130] SCMI_RESERVED_1_C13 - 4'b 1111, // index[ 131] SCMI_CHANNEL_STATUS_C13 - 4'b 1111, // index[ 132] SCMI_RESERVED_2_C13 - 4'b 1111, // index[ 133] SCMI_RESERVED_3_C13 - 4'b 1111, // index[ 134] SCMI_CHANNEL_FLAGS_C13 - 4'b 1111, // index[ 135] SCMI_LENGTH_C13 - 4'b 1111, // index[ 136] SCMI_MESSAGE_HEADER_C13 - 4'b 1111, // index[ 137] SCMI_MESSAGE_PAYLOAD_1_C13 - 4'b 1111, // index[ 138] SCMI_DOORBELL_C13 - 4'b 1111, // index[ 139] SCMI_COMPLETION_INTERRUPT_C13 - 4'b 1111, // index[ 140] SCMI_RESERVED_1_C14 - 4'b 1111, // index[ 141] SCMI_CHANNEL_STATUS_C14 - 4'b 1111, // index[ 142] SCMI_RESERVED_2_C14 - 4'b 1111, // index[ 143] SCMI_RESERVED_3_C14 - 4'b 1111, // index[ 144] SCMI_CHANNEL_FLAGS_C14 - 4'b 1111, // index[ 145] SCMI_LENGTH_C14 - 4'b 1111, // index[ 146] SCMI_MESSAGE_HEADER_C14 - 4'b 1111, // index[ 147] SCMI_MESSAGE_PAYLOAD_1_C14 - 4'b 1111, // index[ 148] SCMI_DOORBELL_C14 - 4'b 1111, // index[ 149] SCMI_COMPLETION_INTERRUPT_C14 - 4'b 1111, // index[ 150] SCMI_RESERVED_1_C15 - 4'b 1111, // index[ 151] SCMI_CHANNEL_STATUS_C15 - 4'b 1111, // index[ 152] SCMI_RESERVED_2_C15 - 4'b 1111, // index[ 153] SCMI_RESERVED_3_C15 - 4'b 1111, // index[ 154] SCMI_CHANNEL_FLAGS_C15 - 4'b 1111, // index[ 155] SCMI_LENGTH_C15 - 4'b 1111, // index[ 156] SCMI_MESSAGE_HEADER_C15 - 4'b 1111, // index[ 157] SCMI_MESSAGE_PAYLOAD_1_C15 - 4'b 1111, // index[ 158] SCMI_DOORBELL_C15 - 4'b 1111, // index[ 159] SCMI_COMPLETION_INTERRUPT_C15 - 4'b 1111, // index[ 160] SCMI_RESERVED_1_C16 - 4'b 1111, // index[ 161] SCMI_CHANNEL_STATUS_C16 - 4'b 1111, // index[ 162] SCMI_RESERVED_2_C16 - 4'b 1111, // index[ 163] SCMI_RESERVED_3_C16 - 4'b 1111, // index[ 164] SCMI_CHANNEL_FLAGS_C16 - 4'b 1111, // index[ 165] SCMI_LENGTH_C16 - 4'b 1111, // index[ 166] SCMI_MESSAGE_HEADER_C16 - 4'b 1111, // index[ 167] SCMI_MESSAGE_PAYLOAD_1_C16 - 4'b 1111, // index[ 168] SCMI_DOORBELL_C16 - 4'b 1111, // index[ 169] SCMI_COMPLETION_INTERRUPT_C16 - 4'b 1111, // index[ 170] SCMI_RESERVED_1_C17 - 4'b 1111, // index[ 171] SCMI_CHANNEL_STATUS_C17 - 4'b 1111, // index[ 172] SCMI_RESERVED_2_C17 - 4'b 1111, // index[ 173] SCMI_RESERVED_3_C17 - 4'b 1111, // index[ 174] SCMI_CHANNEL_FLAGS_C17 - 4'b 1111, // index[ 175] SCMI_LENGTH_C17 - 4'b 1111, // index[ 176] SCMI_MESSAGE_HEADER_C17 - 4'b 1111, // index[ 177] SCMI_MESSAGE_PAYLOAD_1_C17 - 4'b 1111, // index[ 178] SCMI_DOORBELL_C17 - 4'b 1111, // index[ 179] SCMI_COMPLETION_INTERRUPT_C17 - 4'b 1111, // index[ 180] SCMI_RESERVED_1_C18 - 4'b 1111, // index[ 181] SCMI_CHANNEL_STATUS_C18 - 4'b 1111, // index[ 182] SCMI_RESERVED_2_C18 - 4'b 1111, // index[ 183] SCMI_RESERVED_3_C18 - 4'b 1111, // index[ 184] SCMI_CHANNEL_FLAGS_C18 - 4'b 1111, // index[ 185] SCMI_LENGTH_C18 - 4'b 1111, // index[ 186] SCMI_MESSAGE_HEADER_C18 - 4'b 1111, // index[ 187] SCMI_MESSAGE_PAYLOAD_1_C18 - 4'b 1111, // index[ 188] SCMI_DOORBELL_C18 - 4'b 1111, // index[ 189] SCMI_COMPLETION_INTERRUPT_C18 - 4'b 1111, // index[ 190] SCMI_RESERVED_1_C19 - 4'b 1111, // index[ 191] SCMI_CHANNEL_STATUS_C19 - 4'b 1111, // index[ 192] SCMI_RESERVED_2_C19 - 4'b 1111, // index[ 193] SCMI_RESERVED_3_C19 - 4'b 1111, // index[ 194] SCMI_CHANNEL_FLAGS_C19 - 4'b 1111, // index[ 195] SCMI_LENGTH_C19 - 4'b 1111, // index[ 196] SCMI_MESSAGE_HEADER_C19 - 4'b 1111, // index[ 197] SCMI_MESSAGE_PAYLOAD_1_C19 - 4'b 1111, // index[ 198] SCMI_DOORBELL_C19 - 4'b 1111, // index[ 199] SCMI_COMPLETION_INTERRUPT_C19 - 4'b 1111, // index[ 200] SCMI_RESERVED_1_C20 - 4'b 1111, // index[ 201] SCMI_CHANNEL_STATUS_C20 - 4'b 1111, // index[ 202] SCMI_RESERVED_2_C20 - 4'b 1111, // index[ 203] SCMI_RESERVED_3_C20 - 4'b 1111, // index[ 204] SCMI_CHANNEL_FLAGS_C20 - 4'b 1111, // index[ 205] SCMI_LENGTH_C20 - 4'b 1111, // index[ 206] SCMI_MESSAGE_HEADER_C20 - 4'b 1111, // index[ 207] SCMI_MESSAGE_PAYLOAD_1_C20 - 4'b 1111, // index[ 208] SCMI_DOORBELL_C20 - 4'b 1111, // index[ 209] SCMI_COMPLETION_INTERRUPT_C20 - 4'b 1111, // index[ 210] SCMI_RESERVED_1_C21 - 4'b 1111, // index[ 211] SCMI_CHANNEL_STATUS_C21 - 4'b 1111, // index[ 212] SCMI_RESERVED_2_C21 - 4'b 1111, // index[ 213] SCMI_RESERVED_3_C21 - 4'b 1111, // index[ 214] SCMI_CHANNEL_FLAGS_C21 - 4'b 1111, // index[ 215] SCMI_LENGTH_C21 - 4'b 1111, // index[ 216] SCMI_MESSAGE_HEADER_C21 - 4'b 1111, // index[ 217] SCMI_MESSAGE_PAYLOAD_1_C21 - 4'b 1111, // index[ 218] SCMI_DOORBELL_C21 - 4'b 1111, // index[ 219] SCMI_COMPLETION_INTERRUPT_C21 - 4'b 1111, // index[ 220] SCMI_RESERVED_1_C22 - 4'b 1111, // index[ 221] SCMI_CHANNEL_STATUS_C22 - 4'b 1111, // index[ 222] SCMI_RESERVED_2_C22 - 4'b 1111, // index[ 223] SCMI_RESERVED_3_C22 - 4'b 1111, // index[ 224] SCMI_CHANNEL_FLAGS_C22 - 4'b 1111, // index[ 225] SCMI_LENGTH_C22 - 4'b 1111, // index[ 226] SCMI_MESSAGE_HEADER_C22 - 4'b 1111, // index[ 227] SCMI_MESSAGE_PAYLOAD_1_C22 - 4'b 1111, // index[ 228] SCMI_DOORBELL_C22 - 4'b 1111, // index[ 229] SCMI_COMPLETION_INTERRUPT_C22 - 4'b 1111, // index[ 230] SCMI_RESERVED_1_C23 - 4'b 1111, // index[ 231] SCMI_CHANNEL_STATUS_C23 - 4'b 1111, // index[ 232] SCMI_RESERVED_2_C23 - 4'b 1111, // index[ 233] SCMI_RESERVED_3_C23 - 4'b 1111, // index[ 234] SCMI_CHANNEL_FLAGS_C23 - 4'b 1111, // index[ 235] SCMI_LENGTH_C23 - 4'b 1111, // index[ 236] SCMI_MESSAGE_HEADER_C23 - 4'b 1111, // index[ 237] SCMI_MESSAGE_PAYLOAD_1_C23 - 4'b 1111, // index[ 238] SCMI_DOORBELL_C23 - 4'b 1111, // index[ 239] SCMI_COMPLETION_INTERRUPT_C23 - 4'b 1111, // index[ 240] SCMI_RESERVED_1_C24 - 4'b 1111, // index[ 241] SCMI_CHANNEL_STATUS_C24 - 4'b 1111, // index[ 242] SCMI_RESERVED_2_C24 - 4'b 1111, // index[ 243] SCMI_RESERVED_3_C24 - 4'b 1111, // index[ 244] SCMI_CHANNEL_FLAGS_C24 - 4'b 1111, // index[ 245] SCMI_LENGTH_C24 - 4'b 1111, // index[ 246] SCMI_MESSAGE_HEADER_C24 - 4'b 1111, // index[ 247] SCMI_MESSAGE_PAYLOAD_1_C24 - 4'b 1111, // index[ 248] SCMI_DOORBELL_C24 - 4'b 1111, // index[ 249] SCMI_COMPLETION_INTERRUPT_C24 - 4'b 1111, // index[ 250] SCMI_RESERVED_1_C25 - 4'b 1111, // index[ 251] SCMI_CHANNEL_STATUS_C25 - 4'b 1111, // index[ 252] SCMI_RESERVED_2_C25 - 4'b 1111, // index[ 253] SCMI_RESERVED_3_C25 - 4'b 1111, // index[ 254] SCMI_CHANNEL_FLAGS_C25 - 4'b 1111, // index[ 255] SCMI_LENGTH_C25 - 4'b 1111, // index[ 256] SCMI_MESSAGE_HEADER_C25 - 4'b 1111, // index[ 257] SCMI_MESSAGE_PAYLOAD_1_C25 - 4'b 1111, // index[ 258] SCMI_DOORBELL_C25 - 4'b 1111, // index[ 259] SCMI_COMPLETION_INTERRUPT_C25 - 4'b 1111, // index[ 260] SCMI_RESERVED_1_C26 - 4'b 1111, // index[ 261] SCMI_CHANNEL_STATUS_C26 - 4'b 1111, // index[ 262] SCMI_RESERVED_2_C26 - 4'b 1111, // index[ 263] SCMI_RESERVED_3_C26 - 4'b 1111, // index[ 264] SCMI_CHANNEL_FLAGS_C26 - 4'b 1111, // index[ 265] SCMI_LENGTH_C26 - 4'b 1111, // index[ 266] SCMI_MESSAGE_HEADER_C26 - 4'b 1111, // index[ 267] SCMI_MESSAGE_PAYLOAD_1_C26 - 4'b 1111, // index[ 268] SCMI_DOORBELL_C26 - 4'b 1111, // index[ 269] SCMI_COMPLETION_INTERRUPT_C26 - 4'b 1111, // index[ 270] SCMI_RESERVED_1_C27 - 4'b 1111, // index[ 271] SCMI_CHANNEL_STATUS_C27 - 4'b 1111, // index[ 272] SCMI_RESERVED_2_C27 - 4'b 1111, // index[ 273] SCMI_RESERVED_3_C27 - 4'b 1111, // index[ 274] SCMI_CHANNEL_FLAGS_C27 - 4'b 1111, // index[ 275] SCMI_LENGTH_C27 - 4'b 1111, // index[ 276] SCMI_MESSAGE_HEADER_C27 - 4'b 1111, // index[ 277] SCMI_MESSAGE_PAYLOAD_1_C27 - 4'b 1111, // index[ 278] SCMI_DOORBELL_C27 - 4'b 1111, // index[ 279] SCMI_COMPLETION_INTERRUPT_C27 - 4'b 1111, // index[ 280] SCMI_RESERVED_1_C28 - 4'b 1111, // index[ 281] SCMI_CHANNEL_STATUS_C28 - 4'b 1111, // index[ 282] SCMI_RESERVED_2_C28 - 4'b 1111, // index[ 283] SCMI_RESERVED_3_C28 - 4'b 1111, // index[ 284] SCMI_CHANNEL_FLAGS_C28 - 4'b 1111, // index[ 285] SCMI_LENGTH_C28 - 4'b 1111, // index[ 286] SCMI_MESSAGE_HEADER_C28 - 4'b 1111, // index[ 287] SCMI_MESSAGE_PAYLOAD_1_C28 - 4'b 1111, // index[ 288] SCMI_DOORBELL_C28 - 4'b 1111, // index[ 289] SCMI_COMPLETION_INTERRUPT_C28 - 4'b 1111, // index[ 290] SCMI_RESERVED_1_C29 - 4'b 1111, // index[ 291] SCMI_CHANNEL_STATUS_C29 - 4'b 1111, // index[ 292] SCMI_RESERVED_2_C29 - 4'b 1111, // index[ 293] SCMI_RESERVED_3_C29 - 4'b 1111, // index[ 294] SCMI_CHANNEL_FLAGS_C29 - 4'b 1111, // index[ 295] SCMI_LENGTH_C29 - 4'b 1111, // index[ 296] SCMI_MESSAGE_HEADER_C29 - 4'b 1111, // index[ 297] SCMI_MESSAGE_PAYLOAD_1_C29 - 4'b 1111, // index[ 298] SCMI_DOORBELL_C29 - 4'b 1111, // index[ 299] SCMI_COMPLETION_INTERRUPT_C29 - 4'b 1111, // index[ 300] SCMI_RESERVED_1_C30 - 4'b 1111, // index[ 301] SCMI_CHANNEL_STATUS_C30 - 4'b 1111, // index[ 302] SCMI_RESERVED_2_C30 - 4'b 1111, // index[ 303] SCMI_RESERVED_3_C30 - 4'b 1111, // index[ 304] SCMI_CHANNEL_FLAGS_C30 - 4'b 1111, // index[ 305] SCMI_LENGTH_C30 - 4'b 1111, // index[ 306] SCMI_MESSAGE_HEADER_C30 - 4'b 1111, // index[ 307] SCMI_MESSAGE_PAYLOAD_1_C30 - 4'b 1111, // index[ 308] SCMI_DOORBELL_C30 - 4'b 1111, // index[ 309] SCMI_COMPLETION_INTERRUPT_C30 - 4'b 1111, // index[ 310] SCMI_RESERVED_1_C31 - 4'b 1111, // index[ 311] SCMI_CHANNEL_STATUS_C31 - 4'b 1111, // index[ 312] SCMI_RESERVED_2_C31 - 4'b 1111, // index[ 313] SCMI_RESERVED_3_C31 - 4'b 1111, // index[ 314] SCMI_CHANNEL_FLAGS_C31 - 4'b 1111, // index[ 315] SCMI_LENGTH_C31 - 4'b 1111, // index[ 316] SCMI_MESSAGE_HEADER_C31 - 4'b 1111, // index[ 317] SCMI_MESSAGE_PAYLOAD_1_C31 - 4'b 1111, // index[ 318] SCMI_DOORBELL_C31 - 4'b 1111, // index[ 319] SCMI_COMPLETION_INTERRUPT_C31 - 4'b 1111, // index[ 320] SCMI_RESERVED_1_C32 - 4'b 1111, // index[ 321] SCMI_CHANNEL_STATUS_C32 - 4'b 1111, // index[ 322] SCMI_RESERVED_2_C32 - 4'b 1111, // index[ 323] SCMI_RESERVED_3_C32 - 4'b 1111, // index[ 324] SCMI_CHANNEL_FLAGS_C32 - 4'b 1111, // index[ 325] SCMI_LENGTH_C32 - 4'b 1111, // index[ 326] SCMI_MESSAGE_HEADER_C32 - 4'b 1111, // index[ 327] SCMI_MESSAGE_PAYLOAD_1_C32 - 4'b 1111, // index[ 328] SCMI_DOORBELL_C32 - 4'b 1111, // index[ 329] SCMI_COMPLETION_INTERRUPT_C32 - 4'b 1111, // index[ 330] SCMI_RESERVED_1_C33 - 4'b 1111, // index[ 331] SCMI_CHANNEL_STATUS_C33 - 4'b 1111, // index[ 332] SCMI_RESERVED_2_C33 - 4'b 1111, // index[ 333] SCMI_RESERVED_3_C33 - 4'b 1111, // index[ 334] SCMI_CHANNEL_FLAGS_C33 - 4'b 1111, // index[ 335] SCMI_LENGTH_C33 - 4'b 1111, // index[ 336] SCMI_MESSAGE_HEADER_C33 - 4'b 1111, // index[ 337] SCMI_MESSAGE_PAYLOAD_1_C33 - 4'b 1111, // index[ 338] SCMI_DOORBELL_C33 - 4'b 1111, // index[ 339] SCMI_COMPLETION_INTERRUPT_C33 - 4'b 1111, // index[ 340] SCMI_RESERVED_1_C34 - 4'b 1111, // index[ 341] SCMI_CHANNEL_STATUS_C34 - 4'b 1111, // index[ 342] SCMI_RESERVED_2_C34 - 4'b 1111, // index[ 343] SCMI_RESERVED_3_C34 - 4'b 1111, // index[ 344] SCMI_CHANNEL_FLAGS_C34 - 4'b 1111, // index[ 345] SCMI_LENGTH_C34 - 4'b 1111, // index[ 346] SCMI_MESSAGE_HEADER_C34 - 4'b 1111, // index[ 347] SCMI_MESSAGE_PAYLOAD_1_C34 - 4'b 1111, // index[ 348] SCMI_DOORBELL_C34 - 4'b 1111, // index[ 349] SCMI_COMPLETION_INTERRUPT_C34 - 4'b 1111, // index[ 350] SCMI_RESERVED_1_C35 - 4'b 1111, // index[ 351] SCMI_CHANNEL_STATUS_C35 - 4'b 1111, // index[ 352] SCMI_RESERVED_2_C35 - 4'b 1111, // index[ 353] SCMI_RESERVED_3_C35 - 4'b 1111, // index[ 354] SCMI_CHANNEL_FLAGS_C35 - 4'b 1111, // index[ 355] SCMI_LENGTH_C35 - 4'b 1111, // index[ 356] SCMI_MESSAGE_HEADER_C35 - 4'b 1111, // index[ 357] SCMI_MESSAGE_PAYLOAD_1_C35 - 4'b 1111, // index[ 358] SCMI_DOORBELL_C35 - 4'b 1111, // index[ 359] SCMI_COMPLETION_INTERRUPT_C35 - 4'b 1111, // index[ 360] SCMI_RESERVED_1_C36 - 4'b 1111, // index[ 361] SCMI_CHANNEL_STATUS_C36 - 4'b 1111, // index[ 362] SCMI_RESERVED_2_C36 - 4'b 1111, // index[ 363] SCMI_RESERVED_3_C36 - 4'b 1111, // index[ 364] SCMI_CHANNEL_FLAGS_C36 - 4'b 1111, // index[ 365] SCMI_LENGTH_C36 - 4'b 1111, // index[ 366] SCMI_MESSAGE_HEADER_C36 - 4'b 1111, // index[ 367] SCMI_MESSAGE_PAYLOAD_1_C36 - 4'b 1111, // index[ 368] SCMI_DOORBELL_C36 - 4'b 1111, // index[ 369] SCMI_COMPLETION_INTERRUPT_C36 - 4'b 1111, // index[ 370] SCMI_RESERVED_1_C37 - 4'b 1111, // index[ 371] SCMI_CHANNEL_STATUS_C37 - 4'b 1111, // index[ 372] SCMI_RESERVED_2_C37 - 4'b 1111, // index[ 373] SCMI_RESERVED_3_C37 - 4'b 1111, // index[ 374] SCMI_CHANNEL_FLAGS_C37 - 4'b 1111, // index[ 375] SCMI_LENGTH_C37 - 4'b 1111, // index[ 376] SCMI_MESSAGE_HEADER_C37 - 4'b 1111, // index[ 377] SCMI_MESSAGE_PAYLOAD_1_C37 - 4'b 1111, // index[ 378] SCMI_DOORBELL_C37 - 4'b 1111, // index[ 379] SCMI_COMPLETION_INTERRUPT_C37 - 4'b 1111, // index[ 380] SCMI_RESERVED_1_C38 - 4'b 1111, // index[ 381] SCMI_CHANNEL_STATUS_C38 - 4'b 1111, // index[ 382] SCMI_RESERVED_2_C38 - 4'b 1111, // index[ 383] SCMI_RESERVED_3_C38 - 4'b 1111, // index[ 384] SCMI_CHANNEL_FLAGS_C38 - 4'b 1111, // index[ 385] SCMI_LENGTH_C38 - 4'b 1111, // index[ 386] SCMI_MESSAGE_HEADER_C38 - 4'b 1111, // index[ 387] SCMI_MESSAGE_PAYLOAD_1_C38 - 4'b 1111, // index[ 388] SCMI_DOORBELL_C38 - 4'b 1111, // index[ 389] SCMI_COMPLETION_INTERRUPT_C38 - 4'b 1111, // index[ 390] SCMI_RESERVED_1_C39 - 4'b 1111, // index[ 391] SCMI_CHANNEL_STATUS_C39 - 4'b 1111, // index[ 392] SCMI_RESERVED_2_C39 - 4'b 1111, // index[ 393] SCMI_RESERVED_3_C39 - 4'b 1111, // index[ 394] SCMI_CHANNEL_FLAGS_C39 - 4'b 1111, // index[ 395] SCMI_LENGTH_C39 - 4'b 1111, // index[ 396] SCMI_MESSAGE_HEADER_C39 - 4'b 1111, // index[ 397] SCMI_MESSAGE_PAYLOAD_1_C39 - 4'b 1111, // index[ 398] SCMI_DOORBELL_C39 - 4'b 1111, // index[ 399] SCMI_COMPLETION_INTERRUPT_C39 - 4'b 1111, // index[ 400] SCMI_RESERVED_1_C40 - 4'b 1111, // index[ 401] SCMI_CHANNEL_STATUS_C40 - 4'b 1111, // index[ 402] SCMI_RESERVED_2_C40 - 4'b 1111, // index[ 403] SCMI_RESERVED_3_C40 - 4'b 1111, // index[ 404] SCMI_CHANNEL_FLAGS_C40 - 4'b 1111, // index[ 405] SCMI_LENGTH_C40 - 4'b 1111, // index[ 406] SCMI_MESSAGE_HEADER_C40 - 4'b 1111, // index[ 407] SCMI_MESSAGE_PAYLOAD_1_C40 - 4'b 1111, // index[ 408] SCMI_DOORBELL_C40 - 4'b 1111, // index[ 409] SCMI_COMPLETION_INTERRUPT_C40 - 4'b 1111, // index[ 410] SCMI_RESERVED_1_C41 - 4'b 1111, // index[ 411] SCMI_CHANNEL_STATUS_C41 - 4'b 1111, // index[ 412] SCMI_RESERVED_2_C41 - 4'b 1111, // index[ 413] SCMI_RESERVED_3_C41 - 4'b 1111, // index[ 414] SCMI_CHANNEL_FLAGS_C41 - 4'b 1111, // index[ 415] SCMI_LENGTH_C41 - 4'b 1111, // index[ 416] SCMI_MESSAGE_HEADER_C41 - 4'b 1111, // index[ 417] SCMI_MESSAGE_PAYLOAD_1_C41 - 4'b 1111, // index[ 418] SCMI_DOORBELL_C41 - 4'b 1111, // index[ 419] SCMI_COMPLETION_INTERRUPT_C41 - 4'b 1111, // index[ 420] SCMI_RESERVED_1_C42 - 4'b 1111, // index[ 421] SCMI_CHANNEL_STATUS_C42 - 4'b 1111, // index[ 422] SCMI_RESERVED_2_C42 - 4'b 1111, // index[ 423] SCMI_RESERVED_3_C42 - 4'b 1111, // index[ 424] SCMI_CHANNEL_FLAGS_C42 - 4'b 1111, // index[ 425] SCMI_LENGTH_C42 - 4'b 1111, // index[ 426] SCMI_MESSAGE_HEADER_C42 - 4'b 1111, // index[ 427] SCMI_MESSAGE_PAYLOAD_1_C42 - 4'b 1111, // index[ 428] SCMI_DOORBELL_C42 - 4'b 1111, // index[ 429] SCMI_COMPLETION_INTERRUPT_C42 - 4'b 1111, // index[ 430] SCMI_RESERVED_1_C43 - 4'b 1111, // index[ 431] SCMI_CHANNEL_STATUS_C43 - 4'b 1111, // index[ 432] SCMI_RESERVED_2_C43 - 4'b 1111, // index[ 433] SCMI_RESERVED_3_C43 - 4'b 1111, // index[ 434] SCMI_CHANNEL_FLAGS_C43 - 4'b 1111, // index[ 435] SCMI_LENGTH_C43 - 4'b 1111, // index[ 436] SCMI_MESSAGE_HEADER_C43 - 4'b 1111, // index[ 437] SCMI_MESSAGE_PAYLOAD_1_C43 - 4'b 1111, // index[ 438] SCMI_DOORBELL_C43 - 4'b 1111, // index[ 439] SCMI_COMPLETION_INTERRUPT_C43 - 4'b 1111, // index[ 440] SCMI_RESERVED_1_C44 - 4'b 1111, // index[ 441] SCMI_CHANNEL_STATUS_C44 - 4'b 1111, // index[ 442] SCMI_RESERVED_2_C44 - 4'b 1111, // index[ 443] SCMI_RESERVED_3_C44 - 4'b 1111, // index[ 444] SCMI_CHANNEL_FLAGS_C44 - 4'b 1111, // index[ 445] SCMI_LENGTH_C44 - 4'b 1111, // index[ 446] SCMI_MESSAGE_HEADER_C44 - 4'b 1111, // index[ 447] SCMI_MESSAGE_PAYLOAD_1_C44 - 4'b 1111, // index[ 448] SCMI_DOORBELL_C44 - 4'b 1111, // index[ 449] SCMI_COMPLETION_INTERRUPT_C44 - 4'b 1111, // index[ 450] SCMI_RESERVED_1_C45 - 4'b 1111, // index[ 451] SCMI_CHANNEL_STATUS_C45 - 4'b 1111, // index[ 452] SCMI_RESERVED_2_C45 - 4'b 1111, // index[ 453] SCMI_RESERVED_3_C45 - 4'b 1111, // index[ 454] SCMI_CHANNEL_FLAGS_C45 - 4'b 1111, // index[ 455] SCMI_LENGTH_C45 - 4'b 1111, // index[ 456] SCMI_MESSAGE_HEADER_C45 - 4'b 1111, // index[ 457] SCMI_MESSAGE_PAYLOAD_1_C45 - 4'b 1111, // index[ 458] SCMI_DOORBELL_C45 - 4'b 1111, // index[ 459] SCMI_COMPLETION_INTERRUPT_C45 - 4'b 1111, // index[ 460] SCMI_RESERVED_1_C46 - 4'b 1111, // index[ 461] SCMI_CHANNEL_STATUS_C46 - 4'b 1111, // index[ 462] SCMI_RESERVED_2_C46 - 4'b 1111, // index[ 463] SCMI_RESERVED_3_C46 - 4'b 1111, // index[ 464] SCMI_CHANNEL_FLAGS_C46 - 4'b 1111, // index[ 465] SCMI_LENGTH_C46 - 4'b 1111, // index[ 466] SCMI_MESSAGE_HEADER_C46 - 4'b 1111, // index[ 467] SCMI_MESSAGE_PAYLOAD_1_C46 - 4'b 1111, // index[ 468] SCMI_DOORBELL_C46 - 4'b 1111, // index[ 469] SCMI_COMPLETION_INTERRUPT_C46 - 4'b 1111, // index[ 470] SCMI_RESERVED_1_C47 - 4'b 1111, // index[ 471] SCMI_CHANNEL_STATUS_C47 - 4'b 1111, // index[ 472] SCMI_RESERVED_2_C47 - 4'b 1111, // index[ 473] SCMI_RESERVED_3_C47 - 4'b 1111, // index[ 474] SCMI_CHANNEL_FLAGS_C47 - 4'b 1111, // index[ 475] SCMI_LENGTH_C47 - 4'b 1111, // index[ 476] SCMI_MESSAGE_HEADER_C47 - 4'b 1111, // index[ 477] SCMI_MESSAGE_PAYLOAD_1_C47 - 4'b 1111, // index[ 478] SCMI_DOORBELL_C47 - 4'b 1111, // index[ 479] SCMI_COMPLETION_INTERRUPT_C47 - 4'b 1111, // index[ 480] SCMI_RESERVED_1_C48 - 4'b 1111, // index[ 481] SCMI_CHANNEL_STATUS_C48 - 4'b 1111, // index[ 482] SCMI_RESERVED_2_C48 - 4'b 1111, // index[ 483] SCMI_RESERVED_3_C48 - 4'b 1111, // index[ 484] SCMI_CHANNEL_FLAGS_C48 - 4'b 1111, // index[ 485] SCMI_LENGTH_C48 - 4'b 1111, // index[ 486] SCMI_MESSAGE_HEADER_C48 - 4'b 1111, // index[ 487] SCMI_MESSAGE_PAYLOAD_1_C48 - 4'b 1111, // index[ 488] SCMI_DOORBELL_C48 - 4'b 1111, // index[ 489] SCMI_COMPLETION_INTERRUPT_C48 - 4'b 1111, // index[ 490] SCMI_RESERVED_1_C49 - 4'b 1111, // index[ 491] SCMI_CHANNEL_STATUS_C49 - 4'b 1111, // index[ 492] SCMI_RESERVED_2_C49 - 4'b 1111, // index[ 493] SCMI_RESERVED_3_C49 - 4'b 1111, // index[ 494] SCMI_CHANNEL_FLAGS_C49 - 4'b 1111, // index[ 495] SCMI_LENGTH_C49 - 4'b 1111, // index[ 496] SCMI_MESSAGE_HEADER_C49 - 4'b 1111, // index[ 497] SCMI_MESSAGE_PAYLOAD_1_C49 - 4'b 1111, // index[ 498] SCMI_DOORBELL_C49 - 4'b 1111, // index[ 499] SCMI_COMPLETION_INTERRUPT_C49 - 4'b 1111, // index[ 500] SCMI_RESERVED_1_C50 - 4'b 1111, // index[ 501] SCMI_CHANNEL_STATUS_C50 - 4'b 1111, // index[ 502] SCMI_RESERVED_2_C50 - 4'b 1111, // index[ 503] SCMI_RESERVED_3_C50 - 4'b 1111, // index[ 504] SCMI_CHANNEL_FLAGS_C50 - 4'b 1111, // index[ 505] SCMI_LENGTH_C50 - 4'b 1111, // index[ 506] SCMI_MESSAGE_HEADER_C50 - 4'b 1111, // index[ 507] SCMI_MESSAGE_PAYLOAD_1_C50 - 4'b 1111, // index[ 508] SCMI_DOORBELL_C50 - 4'b 1111, // index[ 509] SCMI_COMPLETION_INTERRUPT_C50 - 4'b 1111, // index[ 510] SCMI_RESERVED_1_C51 - 4'b 1111, // index[ 511] SCMI_CHANNEL_STATUS_C51 - 4'b 1111, // index[ 512] SCMI_RESERVED_2_C51 - 4'b 1111, // index[ 513] SCMI_RESERVED_3_C51 - 4'b 1111, // index[ 514] SCMI_CHANNEL_FLAGS_C51 - 4'b 1111, // index[ 515] SCMI_LENGTH_C51 - 4'b 1111, // index[ 516] SCMI_MESSAGE_HEADER_C51 - 4'b 1111, // index[ 517] SCMI_MESSAGE_PAYLOAD_1_C51 - 4'b 1111, // index[ 518] SCMI_DOORBELL_C51 - 4'b 1111, // index[ 519] SCMI_COMPLETION_INTERRUPT_C51 - 4'b 1111, // index[ 520] SCMI_RESERVED_1_C52 - 4'b 1111, // index[ 521] SCMI_CHANNEL_STATUS_C52 - 4'b 1111, // index[ 522] SCMI_RESERVED_2_C52 - 4'b 1111, // index[ 523] SCMI_RESERVED_3_C52 - 4'b 1111, // index[ 524] SCMI_CHANNEL_FLAGS_C52 - 4'b 1111, // index[ 525] SCMI_LENGTH_C52 - 4'b 1111, // index[ 526] SCMI_MESSAGE_HEADER_C52 - 4'b 1111, // index[ 527] SCMI_MESSAGE_PAYLOAD_1_C52 - 4'b 1111, // index[ 528] SCMI_DOORBELL_C52 - 4'b 1111, // index[ 529] SCMI_COMPLETION_INTERRUPT_C52 - 4'b 1111, // index[ 530] SCMI_RESERVED_1_C53 - 4'b 1111, // index[ 531] SCMI_CHANNEL_STATUS_C53 - 4'b 1111, // index[ 532] SCMI_RESERVED_2_C53 - 4'b 1111, // index[ 533] SCMI_RESERVED_3_C53 - 4'b 1111, // index[ 534] SCMI_CHANNEL_FLAGS_C53 - 4'b 1111, // index[ 535] SCMI_LENGTH_C53 - 4'b 1111, // index[ 536] SCMI_MESSAGE_HEADER_C53 - 4'b 1111, // index[ 537] SCMI_MESSAGE_PAYLOAD_1_C53 - 4'b 1111, // index[ 538] SCMI_DOORBELL_C53 - 4'b 1111, // index[ 539] SCMI_COMPLETION_INTERRUPT_C53 - 4'b 1111, // index[ 540] SCMI_RESERVED_1_C54 - 4'b 1111, // index[ 541] SCMI_CHANNEL_STATUS_C54 - 4'b 1111, // index[ 542] SCMI_RESERVED_2_C54 - 4'b 1111, // index[ 543] SCMI_RESERVED_3_C54 - 4'b 1111, // index[ 544] SCMI_CHANNEL_FLAGS_C54 - 4'b 1111, // index[ 545] SCMI_LENGTH_C54 - 4'b 1111, // index[ 546] SCMI_MESSAGE_HEADER_C54 - 4'b 1111, // index[ 547] SCMI_MESSAGE_PAYLOAD_1_C54 - 4'b 1111, // index[ 548] SCMI_DOORBELL_C54 - 4'b 1111, // index[ 549] SCMI_COMPLETION_INTERRUPT_C54 - 4'b 1111, // index[ 550] SCMI_RESERVED_1_C55 - 4'b 1111, // index[ 551] SCMI_CHANNEL_STATUS_C55 - 4'b 1111, // index[ 552] SCMI_RESERVED_2_C55 - 4'b 1111, // index[ 553] SCMI_RESERVED_3_C55 - 4'b 1111, // index[ 554] SCMI_CHANNEL_FLAGS_C55 - 4'b 1111, // index[ 555] SCMI_LENGTH_C55 - 4'b 1111, // index[ 556] SCMI_MESSAGE_HEADER_C55 - 4'b 1111, // index[ 557] SCMI_MESSAGE_PAYLOAD_1_C55 - 4'b 1111, // index[ 558] SCMI_DOORBELL_C55 - 4'b 1111, // index[ 559] SCMI_COMPLETION_INTERRUPT_C55 - 4'b 1111, // index[ 560] SCMI_RESERVED_1_C56 - 4'b 1111, // index[ 561] SCMI_CHANNEL_STATUS_C56 - 4'b 1111, // index[ 562] SCMI_RESERVED_2_C56 - 4'b 1111, // index[ 563] SCMI_RESERVED_3_C56 - 4'b 1111, // index[ 564] SCMI_CHANNEL_FLAGS_C56 - 4'b 1111, // index[ 565] SCMI_LENGTH_C56 - 4'b 1111, // index[ 566] SCMI_MESSAGE_HEADER_C56 - 4'b 1111, // index[ 567] SCMI_MESSAGE_PAYLOAD_1_C56 - 4'b 1111, // index[ 568] SCMI_DOORBELL_C56 - 4'b 1111, // index[ 569] SCMI_COMPLETION_INTERRUPT_C56 - 4'b 1111, // index[ 570] SCMI_RESERVED_1_C57 - 4'b 1111, // index[ 571] SCMI_CHANNEL_STATUS_C57 - 4'b 1111, // index[ 572] SCMI_RESERVED_2_C57 - 4'b 1111, // index[ 573] SCMI_RESERVED_3_C57 - 4'b 1111, // index[ 574] SCMI_CHANNEL_FLAGS_C57 - 4'b 1111, // index[ 575] SCMI_LENGTH_C57 - 4'b 1111, // index[ 576] SCMI_MESSAGE_HEADER_C57 - 4'b 1111, // index[ 577] SCMI_MESSAGE_PAYLOAD_1_C57 - 4'b 1111, // index[ 578] SCMI_DOORBELL_C57 - 4'b 1111, // index[ 579] SCMI_COMPLETION_INTERRUPT_C57 - 4'b 1111, // index[ 580] SCMI_RESERVED_1_C58 - 4'b 1111, // index[ 581] SCMI_CHANNEL_STATUS_C58 - 4'b 1111, // index[ 582] SCMI_RESERVED_2_C58 - 4'b 1111, // index[ 583] SCMI_RESERVED_3_C58 - 4'b 1111, // index[ 584] SCMI_CHANNEL_FLAGS_C58 - 4'b 1111, // index[ 585] SCMI_LENGTH_C58 - 4'b 1111, // index[ 586] SCMI_MESSAGE_HEADER_C58 - 4'b 1111, // index[ 587] SCMI_MESSAGE_PAYLOAD_1_C58 - 4'b 1111, // index[ 588] SCMI_DOORBELL_C58 - 4'b 1111, // index[ 589] SCMI_COMPLETION_INTERRUPT_C58 - 4'b 1111, // index[ 590] SCMI_RESERVED_1_C59 - 4'b 1111, // index[ 591] SCMI_CHANNEL_STATUS_C59 - 4'b 1111, // index[ 592] SCMI_RESERVED_2_C59 - 4'b 1111, // index[ 593] SCMI_RESERVED_3_C59 - 4'b 1111, // index[ 594] SCMI_CHANNEL_FLAGS_C59 - 4'b 1111, // index[ 595] SCMI_LENGTH_C59 - 4'b 1111, // index[ 596] SCMI_MESSAGE_HEADER_C59 - 4'b 1111, // index[ 597] SCMI_MESSAGE_PAYLOAD_1_C59 - 4'b 1111, // index[ 598] SCMI_DOORBELL_C59 - 4'b 1111, // index[ 599] SCMI_COMPLETION_INTERRUPT_C59 - 4'b 1111, // index[ 600] SCMI_RESERVED_1_C60 - 4'b 1111, // index[ 601] SCMI_CHANNEL_STATUS_C60 - 4'b 1111, // index[ 602] SCMI_RESERVED_2_C60 - 4'b 1111, // index[ 603] SCMI_RESERVED_3_C60 - 4'b 1111, // index[ 604] SCMI_CHANNEL_FLAGS_C60 - 4'b 1111, // index[ 605] SCMI_LENGTH_C60 - 4'b 1111, // index[ 606] SCMI_MESSAGE_HEADER_C60 - 4'b 1111, // index[ 607] SCMI_MESSAGE_PAYLOAD_1_C60 - 4'b 1111, // index[ 608] SCMI_DOORBELL_C60 - 4'b 1111, // index[ 609] SCMI_COMPLETION_INTERRUPT_C60 - 4'b 1111, // index[ 610] SCMI_RESERVED_1_C61 - 4'b 1111, // index[ 611] SCMI_CHANNEL_STATUS_C61 - 4'b 1111, // index[ 612] SCMI_RESERVED_2_C61 - 4'b 1111, // index[ 613] SCMI_RESERVED_3_C61 - 4'b 1111, // index[ 614] SCMI_CHANNEL_FLAGS_C61 - 4'b 1111, // index[ 615] SCMI_LENGTH_C61 - 4'b 1111, // index[ 616] SCMI_MESSAGE_HEADER_C61 - 4'b 1111, // index[ 617] SCMI_MESSAGE_PAYLOAD_1_C61 - 4'b 1111, // index[ 618] SCMI_DOORBELL_C61 - 4'b 1111, // index[ 619] SCMI_COMPLETION_INTERRUPT_C61 - 4'b 1111, // index[ 620] SCMI_RESERVED_1_C62 - 4'b 1111, // index[ 621] SCMI_CHANNEL_STATUS_C62 - 4'b 1111, // index[ 622] SCMI_RESERVED_2_C62 - 4'b 1111, // index[ 623] SCMI_RESERVED_3_C62 - 4'b 1111, // index[ 624] SCMI_CHANNEL_FLAGS_C62 - 4'b 1111, // index[ 625] SCMI_LENGTH_C62 - 4'b 1111, // index[ 626] SCMI_MESSAGE_HEADER_C62 - 4'b 1111, // index[ 627] SCMI_MESSAGE_PAYLOAD_1_C62 - 4'b 1111, // index[ 628] SCMI_DOORBELL_C62 - 4'b 1111, // index[ 629] SCMI_COMPLETION_INTERRUPT_C62 - 4'b 1111, // index[ 630] SCMI_RESERVED_1_C63 - 4'b 1111, // index[ 631] SCMI_CHANNEL_STATUS_C63 - 4'b 1111, // index[ 632] SCMI_RESERVED_2_C63 - 4'b 1111, // index[ 633] SCMI_RESERVED_3_C63 - 4'b 1111, // index[ 634] SCMI_CHANNEL_FLAGS_C63 - 4'b 1111, // index[ 635] SCMI_LENGTH_C63 - 4'b 1111, // index[ 636] SCMI_MESSAGE_HEADER_C63 - 4'b 1111, // index[ 637] SCMI_MESSAGE_PAYLOAD_1_C63 - 4'b 1111, // index[ 638] SCMI_DOORBELL_C63 - 4'b 1111, // index[ 639] SCMI_COMPLETION_INTERRUPT_C63 - 4'b 1111, // index[ 640] SCMI_RESERVED_1_C64 - 4'b 1111, // index[ 641] SCMI_CHANNEL_STATUS_C64 - 4'b 1111, // index[ 642] SCMI_RESERVED_2_C64 - 4'b 1111, // index[ 643] SCMI_RESERVED_3_C64 - 4'b 1111, // index[ 644] SCMI_CHANNEL_FLAGS_C64 - 4'b 1111, // index[ 645] SCMI_LENGTH_C64 - 4'b 1111, // index[ 646] SCMI_MESSAGE_HEADER_C64 - 4'b 1111, // index[ 647] SCMI_MESSAGE_PAYLOAD_1_C64 - 4'b 1111, // index[ 648] SCMI_DOORBELL_C64 - 4'b 1111, // index[ 649] SCMI_COMPLETION_INTERRUPT_C64 - 4'b 1111, // index[ 650] SCMI_RESERVED_1_C65 - 4'b 1111, // index[ 651] SCMI_CHANNEL_STATUS_C65 - 4'b 1111, // index[ 652] SCMI_RESERVED_2_C65 - 4'b 1111, // index[ 653] SCMI_RESERVED_3_C65 - 4'b 1111, // index[ 654] SCMI_CHANNEL_FLAGS_C65 - 4'b 1111, // index[ 655] SCMI_LENGTH_C65 - 4'b 1111, // index[ 656] SCMI_MESSAGE_HEADER_C65 - 4'b 1111, // index[ 657] SCMI_MESSAGE_PAYLOAD_1_C65 - 4'b 1111, // index[ 658] SCMI_DOORBELL_C65 - 4'b 1111, // index[ 659] SCMI_COMPLETION_INTERRUPT_C65 - 4'b 1111, // index[ 660] SCMI_RESERVED_1_C66 - 4'b 1111, // index[ 661] SCMI_CHANNEL_STATUS_C66 - 4'b 1111, // index[ 662] SCMI_RESERVED_2_C66 - 4'b 1111, // index[ 663] SCMI_RESERVED_3_C66 - 4'b 1111, // index[ 664] SCMI_CHANNEL_FLAGS_C66 - 4'b 1111, // index[ 665] SCMI_LENGTH_C66 - 4'b 1111, // index[ 666] SCMI_MESSAGE_HEADER_C66 - 4'b 1111, // index[ 667] SCMI_MESSAGE_PAYLOAD_1_C66 - 4'b 1111, // index[ 668] SCMI_DOORBELL_C66 - 4'b 1111, // index[ 669] SCMI_COMPLETION_INTERRUPT_C66 - 4'b 1111, // index[ 670] SCMI_RESERVED_1_C67 - 4'b 1111, // index[ 671] SCMI_CHANNEL_STATUS_C67 - 4'b 1111, // index[ 672] SCMI_RESERVED_2_C67 - 4'b 1111, // index[ 673] SCMI_RESERVED_3_C67 - 4'b 1111, // index[ 674] SCMI_CHANNEL_FLAGS_C67 - 4'b 1111, // index[ 675] SCMI_LENGTH_C67 - 4'b 1111, // index[ 676] SCMI_MESSAGE_HEADER_C67 - 4'b 1111, // index[ 677] SCMI_MESSAGE_PAYLOAD_1_C67 - 4'b 1111, // index[ 678] SCMI_DOORBELL_C67 - 4'b 1111, // index[ 679] SCMI_COMPLETION_INTERRUPT_C67 - 4'b 1111, // index[ 680] SCMI_RESERVED_1_C68 - 4'b 1111, // index[ 681] SCMI_CHANNEL_STATUS_C68 - 4'b 1111, // index[ 682] SCMI_RESERVED_2_C68 - 4'b 1111, // index[ 683] SCMI_RESERVED_3_C68 - 4'b 1111, // index[ 684] SCMI_CHANNEL_FLAGS_C68 - 4'b 1111, // index[ 685] SCMI_LENGTH_C68 - 4'b 1111, // index[ 686] SCMI_MESSAGE_HEADER_C68 - 4'b 1111, // index[ 687] SCMI_MESSAGE_PAYLOAD_1_C68 - 4'b 1111, // index[ 688] SCMI_DOORBELL_C68 - 4'b 1111, // index[ 689] SCMI_COMPLETION_INTERRUPT_C68 - 4'b 1111, // index[ 690] SCMI_RESERVED_1_C69 - 4'b 1111, // index[ 691] SCMI_CHANNEL_STATUS_C69 - 4'b 1111, // index[ 692] SCMI_RESERVED_2_C69 - 4'b 1111, // index[ 693] SCMI_RESERVED_3_C69 - 4'b 1111, // index[ 694] SCMI_CHANNEL_FLAGS_C69 - 4'b 1111, // index[ 695] SCMI_LENGTH_C69 - 4'b 1111, // index[ 696] SCMI_MESSAGE_HEADER_C69 - 4'b 1111, // index[ 697] SCMI_MESSAGE_PAYLOAD_1_C69 - 4'b 1111, // index[ 698] SCMI_DOORBELL_C69 - 4'b 1111, // index[ 699] SCMI_COMPLETION_INTERRUPT_C69 - 4'b 1111, // index[ 700] SCMI_RESERVED_1_C70 - 4'b 1111, // index[ 701] SCMI_CHANNEL_STATUS_C70 - 4'b 1111, // index[ 702] SCMI_RESERVED_2_C70 - 4'b 1111, // index[ 703] SCMI_RESERVED_3_C70 - 4'b 1111, // index[ 704] SCMI_CHANNEL_FLAGS_C70 - 4'b 1111, // index[ 705] SCMI_LENGTH_C70 - 4'b 1111, // index[ 706] SCMI_MESSAGE_HEADER_C70 - 4'b 1111, // index[ 707] SCMI_MESSAGE_PAYLOAD_1_C70 - 4'b 1111, // index[ 708] SCMI_DOORBELL_C70 - 4'b 1111, // index[ 709] SCMI_COMPLETION_INTERRUPT_C70 - 4'b 1111, // index[ 710] SCMI_RESERVED_1_C71 - 4'b 1111, // index[ 711] SCMI_CHANNEL_STATUS_C71 - 4'b 1111, // index[ 712] SCMI_RESERVED_2_C71 - 4'b 1111, // index[ 713] SCMI_RESERVED_3_C71 - 4'b 1111, // index[ 714] SCMI_CHANNEL_FLAGS_C71 - 4'b 1111, // index[ 715] SCMI_LENGTH_C71 - 4'b 1111, // index[ 716] SCMI_MESSAGE_HEADER_C71 - 4'b 1111, // index[ 717] SCMI_MESSAGE_PAYLOAD_1_C71 - 4'b 1111, // index[ 718] SCMI_DOORBELL_C71 - 4'b 1111, // index[ 719] SCMI_COMPLETION_INTERRUPT_C71 - 4'b 1111, // index[ 720] SCMI_RESERVED_1_C72 - 4'b 1111, // index[ 721] SCMI_CHANNEL_STATUS_C72 - 4'b 1111, // index[ 722] SCMI_RESERVED_2_C72 - 4'b 1111, // index[ 723] SCMI_RESERVED_3_C72 - 4'b 1111, // index[ 724] SCMI_CHANNEL_FLAGS_C72 - 4'b 1111, // index[ 725] SCMI_LENGTH_C72 - 4'b 1111, // index[ 726] SCMI_MESSAGE_HEADER_C72 - 4'b 1111, // index[ 727] SCMI_MESSAGE_PAYLOAD_1_C72 - 4'b 1111, // index[ 728] SCMI_DOORBELL_C72 - 4'b 1111, // index[ 729] SCMI_COMPLETION_INTERRUPT_C72 - 4'b 1111, // index[ 730] SCMI_RESERVED_1_C73 - 4'b 1111, // index[ 731] SCMI_CHANNEL_STATUS_C73 - 4'b 1111, // index[ 732] SCMI_RESERVED_2_C73 - 4'b 1111, // index[ 733] SCMI_RESERVED_3_C73 - 4'b 1111, // index[ 734] SCMI_CHANNEL_FLAGS_C73 - 4'b 1111, // index[ 735] SCMI_LENGTH_C73 - 4'b 1111, // index[ 736] SCMI_MESSAGE_HEADER_C73 - 4'b 1111, // index[ 737] SCMI_MESSAGE_PAYLOAD_1_C73 - 4'b 1111, // index[ 738] SCMI_DOORBELL_C73 - 4'b 1111, // index[ 739] SCMI_COMPLETION_INTERRUPT_C73 - 4'b 1111, // index[ 740] SCMI_RESERVED_1_C74 - 4'b 1111, // index[ 741] SCMI_CHANNEL_STATUS_C74 - 4'b 1111, // index[ 742] SCMI_RESERVED_2_C74 - 4'b 1111, // index[ 743] SCMI_RESERVED_3_C74 - 4'b 1111, // index[ 744] SCMI_CHANNEL_FLAGS_C74 - 4'b 1111, // index[ 745] SCMI_LENGTH_C74 - 4'b 1111, // index[ 746] SCMI_MESSAGE_HEADER_C74 - 4'b 1111, // index[ 747] SCMI_MESSAGE_PAYLOAD_1_C74 - 4'b 1111, // index[ 748] SCMI_DOORBELL_C74 - 4'b 1111, // index[ 749] SCMI_COMPLETION_INTERRUPT_C74 - 4'b 1111, // index[ 750] SCMI_RESERVED_1_C75 - 4'b 1111, // index[ 751] SCMI_CHANNEL_STATUS_C75 - 4'b 1111, // index[ 752] SCMI_RESERVED_2_C75 - 4'b 1111, // index[ 753] SCMI_RESERVED_3_C75 - 4'b 1111, // index[ 754] SCMI_CHANNEL_FLAGS_C75 - 4'b 1111, // index[ 755] SCMI_LENGTH_C75 - 4'b 1111, // index[ 756] SCMI_MESSAGE_HEADER_C75 - 4'b 1111, // index[ 757] SCMI_MESSAGE_PAYLOAD_1_C75 - 4'b 1111, // index[ 758] SCMI_DOORBELL_C75 - 4'b 1111, // index[ 759] SCMI_COMPLETION_INTERRUPT_C75 - 4'b 1111, // index[ 760] SCMI_RESERVED_1_C76 - 4'b 1111, // index[ 761] SCMI_CHANNEL_STATUS_C76 - 4'b 1111, // index[ 762] SCMI_RESERVED_2_C76 - 4'b 1111, // index[ 763] SCMI_RESERVED_3_C76 - 4'b 1111, // index[ 764] SCMI_CHANNEL_FLAGS_C76 - 4'b 1111, // index[ 765] SCMI_LENGTH_C76 - 4'b 1111, // index[ 766] SCMI_MESSAGE_HEADER_C76 - 4'b 1111, // index[ 767] SCMI_MESSAGE_PAYLOAD_1_C76 - 4'b 1111, // index[ 768] SCMI_DOORBELL_C76 - 4'b 1111, // index[ 769] SCMI_COMPLETION_INTERRUPT_C76 - 4'b 1111, // index[ 770] SCMI_RESERVED_1_C77 - 4'b 1111, // index[ 771] SCMI_CHANNEL_STATUS_C77 - 4'b 1111, // index[ 772] SCMI_RESERVED_2_C77 - 4'b 1111, // index[ 773] SCMI_RESERVED_3_C77 - 4'b 1111, // index[ 774] SCMI_CHANNEL_FLAGS_C77 - 4'b 1111, // index[ 775] SCMI_LENGTH_C77 - 4'b 1111, // index[ 776] SCMI_MESSAGE_HEADER_C77 - 4'b 1111, // index[ 777] SCMI_MESSAGE_PAYLOAD_1_C77 - 4'b 1111, // index[ 778] SCMI_DOORBELL_C77 - 4'b 1111, // index[ 779] SCMI_COMPLETION_INTERRUPT_C77 - 4'b 1111, // index[ 780] SCMI_RESERVED_1_C78 - 4'b 1111, // index[ 781] SCMI_CHANNEL_STATUS_C78 - 4'b 1111, // index[ 782] SCMI_RESERVED_2_C78 - 4'b 1111, // index[ 783] SCMI_RESERVED_3_C78 - 4'b 1111, // index[ 784] SCMI_CHANNEL_FLAGS_C78 - 4'b 1111, // index[ 785] SCMI_LENGTH_C78 - 4'b 1111, // index[ 786] SCMI_MESSAGE_HEADER_C78 - 4'b 1111, // index[ 787] SCMI_MESSAGE_PAYLOAD_1_C78 - 4'b 1111, // index[ 788] SCMI_DOORBELL_C78 - 4'b 1111, // index[ 789] SCMI_COMPLETION_INTERRUPT_C78 - 4'b 1111, // index[ 790] SCMI_RESERVED_1_C79 - 4'b 1111, // index[ 791] SCMI_CHANNEL_STATUS_C79 - 4'b 1111, // index[ 792] SCMI_RESERVED_2_C79 - 4'b 1111, // index[ 793] SCMI_RESERVED_3_C79 - 4'b 1111, // index[ 794] SCMI_CHANNEL_FLAGS_C79 - 4'b 1111, // index[ 795] SCMI_LENGTH_C79 - 4'b 1111, // index[ 796] SCMI_MESSAGE_HEADER_C79 - 4'b 1111, // index[ 797] SCMI_MESSAGE_PAYLOAD_1_C79 - 4'b 1111, // index[ 798] SCMI_DOORBELL_C79 - 4'b 1111, // index[ 799] SCMI_COMPLETION_INTERRUPT_C79 - 4'b 1111, // index[ 800] SCMI_RESERVED_1_C80 - 4'b 1111, // index[ 801] SCMI_CHANNEL_STATUS_C80 - 4'b 1111, // index[ 802] SCMI_RESERVED_2_C80 - 4'b 1111, // index[ 803] SCMI_RESERVED_3_C80 - 4'b 1111, // index[ 804] SCMI_CHANNEL_FLAGS_C80 - 4'b 1111, // index[ 805] SCMI_LENGTH_C80 - 4'b 1111, // index[ 806] SCMI_MESSAGE_HEADER_C80 - 4'b 1111, // index[ 807] SCMI_MESSAGE_PAYLOAD_1_C80 - 4'b 1111, // index[ 808] SCMI_DOORBELL_C80 - 4'b 1111, // index[ 809] SCMI_COMPLETION_INTERRUPT_C80 - 4'b 1111, // index[ 810] SCMI_RESERVED_1_C81 - 4'b 1111, // index[ 811] SCMI_CHANNEL_STATUS_C81 - 4'b 1111, // index[ 812] SCMI_RESERVED_2_C81 - 4'b 1111, // index[ 813] SCMI_RESERVED_3_C81 - 4'b 1111, // index[ 814] SCMI_CHANNEL_FLAGS_C81 - 4'b 1111, // index[ 815] SCMI_LENGTH_C81 - 4'b 1111, // index[ 816] SCMI_MESSAGE_HEADER_C81 - 4'b 1111, // index[ 817] SCMI_MESSAGE_PAYLOAD_1_C81 - 4'b 1111, // index[ 818] SCMI_DOORBELL_C81 - 4'b 1111, // index[ 819] SCMI_COMPLETION_INTERRUPT_C81 - 4'b 1111, // index[ 820] SCMI_RESERVED_1_C82 - 4'b 1111, // index[ 821] SCMI_CHANNEL_STATUS_C82 - 4'b 1111, // index[ 822] SCMI_RESERVED_2_C82 - 4'b 1111, // index[ 823] SCMI_RESERVED_3_C82 - 4'b 1111, // index[ 824] SCMI_CHANNEL_FLAGS_C82 - 4'b 1111, // index[ 825] SCMI_LENGTH_C82 - 4'b 1111, // index[ 826] SCMI_MESSAGE_HEADER_C82 - 4'b 1111, // index[ 827] SCMI_MESSAGE_PAYLOAD_1_C82 - 4'b 1111, // index[ 828] SCMI_DOORBELL_C82 - 4'b 1111, // index[ 829] SCMI_COMPLETION_INTERRUPT_C82 - 4'b 1111, // index[ 830] SCMI_RESERVED_1_C83 - 4'b 1111, // index[ 831] SCMI_CHANNEL_STATUS_C83 - 4'b 1111, // index[ 832] SCMI_RESERVED_2_C83 - 4'b 1111, // index[ 833] SCMI_RESERVED_3_C83 - 4'b 1111, // index[ 834] SCMI_CHANNEL_FLAGS_C83 - 4'b 1111, // index[ 835] SCMI_LENGTH_C83 - 4'b 1111, // index[ 836] SCMI_MESSAGE_HEADER_C83 - 4'b 1111, // index[ 837] SCMI_MESSAGE_PAYLOAD_1_C83 - 4'b 1111, // index[ 838] SCMI_DOORBELL_C83 - 4'b 1111, // index[ 839] SCMI_COMPLETION_INTERRUPT_C83 - 4'b 1111, // index[ 840] SCMI_RESERVED_1_C84 - 4'b 1111, // index[ 841] SCMI_CHANNEL_STATUS_C84 - 4'b 1111, // index[ 842] SCMI_RESERVED_2_C84 - 4'b 1111, // index[ 843] SCMI_RESERVED_3_C84 - 4'b 1111, // index[ 844] SCMI_CHANNEL_FLAGS_C84 - 4'b 1111, // index[ 845] SCMI_LENGTH_C84 - 4'b 1111, // index[ 846] SCMI_MESSAGE_HEADER_C84 - 4'b 1111, // index[ 847] SCMI_MESSAGE_PAYLOAD_1_C84 - 4'b 1111, // index[ 848] SCMI_DOORBELL_C84 - 4'b 1111, // index[ 849] SCMI_COMPLETION_INTERRUPT_C84 - 4'b 1111, // index[ 850] SCMI_RESERVED_1_C85 - 4'b 1111, // index[ 851] SCMI_CHANNEL_STATUS_C85 - 4'b 1111, // index[ 852] SCMI_RESERVED_2_C85 - 4'b 1111, // index[ 853] SCMI_RESERVED_3_C85 - 4'b 1111, // index[ 854] SCMI_CHANNEL_FLAGS_C85 - 4'b 1111, // index[ 855] SCMI_LENGTH_C85 - 4'b 1111, // index[ 856] SCMI_MESSAGE_HEADER_C85 - 4'b 1111, // index[ 857] SCMI_MESSAGE_PAYLOAD_1_C85 - 4'b 1111, // index[ 858] SCMI_DOORBELL_C85 - 4'b 1111, // index[ 859] SCMI_COMPLETION_INTERRUPT_C85 - 4'b 1111, // index[ 860] SCMI_RESERVED_1_C86 - 4'b 1111, // index[ 861] SCMI_CHANNEL_STATUS_C86 - 4'b 1111, // index[ 862] SCMI_RESERVED_2_C86 - 4'b 1111, // index[ 863] SCMI_RESERVED_3_C86 - 4'b 1111, // index[ 864] SCMI_CHANNEL_FLAGS_C86 - 4'b 1111, // index[ 865] SCMI_LENGTH_C86 - 4'b 1111, // index[ 866] SCMI_MESSAGE_HEADER_C86 - 4'b 1111, // index[ 867] SCMI_MESSAGE_PAYLOAD_1_C86 - 4'b 1111, // index[ 868] SCMI_DOORBELL_C86 - 4'b 1111, // index[ 869] SCMI_COMPLETION_INTERRUPT_C86 - 4'b 1111, // index[ 870] SCMI_RESERVED_1_C87 - 4'b 1111, // index[ 871] SCMI_CHANNEL_STATUS_C87 - 4'b 1111, // index[ 872] SCMI_RESERVED_2_C87 - 4'b 1111, // index[ 873] SCMI_RESERVED_3_C87 - 4'b 1111, // index[ 874] SCMI_CHANNEL_FLAGS_C87 - 4'b 1111, // index[ 875] SCMI_LENGTH_C87 - 4'b 1111, // index[ 876] SCMI_MESSAGE_HEADER_C87 - 4'b 1111, // index[ 877] SCMI_MESSAGE_PAYLOAD_1_C87 - 4'b 1111, // index[ 878] SCMI_DOORBELL_C87 - 4'b 1111, // index[ 879] SCMI_COMPLETION_INTERRUPT_C87 - 4'b 1111, // index[ 880] SCMI_RESERVED_1_C88 - 4'b 1111, // index[ 881] SCMI_CHANNEL_STATUS_C88 - 4'b 1111, // index[ 882] SCMI_RESERVED_2_C88 - 4'b 1111, // index[ 883] SCMI_RESERVED_3_C88 - 4'b 1111, // index[ 884] SCMI_CHANNEL_FLAGS_C88 - 4'b 1111, // index[ 885] SCMI_LENGTH_C88 - 4'b 1111, // index[ 886] SCMI_MESSAGE_HEADER_C88 - 4'b 1111, // index[ 887] SCMI_MESSAGE_PAYLOAD_1_C88 - 4'b 1111, // index[ 888] SCMI_DOORBELL_C88 - 4'b 1111, // index[ 889] SCMI_COMPLETION_INTERRUPT_C88 - 4'b 1111, // index[ 890] SCMI_RESERVED_1_C89 - 4'b 1111, // index[ 891] SCMI_CHANNEL_STATUS_C89 - 4'b 1111, // index[ 892] SCMI_RESERVED_2_C89 - 4'b 1111, // index[ 893] SCMI_RESERVED_3_C89 - 4'b 1111, // index[ 894] SCMI_CHANNEL_FLAGS_C89 - 4'b 1111, // index[ 895] SCMI_LENGTH_C89 - 4'b 1111, // index[ 896] SCMI_MESSAGE_HEADER_C89 - 4'b 1111, // index[ 897] SCMI_MESSAGE_PAYLOAD_1_C89 - 4'b 1111, // index[ 898] SCMI_DOORBELL_C89 - 4'b 1111, // index[ 899] SCMI_COMPLETION_INTERRUPT_C89 - 4'b 1111, // index[ 900] SCMI_RESERVED_1_C90 - 4'b 1111, // index[ 901] SCMI_CHANNEL_STATUS_C90 - 4'b 1111, // index[ 902] SCMI_RESERVED_2_C90 - 4'b 1111, // index[ 903] SCMI_RESERVED_3_C90 - 4'b 1111, // index[ 904] SCMI_CHANNEL_FLAGS_C90 - 4'b 1111, // index[ 905] SCMI_LENGTH_C90 - 4'b 1111, // index[ 906] SCMI_MESSAGE_HEADER_C90 - 4'b 1111, // index[ 907] SCMI_MESSAGE_PAYLOAD_1_C90 - 4'b 1111, // index[ 908] SCMI_DOORBELL_C90 - 4'b 1111, // index[ 909] SCMI_COMPLETION_INTERRUPT_C90 - 4'b 1111, // index[ 910] SCMI_RESERVED_1_C91 - 4'b 1111, // index[ 911] SCMI_CHANNEL_STATUS_C91 - 4'b 1111, // index[ 912] SCMI_RESERVED_2_C91 - 4'b 1111, // index[ 913] SCMI_RESERVED_3_C91 - 4'b 1111, // index[ 914] SCMI_CHANNEL_FLAGS_C91 - 4'b 1111, // index[ 915] SCMI_LENGTH_C91 - 4'b 1111, // index[ 916] SCMI_MESSAGE_HEADER_C91 - 4'b 1111, // index[ 917] SCMI_MESSAGE_PAYLOAD_1_C91 - 4'b 1111, // index[ 918] SCMI_DOORBELL_C91 - 4'b 1111, // index[ 919] SCMI_COMPLETION_INTERRUPT_C91 - 4'b 1111, // index[ 920] SCMI_RESERVED_1_C92 - 4'b 1111, // index[ 921] SCMI_CHANNEL_STATUS_C92 - 4'b 1111, // index[ 922] SCMI_RESERVED_2_C92 - 4'b 1111, // index[ 923] SCMI_RESERVED_3_C92 - 4'b 1111, // index[ 924] SCMI_CHANNEL_FLAGS_C92 - 4'b 1111, // index[ 925] SCMI_LENGTH_C92 - 4'b 1111, // index[ 926] SCMI_MESSAGE_HEADER_C92 - 4'b 1111, // index[ 927] SCMI_MESSAGE_PAYLOAD_1_C92 - 4'b 1111, // index[ 928] SCMI_DOORBELL_C92 - 4'b 1111, // index[ 929] SCMI_COMPLETION_INTERRUPT_C92 - 4'b 1111, // index[ 930] SCMI_RESERVED_1_C93 - 4'b 1111, // index[ 931] SCMI_CHANNEL_STATUS_C93 - 4'b 1111, // index[ 932] SCMI_RESERVED_2_C93 - 4'b 1111, // index[ 933] SCMI_RESERVED_3_C93 - 4'b 1111, // index[ 934] SCMI_CHANNEL_FLAGS_C93 - 4'b 1111, // index[ 935] SCMI_LENGTH_C93 - 4'b 1111, // index[ 936] SCMI_MESSAGE_HEADER_C93 - 4'b 1111, // index[ 937] SCMI_MESSAGE_PAYLOAD_1_C93 - 4'b 1111, // index[ 938] SCMI_DOORBELL_C93 - 4'b 1111, // index[ 939] SCMI_COMPLETION_INTERRUPT_C93 - 4'b 1111, // index[ 940] SCMI_RESERVED_1_C94 - 4'b 1111, // index[ 941] SCMI_CHANNEL_STATUS_C94 - 4'b 1111, // index[ 942] SCMI_RESERVED_2_C94 - 4'b 1111, // index[ 943] SCMI_RESERVED_3_C94 - 4'b 1111, // index[ 944] SCMI_CHANNEL_FLAGS_C94 - 4'b 1111, // index[ 945] SCMI_LENGTH_C94 - 4'b 1111, // index[ 946] SCMI_MESSAGE_HEADER_C94 - 4'b 1111, // index[ 947] SCMI_MESSAGE_PAYLOAD_1_C94 - 4'b 1111, // index[ 948] SCMI_DOORBELL_C94 - 4'b 1111, // index[ 949] SCMI_COMPLETION_INTERRUPT_C94 - 4'b 1111, // index[ 950] SCMI_RESERVED_1_C95 - 4'b 1111, // index[ 951] SCMI_CHANNEL_STATUS_C95 - 4'b 1111, // index[ 952] SCMI_RESERVED_2_C95 - 4'b 1111, // index[ 953] SCMI_RESERVED_3_C95 - 4'b 1111, // index[ 954] SCMI_CHANNEL_FLAGS_C95 - 4'b 1111, // index[ 955] SCMI_LENGTH_C95 - 4'b 1111, // index[ 956] SCMI_MESSAGE_HEADER_C95 - 4'b 1111, // index[ 957] SCMI_MESSAGE_PAYLOAD_1_C95 - 4'b 1111, // index[ 958] SCMI_DOORBELL_C95 - 4'b 1111, // index[ 959] SCMI_COMPLETION_INTERRUPT_C95 - 4'b 1111, // index[ 960] SCMI_RESERVED_1_C96 - 4'b 1111, // index[ 961] SCMI_CHANNEL_STATUS_C96 - 4'b 1111, // index[ 962] SCMI_RESERVED_2_C96 - 4'b 1111, // index[ 963] SCMI_RESERVED_3_C96 - 4'b 1111, // index[ 964] SCMI_CHANNEL_FLAGS_C96 - 4'b 1111, // index[ 965] SCMI_LENGTH_C96 - 4'b 1111, // index[ 966] SCMI_MESSAGE_HEADER_C96 - 4'b 1111, // index[ 967] SCMI_MESSAGE_PAYLOAD_1_C96 - 4'b 1111, // index[ 968] SCMI_DOORBELL_C96 - 4'b 1111, // index[ 969] SCMI_COMPLETION_INTERRUPT_C96 - 4'b 1111, // index[ 970] SCMI_RESERVED_1_C97 - 4'b 1111, // index[ 971] SCMI_CHANNEL_STATUS_C97 - 4'b 1111, // index[ 972] SCMI_RESERVED_2_C97 - 4'b 1111, // index[ 973] SCMI_RESERVED_3_C97 - 4'b 1111, // index[ 974] SCMI_CHANNEL_FLAGS_C97 - 4'b 1111, // index[ 975] SCMI_LENGTH_C97 - 4'b 1111, // index[ 976] SCMI_MESSAGE_HEADER_C97 - 4'b 1111, // index[ 977] SCMI_MESSAGE_PAYLOAD_1_C97 - 4'b 1111, // index[ 978] SCMI_DOORBELL_C97 - 4'b 1111, // index[ 979] SCMI_COMPLETION_INTERRUPT_C97 - 4'b 1111, // index[ 980] SCMI_RESERVED_1_C98 - 4'b 1111, // index[ 981] SCMI_CHANNEL_STATUS_C98 - 4'b 1111, // index[ 982] SCMI_RESERVED_2_C98 - 4'b 1111, // index[ 983] SCMI_RESERVED_3_C98 - 4'b 1111, // index[ 984] SCMI_CHANNEL_FLAGS_C98 - 4'b 1111, // index[ 985] SCMI_LENGTH_C98 - 4'b 1111, // index[ 986] SCMI_MESSAGE_HEADER_C98 - 4'b 1111, // index[ 987] SCMI_MESSAGE_PAYLOAD_1_C98 - 4'b 1111, // index[ 988] SCMI_DOORBELL_C98 - 4'b 1111, // index[ 989] SCMI_COMPLETION_INTERRUPT_C98 - 4'b 1111, // index[ 990] SCMI_RESERVED_1_C99 - 4'b 1111, // index[ 991] SCMI_CHANNEL_STATUS_C99 - 4'b 1111, // index[ 992] SCMI_RESERVED_2_C99 - 4'b 1111, // index[ 993] SCMI_RESERVED_3_C99 - 4'b 1111, // index[ 994] SCMI_CHANNEL_FLAGS_C99 - 4'b 1111, // index[ 995] SCMI_LENGTH_C99 - 4'b 1111, // index[ 996] SCMI_MESSAGE_HEADER_C99 - 4'b 1111, // index[ 997] SCMI_MESSAGE_PAYLOAD_1_C99 - 4'b 1111, // index[ 998] SCMI_DOORBELL_C99 - 4'b 1111, // index[ 999] SCMI_COMPLETION_INTERRUPT_C99 - 4'b 1111, // index[1000] SCMI_RESERVED_1_C100 - 4'b 1111, // index[1001] SCMI_CHANNEL_STATUS_C100 - 4'b 1111, // index[1002] SCMI_RESERVED_2_C100 - 4'b 1111, // index[1003] SCMI_RESERVED_3_C100 - 4'b 1111, // index[1004] SCMI_CHANNEL_FLAGS_C100 - 4'b 1111, // index[1005] SCMI_LENGTH_C100 - 4'b 1111, // index[1006] SCMI_MESSAGE_HEADER_C100 - 4'b 1111, // index[1007] SCMI_MESSAGE_PAYLOAD_1_C100 - 4'b 1111, // index[1008] SCMI_DOORBELL_C100 - 4'b 1111, // index[1009] SCMI_COMPLETION_INTERRUPT_C100 - 4'b 1111, // index[1010] SCMI_RESERVED_1_C101 - 4'b 1111, // index[1011] SCMI_CHANNEL_STATUS_C101 - 4'b 1111, // index[1012] SCMI_RESERVED_2_C101 - 4'b 1111, // index[1013] SCMI_RESERVED_3_C101 - 4'b 1111, // index[1014] SCMI_CHANNEL_FLAGS_C101 - 4'b 1111, // index[1015] SCMI_LENGTH_C101 - 4'b 1111, // index[1016] SCMI_MESSAGE_HEADER_C101 - 4'b 1111, // index[1017] SCMI_MESSAGE_PAYLOAD_1_C101 - 4'b 1111, // index[1018] SCMI_DOORBELL_C101 - 4'b 1111, // index[1019] SCMI_COMPLETION_INTERRUPT_C101 - 4'b 1111, // index[1020] SCMI_RESERVED_1_C102 - 4'b 1111, // index[1021] SCMI_CHANNEL_STATUS_C102 - 4'b 1111, // index[1022] SCMI_RESERVED_2_C102 - 4'b 1111, // index[1023] SCMI_RESERVED_3_C102 - 4'b 1111, // index[1024] SCMI_CHANNEL_FLAGS_C102 - 4'b 1111, // index[1025] SCMI_LENGTH_C102 - 4'b 1111, // index[1026] SCMI_MESSAGE_HEADER_C102 - 4'b 1111, // index[1027] SCMI_MESSAGE_PAYLOAD_1_C102 - 4'b 1111, // index[1028] SCMI_DOORBELL_C102 - 4'b 1111, // index[1029] SCMI_COMPLETION_INTERRUPT_C102 - 4'b 1111, // index[1030] SCMI_RESERVED_1_C103 - 4'b 1111, // index[1031] SCMI_CHANNEL_STATUS_C103 - 4'b 1111, // index[1032] SCMI_RESERVED_2_C103 - 4'b 1111, // index[1033] SCMI_RESERVED_3_C103 - 4'b 1111, // index[1034] SCMI_CHANNEL_FLAGS_C103 - 4'b 1111, // index[1035] SCMI_LENGTH_C103 - 4'b 1111, // index[1036] SCMI_MESSAGE_HEADER_C103 - 4'b 1111, // index[1037] SCMI_MESSAGE_PAYLOAD_1_C103 - 4'b 1111, // index[1038] SCMI_DOORBELL_C103 - 4'b 1111, // index[1039] SCMI_COMPLETION_INTERRUPT_C103 - 4'b 1111, // index[1040] SCMI_RESERVED_1_C104 - 4'b 1111, // index[1041] SCMI_CHANNEL_STATUS_C104 - 4'b 1111, // index[1042] SCMI_RESERVED_2_C104 - 4'b 1111, // index[1043] SCMI_RESERVED_3_C104 - 4'b 1111, // index[1044] SCMI_CHANNEL_FLAGS_C104 - 4'b 1111, // index[1045] SCMI_LENGTH_C104 - 4'b 1111, // index[1046] SCMI_MESSAGE_HEADER_C104 - 4'b 1111, // index[1047] SCMI_MESSAGE_PAYLOAD_1_C104 - 4'b 1111, // index[1048] SCMI_DOORBELL_C104 - 4'b 1111, // index[1049] SCMI_COMPLETION_INTERRUPT_C104 - 4'b 1111, // index[1050] SCMI_RESERVED_1_C105 - 4'b 1111, // index[1051] SCMI_CHANNEL_STATUS_C105 - 4'b 1111, // index[1052] SCMI_RESERVED_2_C105 - 4'b 1111, // index[1053] SCMI_RESERVED_3_C105 - 4'b 1111, // index[1054] SCMI_CHANNEL_FLAGS_C105 - 4'b 1111, // index[1055] SCMI_LENGTH_C105 - 4'b 1111, // index[1056] SCMI_MESSAGE_HEADER_C105 - 4'b 1111, // index[1057] SCMI_MESSAGE_PAYLOAD_1_C105 - 4'b 1111, // index[1058] SCMI_DOORBELL_C105 - 4'b 1111, // index[1059] SCMI_COMPLETION_INTERRUPT_C105 - 4'b 1111, // index[1060] SCMI_RESERVED_1_C106 - 4'b 1111, // index[1061] SCMI_CHANNEL_STATUS_C106 - 4'b 1111, // index[1062] SCMI_RESERVED_2_C106 - 4'b 1111, // index[1063] SCMI_RESERVED_3_C106 - 4'b 1111, // index[1064] SCMI_CHANNEL_FLAGS_C106 - 4'b 1111, // index[1065] SCMI_LENGTH_C106 - 4'b 1111, // index[1066] SCMI_MESSAGE_HEADER_C106 - 4'b 1111, // index[1067] SCMI_MESSAGE_PAYLOAD_1_C106 - 4'b 1111, // index[1068] SCMI_DOORBELL_C106 - 4'b 1111, // index[1069] SCMI_COMPLETION_INTERRUPT_C106 - 4'b 1111, // index[1070] SCMI_RESERVED_1_C107 - 4'b 1111, // index[1071] SCMI_CHANNEL_STATUS_C107 - 4'b 1111, // index[1072] SCMI_RESERVED_2_C107 - 4'b 1111, // index[1073] SCMI_RESERVED_3_C107 - 4'b 1111, // index[1074] SCMI_CHANNEL_FLAGS_C107 - 4'b 1111, // index[1075] SCMI_LENGTH_C107 - 4'b 1111, // index[1076] SCMI_MESSAGE_HEADER_C107 - 4'b 1111, // index[1077] SCMI_MESSAGE_PAYLOAD_1_C107 - 4'b 1111, // index[1078] SCMI_DOORBELL_C107 - 4'b 1111, // index[1079] SCMI_COMPLETION_INTERRUPT_C107 - 4'b 1111, // index[1080] SCMI_RESERVED_1_C108 - 4'b 1111, // index[1081] SCMI_CHANNEL_STATUS_C108 - 4'b 1111, // index[1082] SCMI_RESERVED_2_C108 - 4'b 1111, // index[1083] SCMI_RESERVED_3_C108 - 4'b 1111, // index[1084] SCMI_CHANNEL_FLAGS_C108 - 4'b 1111, // index[1085] SCMI_LENGTH_C108 - 4'b 1111, // index[1086] SCMI_MESSAGE_HEADER_C108 - 4'b 1111, // index[1087] SCMI_MESSAGE_PAYLOAD_1_C108 - 4'b 1111, // index[1088] SCMI_DOORBELL_C108 - 4'b 1111, // index[1089] SCMI_COMPLETION_INTERRUPT_C108 - 4'b 1111, // index[1090] SCMI_RESERVED_1_C109 - 4'b 1111, // index[1091] SCMI_CHANNEL_STATUS_C109 - 4'b 1111, // index[1092] SCMI_RESERVED_2_C109 - 4'b 1111, // index[1093] SCMI_RESERVED_3_C109 - 4'b 1111, // index[1094] SCMI_CHANNEL_FLAGS_C109 - 4'b 1111, // index[1095] SCMI_LENGTH_C109 - 4'b 1111, // index[1096] SCMI_MESSAGE_HEADER_C109 - 4'b 1111, // index[1097] SCMI_MESSAGE_PAYLOAD_1_C109 - 4'b 1111, // index[1098] SCMI_DOORBELL_C109 - 4'b 1111, // index[1099] SCMI_COMPLETION_INTERRUPT_C109 - 4'b 1111, // index[1100] SCMI_RESERVED_1_C110 - 4'b 1111, // index[1101] SCMI_CHANNEL_STATUS_C110 - 4'b 1111, // index[1102] SCMI_RESERVED_2_C110 - 4'b 1111, // index[1103] SCMI_RESERVED_3_C110 - 4'b 1111, // index[1104] SCMI_CHANNEL_FLAGS_C110 - 4'b 1111, // index[1105] SCMI_LENGTH_C110 - 4'b 1111, // index[1106] SCMI_MESSAGE_HEADER_C110 - 4'b 1111, // index[1107] SCMI_MESSAGE_PAYLOAD_1_C110 - 4'b 1111, // index[1108] SCMI_DOORBELL_C110 - 4'b 1111, // index[1109] SCMI_COMPLETION_INTERRUPT_C110 - 4'b 1111, // index[1110] SCMI_RESERVED_1_C111 - 4'b 1111, // index[1111] SCMI_CHANNEL_STATUS_C111 - 4'b 1111, // index[1112] SCMI_RESERVED_2_C111 - 4'b 1111, // index[1113] SCMI_RESERVED_3_C111 - 4'b 1111, // index[1114] SCMI_CHANNEL_FLAGS_C111 - 4'b 1111, // index[1115] SCMI_LENGTH_C111 - 4'b 1111, // index[1116] SCMI_MESSAGE_HEADER_C111 - 4'b 1111, // index[1117] SCMI_MESSAGE_PAYLOAD_1_C111 - 4'b 1111, // index[1118] SCMI_DOORBELL_C111 - 4'b 1111, // index[1119] SCMI_COMPLETION_INTERRUPT_C111 - 4'b 1111, // index[1120] SCMI_RESERVED_1_C112 - 4'b 1111, // index[1121] SCMI_CHANNEL_STATUS_C112 - 4'b 1111, // index[1122] SCMI_RESERVED_2_C112 - 4'b 1111, // index[1123] SCMI_RESERVED_3_C112 - 4'b 1111, // index[1124] SCMI_CHANNEL_FLAGS_C112 - 4'b 1111, // index[1125] SCMI_LENGTH_C112 - 4'b 1111, // index[1126] SCMI_MESSAGE_HEADER_C112 - 4'b 1111, // index[1127] SCMI_MESSAGE_PAYLOAD_1_C112 - 4'b 1111, // index[1128] SCMI_DOORBELL_C112 - 4'b 1111, // index[1129] SCMI_COMPLETION_INTERRUPT_C112 - 4'b 1111, // index[1130] SCMI_RESERVED_1_C113 - 4'b 1111, // index[1131] SCMI_CHANNEL_STATUS_C113 - 4'b 1111, // index[1132] SCMI_RESERVED_2_C113 - 4'b 1111, // index[1133] SCMI_RESERVED_3_C113 - 4'b 1111, // index[1134] SCMI_CHANNEL_FLAGS_C113 - 4'b 1111, // index[1135] SCMI_LENGTH_C113 - 4'b 1111, // index[1136] SCMI_MESSAGE_HEADER_C113 - 4'b 1111, // index[1137] SCMI_MESSAGE_PAYLOAD_1_C113 - 4'b 1111, // index[1138] SCMI_DOORBELL_C113 - 4'b 1111, // index[1139] SCMI_COMPLETION_INTERRUPT_C113 - 4'b 1111, // index[1140] SCMI_RESERVED_1_C114 - 4'b 1111, // index[1141] SCMI_CHANNEL_STATUS_C114 - 4'b 1111, // index[1142] SCMI_RESERVED_2_C114 - 4'b 1111, // index[1143] SCMI_RESERVED_3_C114 - 4'b 1111, // index[1144] SCMI_CHANNEL_FLAGS_C114 - 4'b 1111, // index[1145] SCMI_LENGTH_C114 - 4'b 1111, // index[1146] SCMI_MESSAGE_HEADER_C114 - 4'b 1111, // index[1147] SCMI_MESSAGE_PAYLOAD_1_C114 - 4'b 1111, // index[1148] SCMI_DOORBELL_C114 - 4'b 1111, // index[1149] SCMI_COMPLETION_INTERRUPT_C114 - 4'b 1111, // index[1150] SCMI_RESERVED_1_C115 - 4'b 1111, // index[1151] SCMI_CHANNEL_STATUS_C115 - 4'b 1111, // index[1152] SCMI_RESERVED_2_C115 - 4'b 1111, // index[1153] SCMI_RESERVED_3_C115 - 4'b 1111, // index[1154] SCMI_CHANNEL_FLAGS_C115 - 4'b 1111, // index[1155] SCMI_LENGTH_C115 - 4'b 1111, // index[1156] SCMI_MESSAGE_HEADER_C115 - 4'b 1111, // index[1157] SCMI_MESSAGE_PAYLOAD_1_C115 - 4'b 1111, // index[1158] SCMI_DOORBELL_C115 - 4'b 1111, // index[1159] SCMI_COMPLETION_INTERRUPT_C115 - 4'b 1111, // index[1160] SCMI_RESERVED_1_C116 - 4'b 1111, // index[1161] SCMI_CHANNEL_STATUS_C116 - 4'b 1111, // index[1162] SCMI_RESERVED_2_C116 - 4'b 1111, // index[1163] SCMI_RESERVED_3_C116 - 4'b 1111, // index[1164] SCMI_CHANNEL_FLAGS_C116 - 4'b 1111, // index[1165] SCMI_LENGTH_C116 - 4'b 1111, // index[1166] SCMI_MESSAGE_HEADER_C116 - 4'b 1111, // index[1167] SCMI_MESSAGE_PAYLOAD_1_C116 - 4'b 1111, // index[1168] SCMI_DOORBELL_C116 - 4'b 1111, // index[1169] SCMI_COMPLETION_INTERRUPT_C116 - 4'b 1111, // index[1170] SCMI_RESERVED_1_C117 - 4'b 1111, // index[1171] SCMI_CHANNEL_STATUS_C117 - 4'b 1111, // index[1172] SCMI_RESERVED_2_C117 - 4'b 1111, // index[1173] SCMI_RESERVED_3_C117 - 4'b 1111, // index[1174] SCMI_CHANNEL_FLAGS_C117 - 4'b 1111, // index[1175] SCMI_LENGTH_C117 - 4'b 1111, // index[1176] SCMI_MESSAGE_HEADER_C117 - 4'b 1111, // index[1177] SCMI_MESSAGE_PAYLOAD_1_C117 - 4'b 1111, // index[1178] SCMI_DOORBELL_C117 - 4'b 1111, // index[1179] SCMI_COMPLETION_INTERRUPT_C117 - 4'b 1111, // index[1180] SCMI_RESERVED_1_C118 - 4'b 1111, // index[1181] SCMI_CHANNEL_STATUS_C118 - 4'b 1111, // index[1182] SCMI_RESERVED_2_C118 - 4'b 1111, // index[1183] SCMI_RESERVED_3_C118 - 4'b 1111, // index[1184] SCMI_CHANNEL_FLAGS_C118 - 4'b 1111, // index[1185] SCMI_LENGTH_C118 - 4'b 1111, // index[1186] SCMI_MESSAGE_HEADER_C118 - 4'b 1111, // index[1187] SCMI_MESSAGE_PAYLOAD_1_C118 - 4'b 1111, // index[1188] SCMI_DOORBELL_C118 - 4'b 1111, // index[1189] SCMI_COMPLETION_INTERRUPT_C118 - 4'b 1111, // index[1190] SCMI_RESERVED_1_C119 - 4'b 1111, // index[1191] SCMI_CHANNEL_STATUS_C119 - 4'b 1111, // index[1192] SCMI_RESERVED_2_C119 - 4'b 1111, // index[1193] SCMI_RESERVED_3_C119 - 4'b 1111, // index[1194] SCMI_CHANNEL_FLAGS_C119 - 4'b 1111, // index[1195] SCMI_LENGTH_C119 - 4'b 1111, // index[1196] SCMI_MESSAGE_HEADER_C119 - 4'b 1111, // index[1197] SCMI_MESSAGE_PAYLOAD_1_C119 - 4'b 1111, // index[1198] SCMI_DOORBELL_C119 - 4'b 1111, // index[1199] SCMI_COMPLETION_INTERRUPT_C119 - 4'b 1111, // index[1200] SCMI_RESERVED_1_C120 - 4'b 1111, // index[1201] SCMI_CHANNEL_STATUS_C120 - 4'b 1111, // index[1202] SCMI_RESERVED_2_C120 - 4'b 1111, // index[1203] SCMI_RESERVED_3_C120 - 4'b 1111, // index[1204] SCMI_CHANNEL_FLAGS_C120 - 4'b 1111, // index[1205] SCMI_LENGTH_C120 - 4'b 1111, // index[1206] SCMI_MESSAGE_HEADER_C120 - 4'b 1111, // index[1207] SCMI_MESSAGE_PAYLOAD_1_C120 - 4'b 1111, // index[1208] SCMI_DOORBELL_C120 - 4'b 1111, // index[1209] SCMI_COMPLETION_INTERRUPT_C120 - 4'b 1111, // index[1210] SCMI_RESERVED_1_C121 - 4'b 1111, // index[1211] SCMI_CHANNEL_STATUS_C121 - 4'b 1111, // index[1212] SCMI_RESERVED_2_C121 - 4'b 1111, // index[1213] SCMI_RESERVED_3_C121 - 4'b 1111, // index[1214] SCMI_CHANNEL_FLAGS_C121 - 4'b 1111, // index[1215] SCMI_LENGTH_C121 - 4'b 1111, // index[1216] SCMI_MESSAGE_HEADER_C121 - 4'b 1111, // index[1217] SCMI_MESSAGE_PAYLOAD_1_C121 - 4'b 1111, // index[1218] SCMI_DOORBELL_C121 - 4'b 1111, // index[1219] SCMI_COMPLETION_INTERRUPT_C121 - 4'b 1111, // index[1220] SCMI_RESERVED_1_C122 - 4'b 1111, // index[1221] SCMI_CHANNEL_STATUS_C122 - 4'b 1111, // index[1222] SCMI_RESERVED_2_C122 - 4'b 1111, // index[1223] SCMI_RESERVED_3_C122 - 4'b 1111, // index[1224] SCMI_CHANNEL_FLAGS_C122 - 4'b 1111, // index[1225] SCMI_LENGTH_C122 - 4'b 1111, // index[1226] SCMI_MESSAGE_HEADER_C122 - 4'b 1111, // index[1227] SCMI_MESSAGE_PAYLOAD_1_C122 - 4'b 1111, // index[1228] SCMI_DOORBELL_C122 - 4'b 1111, // index[1229] SCMI_COMPLETION_INTERRUPT_C122 - 4'b 1111, // index[1230] SCMI_RESERVED_1_C123 - 4'b 1111, // index[1231] SCMI_CHANNEL_STATUS_C123 - 4'b 1111, // index[1232] SCMI_RESERVED_2_C123 - 4'b 1111, // index[1233] SCMI_RESERVED_3_C123 - 4'b 1111, // index[1234] SCMI_CHANNEL_FLAGS_C123 - 4'b 1111, // index[1235] SCMI_LENGTH_C123 - 4'b 1111, // index[1236] SCMI_MESSAGE_HEADER_C123 - 4'b 1111, // index[1237] SCMI_MESSAGE_PAYLOAD_1_C123 - 4'b 1111, // index[1238] SCMI_DOORBELL_C123 - 4'b 1111, // index[1239] SCMI_COMPLETION_INTERRUPT_C123 - 4'b 1111, // index[1240] SCMI_RESERVED_1_C124 - 4'b 1111, // index[1241] SCMI_CHANNEL_STATUS_C124 - 4'b 1111, // index[1242] SCMI_RESERVED_2_C124 - 4'b 1111, // index[1243] SCMI_RESERVED_3_C124 - 4'b 1111, // index[1244] SCMI_CHANNEL_FLAGS_C124 - 4'b 1111, // index[1245] SCMI_LENGTH_C124 - 4'b 1111, // index[1246] SCMI_MESSAGE_HEADER_C124 - 4'b 1111, // index[1247] SCMI_MESSAGE_PAYLOAD_1_C124 - 4'b 1111, // index[1248] SCMI_DOORBELL_C124 - 4'b 1111, // index[1249] SCMI_COMPLETION_INTERRUPT_C124 - 4'b 1111, // index[1250] SCMI_RESERVED_1_C125 - 4'b 1111, // index[1251] SCMI_CHANNEL_STATUS_C125 - 4'b 1111, // index[1252] SCMI_RESERVED_2_C125 - 4'b 1111, // index[1253] SCMI_RESERVED_3_C125 - 4'b 1111, // index[1254] SCMI_CHANNEL_FLAGS_C125 - 4'b 1111, // index[1255] SCMI_LENGTH_C125 - 4'b 1111, // index[1256] SCMI_MESSAGE_HEADER_C125 - 4'b 1111, // index[1257] SCMI_MESSAGE_PAYLOAD_1_C125 - 4'b 1111, // index[1258] SCMI_DOORBELL_C125 - 4'b 1111, // index[1259] SCMI_COMPLETION_INTERRUPT_C125 - 4'b 1111, // index[1260] SCMI_RESERVED_1_C126 - 4'b 1111, // index[1261] SCMI_CHANNEL_STATUS_C126 - 4'b 1111, // index[1262] SCMI_RESERVED_2_C126 - 4'b 1111, // index[1263] SCMI_RESERVED_3_C126 - 4'b 1111, // index[1264] SCMI_CHANNEL_FLAGS_C126 - 4'b 1111, // index[1265] SCMI_LENGTH_C126 - 4'b 1111, // index[1266] SCMI_MESSAGE_HEADER_C126 - 4'b 1111, // index[1267] SCMI_MESSAGE_PAYLOAD_1_C126 - 4'b 1111, // index[1268] SCMI_DOORBELL_C126 - 4'b 1111, // index[1269] SCMI_COMPLETION_INTERRUPT_C126 - 4'b 1111, // index[1270] SCMI_RESERVED_1_C127 - 4'b 1111, // index[1271] SCMI_CHANNEL_STATUS_C127 - 4'b 1111, // index[1272] SCMI_RESERVED_2_C127 - 4'b 1111, // index[1273] SCMI_RESERVED_3_C127 - 4'b 1111, // index[1274] SCMI_CHANNEL_FLAGS_C127 - 4'b 1111, // index[1275] SCMI_LENGTH_C127 - 4'b 1111, // index[1276] SCMI_MESSAGE_HEADER_C127 - 4'b 1111, // index[1277] SCMI_MESSAGE_PAYLOAD_1_C127 - 4'b 1111, // index[1278] SCMI_DOORBELL_C127 - 4'b 1111, // index[1279] SCMI_COMPLETION_INTERRUPT_C127 - 4'b 1111, // index[1280] SCMI_RESERVED_1_C128 - 4'b 1111, // index[1281] SCMI_CHANNEL_STATUS_C128 - 4'b 1111, // index[1282] SCMI_RESERVED_2_C128 - 4'b 1111, // index[1283] SCMI_RESERVED_3_C128 - 4'b 1111, // index[1284] SCMI_CHANNEL_FLAGS_C128 - 4'b 1111, // index[1285] SCMI_LENGTH_C128 - 4'b 1111, // index[1286] SCMI_MESSAGE_HEADER_C128 - 4'b 1111, // index[1287] SCMI_MESSAGE_PAYLOAD_1_C128 - 4'b 1111, // index[1288] SCMI_DOORBELL_C128 - 4'b 1111, // index[1289] SCMI_COMPLETION_INTERRUPT_C128 - 4'b 1111, // index[1290] SCMI_RESERVED_1_C129 - 4'b 1111, // index[1291] SCMI_CHANNEL_STATUS_C129 - 4'b 1111, // index[1292] SCMI_RESERVED_2_C129 - 4'b 1111, // index[1293] SCMI_RESERVED_3_C129 - 4'b 1111, // index[1294] SCMI_CHANNEL_FLAGS_C129 - 4'b 1111, // index[1295] SCMI_LENGTH_C129 - 4'b 1111, // index[1296] SCMI_MESSAGE_HEADER_C129 - 4'b 1111, // index[1297] SCMI_MESSAGE_PAYLOAD_1_C129 - 4'b 1111, // index[1298] SCMI_DOORBELL_C129 - 4'b 1111, // index[1299] SCMI_COMPLETION_INTERRUPT_C129 - 4'b 1111, // index[1300] SCMI_RESERVED_1_C130 - 4'b 1111, // index[1301] SCMI_CHANNEL_STATUS_C130 - 4'b 1111, // index[1302] SCMI_RESERVED_2_C130 - 4'b 1111, // index[1303] SCMI_RESERVED_3_C130 - 4'b 1111, // index[1304] SCMI_CHANNEL_FLAGS_C130 - 4'b 1111, // index[1305] SCMI_LENGTH_C130 - 4'b 1111, // index[1306] SCMI_MESSAGE_HEADER_C130 - 4'b 1111, // index[1307] SCMI_MESSAGE_PAYLOAD_1_C130 - 4'b 1111, // index[1308] SCMI_DOORBELL_C130 - 4'b 1111, // index[1309] SCMI_COMPLETION_INTERRUPT_C130 - 4'b 1111, // index[1310] SCMI_RESERVED_1_C131 - 4'b 1111, // index[1311] SCMI_CHANNEL_STATUS_C131 - 4'b 1111, // index[1312] SCMI_RESERVED_2_C131 - 4'b 1111, // index[1313] SCMI_RESERVED_3_C131 - 4'b 1111, // index[1314] SCMI_CHANNEL_FLAGS_C131 - 4'b 1111, // index[1315] SCMI_LENGTH_C131 - 4'b 1111, // index[1316] SCMI_MESSAGE_HEADER_C131 - 4'b 1111, // index[1317] SCMI_MESSAGE_PAYLOAD_1_C131 - 4'b 1111, // index[1318] SCMI_DOORBELL_C131 - 4'b 1111, // index[1319] SCMI_COMPLETION_INTERRUPT_C131 - 4'b 1111, // index[1320] SCMI_RESERVED_1_C132 - 4'b 1111, // index[1321] SCMI_CHANNEL_STATUS_C132 - 4'b 1111, // index[1322] SCMI_RESERVED_2_C132 - 4'b 1111, // index[1323] SCMI_RESERVED_3_C132 - 4'b 1111, // index[1324] SCMI_CHANNEL_FLAGS_C132 - 4'b 1111, // index[1325] SCMI_LENGTH_C132 - 4'b 1111, // index[1326] SCMI_MESSAGE_HEADER_C132 - 4'b 1111, // index[1327] SCMI_MESSAGE_PAYLOAD_1_C132 - 4'b 1111, // index[1328] SCMI_DOORBELL_C132 - 4'b 1111, // index[1329] SCMI_COMPLETION_INTERRUPT_C132 - 4'b 1111, // index[1330] SCMI_RESERVED_1_C133 - 4'b 1111, // index[1331] SCMI_CHANNEL_STATUS_C133 - 4'b 1111, // index[1332] SCMI_RESERVED_2_C133 - 4'b 1111, // index[1333] SCMI_RESERVED_3_C133 - 4'b 1111, // index[1334] SCMI_CHANNEL_FLAGS_C133 - 4'b 1111, // index[1335] SCMI_LENGTH_C133 - 4'b 1111, // index[1336] SCMI_MESSAGE_HEADER_C133 - 4'b 1111, // index[1337] SCMI_MESSAGE_PAYLOAD_1_C133 - 4'b 1111, // index[1338] SCMI_DOORBELL_C133 - 4'b 1111, // index[1339] SCMI_COMPLETION_INTERRUPT_C133 - 4'b 1111, // index[1340] SCMI_RESERVED_1_C134 - 4'b 1111, // index[1341] SCMI_CHANNEL_STATUS_C134 - 4'b 1111, // index[1342] SCMI_RESERVED_2_C134 - 4'b 1111, // index[1343] SCMI_RESERVED_3_C134 - 4'b 1111, // index[1344] SCMI_CHANNEL_FLAGS_C134 - 4'b 1111, // index[1345] SCMI_LENGTH_C134 - 4'b 1111, // index[1346] SCMI_MESSAGE_HEADER_C134 - 4'b 1111, // index[1347] SCMI_MESSAGE_PAYLOAD_1_C134 - 4'b 1111, // index[1348] SCMI_DOORBELL_C134 - 4'b 1111, // index[1349] SCMI_COMPLETION_INTERRUPT_C134 - 4'b 1111, // index[1350] SCMI_RESERVED_1_C135 - 4'b 1111, // index[1351] SCMI_CHANNEL_STATUS_C135 - 4'b 1111, // index[1352] SCMI_RESERVED_2_C135 - 4'b 1111, // index[1353] SCMI_RESERVED_3_C135 - 4'b 1111, // index[1354] SCMI_CHANNEL_FLAGS_C135 - 4'b 1111, // index[1355] SCMI_LENGTH_C135 - 4'b 1111, // index[1356] SCMI_MESSAGE_HEADER_C135 - 4'b 1111, // index[1357] SCMI_MESSAGE_PAYLOAD_1_C135 - 4'b 1111, // index[1358] SCMI_DOORBELL_C135 - 4'b 1111, // index[1359] SCMI_COMPLETION_INTERRUPT_C135 - 4'b 1111, // index[1360] SCMI_RESERVED_1_C136 - 4'b 1111, // index[1361] SCMI_CHANNEL_STATUS_C136 - 4'b 1111, // index[1362] SCMI_RESERVED_2_C136 - 4'b 1111, // index[1363] SCMI_RESERVED_3_C136 - 4'b 1111, // index[1364] SCMI_CHANNEL_FLAGS_C136 - 4'b 1111, // index[1365] SCMI_LENGTH_C136 - 4'b 1111, // index[1366] SCMI_MESSAGE_HEADER_C136 - 4'b 1111, // index[1367] SCMI_MESSAGE_PAYLOAD_1_C136 - 4'b 1111, // index[1368] SCMI_DOORBELL_C136 - 4'b 1111, // index[1369] SCMI_COMPLETION_INTERRUPT_C136 - 4'b 1111, // index[1370] SCMI_RESERVED_1_C137 - 4'b 1111, // index[1371] SCMI_CHANNEL_STATUS_C137 - 4'b 1111, // index[1372] SCMI_RESERVED_2_C137 - 4'b 1111, // index[1373] SCMI_RESERVED_3_C137 - 4'b 1111, // index[1374] SCMI_CHANNEL_FLAGS_C137 - 4'b 1111, // index[1375] SCMI_LENGTH_C137 - 4'b 1111, // index[1376] SCMI_MESSAGE_HEADER_C137 - 4'b 1111, // index[1377] SCMI_MESSAGE_PAYLOAD_1_C137 - 4'b 1111, // index[1378] SCMI_DOORBELL_C137 - 4'b 1111, // index[1379] SCMI_COMPLETION_INTERRUPT_C137 - 4'b 1111, // index[1380] SCMI_RESERVED_1_C138 - 4'b 1111, // index[1381] SCMI_CHANNEL_STATUS_C138 - 4'b 1111, // index[1382] SCMI_RESERVED_2_C138 - 4'b 1111, // index[1383] SCMI_RESERVED_3_C138 - 4'b 1111, // index[1384] SCMI_CHANNEL_FLAGS_C138 - 4'b 1111, // index[1385] SCMI_LENGTH_C138 - 4'b 1111, // index[1386] SCMI_MESSAGE_HEADER_C138 - 4'b 1111, // index[1387] SCMI_MESSAGE_PAYLOAD_1_C138 - 4'b 1111, // index[1388] SCMI_DOORBELL_C138 - 4'b 1111, // index[1389] SCMI_COMPLETION_INTERRUPT_C138 - 4'b 1111, // index[1390] SCMI_RESERVED_1_C139 - 4'b 1111, // index[1391] SCMI_CHANNEL_STATUS_C139 - 4'b 1111, // index[1392] SCMI_RESERVED_2_C139 - 4'b 1111, // index[1393] SCMI_RESERVED_3_C139 - 4'b 1111, // index[1394] SCMI_CHANNEL_FLAGS_C139 - 4'b 1111, // index[1395] SCMI_LENGTH_C139 - 4'b 1111, // index[1396] SCMI_MESSAGE_HEADER_C139 - 4'b 1111, // index[1397] SCMI_MESSAGE_PAYLOAD_1_C139 - 4'b 1111, // index[1398] SCMI_DOORBELL_C139 - 4'b 1111, // index[1399] SCMI_COMPLETION_INTERRUPT_C139 - 4'b 1111, // index[1400] SCMI_RESERVED_1_C140 - 4'b 1111, // index[1401] SCMI_CHANNEL_STATUS_C140 - 4'b 1111, // index[1402] SCMI_RESERVED_2_C140 - 4'b 1111, // index[1403] SCMI_RESERVED_3_C140 - 4'b 1111, // index[1404] SCMI_CHANNEL_FLAGS_C140 - 4'b 1111, // index[1405] SCMI_LENGTH_C140 - 4'b 1111, // index[1406] SCMI_MESSAGE_HEADER_C140 - 4'b 1111, // index[1407] SCMI_MESSAGE_PAYLOAD_1_C140 - 4'b 1111, // index[1408] SCMI_DOORBELL_C140 - 4'b 1111, // index[1409] SCMI_COMPLETION_INTERRUPT_C140 - 4'b 1111, // index[1410] SCMI_RESERVED_1_C141 - 4'b 1111, // index[1411] SCMI_CHANNEL_STATUS_C141 - 4'b 1111, // index[1412] SCMI_RESERVED_2_C141 - 4'b 1111, // index[1413] SCMI_RESERVED_3_C141 - 4'b 1111, // index[1414] SCMI_CHANNEL_FLAGS_C141 - 4'b 1111, // index[1415] SCMI_LENGTH_C141 - 4'b 1111, // index[1416] SCMI_MESSAGE_HEADER_C141 - 4'b 1111, // index[1417] SCMI_MESSAGE_PAYLOAD_1_C141 - 4'b 1111, // index[1418] SCMI_DOORBELL_C141 - 4'b 1111, // index[1419] SCMI_COMPLETION_INTERRUPT_C141 - 4'b 1111, // index[1420] SCMI_RESERVED_1_C142 - 4'b 1111, // index[1421] SCMI_CHANNEL_STATUS_C142 - 4'b 1111, // index[1422] SCMI_RESERVED_2_C142 - 4'b 1111, // index[1423] SCMI_RESERVED_3_C142 - 4'b 1111, // index[1424] SCMI_CHANNEL_FLAGS_C142 - 4'b 1111, // index[1425] SCMI_LENGTH_C142 - 4'b 1111, // index[1426] SCMI_MESSAGE_HEADER_C142 - 4'b 1111, // index[1427] SCMI_MESSAGE_PAYLOAD_1_C142 - 4'b 1111, // index[1428] SCMI_DOORBELL_C142 - 4'b 1111, // index[1429] SCMI_COMPLETION_INTERRUPT_C142 - 4'b 1111, // index[1430] SCMI_RESERVED_1_C143 - 4'b 1111, // index[1431] SCMI_CHANNEL_STATUS_C143 - 4'b 1111, // index[1432] SCMI_RESERVED_2_C143 - 4'b 1111, // index[1433] SCMI_RESERVED_3_C143 - 4'b 1111, // index[1434] SCMI_CHANNEL_FLAGS_C143 - 4'b 1111, // index[1435] SCMI_LENGTH_C143 - 4'b 1111, // index[1436] SCMI_MESSAGE_HEADER_C143 - 4'b 1111, // index[1437] SCMI_MESSAGE_PAYLOAD_1_C143 - 4'b 1111, // index[1438] SCMI_DOORBELL_C143 - 4'b 1111, // index[1439] SCMI_COMPLETION_INTERRUPT_C143 - 4'b 1111, // index[1440] SCMI_RESERVED_1_C144 - 4'b 1111, // index[1441] SCMI_CHANNEL_STATUS_C144 - 4'b 1111, // index[1442] SCMI_RESERVED_2_C144 - 4'b 1111, // index[1443] SCMI_RESERVED_3_C144 - 4'b 1111, // index[1444] SCMI_CHANNEL_FLAGS_C144 - 4'b 1111, // index[1445] SCMI_LENGTH_C144 - 4'b 1111, // index[1446] SCMI_MESSAGE_HEADER_C144 - 4'b 1111, // index[1447] SCMI_MESSAGE_PAYLOAD_1_C144 - 4'b 1111, // index[1448] SCMI_DOORBELL_C144 - 4'b 1111, // index[1449] SCMI_COMPLETION_INTERRUPT_C144 - 4'b 1111, // index[1450] SCMI_RESERVED_1_C145 - 4'b 1111, // index[1451] SCMI_CHANNEL_STATUS_C145 - 4'b 1111, // index[1452] SCMI_RESERVED_2_C145 - 4'b 1111, // index[1453] SCMI_RESERVED_3_C145 - 4'b 1111, // index[1454] SCMI_CHANNEL_FLAGS_C145 - 4'b 1111, // index[1455] SCMI_LENGTH_C145 - 4'b 1111, // index[1456] SCMI_MESSAGE_HEADER_C145 - 4'b 1111, // index[1457] SCMI_MESSAGE_PAYLOAD_1_C145 - 4'b 1111, // index[1458] SCMI_DOORBELL_C145 - 4'b 1111, // index[1459] SCMI_COMPLETION_INTERRUPT_C145 - 4'b 1111, // index[1460] SCMI_RESERVED_1_C146 - 4'b 1111, // index[1461] SCMI_CHANNEL_STATUS_C146 - 4'b 1111, // index[1462] SCMI_RESERVED_2_C146 - 4'b 1111, // index[1463] SCMI_RESERVED_3_C146 - 4'b 1111, // index[1464] SCMI_CHANNEL_FLAGS_C146 - 4'b 1111, // index[1465] SCMI_LENGTH_C146 - 4'b 1111, // index[1466] SCMI_MESSAGE_HEADER_C146 - 4'b 1111, // index[1467] SCMI_MESSAGE_PAYLOAD_1_C146 - 4'b 1111, // index[1468] SCMI_DOORBELL_C146 - 4'b 1111 // index[1469] SCMI_COMPLETION_INTERRUPT_C146 + parameter logic [3:0] SCMI_PERMIT [42] = '{ + 4'b 1111, // index[ 0] SCMI_RESERVED_1_C0 + 4'b 1111, // index[ 1] SCMI_CHANNEL_STATUS_C0 + 4'b 1111, // index[ 2] SCMI_RESERVED_2_C0 + 4'b 1111, // index[ 3] SCMI_RESERVED_3_C0 + 4'b 1111, // index[ 4] SCMI_CHANNEL_FLAGS_C0 + 4'b 1111, // index[ 5] SCMI_LENGTH_C0 + 4'b 1111, // index[ 6] SCMI_MESSAGE_HEADER_C0 + 4'b 1111, // index[ 7] SCMI_MESSAGE_PAYLOAD_0_C0 + 4'b 1111, // index[ 8] SCMI_MESSAGE_PAYLOAD_1_C0 + 4'b 1111, // index[ 9] SCMI_MESSAGE_PAYLOAD_2_C0 + 4'b 1111, // index[10] SCMI_MESSAGE_PAYLOAD_3_C0 + 4'b 1111, // index[11] SCMI_MESSAGE_PAYLOAD_4_C0 + 4'b 1111, // index[12] SCMI_MESSAGE_PAYLOAD_5_C0 + 4'b 1111, // index[13] SCMI_MESSAGE_PAYLOAD_6_C0 + 4'b 1111, // index[14] SCMI_MESSAGE_PAYLOAD_7_C0 + 4'b 1111, // index[15] SCMI_MESSAGE_PAYLOAD_8_C0 + 4'b 1111, // index[16] SCMI_MESSAGE_PAYLOAD_9_C0 + 4'b 1111, // index[17] SCMI_MESSAGE_PAYLOAD_10_C0 + 4'b 1111, // index[18] SCMI_MESSAGE_PAYLOAD_11_C0 + 4'b 1111, // index[19] SCMI_MESSAGE_PAYLOAD_12_C0 + 4'b 1111, // index[20] SCMI_MESSAGE_PAYLOAD_13_C0 + 4'b 1111, // index[21] SCMI_MESSAGE_PAYLOAD_14_C0 + 4'b 1111, // index[22] SCMI_MESSAGE_PAYLOAD_15_C0 + 4'b 1111, // index[23] SCMI_MESSAGE_PAYLOAD_16_C0 + 4'b 1111, // index[24] SCMI_MESSAGE_PAYLOAD_17_C0 + 4'b 1111, // index[25] SCMI_MESSAGE_PAYLOAD_18_C0 + 4'b 1111, // index[26] SCMI_MESSAGE_PAYLOAD_19_C0 + 4'b 1111, // index[27] SCMI_MESSAGE_PAYLOAD_20_C0 + 4'b 1111, // index[28] SCMI_MESSAGE_PAYLOAD_21_C0 + 4'b 1111, // index[29] SCMI_MESSAGE_PAYLOAD_22_C0 + 4'b 1111, // index[30] SCMI_MESSAGE_PAYLOAD_23_C0 + 4'b 1111, // index[31] SCMI_MESSAGE_PAYLOAD_24_C0 + 4'b 1111, // index[32] SCMI_MESSAGE_PAYLOAD_25_C0 + 4'b 1111, // index[33] SCMI_MESSAGE_PAYLOAD_26_C0 + 4'b 1111, // index[34] SCMI_MESSAGE_PAYLOAD_27_C0 + 4'b 1111, // index[35] SCMI_MESSAGE_PAYLOAD_28_C0 + 4'b 1111, // index[36] SCMI_MESSAGE_PAYLOAD_29_C0 + 4'b 1111, // index[37] SCMI_MESSAGE_PAYLOAD_30_C0 + 4'b 1111, // index[38] SCMI_MESSAGE_PAYLOAD_31_C0 + 4'b 1111, // index[39] SCMI_MESSAGE_PAYLOAD_32_C0 + 4'b 1111, // index[40] SCMI_DOORBELL_C0 + 4'b 1111 // index[41] SCMI_COMPLETION_INTERRUPT_C0 }; endpackage diff --git a/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_top.sv b/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_top.sv index dd7839d..e2801fd 100644 --- a/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_top.sv +++ b/hw/ips/axi_scmi_mailbox/rtl/scmi_reg_top.sv @@ -10,7 +10,7 @@ module scmi_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 13 + parameter int AW = 8 ) ( input clk_i, input rst_ni, @@ -82,6 +82,9 @@ module scmi_reg_top #( logic [31:0] reserved_2_c0_qs; logic [31:0] reserved_2_c0_wd; logic reserved_2_c0_we; + logic [31:0] reserved_3_c0_qs; + logic [31:0] reserved_3_c0_wd; + logic reserved_3_c0_we; logic channel_flags_c0_intr_enable_qs; logic channel_flags_c0_intr_enable_wd; logic channel_flags_c0_intr_enable_we; @@ -106,7905 +109,111 @@ module scmi_reg_top #( logic [3:0] message_header_c0_field1_qs; logic [3:0] message_header_c0_field1_wd; logic message_header_c0_field1_we; + logic [31:0] message_payload_0_c0_qs; + logic [31:0] message_payload_0_c0_wd; + logic message_payload_0_c0_we; logic [31:0] message_payload_1_c0_qs; logic [31:0] message_payload_1_c0_wd; logic message_payload_1_c0_we; - logic doorbell_c0_intr_qs; - logic doorbell_c0_intr_wd; - logic doorbell_c0_intr_we; - logic [30:0] doorbell_c0_preserve_mask_qs; - logic [30:0] doorbell_c0_preserve_mask_wd; - logic doorbell_c0_preserve_mask_we; - logic completion_interrupt_c0_intr_qs; - logic completion_interrupt_c0_intr_wd; - logic completion_interrupt_c0_intr_we; - logic [30:0] completion_interrupt_c0_preserve_mask_qs; - logic [30:0] completion_interrupt_c0_preserve_mask_wd; - logic completion_interrupt_c0_preserve_mask_we; - logic [31:0] reserved_1_c1_qs; - logic [31:0] reserved_1_c1_wd; - logic reserved_1_c1_we; - logic channel_status_c1_channel_free_qs; - logic channel_status_c1_channel_free_wd; - logic channel_status_c1_channel_free_we; - logic channel_status_c1_channel_error_qs; - logic channel_status_c1_channel_error_wd; - logic channel_status_c1_channel_error_we; - logic [29:0] channel_status_c1_field1_qs; - logic [29:0] channel_status_c1_field1_wd; - logic channel_status_c1_field1_we; - logic [31:0] reserved_2_c1_qs; - logic [31:0] reserved_2_c1_wd; - logic reserved_2_c1_we; - logic channel_flags_c1_intr_enable_qs; - logic channel_flags_c1_intr_enable_wd; - logic channel_flags_c1_intr_enable_we; - logic [30:0] channel_flags_c1_field1_qs; - logic [30:0] channel_flags_c1_field1_wd; - logic channel_flags_c1_field1_we; - logic [31:0] length_c1_qs; - logic [31:0] length_c1_wd; - logic length_c1_we; - logic [7:0] message_header_c1_message_id_qs; - logic [7:0] message_header_c1_message_id_wd; - logic message_header_c1_message_id_we; - logic [1:0] message_header_c1_message_type_qs; - logic [1:0] message_header_c1_message_type_wd; - logic message_header_c1_message_type_we; - logic [7:0] message_header_c1_protocol_id_qs; - logic [7:0] message_header_c1_protocol_id_wd; - logic message_header_c1_protocol_id_we; - logic [9:0] message_header_c1_token_qs; - logic [9:0] message_header_c1_token_wd; - logic message_header_c1_token_we; - logic [3:0] message_header_c1_field1_qs; - logic [3:0] message_header_c1_field1_wd; - logic message_header_c1_field1_we; - logic [31:0] message_payload_1_c1_qs; - logic [31:0] message_payload_1_c1_wd; - logic message_payload_1_c1_we; - logic doorbell_c1_intr_qs; - logic doorbell_c1_intr_wd; - logic doorbell_c1_intr_we; - logic [30:0] doorbell_c1_preserve_mask_qs; - logic [30:0] doorbell_c1_preserve_mask_wd; - logic doorbell_c1_preserve_mask_we; - logic completion_interrupt_c1_intr_qs; - logic completion_interrupt_c1_intr_wd; - logic completion_interrupt_c1_intr_we; - logic [30:0] completion_interrupt_c1_preserve_mask_qs; - logic [30:0] completion_interrupt_c1_preserve_mask_wd; - logic completion_interrupt_c1_preserve_mask_we; - logic [31:0] reserved_1_c2_qs; - logic [31:0] reserved_1_c2_wd; - logic reserved_1_c2_we; - logic channel_status_c2_channel_free_qs; - logic channel_status_c2_channel_free_wd; - logic channel_status_c2_channel_free_we; - logic channel_status_c2_channel_error_qs; - logic channel_status_c2_channel_error_wd; - logic channel_status_c2_channel_error_we; - logic [29:0] channel_status_c2_field1_qs; - logic [29:0] channel_status_c2_field1_wd; - logic channel_status_c2_field1_we; - logic [31:0] reserved_2_c2_qs; - logic [31:0] reserved_2_c2_wd; - logic reserved_2_c2_we; - logic channel_flags_c2_intr_enable_qs; - logic channel_flags_c2_intr_enable_wd; - logic channel_flags_c2_intr_enable_we; - logic [30:0] channel_flags_c2_field1_qs; - logic [30:0] channel_flags_c2_field1_wd; - logic channel_flags_c2_field1_we; - logic [31:0] length_c2_qs; - logic [31:0] length_c2_wd; - logic length_c2_we; - logic [7:0] message_header_c2_message_id_qs; - logic [7:0] message_header_c2_message_id_wd; - logic message_header_c2_message_id_we; - logic [1:0] message_header_c2_message_type_qs; - logic [1:0] message_header_c2_message_type_wd; - logic message_header_c2_message_type_we; - logic [7:0] message_header_c2_protocol_id_qs; - logic [7:0] message_header_c2_protocol_id_wd; - logic message_header_c2_protocol_id_we; - logic [9:0] message_header_c2_token_qs; - logic [9:0] message_header_c2_token_wd; - logic message_header_c2_token_we; - logic [3:0] message_header_c2_field1_qs; - logic [3:0] message_header_c2_field1_wd; - logic message_header_c2_field1_we; - logic [31:0] message_payload_1_c2_qs; - logic [31:0] message_payload_1_c2_wd; - logic message_payload_1_c2_we; - logic doorbell_c2_intr_qs; - logic doorbell_c2_intr_wd; - logic doorbell_c2_intr_we; - logic [30:0] doorbell_c2_preserve_mask_qs; - logic [30:0] doorbell_c2_preserve_mask_wd; - logic doorbell_c2_preserve_mask_we; - logic completion_interrupt_c2_intr_qs; - logic completion_interrupt_c2_intr_wd; - logic completion_interrupt_c2_intr_we; - logic [30:0] completion_interrupt_c2_preserve_mask_qs; - logic [30:0] completion_interrupt_c2_preserve_mask_wd; - logic completion_interrupt_c2_preserve_mask_we; - logic [31:0] reserved_1_c3_qs; - logic [31:0] reserved_1_c3_wd; - logic reserved_1_c3_we; - logic channel_status_c3_channel_free_qs; - logic channel_status_c3_channel_free_wd; - logic channel_status_c3_channel_free_we; - logic channel_status_c3_channel_error_qs; - logic channel_status_c3_channel_error_wd; - logic channel_status_c3_channel_error_we; - logic [29:0] channel_status_c3_field1_qs; - logic [29:0] channel_status_c3_field1_wd; - logic channel_status_c3_field1_we; - logic [31:0] reserved_2_c3_qs; - logic [31:0] reserved_2_c3_wd; - logic reserved_2_c3_we; - logic channel_flags_c3_intr_enable_qs; - logic channel_flags_c3_intr_enable_wd; - logic channel_flags_c3_intr_enable_we; - logic [30:0] channel_flags_c3_field1_qs; - logic [30:0] channel_flags_c3_field1_wd; - logic channel_flags_c3_field1_we; - logic [31:0] length_c3_qs; - logic [31:0] length_c3_wd; - logic length_c3_we; - logic [7:0] message_header_c3_message_id_qs; - logic [7:0] message_header_c3_message_id_wd; - logic message_header_c3_message_id_we; - logic [1:0] message_header_c3_message_type_qs; - logic [1:0] message_header_c3_message_type_wd; - logic message_header_c3_message_type_we; - logic [7:0] message_header_c3_protocol_id_qs; - logic [7:0] message_header_c3_protocol_id_wd; - logic message_header_c3_protocol_id_we; - logic [9:0] message_header_c3_token_qs; - logic [9:0] message_header_c3_token_wd; - logic message_header_c3_token_we; - logic [3:0] message_header_c3_field1_qs; - logic [3:0] message_header_c3_field1_wd; - logic message_header_c3_field1_we; - logic [31:0] message_payload_1_c3_qs; - logic [31:0] message_payload_1_c3_wd; - logic message_payload_1_c3_we; - logic doorbell_c3_intr_qs; - logic doorbell_c3_intr_wd; - logic doorbell_c3_intr_we; - logic [30:0] doorbell_c3_preserve_mask_qs; - logic [30:0] doorbell_c3_preserve_mask_wd; - logic doorbell_c3_preserve_mask_we; - logic completion_interrupt_c3_intr_qs; - logic completion_interrupt_c3_intr_wd; - logic completion_interrupt_c3_intr_we; - logic [30:0] completion_interrupt_c3_preserve_mask_qs; - logic [30:0] completion_interrupt_c3_preserve_mask_wd; - logic completion_interrupt_c3_preserve_mask_we; - logic [31:0] reserved_1_c4_qs; - logic [31:0] reserved_1_c4_wd; - logic reserved_1_c4_we; - logic channel_status_c4_channel_free_qs; - logic channel_status_c4_channel_free_wd; - logic channel_status_c4_channel_free_we; - logic channel_status_c4_channel_error_qs; - logic channel_status_c4_channel_error_wd; - logic channel_status_c4_channel_error_we; - logic [29:0] channel_status_c4_field1_qs; - logic [29:0] channel_status_c4_field1_wd; - logic channel_status_c4_field1_we; - logic [31:0] reserved_2_c4_qs; - logic [31:0] reserved_2_c4_wd; - logic reserved_2_c4_we; - logic channel_flags_c4_intr_enable_qs; - logic channel_flags_c4_intr_enable_wd; - logic channel_flags_c4_intr_enable_we; - logic [30:0] channel_flags_c4_field1_qs; - logic [30:0] channel_flags_c4_field1_wd; - logic channel_flags_c4_field1_we; - logic [31:0] length_c4_qs; - logic [31:0] length_c4_wd; - logic length_c4_we; - logic [7:0] message_header_c4_message_id_qs; - logic [7:0] message_header_c4_message_id_wd; - logic message_header_c4_message_id_we; - logic [1:0] message_header_c4_message_type_qs; - logic [1:0] message_header_c4_message_type_wd; - logic message_header_c4_message_type_we; - logic [7:0] message_header_c4_protocol_id_qs; - logic [7:0] message_header_c4_protocol_id_wd; - logic message_header_c4_protocol_id_we; - logic [9:0] message_header_c4_token_qs; - logic [9:0] message_header_c4_token_wd; - logic message_header_c4_token_we; - logic [3:0] message_header_c4_field1_qs; - logic [3:0] message_header_c4_field1_wd; - logic message_header_c4_field1_we; - logic [31:0] message_payload_1_c4_qs; - logic [31:0] message_payload_1_c4_wd; - logic message_payload_1_c4_we; - logic doorbell_c4_intr_qs; - logic doorbell_c4_intr_wd; - logic doorbell_c4_intr_we; - logic [30:0] doorbell_c4_preserve_mask_qs; - logic [30:0] doorbell_c4_preserve_mask_wd; - logic doorbell_c4_preserve_mask_we; - logic completion_interrupt_c4_intr_qs; - logic completion_interrupt_c4_intr_wd; - logic completion_interrupt_c4_intr_we; - logic [30:0] completion_interrupt_c4_preserve_mask_qs; - logic [30:0] completion_interrupt_c4_preserve_mask_wd; - logic completion_interrupt_c4_preserve_mask_we; - logic [31:0] reserved_1_c5_qs; - logic [31:0] reserved_1_c5_wd; - logic reserved_1_c5_we; - logic channel_status_c5_channel_free_qs; - logic channel_status_c5_channel_free_wd; - logic channel_status_c5_channel_free_we; - logic channel_status_c5_channel_error_qs; - logic channel_status_c5_channel_error_wd; - logic channel_status_c5_channel_error_we; - logic [29:0] channel_status_c5_field1_qs; - logic [29:0] channel_status_c5_field1_wd; - logic channel_status_c5_field1_we; - logic [31:0] reserved_2_c5_qs; - logic [31:0] reserved_2_c5_wd; - logic reserved_2_c5_we; - logic channel_flags_c5_intr_enable_qs; - logic channel_flags_c5_intr_enable_wd; - logic channel_flags_c5_intr_enable_we; - logic [30:0] channel_flags_c5_field1_qs; - logic [30:0] channel_flags_c5_field1_wd; - logic channel_flags_c5_field1_we; - logic [31:0] length_c5_qs; - logic [31:0] length_c5_wd; - logic length_c5_we; - logic [7:0] message_header_c5_message_id_qs; - logic [7:0] message_header_c5_message_id_wd; - logic message_header_c5_message_id_we; - logic [1:0] message_header_c5_message_type_qs; - logic [1:0] message_header_c5_message_type_wd; - logic message_header_c5_message_type_we; - logic [7:0] message_header_c5_protocol_id_qs; - logic [7:0] message_header_c5_protocol_id_wd; - logic message_header_c5_protocol_id_we; - logic [9:0] message_header_c5_token_qs; - logic [9:0] message_header_c5_token_wd; - logic message_header_c5_token_we; - logic [3:0] message_header_c5_field1_qs; - logic [3:0] message_header_c5_field1_wd; - logic message_header_c5_field1_we; - logic [31:0] message_payload_1_c5_qs; - logic [31:0] message_payload_1_c5_wd; - logic message_payload_1_c5_we; - logic doorbell_c5_intr_qs; - logic doorbell_c5_intr_wd; - logic doorbell_c5_intr_we; - logic [30:0] doorbell_c5_preserve_mask_qs; - logic [30:0] doorbell_c5_preserve_mask_wd; - logic doorbell_c5_preserve_mask_we; - logic completion_interrupt_c5_intr_qs; - logic completion_interrupt_c5_intr_wd; - logic completion_interrupt_c5_intr_we; - logic [30:0] completion_interrupt_c5_preserve_mask_qs; - logic [30:0] completion_interrupt_c5_preserve_mask_wd; - logic completion_interrupt_c5_preserve_mask_we; - logic [31:0] reserved_1_c6_qs; - logic [31:0] reserved_1_c6_wd; - logic reserved_1_c6_we; - logic channel_status_c6_channel_free_qs; - logic channel_status_c6_channel_free_wd; - logic channel_status_c6_channel_free_we; - logic channel_status_c6_channel_error_qs; - logic channel_status_c6_channel_error_wd; - logic channel_status_c6_channel_error_we; - logic [29:0] channel_status_c6_field1_qs; - logic [29:0] channel_status_c6_field1_wd; - logic channel_status_c6_field1_we; - logic [31:0] reserved_2_c6_qs; - logic [31:0] reserved_2_c6_wd; - logic reserved_2_c6_we; - logic channel_flags_c6_intr_enable_qs; - logic channel_flags_c6_intr_enable_wd; - logic channel_flags_c6_intr_enable_we; - logic [30:0] channel_flags_c6_field1_qs; - logic [30:0] channel_flags_c6_field1_wd; - logic channel_flags_c6_field1_we; - logic [31:0] length_c6_qs; - logic [31:0] length_c6_wd; - logic length_c6_we; - logic [7:0] message_header_c6_message_id_qs; - logic [7:0] message_header_c6_message_id_wd; - logic message_header_c6_message_id_we; - logic [1:0] message_header_c6_message_type_qs; - logic [1:0] message_header_c6_message_type_wd; - logic message_header_c6_message_type_we; - logic [7:0] message_header_c6_protocol_id_qs; - logic [7:0] message_header_c6_protocol_id_wd; - logic message_header_c6_protocol_id_we; - logic [9:0] message_header_c6_token_qs; - logic [9:0] message_header_c6_token_wd; - logic message_header_c6_token_we; - logic [3:0] message_header_c6_field1_qs; - logic [3:0] message_header_c6_field1_wd; - logic message_header_c6_field1_we; - logic [31:0] message_payload_1_c6_qs; - logic [31:0] message_payload_1_c6_wd; - logic message_payload_1_c6_we; - logic doorbell_c6_intr_qs; - logic doorbell_c6_intr_wd; - logic doorbell_c6_intr_we; - logic [30:0] doorbell_c6_preserve_mask_qs; - logic [30:0] doorbell_c6_preserve_mask_wd; - logic doorbell_c6_preserve_mask_we; - logic completion_interrupt_c6_intr_qs; - logic completion_interrupt_c6_intr_wd; - logic completion_interrupt_c6_intr_we; - logic [30:0] completion_interrupt_c6_preserve_mask_qs; - logic [30:0] completion_interrupt_c6_preserve_mask_wd; - logic completion_interrupt_c6_preserve_mask_we; - logic [31:0] reserved_1_c7_qs; - logic [31:0] reserved_1_c7_wd; - logic reserved_1_c7_we; - logic channel_status_c7_channel_free_qs; - logic channel_status_c7_channel_free_wd; - logic channel_status_c7_channel_free_we; - logic channel_status_c7_channel_error_qs; - logic channel_status_c7_channel_error_wd; - logic channel_status_c7_channel_error_we; - logic [29:0] channel_status_c7_field1_qs; - logic [29:0] channel_status_c7_field1_wd; - logic channel_status_c7_field1_we; - logic [31:0] reserved_2_c7_qs; - logic [31:0] reserved_2_c7_wd; - logic reserved_2_c7_we; - logic channel_flags_c7_intr_enable_qs; - logic channel_flags_c7_intr_enable_wd; - logic channel_flags_c7_intr_enable_we; - logic [30:0] channel_flags_c7_field1_qs; - logic [30:0] channel_flags_c7_field1_wd; - logic channel_flags_c7_field1_we; - logic [31:0] length_c7_qs; - logic [31:0] length_c7_wd; - logic length_c7_we; - logic [7:0] message_header_c7_message_id_qs; - logic [7:0] message_header_c7_message_id_wd; - logic message_header_c7_message_id_we; - logic [1:0] message_header_c7_message_type_qs; - logic [1:0] message_header_c7_message_type_wd; - logic message_header_c7_message_type_we; - logic [7:0] message_header_c7_protocol_id_qs; - logic [7:0] message_header_c7_protocol_id_wd; - logic message_header_c7_protocol_id_we; - logic [9:0] message_header_c7_token_qs; - logic [9:0] message_header_c7_token_wd; - logic message_header_c7_token_we; - logic [3:0] message_header_c7_field1_qs; - logic [3:0] message_header_c7_field1_wd; - logic message_header_c7_field1_we; - logic [31:0] message_payload_1_c7_qs; - logic [31:0] message_payload_1_c7_wd; - logic message_payload_1_c7_we; - logic doorbell_c7_intr_qs; - logic doorbell_c7_intr_wd; - logic doorbell_c7_intr_we; - logic [30:0] doorbell_c7_preserve_mask_qs; - logic [30:0] doorbell_c7_preserve_mask_wd; - logic doorbell_c7_preserve_mask_we; - logic completion_interrupt_c7_intr_qs; - logic completion_interrupt_c7_intr_wd; - logic completion_interrupt_c7_intr_we; - logic [30:0] completion_interrupt_c7_preserve_mask_qs; - logic [30:0] completion_interrupt_c7_preserve_mask_wd; - logic completion_interrupt_c7_preserve_mask_we; - logic [31:0] reserved_1_c8_qs; - logic [31:0] reserved_1_c8_wd; - logic reserved_1_c8_we; - logic channel_status_c8_channel_free_qs; - logic channel_status_c8_channel_free_wd; - logic channel_status_c8_channel_free_we; - logic channel_status_c8_channel_error_qs; - logic channel_status_c8_channel_error_wd; - logic channel_status_c8_channel_error_we; - logic [29:0] channel_status_c8_field1_qs; - logic [29:0] channel_status_c8_field1_wd; - logic channel_status_c8_field1_we; - logic [31:0] reserved_2_c8_qs; - logic [31:0] reserved_2_c8_wd; - logic reserved_2_c8_we; - logic channel_flags_c8_intr_enable_qs; - logic channel_flags_c8_intr_enable_wd; - logic channel_flags_c8_intr_enable_we; - logic [30:0] channel_flags_c8_field1_qs; - logic [30:0] channel_flags_c8_field1_wd; - logic channel_flags_c8_field1_we; - logic [31:0] length_c8_qs; - logic [31:0] length_c8_wd; - logic length_c8_we; - logic [7:0] message_header_c8_message_id_qs; - logic [7:0] message_header_c8_message_id_wd; - logic message_header_c8_message_id_we; - logic [1:0] message_header_c8_message_type_qs; - logic [1:0] message_header_c8_message_type_wd; - logic message_header_c8_message_type_we; - logic [7:0] message_header_c8_protocol_id_qs; - logic [7:0] message_header_c8_protocol_id_wd; - logic message_header_c8_protocol_id_we; - logic [9:0] message_header_c8_token_qs; - logic [9:0] message_header_c8_token_wd; - logic message_header_c8_token_we; - logic [3:0] message_header_c8_field1_qs; - logic [3:0] message_header_c8_field1_wd; - logic message_header_c8_field1_we; - logic [31:0] message_payload_1_c8_qs; - logic [31:0] message_payload_1_c8_wd; - logic message_payload_1_c8_we; - logic doorbell_c8_intr_qs; - logic doorbell_c8_intr_wd; - logic doorbell_c8_intr_we; - logic [30:0] doorbell_c8_preserve_mask_qs; - logic [30:0] doorbell_c8_preserve_mask_wd; - logic doorbell_c8_preserve_mask_we; - logic completion_interrupt_c8_intr_qs; - logic completion_interrupt_c8_intr_wd; - logic completion_interrupt_c8_intr_we; - logic [30:0] completion_interrupt_c8_preserve_mask_qs; - logic [30:0] completion_interrupt_c8_preserve_mask_wd; - logic completion_interrupt_c8_preserve_mask_we; - logic [31:0] reserved_1_c9_qs; - logic [31:0] reserved_1_c9_wd; - logic reserved_1_c9_we; - logic channel_status_c9_channel_free_qs; - logic channel_status_c9_channel_free_wd; - logic channel_status_c9_channel_free_we; - logic channel_status_c9_channel_error_qs; - logic channel_status_c9_channel_error_wd; - logic channel_status_c9_channel_error_we; - logic [29:0] channel_status_c9_field1_qs; - logic [29:0] channel_status_c9_field1_wd; - logic channel_status_c9_field1_we; - logic [31:0] reserved_2_c9_qs; - logic [31:0] reserved_2_c9_wd; - logic reserved_2_c9_we; - logic channel_flags_c9_intr_enable_qs; - logic channel_flags_c9_intr_enable_wd; - logic channel_flags_c9_intr_enable_we; - logic [30:0] channel_flags_c9_field1_qs; - logic [30:0] channel_flags_c9_field1_wd; - logic channel_flags_c9_field1_we; - logic [31:0] length_c9_qs; - logic [31:0] length_c9_wd; - logic length_c9_we; - logic [7:0] message_header_c9_message_id_qs; - logic [7:0] message_header_c9_message_id_wd; - logic message_header_c9_message_id_we; - logic [1:0] message_header_c9_message_type_qs; - logic [1:0] message_header_c9_message_type_wd; - logic message_header_c9_message_type_we; - logic [7:0] message_header_c9_protocol_id_qs; - logic [7:0] message_header_c9_protocol_id_wd; - logic message_header_c9_protocol_id_we; - logic [9:0] message_header_c9_token_qs; - logic [9:0] message_header_c9_token_wd; - logic message_header_c9_token_we; - logic [3:0] message_header_c9_field1_qs; - logic [3:0] message_header_c9_field1_wd; - logic message_header_c9_field1_we; - logic [31:0] message_payload_1_c9_qs; - logic [31:0] message_payload_1_c9_wd; - logic message_payload_1_c9_we; - logic doorbell_c9_intr_qs; - logic doorbell_c9_intr_wd; - logic doorbell_c9_intr_we; - logic [30:0] doorbell_c9_preserve_mask_qs; - logic [30:0] doorbell_c9_preserve_mask_wd; - logic doorbell_c9_preserve_mask_we; - logic completion_interrupt_c9_intr_qs; - logic completion_interrupt_c9_intr_wd; - logic completion_interrupt_c9_intr_we; - logic [30:0] completion_interrupt_c9_preserve_mask_qs; - logic [30:0] completion_interrupt_c9_preserve_mask_wd; - logic completion_interrupt_c9_preserve_mask_we; - logic [31:0] reserved_1_c10_qs; - logic [31:0] reserved_1_c10_wd; - logic reserved_1_c10_we; - logic channel_status_c10_channel_free_qs; - logic channel_status_c10_channel_free_wd; - logic channel_status_c10_channel_free_we; - logic channel_status_c10_channel_error_qs; - logic channel_status_c10_channel_error_wd; - logic channel_status_c10_channel_error_we; - logic [29:0] channel_status_c10_field1_qs; - logic [29:0] channel_status_c10_field1_wd; - logic channel_status_c10_field1_we; - logic [31:0] reserved_2_c10_qs; - logic [31:0] reserved_2_c10_wd; - logic reserved_2_c10_we; - logic channel_flags_c10_intr_enable_qs; - logic channel_flags_c10_intr_enable_wd; - logic channel_flags_c10_intr_enable_we; - logic [30:0] channel_flags_c10_field1_qs; - logic [30:0] channel_flags_c10_field1_wd; - logic channel_flags_c10_field1_we; - logic [31:0] length_c10_qs; - logic [31:0] length_c10_wd; - logic length_c10_we; - logic [7:0] message_header_c10_message_id_qs; - logic [7:0] message_header_c10_message_id_wd; - logic message_header_c10_message_id_we; - logic [1:0] message_header_c10_message_type_qs; - logic [1:0] message_header_c10_message_type_wd; - logic message_header_c10_message_type_we; - logic [7:0] message_header_c10_protocol_id_qs; - logic [7:0] message_header_c10_protocol_id_wd; - logic message_header_c10_protocol_id_we; - logic [9:0] message_header_c10_token_qs; - logic [9:0] message_header_c10_token_wd; - logic message_header_c10_token_we; - logic [3:0] message_header_c10_field1_qs; - logic [3:0] message_header_c10_field1_wd; - logic message_header_c10_field1_we; - logic [31:0] message_payload_1_c10_qs; - logic [31:0] message_payload_1_c10_wd; - logic message_payload_1_c10_we; - logic doorbell_c10_intr_qs; - logic doorbell_c10_intr_wd; - logic doorbell_c10_intr_we; - logic [30:0] doorbell_c10_preserve_mask_qs; - logic [30:0] doorbell_c10_preserve_mask_wd; - logic doorbell_c10_preserve_mask_we; - logic completion_interrupt_c10_intr_qs; - logic completion_interrupt_c10_intr_wd; - logic completion_interrupt_c10_intr_we; - logic [30:0] completion_interrupt_c10_preserve_mask_qs; - logic [30:0] completion_interrupt_c10_preserve_mask_wd; - logic completion_interrupt_c10_preserve_mask_we; - logic [31:0] reserved_1_c11_qs; - logic [31:0] reserved_1_c11_wd; - logic reserved_1_c11_we; - logic channel_status_c11_channel_free_qs; - logic channel_status_c11_channel_free_wd; - logic channel_status_c11_channel_free_we; - logic channel_status_c11_channel_error_qs; - logic channel_status_c11_channel_error_wd; - logic channel_status_c11_channel_error_we; - logic [29:0] channel_status_c11_field1_qs; - logic [29:0] channel_status_c11_field1_wd; - logic channel_status_c11_field1_we; - logic [31:0] reserved_2_c11_qs; - logic [31:0] reserved_2_c11_wd; - logic reserved_2_c11_we; - logic channel_flags_c11_intr_enable_qs; - logic channel_flags_c11_intr_enable_wd; - logic channel_flags_c11_intr_enable_we; - logic [30:0] channel_flags_c11_field1_qs; - logic [30:0] channel_flags_c11_field1_wd; - logic channel_flags_c11_field1_we; - logic [31:0] length_c11_qs; - logic [31:0] length_c11_wd; - logic length_c11_we; - logic [7:0] message_header_c11_message_id_qs; - logic [7:0] message_header_c11_message_id_wd; - logic message_header_c11_message_id_we; - logic [1:0] message_header_c11_message_type_qs; - logic [1:0] message_header_c11_message_type_wd; - logic message_header_c11_message_type_we; - logic [7:0] message_header_c11_protocol_id_qs; - logic [7:0] message_header_c11_protocol_id_wd; - logic message_header_c11_protocol_id_we; - logic [9:0] message_header_c11_token_qs; - logic [9:0] message_header_c11_token_wd; - logic message_header_c11_token_we; - logic [3:0] message_header_c11_field1_qs; - logic [3:0] message_header_c11_field1_wd; - logic message_header_c11_field1_we; - logic [31:0] message_payload_1_c11_qs; - logic [31:0] message_payload_1_c11_wd; - logic message_payload_1_c11_we; - logic doorbell_c11_intr_qs; - logic doorbell_c11_intr_wd; - logic doorbell_c11_intr_we; - logic [30:0] doorbell_c11_preserve_mask_qs; - logic [30:0] doorbell_c11_preserve_mask_wd; - logic doorbell_c11_preserve_mask_we; - logic completion_interrupt_c11_intr_qs; - logic completion_interrupt_c11_intr_wd; - logic completion_interrupt_c11_intr_we; - logic [30:0] completion_interrupt_c11_preserve_mask_qs; - logic [30:0] completion_interrupt_c11_preserve_mask_wd; - logic completion_interrupt_c11_preserve_mask_we; - logic [31:0] reserved_1_c12_qs; - logic [31:0] reserved_1_c12_wd; - logic reserved_1_c12_we; - logic channel_status_c12_channel_free_qs; - logic channel_status_c12_channel_free_wd; - logic channel_status_c12_channel_free_we; - logic channel_status_c12_channel_error_qs; - logic channel_status_c12_channel_error_wd; - logic channel_status_c12_channel_error_we; - logic [29:0] channel_status_c12_field1_qs; - logic [29:0] channel_status_c12_field1_wd; - logic channel_status_c12_field1_we; - logic [31:0] reserved_2_c12_qs; - logic [31:0] reserved_2_c12_wd; - logic reserved_2_c12_we; - logic channel_flags_c12_intr_enable_qs; - logic channel_flags_c12_intr_enable_wd; - logic channel_flags_c12_intr_enable_we; - logic [30:0] channel_flags_c12_field1_qs; - logic [30:0] channel_flags_c12_field1_wd; - logic channel_flags_c12_field1_we; - logic [31:0] length_c12_qs; - logic [31:0] length_c12_wd; - logic length_c12_we; - logic [7:0] message_header_c12_message_id_qs; - logic [7:0] message_header_c12_message_id_wd; - logic message_header_c12_message_id_we; - logic [1:0] message_header_c12_message_type_qs; - logic [1:0] message_header_c12_message_type_wd; - logic message_header_c12_message_type_we; - logic [7:0] message_header_c12_protocol_id_qs; - logic [7:0] message_header_c12_protocol_id_wd; - logic message_header_c12_protocol_id_we; - logic [9:0] message_header_c12_token_qs; - logic [9:0] message_header_c12_token_wd; - logic message_header_c12_token_we; - logic [3:0] message_header_c12_field1_qs; - logic [3:0] message_header_c12_field1_wd; - logic message_header_c12_field1_we; - logic [31:0] message_payload_1_c12_qs; - logic [31:0] message_payload_1_c12_wd; - logic message_payload_1_c12_we; - logic doorbell_c12_intr_qs; - logic doorbell_c12_intr_wd; - logic doorbell_c12_intr_we; - logic [30:0] doorbell_c12_preserve_mask_qs; - logic [30:0] doorbell_c12_preserve_mask_wd; - logic doorbell_c12_preserve_mask_we; - logic completion_interrupt_c12_intr_qs; - logic completion_interrupt_c12_intr_wd; - logic completion_interrupt_c12_intr_we; - logic [30:0] completion_interrupt_c12_preserve_mask_qs; - logic [30:0] completion_interrupt_c12_preserve_mask_wd; - logic completion_interrupt_c12_preserve_mask_we; - logic [31:0] reserved_1_c13_qs; - logic [31:0] reserved_1_c13_wd; - logic reserved_1_c13_we; - logic channel_status_c13_channel_free_qs; - logic channel_status_c13_channel_free_wd; - logic channel_status_c13_channel_free_we; - logic channel_status_c13_channel_error_qs; - logic channel_status_c13_channel_error_wd; - logic channel_status_c13_channel_error_we; - logic [29:0] channel_status_c13_field1_qs; - logic [29:0] channel_status_c13_field1_wd; - logic channel_status_c13_field1_we; - logic [31:0] reserved_2_c13_qs; - logic [31:0] reserved_2_c13_wd; - logic reserved_2_c13_we; - logic channel_flags_c13_intr_enable_qs; - logic channel_flags_c13_intr_enable_wd; - logic channel_flags_c13_intr_enable_we; - logic [30:0] channel_flags_c13_field1_qs; - logic [30:0] channel_flags_c13_field1_wd; - logic channel_flags_c13_field1_we; - logic [31:0] length_c13_qs; - logic [31:0] length_c13_wd; - logic length_c13_we; - logic [7:0] message_header_c13_message_id_qs; - logic [7:0] message_header_c13_message_id_wd; - logic message_header_c13_message_id_we; - logic [1:0] message_header_c13_message_type_qs; - logic [1:0] message_header_c13_message_type_wd; - logic message_header_c13_message_type_we; - logic [7:0] message_header_c13_protocol_id_qs; - logic [7:0] message_header_c13_protocol_id_wd; - logic message_header_c13_protocol_id_we; - logic [9:0] message_header_c13_token_qs; - logic [9:0] message_header_c13_token_wd; - logic message_header_c13_token_we; - logic [3:0] message_header_c13_field1_qs; - logic [3:0] message_header_c13_field1_wd; - logic message_header_c13_field1_we; - logic [31:0] message_payload_1_c13_qs; - logic [31:0] message_payload_1_c13_wd; - logic message_payload_1_c13_we; - logic doorbell_c13_intr_qs; - logic doorbell_c13_intr_wd; - logic doorbell_c13_intr_we; - logic [30:0] doorbell_c13_preserve_mask_qs; - logic [30:0] doorbell_c13_preserve_mask_wd; - logic doorbell_c13_preserve_mask_we; - logic completion_interrupt_c13_intr_qs; - logic completion_interrupt_c13_intr_wd; - logic completion_interrupt_c13_intr_we; - logic [30:0] completion_interrupt_c13_preserve_mask_qs; - logic [30:0] completion_interrupt_c13_preserve_mask_wd; - logic completion_interrupt_c13_preserve_mask_we; - logic [31:0] reserved_1_c14_qs; - logic [31:0] reserved_1_c14_wd; - logic reserved_1_c14_we; - logic channel_status_c14_channel_free_qs; - logic channel_status_c14_channel_free_wd; - logic channel_status_c14_channel_free_we; - logic channel_status_c14_channel_error_qs; - logic channel_status_c14_channel_error_wd; - logic channel_status_c14_channel_error_we; - logic [29:0] channel_status_c14_field1_qs; - logic [29:0] channel_status_c14_field1_wd; - logic channel_status_c14_field1_we; - logic [31:0] reserved_2_c14_qs; - logic [31:0] reserved_2_c14_wd; - logic reserved_2_c14_we; - logic channel_flags_c14_intr_enable_qs; - logic channel_flags_c14_intr_enable_wd; - logic channel_flags_c14_intr_enable_we; - logic [30:0] channel_flags_c14_field1_qs; - logic [30:0] channel_flags_c14_field1_wd; - logic channel_flags_c14_field1_we; - logic [31:0] length_c14_qs; - logic [31:0] length_c14_wd; - logic length_c14_we; - logic [7:0] message_header_c14_message_id_qs; - logic [7:0] message_header_c14_message_id_wd; - logic message_header_c14_message_id_we; - logic [1:0] message_header_c14_message_type_qs; - logic [1:0] message_header_c14_message_type_wd; - logic message_header_c14_message_type_we; - logic [7:0] message_header_c14_protocol_id_qs; - logic [7:0] message_header_c14_protocol_id_wd; - logic message_header_c14_protocol_id_we; - logic [9:0] message_header_c14_token_qs; - logic [9:0] message_header_c14_token_wd; - logic message_header_c14_token_we; - logic [3:0] message_header_c14_field1_qs; - logic [3:0] message_header_c14_field1_wd; - logic message_header_c14_field1_we; - logic [31:0] message_payload_1_c14_qs; - logic [31:0] message_payload_1_c14_wd; - logic message_payload_1_c14_we; - logic doorbell_c14_intr_qs; - logic doorbell_c14_intr_wd; - logic doorbell_c14_intr_we; - logic [30:0] doorbell_c14_preserve_mask_qs; - logic [30:0] doorbell_c14_preserve_mask_wd; - logic doorbell_c14_preserve_mask_we; - logic completion_interrupt_c14_intr_qs; - logic completion_interrupt_c14_intr_wd; - logic completion_interrupt_c14_intr_we; - logic [30:0] completion_interrupt_c14_preserve_mask_qs; - logic [30:0] completion_interrupt_c14_preserve_mask_wd; - logic completion_interrupt_c14_preserve_mask_we; - logic [31:0] reserved_1_c15_qs; - logic [31:0] reserved_1_c15_wd; - logic reserved_1_c15_we; - logic channel_status_c15_channel_free_qs; - logic channel_status_c15_channel_free_wd; - logic channel_status_c15_channel_free_we; - logic channel_status_c15_channel_error_qs; - logic channel_status_c15_channel_error_wd; - logic channel_status_c15_channel_error_we; - logic [29:0] channel_status_c15_field1_qs; - logic [29:0] channel_status_c15_field1_wd; - logic channel_status_c15_field1_we; - logic [31:0] reserved_2_c15_qs; - logic [31:0] reserved_2_c15_wd; - logic reserved_2_c15_we; - logic channel_flags_c15_intr_enable_qs; - logic channel_flags_c15_intr_enable_wd; - logic channel_flags_c15_intr_enable_we; - logic [30:0] channel_flags_c15_field1_qs; - logic [30:0] channel_flags_c15_field1_wd; - logic channel_flags_c15_field1_we; - logic [31:0] length_c15_qs; - logic [31:0] length_c15_wd; - logic length_c15_we; - logic [7:0] message_header_c15_message_id_qs; - logic [7:0] message_header_c15_message_id_wd; - logic message_header_c15_message_id_we; - logic [1:0] message_header_c15_message_type_qs; - logic [1:0] message_header_c15_message_type_wd; - logic message_header_c15_message_type_we; - logic [7:0] message_header_c15_protocol_id_qs; - logic [7:0] message_header_c15_protocol_id_wd; - logic message_header_c15_protocol_id_we; - logic [9:0] message_header_c15_token_qs; - logic [9:0] message_header_c15_token_wd; - logic message_header_c15_token_we; - logic [3:0] message_header_c15_field1_qs; - logic [3:0] message_header_c15_field1_wd; - logic message_header_c15_field1_we; - logic [31:0] message_payload_1_c15_qs; - logic [31:0] message_payload_1_c15_wd; - logic message_payload_1_c15_we; - logic doorbell_c15_intr_qs; - logic doorbell_c15_intr_wd; - logic doorbell_c15_intr_we; - logic [30:0] doorbell_c15_preserve_mask_qs; - logic [30:0] doorbell_c15_preserve_mask_wd; - logic doorbell_c15_preserve_mask_we; - logic completion_interrupt_c15_intr_qs; - logic completion_interrupt_c15_intr_wd; - logic completion_interrupt_c15_intr_we; - logic [30:0] completion_interrupt_c15_preserve_mask_qs; - logic [30:0] completion_interrupt_c15_preserve_mask_wd; - logic completion_interrupt_c15_preserve_mask_we; - logic [31:0] reserved_1_c16_qs; - logic [31:0] reserved_1_c16_wd; - logic reserved_1_c16_we; - logic channel_status_c16_channel_free_qs; - logic channel_status_c16_channel_free_wd; - logic channel_status_c16_channel_free_we; - logic channel_status_c16_channel_error_qs; - logic channel_status_c16_channel_error_wd; - logic channel_status_c16_channel_error_we; - logic [29:0] channel_status_c16_field1_qs; - logic [29:0] channel_status_c16_field1_wd; - logic channel_status_c16_field1_we; - logic [31:0] reserved_2_c16_qs; - logic [31:0] reserved_2_c16_wd; - logic reserved_2_c16_we; - logic channel_flags_c16_intr_enable_qs; - logic channel_flags_c16_intr_enable_wd; - logic channel_flags_c16_intr_enable_we; - logic [30:0] channel_flags_c16_field1_qs; - logic [30:0] channel_flags_c16_field1_wd; - logic channel_flags_c16_field1_we; - logic [31:0] length_c16_qs; - logic [31:0] length_c16_wd; - logic length_c16_we; - logic [7:0] message_header_c16_message_id_qs; - logic [7:0] message_header_c16_message_id_wd; - logic message_header_c16_message_id_we; - logic [1:0] message_header_c16_message_type_qs; - logic [1:0] message_header_c16_message_type_wd; - logic message_header_c16_message_type_we; - logic [7:0] message_header_c16_protocol_id_qs; - logic [7:0] message_header_c16_protocol_id_wd; - logic message_header_c16_protocol_id_we; - logic [9:0] message_header_c16_token_qs; - logic [9:0] message_header_c16_token_wd; - logic message_header_c16_token_we; - logic [3:0] message_header_c16_field1_qs; - logic [3:0] message_header_c16_field1_wd; - logic message_header_c16_field1_we; - logic [31:0] message_payload_1_c16_qs; - logic [31:0] message_payload_1_c16_wd; - logic message_payload_1_c16_we; - logic doorbell_c16_intr_qs; - logic doorbell_c16_intr_wd; - logic doorbell_c16_intr_we; - logic [30:0] doorbell_c16_preserve_mask_qs; - logic [30:0] doorbell_c16_preserve_mask_wd; - logic doorbell_c16_preserve_mask_we; - logic completion_interrupt_c16_intr_qs; - logic completion_interrupt_c16_intr_wd; - logic completion_interrupt_c16_intr_we; - logic [30:0] completion_interrupt_c16_preserve_mask_qs; - logic [30:0] completion_interrupt_c16_preserve_mask_wd; - logic completion_interrupt_c16_preserve_mask_we; - logic [31:0] reserved_1_c17_qs; - logic [31:0] reserved_1_c17_wd; - logic reserved_1_c17_we; - logic channel_status_c17_channel_free_qs; - logic channel_status_c17_channel_free_wd; - logic channel_status_c17_channel_free_we; - logic channel_status_c17_channel_error_qs; - logic channel_status_c17_channel_error_wd; - logic channel_status_c17_channel_error_we; - logic [29:0] channel_status_c17_field1_qs; - logic [29:0] channel_status_c17_field1_wd; - logic channel_status_c17_field1_we; - logic [31:0] reserved_2_c17_qs; - logic [31:0] reserved_2_c17_wd; - logic reserved_2_c17_we; - logic channel_flags_c17_intr_enable_qs; - logic channel_flags_c17_intr_enable_wd; - logic channel_flags_c17_intr_enable_we; - logic [30:0] channel_flags_c17_field1_qs; - logic [30:0] channel_flags_c17_field1_wd; - logic channel_flags_c17_field1_we; - logic [31:0] length_c17_qs; - logic [31:0] length_c17_wd; - logic length_c17_we; - logic [7:0] message_header_c17_message_id_qs; - logic [7:0] message_header_c17_message_id_wd; - logic message_header_c17_message_id_we; - logic [1:0] message_header_c17_message_type_qs; - logic [1:0] message_header_c17_message_type_wd; - logic message_header_c17_message_type_we; - logic [7:0] message_header_c17_protocol_id_qs; - logic [7:0] message_header_c17_protocol_id_wd; - logic message_header_c17_protocol_id_we; - logic [9:0] message_header_c17_token_qs; - logic [9:0] message_header_c17_token_wd; - logic message_header_c17_token_we; - logic [3:0] message_header_c17_field1_qs; - logic [3:0] message_header_c17_field1_wd; - logic message_header_c17_field1_we; - logic [31:0] message_payload_1_c17_qs; - logic [31:0] message_payload_1_c17_wd; - logic message_payload_1_c17_we; - logic doorbell_c17_intr_qs; - logic doorbell_c17_intr_wd; - logic doorbell_c17_intr_we; - logic [30:0] doorbell_c17_preserve_mask_qs; - logic [30:0] doorbell_c17_preserve_mask_wd; - logic doorbell_c17_preserve_mask_we; - logic completion_interrupt_c17_intr_qs; - logic completion_interrupt_c17_intr_wd; - logic completion_interrupt_c17_intr_we; - logic [30:0] completion_interrupt_c17_preserve_mask_qs; - logic [30:0] completion_interrupt_c17_preserve_mask_wd; - logic completion_interrupt_c17_preserve_mask_we; - logic [31:0] reserved_1_c18_qs; - logic [31:0] reserved_1_c18_wd; - logic reserved_1_c18_we; - logic channel_status_c18_channel_free_qs; - logic channel_status_c18_channel_free_wd; - logic channel_status_c18_channel_free_we; - logic channel_status_c18_channel_error_qs; - logic channel_status_c18_channel_error_wd; - logic channel_status_c18_channel_error_we; - logic [29:0] channel_status_c18_field1_qs; - logic [29:0] channel_status_c18_field1_wd; - logic channel_status_c18_field1_we; - logic [31:0] reserved_2_c18_qs; - logic [31:0] reserved_2_c18_wd; - logic reserved_2_c18_we; - logic channel_flags_c18_intr_enable_qs; - logic channel_flags_c18_intr_enable_wd; - logic channel_flags_c18_intr_enable_we; - logic [30:0] channel_flags_c18_field1_qs; - logic [30:0] channel_flags_c18_field1_wd; - logic channel_flags_c18_field1_we; - logic [31:0] length_c18_qs; - logic [31:0] length_c18_wd; - logic length_c18_we; - logic [7:0] message_header_c18_message_id_qs; - logic [7:0] message_header_c18_message_id_wd; - logic message_header_c18_message_id_we; - logic [1:0] message_header_c18_message_type_qs; - logic [1:0] message_header_c18_message_type_wd; - logic message_header_c18_message_type_we; - logic [7:0] message_header_c18_protocol_id_qs; - logic [7:0] message_header_c18_protocol_id_wd; - logic message_header_c18_protocol_id_we; - logic [9:0] message_header_c18_token_qs; - logic [9:0] message_header_c18_token_wd; - logic message_header_c18_token_we; - logic [3:0] message_header_c18_field1_qs; - logic [3:0] message_header_c18_field1_wd; - logic message_header_c18_field1_we; - logic [31:0] message_payload_1_c18_qs; - logic [31:0] message_payload_1_c18_wd; - logic message_payload_1_c18_we; - logic doorbell_c18_intr_qs; - logic doorbell_c18_intr_wd; - logic doorbell_c18_intr_we; - logic [30:0] doorbell_c18_preserve_mask_qs; - logic [30:0] doorbell_c18_preserve_mask_wd; - logic doorbell_c18_preserve_mask_we; - logic completion_interrupt_c18_intr_qs; - logic completion_interrupt_c18_intr_wd; - logic completion_interrupt_c18_intr_we; - logic [30:0] completion_interrupt_c18_preserve_mask_qs; - logic [30:0] completion_interrupt_c18_preserve_mask_wd; - logic completion_interrupt_c18_preserve_mask_we; - logic [31:0] reserved_1_c19_qs; - logic [31:0] reserved_1_c19_wd; - logic reserved_1_c19_we; - logic channel_status_c19_channel_free_qs; - logic channel_status_c19_channel_free_wd; - logic channel_status_c19_channel_free_we; - logic channel_status_c19_channel_error_qs; - logic channel_status_c19_channel_error_wd; - logic channel_status_c19_channel_error_we; - logic [29:0] channel_status_c19_field1_qs; - logic [29:0] channel_status_c19_field1_wd; - logic channel_status_c19_field1_we; - logic [31:0] reserved_2_c19_qs; - logic [31:0] reserved_2_c19_wd; - logic reserved_2_c19_we; - logic channel_flags_c19_intr_enable_qs; - logic channel_flags_c19_intr_enable_wd; - logic channel_flags_c19_intr_enable_we; - logic [30:0] channel_flags_c19_field1_qs; - logic [30:0] channel_flags_c19_field1_wd; - logic channel_flags_c19_field1_we; - logic [31:0] length_c19_qs; - logic [31:0] length_c19_wd; - logic length_c19_we; - logic [7:0] message_header_c19_message_id_qs; - logic [7:0] message_header_c19_message_id_wd; - logic message_header_c19_message_id_we; - logic [1:0] message_header_c19_message_type_qs; - logic [1:0] message_header_c19_message_type_wd; - logic message_header_c19_message_type_we; - logic [7:0] message_header_c19_protocol_id_qs; - logic [7:0] message_header_c19_protocol_id_wd; - logic message_header_c19_protocol_id_we; - logic [9:0] message_header_c19_token_qs; - logic [9:0] message_header_c19_token_wd; - logic message_header_c19_token_we; - logic [3:0] message_header_c19_field1_qs; - logic [3:0] message_header_c19_field1_wd; - logic message_header_c19_field1_we; - logic [31:0] message_payload_1_c19_qs; - logic [31:0] message_payload_1_c19_wd; - logic message_payload_1_c19_we; - logic doorbell_c19_intr_qs; - logic doorbell_c19_intr_wd; - logic doorbell_c19_intr_we; - logic [30:0] doorbell_c19_preserve_mask_qs; - logic [30:0] doorbell_c19_preserve_mask_wd; - logic doorbell_c19_preserve_mask_we; - logic completion_interrupt_c19_intr_qs; - logic completion_interrupt_c19_intr_wd; - logic completion_interrupt_c19_intr_we; - logic [30:0] completion_interrupt_c19_preserve_mask_qs; - logic [30:0] completion_interrupt_c19_preserve_mask_wd; - logic completion_interrupt_c19_preserve_mask_we; - logic [31:0] reserved_1_c20_qs; - logic [31:0] reserved_1_c20_wd; - logic reserved_1_c20_we; - logic channel_status_c20_channel_free_qs; - logic channel_status_c20_channel_free_wd; - logic channel_status_c20_channel_free_we; - logic channel_status_c20_channel_error_qs; - logic channel_status_c20_channel_error_wd; - logic channel_status_c20_channel_error_we; - logic [29:0] channel_status_c20_field1_qs; - logic [29:0] channel_status_c20_field1_wd; - logic channel_status_c20_field1_we; - logic [31:0] reserved_2_c20_qs; - logic [31:0] reserved_2_c20_wd; - logic reserved_2_c20_we; - logic channel_flags_c20_intr_enable_qs; - logic channel_flags_c20_intr_enable_wd; - logic channel_flags_c20_intr_enable_we; - logic [30:0] channel_flags_c20_field1_qs; - logic [30:0] channel_flags_c20_field1_wd; - logic channel_flags_c20_field1_we; - logic [31:0] length_c20_qs; - logic [31:0] length_c20_wd; - logic length_c20_we; - logic [7:0] message_header_c20_message_id_qs; - logic [7:0] message_header_c20_message_id_wd; - logic message_header_c20_message_id_we; - logic [1:0] message_header_c20_message_type_qs; - logic [1:0] message_header_c20_message_type_wd; - logic message_header_c20_message_type_we; - logic [7:0] message_header_c20_protocol_id_qs; - logic [7:0] message_header_c20_protocol_id_wd; - logic message_header_c20_protocol_id_we; - logic [9:0] message_header_c20_token_qs; - logic [9:0] message_header_c20_token_wd; - logic message_header_c20_token_we; - logic [3:0] message_header_c20_field1_qs; - logic [3:0] message_header_c20_field1_wd; - logic message_header_c20_field1_we; - logic [31:0] message_payload_1_c20_qs; - logic [31:0] message_payload_1_c20_wd; - logic message_payload_1_c20_we; - logic doorbell_c20_intr_qs; - logic doorbell_c20_intr_wd; - logic doorbell_c20_intr_we; - logic [30:0] doorbell_c20_preserve_mask_qs; - logic [30:0] doorbell_c20_preserve_mask_wd; - logic doorbell_c20_preserve_mask_we; - logic completion_interrupt_c20_intr_qs; - logic completion_interrupt_c20_intr_wd; - logic completion_interrupt_c20_intr_we; - logic [30:0] completion_interrupt_c20_preserve_mask_qs; - logic [30:0] completion_interrupt_c20_preserve_mask_wd; - logic completion_interrupt_c20_preserve_mask_we; - logic [31:0] reserved_1_c21_qs; - logic [31:0] reserved_1_c21_wd; - logic reserved_1_c21_we; - logic channel_status_c21_channel_free_qs; - logic channel_status_c21_channel_free_wd; - logic channel_status_c21_channel_free_we; - logic channel_status_c21_channel_error_qs; - logic channel_status_c21_channel_error_wd; - logic channel_status_c21_channel_error_we; - logic [29:0] channel_status_c21_field1_qs; - logic [29:0] channel_status_c21_field1_wd; - logic channel_status_c21_field1_we; - logic [31:0] reserved_2_c21_qs; - logic [31:0] reserved_2_c21_wd; - logic reserved_2_c21_we; - logic channel_flags_c21_intr_enable_qs; - logic channel_flags_c21_intr_enable_wd; - logic channel_flags_c21_intr_enable_we; - logic [30:0] channel_flags_c21_field1_qs; - logic [30:0] channel_flags_c21_field1_wd; - logic channel_flags_c21_field1_we; - logic [31:0] length_c21_qs; - logic [31:0] length_c21_wd; - logic length_c21_we; - logic [7:0] message_header_c21_message_id_qs; - logic [7:0] message_header_c21_message_id_wd; - logic message_header_c21_message_id_we; - logic [1:0] message_header_c21_message_type_qs; - logic [1:0] message_header_c21_message_type_wd; - logic message_header_c21_message_type_we; - logic [7:0] message_header_c21_protocol_id_qs; - logic [7:0] message_header_c21_protocol_id_wd; - logic message_header_c21_protocol_id_we; - logic [9:0] message_header_c21_token_qs; - logic [9:0] message_header_c21_token_wd; - logic message_header_c21_token_we; - logic [3:0] message_header_c21_field1_qs; - logic [3:0] message_header_c21_field1_wd; - logic message_header_c21_field1_we; - logic [31:0] message_payload_1_c21_qs; - logic [31:0] message_payload_1_c21_wd; - logic message_payload_1_c21_we; - logic doorbell_c21_intr_qs; - logic doorbell_c21_intr_wd; - logic doorbell_c21_intr_we; - logic [30:0] doorbell_c21_preserve_mask_qs; - logic [30:0] doorbell_c21_preserve_mask_wd; - logic doorbell_c21_preserve_mask_we; - logic completion_interrupt_c21_intr_qs; - logic completion_interrupt_c21_intr_wd; - logic completion_interrupt_c21_intr_we; - logic [30:0] completion_interrupt_c21_preserve_mask_qs; - logic [30:0] completion_interrupt_c21_preserve_mask_wd; - logic completion_interrupt_c21_preserve_mask_we; - logic [31:0] reserved_1_c22_qs; - logic [31:0] reserved_1_c22_wd; - logic reserved_1_c22_we; - logic channel_status_c22_channel_free_qs; - logic channel_status_c22_channel_free_wd; - logic channel_status_c22_channel_free_we; - logic channel_status_c22_channel_error_qs; - logic channel_status_c22_channel_error_wd; - logic channel_status_c22_channel_error_we; - logic [29:0] channel_status_c22_field1_qs; - logic [29:0] channel_status_c22_field1_wd; - logic channel_status_c22_field1_we; - logic [31:0] reserved_2_c22_qs; - logic [31:0] reserved_2_c22_wd; - logic reserved_2_c22_we; - logic channel_flags_c22_intr_enable_qs; - logic channel_flags_c22_intr_enable_wd; - logic channel_flags_c22_intr_enable_we; - logic [30:0] channel_flags_c22_field1_qs; - logic [30:0] channel_flags_c22_field1_wd; - logic channel_flags_c22_field1_we; - logic [31:0] length_c22_qs; - logic [31:0] length_c22_wd; - logic length_c22_we; - logic [7:0] message_header_c22_message_id_qs; - logic [7:0] message_header_c22_message_id_wd; - logic message_header_c22_message_id_we; - logic [1:0] message_header_c22_message_type_qs; - logic [1:0] message_header_c22_message_type_wd; - logic message_header_c22_message_type_we; - logic [7:0] message_header_c22_protocol_id_qs; - logic [7:0] message_header_c22_protocol_id_wd; - logic message_header_c22_protocol_id_we; - logic [9:0] message_header_c22_token_qs; - logic [9:0] message_header_c22_token_wd; - logic message_header_c22_token_we; - logic [3:0] message_header_c22_field1_qs; - logic [3:0] message_header_c22_field1_wd; - logic message_header_c22_field1_we; - logic [31:0] message_payload_1_c22_qs; - logic [31:0] message_payload_1_c22_wd; - logic message_payload_1_c22_we; - logic doorbell_c22_intr_qs; - logic doorbell_c22_intr_wd; - logic doorbell_c22_intr_we; - logic [30:0] doorbell_c22_preserve_mask_qs; - logic [30:0] doorbell_c22_preserve_mask_wd; - logic doorbell_c22_preserve_mask_we; - logic completion_interrupt_c22_intr_qs; - logic completion_interrupt_c22_intr_wd; - logic completion_interrupt_c22_intr_we; - logic [30:0] completion_interrupt_c22_preserve_mask_qs; - logic [30:0] completion_interrupt_c22_preserve_mask_wd; - logic completion_interrupt_c22_preserve_mask_we; - logic [31:0] reserved_1_c23_qs; - logic [31:0] reserved_1_c23_wd; - logic reserved_1_c23_we; - logic channel_status_c23_channel_free_qs; - logic channel_status_c23_channel_free_wd; - logic channel_status_c23_channel_free_we; - logic channel_status_c23_channel_error_qs; - logic channel_status_c23_channel_error_wd; - logic channel_status_c23_channel_error_we; - logic [29:0] channel_status_c23_field1_qs; - logic [29:0] channel_status_c23_field1_wd; - logic channel_status_c23_field1_we; - logic [31:0] reserved_2_c23_qs; - logic [31:0] reserved_2_c23_wd; - logic reserved_2_c23_we; - logic channel_flags_c23_intr_enable_qs; - logic channel_flags_c23_intr_enable_wd; - logic channel_flags_c23_intr_enable_we; - logic [30:0] channel_flags_c23_field1_qs; - logic [30:0] channel_flags_c23_field1_wd; - logic channel_flags_c23_field1_we; - logic [31:0] length_c23_qs; - logic [31:0] length_c23_wd; - logic length_c23_we; - logic [7:0] message_header_c23_message_id_qs; - logic [7:0] message_header_c23_message_id_wd; - logic message_header_c23_message_id_we; - logic [1:0] message_header_c23_message_type_qs; - logic [1:0] message_header_c23_message_type_wd; - logic message_header_c23_message_type_we; - logic [7:0] message_header_c23_protocol_id_qs; - logic [7:0] message_header_c23_protocol_id_wd; - logic message_header_c23_protocol_id_we; - logic [9:0] message_header_c23_token_qs; - logic [9:0] message_header_c23_token_wd; - logic message_header_c23_token_we; - logic [3:0] message_header_c23_field1_qs; - logic [3:0] message_header_c23_field1_wd; - logic message_header_c23_field1_we; - logic [31:0] message_payload_1_c23_qs; - logic [31:0] message_payload_1_c23_wd; - logic message_payload_1_c23_we; - logic doorbell_c23_intr_qs; - logic doorbell_c23_intr_wd; - logic doorbell_c23_intr_we; - logic [30:0] doorbell_c23_preserve_mask_qs; - logic [30:0] doorbell_c23_preserve_mask_wd; - logic doorbell_c23_preserve_mask_we; - logic completion_interrupt_c23_intr_qs; - logic completion_interrupt_c23_intr_wd; - logic completion_interrupt_c23_intr_we; - logic [30:0] completion_interrupt_c23_preserve_mask_qs; - logic [30:0] completion_interrupt_c23_preserve_mask_wd; - logic completion_interrupt_c23_preserve_mask_we; - logic [31:0] reserved_1_c24_qs; - logic [31:0] reserved_1_c24_wd; - logic reserved_1_c24_we; - logic channel_status_c24_channel_free_qs; - logic channel_status_c24_channel_free_wd; - logic channel_status_c24_channel_free_we; - logic channel_status_c24_channel_error_qs; - logic channel_status_c24_channel_error_wd; - logic channel_status_c24_channel_error_we; - logic [29:0] channel_status_c24_field1_qs; - logic [29:0] channel_status_c24_field1_wd; - logic channel_status_c24_field1_we; - logic [31:0] reserved_2_c24_qs; - logic [31:0] reserved_2_c24_wd; - logic reserved_2_c24_we; - logic channel_flags_c24_intr_enable_qs; - logic channel_flags_c24_intr_enable_wd; - logic channel_flags_c24_intr_enable_we; - logic [30:0] channel_flags_c24_field1_qs; - logic [30:0] channel_flags_c24_field1_wd; - logic channel_flags_c24_field1_we; - logic [31:0] length_c24_qs; - logic [31:0] length_c24_wd; - logic length_c24_we; - logic [7:0] message_header_c24_message_id_qs; - logic [7:0] message_header_c24_message_id_wd; - logic message_header_c24_message_id_we; - logic [1:0] message_header_c24_message_type_qs; - logic [1:0] message_header_c24_message_type_wd; - logic message_header_c24_message_type_we; - logic [7:0] message_header_c24_protocol_id_qs; - logic [7:0] message_header_c24_protocol_id_wd; - logic message_header_c24_protocol_id_we; - logic [9:0] message_header_c24_token_qs; - logic [9:0] message_header_c24_token_wd; - logic message_header_c24_token_we; - logic [3:0] message_header_c24_field1_qs; - logic [3:0] message_header_c24_field1_wd; - logic message_header_c24_field1_we; - logic [31:0] message_payload_1_c24_qs; - logic [31:0] message_payload_1_c24_wd; - logic message_payload_1_c24_we; - logic doorbell_c24_intr_qs; - logic doorbell_c24_intr_wd; - logic doorbell_c24_intr_we; - logic [30:0] doorbell_c24_preserve_mask_qs; - logic [30:0] doorbell_c24_preserve_mask_wd; - logic doorbell_c24_preserve_mask_we; - logic completion_interrupt_c24_intr_qs; - logic completion_interrupt_c24_intr_wd; - logic completion_interrupt_c24_intr_we; - logic [30:0] completion_interrupt_c24_preserve_mask_qs; - logic [30:0] completion_interrupt_c24_preserve_mask_wd; - logic completion_interrupt_c24_preserve_mask_we; - logic [31:0] reserved_1_c25_qs; - logic [31:0] reserved_1_c25_wd; - logic reserved_1_c25_we; - logic channel_status_c25_channel_free_qs; - logic channel_status_c25_channel_free_wd; - logic channel_status_c25_channel_free_we; - logic channel_status_c25_channel_error_qs; - logic channel_status_c25_channel_error_wd; - logic channel_status_c25_channel_error_we; - logic [29:0] channel_status_c25_field1_qs; - logic [29:0] channel_status_c25_field1_wd; - logic channel_status_c25_field1_we; - logic [31:0] reserved_2_c25_qs; - logic [31:0] reserved_2_c25_wd; - logic reserved_2_c25_we; - logic channel_flags_c25_intr_enable_qs; - logic channel_flags_c25_intr_enable_wd; - logic channel_flags_c25_intr_enable_we; - logic [30:0] channel_flags_c25_field1_qs; - logic [30:0] channel_flags_c25_field1_wd; - logic channel_flags_c25_field1_we; - logic [31:0] length_c25_qs; - logic [31:0] length_c25_wd; - logic length_c25_we; - logic [7:0] message_header_c25_message_id_qs; - logic [7:0] message_header_c25_message_id_wd; - logic message_header_c25_message_id_we; - logic [1:0] message_header_c25_message_type_qs; - logic [1:0] message_header_c25_message_type_wd; - logic message_header_c25_message_type_we; - logic [7:0] message_header_c25_protocol_id_qs; - logic [7:0] message_header_c25_protocol_id_wd; - logic message_header_c25_protocol_id_we; - logic [9:0] message_header_c25_token_qs; - logic [9:0] message_header_c25_token_wd; - logic message_header_c25_token_we; - logic [3:0] message_header_c25_field1_qs; - logic [3:0] message_header_c25_field1_wd; - logic message_header_c25_field1_we; - logic [31:0] message_payload_1_c25_qs; - logic [31:0] message_payload_1_c25_wd; - logic message_payload_1_c25_we; - logic doorbell_c25_intr_qs; - logic doorbell_c25_intr_wd; - logic doorbell_c25_intr_we; - logic [30:0] doorbell_c25_preserve_mask_qs; - logic [30:0] doorbell_c25_preserve_mask_wd; - logic doorbell_c25_preserve_mask_we; - logic completion_interrupt_c25_intr_qs; - logic completion_interrupt_c25_intr_wd; - logic completion_interrupt_c25_intr_we; - logic [30:0] completion_interrupt_c25_preserve_mask_qs; - logic [30:0] completion_interrupt_c25_preserve_mask_wd; - logic completion_interrupt_c25_preserve_mask_we; - logic [31:0] reserved_1_c26_qs; - logic [31:0] reserved_1_c26_wd; - logic reserved_1_c26_we; - logic channel_status_c26_channel_free_qs; - logic channel_status_c26_channel_free_wd; - logic channel_status_c26_channel_free_we; - logic channel_status_c26_channel_error_qs; - logic channel_status_c26_channel_error_wd; - logic channel_status_c26_channel_error_we; - logic [29:0] channel_status_c26_field1_qs; - logic [29:0] channel_status_c26_field1_wd; - logic channel_status_c26_field1_we; - logic [31:0] reserved_2_c26_qs; - logic [31:0] reserved_2_c26_wd; - logic reserved_2_c26_we; - logic channel_flags_c26_intr_enable_qs; - logic channel_flags_c26_intr_enable_wd; - logic channel_flags_c26_intr_enable_we; - logic [30:0] channel_flags_c26_field1_qs; - logic [30:0] channel_flags_c26_field1_wd; - logic channel_flags_c26_field1_we; - logic [31:0] length_c26_qs; - logic [31:0] length_c26_wd; - logic length_c26_we; - logic [7:0] message_header_c26_message_id_qs; - logic [7:0] message_header_c26_message_id_wd; - logic message_header_c26_message_id_we; - logic [1:0] message_header_c26_message_type_qs; - logic [1:0] message_header_c26_message_type_wd; - logic message_header_c26_message_type_we; - logic [7:0] message_header_c26_protocol_id_qs; - logic [7:0] message_header_c26_protocol_id_wd; - logic message_header_c26_protocol_id_we; - logic [9:0] message_header_c26_token_qs; - logic [9:0] message_header_c26_token_wd; - logic message_header_c26_token_we; - logic [3:0] message_header_c26_field1_qs; - logic [3:0] message_header_c26_field1_wd; - logic message_header_c26_field1_we; - logic [31:0] message_payload_1_c26_qs; - logic [31:0] message_payload_1_c26_wd; - logic message_payload_1_c26_we; - logic doorbell_c26_intr_qs; - logic doorbell_c26_intr_wd; - logic doorbell_c26_intr_we; - logic [30:0] doorbell_c26_preserve_mask_qs; - logic [30:0] doorbell_c26_preserve_mask_wd; - logic doorbell_c26_preserve_mask_we; - logic completion_interrupt_c26_intr_qs; - logic completion_interrupt_c26_intr_wd; - logic completion_interrupt_c26_intr_we; - logic [30:0] completion_interrupt_c26_preserve_mask_qs; - logic [30:0] completion_interrupt_c26_preserve_mask_wd; - logic completion_interrupt_c26_preserve_mask_we; - logic [31:0] reserved_1_c27_qs; - logic [31:0] reserved_1_c27_wd; - logic reserved_1_c27_we; - logic channel_status_c27_channel_free_qs; - logic channel_status_c27_channel_free_wd; - logic channel_status_c27_channel_free_we; - logic channel_status_c27_channel_error_qs; - logic channel_status_c27_channel_error_wd; - logic channel_status_c27_channel_error_we; - logic [29:0] channel_status_c27_field1_qs; - logic [29:0] channel_status_c27_field1_wd; - logic channel_status_c27_field1_we; - logic [31:0] reserved_2_c27_qs; - logic [31:0] reserved_2_c27_wd; - logic reserved_2_c27_we; - logic channel_flags_c27_intr_enable_qs; - logic channel_flags_c27_intr_enable_wd; - logic channel_flags_c27_intr_enable_we; - logic [30:0] channel_flags_c27_field1_qs; - logic [30:0] channel_flags_c27_field1_wd; - logic channel_flags_c27_field1_we; - logic [31:0] length_c27_qs; - logic [31:0] length_c27_wd; - logic length_c27_we; - logic [7:0] message_header_c27_message_id_qs; - logic [7:0] message_header_c27_message_id_wd; - logic message_header_c27_message_id_we; - logic [1:0] message_header_c27_message_type_qs; - logic [1:0] message_header_c27_message_type_wd; - logic message_header_c27_message_type_we; - logic [7:0] message_header_c27_protocol_id_qs; - logic [7:0] message_header_c27_protocol_id_wd; - logic message_header_c27_protocol_id_we; - logic [9:0] message_header_c27_token_qs; - logic [9:0] message_header_c27_token_wd; - logic message_header_c27_token_we; - logic [3:0] message_header_c27_field1_qs; - logic [3:0] message_header_c27_field1_wd; - logic message_header_c27_field1_we; - logic [31:0] message_payload_1_c27_qs; - logic [31:0] message_payload_1_c27_wd; - logic message_payload_1_c27_we; - logic doorbell_c27_intr_qs; - logic doorbell_c27_intr_wd; - logic doorbell_c27_intr_we; - logic [30:0] doorbell_c27_preserve_mask_qs; - logic [30:0] doorbell_c27_preserve_mask_wd; - logic doorbell_c27_preserve_mask_we; - logic completion_interrupt_c27_intr_qs; - logic completion_interrupt_c27_intr_wd; - logic completion_interrupt_c27_intr_we; - logic [30:0] completion_interrupt_c27_preserve_mask_qs; - logic [30:0] completion_interrupt_c27_preserve_mask_wd; - logic completion_interrupt_c27_preserve_mask_we; - logic [31:0] reserved_1_c28_qs; - logic [31:0] reserved_1_c28_wd; - logic reserved_1_c28_we; - logic channel_status_c28_channel_free_qs; - logic channel_status_c28_channel_free_wd; - logic channel_status_c28_channel_free_we; - logic channel_status_c28_channel_error_qs; - logic channel_status_c28_channel_error_wd; - logic channel_status_c28_channel_error_we; - logic [29:0] channel_status_c28_field1_qs; - logic [29:0] channel_status_c28_field1_wd; - logic channel_status_c28_field1_we; - logic [31:0] reserved_2_c28_qs; - logic [31:0] reserved_2_c28_wd; - logic reserved_2_c28_we; - logic channel_flags_c28_intr_enable_qs; - logic channel_flags_c28_intr_enable_wd; - logic channel_flags_c28_intr_enable_we; - logic [30:0] channel_flags_c28_field1_qs; - logic [30:0] channel_flags_c28_field1_wd; - logic channel_flags_c28_field1_we; - logic [31:0] length_c28_qs; - logic [31:0] length_c28_wd; - logic length_c28_we; - logic [7:0] message_header_c28_message_id_qs; - logic [7:0] message_header_c28_message_id_wd; - logic message_header_c28_message_id_we; - logic [1:0] message_header_c28_message_type_qs; - logic [1:0] message_header_c28_message_type_wd; - logic message_header_c28_message_type_we; - logic [7:0] message_header_c28_protocol_id_qs; - logic [7:0] message_header_c28_protocol_id_wd; - logic message_header_c28_protocol_id_we; - logic [9:0] message_header_c28_token_qs; - logic [9:0] message_header_c28_token_wd; - logic message_header_c28_token_we; - logic [3:0] message_header_c28_field1_qs; - logic [3:0] message_header_c28_field1_wd; - logic message_header_c28_field1_we; - logic [31:0] message_payload_1_c28_qs; - logic [31:0] message_payload_1_c28_wd; - logic message_payload_1_c28_we; - logic doorbell_c28_intr_qs; - logic doorbell_c28_intr_wd; - logic doorbell_c28_intr_we; - logic [30:0] doorbell_c28_preserve_mask_qs; - logic [30:0] doorbell_c28_preserve_mask_wd; - logic doorbell_c28_preserve_mask_we; - logic completion_interrupt_c28_intr_qs; - logic completion_interrupt_c28_intr_wd; - logic completion_interrupt_c28_intr_we; - logic [30:0] completion_interrupt_c28_preserve_mask_qs; - logic [30:0] completion_interrupt_c28_preserve_mask_wd; - logic completion_interrupt_c28_preserve_mask_we; - logic [31:0] reserved_1_c29_qs; - logic [31:0] reserved_1_c29_wd; - logic reserved_1_c29_we; - logic channel_status_c29_channel_free_qs; - logic channel_status_c29_channel_free_wd; - logic channel_status_c29_channel_free_we; - logic channel_status_c29_channel_error_qs; - logic channel_status_c29_channel_error_wd; - logic channel_status_c29_channel_error_we; - logic [29:0] channel_status_c29_field1_qs; - logic [29:0] channel_status_c29_field1_wd; - logic channel_status_c29_field1_we; - logic [31:0] reserved_2_c29_qs; - logic [31:0] reserved_2_c29_wd; - logic reserved_2_c29_we; - logic channel_flags_c29_intr_enable_qs; - logic channel_flags_c29_intr_enable_wd; - logic channel_flags_c29_intr_enable_we; - logic [30:0] channel_flags_c29_field1_qs; - logic [30:0] channel_flags_c29_field1_wd; - logic channel_flags_c29_field1_we; - logic [31:0] length_c29_qs; - logic [31:0] length_c29_wd; - logic length_c29_we; - logic [7:0] message_header_c29_message_id_qs; - logic [7:0] message_header_c29_message_id_wd; - logic message_header_c29_message_id_we; - logic [1:0] message_header_c29_message_type_qs; - logic [1:0] message_header_c29_message_type_wd; - logic message_header_c29_message_type_we; - logic [7:0] message_header_c29_protocol_id_qs; - logic [7:0] message_header_c29_protocol_id_wd; - logic message_header_c29_protocol_id_we; - logic [9:0] message_header_c29_token_qs; - logic [9:0] message_header_c29_token_wd; - logic message_header_c29_token_we; - logic [3:0] message_header_c29_field1_qs; - logic [3:0] message_header_c29_field1_wd; - logic message_header_c29_field1_we; - logic [31:0] message_payload_1_c29_qs; - logic [31:0] message_payload_1_c29_wd; - logic message_payload_1_c29_we; - logic doorbell_c29_intr_qs; - logic doorbell_c29_intr_wd; - logic doorbell_c29_intr_we; - logic [30:0] doorbell_c29_preserve_mask_qs; - logic [30:0] doorbell_c29_preserve_mask_wd; - logic doorbell_c29_preserve_mask_we; - logic completion_interrupt_c29_intr_qs; - logic completion_interrupt_c29_intr_wd; - logic completion_interrupt_c29_intr_we; - logic [30:0] completion_interrupt_c29_preserve_mask_qs; - logic [30:0] completion_interrupt_c29_preserve_mask_wd; - logic completion_interrupt_c29_preserve_mask_we; - logic [31:0] reserved_1_c30_qs; - logic [31:0] reserved_1_c30_wd; - logic reserved_1_c30_we; - logic channel_status_c30_channel_free_qs; - logic channel_status_c30_channel_free_wd; - logic channel_status_c30_channel_free_we; - logic channel_status_c30_channel_error_qs; - logic channel_status_c30_channel_error_wd; - logic channel_status_c30_channel_error_we; - logic [29:0] channel_status_c30_field1_qs; - logic [29:0] channel_status_c30_field1_wd; - logic channel_status_c30_field1_we; - logic [31:0] reserved_2_c30_qs; - logic [31:0] reserved_2_c30_wd; - logic reserved_2_c30_we; - logic channel_flags_c30_intr_enable_qs; - logic channel_flags_c30_intr_enable_wd; - logic channel_flags_c30_intr_enable_we; - logic [30:0] channel_flags_c30_field1_qs; - logic [30:0] channel_flags_c30_field1_wd; - logic channel_flags_c30_field1_we; - logic [31:0] length_c30_qs; - logic [31:0] length_c30_wd; - logic length_c30_we; - logic [7:0] message_header_c30_message_id_qs; - logic [7:0] message_header_c30_message_id_wd; - logic message_header_c30_message_id_we; - logic [1:0] message_header_c30_message_type_qs; - logic [1:0] message_header_c30_message_type_wd; - logic message_header_c30_message_type_we; - logic [7:0] message_header_c30_protocol_id_qs; - logic [7:0] message_header_c30_protocol_id_wd; - logic message_header_c30_protocol_id_we; - logic [9:0] message_header_c30_token_qs; - logic [9:0] message_header_c30_token_wd; - logic message_header_c30_token_we; - logic [3:0] message_header_c30_field1_qs; - logic [3:0] message_header_c30_field1_wd; - logic message_header_c30_field1_we; - logic [31:0] message_payload_1_c30_qs; - logic [31:0] message_payload_1_c30_wd; - logic message_payload_1_c30_we; - logic doorbell_c30_intr_qs; - logic doorbell_c30_intr_wd; - logic doorbell_c30_intr_we; - logic [30:0] doorbell_c30_preserve_mask_qs; - logic [30:0] doorbell_c30_preserve_mask_wd; - logic doorbell_c30_preserve_mask_we; - logic completion_interrupt_c30_intr_qs; - logic completion_interrupt_c30_intr_wd; - logic completion_interrupt_c30_intr_we; - logic [30:0] completion_interrupt_c30_preserve_mask_qs; - logic [30:0] completion_interrupt_c30_preserve_mask_wd; - logic completion_interrupt_c30_preserve_mask_we; - logic [31:0] reserved_1_c31_qs; - logic [31:0] reserved_1_c31_wd; - logic reserved_1_c31_we; - logic channel_status_c31_channel_free_qs; - logic channel_status_c31_channel_free_wd; - logic channel_status_c31_channel_free_we; - logic channel_status_c31_channel_error_qs; - logic channel_status_c31_channel_error_wd; - logic channel_status_c31_channel_error_we; - logic [29:0] channel_status_c31_field1_qs; - logic [29:0] channel_status_c31_field1_wd; - logic channel_status_c31_field1_we; - logic [31:0] reserved_2_c31_qs; - logic [31:0] reserved_2_c31_wd; - logic reserved_2_c31_we; - logic channel_flags_c31_intr_enable_qs; - logic channel_flags_c31_intr_enable_wd; - logic channel_flags_c31_intr_enable_we; - logic [30:0] channel_flags_c31_field1_qs; - logic [30:0] channel_flags_c31_field1_wd; - logic channel_flags_c31_field1_we; - logic [31:0] length_c31_qs; - logic [31:0] length_c31_wd; - logic length_c31_we; - logic [7:0] message_header_c31_message_id_qs; - logic [7:0] message_header_c31_message_id_wd; - logic message_header_c31_message_id_we; - logic [1:0] message_header_c31_message_type_qs; - logic [1:0] message_header_c31_message_type_wd; - logic message_header_c31_message_type_we; - logic [7:0] message_header_c31_protocol_id_qs; - logic [7:0] message_header_c31_protocol_id_wd; - logic message_header_c31_protocol_id_we; - logic [9:0] message_header_c31_token_qs; - logic [9:0] message_header_c31_token_wd; - logic message_header_c31_token_we; - logic [3:0] message_header_c31_field1_qs; - logic [3:0] message_header_c31_field1_wd; - logic message_header_c31_field1_we; - logic [31:0] message_payload_1_c31_qs; - logic [31:0] message_payload_1_c31_wd; - logic message_payload_1_c31_we; - logic doorbell_c31_intr_qs; - logic doorbell_c31_intr_wd; - logic doorbell_c31_intr_we; - logic [30:0] doorbell_c31_preserve_mask_qs; - logic [30:0] doorbell_c31_preserve_mask_wd; - logic doorbell_c31_preserve_mask_we; - logic completion_interrupt_c31_intr_qs; - logic completion_interrupt_c31_intr_wd; - logic completion_interrupt_c31_intr_we; - logic [30:0] completion_interrupt_c31_preserve_mask_qs; - logic [30:0] completion_interrupt_c31_preserve_mask_wd; - logic completion_interrupt_c31_preserve_mask_we; - logic [31:0] reserved_1_c32_qs; - logic [31:0] reserved_1_c32_wd; - logic reserved_1_c32_we; - logic channel_status_c32_channel_free_qs; - logic channel_status_c32_channel_free_wd; - logic channel_status_c32_channel_free_we; - logic channel_status_c32_channel_error_qs; - logic channel_status_c32_channel_error_wd; - logic channel_status_c32_channel_error_we; - logic [29:0] channel_status_c32_field1_qs; - logic [29:0] channel_status_c32_field1_wd; - logic channel_status_c32_field1_we; - logic [31:0] reserved_2_c32_qs; - logic [31:0] reserved_2_c32_wd; - logic reserved_2_c32_we; - logic channel_flags_c32_intr_enable_qs; - logic channel_flags_c32_intr_enable_wd; - logic channel_flags_c32_intr_enable_we; - logic [30:0] channel_flags_c32_field1_qs; - logic [30:0] channel_flags_c32_field1_wd; - logic channel_flags_c32_field1_we; - logic [31:0] length_c32_qs; - logic [31:0] length_c32_wd; - logic length_c32_we; - logic [7:0] message_header_c32_message_id_qs; - logic [7:0] message_header_c32_message_id_wd; - logic message_header_c32_message_id_we; - logic [1:0] message_header_c32_message_type_qs; - logic [1:0] message_header_c32_message_type_wd; - logic message_header_c32_message_type_we; - logic [7:0] message_header_c32_protocol_id_qs; - logic [7:0] message_header_c32_protocol_id_wd; - logic message_header_c32_protocol_id_we; - logic [9:0] message_header_c32_token_qs; - logic [9:0] message_header_c32_token_wd; - logic message_header_c32_token_we; - logic [3:0] message_header_c32_field1_qs; - logic [3:0] message_header_c32_field1_wd; - logic message_header_c32_field1_we; - logic [31:0] message_payload_1_c32_qs; - logic [31:0] message_payload_1_c32_wd; - logic message_payload_1_c32_we; - logic doorbell_c32_intr_qs; - logic doorbell_c32_intr_wd; - logic doorbell_c32_intr_we; - logic [30:0] doorbell_c32_preserve_mask_qs; - logic [30:0] doorbell_c32_preserve_mask_wd; - logic doorbell_c32_preserve_mask_we; - logic completion_interrupt_c32_intr_qs; - logic completion_interrupt_c32_intr_wd; - logic completion_interrupt_c32_intr_we; - logic [30:0] completion_interrupt_c32_preserve_mask_qs; - logic [30:0] completion_interrupt_c32_preserve_mask_wd; - logic completion_interrupt_c32_preserve_mask_we; - logic [31:0] reserved_1_c33_qs; - logic [31:0] reserved_1_c33_wd; - logic reserved_1_c33_we; - logic channel_status_c33_channel_free_qs; - logic channel_status_c33_channel_free_wd; - logic channel_status_c33_channel_free_we; - logic channel_status_c33_channel_error_qs; - logic channel_status_c33_channel_error_wd; - logic channel_status_c33_channel_error_we; - logic [29:0] channel_status_c33_field1_qs; - logic [29:0] channel_status_c33_field1_wd; - logic channel_status_c33_field1_we; - logic [31:0] reserved_2_c33_qs; - logic [31:0] reserved_2_c33_wd; - logic reserved_2_c33_we; - logic channel_flags_c33_intr_enable_qs; - logic channel_flags_c33_intr_enable_wd; - logic channel_flags_c33_intr_enable_we; - logic [30:0] channel_flags_c33_field1_qs; - logic [30:0] channel_flags_c33_field1_wd; - logic channel_flags_c33_field1_we; - logic [31:0] length_c33_qs; - logic [31:0] length_c33_wd; - logic length_c33_we; - logic [7:0] message_header_c33_message_id_qs; - logic [7:0] message_header_c33_message_id_wd; - logic message_header_c33_message_id_we; - logic [1:0] message_header_c33_message_type_qs; - logic [1:0] message_header_c33_message_type_wd; - logic message_header_c33_message_type_we; - logic [7:0] message_header_c33_protocol_id_qs; - logic [7:0] message_header_c33_protocol_id_wd; - logic message_header_c33_protocol_id_we; - logic [9:0] message_header_c33_token_qs; - logic [9:0] message_header_c33_token_wd; - logic message_header_c33_token_we; - logic [3:0] message_header_c33_field1_qs; - logic [3:0] message_header_c33_field1_wd; - logic message_header_c33_field1_we; - logic [31:0] message_payload_1_c33_qs; - logic [31:0] message_payload_1_c33_wd; - logic message_payload_1_c33_we; - logic doorbell_c33_intr_qs; - logic doorbell_c33_intr_wd; - logic doorbell_c33_intr_we; - logic [30:0] doorbell_c33_preserve_mask_qs; - logic [30:0] doorbell_c33_preserve_mask_wd; - logic doorbell_c33_preserve_mask_we; - logic completion_interrupt_c33_intr_qs; - logic completion_interrupt_c33_intr_wd; - logic completion_interrupt_c33_intr_we; - logic [30:0] completion_interrupt_c33_preserve_mask_qs; - logic [30:0] completion_interrupt_c33_preserve_mask_wd; - logic completion_interrupt_c33_preserve_mask_we; - logic [31:0] reserved_1_c34_qs; - logic [31:0] reserved_1_c34_wd; - logic reserved_1_c34_we; - logic channel_status_c34_channel_free_qs; - logic channel_status_c34_channel_free_wd; - logic channel_status_c34_channel_free_we; - logic channel_status_c34_channel_error_qs; - logic channel_status_c34_channel_error_wd; - logic channel_status_c34_channel_error_we; - logic [29:0] channel_status_c34_field1_qs; - logic [29:0] channel_status_c34_field1_wd; - logic channel_status_c34_field1_we; - logic [31:0] reserved_2_c34_qs; - logic [31:0] reserved_2_c34_wd; - logic reserved_2_c34_we; - logic channel_flags_c34_intr_enable_qs; - logic channel_flags_c34_intr_enable_wd; - logic channel_flags_c34_intr_enable_we; - logic [30:0] channel_flags_c34_field1_qs; - logic [30:0] channel_flags_c34_field1_wd; - logic channel_flags_c34_field1_we; - logic [31:0] length_c34_qs; - logic [31:0] length_c34_wd; - logic length_c34_we; - logic [7:0] message_header_c34_message_id_qs; - logic [7:0] message_header_c34_message_id_wd; - logic message_header_c34_message_id_we; - logic [1:0] message_header_c34_message_type_qs; - logic [1:0] message_header_c34_message_type_wd; - logic message_header_c34_message_type_we; - logic [7:0] message_header_c34_protocol_id_qs; - logic [7:0] message_header_c34_protocol_id_wd; - logic message_header_c34_protocol_id_we; - logic [9:0] message_header_c34_token_qs; - logic [9:0] message_header_c34_token_wd; - logic message_header_c34_token_we; - logic [3:0] message_header_c34_field1_qs; - logic [3:0] message_header_c34_field1_wd; - logic message_header_c34_field1_we; - logic [31:0] message_payload_1_c34_qs; - logic [31:0] message_payload_1_c34_wd; - logic message_payload_1_c34_we; - logic doorbell_c34_intr_qs; - logic doorbell_c34_intr_wd; - logic doorbell_c34_intr_we; - logic [30:0] doorbell_c34_preserve_mask_qs; - logic [30:0] doorbell_c34_preserve_mask_wd; - logic doorbell_c34_preserve_mask_we; - logic completion_interrupt_c34_intr_qs; - logic completion_interrupt_c34_intr_wd; - logic completion_interrupt_c34_intr_we; - logic [30:0] completion_interrupt_c34_preserve_mask_qs; - logic [30:0] completion_interrupt_c34_preserve_mask_wd; - logic completion_interrupt_c34_preserve_mask_we; - logic [31:0] reserved_1_c35_qs; - logic [31:0] reserved_1_c35_wd; - logic reserved_1_c35_we; - logic channel_status_c35_channel_free_qs; - logic channel_status_c35_channel_free_wd; - logic channel_status_c35_channel_free_we; - logic channel_status_c35_channel_error_qs; - logic channel_status_c35_channel_error_wd; - logic channel_status_c35_channel_error_we; - logic [29:0] channel_status_c35_field1_qs; - logic [29:0] channel_status_c35_field1_wd; - logic channel_status_c35_field1_we; - logic [31:0] reserved_2_c35_qs; - logic [31:0] reserved_2_c35_wd; - logic reserved_2_c35_we; - logic channel_flags_c35_intr_enable_qs; - logic channel_flags_c35_intr_enable_wd; - logic channel_flags_c35_intr_enable_we; - logic [30:0] channel_flags_c35_field1_qs; - logic [30:0] channel_flags_c35_field1_wd; - logic channel_flags_c35_field1_we; - logic [31:0] length_c35_qs; - logic [31:0] length_c35_wd; - logic length_c35_we; - logic [7:0] message_header_c35_message_id_qs; - logic [7:0] message_header_c35_message_id_wd; - logic message_header_c35_message_id_we; - logic [1:0] message_header_c35_message_type_qs; - logic [1:0] message_header_c35_message_type_wd; - logic message_header_c35_message_type_we; - logic [7:0] message_header_c35_protocol_id_qs; - logic [7:0] message_header_c35_protocol_id_wd; - logic message_header_c35_protocol_id_we; - logic [9:0] message_header_c35_token_qs; - logic [9:0] message_header_c35_token_wd; - logic message_header_c35_token_we; - logic [3:0] message_header_c35_field1_qs; - logic [3:0] message_header_c35_field1_wd; - logic message_header_c35_field1_we; - logic [31:0] message_payload_1_c35_qs; - logic [31:0] message_payload_1_c35_wd; - logic message_payload_1_c35_we; - logic doorbell_c35_intr_qs; - logic doorbell_c35_intr_wd; - logic doorbell_c35_intr_we; - logic [30:0] doorbell_c35_preserve_mask_qs; - logic [30:0] doorbell_c35_preserve_mask_wd; - logic doorbell_c35_preserve_mask_we; - logic completion_interrupt_c35_intr_qs; - logic completion_interrupt_c35_intr_wd; - logic completion_interrupt_c35_intr_we; - logic [30:0] completion_interrupt_c35_preserve_mask_qs; - logic [30:0] completion_interrupt_c35_preserve_mask_wd; - logic completion_interrupt_c35_preserve_mask_we; - logic [31:0] reserved_1_c36_qs; - logic [31:0] reserved_1_c36_wd; - logic reserved_1_c36_we; - logic channel_status_c36_channel_free_qs; - logic channel_status_c36_channel_free_wd; - logic channel_status_c36_channel_free_we; - logic channel_status_c36_channel_error_qs; - logic channel_status_c36_channel_error_wd; - logic channel_status_c36_channel_error_we; - logic [29:0] channel_status_c36_field1_qs; - logic [29:0] channel_status_c36_field1_wd; - logic channel_status_c36_field1_we; - logic [31:0] reserved_2_c36_qs; - logic [31:0] reserved_2_c36_wd; - logic reserved_2_c36_we; - logic channel_flags_c36_intr_enable_qs; - logic channel_flags_c36_intr_enable_wd; - logic channel_flags_c36_intr_enable_we; - logic [30:0] channel_flags_c36_field1_qs; - logic [30:0] channel_flags_c36_field1_wd; - logic channel_flags_c36_field1_we; - logic [31:0] length_c36_qs; - logic [31:0] length_c36_wd; - logic length_c36_we; - logic [7:0] message_header_c36_message_id_qs; - logic [7:0] message_header_c36_message_id_wd; - logic message_header_c36_message_id_we; - logic [1:0] message_header_c36_message_type_qs; - logic [1:0] message_header_c36_message_type_wd; - logic message_header_c36_message_type_we; - logic [7:0] message_header_c36_protocol_id_qs; - logic [7:0] message_header_c36_protocol_id_wd; - logic message_header_c36_protocol_id_we; - logic [9:0] message_header_c36_token_qs; - logic [9:0] message_header_c36_token_wd; - logic message_header_c36_token_we; - logic [3:0] message_header_c36_field1_qs; - logic [3:0] message_header_c36_field1_wd; - logic message_header_c36_field1_we; - logic [31:0] message_payload_1_c36_qs; - logic [31:0] message_payload_1_c36_wd; - logic message_payload_1_c36_we; - logic doorbell_c36_intr_qs; - logic doorbell_c36_intr_wd; - logic doorbell_c36_intr_we; - logic [30:0] doorbell_c36_preserve_mask_qs; - logic [30:0] doorbell_c36_preserve_mask_wd; - logic doorbell_c36_preserve_mask_we; - logic completion_interrupt_c36_intr_qs; - logic completion_interrupt_c36_intr_wd; - logic completion_interrupt_c36_intr_we; - logic [30:0] completion_interrupt_c36_preserve_mask_qs; - logic [30:0] completion_interrupt_c36_preserve_mask_wd; - logic completion_interrupt_c36_preserve_mask_we; - logic [31:0] reserved_1_c37_qs; - logic [31:0] reserved_1_c37_wd; - logic reserved_1_c37_we; - logic channel_status_c37_channel_free_qs; - logic channel_status_c37_channel_free_wd; - logic channel_status_c37_channel_free_we; - logic channel_status_c37_channel_error_qs; - logic channel_status_c37_channel_error_wd; - logic channel_status_c37_channel_error_we; - logic [29:0] channel_status_c37_field1_qs; - logic [29:0] channel_status_c37_field1_wd; - logic channel_status_c37_field1_we; - logic [31:0] reserved_2_c37_qs; - logic [31:0] reserved_2_c37_wd; - logic reserved_2_c37_we; - logic channel_flags_c37_intr_enable_qs; - logic channel_flags_c37_intr_enable_wd; - logic channel_flags_c37_intr_enable_we; - logic [30:0] channel_flags_c37_field1_qs; - logic [30:0] channel_flags_c37_field1_wd; - logic channel_flags_c37_field1_we; - logic [31:0] length_c37_qs; - logic [31:0] length_c37_wd; - logic length_c37_we; - logic [7:0] message_header_c37_message_id_qs; - logic [7:0] message_header_c37_message_id_wd; - logic message_header_c37_message_id_we; - logic [1:0] message_header_c37_message_type_qs; - logic [1:0] message_header_c37_message_type_wd; - logic message_header_c37_message_type_we; - logic [7:0] message_header_c37_protocol_id_qs; - logic [7:0] message_header_c37_protocol_id_wd; - logic message_header_c37_protocol_id_we; - logic [9:0] message_header_c37_token_qs; - logic [9:0] message_header_c37_token_wd; - logic message_header_c37_token_we; - logic [3:0] message_header_c37_field1_qs; - logic [3:0] message_header_c37_field1_wd; - logic message_header_c37_field1_we; - logic [31:0] message_payload_1_c37_qs; - logic [31:0] message_payload_1_c37_wd; - logic message_payload_1_c37_we; - logic doorbell_c37_intr_qs; - logic doorbell_c37_intr_wd; - logic doorbell_c37_intr_we; - logic [30:0] doorbell_c37_preserve_mask_qs; - logic [30:0] doorbell_c37_preserve_mask_wd; - logic doorbell_c37_preserve_mask_we; - logic completion_interrupt_c37_intr_qs; - logic completion_interrupt_c37_intr_wd; - logic completion_interrupt_c37_intr_we; - logic [30:0] completion_interrupt_c37_preserve_mask_qs; - logic [30:0] completion_interrupt_c37_preserve_mask_wd; - logic completion_interrupt_c37_preserve_mask_we; - logic [31:0] reserved_1_c38_qs; - logic [31:0] reserved_1_c38_wd; - logic reserved_1_c38_we; - logic channel_status_c38_channel_free_qs; - logic channel_status_c38_channel_free_wd; - logic channel_status_c38_channel_free_we; - logic channel_status_c38_channel_error_qs; - logic channel_status_c38_channel_error_wd; - logic channel_status_c38_channel_error_we; - logic [29:0] channel_status_c38_field1_qs; - logic [29:0] channel_status_c38_field1_wd; - logic channel_status_c38_field1_we; - logic [31:0] reserved_2_c38_qs; - logic [31:0] reserved_2_c38_wd; - logic reserved_2_c38_we; - logic channel_flags_c38_intr_enable_qs; - logic channel_flags_c38_intr_enable_wd; - logic channel_flags_c38_intr_enable_we; - logic [30:0] channel_flags_c38_field1_qs; - logic [30:0] channel_flags_c38_field1_wd; - logic channel_flags_c38_field1_we; - logic [31:0] length_c38_qs; - logic [31:0] length_c38_wd; - logic length_c38_we; - logic [7:0] message_header_c38_message_id_qs; - logic [7:0] message_header_c38_message_id_wd; - logic message_header_c38_message_id_we; - logic [1:0] message_header_c38_message_type_qs; - logic [1:0] message_header_c38_message_type_wd; - logic message_header_c38_message_type_we; - logic [7:0] message_header_c38_protocol_id_qs; - logic [7:0] message_header_c38_protocol_id_wd; - logic message_header_c38_protocol_id_we; - logic [9:0] message_header_c38_token_qs; - logic [9:0] message_header_c38_token_wd; - logic message_header_c38_token_we; - logic [3:0] message_header_c38_field1_qs; - logic [3:0] message_header_c38_field1_wd; - logic message_header_c38_field1_we; - logic [31:0] message_payload_1_c38_qs; - logic [31:0] message_payload_1_c38_wd; - logic message_payload_1_c38_we; - logic doorbell_c38_intr_qs; - logic doorbell_c38_intr_wd; - logic doorbell_c38_intr_we; - logic [30:0] doorbell_c38_preserve_mask_qs; - logic [30:0] doorbell_c38_preserve_mask_wd; - logic doorbell_c38_preserve_mask_we; - logic completion_interrupt_c38_intr_qs; - logic completion_interrupt_c38_intr_wd; - logic completion_interrupt_c38_intr_we; - logic [30:0] completion_interrupt_c38_preserve_mask_qs; - logic [30:0] completion_interrupt_c38_preserve_mask_wd; - logic completion_interrupt_c38_preserve_mask_we; - logic [31:0] reserved_1_c39_qs; - logic [31:0] reserved_1_c39_wd; - logic reserved_1_c39_we; - logic channel_status_c39_channel_free_qs; - logic channel_status_c39_channel_free_wd; - logic channel_status_c39_channel_free_we; - logic channel_status_c39_channel_error_qs; - logic channel_status_c39_channel_error_wd; - logic channel_status_c39_channel_error_we; - logic [29:0] channel_status_c39_field1_qs; - logic [29:0] channel_status_c39_field1_wd; - logic channel_status_c39_field1_we; - logic [31:0] reserved_2_c39_qs; - logic [31:0] reserved_2_c39_wd; - logic reserved_2_c39_we; - logic channel_flags_c39_intr_enable_qs; - logic channel_flags_c39_intr_enable_wd; - logic channel_flags_c39_intr_enable_we; - logic [30:0] channel_flags_c39_field1_qs; - logic [30:0] channel_flags_c39_field1_wd; - logic channel_flags_c39_field1_we; - logic [31:0] length_c39_qs; - logic [31:0] length_c39_wd; - logic length_c39_we; - logic [7:0] message_header_c39_message_id_qs; - logic [7:0] message_header_c39_message_id_wd; - logic message_header_c39_message_id_we; - logic [1:0] message_header_c39_message_type_qs; - logic [1:0] message_header_c39_message_type_wd; - logic message_header_c39_message_type_we; - logic [7:0] message_header_c39_protocol_id_qs; - logic [7:0] message_header_c39_protocol_id_wd; - logic message_header_c39_protocol_id_we; - logic [9:0] message_header_c39_token_qs; - logic [9:0] message_header_c39_token_wd; - logic message_header_c39_token_we; - logic [3:0] message_header_c39_field1_qs; - logic [3:0] message_header_c39_field1_wd; - logic message_header_c39_field1_we; - logic [31:0] message_payload_1_c39_qs; - logic [31:0] message_payload_1_c39_wd; - logic message_payload_1_c39_we; - logic doorbell_c39_intr_qs; - logic doorbell_c39_intr_wd; - logic doorbell_c39_intr_we; - logic [30:0] doorbell_c39_preserve_mask_qs; - logic [30:0] doorbell_c39_preserve_mask_wd; - logic doorbell_c39_preserve_mask_we; - logic completion_interrupt_c39_intr_qs; - logic completion_interrupt_c39_intr_wd; - logic completion_interrupt_c39_intr_we; - logic [30:0] completion_interrupt_c39_preserve_mask_qs; - logic [30:0] completion_interrupt_c39_preserve_mask_wd; - logic completion_interrupt_c39_preserve_mask_we; - logic [31:0] reserved_1_c40_qs; - logic [31:0] reserved_1_c40_wd; - logic reserved_1_c40_we; - logic channel_status_c40_channel_free_qs; - logic channel_status_c40_channel_free_wd; - logic channel_status_c40_channel_free_we; - logic channel_status_c40_channel_error_qs; - logic channel_status_c40_channel_error_wd; - logic channel_status_c40_channel_error_we; - logic [29:0] channel_status_c40_field1_qs; - logic [29:0] channel_status_c40_field1_wd; - logic channel_status_c40_field1_we; - logic [31:0] reserved_2_c40_qs; - logic [31:0] reserved_2_c40_wd; - logic reserved_2_c40_we; - logic channel_flags_c40_intr_enable_qs; - logic channel_flags_c40_intr_enable_wd; - logic channel_flags_c40_intr_enable_we; - logic [30:0] channel_flags_c40_field1_qs; - logic [30:0] channel_flags_c40_field1_wd; - logic channel_flags_c40_field1_we; - logic [31:0] length_c40_qs; - logic [31:0] length_c40_wd; - logic length_c40_we; - logic [7:0] message_header_c40_message_id_qs; - logic [7:0] message_header_c40_message_id_wd; - logic message_header_c40_message_id_we; - logic [1:0] message_header_c40_message_type_qs; - logic [1:0] message_header_c40_message_type_wd; - logic message_header_c40_message_type_we; - logic [7:0] message_header_c40_protocol_id_qs; - logic [7:0] message_header_c40_protocol_id_wd; - logic message_header_c40_protocol_id_we; - logic [9:0] message_header_c40_token_qs; - logic [9:0] message_header_c40_token_wd; - logic message_header_c40_token_we; - logic [3:0] message_header_c40_field1_qs; - logic [3:0] message_header_c40_field1_wd; - logic message_header_c40_field1_we; - logic [31:0] message_payload_1_c40_qs; - logic [31:0] message_payload_1_c40_wd; - logic message_payload_1_c40_we; - logic doorbell_c40_intr_qs; - logic doorbell_c40_intr_wd; - logic doorbell_c40_intr_we; - logic [30:0] doorbell_c40_preserve_mask_qs; - logic [30:0] doorbell_c40_preserve_mask_wd; - logic doorbell_c40_preserve_mask_we; - logic completion_interrupt_c40_intr_qs; - logic completion_interrupt_c40_intr_wd; - logic completion_interrupt_c40_intr_we; - logic [30:0] completion_interrupt_c40_preserve_mask_qs; - logic [30:0] completion_interrupt_c40_preserve_mask_wd; - logic completion_interrupt_c40_preserve_mask_we; - logic [31:0] reserved_1_c41_qs; - logic [31:0] reserved_1_c41_wd; - logic reserved_1_c41_we; - logic channel_status_c41_channel_free_qs; - logic channel_status_c41_channel_free_wd; - logic channel_status_c41_channel_free_we; - logic channel_status_c41_channel_error_qs; - logic channel_status_c41_channel_error_wd; - logic channel_status_c41_channel_error_we; - logic [29:0] channel_status_c41_field1_qs; - logic [29:0] channel_status_c41_field1_wd; - logic channel_status_c41_field1_we; - logic [31:0] reserved_2_c41_qs; - logic [31:0] reserved_2_c41_wd; - logic reserved_2_c41_we; - logic channel_flags_c41_intr_enable_qs; - logic channel_flags_c41_intr_enable_wd; - logic channel_flags_c41_intr_enable_we; - logic [30:0] channel_flags_c41_field1_qs; - logic [30:0] channel_flags_c41_field1_wd; - logic channel_flags_c41_field1_we; - logic [31:0] length_c41_qs; - logic [31:0] length_c41_wd; - logic length_c41_we; - logic [7:0] message_header_c41_message_id_qs; - logic [7:0] message_header_c41_message_id_wd; - logic message_header_c41_message_id_we; - logic [1:0] message_header_c41_message_type_qs; - logic [1:0] message_header_c41_message_type_wd; - logic message_header_c41_message_type_we; - logic [7:0] message_header_c41_protocol_id_qs; - logic [7:0] message_header_c41_protocol_id_wd; - logic message_header_c41_protocol_id_we; - logic [9:0] message_header_c41_token_qs; - logic [9:0] message_header_c41_token_wd; - logic message_header_c41_token_we; - logic [3:0] message_header_c41_field1_qs; - logic [3:0] message_header_c41_field1_wd; - logic message_header_c41_field1_we; - logic [31:0] message_payload_1_c41_qs; - logic [31:0] message_payload_1_c41_wd; - logic message_payload_1_c41_we; - logic doorbell_c41_intr_qs; - logic doorbell_c41_intr_wd; - logic doorbell_c41_intr_we; - logic [30:0] doorbell_c41_preserve_mask_qs; - logic [30:0] doorbell_c41_preserve_mask_wd; - logic doorbell_c41_preserve_mask_we; - logic completion_interrupt_c41_intr_qs; - logic completion_interrupt_c41_intr_wd; - logic completion_interrupt_c41_intr_we; - logic [30:0] completion_interrupt_c41_preserve_mask_qs; - logic [30:0] completion_interrupt_c41_preserve_mask_wd; - logic completion_interrupt_c41_preserve_mask_we; - logic [31:0] reserved_1_c42_qs; - logic [31:0] reserved_1_c42_wd; - logic reserved_1_c42_we; - logic channel_status_c42_channel_free_qs; - logic channel_status_c42_channel_free_wd; - logic channel_status_c42_channel_free_we; - logic channel_status_c42_channel_error_qs; - logic channel_status_c42_channel_error_wd; - logic channel_status_c42_channel_error_we; - logic [29:0] channel_status_c42_field1_qs; - logic [29:0] channel_status_c42_field1_wd; - logic channel_status_c42_field1_we; - logic [31:0] reserved_2_c42_qs; - logic [31:0] reserved_2_c42_wd; - logic reserved_2_c42_we; - logic channel_flags_c42_intr_enable_qs; - logic channel_flags_c42_intr_enable_wd; - logic channel_flags_c42_intr_enable_we; - logic [30:0] channel_flags_c42_field1_qs; - logic [30:0] channel_flags_c42_field1_wd; - logic channel_flags_c42_field1_we; - logic [31:0] length_c42_qs; - logic [31:0] length_c42_wd; - logic length_c42_we; - logic [7:0] message_header_c42_message_id_qs; - logic [7:0] message_header_c42_message_id_wd; - logic message_header_c42_message_id_we; - logic [1:0] message_header_c42_message_type_qs; - logic [1:0] message_header_c42_message_type_wd; - logic message_header_c42_message_type_we; - logic [7:0] message_header_c42_protocol_id_qs; - logic [7:0] message_header_c42_protocol_id_wd; - logic message_header_c42_protocol_id_we; - logic [9:0] message_header_c42_token_qs; - logic [9:0] message_header_c42_token_wd; - logic message_header_c42_token_we; - logic [3:0] message_header_c42_field1_qs; - logic [3:0] message_header_c42_field1_wd; - logic message_header_c42_field1_we; - logic [31:0] message_payload_1_c42_qs; - logic [31:0] message_payload_1_c42_wd; - logic message_payload_1_c42_we; - logic doorbell_c42_intr_qs; - logic doorbell_c42_intr_wd; - logic doorbell_c42_intr_we; - logic [30:0] doorbell_c42_preserve_mask_qs; - logic [30:0] doorbell_c42_preserve_mask_wd; - logic doorbell_c42_preserve_mask_we; - logic completion_interrupt_c42_intr_qs; - logic completion_interrupt_c42_intr_wd; - logic completion_interrupt_c42_intr_we; - logic [30:0] completion_interrupt_c42_preserve_mask_qs; - logic [30:0] completion_interrupt_c42_preserve_mask_wd; - logic completion_interrupt_c42_preserve_mask_we; - logic [31:0] reserved_1_c43_qs; - logic [31:0] reserved_1_c43_wd; - logic reserved_1_c43_we; - logic channel_status_c43_channel_free_qs; - logic channel_status_c43_channel_free_wd; - logic channel_status_c43_channel_free_we; - logic channel_status_c43_channel_error_qs; - logic channel_status_c43_channel_error_wd; - logic channel_status_c43_channel_error_we; - logic [29:0] channel_status_c43_field1_qs; - logic [29:0] channel_status_c43_field1_wd; - logic channel_status_c43_field1_we; - logic [31:0] reserved_2_c43_qs; - logic [31:0] reserved_2_c43_wd; - logic reserved_2_c43_we; - logic channel_flags_c43_intr_enable_qs; - logic channel_flags_c43_intr_enable_wd; - logic channel_flags_c43_intr_enable_we; - logic [30:0] channel_flags_c43_field1_qs; - logic [30:0] channel_flags_c43_field1_wd; - logic channel_flags_c43_field1_we; - logic [31:0] length_c43_qs; - logic [31:0] length_c43_wd; - logic length_c43_we; - logic [7:0] message_header_c43_message_id_qs; - logic [7:0] message_header_c43_message_id_wd; - logic message_header_c43_message_id_we; - logic [1:0] message_header_c43_message_type_qs; - logic [1:0] message_header_c43_message_type_wd; - logic message_header_c43_message_type_we; - logic [7:0] message_header_c43_protocol_id_qs; - logic [7:0] message_header_c43_protocol_id_wd; - logic message_header_c43_protocol_id_we; - logic [9:0] message_header_c43_token_qs; - logic [9:0] message_header_c43_token_wd; - logic message_header_c43_token_we; - logic [3:0] message_header_c43_field1_qs; - logic [3:0] message_header_c43_field1_wd; - logic message_header_c43_field1_we; - logic [31:0] message_payload_1_c43_qs; - logic [31:0] message_payload_1_c43_wd; - logic message_payload_1_c43_we; - logic doorbell_c43_intr_qs; - logic doorbell_c43_intr_wd; - logic doorbell_c43_intr_we; - logic [30:0] doorbell_c43_preserve_mask_qs; - logic [30:0] doorbell_c43_preserve_mask_wd; - logic doorbell_c43_preserve_mask_we; - logic completion_interrupt_c43_intr_qs; - logic completion_interrupt_c43_intr_wd; - logic completion_interrupt_c43_intr_we; - logic [30:0] completion_interrupt_c43_preserve_mask_qs; - logic [30:0] completion_interrupt_c43_preserve_mask_wd; - logic completion_interrupt_c43_preserve_mask_we; - logic [31:0] reserved_1_c44_qs; - logic [31:0] reserved_1_c44_wd; - logic reserved_1_c44_we; - logic channel_status_c44_channel_free_qs; - logic channel_status_c44_channel_free_wd; - logic channel_status_c44_channel_free_we; - logic channel_status_c44_channel_error_qs; - logic channel_status_c44_channel_error_wd; - logic channel_status_c44_channel_error_we; - logic [29:0] channel_status_c44_field1_qs; - logic [29:0] channel_status_c44_field1_wd; - logic channel_status_c44_field1_we; - logic [31:0] reserved_2_c44_qs; - logic [31:0] reserved_2_c44_wd; - logic reserved_2_c44_we; - logic channel_flags_c44_intr_enable_qs; - logic channel_flags_c44_intr_enable_wd; - logic channel_flags_c44_intr_enable_we; - logic [30:0] channel_flags_c44_field1_qs; - logic [30:0] channel_flags_c44_field1_wd; - logic channel_flags_c44_field1_we; - logic [31:0] length_c44_qs; - logic [31:0] length_c44_wd; - logic length_c44_we; - logic [7:0] message_header_c44_message_id_qs; - logic [7:0] message_header_c44_message_id_wd; - logic message_header_c44_message_id_we; - logic [1:0] message_header_c44_message_type_qs; - logic [1:0] message_header_c44_message_type_wd; - logic message_header_c44_message_type_we; - logic [7:0] message_header_c44_protocol_id_qs; - logic [7:0] message_header_c44_protocol_id_wd; - logic message_header_c44_protocol_id_we; - logic [9:0] message_header_c44_token_qs; - logic [9:0] message_header_c44_token_wd; - logic message_header_c44_token_we; - logic [3:0] message_header_c44_field1_qs; - logic [3:0] message_header_c44_field1_wd; - logic message_header_c44_field1_we; - logic [31:0] message_payload_1_c44_qs; - logic [31:0] message_payload_1_c44_wd; - logic message_payload_1_c44_we; - logic doorbell_c44_intr_qs; - logic doorbell_c44_intr_wd; - logic doorbell_c44_intr_we; - logic [30:0] doorbell_c44_preserve_mask_qs; - logic [30:0] doorbell_c44_preserve_mask_wd; - logic doorbell_c44_preserve_mask_we; - logic completion_interrupt_c44_intr_qs; - logic completion_interrupt_c44_intr_wd; - logic completion_interrupt_c44_intr_we; - logic [30:0] completion_interrupt_c44_preserve_mask_qs; - logic [30:0] completion_interrupt_c44_preserve_mask_wd; - logic completion_interrupt_c44_preserve_mask_we; - logic [31:0] reserved_1_c45_qs; - logic [31:0] reserved_1_c45_wd; - logic reserved_1_c45_we; - logic channel_status_c45_channel_free_qs; - logic channel_status_c45_channel_free_wd; - logic channel_status_c45_channel_free_we; - logic channel_status_c45_channel_error_qs; - logic channel_status_c45_channel_error_wd; - logic channel_status_c45_channel_error_we; - logic [29:0] channel_status_c45_field1_qs; - logic [29:0] channel_status_c45_field1_wd; - logic channel_status_c45_field1_we; - logic [31:0] reserved_2_c45_qs; - logic [31:0] reserved_2_c45_wd; - logic reserved_2_c45_we; - logic channel_flags_c45_intr_enable_qs; - logic channel_flags_c45_intr_enable_wd; - logic channel_flags_c45_intr_enable_we; - logic [30:0] channel_flags_c45_field1_qs; - logic [30:0] channel_flags_c45_field1_wd; - logic channel_flags_c45_field1_we; - logic [31:0] length_c45_qs; - logic [31:0] length_c45_wd; - logic length_c45_we; - logic [7:0] message_header_c45_message_id_qs; - logic [7:0] message_header_c45_message_id_wd; - logic message_header_c45_message_id_we; - logic [1:0] message_header_c45_message_type_qs; - logic [1:0] message_header_c45_message_type_wd; - logic message_header_c45_message_type_we; - logic [7:0] message_header_c45_protocol_id_qs; - logic [7:0] message_header_c45_protocol_id_wd; - logic message_header_c45_protocol_id_we; - logic [9:0] message_header_c45_token_qs; - logic [9:0] message_header_c45_token_wd; - logic message_header_c45_token_we; - logic [3:0] message_header_c45_field1_qs; - logic [3:0] message_header_c45_field1_wd; - logic message_header_c45_field1_we; - logic [31:0] message_payload_1_c45_qs; - logic [31:0] message_payload_1_c45_wd; - logic message_payload_1_c45_we; - logic doorbell_c45_intr_qs; - logic doorbell_c45_intr_wd; - logic doorbell_c45_intr_we; - logic [30:0] doorbell_c45_preserve_mask_qs; - logic [30:0] doorbell_c45_preserve_mask_wd; - logic doorbell_c45_preserve_mask_we; - logic completion_interrupt_c45_intr_qs; - logic completion_interrupt_c45_intr_wd; - logic completion_interrupt_c45_intr_we; - logic [30:0] completion_interrupt_c45_preserve_mask_qs; - logic [30:0] completion_interrupt_c45_preserve_mask_wd; - logic completion_interrupt_c45_preserve_mask_we; - logic [31:0] reserved_1_c46_qs; - logic [31:0] reserved_1_c46_wd; - logic reserved_1_c46_we; - logic channel_status_c46_channel_free_qs; - logic channel_status_c46_channel_free_wd; - logic channel_status_c46_channel_free_we; - logic channel_status_c46_channel_error_qs; - logic channel_status_c46_channel_error_wd; - logic channel_status_c46_channel_error_we; - logic [29:0] channel_status_c46_field1_qs; - logic [29:0] channel_status_c46_field1_wd; - logic channel_status_c46_field1_we; - logic [31:0] reserved_2_c46_qs; - logic [31:0] reserved_2_c46_wd; - logic reserved_2_c46_we; - logic channel_flags_c46_intr_enable_qs; - logic channel_flags_c46_intr_enable_wd; - logic channel_flags_c46_intr_enable_we; - logic [30:0] channel_flags_c46_field1_qs; - logic [30:0] channel_flags_c46_field1_wd; - logic channel_flags_c46_field1_we; - logic [31:0] length_c46_qs; - logic [31:0] length_c46_wd; - logic length_c46_we; - logic [7:0] message_header_c46_message_id_qs; - logic [7:0] message_header_c46_message_id_wd; - logic message_header_c46_message_id_we; - logic [1:0] message_header_c46_message_type_qs; - logic [1:0] message_header_c46_message_type_wd; - logic message_header_c46_message_type_we; - logic [7:0] message_header_c46_protocol_id_qs; - logic [7:0] message_header_c46_protocol_id_wd; - logic message_header_c46_protocol_id_we; - logic [9:0] message_header_c46_token_qs; - logic [9:0] message_header_c46_token_wd; - logic message_header_c46_token_we; - logic [3:0] message_header_c46_field1_qs; - logic [3:0] message_header_c46_field1_wd; - logic message_header_c46_field1_we; - logic [31:0] message_payload_1_c46_qs; - logic [31:0] message_payload_1_c46_wd; - logic message_payload_1_c46_we; - logic doorbell_c46_intr_qs; - logic doorbell_c46_intr_wd; - logic doorbell_c46_intr_we; - logic [30:0] doorbell_c46_preserve_mask_qs; - logic [30:0] doorbell_c46_preserve_mask_wd; - logic doorbell_c46_preserve_mask_we; - logic completion_interrupt_c46_intr_qs; - logic completion_interrupt_c46_intr_wd; - logic completion_interrupt_c46_intr_we; - logic [30:0] completion_interrupt_c46_preserve_mask_qs; - logic [30:0] completion_interrupt_c46_preserve_mask_wd; - logic completion_interrupt_c46_preserve_mask_we; - logic [31:0] reserved_1_c47_qs; - logic [31:0] reserved_1_c47_wd; - logic reserved_1_c47_we; - logic channel_status_c47_channel_free_qs; - logic channel_status_c47_channel_free_wd; - logic channel_status_c47_channel_free_we; - logic channel_status_c47_channel_error_qs; - logic channel_status_c47_channel_error_wd; - logic channel_status_c47_channel_error_we; - logic [29:0] channel_status_c47_field1_qs; - logic [29:0] channel_status_c47_field1_wd; - logic channel_status_c47_field1_we; - logic [31:0] reserved_2_c47_qs; - logic [31:0] reserved_2_c47_wd; - logic reserved_2_c47_we; - logic channel_flags_c47_intr_enable_qs; - logic channel_flags_c47_intr_enable_wd; - logic channel_flags_c47_intr_enable_we; - logic [30:0] channel_flags_c47_field1_qs; - logic [30:0] channel_flags_c47_field1_wd; - logic channel_flags_c47_field1_we; - logic [31:0] length_c47_qs; - logic [31:0] length_c47_wd; - logic length_c47_we; - logic [7:0] message_header_c47_message_id_qs; - logic [7:0] message_header_c47_message_id_wd; - logic message_header_c47_message_id_we; - logic [1:0] message_header_c47_message_type_qs; - logic [1:0] message_header_c47_message_type_wd; - logic message_header_c47_message_type_we; - logic [7:0] message_header_c47_protocol_id_qs; - logic [7:0] message_header_c47_protocol_id_wd; - logic message_header_c47_protocol_id_we; - logic [9:0] message_header_c47_token_qs; - logic [9:0] message_header_c47_token_wd; - logic message_header_c47_token_we; - logic [3:0] message_header_c47_field1_qs; - logic [3:0] message_header_c47_field1_wd; - logic message_header_c47_field1_we; - logic [31:0] message_payload_1_c47_qs; - logic [31:0] message_payload_1_c47_wd; - logic message_payload_1_c47_we; - logic doorbell_c47_intr_qs; - logic doorbell_c47_intr_wd; - logic doorbell_c47_intr_we; - logic [30:0] doorbell_c47_preserve_mask_qs; - logic [30:0] doorbell_c47_preserve_mask_wd; - logic doorbell_c47_preserve_mask_we; - logic completion_interrupt_c47_intr_qs; - logic completion_interrupt_c47_intr_wd; - logic completion_interrupt_c47_intr_we; - logic [30:0] completion_interrupt_c47_preserve_mask_qs; - logic [30:0] completion_interrupt_c47_preserve_mask_wd; - logic completion_interrupt_c47_preserve_mask_we; - logic [31:0] reserved_1_c48_qs; - logic [31:0] reserved_1_c48_wd; - logic reserved_1_c48_we; - logic channel_status_c48_channel_free_qs; - logic channel_status_c48_channel_free_wd; - logic channel_status_c48_channel_free_we; - logic channel_status_c48_channel_error_qs; - logic channel_status_c48_channel_error_wd; - logic channel_status_c48_channel_error_we; - logic [29:0] channel_status_c48_field1_qs; - logic [29:0] channel_status_c48_field1_wd; - logic channel_status_c48_field1_we; - logic [31:0] reserved_2_c48_qs; - logic [31:0] reserved_2_c48_wd; - logic reserved_2_c48_we; - logic channel_flags_c48_intr_enable_qs; - logic channel_flags_c48_intr_enable_wd; - logic channel_flags_c48_intr_enable_we; - logic [30:0] channel_flags_c48_field1_qs; - logic [30:0] channel_flags_c48_field1_wd; - logic channel_flags_c48_field1_we; - logic [31:0] length_c48_qs; - logic [31:0] length_c48_wd; - logic length_c48_we; - logic [7:0] message_header_c48_message_id_qs; - logic [7:0] message_header_c48_message_id_wd; - logic message_header_c48_message_id_we; - logic [1:0] message_header_c48_message_type_qs; - logic [1:0] message_header_c48_message_type_wd; - logic message_header_c48_message_type_we; - logic [7:0] message_header_c48_protocol_id_qs; - logic [7:0] message_header_c48_protocol_id_wd; - logic message_header_c48_protocol_id_we; - logic [9:0] message_header_c48_token_qs; - logic [9:0] message_header_c48_token_wd; - logic message_header_c48_token_we; - logic [3:0] message_header_c48_field1_qs; - logic [3:0] message_header_c48_field1_wd; - logic message_header_c48_field1_we; - logic [31:0] message_payload_1_c48_qs; - logic [31:0] message_payload_1_c48_wd; - logic message_payload_1_c48_we; - logic doorbell_c48_intr_qs; - logic doorbell_c48_intr_wd; - logic doorbell_c48_intr_we; - logic [30:0] doorbell_c48_preserve_mask_qs; - logic [30:0] doorbell_c48_preserve_mask_wd; - logic doorbell_c48_preserve_mask_we; - logic completion_interrupt_c48_intr_qs; - logic completion_interrupt_c48_intr_wd; - logic completion_interrupt_c48_intr_we; - logic [30:0] completion_interrupt_c48_preserve_mask_qs; - logic [30:0] completion_interrupt_c48_preserve_mask_wd; - logic completion_interrupt_c48_preserve_mask_we; - logic [31:0] reserved_1_c49_qs; - logic [31:0] reserved_1_c49_wd; - logic reserved_1_c49_we; - logic channel_status_c49_channel_free_qs; - logic channel_status_c49_channel_free_wd; - logic channel_status_c49_channel_free_we; - logic channel_status_c49_channel_error_qs; - logic channel_status_c49_channel_error_wd; - logic channel_status_c49_channel_error_we; - logic [29:0] channel_status_c49_field1_qs; - logic [29:0] channel_status_c49_field1_wd; - logic channel_status_c49_field1_we; - logic [31:0] reserved_2_c49_qs; - logic [31:0] reserved_2_c49_wd; - logic reserved_2_c49_we; - logic channel_flags_c49_intr_enable_qs; - logic channel_flags_c49_intr_enable_wd; - logic channel_flags_c49_intr_enable_we; - logic [30:0] channel_flags_c49_field1_qs; - logic [30:0] channel_flags_c49_field1_wd; - logic channel_flags_c49_field1_we; - logic [31:0] length_c49_qs; - logic [31:0] length_c49_wd; - logic length_c49_we; - logic [7:0] message_header_c49_message_id_qs; - logic [7:0] message_header_c49_message_id_wd; - logic message_header_c49_message_id_we; - logic [1:0] message_header_c49_message_type_qs; - logic [1:0] message_header_c49_message_type_wd; - logic message_header_c49_message_type_we; - logic [7:0] message_header_c49_protocol_id_qs; - logic [7:0] message_header_c49_protocol_id_wd; - logic message_header_c49_protocol_id_we; - logic [9:0] message_header_c49_token_qs; - logic [9:0] message_header_c49_token_wd; - logic message_header_c49_token_we; - logic [3:0] message_header_c49_field1_qs; - logic [3:0] message_header_c49_field1_wd; - logic message_header_c49_field1_we; - logic [31:0] message_payload_1_c49_qs; - logic [31:0] message_payload_1_c49_wd; - logic message_payload_1_c49_we; - logic doorbell_c49_intr_qs; - logic doorbell_c49_intr_wd; - logic doorbell_c49_intr_we; - logic [30:0] doorbell_c49_preserve_mask_qs; - logic [30:0] doorbell_c49_preserve_mask_wd; - logic doorbell_c49_preserve_mask_we; - logic completion_interrupt_c49_intr_qs; - logic completion_interrupt_c49_intr_wd; - logic completion_interrupt_c49_intr_we; - logic [30:0] completion_interrupt_c49_preserve_mask_qs; - logic [30:0] completion_interrupt_c49_preserve_mask_wd; - logic completion_interrupt_c49_preserve_mask_we; - logic [31:0] reserved_1_c50_qs; - logic [31:0] reserved_1_c50_wd; - logic reserved_1_c50_we; - logic channel_status_c50_channel_free_qs; - logic channel_status_c50_channel_free_wd; - logic channel_status_c50_channel_free_we; - logic channel_status_c50_channel_error_qs; - logic channel_status_c50_channel_error_wd; - logic channel_status_c50_channel_error_we; - logic [29:0] channel_status_c50_field1_qs; - logic [29:0] channel_status_c50_field1_wd; - logic channel_status_c50_field1_we; - logic [31:0] reserved_2_c50_qs; - logic [31:0] reserved_2_c50_wd; - logic reserved_2_c50_we; - logic channel_flags_c50_intr_enable_qs; - logic channel_flags_c50_intr_enable_wd; - logic channel_flags_c50_intr_enable_we; - logic [30:0] channel_flags_c50_field1_qs; - logic [30:0] channel_flags_c50_field1_wd; - logic channel_flags_c50_field1_we; - logic [31:0] length_c50_qs; - logic [31:0] length_c50_wd; - logic length_c50_we; - logic [7:0] message_header_c50_message_id_qs; - logic [7:0] message_header_c50_message_id_wd; - logic message_header_c50_message_id_we; - logic [1:0] message_header_c50_message_type_qs; - logic [1:0] message_header_c50_message_type_wd; - logic message_header_c50_message_type_we; - logic [7:0] message_header_c50_protocol_id_qs; - logic [7:0] message_header_c50_protocol_id_wd; - logic message_header_c50_protocol_id_we; - logic [9:0] message_header_c50_token_qs; - logic [9:0] message_header_c50_token_wd; - logic message_header_c50_token_we; - logic [3:0] message_header_c50_field1_qs; - logic [3:0] message_header_c50_field1_wd; - logic message_header_c50_field1_we; - logic [31:0] message_payload_1_c50_qs; - logic [31:0] message_payload_1_c50_wd; - logic message_payload_1_c50_we; - logic doorbell_c50_intr_qs; - logic doorbell_c50_intr_wd; - logic doorbell_c50_intr_we; - logic [30:0] doorbell_c50_preserve_mask_qs; - logic [30:0] doorbell_c50_preserve_mask_wd; - logic doorbell_c50_preserve_mask_we; - logic completion_interrupt_c50_intr_qs; - logic completion_interrupt_c50_intr_wd; - logic completion_interrupt_c50_intr_we; - logic [30:0] completion_interrupt_c50_preserve_mask_qs; - logic [30:0] completion_interrupt_c50_preserve_mask_wd; - logic completion_interrupt_c50_preserve_mask_we; - logic [31:0] reserved_1_c51_qs; - logic [31:0] reserved_1_c51_wd; - logic reserved_1_c51_we; - logic channel_status_c51_channel_free_qs; - logic channel_status_c51_channel_free_wd; - logic channel_status_c51_channel_free_we; - logic channel_status_c51_channel_error_qs; - logic channel_status_c51_channel_error_wd; - logic channel_status_c51_channel_error_we; - logic [29:0] channel_status_c51_field1_qs; - logic [29:0] channel_status_c51_field1_wd; - logic channel_status_c51_field1_we; - logic [31:0] reserved_2_c51_qs; - logic [31:0] reserved_2_c51_wd; - logic reserved_2_c51_we; - logic channel_flags_c51_intr_enable_qs; - logic channel_flags_c51_intr_enable_wd; - logic channel_flags_c51_intr_enable_we; - logic [30:0] channel_flags_c51_field1_qs; - logic [30:0] channel_flags_c51_field1_wd; - logic channel_flags_c51_field1_we; - logic [31:0] length_c51_qs; - logic [31:0] length_c51_wd; - logic length_c51_we; - logic [7:0] message_header_c51_message_id_qs; - logic [7:0] message_header_c51_message_id_wd; - logic message_header_c51_message_id_we; - logic [1:0] message_header_c51_message_type_qs; - logic [1:0] message_header_c51_message_type_wd; - logic message_header_c51_message_type_we; - logic [7:0] message_header_c51_protocol_id_qs; - logic [7:0] message_header_c51_protocol_id_wd; - logic message_header_c51_protocol_id_we; - logic [9:0] message_header_c51_token_qs; - logic [9:0] message_header_c51_token_wd; - logic message_header_c51_token_we; - logic [3:0] message_header_c51_field1_qs; - logic [3:0] message_header_c51_field1_wd; - logic message_header_c51_field1_we; - logic [31:0] message_payload_1_c51_qs; - logic [31:0] message_payload_1_c51_wd; - logic message_payload_1_c51_we; - logic doorbell_c51_intr_qs; - logic doorbell_c51_intr_wd; - logic doorbell_c51_intr_we; - logic [30:0] doorbell_c51_preserve_mask_qs; - logic [30:0] doorbell_c51_preserve_mask_wd; - logic doorbell_c51_preserve_mask_we; - logic completion_interrupt_c51_intr_qs; - logic completion_interrupt_c51_intr_wd; - logic completion_interrupt_c51_intr_we; - logic [30:0] completion_interrupt_c51_preserve_mask_qs; - logic [30:0] completion_interrupt_c51_preserve_mask_wd; - logic completion_interrupt_c51_preserve_mask_we; - logic [31:0] reserved_1_c52_qs; - logic [31:0] reserved_1_c52_wd; - logic reserved_1_c52_we; - logic channel_status_c52_channel_free_qs; - logic channel_status_c52_channel_free_wd; - logic channel_status_c52_channel_free_we; - logic channel_status_c52_channel_error_qs; - logic channel_status_c52_channel_error_wd; - logic channel_status_c52_channel_error_we; - logic [29:0] channel_status_c52_field1_qs; - logic [29:0] channel_status_c52_field1_wd; - logic channel_status_c52_field1_we; - logic [31:0] reserved_2_c52_qs; - logic [31:0] reserved_2_c52_wd; - logic reserved_2_c52_we; - logic channel_flags_c52_intr_enable_qs; - logic channel_flags_c52_intr_enable_wd; - logic channel_flags_c52_intr_enable_we; - logic [30:0] channel_flags_c52_field1_qs; - logic [30:0] channel_flags_c52_field1_wd; - logic channel_flags_c52_field1_we; - logic [31:0] length_c52_qs; - logic [31:0] length_c52_wd; - logic length_c52_we; - logic [7:0] message_header_c52_message_id_qs; - logic [7:0] message_header_c52_message_id_wd; - logic message_header_c52_message_id_we; - logic [1:0] message_header_c52_message_type_qs; - logic [1:0] message_header_c52_message_type_wd; - logic message_header_c52_message_type_we; - logic [7:0] message_header_c52_protocol_id_qs; - logic [7:0] message_header_c52_protocol_id_wd; - logic message_header_c52_protocol_id_we; - logic [9:0] message_header_c52_token_qs; - logic [9:0] message_header_c52_token_wd; - logic message_header_c52_token_we; - logic [3:0] message_header_c52_field1_qs; - logic [3:0] message_header_c52_field1_wd; - logic message_header_c52_field1_we; - logic [31:0] message_payload_1_c52_qs; - logic [31:0] message_payload_1_c52_wd; - logic message_payload_1_c52_we; - logic doorbell_c52_intr_qs; - logic doorbell_c52_intr_wd; - logic doorbell_c52_intr_we; - logic [30:0] doorbell_c52_preserve_mask_qs; - logic [30:0] doorbell_c52_preserve_mask_wd; - logic doorbell_c52_preserve_mask_we; - logic completion_interrupt_c52_intr_qs; - logic completion_interrupt_c52_intr_wd; - logic completion_interrupt_c52_intr_we; - logic [30:0] completion_interrupt_c52_preserve_mask_qs; - logic [30:0] completion_interrupt_c52_preserve_mask_wd; - logic completion_interrupt_c52_preserve_mask_we; - logic [31:0] reserved_1_c53_qs; - logic [31:0] reserved_1_c53_wd; - logic reserved_1_c53_we; - logic channel_status_c53_channel_free_qs; - logic channel_status_c53_channel_free_wd; - logic channel_status_c53_channel_free_we; - logic channel_status_c53_channel_error_qs; - logic channel_status_c53_channel_error_wd; - logic channel_status_c53_channel_error_we; - logic [29:0] channel_status_c53_field1_qs; - logic [29:0] channel_status_c53_field1_wd; - logic channel_status_c53_field1_we; - logic [31:0] reserved_2_c53_qs; - logic [31:0] reserved_2_c53_wd; - logic reserved_2_c53_we; - logic channel_flags_c53_intr_enable_qs; - logic channel_flags_c53_intr_enable_wd; - logic channel_flags_c53_intr_enable_we; - logic [30:0] channel_flags_c53_field1_qs; - logic [30:0] channel_flags_c53_field1_wd; - logic channel_flags_c53_field1_we; - logic [31:0] length_c53_qs; - logic [31:0] length_c53_wd; - logic length_c53_we; - logic [7:0] message_header_c53_message_id_qs; - logic [7:0] message_header_c53_message_id_wd; - logic message_header_c53_message_id_we; - logic [1:0] message_header_c53_message_type_qs; - logic [1:0] message_header_c53_message_type_wd; - logic message_header_c53_message_type_we; - logic [7:0] message_header_c53_protocol_id_qs; - logic [7:0] message_header_c53_protocol_id_wd; - logic message_header_c53_protocol_id_we; - logic [9:0] message_header_c53_token_qs; - logic [9:0] message_header_c53_token_wd; - logic message_header_c53_token_we; - logic [3:0] message_header_c53_field1_qs; - logic [3:0] message_header_c53_field1_wd; - logic message_header_c53_field1_we; - logic [31:0] message_payload_1_c53_qs; - logic [31:0] message_payload_1_c53_wd; - logic message_payload_1_c53_we; - logic doorbell_c53_intr_qs; - logic doorbell_c53_intr_wd; - logic doorbell_c53_intr_we; - logic [30:0] doorbell_c53_preserve_mask_qs; - logic [30:0] doorbell_c53_preserve_mask_wd; - logic doorbell_c53_preserve_mask_we; - logic completion_interrupt_c53_intr_qs; - logic completion_interrupt_c53_intr_wd; - logic completion_interrupt_c53_intr_we; - logic [30:0] completion_interrupt_c53_preserve_mask_qs; - logic [30:0] completion_interrupt_c53_preserve_mask_wd; - logic completion_interrupt_c53_preserve_mask_we; - logic [31:0] reserved_1_c54_qs; - logic [31:0] reserved_1_c54_wd; - logic reserved_1_c54_we; - logic channel_status_c54_channel_free_qs; - logic channel_status_c54_channel_free_wd; - logic channel_status_c54_channel_free_we; - logic channel_status_c54_channel_error_qs; - logic channel_status_c54_channel_error_wd; - logic channel_status_c54_channel_error_we; - logic [29:0] channel_status_c54_field1_qs; - logic [29:0] channel_status_c54_field1_wd; - logic channel_status_c54_field1_we; - logic [31:0] reserved_2_c54_qs; - logic [31:0] reserved_2_c54_wd; - logic reserved_2_c54_we; - logic channel_flags_c54_intr_enable_qs; - logic channel_flags_c54_intr_enable_wd; - logic channel_flags_c54_intr_enable_we; - logic [30:0] channel_flags_c54_field1_qs; - logic [30:0] channel_flags_c54_field1_wd; - logic channel_flags_c54_field1_we; - logic [31:0] length_c54_qs; - logic [31:0] length_c54_wd; - logic length_c54_we; - logic [7:0] message_header_c54_message_id_qs; - logic [7:0] message_header_c54_message_id_wd; - logic message_header_c54_message_id_we; - logic [1:0] message_header_c54_message_type_qs; - logic [1:0] message_header_c54_message_type_wd; - logic message_header_c54_message_type_we; - logic [7:0] message_header_c54_protocol_id_qs; - logic [7:0] message_header_c54_protocol_id_wd; - logic message_header_c54_protocol_id_we; - logic [9:0] message_header_c54_token_qs; - logic [9:0] message_header_c54_token_wd; - logic message_header_c54_token_we; - logic [3:0] message_header_c54_field1_qs; - logic [3:0] message_header_c54_field1_wd; - logic message_header_c54_field1_we; - logic [31:0] message_payload_1_c54_qs; - logic [31:0] message_payload_1_c54_wd; - logic message_payload_1_c54_we; - logic doorbell_c54_intr_qs; - logic doorbell_c54_intr_wd; - logic doorbell_c54_intr_we; - logic [30:0] doorbell_c54_preserve_mask_qs; - logic [30:0] doorbell_c54_preserve_mask_wd; - logic doorbell_c54_preserve_mask_we; - logic completion_interrupt_c54_intr_qs; - logic completion_interrupt_c54_intr_wd; - logic completion_interrupt_c54_intr_we; - logic [30:0] completion_interrupt_c54_preserve_mask_qs; - logic [30:0] completion_interrupt_c54_preserve_mask_wd; - logic completion_interrupt_c54_preserve_mask_we; - logic [31:0] reserved_1_c55_qs; - logic [31:0] reserved_1_c55_wd; - logic reserved_1_c55_we; - logic channel_status_c55_channel_free_qs; - logic channel_status_c55_channel_free_wd; - logic channel_status_c55_channel_free_we; - logic channel_status_c55_channel_error_qs; - logic channel_status_c55_channel_error_wd; - logic channel_status_c55_channel_error_we; - logic [29:0] channel_status_c55_field1_qs; - logic [29:0] channel_status_c55_field1_wd; - logic channel_status_c55_field1_we; - logic [31:0] reserved_2_c55_qs; - logic [31:0] reserved_2_c55_wd; - logic reserved_2_c55_we; - logic channel_flags_c55_intr_enable_qs; - logic channel_flags_c55_intr_enable_wd; - logic channel_flags_c55_intr_enable_we; - logic [30:0] channel_flags_c55_field1_qs; - logic [30:0] channel_flags_c55_field1_wd; - logic channel_flags_c55_field1_we; - logic [31:0] length_c55_qs; - logic [31:0] length_c55_wd; - logic length_c55_we; - logic [7:0] message_header_c55_message_id_qs; - logic [7:0] message_header_c55_message_id_wd; - logic message_header_c55_message_id_we; - logic [1:0] message_header_c55_message_type_qs; - logic [1:0] message_header_c55_message_type_wd; - logic message_header_c55_message_type_we; - logic [7:0] message_header_c55_protocol_id_qs; - logic [7:0] message_header_c55_protocol_id_wd; - logic message_header_c55_protocol_id_we; - logic [9:0] message_header_c55_token_qs; - logic [9:0] message_header_c55_token_wd; - logic message_header_c55_token_we; - logic [3:0] message_header_c55_field1_qs; - logic [3:0] message_header_c55_field1_wd; - logic message_header_c55_field1_we; - logic [31:0] message_payload_1_c55_qs; - logic [31:0] message_payload_1_c55_wd; - logic message_payload_1_c55_we; - logic doorbell_c55_intr_qs; - logic doorbell_c55_intr_wd; - logic doorbell_c55_intr_we; - logic [30:0] doorbell_c55_preserve_mask_qs; - logic [30:0] doorbell_c55_preserve_mask_wd; - logic doorbell_c55_preserve_mask_we; - logic completion_interrupt_c55_intr_qs; - logic completion_interrupt_c55_intr_wd; - logic completion_interrupt_c55_intr_we; - logic [30:0] completion_interrupt_c55_preserve_mask_qs; - logic [30:0] completion_interrupt_c55_preserve_mask_wd; - logic completion_interrupt_c55_preserve_mask_we; - logic [31:0] reserved_1_c56_qs; - logic [31:0] reserved_1_c56_wd; - logic reserved_1_c56_we; - logic channel_status_c56_channel_free_qs; - logic channel_status_c56_channel_free_wd; - logic channel_status_c56_channel_free_we; - logic channel_status_c56_channel_error_qs; - logic channel_status_c56_channel_error_wd; - logic channel_status_c56_channel_error_we; - logic [29:0] channel_status_c56_field1_qs; - logic [29:0] channel_status_c56_field1_wd; - logic channel_status_c56_field1_we; - logic [31:0] reserved_2_c56_qs; - logic [31:0] reserved_2_c56_wd; - logic reserved_2_c56_we; - logic channel_flags_c56_intr_enable_qs; - logic channel_flags_c56_intr_enable_wd; - logic channel_flags_c56_intr_enable_we; - logic [30:0] channel_flags_c56_field1_qs; - logic [30:0] channel_flags_c56_field1_wd; - logic channel_flags_c56_field1_we; - logic [31:0] length_c56_qs; - logic [31:0] length_c56_wd; - logic length_c56_we; - logic [7:0] message_header_c56_message_id_qs; - logic [7:0] message_header_c56_message_id_wd; - logic message_header_c56_message_id_we; - logic [1:0] message_header_c56_message_type_qs; - logic [1:0] message_header_c56_message_type_wd; - logic message_header_c56_message_type_we; - logic [7:0] message_header_c56_protocol_id_qs; - logic [7:0] message_header_c56_protocol_id_wd; - logic message_header_c56_protocol_id_we; - logic [9:0] message_header_c56_token_qs; - logic [9:0] message_header_c56_token_wd; - logic message_header_c56_token_we; - logic [3:0] message_header_c56_field1_qs; - logic [3:0] message_header_c56_field1_wd; - logic message_header_c56_field1_we; - logic [31:0] message_payload_1_c56_qs; - logic [31:0] message_payload_1_c56_wd; - logic message_payload_1_c56_we; - logic doorbell_c56_intr_qs; - logic doorbell_c56_intr_wd; - logic doorbell_c56_intr_we; - logic [30:0] doorbell_c56_preserve_mask_qs; - logic [30:0] doorbell_c56_preserve_mask_wd; - logic doorbell_c56_preserve_mask_we; - logic completion_interrupt_c56_intr_qs; - logic completion_interrupt_c56_intr_wd; - logic completion_interrupt_c56_intr_we; - logic [30:0] completion_interrupt_c56_preserve_mask_qs; - logic [30:0] completion_interrupt_c56_preserve_mask_wd; - logic completion_interrupt_c56_preserve_mask_we; - logic [31:0] reserved_1_c57_qs; - logic [31:0] reserved_1_c57_wd; - logic reserved_1_c57_we; - logic channel_status_c57_channel_free_qs; - logic channel_status_c57_channel_free_wd; - logic channel_status_c57_channel_free_we; - logic channel_status_c57_channel_error_qs; - logic channel_status_c57_channel_error_wd; - logic channel_status_c57_channel_error_we; - logic [29:0] channel_status_c57_field1_qs; - logic [29:0] channel_status_c57_field1_wd; - logic channel_status_c57_field1_we; - logic [31:0] reserved_2_c57_qs; - logic [31:0] reserved_2_c57_wd; - logic reserved_2_c57_we; - logic channel_flags_c57_intr_enable_qs; - logic channel_flags_c57_intr_enable_wd; - logic channel_flags_c57_intr_enable_we; - logic [30:0] channel_flags_c57_field1_qs; - logic [30:0] channel_flags_c57_field1_wd; - logic channel_flags_c57_field1_we; - logic [31:0] length_c57_qs; - logic [31:0] length_c57_wd; - logic length_c57_we; - logic [7:0] message_header_c57_message_id_qs; - logic [7:0] message_header_c57_message_id_wd; - logic message_header_c57_message_id_we; - logic [1:0] message_header_c57_message_type_qs; - logic [1:0] message_header_c57_message_type_wd; - logic message_header_c57_message_type_we; - logic [7:0] message_header_c57_protocol_id_qs; - logic [7:0] message_header_c57_protocol_id_wd; - logic message_header_c57_protocol_id_we; - logic [9:0] message_header_c57_token_qs; - logic [9:0] message_header_c57_token_wd; - logic message_header_c57_token_we; - logic [3:0] message_header_c57_field1_qs; - logic [3:0] message_header_c57_field1_wd; - logic message_header_c57_field1_we; - logic [31:0] message_payload_1_c57_qs; - logic [31:0] message_payload_1_c57_wd; - logic message_payload_1_c57_we; - logic doorbell_c57_intr_qs; - logic doorbell_c57_intr_wd; - logic doorbell_c57_intr_we; - logic [30:0] doorbell_c57_preserve_mask_qs; - logic [30:0] doorbell_c57_preserve_mask_wd; - logic doorbell_c57_preserve_mask_we; - logic completion_interrupt_c57_intr_qs; - logic completion_interrupt_c57_intr_wd; - logic completion_interrupt_c57_intr_we; - logic [30:0] completion_interrupt_c57_preserve_mask_qs; - logic [30:0] completion_interrupt_c57_preserve_mask_wd; - logic completion_interrupt_c57_preserve_mask_we; - logic [31:0] reserved_1_c58_qs; - logic [31:0] reserved_1_c58_wd; - logic reserved_1_c58_we; - logic channel_status_c58_channel_free_qs; - logic channel_status_c58_channel_free_wd; - logic channel_status_c58_channel_free_we; - logic channel_status_c58_channel_error_qs; - logic channel_status_c58_channel_error_wd; - logic channel_status_c58_channel_error_we; - logic [29:0] channel_status_c58_field1_qs; - logic [29:0] channel_status_c58_field1_wd; - logic channel_status_c58_field1_we; - logic [31:0] reserved_2_c58_qs; - logic [31:0] reserved_2_c58_wd; - logic reserved_2_c58_we; - logic channel_flags_c58_intr_enable_qs; - logic channel_flags_c58_intr_enable_wd; - logic channel_flags_c58_intr_enable_we; - logic [30:0] channel_flags_c58_field1_qs; - logic [30:0] channel_flags_c58_field1_wd; - logic channel_flags_c58_field1_we; - logic [31:0] length_c58_qs; - logic [31:0] length_c58_wd; - logic length_c58_we; - logic [7:0] message_header_c58_message_id_qs; - logic [7:0] message_header_c58_message_id_wd; - logic message_header_c58_message_id_we; - logic [1:0] message_header_c58_message_type_qs; - logic [1:0] message_header_c58_message_type_wd; - logic message_header_c58_message_type_we; - logic [7:0] message_header_c58_protocol_id_qs; - logic [7:0] message_header_c58_protocol_id_wd; - logic message_header_c58_protocol_id_we; - logic [9:0] message_header_c58_token_qs; - logic [9:0] message_header_c58_token_wd; - logic message_header_c58_token_we; - logic [3:0] message_header_c58_field1_qs; - logic [3:0] message_header_c58_field1_wd; - logic message_header_c58_field1_we; - logic [31:0] message_payload_1_c58_qs; - logic [31:0] message_payload_1_c58_wd; - logic message_payload_1_c58_we; - logic doorbell_c58_intr_qs; - logic doorbell_c58_intr_wd; - logic doorbell_c58_intr_we; - logic [30:0] doorbell_c58_preserve_mask_qs; - logic [30:0] doorbell_c58_preserve_mask_wd; - logic doorbell_c58_preserve_mask_we; - logic completion_interrupt_c58_intr_qs; - logic completion_interrupt_c58_intr_wd; - logic completion_interrupt_c58_intr_we; - logic [30:0] completion_interrupt_c58_preserve_mask_qs; - logic [30:0] completion_interrupt_c58_preserve_mask_wd; - logic completion_interrupt_c58_preserve_mask_we; - logic [31:0] reserved_1_c59_qs; - logic [31:0] reserved_1_c59_wd; - logic reserved_1_c59_we; - logic channel_status_c59_channel_free_qs; - logic channel_status_c59_channel_free_wd; - logic channel_status_c59_channel_free_we; - logic channel_status_c59_channel_error_qs; - logic channel_status_c59_channel_error_wd; - logic channel_status_c59_channel_error_we; - logic [29:0] channel_status_c59_field1_qs; - logic [29:0] channel_status_c59_field1_wd; - logic channel_status_c59_field1_we; - logic [31:0] reserved_2_c59_qs; - logic [31:0] reserved_2_c59_wd; - logic reserved_2_c59_we; - logic channel_flags_c59_intr_enable_qs; - logic channel_flags_c59_intr_enable_wd; - logic channel_flags_c59_intr_enable_we; - logic [30:0] channel_flags_c59_field1_qs; - logic [30:0] channel_flags_c59_field1_wd; - logic channel_flags_c59_field1_we; - logic [31:0] length_c59_qs; - logic [31:0] length_c59_wd; - logic length_c59_we; - logic [7:0] message_header_c59_message_id_qs; - logic [7:0] message_header_c59_message_id_wd; - logic message_header_c59_message_id_we; - logic [1:0] message_header_c59_message_type_qs; - logic [1:0] message_header_c59_message_type_wd; - logic message_header_c59_message_type_we; - logic [7:0] message_header_c59_protocol_id_qs; - logic [7:0] message_header_c59_protocol_id_wd; - logic message_header_c59_protocol_id_we; - logic [9:0] message_header_c59_token_qs; - logic [9:0] message_header_c59_token_wd; - logic message_header_c59_token_we; - logic [3:0] message_header_c59_field1_qs; - logic [3:0] message_header_c59_field1_wd; - logic message_header_c59_field1_we; - logic [31:0] message_payload_1_c59_qs; - logic [31:0] message_payload_1_c59_wd; - logic message_payload_1_c59_we; - logic doorbell_c59_intr_qs; - logic doorbell_c59_intr_wd; - logic doorbell_c59_intr_we; - logic [30:0] doorbell_c59_preserve_mask_qs; - logic [30:0] doorbell_c59_preserve_mask_wd; - logic doorbell_c59_preserve_mask_we; - logic completion_interrupt_c59_intr_qs; - logic completion_interrupt_c59_intr_wd; - logic completion_interrupt_c59_intr_we; - logic [30:0] completion_interrupt_c59_preserve_mask_qs; - logic [30:0] completion_interrupt_c59_preserve_mask_wd; - logic completion_interrupt_c59_preserve_mask_we; - logic [31:0] reserved_1_c60_qs; - logic [31:0] reserved_1_c60_wd; - logic reserved_1_c60_we; - logic channel_status_c60_channel_free_qs; - logic channel_status_c60_channel_free_wd; - logic channel_status_c60_channel_free_we; - logic channel_status_c60_channel_error_qs; - logic channel_status_c60_channel_error_wd; - logic channel_status_c60_channel_error_we; - logic [29:0] channel_status_c60_field1_qs; - logic [29:0] channel_status_c60_field1_wd; - logic channel_status_c60_field1_we; - logic [31:0] reserved_2_c60_qs; - logic [31:0] reserved_2_c60_wd; - logic reserved_2_c60_we; - logic channel_flags_c60_intr_enable_qs; - logic channel_flags_c60_intr_enable_wd; - logic channel_flags_c60_intr_enable_we; - logic [30:0] channel_flags_c60_field1_qs; - logic [30:0] channel_flags_c60_field1_wd; - logic channel_flags_c60_field1_we; - logic [31:0] length_c60_qs; - logic [31:0] length_c60_wd; - logic length_c60_we; - logic [7:0] message_header_c60_message_id_qs; - logic [7:0] message_header_c60_message_id_wd; - logic message_header_c60_message_id_we; - logic [1:0] message_header_c60_message_type_qs; - logic [1:0] message_header_c60_message_type_wd; - logic message_header_c60_message_type_we; - logic [7:0] message_header_c60_protocol_id_qs; - logic [7:0] message_header_c60_protocol_id_wd; - logic message_header_c60_protocol_id_we; - logic [9:0] message_header_c60_token_qs; - logic [9:0] message_header_c60_token_wd; - logic message_header_c60_token_we; - logic [3:0] message_header_c60_field1_qs; - logic [3:0] message_header_c60_field1_wd; - logic message_header_c60_field1_we; - logic [31:0] message_payload_1_c60_qs; - logic [31:0] message_payload_1_c60_wd; - logic message_payload_1_c60_we; - logic doorbell_c60_intr_qs; - logic doorbell_c60_intr_wd; - logic doorbell_c60_intr_we; - logic [30:0] doorbell_c60_preserve_mask_qs; - logic [30:0] doorbell_c60_preserve_mask_wd; - logic doorbell_c60_preserve_mask_we; - logic completion_interrupt_c60_intr_qs; - logic completion_interrupt_c60_intr_wd; - logic completion_interrupt_c60_intr_we; - logic [30:0] completion_interrupt_c60_preserve_mask_qs; - logic [30:0] completion_interrupt_c60_preserve_mask_wd; - logic completion_interrupt_c60_preserve_mask_we; - logic [31:0] reserved_1_c61_qs; - logic [31:0] reserved_1_c61_wd; - logic reserved_1_c61_we; - logic channel_status_c61_channel_free_qs; - logic channel_status_c61_channel_free_wd; - logic channel_status_c61_channel_free_we; - logic channel_status_c61_channel_error_qs; - logic channel_status_c61_channel_error_wd; - logic channel_status_c61_channel_error_we; - logic [29:0] channel_status_c61_field1_qs; - logic [29:0] channel_status_c61_field1_wd; - logic channel_status_c61_field1_we; - logic [31:0] reserved_2_c61_qs; - logic [31:0] reserved_2_c61_wd; - logic reserved_2_c61_we; - logic channel_flags_c61_intr_enable_qs; - logic channel_flags_c61_intr_enable_wd; - logic channel_flags_c61_intr_enable_we; - logic [30:0] channel_flags_c61_field1_qs; - logic [30:0] channel_flags_c61_field1_wd; - logic channel_flags_c61_field1_we; - logic [31:0] length_c61_qs; - logic [31:0] length_c61_wd; - logic length_c61_we; - logic [7:0] message_header_c61_message_id_qs; - logic [7:0] message_header_c61_message_id_wd; - logic message_header_c61_message_id_we; - logic [1:0] message_header_c61_message_type_qs; - logic [1:0] message_header_c61_message_type_wd; - logic message_header_c61_message_type_we; - logic [7:0] message_header_c61_protocol_id_qs; - logic [7:0] message_header_c61_protocol_id_wd; - logic message_header_c61_protocol_id_we; - logic [9:0] message_header_c61_token_qs; - logic [9:0] message_header_c61_token_wd; - logic message_header_c61_token_we; - logic [3:0] message_header_c61_field1_qs; - logic [3:0] message_header_c61_field1_wd; - logic message_header_c61_field1_we; - logic [31:0] message_payload_1_c61_qs; - logic [31:0] message_payload_1_c61_wd; - logic message_payload_1_c61_we; - logic doorbell_c61_intr_qs; - logic doorbell_c61_intr_wd; - logic doorbell_c61_intr_we; - logic [30:0] doorbell_c61_preserve_mask_qs; - logic [30:0] doorbell_c61_preserve_mask_wd; - logic doorbell_c61_preserve_mask_we; - logic completion_interrupt_c61_intr_qs; - logic completion_interrupt_c61_intr_wd; - logic completion_interrupt_c61_intr_we; - logic [30:0] completion_interrupt_c61_preserve_mask_qs; - logic [30:0] completion_interrupt_c61_preserve_mask_wd; - logic completion_interrupt_c61_preserve_mask_we; - logic [31:0] reserved_1_c62_qs; - logic [31:0] reserved_1_c62_wd; - logic reserved_1_c62_we; - logic channel_status_c62_channel_free_qs; - logic channel_status_c62_channel_free_wd; - logic channel_status_c62_channel_free_we; - logic channel_status_c62_channel_error_qs; - logic channel_status_c62_channel_error_wd; - logic channel_status_c62_channel_error_we; - logic [29:0] channel_status_c62_field1_qs; - logic [29:0] channel_status_c62_field1_wd; - logic channel_status_c62_field1_we; - logic [31:0] reserved_2_c62_qs; - logic [31:0] reserved_2_c62_wd; - logic reserved_2_c62_we; - logic channel_flags_c62_intr_enable_qs; - logic channel_flags_c62_intr_enable_wd; - logic channel_flags_c62_intr_enable_we; - logic [30:0] channel_flags_c62_field1_qs; - logic [30:0] channel_flags_c62_field1_wd; - logic channel_flags_c62_field1_we; - logic [31:0] length_c62_qs; - logic [31:0] length_c62_wd; - logic length_c62_we; - logic [7:0] message_header_c62_message_id_qs; - logic [7:0] message_header_c62_message_id_wd; - logic message_header_c62_message_id_we; - logic [1:0] message_header_c62_message_type_qs; - logic [1:0] message_header_c62_message_type_wd; - logic message_header_c62_message_type_we; - logic [7:0] message_header_c62_protocol_id_qs; - logic [7:0] message_header_c62_protocol_id_wd; - logic message_header_c62_protocol_id_we; - logic [9:0] message_header_c62_token_qs; - logic [9:0] message_header_c62_token_wd; - logic message_header_c62_token_we; - logic [3:0] message_header_c62_field1_qs; - logic [3:0] message_header_c62_field1_wd; - logic message_header_c62_field1_we; - logic [31:0] message_payload_1_c62_qs; - logic [31:0] message_payload_1_c62_wd; - logic message_payload_1_c62_we; - logic doorbell_c62_intr_qs; - logic doorbell_c62_intr_wd; - logic doorbell_c62_intr_we; - logic [30:0] doorbell_c62_preserve_mask_qs; - logic [30:0] doorbell_c62_preserve_mask_wd; - logic doorbell_c62_preserve_mask_we; - logic completion_interrupt_c62_intr_qs; - logic completion_interrupt_c62_intr_wd; - logic completion_interrupt_c62_intr_we; - logic [30:0] completion_interrupt_c62_preserve_mask_qs; - logic [30:0] completion_interrupt_c62_preserve_mask_wd; - logic completion_interrupt_c62_preserve_mask_we; - logic [31:0] reserved_1_c63_qs; - logic [31:0] reserved_1_c63_wd; - logic reserved_1_c63_we; - logic channel_status_c63_channel_free_qs; - logic channel_status_c63_channel_free_wd; - logic channel_status_c63_channel_free_we; - logic channel_status_c63_channel_error_qs; - logic channel_status_c63_channel_error_wd; - logic channel_status_c63_channel_error_we; - logic [29:0] channel_status_c63_field1_qs; - logic [29:0] channel_status_c63_field1_wd; - logic channel_status_c63_field1_we; - logic [31:0] reserved_2_c63_qs; - logic [31:0] reserved_2_c63_wd; - logic reserved_2_c63_we; - logic channel_flags_c63_intr_enable_qs; - logic channel_flags_c63_intr_enable_wd; - logic channel_flags_c63_intr_enable_we; - logic [30:0] channel_flags_c63_field1_qs; - logic [30:0] channel_flags_c63_field1_wd; - logic channel_flags_c63_field1_we; - logic [31:0] length_c63_qs; - logic [31:0] length_c63_wd; - logic length_c63_we; - logic [7:0] message_header_c63_message_id_qs; - logic [7:0] message_header_c63_message_id_wd; - logic message_header_c63_message_id_we; - logic [1:0] message_header_c63_message_type_qs; - logic [1:0] message_header_c63_message_type_wd; - logic message_header_c63_message_type_we; - logic [7:0] message_header_c63_protocol_id_qs; - logic [7:0] message_header_c63_protocol_id_wd; - logic message_header_c63_protocol_id_we; - logic [9:0] message_header_c63_token_qs; - logic [9:0] message_header_c63_token_wd; - logic message_header_c63_token_we; - logic [3:0] message_header_c63_field1_qs; - logic [3:0] message_header_c63_field1_wd; - logic message_header_c63_field1_we; - logic [31:0] message_payload_1_c63_qs; - logic [31:0] message_payload_1_c63_wd; - logic message_payload_1_c63_we; - logic doorbell_c63_intr_qs; - logic doorbell_c63_intr_wd; - logic doorbell_c63_intr_we; - logic [30:0] doorbell_c63_preserve_mask_qs; - logic [30:0] doorbell_c63_preserve_mask_wd; - logic doorbell_c63_preserve_mask_we; - logic completion_interrupt_c63_intr_qs; - logic completion_interrupt_c63_intr_wd; - logic completion_interrupt_c63_intr_we; - logic [30:0] completion_interrupt_c63_preserve_mask_qs; - logic [30:0] completion_interrupt_c63_preserve_mask_wd; - logic completion_interrupt_c63_preserve_mask_we; - logic [31:0] reserved_1_c64_qs; - logic [31:0] reserved_1_c64_wd; - logic reserved_1_c64_we; - logic channel_status_c64_channel_free_qs; - logic channel_status_c64_channel_free_wd; - logic channel_status_c64_channel_free_we; - logic channel_status_c64_channel_error_qs; - logic channel_status_c64_channel_error_wd; - logic channel_status_c64_channel_error_we; - logic [29:0] channel_status_c64_field1_qs; - logic [29:0] channel_status_c64_field1_wd; - logic channel_status_c64_field1_we; - logic [31:0] reserved_2_c64_qs; - logic [31:0] reserved_2_c64_wd; - logic reserved_2_c64_we; - logic channel_flags_c64_intr_enable_qs; - logic channel_flags_c64_intr_enable_wd; - logic channel_flags_c64_intr_enable_we; - logic [30:0] channel_flags_c64_field1_qs; - logic [30:0] channel_flags_c64_field1_wd; - logic channel_flags_c64_field1_we; - logic [31:0] length_c64_qs; - logic [31:0] length_c64_wd; - logic length_c64_we; - logic [7:0] message_header_c64_message_id_qs; - logic [7:0] message_header_c64_message_id_wd; - logic message_header_c64_message_id_we; - logic [1:0] message_header_c64_message_type_qs; - logic [1:0] message_header_c64_message_type_wd; - logic message_header_c64_message_type_we; - logic [7:0] message_header_c64_protocol_id_qs; - logic [7:0] message_header_c64_protocol_id_wd; - logic message_header_c64_protocol_id_we; - logic [9:0] message_header_c64_token_qs; - logic [9:0] message_header_c64_token_wd; - logic message_header_c64_token_we; - logic [3:0] message_header_c64_field1_qs; - logic [3:0] message_header_c64_field1_wd; - logic message_header_c64_field1_we; - logic [31:0] message_payload_1_c64_qs; - logic [31:0] message_payload_1_c64_wd; - logic message_payload_1_c64_we; - logic doorbell_c64_intr_qs; - logic doorbell_c64_intr_wd; - logic doorbell_c64_intr_we; - logic [30:0] doorbell_c64_preserve_mask_qs; - logic [30:0] doorbell_c64_preserve_mask_wd; - logic doorbell_c64_preserve_mask_we; - logic completion_interrupt_c64_intr_qs; - logic completion_interrupt_c64_intr_wd; - logic completion_interrupt_c64_intr_we; - logic [30:0] completion_interrupt_c64_preserve_mask_qs; - logic [30:0] completion_interrupt_c64_preserve_mask_wd; - logic completion_interrupt_c64_preserve_mask_we; - logic [31:0] reserved_1_c65_qs; - logic [31:0] reserved_1_c65_wd; - logic reserved_1_c65_we; - logic channel_status_c65_channel_free_qs; - logic channel_status_c65_channel_free_wd; - logic channel_status_c65_channel_free_we; - logic channel_status_c65_channel_error_qs; - logic channel_status_c65_channel_error_wd; - logic channel_status_c65_channel_error_we; - logic [29:0] channel_status_c65_field1_qs; - logic [29:0] channel_status_c65_field1_wd; - logic channel_status_c65_field1_we; - logic [31:0] reserved_2_c65_qs; - logic [31:0] reserved_2_c65_wd; - logic reserved_2_c65_we; - logic channel_flags_c65_intr_enable_qs; - logic channel_flags_c65_intr_enable_wd; - logic channel_flags_c65_intr_enable_we; - logic [30:0] channel_flags_c65_field1_qs; - logic [30:0] channel_flags_c65_field1_wd; - logic channel_flags_c65_field1_we; - logic [31:0] length_c65_qs; - logic [31:0] length_c65_wd; - logic length_c65_we; - logic [7:0] message_header_c65_message_id_qs; - logic [7:0] message_header_c65_message_id_wd; - logic message_header_c65_message_id_we; - logic [1:0] message_header_c65_message_type_qs; - logic [1:0] message_header_c65_message_type_wd; - logic message_header_c65_message_type_we; - logic [7:0] message_header_c65_protocol_id_qs; - logic [7:0] message_header_c65_protocol_id_wd; - logic message_header_c65_protocol_id_we; - logic [9:0] message_header_c65_token_qs; - logic [9:0] message_header_c65_token_wd; - logic message_header_c65_token_we; - logic [3:0] message_header_c65_field1_qs; - logic [3:0] message_header_c65_field1_wd; - logic message_header_c65_field1_we; - logic [31:0] message_payload_1_c65_qs; - logic [31:0] message_payload_1_c65_wd; - logic message_payload_1_c65_we; - logic doorbell_c65_intr_qs; - logic doorbell_c65_intr_wd; - logic doorbell_c65_intr_we; - logic [30:0] doorbell_c65_preserve_mask_qs; - logic [30:0] doorbell_c65_preserve_mask_wd; - logic doorbell_c65_preserve_mask_we; - logic completion_interrupt_c65_intr_qs; - logic completion_interrupt_c65_intr_wd; - logic completion_interrupt_c65_intr_we; - logic [30:0] completion_interrupt_c65_preserve_mask_qs; - logic [30:0] completion_interrupt_c65_preserve_mask_wd; - logic completion_interrupt_c65_preserve_mask_we; - logic [31:0] reserved_1_c66_qs; - logic [31:0] reserved_1_c66_wd; - logic reserved_1_c66_we; - logic channel_status_c66_channel_free_qs; - logic channel_status_c66_channel_free_wd; - logic channel_status_c66_channel_free_we; - logic channel_status_c66_channel_error_qs; - logic channel_status_c66_channel_error_wd; - logic channel_status_c66_channel_error_we; - logic [29:0] channel_status_c66_field1_qs; - logic [29:0] channel_status_c66_field1_wd; - logic channel_status_c66_field1_we; - logic [31:0] reserved_2_c66_qs; - logic [31:0] reserved_2_c66_wd; - logic reserved_2_c66_we; - logic channel_flags_c66_intr_enable_qs; - logic channel_flags_c66_intr_enable_wd; - logic channel_flags_c66_intr_enable_we; - logic [30:0] channel_flags_c66_field1_qs; - logic [30:0] channel_flags_c66_field1_wd; - logic channel_flags_c66_field1_we; - logic [31:0] length_c66_qs; - logic [31:0] length_c66_wd; - logic length_c66_we; - logic [7:0] message_header_c66_message_id_qs; - logic [7:0] message_header_c66_message_id_wd; - logic message_header_c66_message_id_we; - logic [1:0] message_header_c66_message_type_qs; - logic [1:0] message_header_c66_message_type_wd; - logic message_header_c66_message_type_we; - logic [7:0] message_header_c66_protocol_id_qs; - logic [7:0] message_header_c66_protocol_id_wd; - logic message_header_c66_protocol_id_we; - logic [9:0] message_header_c66_token_qs; - logic [9:0] message_header_c66_token_wd; - logic message_header_c66_token_we; - logic [3:0] message_header_c66_field1_qs; - logic [3:0] message_header_c66_field1_wd; - logic message_header_c66_field1_we; - logic [31:0] message_payload_1_c66_qs; - logic [31:0] message_payload_1_c66_wd; - logic message_payload_1_c66_we; - logic doorbell_c66_intr_qs; - logic doorbell_c66_intr_wd; - logic doorbell_c66_intr_we; - logic [30:0] doorbell_c66_preserve_mask_qs; - logic [30:0] doorbell_c66_preserve_mask_wd; - logic doorbell_c66_preserve_mask_we; - logic completion_interrupt_c66_intr_qs; - logic completion_interrupt_c66_intr_wd; - logic completion_interrupt_c66_intr_we; - logic [30:0] completion_interrupt_c66_preserve_mask_qs; - logic [30:0] completion_interrupt_c66_preserve_mask_wd; - logic completion_interrupt_c66_preserve_mask_we; - logic [31:0] reserved_1_c67_qs; - logic [31:0] reserved_1_c67_wd; - logic reserved_1_c67_we; - logic channel_status_c67_channel_free_qs; - logic channel_status_c67_channel_free_wd; - logic channel_status_c67_channel_free_we; - logic channel_status_c67_channel_error_qs; - logic channel_status_c67_channel_error_wd; - logic channel_status_c67_channel_error_we; - logic [29:0] channel_status_c67_field1_qs; - logic [29:0] channel_status_c67_field1_wd; - logic channel_status_c67_field1_we; - logic [31:0] reserved_2_c67_qs; - logic [31:0] reserved_2_c67_wd; - logic reserved_2_c67_we; - logic channel_flags_c67_intr_enable_qs; - logic channel_flags_c67_intr_enable_wd; - logic channel_flags_c67_intr_enable_we; - logic [30:0] channel_flags_c67_field1_qs; - logic [30:0] channel_flags_c67_field1_wd; - logic channel_flags_c67_field1_we; - logic [31:0] length_c67_qs; - logic [31:0] length_c67_wd; - logic length_c67_we; - logic [7:0] message_header_c67_message_id_qs; - logic [7:0] message_header_c67_message_id_wd; - logic message_header_c67_message_id_we; - logic [1:0] message_header_c67_message_type_qs; - logic [1:0] message_header_c67_message_type_wd; - logic message_header_c67_message_type_we; - logic [7:0] message_header_c67_protocol_id_qs; - logic [7:0] message_header_c67_protocol_id_wd; - logic message_header_c67_protocol_id_we; - logic [9:0] message_header_c67_token_qs; - logic [9:0] message_header_c67_token_wd; - logic message_header_c67_token_we; - logic [3:0] message_header_c67_field1_qs; - logic [3:0] message_header_c67_field1_wd; - logic message_header_c67_field1_we; - logic [31:0] message_payload_1_c67_qs; - logic [31:0] message_payload_1_c67_wd; - logic message_payload_1_c67_we; - logic doorbell_c67_intr_qs; - logic doorbell_c67_intr_wd; - logic doorbell_c67_intr_we; - logic [30:0] doorbell_c67_preserve_mask_qs; - logic [30:0] doorbell_c67_preserve_mask_wd; - logic doorbell_c67_preserve_mask_we; - logic completion_interrupt_c67_intr_qs; - logic completion_interrupt_c67_intr_wd; - logic completion_interrupt_c67_intr_we; - logic [30:0] completion_interrupt_c67_preserve_mask_qs; - logic [30:0] completion_interrupt_c67_preserve_mask_wd; - logic completion_interrupt_c67_preserve_mask_we; - logic [31:0] reserved_1_c68_qs; - logic [31:0] reserved_1_c68_wd; - logic reserved_1_c68_we; - logic channel_status_c68_channel_free_qs; - logic channel_status_c68_channel_free_wd; - logic channel_status_c68_channel_free_we; - logic channel_status_c68_channel_error_qs; - logic channel_status_c68_channel_error_wd; - logic channel_status_c68_channel_error_we; - logic [29:0] channel_status_c68_field1_qs; - logic [29:0] channel_status_c68_field1_wd; - logic channel_status_c68_field1_we; - logic [31:0] reserved_2_c68_qs; - logic [31:0] reserved_2_c68_wd; - logic reserved_2_c68_we; - logic channel_flags_c68_intr_enable_qs; - logic channel_flags_c68_intr_enable_wd; - logic channel_flags_c68_intr_enable_we; - logic [30:0] channel_flags_c68_field1_qs; - logic [30:0] channel_flags_c68_field1_wd; - logic channel_flags_c68_field1_we; - logic [31:0] length_c68_qs; - logic [31:0] length_c68_wd; - logic length_c68_we; - logic [7:0] message_header_c68_message_id_qs; - logic [7:0] message_header_c68_message_id_wd; - logic message_header_c68_message_id_we; - logic [1:0] message_header_c68_message_type_qs; - logic [1:0] message_header_c68_message_type_wd; - logic message_header_c68_message_type_we; - logic [7:0] message_header_c68_protocol_id_qs; - logic [7:0] message_header_c68_protocol_id_wd; - logic message_header_c68_protocol_id_we; - logic [9:0] message_header_c68_token_qs; - logic [9:0] message_header_c68_token_wd; - logic message_header_c68_token_we; - logic [3:0] message_header_c68_field1_qs; - logic [3:0] message_header_c68_field1_wd; - logic message_header_c68_field1_we; - logic [31:0] message_payload_1_c68_qs; - logic [31:0] message_payload_1_c68_wd; - logic message_payload_1_c68_we; - logic doorbell_c68_intr_qs; - logic doorbell_c68_intr_wd; - logic doorbell_c68_intr_we; - logic [30:0] doorbell_c68_preserve_mask_qs; - logic [30:0] doorbell_c68_preserve_mask_wd; - logic doorbell_c68_preserve_mask_we; - logic completion_interrupt_c68_intr_qs; - logic completion_interrupt_c68_intr_wd; - logic completion_interrupt_c68_intr_we; - logic [30:0] completion_interrupt_c68_preserve_mask_qs; - logic [30:0] completion_interrupt_c68_preserve_mask_wd; - logic completion_interrupt_c68_preserve_mask_we; - logic [31:0] reserved_1_c69_qs; - logic [31:0] reserved_1_c69_wd; - logic reserved_1_c69_we; - logic channel_status_c69_channel_free_qs; - logic channel_status_c69_channel_free_wd; - logic channel_status_c69_channel_free_we; - logic channel_status_c69_channel_error_qs; - logic channel_status_c69_channel_error_wd; - logic channel_status_c69_channel_error_we; - logic [29:0] channel_status_c69_field1_qs; - logic [29:0] channel_status_c69_field1_wd; - logic channel_status_c69_field1_we; - logic [31:0] reserved_2_c69_qs; - logic [31:0] reserved_2_c69_wd; - logic reserved_2_c69_we; - logic channel_flags_c69_intr_enable_qs; - logic channel_flags_c69_intr_enable_wd; - logic channel_flags_c69_intr_enable_we; - logic [30:0] channel_flags_c69_field1_qs; - logic [30:0] channel_flags_c69_field1_wd; - logic channel_flags_c69_field1_we; - logic [31:0] length_c69_qs; - logic [31:0] length_c69_wd; - logic length_c69_we; - logic [7:0] message_header_c69_message_id_qs; - logic [7:0] message_header_c69_message_id_wd; - logic message_header_c69_message_id_we; - logic [1:0] message_header_c69_message_type_qs; - logic [1:0] message_header_c69_message_type_wd; - logic message_header_c69_message_type_we; - logic [7:0] message_header_c69_protocol_id_qs; - logic [7:0] message_header_c69_protocol_id_wd; - logic message_header_c69_protocol_id_we; - logic [9:0] message_header_c69_token_qs; - logic [9:0] message_header_c69_token_wd; - logic message_header_c69_token_we; - logic [3:0] message_header_c69_field1_qs; - logic [3:0] message_header_c69_field1_wd; - logic message_header_c69_field1_we; - logic [31:0] message_payload_1_c69_qs; - logic [31:0] message_payload_1_c69_wd; - logic message_payload_1_c69_we; - logic doorbell_c69_intr_qs; - logic doorbell_c69_intr_wd; - logic doorbell_c69_intr_we; - logic [30:0] doorbell_c69_preserve_mask_qs; - logic [30:0] doorbell_c69_preserve_mask_wd; - logic doorbell_c69_preserve_mask_we; - logic completion_interrupt_c69_intr_qs; - logic completion_interrupt_c69_intr_wd; - logic completion_interrupt_c69_intr_we; - logic [30:0] completion_interrupt_c69_preserve_mask_qs; - logic [30:0] completion_interrupt_c69_preserve_mask_wd; - logic completion_interrupt_c69_preserve_mask_we; - logic [31:0] reserved_1_c70_qs; - logic [31:0] reserved_1_c70_wd; - logic reserved_1_c70_we; - logic channel_status_c70_channel_free_qs; - logic channel_status_c70_channel_free_wd; - logic channel_status_c70_channel_free_we; - logic channel_status_c70_channel_error_qs; - logic channel_status_c70_channel_error_wd; - logic channel_status_c70_channel_error_we; - logic [29:0] channel_status_c70_field1_qs; - logic [29:0] channel_status_c70_field1_wd; - logic channel_status_c70_field1_we; - logic [31:0] reserved_2_c70_qs; - logic [31:0] reserved_2_c70_wd; - logic reserved_2_c70_we; - logic channel_flags_c70_intr_enable_qs; - logic channel_flags_c70_intr_enable_wd; - logic channel_flags_c70_intr_enable_we; - logic [30:0] channel_flags_c70_field1_qs; - logic [30:0] channel_flags_c70_field1_wd; - logic channel_flags_c70_field1_we; - logic [31:0] length_c70_qs; - logic [31:0] length_c70_wd; - logic length_c70_we; - logic [7:0] message_header_c70_message_id_qs; - logic [7:0] message_header_c70_message_id_wd; - logic message_header_c70_message_id_we; - logic [1:0] message_header_c70_message_type_qs; - logic [1:0] message_header_c70_message_type_wd; - logic message_header_c70_message_type_we; - logic [7:0] message_header_c70_protocol_id_qs; - logic [7:0] message_header_c70_protocol_id_wd; - logic message_header_c70_protocol_id_we; - logic [9:0] message_header_c70_token_qs; - logic [9:0] message_header_c70_token_wd; - logic message_header_c70_token_we; - logic [3:0] message_header_c70_field1_qs; - logic [3:0] message_header_c70_field1_wd; - logic message_header_c70_field1_we; - logic [31:0] message_payload_1_c70_qs; - logic [31:0] message_payload_1_c70_wd; - logic message_payload_1_c70_we; - logic doorbell_c70_intr_qs; - logic doorbell_c70_intr_wd; - logic doorbell_c70_intr_we; - logic [30:0] doorbell_c70_preserve_mask_qs; - logic [30:0] doorbell_c70_preserve_mask_wd; - logic doorbell_c70_preserve_mask_we; - logic completion_interrupt_c70_intr_qs; - logic completion_interrupt_c70_intr_wd; - logic completion_interrupt_c70_intr_we; - logic [30:0] completion_interrupt_c70_preserve_mask_qs; - logic [30:0] completion_interrupt_c70_preserve_mask_wd; - logic completion_interrupt_c70_preserve_mask_we; - logic [31:0] reserved_1_c71_qs; - logic [31:0] reserved_1_c71_wd; - logic reserved_1_c71_we; - logic channel_status_c71_channel_free_qs; - logic channel_status_c71_channel_free_wd; - logic channel_status_c71_channel_free_we; - logic channel_status_c71_channel_error_qs; - logic channel_status_c71_channel_error_wd; - logic channel_status_c71_channel_error_we; - logic [29:0] channel_status_c71_field1_qs; - logic [29:0] channel_status_c71_field1_wd; - logic channel_status_c71_field1_we; - logic [31:0] reserved_2_c71_qs; - logic [31:0] reserved_2_c71_wd; - logic reserved_2_c71_we; - logic channel_flags_c71_intr_enable_qs; - logic channel_flags_c71_intr_enable_wd; - logic channel_flags_c71_intr_enable_we; - logic [30:0] channel_flags_c71_field1_qs; - logic [30:0] channel_flags_c71_field1_wd; - logic channel_flags_c71_field1_we; - logic [31:0] length_c71_qs; - logic [31:0] length_c71_wd; - logic length_c71_we; - logic [7:0] message_header_c71_message_id_qs; - logic [7:0] message_header_c71_message_id_wd; - logic message_header_c71_message_id_we; - logic [1:0] message_header_c71_message_type_qs; - logic [1:0] message_header_c71_message_type_wd; - logic message_header_c71_message_type_we; - logic [7:0] message_header_c71_protocol_id_qs; - logic [7:0] message_header_c71_protocol_id_wd; - logic message_header_c71_protocol_id_we; - logic [9:0] message_header_c71_token_qs; - logic [9:0] message_header_c71_token_wd; - logic message_header_c71_token_we; - logic [3:0] message_header_c71_field1_qs; - logic [3:0] message_header_c71_field1_wd; - logic message_header_c71_field1_we; - logic [31:0] message_payload_1_c71_qs; - logic [31:0] message_payload_1_c71_wd; - logic message_payload_1_c71_we; - logic doorbell_c71_intr_qs; - logic doorbell_c71_intr_wd; - logic doorbell_c71_intr_we; - logic [30:0] doorbell_c71_preserve_mask_qs; - logic [30:0] doorbell_c71_preserve_mask_wd; - logic doorbell_c71_preserve_mask_we; - logic completion_interrupt_c71_intr_qs; - logic completion_interrupt_c71_intr_wd; - logic completion_interrupt_c71_intr_we; - logic [30:0] completion_interrupt_c71_preserve_mask_qs; - logic [30:0] completion_interrupt_c71_preserve_mask_wd; - logic completion_interrupt_c71_preserve_mask_we; - logic [31:0] reserved_1_c72_qs; - logic [31:0] reserved_1_c72_wd; - logic reserved_1_c72_we; - logic channel_status_c72_channel_free_qs; - logic channel_status_c72_channel_free_wd; - logic channel_status_c72_channel_free_we; - logic channel_status_c72_channel_error_qs; - logic channel_status_c72_channel_error_wd; - logic channel_status_c72_channel_error_we; - logic [29:0] channel_status_c72_field1_qs; - logic [29:0] channel_status_c72_field1_wd; - logic channel_status_c72_field1_we; - logic [31:0] reserved_2_c72_qs; - logic [31:0] reserved_2_c72_wd; - logic reserved_2_c72_we; - logic channel_flags_c72_intr_enable_qs; - logic channel_flags_c72_intr_enable_wd; - logic channel_flags_c72_intr_enable_we; - logic [30:0] channel_flags_c72_field1_qs; - logic [30:0] channel_flags_c72_field1_wd; - logic channel_flags_c72_field1_we; - logic [31:0] length_c72_qs; - logic [31:0] length_c72_wd; - logic length_c72_we; - logic [7:0] message_header_c72_message_id_qs; - logic [7:0] message_header_c72_message_id_wd; - logic message_header_c72_message_id_we; - logic [1:0] message_header_c72_message_type_qs; - logic [1:0] message_header_c72_message_type_wd; - logic message_header_c72_message_type_we; - logic [7:0] message_header_c72_protocol_id_qs; - logic [7:0] message_header_c72_protocol_id_wd; - logic message_header_c72_protocol_id_we; - logic [9:0] message_header_c72_token_qs; - logic [9:0] message_header_c72_token_wd; - logic message_header_c72_token_we; - logic [3:0] message_header_c72_field1_qs; - logic [3:0] message_header_c72_field1_wd; - logic message_header_c72_field1_we; - logic [31:0] message_payload_1_c72_qs; - logic [31:0] message_payload_1_c72_wd; - logic message_payload_1_c72_we; - logic doorbell_c72_intr_qs; - logic doorbell_c72_intr_wd; - logic doorbell_c72_intr_we; - logic [30:0] doorbell_c72_preserve_mask_qs; - logic [30:0] doorbell_c72_preserve_mask_wd; - logic doorbell_c72_preserve_mask_we; - logic completion_interrupt_c72_intr_qs; - logic completion_interrupt_c72_intr_wd; - logic completion_interrupt_c72_intr_we; - logic [30:0] completion_interrupt_c72_preserve_mask_qs; - logic [30:0] completion_interrupt_c72_preserve_mask_wd; - logic completion_interrupt_c72_preserve_mask_we; - logic [31:0] reserved_1_c73_qs; - logic [31:0] reserved_1_c73_wd; - logic reserved_1_c73_we; - logic channel_status_c73_channel_free_qs; - logic channel_status_c73_channel_free_wd; - logic channel_status_c73_channel_free_we; - logic channel_status_c73_channel_error_qs; - logic channel_status_c73_channel_error_wd; - logic channel_status_c73_channel_error_we; - logic [29:0] channel_status_c73_field1_qs; - logic [29:0] channel_status_c73_field1_wd; - logic channel_status_c73_field1_we; - logic [31:0] reserved_2_c73_qs; - logic [31:0] reserved_2_c73_wd; - logic reserved_2_c73_we; - logic channel_flags_c73_intr_enable_qs; - logic channel_flags_c73_intr_enable_wd; - logic channel_flags_c73_intr_enable_we; - logic [30:0] channel_flags_c73_field1_qs; - logic [30:0] channel_flags_c73_field1_wd; - logic channel_flags_c73_field1_we; - logic [31:0] length_c73_qs; - logic [31:0] length_c73_wd; - logic length_c73_we; - logic [7:0] message_header_c73_message_id_qs; - logic [7:0] message_header_c73_message_id_wd; - logic message_header_c73_message_id_we; - logic [1:0] message_header_c73_message_type_qs; - logic [1:0] message_header_c73_message_type_wd; - logic message_header_c73_message_type_we; - logic [7:0] message_header_c73_protocol_id_qs; - logic [7:0] message_header_c73_protocol_id_wd; - logic message_header_c73_protocol_id_we; - logic [9:0] message_header_c73_token_qs; - logic [9:0] message_header_c73_token_wd; - logic message_header_c73_token_we; - logic [3:0] message_header_c73_field1_qs; - logic [3:0] message_header_c73_field1_wd; - logic message_header_c73_field1_we; - logic [31:0] message_payload_1_c73_qs; - logic [31:0] message_payload_1_c73_wd; - logic message_payload_1_c73_we; - logic doorbell_c73_intr_qs; - logic doorbell_c73_intr_wd; - logic doorbell_c73_intr_we; - logic [30:0] doorbell_c73_preserve_mask_qs; - logic [30:0] doorbell_c73_preserve_mask_wd; - logic doorbell_c73_preserve_mask_we; - logic completion_interrupt_c73_intr_qs; - logic completion_interrupt_c73_intr_wd; - logic completion_interrupt_c73_intr_we; - logic [30:0] completion_interrupt_c73_preserve_mask_qs; - logic [30:0] completion_interrupt_c73_preserve_mask_wd; - logic completion_interrupt_c73_preserve_mask_we; - logic [31:0] reserved_1_c74_qs; - logic [31:0] reserved_1_c74_wd; - logic reserved_1_c74_we; - logic channel_status_c74_channel_free_qs; - logic channel_status_c74_channel_free_wd; - logic channel_status_c74_channel_free_we; - logic channel_status_c74_channel_error_qs; - logic channel_status_c74_channel_error_wd; - logic channel_status_c74_channel_error_we; - logic [29:0] channel_status_c74_field1_qs; - logic [29:0] channel_status_c74_field1_wd; - logic channel_status_c74_field1_we; - logic [31:0] reserved_2_c74_qs; - logic [31:0] reserved_2_c74_wd; - logic reserved_2_c74_we; - logic channel_flags_c74_intr_enable_qs; - logic channel_flags_c74_intr_enable_wd; - logic channel_flags_c74_intr_enable_we; - logic [30:0] channel_flags_c74_field1_qs; - logic [30:0] channel_flags_c74_field1_wd; - logic channel_flags_c74_field1_we; - logic [31:0] length_c74_qs; - logic [31:0] length_c74_wd; - logic length_c74_we; - logic [7:0] message_header_c74_message_id_qs; - logic [7:0] message_header_c74_message_id_wd; - logic message_header_c74_message_id_we; - logic [1:0] message_header_c74_message_type_qs; - logic [1:0] message_header_c74_message_type_wd; - logic message_header_c74_message_type_we; - logic [7:0] message_header_c74_protocol_id_qs; - logic [7:0] message_header_c74_protocol_id_wd; - logic message_header_c74_protocol_id_we; - logic [9:0] message_header_c74_token_qs; - logic [9:0] message_header_c74_token_wd; - logic message_header_c74_token_we; - logic [3:0] message_header_c74_field1_qs; - logic [3:0] message_header_c74_field1_wd; - logic message_header_c74_field1_we; - logic [31:0] message_payload_1_c74_qs; - logic [31:0] message_payload_1_c74_wd; - logic message_payload_1_c74_we; - logic doorbell_c74_intr_qs; - logic doorbell_c74_intr_wd; - logic doorbell_c74_intr_we; - logic [30:0] doorbell_c74_preserve_mask_qs; - logic [30:0] doorbell_c74_preserve_mask_wd; - logic doorbell_c74_preserve_mask_we; - logic completion_interrupt_c74_intr_qs; - logic completion_interrupt_c74_intr_wd; - logic completion_interrupt_c74_intr_we; - logic [30:0] completion_interrupt_c74_preserve_mask_qs; - logic [30:0] completion_interrupt_c74_preserve_mask_wd; - logic completion_interrupt_c74_preserve_mask_we; - logic [31:0] reserved_1_c75_qs; - logic [31:0] reserved_1_c75_wd; - logic reserved_1_c75_we; - logic channel_status_c75_channel_free_qs; - logic channel_status_c75_channel_free_wd; - logic channel_status_c75_channel_free_we; - logic channel_status_c75_channel_error_qs; - logic channel_status_c75_channel_error_wd; - logic channel_status_c75_channel_error_we; - logic [29:0] channel_status_c75_field1_qs; - logic [29:0] channel_status_c75_field1_wd; - logic channel_status_c75_field1_we; - logic [31:0] reserved_2_c75_qs; - logic [31:0] reserved_2_c75_wd; - logic reserved_2_c75_we; - logic channel_flags_c75_intr_enable_qs; - logic channel_flags_c75_intr_enable_wd; - logic channel_flags_c75_intr_enable_we; - logic [30:0] channel_flags_c75_field1_qs; - logic [30:0] channel_flags_c75_field1_wd; - logic channel_flags_c75_field1_we; - logic [31:0] length_c75_qs; - logic [31:0] length_c75_wd; - logic length_c75_we; - logic [7:0] message_header_c75_message_id_qs; - logic [7:0] message_header_c75_message_id_wd; - logic message_header_c75_message_id_we; - logic [1:0] message_header_c75_message_type_qs; - logic [1:0] message_header_c75_message_type_wd; - logic message_header_c75_message_type_we; - logic [7:0] message_header_c75_protocol_id_qs; - logic [7:0] message_header_c75_protocol_id_wd; - logic message_header_c75_protocol_id_we; - logic [9:0] message_header_c75_token_qs; - logic [9:0] message_header_c75_token_wd; - logic message_header_c75_token_we; - logic [3:0] message_header_c75_field1_qs; - logic [3:0] message_header_c75_field1_wd; - logic message_header_c75_field1_we; - logic [31:0] message_payload_1_c75_qs; - logic [31:0] message_payload_1_c75_wd; - logic message_payload_1_c75_we; - logic doorbell_c75_intr_qs; - logic doorbell_c75_intr_wd; - logic doorbell_c75_intr_we; - logic [30:0] doorbell_c75_preserve_mask_qs; - logic [30:0] doorbell_c75_preserve_mask_wd; - logic doorbell_c75_preserve_mask_we; - logic completion_interrupt_c75_intr_qs; - logic completion_interrupt_c75_intr_wd; - logic completion_interrupt_c75_intr_we; - logic [30:0] completion_interrupt_c75_preserve_mask_qs; - logic [30:0] completion_interrupt_c75_preserve_mask_wd; - logic completion_interrupt_c75_preserve_mask_we; - logic [31:0] reserved_1_c76_qs; - logic [31:0] reserved_1_c76_wd; - logic reserved_1_c76_we; - logic channel_status_c76_channel_free_qs; - logic channel_status_c76_channel_free_wd; - logic channel_status_c76_channel_free_we; - logic channel_status_c76_channel_error_qs; - logic channel_status_c76_channel_error_wd; - logic channel_status_c76_channel_error_we; - logic [29:0] channel_status_c76_field1_qs; - logic [29:0] channel_status_c76_field1_wd; - logic channel_status_c76_field1_we; - logic [31:0] reserved_2_c76_qs; - logic [31:0] reserved_2_c76_wd; - logic reserved_2_c76_we; - logic channel_flags_c76_intr_enable_qs; - logic channel_flags_c76_intr_enable_wd; - logic channel_flags_c76_intr_enable_we; - logic [30:0] channel_flags_c76_field1_qs; - logic [30:0] channel_flags_c76_field1_wd; - logic channel_flags_c76_field1_we; - logic [31:0] length_c76_qs; - logic [31:0] length_c76_wd; - logic length_c76_we; - logic [7:0] message_header_c76_message_id_qs; - logic [7:0] message_header_c76_message_id_wd; - logic message_header_c76_message_id_we; - logic [1:0] message_header_c76_message_type_qs; - logic [1:0] message_header_c76_message_type_wd; - logic message_header_c76_message_type_we; - logic [7:0] message_header_c76_protocol_id_qs; - logic [7:0] message_header_c76_protocol_id_wd; - logic message_header_c76_protocol_id_we; - logic [9:0] message_header_c76_token_qs; - logic [9:0] message_header_c76_token_wd; - logic message_header_c76_token_we; - logic [3:0] message_header_c76_field1_qs; - logic [3:0] message_header_c76_field1_wd; - logic message_header_c76_field1_we; - logic [31:0] message_payload_1_c76_qs; - logic [31:0] message_payload_1_c76_wd; - logic message_payload_1_c76_we; - logic doorbell_c76_intr_qs; - logic doorbell_c76_intr_wd; - logic doorbell_c76_intr_we; - logic [30:0] doorbell_c76_preserve_mask_qs; - logic [30:0] doorbell_c76_preserve_mask_wd; - logic doorbell_c76_preserve_mask_we; - logic completion_interrupt_c76_intr_qs; - logic completion_interrupt_c76_intr_wd; - logic completion_interrupt_c76_intr_we; - logic [30:0] completion_interrupt_c76_preserve_mask_qs; - logic [30:0] completion_interrupt_c76_preserve_mask_wd; - logic completion_interrupt_c76_preserve_mask_we; - logic [31:0] reserved_1_c77_qs; - logic [31:0] reserved_1_c77_wd; - logic reserved_1_c77_we; - logic channel_status_c77_channel_free_qs; - logic channel_status_c77_channel_free_wd; - logic channel_status_c77_channel_free_we; - logic channel_status_c77_channel_error_qs; - logic channel_status_c77_channel_error_wd; - logic channel_status_c77_channel_error_we; - logic [29:0] channel_status_c77_field1_qs; - logic [29:0] channel_status_c77_field1_wd; - logic channel_status_c77_field1_we; - logic [31:0] reserved_2_c77_qs; - logic [31:0] reserved_2_c77_wd; - logic reserved_2_c77_we; - logic channel_flags_c77_intr_enable_qs; - logic channel_flags_c77_intr_enable_wd; - logic channel_flags_c77_intr_enable_we; - logic [30:0] channel_flags_c77_field1_qs; - logic [30:0] channel_flags_c77_field1_wd; - logic channel_flags_c77_field1_we; - logic [31:0] length_c77_qs; - logic [31:0] length_c77_wd; - logic length_c77_we; - logic [7:0] message_header_c77_message_id_qs; - logic [7:0] message_header_c77_message_id_wd; - logic message_header_c77_message_id_we; - logic [1:0] message_header_c77_message_type_qs; - logic [1:0] message_header_c77_message_type_wd; - logic message_header_c77_message_type_we; - logic [7:0] message_header_c77_protocol_id_qs; - logic [7:0] message_header_c77_protocol_id_wd; - logic message_header_c77_protocol_id_we; - logic [9:0] message_header_c77_token_qs; - logic [9:0] message_header_c77_token_wd; - logic message_header_c77_token_we; - logic [3:0] message_header_c77_field1_qs; - logic [3:0] message_header_c77_field1_wd; - logic message_header_c77_field1_we; - logic [31:0] message_payload_1_c77_qs; - logic [31:0] message_payload_1_c77_wd; - logic message_payload_1_c77_we; - logic doorbell_c77_intr_qs; - logic doorbell_c77_intr_wd; - logic doorbell_c77_intr_we; - logic [30:0] doorbell_c77_preserve_mask_qs; - logic [30:0] doorbell_c77_preserve_mask_wd; - logic doorbell_c77_preserve_mask_we; - logic completion_interrupt_c77_intr_qs; - logic completion_interrupt_c77_intr_wd; - logic completion_interrupt_c77_intr_we; - logic [30:0] completion_interrupt_c77_preserve_mask_qs; - logic [30:0] completion_interrupt_c77_preserve_mask_wd; - logic completion_interrupt_c77_preserve_mask_we; - logic [31:0] reserved_1_c78_qs; - logic [31:0] reserved_1_c78_wd; - logic reserved_1_c78_we; - logic channel_status_c78_channel_free_qs; - logic channel_status_c78_channel_free_wd; - logic channel_status_c78_channel_free_we; - logic channel_status_c78_channel_error_qs; - logic channel_status_c78_channel_error_wd; - logic channel_status_c78_channel_error_we; - logic [29:0] channel_status_c78_field1_qs; - logic [29:0] channel_status_c78_field1_wd; - logic channel_status_c78_field1_we; - logic [31:0] reserved_2_c78_qs; - logic [31:0] reserved_2_c78_wd; - logic reserved_2_c78_we; - logic channel_flags_c78_intr_enable_qs; - logic channel_flags_c78_intr_enable_wd; - logic channel_flags_c78_intr_enable_we; - logic [30:0] channel_flags_c78_field1_qs; - logic [30:0] channel_flags_c78_field1_wd; - logic channel_flags_c78_field1_we; - logic [31:0] length_c78_qs; - logic [31:0] length_c78_wd; - logic length_c78_we; - logic [7:0] message_header_c78_message_id_qs; - logic [7:0] message_header_c78_message_id_wd; - logic message_header_c78_message_id_we; - logic [1:0] message_header_c78_message_type_qs; - logic [1:0] message_header_c78_message_type_wd; - logic message_header_c78_message_type_we; - logic [7:0] message_header_c78_protocol_id_qs; - logic [7:0] message_header_c78_protocol_id_wd; - logic message_header_c78_protocol_id_we; - logic [9:0] message_header_c78_token_qs; - logic [9:0] message_header_c78_token_wd; - logic message_header_c78_token_we; - logic [3:0] message_header_c78_field1_qs; - logic [3:0] message_header_c78_field1_wd; - logic message_header_c78_field1_we; - logic [31:0] message_payload_1_c78_qs; - logic [31:0] message_payload_1_c78_wd; - logic message_payload_1_c78_we; - logic doorbell_c78_intr_qs; - logic doorbell_c78_intr_wd; - logic doorbell_c78_intr_we; - logic [30:0] doorbell_c78_preserve_mask_qs; - logic [30:0] doorbell_c78_preserve_mask_wd; - logic doorbell_c78_preserve_mask_we; - logic completion_interrupt_c78_intr_qs; - logic completion_interrupt_c78_intr_wd; - logic completion_interrupt_c78_intr_we; - logic [30:0] completion_interrupt_c78_preserve_mask_qs; - logic [30:0] completion_interrupt_c78_preserve_mask_wd; - logic completion_interrupt_c78_preserve_mask_we; - logic [31:0] reserved_1_c79_qs; - logic [31:0] reserved_1_c79_wd; - logic reserved_1_c79_we; - logic channel_status_c79_channel_free_qs; - logic channel_status_c79_channel_free_wd; - logic channel_status_c79_channel_free_we; - logic channel_status_c79_channel_error_qs; - logic channel_status_c79_channel_error_wd; - logic channel_status_c79_channel_error_we; - logic [29:0] channel_status_c79_field1_qs; - logic [29:0] channel_status_c79_field1_wd; - logic channel_status_c79_field1_we; - logic [31:0] reserved_2_c79_qs; - logic [31:0] reserved_2_c79_wd; - logic reserved_2_c79_we; - logic channel_flags_c79_intr_enable_qs; - logic channel_flags_c79_intr_enable_wd; - logic channel_flags_c79_intr_enable_we; - logic [30:0] channel_flags_c79_field1_qs; - logic [30:0] channel_flags_c79_field1_wd; - logic channel_flags_c79_field1_we; - logic [31:0] length_c79_qs; - logic [31:0] length_c79_wd; - logic length_c79_we; - logic [7:0] message_header_c79_message_id_qs; - logic [7:0] message_header_c79_message_id_wd; - logic message_header_c79_message_id_we; - logic [1:0] message_header_c79_message_type_qs; - logic [1:0] message_header_c79_message_type_wd; - logic message_header_c79_message_type_we; - logic [7:0] message_header_c79_protocol_id_qs; - logic [7:0] message_header_c79_protocol_id_wd; - logic message_header_c79_protocol_id_we; - logic [9:0] message_header_c79_token_qs; - logic [9:0] message_header_c79_token_wd; - logic message_header_c79_token_we; - logic [3:0] message_header_c79_field1_qs; - logic [3:0] message_header_c79_field1_wd; - logic message_header_c79_field1_we; - logic [31:0] message_payload_1_c79_qs; - logic [31:0] message_payload_1_c79_wd; - logic message_payload_1_c79_we; - logic doorbell_c79_intr_qs; - logic doorbell_c79_intr_wd; - logic doorbell_c79_intr_we; - logic [30:0] doorbell_c79_preserve_mask_qs; - logic [30:0] doorbell_c79_preserve_mask_wd; - logic doorbell_c79_preserve_mask_we; - logic completion_interrupt_c79_intr_qs; - logic completion_interrupt_c79_intr_wd; - logic completion_interrupt_c79_intr_we; - logic [30:0] completion_interrupt_c79_preserve_mask_qs; - logic [30:0] completion_interrupt_c79_preserve_mask_wd; - logic completion_interrupt_c79_preserve_mask_we; - logic [31:0] reserved_1_c80_qs; - logic [31:0] reserved_1_c80_wd; - logic reserved_1_c80_we; - logic channel_status_c80_channel_free_qs; - logic channel_status_c80_channel_free_wd; - logic channel_status_c80_channel_free_we; - logic channel_status_c80_channel_error_qs; - logic channel_status_c80_channel_error_wd; - logic channel_status_c80_channel_error_we; - logic [29:0] channel_status_c80_field1_qs; - logic [29:0] channel_status_c80_field1_wd; - logic channel_status_c80_field1_we; - logic [31:0] reserved_2_c80_qs; - logic [31:0] reserved_2_c80_wd; - logic reserved_2_c80_we; - logic channel_flags_c80_intr_enable_qs; - logic channel_flags_c80_intr_enable_wd; - logic channel_flags_c80_intr_enable_we; - logic [30:0] channel_flags_c80_field1_qs; - logic [30:0] channel_flags_c80_field1_wd; - logic channel_flags_c80_field1_we; - logic [31:0] length_c80_qs; - logic [31:0] length_c80_wd; - logic length_c80_we; - logic [7:0] message_header_c80_message_id_qs; - logic [7:0] message_header_c80_message_id_wd; - logic message_header_c80_message_id_we; - logic [1:0] message_header_c80_message_type_qs; - logic [1:0] message_header_c80_message_type_wd; - logic message_header_c80_message_type_we; - logic [7:0] message_header_c80_protocol_id_qs; - logic [7:0] message_header_c80_protocol_id_wd; - logic message_header_c80_protocol_id_we; - logic [9:0] message_header_c80_token_qs; - logic [9:0] message_header_c80_token_wd; - logic message_header_c80_token_we; - logic [3:0] message_header_c80_field1_qs; - logic [3:0] message_header_c80_field1_wd; - logic message_header_c80_field1_we; - logic [31:0] message_payload_1_c80_qs; - logic [31:0] message_payload_1_c80_wd; - logic message_payload_1_c80_we; - logic doorbell_c80_intr_qs; - logic doorbell_c80_intr_wd; - logic doorbell_c80_intr_we; - logic [30:0] doorbell_c80_preserve_mask_qs; - logic [30:0] doorbell_c80_preserve_mask_wd; - logic doorbell_c80_preserve_mask_we; - logic completion_interrupt_c80_intr_qs; - logic completion_interrupt_c80_intr_wd; - logic completion_interrupt_c80_intr_we; - logic [30:0] completion_interrupt_c80_preserve_mask_qs; - logic [30:0] completion_interrupt_c80_preserve_mask_wd; - logic completion_interrupt_c80_preserve_mask_we; - logic [31:0] reserved_1_c81_qs; - logic [31:0] reserved_1_c81_wd; - logic reserved_1_c81_we; - logic channel_status_c81_channel_free_qs; - logic channel_status_c81_channel_free_wd; - logic channel_status_c81_channel_free_we; - logic channel_status_c81_channel_error_qs; - logic channel_status_c81_channel_error_wd; - logic channel_status_c81_channel_error_we; - logic [29:0] channel_status_c81_field1_qs; - logic [29:0] channel_status_c81_field1_wd; - logic channel_status_c81_field1_we; - logic [31:0] reserved_2_c81_qs; - logic [31:0] reserved_2_c81_wd; - logic reserved_2_c81_we; - logic channel_flags_c81_intr_enable_qs; - logic channel_flags_c81_intr_enable_wd; - logic channel_flags_c81_intr_enable_we; - logic [30:0] channel_flags_c81_field1_qs; - logic [30:0] channel_flags_c81_field1_wd; - logic channel_flags_c81_field1_we; - logic [31:0] length_c81_qs; - logic [31:0] length_c81_wd; - logic length_c81_we; - logic [7:0] message_header_c81_message_id_qs; - logic [7:0] message_header_c81_message_id_wd; - logic message_header_c81_message_id_we; - logic [1:0] message_header_c81_message_type_qs; - logic [1:0] message_header_c81_message_type_wd; - logic message_header_c81_message_type_we; - logic [7:0] message_header_c81_protocol_id_qs; - logic [7:0] message_header_c81_protocol_id_wd; - logic message_header_c81_protocol_id_we; - logic [9:0] message_header_c81_token_qs; - logic [9:0] message_header_c81_token_wd; - logic message_header_c81_token_we; - logic [3:0] message_header_c81_field1_qs; - logic [3:0] message_header_c81_field1_wd; - logic message_header_c81_field1_we; - logic [31:0] message_payload_1_c81_qs; - logic [31:0] message_payload_1_c81_wd; - logic message_payload_1_c81_we; - logic doorbell_c81_intr_qs; - logic doorbell_c81_intr_wd; - logic doorbell_c81_intr_we; - logic [30:0] doorbell_c81_preserve_mask_qs; - logic [30:0] doorbell_c81_preserve_mask_wd; - logic doorbell_c81_preserve_mask_we; - logic completion_interrupt_c81_intr_qs; - logic completion_interrupt_c81_intr_wd; - logic completion_interrupt_c81_intr_we; - logic [30:0] completion_interrupt_c81_preserve_mask_qs; - logic [30:0] completion_interrupt_c81_preserve_mask_wd; - logic completion_interrupt_c81_preserve_mask_we; - logic [31:0] reserved_1_c82_qs; - logic [31:0] reserved_1_c82_wd; - logic reserved_1_c82_we; - logic channel_status_c82_channel_free_qs; - logic channel_status_c82_channel_free_wd; - logic channel_status_c82_channel_free_we; - logic channel_status_c82_channel_error_qs; - logic channel_status_c82_channel_error_wd; - logic channel_status_c82_channel_error_we; - logic [29:0] channel_status_c82_field1_qs; - logic [29:0] channel_status_c82_field1_wd; - logic channel_status_c82_field1_we; - logic [31:0] reserved_2_c82_qs; - logic [31:0] reserved_2_c82_wd; - logic reserved_2_c82_we; - logic channel_flags_c82_intr_enable_qs; - logic channel_flags_c82_intr_enable_wd; - logic channel_flags_c82_intr_enable_we; - logic [30:0] channel_flags_c82_field1_qs; - logic [30:0] channel_flags_c82_field1_wd; - logic channel_flags_c82_field1_we; - logic [31:0] length_c82_qs; - logic [31:0] length_c82_wd; - logic length_c82_we; - logic [7:0] message_header_c82_message_id_qs; - logic [7:0] message_header_c82_message_id_wd; - logic message_header_c82_message_id_we; - logic [1:0] message_header_c82_message_type_qs; - logic [1:0] message_header_c82_message_type_wd; - logic message_header_c82_message_type_we; - logic [7:0] message_header_c82_protocol_id_qs; - logic [7:0] message_header_c82_protocol_id_wd; - logic message_header_c82_protocol_id_we; - logic [9:0] message_header_c82_token_qs; - logic [9:0] message_header_c82_token_wd; - logic message_header_c82_token_we; - logic [3:0] message_header_c82_field1_qs; - logic [3:0] message_header_c82_field1_wd; - logic message_header_c82_field1_we; - logic [31:0] message_payload_1_c82_qs; - logic [31:0] message_payload_1_c82_wd; - logic message_payload_1_c82_we; - logic doorbell_c82_intr_qs; - logic doorbell_c82_intr_wd; - logic doorbell_c82_intr_we; - logic [30:0] doorbell_c82_preserve_mask_qs; - logic [30:0] doorbell_c82_preserve_mask_wd; - logic doorbell_c82_preserve_mask_we; - logic completion_interrupt_c82_intr_qs; - logic completion_interrupt_c82_intr_wd; - logic completion_interrupt_c82_intr_we; - logic [30:0] completion_interrupt_c82_preserve_mask_qs; - logic [30:0] completion_interrupt_c82_preserve_mask_wd; - logic completion_interrupt_c82_preserve_mask_we; - logic [31:0] reserved_1_c83_qs; - logic [31:0] reserved_1_c83_wd; - logic reserved_1_c83_we; - logic channel_status_c83_channel_free_qs; - logic channel_status_c83_channel_free_wd; - logic channel_status_c83_channel_free_we; - logic channel_status_c83_channel_error_qs; - logic channel_status_c83_channel_error_wd; - logic channel_status_c83_channel_error_we; - logic [29:0] channel_status_c83_field1_qs; - logic [29:0] channel_status_c83_field1_wd; - logic channel_status_c83_field1_we; - logic [31:0] reserved_2_c83_qs; - logic [31:0] reserved_2_c83_wd; - logic reserved_2_c83_we; - logic channel_flags_c83_intr_enable_qs; - logic channel_flags_c83_intr_enable_wd; - logic channel_flags_c83_intr_enable_we; - logic [30:0] channel_flags_c83_field1_qs; - logic [30:0] channel_flags_c83_field1_wd; - logic channel_flags_c83_field1_we; - logic [31:0] length_c83_qs; - logic [31:0] length_c83_wd; - logic length_c83_we; - logic [7:0] message_header_c83_message_id_qs; - logic [7:0] message_header_c83_message_id_wd; - logic message_header_c83_message_id_we; - logic [1:0] message_header_c83_message_type_qs; - logic [1:0] message_header_c83_message_type_wd; - logic message_header_c83_message_type_we; - logic [7:0] message_header_c83_protocol_id_qs; - logic [7:0] message_header_c83_protocol_id_wd; - logic message_header_c83_protocol_id_we; - logic [9:0] message_header_c83_token_qs; - logic [9:0] message_header_c83_token_wd; - logic message_header_c83_token_we; - logic [3:0] message_header_c83_field1_qs; - logic [3:0] message_header_c83_field1_wd; - logic message_header_c83_field1_we; - logic [31:0] message_payload_1_c83_qs; - logic [31:0] message_payload_1_c83_wd; - logic message_payload_1_c83_we; - logic doorbell_c83_intr_qs; - logic doorbell_c83_intr_wd; - logic doorbell_c83_intr_we; - logic [30:0] doorbell_c83_preserve_mask_qs; - logic [30:0] doorbell_c83_preserve_mask_wd; - logic doorbell_c83_preserve_mask_we; - logic completion_interrupt_c83_intr_qs; - logic completion_interrupt_c83_intr_wd; - logic completion_interrupt_c83_intr_we; - logic [30:0] completion_interrupt_c83_preserve_mask_qs; - logic [30:0] completion_interrupt_c83_preserve_mask_wd; - logic completion_interrupt_c83_preserve_mask_we; - logic [31:0] reserved_1_c84_qs; - logic [31:0] reserved_1_c84_wd; - logic reserved_1_c84_we; - logic channel_status_c84_channel_free_qs; - logic channel_status_c84_channel_free_wd; - logic channel_status_c84_channel_free_we; - logic channel_status_c84_channel_error_qs; - logic channel_status_c84_channel_error_wd; - logic channel_status_c84_channel_error_we; - logic [29:0] channel_status_c84_field1_qs; - logic [29:0] channel_status_c84_field1_wd; - logic channel_status_c84_field1_we; - logic [31:0] reserved_2_c84_qs; - logic [31:0] reserved_2_c84_wd; - logic reserved_2_c84_we; - logic channel_flags_c84_intr_enable_qs; - logic channel_flags_c84_intr_enable_wd; - logic channel_flags_c84_intr_enable_we; - logic [30:0] channel_flags_c84_field1_qs; - logic [30:0] channel_flags_c84_field1_wd; - logic channel_flags_c84_field1_we; - logic [31:0] length_c84_qs; - logic [31:0] length_c84_wd; - logic length_c84_we; - logic [7:0] message_header_c84_message_id_qs; - logic [7:0] message_header_c84_message_id_wd; - logic message_header_c84_message_id_we; - logic [1:0] message_header_c84_message_type_qs; - logic [1:0] message_header_c84_message_type_wd; - logic message_header_c84_message_type_we; - logic [7:0] message_header_c84_protocol_id_qs; - logic [7:0] message_header_c84_protocol_id_wd; - logic message_header_c84_protocol_id_we; - logic [9:0] message_header_c84_token_qs; - logic [9:0] message_header_c84_token_wd; - logic message_header_c84_token_we; - logic [3:0] message_header_c84_field1_qs; - logic [3:0] message_header_c84_field1_wd; - logic message_header_c84_field1_we; - logic [31:0] message_payload_1_c84_qs; - logic [31:0] message_payload_1_c84_wd; - logic message_payload_1_c84_we; - logic doorbell_c84_intr_qs; - logic doorbell_c84_intr_wd; - logic doorbell_c84_intr_we; - logic [30:0] doorbell_c84_preserve_mask_qs; - logic [30:0] doorbell_c84_preserve_mask_wd; - logic doorbell_c84_preserve_mask_we; - logic completion_interrupt_c84_intr_qs; - logic completion_interrupt_c84_intr_wd; - logic completion_interrupt_c84_intr_we; - logic [30:0] completion_interrupt_c84_preserve_mask_qs; - logic [30:0] completion_interrupt_c84_preserve_mask_wd; - logic completion_interrupt_c84_preserve_mask_we; - logic [31:0] reserved_1_c85_qs; - logic [31:0] reserved_1_c85_wd; - logic reserved_1_c85_we; - logic channel_status_c85_channel_free_qs; - logic channel_status_c85_channel_free_wd; - logic channel_status_c85_channel_free_we; - logic channel_status_c85_channel_error_qs; - logic channel_status_c85_channel_error_wd; - logic channel_status_c85_channel_error_we; - logic [29:0] channel_status_c85_field1_qs; - logic [29:0] channel_status_c85_field1_wd; - logic channel_status_c85_field1_we; - logic [31:0] reserved_2_c85_qs; - logic [31:0] reserved_2_c85_wd; - logic reserved_2_c85_we; - logic channel_flags_c85_intr_enable_qs; - logic channel_flags_c85_intr_enable_wd; - logic channel_flags_c85_intr_enable_we; - logic [30:0] channel_flags_c85_field1_qs; - logic [30:0] channel_flags_c85_field1_wd; - logic channel_flags_c85_field1_we; - logic [31:0] length_c85_qs; - logic [31:0] length_c85_wd; - logic length_c85_we; - logic [7:0] message_header_c85_message_id_qs; - logic [7:0] message_header_c85_message_id_wd; - logic message_header_c85_message_id_we; - logic [1:0] message_header_c85_message_type_qs; - logic [1:0] message_header_c85_message_type_wd; - logic message_header_c85_message_type_we; - logic [7:0] message_header_c85_protocol_id_qs; - logic [7:0] message_header_c85_protocol_id_wd; - logic message_header_c85_protocol_id_we; - logic [9:0] message_header_c85_token_qs; - logic [9:0] message_header_c85_token_wd; - logic message_header_c85_token_we; - logic [3:0] message_header_c85_field1_qs; - logic [3:0] message_header_c85_field1_wd; - logic message_header_c85_field1_we; - logic [31:0] message_payload_1_c85_qs; - logic [31:0] message_payload_1_c85_wd; - logic message_payload_1_c85_we; - logic doorbell_c85_intr_qs; - logic doorbell_c85_intr_wd; - logic doorbell_c85_intr_we; - logic [30:0] doorbell_c85_preserve_mask_qs; - logic [30:0] doorbell_c85_preserve_mask_wd; - logic doorbell_c85_preserve_mask_we; - logic completion_interrupt_c85_intr_qs; - logic completion_interrupt_c85_intr_wd; - logic completion_interrupt_c85_intr_we; - logic [30:0] completion_interrupt_c85_preserve_mask_qs; - logic [30:0] completion_interrupt_c85_preserve_mask_wd; - logic completion_interrupt_c85_preserve_mask_we; - logic [31:0] reserved_1_c86_qs; - logic [31:0] reserved_1_c86_wd; - logic reserved_1_c86_we; - logic channel_status_c86_channel_free_qs; - logic channel_status_c86_channel_free_wd; - logic channel_status_c86_channel_free_we; - logic channel_status_c86_channel_error_qs; - logic channel_status_c86_channel_error_wd; - logic channel_status_c86_channel_error_we; - logic [29:0] channel_status_c86_field1_qs; - logic [29:0] channel_status_c86_field1_wd; - logic channel_status_c86_field1_we; - logic [31:0] reserved_2_c86_qs; - logic [31:0] reserved_2_c86_wd; - logic reserved_2_c86_we; - logic channel_flags_c86_intr_enable_qs; - logic channel_flags_c86_intr_enable_wd; - logic channel_flags_c86_intr_enable_we; - logic [30:0] channel_flags_c86_field1_qs; - logic [30:0] channel_flags_c86_field1_wd; - logic channel_flags_c86_field1_we; - logic [31:0] length_c86_qs; - logic [31:0] length_c86_wd; - logic length_c86_we; - logic [7:0] message_header_c86_message_id_qs; - logic [7:0] message_header_c86_message_id_wd; - logic message_header_c86_message_id_we; - logic [1:0] message_header_c86_message_type_qs; - logic [1:0] message_header_c86_message_type_wd; - logic message_header_c86_message_type_we; - logic [7:0] message_header_c86_protocol_id_qs; - logic [7:0] message_header_c86_protocol_id_wd; - logic message_header_c86_protocol_id_we; - logic [9:0] message_header_c86_token_qs; - logic [9:0] message_header_c86_token_wd; - logic message_header_c86_token_we; - logic [3:0] message_header_c86_field1_qs; - logic [3:0] message_header_c86_field1_wd; - logic message_header_c86_field1_we; - logic [31:0] message_payload_1_c86_qs; - logic [31:0] message_payload_1_c86_wd; - logic message_payload_1_c86_we; - logic doorbell_c86_intr_qs; - logic doorbell_c86_intr_wd; - logic doorbell_c86_intr_we; - logic [30:0] doorbell_c86_preserve_mask_qs; - logic [30:0] doorbell_c86_preserve_mask_wd; - logic doorbell_c86_preserve_mask_we; - logic completion_interrupt_c86_intr_qs; - logic completion_interrupt_c86_intr_wd; - logic completion_interrupt_c86_intr_we; - logic [30:0] completion_interrupt_c86_preserve_mask_qs; - logic [30:0] completion_interrupt_c86_preserve_mask_wd; - logic completion_interrupt_c86_preserve_mask_we; - logic [31:0] reserved_1_c87_qs; - logic [31:0] reserved_1_c87_wd; - logic reserved_1_c87_we; - logic channel_status_c87_channel_free_qs; - logic channel_status_c87_channel_free_wd; - logic channel_status_c87_channel_free_we; - logic channel_status_c87_channel_error_qs; - logic channel_status_c87_channel_error_wd; - logic channel_status_c87_channel_error_we; - logic [29:0] channel_status_c87_field1_qs; - logic [29:0] channel_status_c87_field1_wd; - logic channel_status_c87_field1_we; - logic [31:0] reserved_2_c87_qs; - logic [31:0] reserved_2_c87_wd; - logic reserved_2_c87_we; - logic channel_flags_c87_intr_enable_qs; - logic channel_flags_c87_intr_enable_wd; - logic channel_flags_c87_intr_enable_we; - logic [30:0] channel_flags_c87_field1_qs; - logic [30:0] channel_flags_c87_field1_wd; - logic channel_flags_c87_field1_we; - logic [31:0] length_c87_qs; - logic [31:0] length_c87_wd; - logic length_c87_we; - logic [7:0] message_header_c87_message_id_qs; - logic [7:0] message_header_c87_message_id_wd; - logic message_header_c87_message_id_we; - logic [1:0] message_header_c87_message_type_qs; - logic [1:0] message_header_c87_message_type_wd; - logic message_header_c87_message_type_we; - logic [7:0] message_header_c87_protocol_id_qs; - logic [7:0] message_header_c87_protocol_id_wd; - logic message_header_c87_protocol_id_we; - logic [9:0] message_header_c87_token_qs; - logic [9:0] message_header_c87_token_wd; - logic message_header_c87_token_we; - logic [3:0] message_header_c87_field1_qs; - logic [3:0] message_header_c87_field1_wd; - logic message_header_c87_field1_we; - logic [31:0] message_payload_1_c87_qs; - logic [31:0] message_payload_1_c87_wd; - logic message_payload_1_c87_we; - logic doorbell_c87_intr_qs; - logic doorbell_c87_intr_wd; - logic doorbell_c87_intr_we; - logic [30:0] doorbell_c87_preserve_mask_qs; - logic [30:0] doorbell_c87_preserve_mask_wd; - logic doorbell_c87_preserve_mask_we; - logic completion_interrupt_c87_intr_qs; - logic completion_interrupt_c87_intr_wd; - logic completion_interrupt_c87_intr_we; - logic [30:0] completion_interrupt_c87_preserve_mask_qs; - logic [30:0] completion_interrupt_c87_preserve_mask_wd; - logic completion_interrupt_c87_preserve_mask_we; - logic [31:0] reserved_1_c88_qs; - logic [31:0] reserved_1_c88_wd; - logic reserved_1_c88_we; - logic channel_status_c88_channel_free_qs; - logic channel_status_c88_channel_free_wd; - logic channel_status_c88_channel_free_we; - logic channel_status_c88_channel_error_qs; - logic channel_status_c88_channel_error_wd; - logic channel_status_c88_channel_error_we; - logic [29:0] channel_status_c88_field1_qs; - logic [29:0] channel_status_c88_field1_wd; - logic channel_status_c88_field1_we; - logic [31:0] reserved_2_c88_qs; - logic [31:0] reserved_2_c88_wd; - logic reserved_2_c88_we; - logic channel_flags_c88_intr_enable_qs; - logic channel_flags_c88_intr_enable_wd; - logic channel_flags_c88_intr_enable_we; - logic [30:0] channel_flags_c88_field1_qs; - logic [30:0] channel_flags_c88_field1_wd; - logic channel_flags_c88_field1_we; - logic [31:0] length_c88_qs; - logic [31:0] length_c88_wd; - logic length_c88_we; - logic [7:0] message_header_c88_message_id_qs; - logic [7:0] message_header_c88_message_id_wd; - logic message_header_c88_message_id_we; - logic [1:0] message_header_c88_message_type_qs; - logic [1:0] message_header_c88_message_type_wd; - logic message_header_c88_message_type_we; - logic [7:0] message_header_c88_protocol_id_qs; - logic [7:0] message_header_c88_protocol_id_wd; - logic message_header_c88_protocol_id_we; - logic [9:0] message_header_c88_token_qs; - logic [9:0] message_header_c88_token_wd; - logic message_header_c88_token_we; - logic [3:0] message_header_c88_field1_qs; - logic [3:0] message_header_c88_field1_wd; - logic message_header_c88_field1_we; - logic [31:0] message_payload_1_c88_qs; - logic [31:0] message_payload_1_c88_wd; - logic message_payload_1_c88_we; - logic doorbell_c88_intr_qs; - logic doorbell_c88_intr_wd; - logic doorbell_c88_intr_we; - logic [30:0] doorbell_c88_preserve_mask_qs; - logic [30:0] doorbell_c88_preserve_mask_wd; - logic doorbell_c88_preserve_mask_we; - logic completion_interrupt_c88_intr_qs; - logic completion_interrupt_c88_intr_wd; - logic completion_interrupt_c88_intr_we; - logic [30:0] completion_interrupt_c88_preserve_mask_qs; - logic [30:0] completion_interrupt_c88_preserve_mask_wd; - logic completion_interrupt_c88_preserve_mask_we; - logic [31:0] reserved_1_c89_qs; - logic [31:0] reserved_1_c89_wd; - logic reserved_1_c89_we; - logic channel_status_c89_channel_free_qs; - logic channel_status_c89_channel_free_wd; - logic channel_status_c89_channel_free_we; - logic channel_status_c89_channel_error_qs; - logic channel_status_c89_channel_error_wd; - logic channel_status_c89_channel_error_we; - logic [29:0] channel_status_c89_field1_qs; - logic [29:0] channel_status_c89_field1_wd; - logic channel_status_c89_field1_we; - logic [31:0] reserved_2_c89_qs; - logic [31:0] reserved_2_c89_wd; - logic reserved_2_c89_we; - logic channel_flags_c89_intr_enable_qs; - logic channel_flags_c89_intr_enable_wd; - logic channel_flags_c89_intr_enable_we; - logic [30:0] channel_flags_c89_field1_qs; - logic [30:0] channel_flags_c89_field1_wd; - logic channel_flags_c89_field1_we; - logic [31:0] length_c89_qs; - logic [31:0] length_c89_wd; - logic length_c89_we; - logic [7:0] message_header_c89_message_id_qs; - logic [7:0] message_header_c89_message_id_wd; - logic message_header_c89_message_id_we; - logic [1:0] message_header_c89_message_type_qs; - logic [1:0] message_header_c89_message_type_wd; - logic message_header_c89_message_type_we; - logic [7:0] message_header_c89_protocol_id_qs; - logic [7:0] message_header_c89_protocol_id_wd; - logic message_header_c89_protocol_id_we; - logic [9:0] message_header_c89_token_qs; - logic [9:0] message_header_c89_token_wd; - logic message_header_c89_token_we; - logic [3:0] message_header_c89_field1_qs; - logic [3:0] message_header_c89_field1_wd; - logic message_header_c89_field1_we; - logic [31:0] message_payload_1_c89_qs; - logic [31:0] message_payload_1_c89_wd; - logic message_payload_1_c89_we; - logic doorbell_c89_intr_qs; - logic doorbell_c89_intr_wd; - logic doorbell_c89_intr_we; - logic [30:0] doorbell_c89_preserve_mask_qs; - logic [30:0] doorbell_c89_preserve_mask_wd; - logic doorbell_c89_preserve_mask_we; - logic completion_interrupt_c89_intr_qs; - logic completion_interrupt_c89_intr_wd; - logic completion_interrupt_c89_intr_we; - logic [30:0] completion_interrupt_c89_preserve_mask_qs; - logic [30:0] completion_interrupt_c89_preserve_mask_wd; - logic completion_interrupt_c89_preserve_mask_we; - logic [31:0] reserved_1_c90_qs; - logic [31:0] reserved_1_c90_wd; - logic reserved_1_c90_we; - logic channel_status_c90_channel_free_qs; - logic channel_status_c90_channel_free_wd; - logic channel_status_c90_channel_free_we; - logic channel_status_c90_channel_error_qs; - logic channel_status_c90_channel_error_wd; - logic channel_status_c90_channel_error_we; - logic [29:0] channel_status_c90_field1_qs; - logic [29:0] channel_status_c90_field1_wd; - logic channel_status_c90_field1_we; - logic [31:0] reserved_2_c90_qs; - logic [31:0] reserved_2_c90_wd; - logic reserved_2_c90_we; - logic channel_flags_c90_intr_enable_qs; - logic channel_flags_c90_intr_enable_wd; - logic channel_flags_c90_intr_enable_we; - logic [30:0] channel_flags_c90_field1_qs; - logic [30:0] channel_flags_c90_field1_wd; - logic channel_flags_c90_field1_we; - logic [31:0] length_c90_qs; - logic [31:0] length_c90_wd; - logic length_c90_we; - logic [7:0] message_header_c90_message_id_qs; - logic [7:0] message_header_c90_message_id_wd; - logic message_header_c90_message_id_we; - logic [1:0] message_header_c90_message_type_qs; - logic [1:0] message_header_c90_message_type_wd; - logic message_header_c90_message_type_we; - logic [7:0] message_header_c90_protocol_id_qs; - logic [7:0] message_header_c90_protocol_id_wd; - logic message_header_c90_protocol_id_we; - logic [9:0] message_header_c90_token_qs; - logic [9:0] message_header_c90_token_wd; - logic message_header_c90_token_we; - logic [3:0] message_header_c90_field1_qs; - logic [3:0] message_header_c90_field1_wd; - logic message_header_c90_field1_we; - logic [31:0] message_payload_1_c90_qs; - logic [31:0] message_payload_1_c90_wd; - logic message_payload_1_c90_we; - logic doorbell_c90_intr_qs; - logic doorbell_c90_intr_wd; - logic doorbell_c90_intr_we; - logic [30:0] doorbell_c90_preserve_mask_qs; - logic [30:0] doorbell_c90_preserve_mask_wd; - logic doorbell_c90_preserve_mask_we; - logic completion_interrupt_c90_intr_qs; - logic completion_interrupt_c90_intr_wd; - logic completion_interrupt_c90_intr_we; - logic [30:0] completion_interrupt_c90_preserve_mask_qs; - logic [30:0] completion_interrupt_c90_preserve_mask_wd; - logic completion_interrupt_c90_preserve_mask_we; - logic [31:0] reserved_1_c91_qs; - logic [31:0] reserved_1_c91_wd; - logic reserved_1_c91_we; - logic channel_status_c91_channel_free_qs; - logic channel_status_c91_channel_free_wd; - logic channel_status_c91_channel_free_we; - logic channel_status_c91_channel_error_qs; - logic channel_status_c91_channel_error_wd; - logic channel_status_c91_channel_error_we; - logic [29:0] channel_status_c91_field1_qs; - logic [29:0] channel_status_c91_field1_wd; - logic channel_status_c91_field1_we; - logic [31:0] reserved_2_c91_qs; - logic [31:0] reserved_2_c91_wd; - logic reserved_2_c91_we; - logic channel_flags_c91_intr_enable_qs; - logic channel_flags_c91_intr_enable_wd; - logic channel_flags_c91_intr_enable_we; - logic [30:0] channel_flags_c91_field1_qs; - logic [30:0] channel_flags_c91_field1_wd; - logic channel_flags_c91_field1_we; - logic [31:0] length_c91_qs; - logic [31:0] length_c91_wd; - logic length_c91_we; - logic [7:0] message_header_c91_message_id_qs; - logic [7:0] message_header_c91_message_id_wd; - logic message_header_c91_message_id_we; - logic [1:0] message_header_c91_message_type_qs; - logic [1:0] message_header_c91_message_type_wd; - logic message_header_c91_message_type_we; - logic [7:0] message_header_c91_protocol_id_qs; - logic [7:0] message_header_c91_protocol_id_wd; - logic message_header_c91_protocol_id_we; - logic [9:0] message_header_c91_token_qs; - logic [9:0] message_header_c91_token_wd; - logic message_header_c91_token_we; - logic [3:0] message_header_c91_field1_qs; - logic [3:0] message_header_c91_field1_wd; - logic message_header_c91_field1_we; - logic [31:0] message_payload_1_c91_qs; - logic [31:0] message_payload_1_c91_wd; - logic message_payload_1_c91_we; - logic doorbell_c91_intr_qs; - logic doorbell_c91_intr_wd; - logic doorbell_c91_intr_we; - logic [30:0] doorbell_c91_preserve_mask_qs; - logic [30:0] doorbell_c91_preserve_mask_wd; - logic doorbell_c91_preserve_mask_we; - logic completion_interrupt_c91_intr_qs; - logic completion_interrupt_c91_intr_wd; - logic completion_interrupt_c91_intr_we; - logic [30:0] completion_interrupt_c91_preserve_mask_qs; - logic [30:0] completion_interrupt_c91_preserve_mask_wd; - logic completion_interrupt_c91_preserve_mask_we; - logic [31:0] reserved_1_c92_qs; - logic [31:0] reserved_1_c92_wd; - logic reserved_1_c92_we; - logic channel_status_c92_channel_free_qs; - logic channel_status_c92_channel_free_wd; - logic channel_status_c92_channel_free_we; - logic channel_status_c92_channel_error_qs; - logic channel_status_c92_channel_error_wd; - logic channel_status_c92_channel_error_we; - logic [29:0] channel_status_c92_field1_qs; - logic [29:0] channel_status_c92_field1_wd; - logic channel_status_c92_field1_we; - logic [31:0] reserved_2_c92_qs; - logic [31:0] reserved_2_c92_wd; - logic reserved_2_c92_we; - logic channel_flags_c92_intr_enable_qs; - logic channel_flags_c92_intr_enable_wd; - logic channel_flags_c92_intr_enable_we; - logic [30:0] channel_flags_c92_field1_qs; - logic [30:0] channel_flags_c92_field1_wd; - logic channel_flags_c92_field1_we; - logic [31:0] length_c92_qs; - logic [31:0] length_c92_wd; - logic length_c92_we; - logic [7:0] message_header_c92_message_id_qs; - logic [7:0] message_header_c92_message_id_wd; - logic message_header_c92_message_id_we; - logic [1:0] message_header_c92_message_type_qs; - logic [1:0] message_header_c92_message_type_wd; - logic message_header_c92_message_type_we; - logic [7:0] message_header_c92_protocol_id_qs; - logic [7:0] message_header_c92_protocol_id_wd; - logic message_header_c92_protocol_id_we; - logic [9:0] message_header_c92_token_qs; - logic [9:0] message_header_c92_token_wd; - logic message_header_c92_token_we; - logic [3:0] message_header_c92_field1_qs; - logic [3:0] message_header_c92_field1_wd; - logic message_header_c92_field1_we; - logic [31:0] message_payload_1_c92_qs; - logic [31:0] message_payload_1_c92_wd; - logic message_payload_1_c92_we; - logic doorbell_c92_intr_qs; - logic doorbell_c92_intr_wd; - logic doorbell_c92_intr_we; - logic [30:0] doorbell_c92_preserve_mask_qs; - logic [30:0] doorbell_c92_preserve_mask_wd; - logic doorbell_c92_preserve_mask_we; - logic completion_interrupt_c92_intr_qs; - logic completion_interrupt_c92_intr_wd; - logic completion_interrupt_c92_intr_we; - logic [30:0] completion_interrupt_c92_preserve_mask_qs; - logic [30:0] completion_interrupt_c92_preserve_mask_wd; - logic completion_interrupt_c92_preserve_mask_we; - logic [31:0] reserved_1_c93_qs; - logic [31:0] reserved_1_c93_wd; - logic reserved_1_c93_we; - logic channel_status_c93_channel_free_qs; - logic channel_status_c93_channel_free_wd; - logic channel_status_c93_channel_free_we; - logic channel_status_c93_channel_error_qs; - logic channel_status_c93_channel_error_wd; - logic channel_status_c93_channel_error_we; - logic [29:0] channel_status_c93_field1_qs; - logic [29:0] channel_status_c93_field1_wd; - logic channel_status_c93_field1_we; - logic [31:0] reserved_2_c93_qs; - logic [31:0] reserved_2_c93_wd; - logic reserved_2_c93_we; - logic channel_flags_c93_intr_enable_qs; - logic channel_flags_c93_intr_enable_wd; - logic channel_flags_c93_intr_enable_we; - logic [30:0] channel_flags_c93_field1_qs; - logic [30:0] channel_flags_c93_field1_wd; - logic channel_flags_c93_field1_we; - logic [31:0] length_c93_qs; - logic [31:0] length_c93_wd; - logic length_c93_we; - logic [7:0] message_header_c93_message_id_qs; - logic [7:0] message_header_c93_message_id_wd; - logic message_header_c93_message_id_we; - logic [1:0] message_header_c93_message_type_qs; - logic [1:0] message_header_c93_message_type_wd; - logic message_header_c93_message_type_we; - logic [7:0] message_header_c93_protocol_id_qs; - logic [7:0] message_header_c93_protocol_id_wd; - logic message_header_c93_protocol_id_we; - logic [9:0] message_header_c93_token_qs; - logic [9:0] message_header_c93_token_wd; - logic message_header_c93_token_we; - logic [3:0] message_header_c93_field1_qs; - logic [3:0] message_header_c93_field1_wd; - logic message_header_c93_field1_we; - logic [31:0] message_payload_1_c93_qs; - logic [31:0] message_payload_1_c93_wd; - logic message_payload_1_c93_we; - logic doorbell_c93_intr_qs; - logic doorbell_c93_intr_wd; - logic doorbell_c93_intr_we; - logic [30:0] doorbell_c93_preserve_mask_qs; - logic [30:0] doorbell_c93_preserve_mask_wd; - logic doorbell_c93_preserve_mask_we; - logic completion_interrupt_c93_intr_qs; - logic completion_interrupt_c93_intr_wd; - logic completion_interrupt_c93_intr_we; - logic [30:0] completion_interrupt_c93_preserve_mask_qs; - logic [30:0] completion_interrupt_c93_preserve_mask_wd; - logic completion_interrupt_c93_preserve_mask_we; - logic [31:0] reserved_1_c94_qs; - logic [31:0] reserved_1_c94_wd; - logic reserved_1_c94_we; - logic channel_status_c94_channel_free_qs; - logic channel_status_c94_channel_free_wd; - logic channel_status_c94_channel_free_we; - logic channel_status_c94_channel_error_qs; - logic channel_status_c94_channel_error_wd; - logic channel_status_c94_channel_error_we; - logic [29:0] channel_status_c94_field1_qs; - logic [29:0] channel_status_c94_field1_wd; - logic channel_status_c94_field1_we; - logic [31:0] reserved_2_c94_qs; - logic [31:0] reserved_2_c94_wd; - logic reserved_2_c94_we; - logic channel_flags_c94_intr_enable_qs; - logic channel_flags_c94_intr_enable_wd; - logic channel_flags_c94_intr_enable_we; - logic [30:0] channel_flags_c94_field1_qs; - logic [30:0] channel_flags_c94_field1_wd; - logic channel_flags_c94_field1_we; - logic [31:0] length_c94_qs; - logic [31:0] length_c94_wd; - logic length_c94_we; - logic [7:0] message_header_c94_message_id_qs; - logic [7:0] message_header_c94_message_id_wd; - logic message_header_c94_message_id_we; - logic [1:0] message_header_c94_message_type_qs; - logic [1:0] message_header_c94_message_type_wd; - logic message_header_c94_message_type_we; - logic [7:0] message_header_c94_protocol_id_qs; - logic [7:0] message_header_c94_protocol_id_wd; - logic message_header_c94_protocol_id_we; - logic [9:0] message_header_c94_token_qs; - logic [9:0] message_header_c94_token_wd; - logic message_header_c94_token_we; - logic [3:0] message_header_c94_field1_qs; - logic [3:0] message_header_c94_field1_wd; - logic message_header_c94_field1_we; - logic [31:0] message_payload_1_c94_qs; - logic [31:0] message_payload_1_c94_wd; - logic message_payload_1_c94_we; - logic doorbell_c94_intr_qs; - logic doorbell_c94_intr_wd; - logic doorbell_c94_intr_we; - logic [30:0] doorbell_c94_preserve_mask_qs; - logic [30:0] doorbell_c94_preserve_mask_wd; - logic doorbell_c94_preserve_mask_we; - logic completion_interrupt_c94_intr_qs; - logic completion_interrupt_c94_intr_wd; - logic completion_interrupt_c94_intr_we; - logic [30:0] completion_interrupt_c94_preserve_mask_qs; - logic [30:0] completion_interrupt_c94_preserve_mask_wd; - logic completion_interrupt_c94_preserve_mask_we; - logic [31:0] reserved_1_c95_qs; - logic [31:0] reserved_1_c95_wd; - logic reserved_1_c95_we; - logic channel_status_c95_channel_free_qs; - logic channel_status_c95_channel_free_wd; - logic channel_status_c95_channel_free_we; - logic channel_status_c95_channel_error_qs; - logic channel_status_c95_channel_error_wd; - logic channel_status_c95_channel_error_we; - logic [29:0] channel_status_c95_field1_qs; - logic [29:0] channel_status_c95_field1_wd; - logic channel_status_c95_field1_we; - logic [31:0] reserved_2_c95_qs; - logic [31:0] reserved_2_c95_wd; - logic reserved_2_c95_we; - logic channel_flags_c95_intr_enable_qs; - logic channel_flags_c95_intr_enable_wd; - logic channel_flags_c95_intr_enable_we; - logic [30:0] channel_flags_c95_field1_qs; - logic [30:0] channel_flags_c95_field1_wd; - logic channel_flags_c95_field1_we; - logic [31:0] length_c95_qs; - logic [31:0] length_c95_wd; - logic length_c95_we; - logic [7:0] message_header_c95_message_id_qs; - logic [7:0] message_header_c95_message_id_wd; - logic message_header_c95_message_id_we; - logic [1:0] message_header_c95_message_type_qs; - logic [1:0] message_header_c95_message_type_wd; - logic message_header_c95_message_type_we; - logic [7:0] message_header_c95_protocol_id_qs; - logic [7:0] message_header_c95_protocol_id_wd; - logic message_header_c95_protocol_id_we; - logic [9:0] message_header_c95_token_qs; - logic [9:0] message_header_c95_token_wd; - logic message_header_c95_token_we; - logic [3:0] message_header_c95_field1_qs; - logic [3:0] message_header_c95_field1_wd; - logic message_header_c95_field1_we; - logic [31:0] message_payload_1_c95_qs; - logic [31:0] message_payload_1_c95_wd; - logic message_payload_1_c95_we; - logic doorbell_c95_intr_qs; - logic doorbell_c95_intr_wd; - logic doorbell_c95_intr_we; - logic [30:0] doorbell_c95_preserve_mask_qs; - logic [30:0] doorbell_c95_preserve_mask_wd; - logic doorbell_c95_preserve_mask_we; - logic completion_interrupt_c95_intr_qs; - logic completion_interrupt_c95_intr_wd; - logic completion_interrupt_c95_intr_we; - logic [30:0] completion_interrupt_c95_preserve_mask_qs; - logic [30:0] completion_interrupt_c95_preserve_mask_wd; - logic completion_interrupt_c95_preserve_mask_we; - logic [31:0] reserved_1_c96_qs; - logic [31:0] reserved_1_c96_wd; - logic reserved_1_c96_we; - logic channel_status_c96_channel_free_qs; - logic channel_status_c96_channel_free_wd; - logic channel_status_c96_channel_free_we; - logic channel_status_c96_channel_error_qs; - logic channel_status_c96_channel_error_wd; - logic channel_status_c96_channel_error_we; - logic [29:0] channel_status_c96_field1_qs; - logic [29:0] channel_status_c96_field1_wd; - logic channel_status_c96_field1_we; - logic [31:0] reserved_2_c96_qs; - logic [31:0] reserved_2_c96_wd; - logic reserved_2_c96_we; - logic channel_flags_c96_intr_enable_qs; - logic channel_flags_c96_intr_enable_wd; - logic channel_flags_c96_intr_enable_we; - logic [30:0] channel_flags_c96_field1_qs; - logic [30:0] channel_flags_c96_field1_wd; - logic channel_flags_c96_field1_we; - logic [31:0] length_c96_qs; - logic [31:0] length_c96_wd; - logic length_c96_we; - logic [7:0] message_header_c96_message_id_qs; - logic [7:0] message_header_c96_message_id_wd; - logic message_header_c96_message_id_we; - logic [1:0] message_header_c96_message_type_qs; - logic [1:0] message_header_c96_message_type_wd; - logic message_header_c96_message_type_we; - logic [7:0] message_header_c96_protocol_id_qs; - logic [7:0] message_header_c96_protocol_id_wd; - logic message_header_c96_protocol_id_we; - logic [9:0] message_header_c96_token_qs; - logic [9:0] message_header_c96_token_wd; - logic message_header_c96_token_we; - logic [3:0] message_header_c96_field1_qs; - logic [3:0] message_header_c96_field1_wd; - logic message_header_c96_field1_we; - logic [31:0] message_payload_1_c96_qs; - logic [31:0] message_payload_1_c96_wd; - logic message_payload_1_c96_we; - logic doorbell_c96_intr_qs; - logic doorbell_c96_intr_wd; - logic doorbell_c96_intr_we; - logic [30:0] doorbell_c96_preserve_mask_qs; - logic [30:0] doorbell_c96_preserve_mask_wd; - logic doorbell_c96_preserve_mask_we; - logic completion_interrupt_c96_intr_qs; - logic completion_interrupt_c96_intr_wd; - logic completion_interrupt_c96_intr_we; - logic [30:0] completion_interrupt_c96_preserve_mask_qs; - logic [30:0] completion_interrupt_c96_preserve_mask_wd; - logic completion_interrupt_c96_preserve_mask_we; - logic [31:0] reserved_1_c97_qs; - logic [31:0] reserved_1_c97_wd; - logic reserved_1_c97_we; - logic channel_status_c97_channel_free_qs; - logic channel_status_c97_channel_free_wd; - logic channel_status_c97_channel_free_we; - logic channel_status_c97_channel_error_qs; - logic channel_status_c97_channel_error_wd; - logic channel_status_c97_channel_error_we; - logic [29:0] channel_status_c97_field1_qs; - logic [29:0] channel_status_c97_field1_wd; - logic channel_status_c97_field1_we; - logic [31:0] reserved_2_c97_qs; - logic [31:0] reserved_2_c97_wd; - logic reserved_2_c97_we; - logic channel_flags_c97_intr_enable_qs; - logic channel_flags_c97_intr_enable_wd; - logic channel_flags_c97_intr_enable_we; - logic [30:0] channel_flags_c97_field1_qs; - logic [30:0] channel_flags_c97_field1_wd; - logic channel_flags_c97_field1_we; - logic [31:0] length_c97_qs; - logic [31:0] length_c97_wd; - logic length_c97_we; - logic [7:0] message_header_c97_message_id_qs; - logic [7:0] message_header_c97_message_id_wd; - logic message_header_c97_message_id_we; - logic [1:0] message_header_c97_message_type_qs; - logic [1:0] message_header_c97_message_type_wd; - logic message_header_c97_message_type_we; - logic [7:0] message_header_c97_protocol_id_qs; - logic [7:0] message_header_c97_protocol_id_wd; - logic message_header_c97_protocol_id_we; - logic [9:0] message_header_c97_token_qs; - logic [9:0] message_header_c97_token_wd; - logic message_header_c97_token_we; - logic [3:0] message_header_c97_field1_qs; - logic [3:0] message_header_c97_field1_wd; - logic message_header_c97_field1_we; - logic [31:0] message_payload_1_c97_qs; - logic [31:0] message_payload_1_c97_wd; - logic message_payload_1_c97_we; - logic doorbell_c97_intr_qs; - logic doorbell_c97_intr_wd; - logic doorbell_c97_intr_we; - logic [30:0] doorbell_c97_preserve_mask_qs; - logic [30:0] doorbell_c97_preserve_mask_wd; - logic doorbell_c97_preserve_mask_we; - logic completion_interrupt_c97_intr_qs; - logic completion_interrupt_c97_intr_wd; - logic completion_interrupt_c97_intr_we; - logic [30:0] completion_interrupt_c97_preserve_mask_qs; - logic [30:0] completion_interrupt_c97_preserve_mask_wd; - logic completion_interrupt_c97_preserve_mask_we; - logic [31:0] reserved_1_c98_qs; - logic [31:0] reserved_1_c98_wd; - logic reserved_1_c98_we; - logic channel_status_c98_channel_free_qs; - logic channel_status_c98_channel_free_wd; - logic channel_status_c98_channel_free_we; - logic channel_status_c98_channel_error_qs; - logic channel_status_c98_channel_error_wd; - logic channel_status_c98_channel_error_we; - logic [29:0] channel_status_c98_field1_qs; - logic [29:0] channel_status_c98_field1_wd; - logic channel_status_c98_field1_we; - logic [31:0] reserved_2_c98_qs; - logic [31:0] reserved_2_c98_wd; - logic reserved_2_c98_we; - logic channel_flags_c98_intr_enable_qs; - logic channel_flags_c98_intr_enable_wd; - logic channel_flags_c98_intr_enable_we; - logic [30:0] channel_flags_c98_field1_qs; - logic [30:0] channel_flags_c98_field1_wd; - logic channel_flags_c98_field1_we; - logic [31:0] length_c98_qs; - logic [31:0] length_c98_wd; - logic length_c98_we; - logic [7:0] message_header_c98_message_id_qs; - logic [7:0] message_header_c98_message_id_wd; - logic message_header_c98_message_id_we; - logic [1:0] message_header_c98_message_type_qs; - logic [1:0] message_header_c98_message_type_wd; - logic message_header_c98_message_type_we; - logic [7:0] message_header_c98_protocol_id_qs; - logic [7:0] message_header_c98_protocol_id_wd; - logic message_header_c98_protocol_id_we; - logic [9:0] message_header_c98_token_qs; - logic [9:0] message_header_c98_token_wd; - logic message_header_c98_token_we; - logic [3:0] message_header_c98_field1_qs; - logic [3:0] message_header_c98_field1_wd; - logic message_header_c98_field1_we; - logic [31:0] message_payload_1_c98_qs; - logic [31:0] message_payload_1_c98_wd; - logic message_payload_1_c98_we; - logic doorbell_c98_intr_qs; - logic doorbell_c98_intr_wd; - logic doorbell_c98_intr_we; - logic [30:0] doorbell_c98_preserve_mask_qs; - logic [30:0] doorbell_c98_preserve_mask_wd; - logic doorbell_c98_preserve_mask_we; - logic completion_interrupt_c98_intr_qs; - logic completion_interrupt_c98_intr_wd; - logic completion_interrupt_c98_intr_we; - logic [30:0] completion_interrupt_c98_preserve_mask_qs; - logic [30:0] completion_interrupt_c98_preserve_mask_wd; - logic completion_interrupt_c98_preserve_mask_we; - logic [31:0] reserved_1_c99_qs; - logic [31:0] reserved_1_c99_wd; - logic reserved_1_c99_we; - logic channel_status_c99_channel_free_qs; - logic channel_status_c99_channel_free_wd; - logic channel_status_c99_channel_free_we; - logic channel_status_c99_channel_error_qs; - logic channel_status_c99_channel_error_wd; - logic channel_status_c99_channel_error_we; - logic [29:0] channel_status_c99_field1_qs; - logic [29:0] channel_status_c99_field1_wd; - logic channel_status_c99_field1_we; - logic [31:0] reserved_2_c99_qs; - logic [31:0] reserved_2_c99_wd; - logic reserved_2_c99_we; - logic channel_flags_c99_intr_enable_qs; - logic channel_flags_c99_intr_enable_wd; - logic channel_flags_c99_intr_enable_we; - logic [30:0] channel_flags_c99_field1_qs; - logic [30:0] channel_flags_c99_field1_wd; - logic channel_flags_c99_field1_we; - logic [31:0] length_c99_qs; - logic [31:0] length_c99_wd; - logic length_c99_we; - logic [7:0] message_header_c99_message_id_qs; - logic [7:0] message_header_c99_message_id_wd; - logic message_header_c99_message_id_we; - logic [1:0] message_header_c99_message_type_qs; - logic [1:0] message_header_c99_message_type_wd; - logic message_header_c99_message_type_we; - logic [7:0] message_header_c99_protocol_id_qs; - logic [7:0] message_header_c99_protocol_id_wd; - logic message_header_c99_protocol_id_we; - logic [9:0] message_header_c99_token_qs; - logic [9:0] message_header_c99_token_wd; - logic message_header_c99_token_we; - logic [3:0] message_header_c99_field1_qs; - logic [3:0] message_header_c99_field1_wd; - logic message_header_c99_field1_we; - logic [31:0] message_payload_1_c99_qs; - logic [31:0] message_payload_1_c99_wd; - logic message_payload_1_c99_we; - logic doorbell_c99_intr_qs; - logic doorbell_c99_intr_wd; - logic doorbell_c99_intr_we; - logic [30:0] doorbell_c99_preserve_mask_qs; - logic [30:0] doorbell_c99_preserve_mask_wd; - logic doorbell_c99_preserve_mask_we; - logic completion_interrupt_c99_intr_qs; - logic completion_interrupt_c99_intr_wd; - logic completion_interrupt_c99_intr_we; - logic [30:0] completion_interrupt_c99_preserve_mask_qs; - logic [30:0] completion_interrupt_c99_preserve_mask_wd; - logic completion_interrupt_c99_preserve_mask_we; - logic [31:0] reserved_1_c100_qs; - logic [31:0] reserved_1_c100_wd; - logic reserved_1_c100_we; - logic channel_status_c100_channel_free_qs; - logic channel_status_c100_channel_free_wd; - logic channel_status_c100_channel_free_we; - logic channel_status_c100_channel_error_qs; - logic channel_status_c100_channel_error_wd; - logic channel_status_c100_channel_error_we; - logic [29:0] channel_status_c100_field1_qs; - logic [29:0] channel_status_c100_field1_wd; - logic channel_status_c100_field1_we; - logic [31:0] reserved_2_c100_qs; - logic [31:0] reserved_2_c100_wd; - logic reserved_2_c100_we; - logic channel_flags_c100_intr_enable_qs; - logic channel_flags_c100_intr_enable_wd; - logic channel_flags_c100_intr_enable_we; - logic [30:0] channel_flags_c100_field1_qs; - logic [30:0] channel_flags_c100_field1_wd; - logic channel_flags_c100_field1_we; - logic [31:0] length_c100_qs; - logic [31:0] length_c100_wd; - logic length_c100_we; - logic [7:0] message_header_c100_message_id_qs; - logic [7:0] message_header_c100_message_id_wd; - logic message_header_c100_message_id_we; - logic [1:0] message_header_c100_message_type_qs; - logic [1:0] message_header_c100_message_type_wd; - logic message_header_c100_message_type_we; - logic [7:0] message_header_c100_protocol_id_qs; - logic [7:0] message_header_c100_protocol_id_wd; - logic message_header_c100_protocol_id_we; - logic [9:0] message_header_c100_token_qs; - logic [9:0] message_header_c100_token_wd; - logic message_header_c100_token_we; - logic [3:0] message_header_c100_field1_qs; - logic [3:0] message_header_c100_field1_wd; - logic message_header_c100_field1_we; - logic [31:0] message_payload_1_c100_qs; - logic [31:0] message_payload_1_c100_wd; - logic message_payload_1_c100_we; - logic doorbell_c100_intr_qs; - logic doorbell_c100_intr_wd; - logic doorbell_c100_intr_we; - logic [30:0] doorbell_c100_preserve_mask_qs; - logic [30:0] doorbell_c100_preserve_mask_wd; - logic doorbell_c100_preserve_mask_we; - logic completion_interrupt_c100_intr_qs; - logic completion_interrupt_c100_intr_wd; - logic completion_interrupt_c100_intr_we; - logic [30:0] completion_interrupt_c100_preserve_mask_qs; - logic [30:0] completion_interrupt_c100_preserve_mask_wd; - logic completion_interrupt_c100_preserve_mask_we; - logic [31:0] reserved_1_c101_qs; - logic [31:0] reserved_1_c101_wd; - logic reserved_1_c101_we; - logic channel_status_c101_channel_free_qs; - logic channel_status_c101_channel_free_wd; - logic channel_status_c101_channel_free_we; - logic channel_status_c101_channel_error_qs; - logic channel_status_c101_channel_error_wd; - logic channel_status_c101_channel_error_we; - logic [29:0] channel_status_c101_field1_qs; - logic [29:0] channel_status_c101_field1_wd; - logic channel_status_c101_field1_we; - logic [31:0] reserved_2_c101_qs; - logic [31:0] reserved_2_c101_wd; - logic reserved_2_c101_we; - logic channel_flags_c101_intr_enable_qs; - logic channel_flags_c101_intr_enable_wd; - logic channel_flags_c101_intr_enable_we; - logic [30:0] channel_flags_c101_field1_qs; - logic [30:0] channel_flags_c101_field1_wd; - logic channel_flags_c101_field1_we; - logic [31:0] length_c101_qs; - logic [31:0] length_c101_wd; - logic length_c101_we; - logic [7:0] message_header_c101_message_id_qs; - logic [7:0] message_header_c101_message_id_wd; - logic message_header_c101_message_id_we; - logic [1:0] message_header_c101_message_type_qs; - logic [1:0] message_header_c101_message_type_wd; - logic message_header_c101_message_type_we; - logic [7:0] message_header_c101_protocol_id_qs; - logic [7:0] message_header_c101_protocol_id_wd; - logic message_header_c101_protocol_id_we; - logic [9:0] message_header_c101_token_qs; - logic [9:0] message_header_c101_token_wd; - logic message_header_c101_token_we; - logic [3:0] message_header_c101_field1_qs; - logic [3:0] message_header_c101_field1_wd; - logic message_header_c101_field1_we; - logic [31:0] message_payload_1_c101_qs; - logic [31:0] message_payload_1_c101_wd; - logic message_payload_1_c101_we; - logic doorbell_c101_intr_qs; - logic doorbell_c101_intr_wd; - logic doorbell_c101_intr_we; - logic [30:0] doorbell_c101_preserve_mask_qs; - logic [30:0] doorbell_c101_preserve_mask_wd; - logic doorbell_c101_preserve_mask_we; - logic completion_interrupt_c101_intr_qs; - logic completion_interrupt_c101_intr_wd; - logic completion_interrupt_c101_intr_we; - logic [30:0] completion_interrupt_c101_preserve_mask_qs; - logic [30:0] completion_interrupt_c101_preserve_mask_wd; - logic completion_interrupt_c101_preserve_mask_we; - logic [31:0] reserved_1_c102_qs; - logic [31:0] reserved_1_c102_wd; - logic reserved_1_c102_we; - logic channel_status_c102_channel_free_qs; - logic channel_status_c102_channel_free_wd; - logic channel_status_c102_channel_free_we; - logic channel_status_c102_channel_error_qs; - logic channel_status_c102_channel_error_wd; - logic channel_status_c102_channel_error_we; - logic [29:0] channel_status_c102_field1_qs; - logic [29:0] channel_status_c102_field1_wd; - logic channel_status_c102_field1_we; - logic [31:0] reserved_2_c102_qs; - logic [31:0] reserved_2_c102_wd; - logic reserved_2_c102_we; - logic channel_flags_c102_intr_enable_qs; - logic channel_flags_c102_intr_enable_wd; - logic channel_flags_c102_intr_enable_we; - logic [30:0] channel_flags_c102_field1_qs; - logic [30:0] channel_flags_c102_field1_wd; - logic channel_flags_c102_field1_we; - logic [31:0] length_c102_qs; - logic [31:0] length_c102_wd; - logic length_c102_we; - logic [7:0] message_header_c102_message_id_qs; - logic [7:0] message_header_c102_message_id_wd; - logic message_header_c102_message_id_we; - logic [1:0] message_header_c102_message_type_qs; - logic [1:0] message_header_c102_message_type_wd; - logic message_header_c102_message_type_we; - logic [7:0] message_header_c102_protocol_id_qs; - logic [7:0] message_header_c102_protocol_id_wd; - logic message_header_c102_protocol_id_we; - logic [9:0] message_header_c102_token_qs; - logic [9:0] message_header_c102_token_wd; - logic message_header_c102_token_we; - logic [3:0] message_header_c102_field1_qs; - logic [3:0] message_header_c102_field1_wd; - logic message_header_c102_field1_we; - logic [31:0] message_payload_1_c102_qs; - logic [31:0] message_payload_1_c102_wd; - logic message_payload_1_c102_we; - logic doorbell_c102_intr_qs; - logic doorbell_c102_intr_wd; - logic doorbell_c102_intr_we; - logic [30:0] doorbell_c102_preserve_mask_qs; - logic [30:0] doorbell_c102_preserve_mask_wd; - logic doorbell_c102_preserve_mask_we; - logic completion_interrupt_c102_intr_qs; - logic completion_interrupt_c102_intr_wd; - logic completion_interrupt_c102_intr_we; - logic [30:0] completion_interrupt_c102_preserve_mask_qs; - logic [30:0] completion_interrupt_c102_preserve_mask_wd; - logic completion_interrupt_c102_preserve_mask_we; - logic [31:0] reserved_1_c103_qs; - logic [31:0] reserved_1_c103_wd; - logic reserved_1_c103_we; - logic channel_status_c103_channel_free_qs; - logic channel_status_c103_channel_free_wd; - logic channel_status_c103_channel_free_we; - logic channel_status_c103_channel_error_qs; - logic channel_status_c103_channel_error_wd; - logic channel_status_c103_channel_error_we; - logic [29:0] channel_status_c103_field1_qs; - logic [29:0] channel_status_c103_field1_wd; - logic channel_status_c103_field1_we; - logic [31:0] reserved_2_c103_qs; - logic [31:0] reserved_2_c103_wd; - logic reserved_2_c103_we; - logic channel_flags_c103_intr_enable_qs; - logic channel_flags_c103_intr_enable_wd; - logic channel_flags_c103_intr_enable_we; - logic [30:0] channel_flags_c103_field1_qs; - logic [30:0] channel_flags_c103_field1_wd; - logic channel_flags_c103_field1_we; - logic [31:0] length_c103_qs; - logic [31:0] length_c103_wd; - logic length_c103_we; - logic [7:0] message_header_c103_message_id_qs; - logic [7:0] message_header_c103_message_id_wd; - logic message_header_c103_message_id_we; - logic [1:0] message_header_c103_message_type_qs; - logic [1:0] message_header_c103_message_type_wd; - logic message_header_c103_message_type_we; - logic [7:0] message_header_c103_protocol_id_qs; - logic [7:0] message_header_c103_protocol_id_wd; - logic message_header_c103_protocol_id_we; - logic [9:0] message_header_c103_token_qs; - logic [9:0] message_header_c103_token_wd; - logic message_header_c103_token_we; - logic [3:0] message_header_c103_field1_qs; - logic [3:0] message_header_c103_field1_wd; - logic message_header_c103_field1_we; - logic [31:0] message_payload_1_c103_qs; - logic [31:0] message_payload_1_c103_wd; - logic message_payload_1_c103_we; - logic doorbell_c103_intr_qs; - logic doorbell_c103_intr_wd; - logic doorbell_c103_intr_we; - logic [30:0] doorbell_c103_preserve_mask_qs; - logic [30:0] doorbell_c103_preserve_mask_wd; - logic doorbell_c103_preserve_mask_we; - logic completion_interrupt_c103_intr_qs; - logic completion_interrupt_c103_intr_wd; - logic completion_interrupt_c103_intr_we; - logic [30:0] completion_interrupt_c103_preserve_mask_qs; - logic [30:0] completion_interrupt_c103_preserve_mask_wd; - logic completion_interrupt_c103_preserve_mask_we; - logic [31:0] reserved_1_c104_qs; - logic [31:0] reserved_1_c104_wd; - logic reserved_1_c104_we; - logic channel_status_c104_channel_free_qs; - logic channel_status_c104_channel_free_wd; - logic channel_status_c104_channel_free_we; - logic channel_status_c104_channel_error_qs; - logic channel_status_c104_channel_error_wd; - logic channel_status_c104_channel_error_we; - logic [29:0] channel_status_c104_field1_qs; - logic [29:0] channel_status_c104_field1_wd; - logic channel_status_c104_field1_we; - logic [31:0] reserved_2_c104_qs; - logic [31:0] reserved_2_c104_wd; - logic reserved_2_c104_we; - logic channel_flags_c104_intr_enable_qs; - logic channel_flags_c104_intr_enable_wd; - logic channel_flags_c104_intr_enable_we; - logic [30:0] channel_flags_c104_field1_qs; - logic [30:0] channel_flags_c104_field1_wd; - logic channel_flags_c104_field1_we; - logic [31:0] length_c104_qs; - logic [31:0] length_c104_wd; - logic length_c104_we; - logic [7:0] message_header_c104_message_id_qs; - logic [7:0] message_header_c104_message_id_wd; - logic message_header_c104_message_id_we; - logic [1:0] message_header_c104_message_type_qs; - logic [1:0] message_header_c104_message_type_wd; - logic message_header_c104_message_type_we; - logic [7:0] message_header_c104_protocol_id_qs; - logic [7:0] message_header_c104_protocol_id_wd; - logic message_header_c104_protocol_id_we; - logic [9:0] message_header_c104_token_qs; - logic [9:0] message_header_c104_token_wd; - logic message_header_c104_token_we; - logic [3:0] message_header_c104_field1_qs; - logic [3:0] message_header_c104_field1_wd; - logic message_header_c104_field1_we; - logic [31:0] message_payload_1_c104_qs; - logic [31:0] message_payload_1_c104_wd; - logic message_payload_1_c104_we; - logic doorbell_c104_intr_qs; - logic doorbell_c104_intr_wd; - logic doorbell_c104_intr_we; - logic [30:0] doorbell_c104_preserve_mask_qs; - logic [30:0] doorbell_c104_preserve_mask_wd; - logic doorbell_c104_preserve_mask_we; - logic completion_interrupt_c104_intr_qs; - logic completion_interrupt_c104_intr_wd; - logic completion_interrupt_c104_intr_we; - logic [30:0] completion_interrupt_c104_preserve_mask_qs; - logic [30:0] completion_interrupt_c104_preserve_mask_wd; - logic completion_interrupt_c104_preserve_mask_we; - logic [31:0] reserved_1_c105_qs; - logic [31:0] reserved_1_c105_wd; - logic reserved_1_c105_we; - logic channel_status_c105_channel_free_qs; - logic channel_status_c105_channel_free_wd; - logic channel_status_c105_channel_free_we; - logic channel_status_c105_channel_error_qs; - logic channel_status_c105_channel_error_wd; - logic channel_status_c105_channel_error_we; - logic [29:0] channel_status_c105_field1_qs; - logic [29:0] channel_status_c105_field1_wd; - logic channel_status_c105_field1_we; - logic [31:0] reserved_2_c105_qs; - logic [31:0] reserved_2_c105_wd; - logic reserved_2_c105_we; - logic channel_flags_c105_intr_enable_qs; - logic channel_flags_c105_intr_enable_wd; - logic channel_flags_c105_intr_enable_we; - logic [30:0] channel_flags_c105_field1_qs; - logic [30:0] channel_flags_c105_field1_wd; - logic channel_flags_c105_field1_we; - logic [31:0] length_c105_qs; - logic [31:0] length_c105_wd; - logic length_c105_we; - logic [7:0] message_header_c105_message_id_qs; - logic [7:0] message_header_c105_message_id_wd; - logic message_header_c105_message_id_we; - logic [1:0] message_header_c105_message_type_qs; - logic [1:0] message_header_c105_message_type_wd; - logic message_header_c105_message_type_we; - logic [7:0] message_header_c105_protocol_id_qs; - logic [7:0] message_header_c105_protocol_id_wd; - logic message_header_c105_protocol_id_we; - logic [9:0] message_header_c105_token_qs; - logic [9:0] message_header_c105_token_wd; - logic message_header_c105_token_we; - logic [3:0] message_header_c105_field1_qs; - logic [3:0] message_header_c105_field1_wd; - logic message_header_c105_field1_we; - logic [31:0] message_payload_1_c105_qs; - logic [31:0] message_payload_1_c105_wd; - logic message_payload_1_c105_we; - logic doorbell_c105_intr_qs; - logic doorbell_c105_intr_wd; - logic doorbell_c105_intr_we; - logic [30:0] doorbell_c105_preserve_mask_qs; - logic [30:0] doorbell_c105_preserve_mask_wd; - logic doorbell_c105_preserve_mask_we; - logic completion_interrupt_c105_intr_qs; - logic completion_interrupt_c105_intr_wd; - logic completion_interrupt_c105_intr_we; - logic [30:0] completion_interrupt_c105_preserve_mask_qs; - logic [30:0] completion_interrupt_c105_preserve_mask_wd; - logic completion_interrupt_c105_preserve_mask_we; - logic [31:0] reserved_1_c106_qs; - logic [31:0] reserved_1_c106_wd; - logic reserved_1_c106_we; - logic channel_status_c106_channel_free_qs; - logic channel_status_c106_channel_free_wd; - logic channel_status_c106_channel_free_we; - logic channel_status_c106_channel_error_qs; - logic channel_status_c106_channel_error_wd; - logic channel_status_c106_channel_error_we; - logic [29:0] channel_status_c106_field1_qs; - logic [29:0] channel_status_c106_field1_wd; - logic channel_status_c106_field1_we; - logic [31:0] reserved_2_c106_qs; - logic [31:0] reserved_2_c106_wd; - logic reserved_2_c106_we; - logic channel_flags_c106_intr_enable_qs; - logic channel_flags_c106_intr_enable_wd; - logic channel_flags_c106_intr_enable_we; - logic [30:0] channel_flags_c106_field1_qs; - logic [30:0] channel_flags_c106_field1_wd; - logic channel_flags_c106_field1_we; - logic [31:0] length_c106_qs; - logic [31:0] length_c106_wd; - logic length_c106_we; - logic [7:0] message_header_c106_message_id_qs; - logic [7:0] message_header_c106_message_id_wd; - logic message_header_c106_message_id_we; - logic [1:0] message_header_c106_message_type_qs; - logic [1:0] message_header_c106_message_type_wd; - logic message_header_c106_message_type_we; - logic [7:0] message_header_c106_protocol_id_qs; - logic [7:0] message_header_c106_protocol_id_wd; - logic message_header_c106_protocol_id_we; - logic [9:0] message_header_c106_token_qs; - logic [9:0] message_header_c106_token_wd; - logic message_header_c106_token_we; - logic [3:0] message_header_c106_field1_qs; - logic [3:0] message_header_c106_field1_wd; - logic message_header_c106_field1_we; - logic [31:0] message_payload_1_c106_qs; - logic [31:0] message_payload_1_c106_wd; - logic message_payload_1_c106_we; - logic doorbell_c106_intr_qs; - logic doorbell_c106_intr_wd; - logic doorbell_c106_intr_we; - logic [30:0] doorbell_c106_preserve_mask_qs; - logic [30:0] doorbell_c106_preserve_mask_wd; - logic doorbell_c106_preserve_mask_we; - logic completion_interrupt_c106_intr_qs; - logic completion_interrupt_c106_intr_wd; - logic completion_interrupt_c106_intr_we; - logic [30:0] completion_interrupt_c106_preserve_mask_qs; - logic [30:0] completion_interrupt_c106_preserve_mask_wd; - logic completion_interrupt_c106_preserve_mask_we; - logic [31:0] reserved_1_c107_qs; - logic [31:0] reserved_1_c107_wd; - logic reserved_1_c107_we; - logic channel_status_c107_channel_free_qs; - logic channel_status_c107_channel_free_wd; - logic channel_status_c107_channel_free_we; - logic channel_status_c107_channel_error_qs; - logic channel_status_c107_channel_error_wd; - logic channel_status_c107_channel_error_we; - logic [29:0] channel_status_c107_field1_qs; - logic [29:0] channel_status_c107_field1_wd; - logic channel_status_c107_field1_we; - logic [31:0] reserved_2_c107_qs; - logic [31:0] reserved_2_c107_wd; - logic reserved_2_c107_we; - logic channel_flags_c107_intr_enable_qs; - logic channel_flags_c107_intr_enable_wd; - logic channel_flags_c107_intr_enable_we; - logic [30:0] channel_flags_c107_field1_qs; - logic [30:0] channel_flags_c107_field1_wd; - logic channel_flags_c107_field1_we; - logic [31:0] length_c107_qs; - logic [31:0] length_c107_wd; - logic length_c107_we; - logic [7:0] message_header_c107_message_id_qs; - logic [7:0] message_header_c107_message_id_wd; - logic message_header_c107_message_id_we; - logic [1:0] message_header_c107_message_type_qs; - logic [1:0] message_header_c107_message_type_wd; - logic message_header_c107_message_type_we; - logic [7:0] message_header_c107_protocol_id_qs; - logic [7:0] message_header_c107_protocol_id_wd; - logic message_header_c107_protocol_id_we; - logic [9:0] message_header_c107_token_qs; - logic [9:0] message_header_c107_token_wd; - logic message_header_c107_token_we; - logic [3:0] message_header_c107_field1_qs; - logic [3:0] message_header_c107_field1_wd; - logic message_header_c107_field1_we; - logic [31:0] message_payload_1_c107_qs; - logic [31:0] message_payload_1_c107_wd; - logic message_payload_1_c107_we; - logic doorbell_c107_intr_qs; - logic doorbell_c107_intr_wd; - logic doorbell_c107_intr_we; - logic [30:0] doorbell_c107_preserve_mask_qs; - logic [30:0] doorbell_c107_preserve_mask_wd; - logic doorbell_c107_preserve_mask_we; - logic completion_interrupt_c107_intr_qs; - logic completion_interrupt_c107_intr_wd; - logic completion_interrupt_c107_intr_we; - logic [30:0] completion_interrupt_c107_preserve_mask_qs; - logic [30:0] completion_interrupt_c107_preserve_mask_wd; - logic completion_interrupt_c107_preserve_mask_we; - logic [31:0] reserved_1_c108_qs; - logic [31:0] reserved_1_c108_wd; - logic reserved_1_c108_we; - logic channel_status_c108_channel_free_qs; - logic channel_status_c108_channel_free_wd; - logic channel_status_c108_channel_free_we; - logic channel_status_c108_channel_error_qs; - logic channel_status_c108_channel_error_wd; - logic channel_status_c108_channel_error_we; - logic [29:0] channel_status_c108_field1_qs; - logic [29:0] channel_status_c108_field1_wd; - logic channel_status_c108_field1_we; - logic [31:0] reserved_2_c108_qs; - logic [31:0] reserved_2_c108_wd; - logic reserved_2_c108_we; - logic channel_flags_c108_intr_enable_qs; - logic channel_flags_c108_intr_enable_wd; - logic channel_flags_c108_intr_enable_we; - logic [30:0] channel_flags_c108_field1_qs; - logic [30:0] channel_flags_c108_field1_wd; - logic channel_flags_c108_field1_we; - logic [31:0] length_c108_qs; - logic [31:0] length_c108_wd; - logic length_c108_we; - logic [7:0] message_header_c108_message_id_qs; - logic [7:0] message_header_c108_message_id_wd; - logic message_header_c108_message_id_we; - logic [1:0] message_header_c108_message_type_qs; - logic [1:0] message_header_c108_message_type_wd; - logic message_header_c108_message_type_we; - logic [7:0] message_header_c108_protocol_id_qs; - logic [7:0] message_header_c108_protocol_id_wd; - logic message_header_c108_protocol_id_we; - logic [9:0] message_header_c108_token_qs; - logic [9:0] message_header_c108_token_wd; - logic message_header_c108_token_we; - logic [3:0] message_header_c108_field1_qs; - logic [3:0] message_header_c108_field1_wd; - logic message_header_c108_field1_we; - logic [31:0] message_payload_1_c108_qs; - logic [31:0] message_payload_1_c108_wd; - logic message_payload_1_c108_we; - logic doorbell_c108_intr_qs; - logic doorbell_c108_intr_wd; - logic doorbell_c108_intr_we; - logic [30:0] doorbell_c108_preserve_mask_qs; - logic [30:0] doorbell_c108_preserve_mask_wd; - logic doorbell_c108_preserve_mask_we; - logic completion_interrupt_c108_intr_qs; - logic completion_interrupt_c108_intr_wd; - logic completion_interrupt_c108_intr_we; - logic [30:0] completion_interrupt_c108_preserve_mask_qs; - logic [30:0] completion_interrupt_c108_preserve_mask_wd; - logic completion_interrupt_c108_preserve_mask_we; - logic [31:0] reserved_1_c109_qs; - logic [31:0] reserved_1_c109_wd; - logic reserved_1_c109_we; - logic channel_status_c109_channel_free_qs; - logic channel_status_c109_channel_free_wd; - logic channel_status_c109_channel_free_we; - logic channel_status_c109_channel_error_qs; - logic channel_status_c109_channel_error_wd; - logic channel_status_c109_channel_error_we; - logic [29:0] channel_status_c109_field1_qs; - logic [29:0] channel_status_c109_field1_wd; - logic channel_status_c109_field1_we; - logic [31:0] reserved_2_c109_qs; - logic [31:0] reserved_2_c109_wd; - logic reserved_2_c109_we; - logic channel_flags_c109_intr_enable_qs; - logic channel_flags_c109_intr_enable_wd; - logic channel_flags_c109_intr_enable_we; - logic [30:0] channel_flags_c109_field1_qs; - logic [30:0] channel_flags_c109_field1_wd; - logic channel_flags_c109_field1_we; - logic [31:0] length_c109_qs; - logic [31:0] length_c109_wd; - logic length_c109_we; - logic [7:0] message_header_c109_message_id_qs; - logic [7:0] message_header_c109_message_id_wd; - logic message_header_c109_message_id_we; - logic [1:0] message_header_c109_message_type_qs; - logic [1:0] message_header_c109_message_type_wd; - logic message_header_c109_message_type_we; - logic [7:0] message_header_c109_protocol_id_qs; - logic [7:0] message_header_c109_protocol_id_wd; - logic message_header_c109_protocol_id_we; - logic [9:0] message_header_c109_token_qs; - logic [9:0] message_header_c109_token_wd; - logic message_header_c109_token_we; - logic [3:0] message_header_c109_field1_qs; - logic [3:0] message_header_c109_field1_wd; - logic message_header_c109_field1_we; - logic [31:0] message_payload_1_c109_qs; - logic [31:0] message_payload_1_c109_wd; - logic message_payload_1_c109_we; - logic doorbell_c109_intr_qs; - logic doorbell_c109_intr_wd; - logic doorbell_c109_intr_we; - logic [30:0] doorbell_c109_preserve_mask_qs; - logic [30:0] doorbell_c109_preserve_mask_wd; - logic doorbell_c109_preserve_mask_we; - logic completion_interrupt_c109_intr_qs; - logic completion_interrupt_c109_intr_wd; - logic completion_interrupt_c109_intr_we; - logic [30:0] completion_interrupt_c109_preserve_mask_qs; - logic [30:0] completion_interrupt_c109_preserve_mask_wd; - logic completion_interrupt_c109_preserve_mask_we; - logic [31:0] reserved_1_c110_qs; - logic [31:0] reserved_1_c110_wd; - logic reserved_1_c110_we; - logic channel_status_c110_channel_free_qs; - logic channel_status_c110_channel_free_wd; - logic channel_status_c110_channel_free_we; - logic channel_status_c110_channel_error_qs; - logic channel_status_c110_channel_error_wd; - logic channel_status_c110_channel_error_we; - logic [29:0] channel_status_c110_field1_qs; - logic [29:0] channel_status_c110_field1_wd; - logic channel_status_c110_field1_we; - logic [31:0] reserved_2_c110_qs; - logic [31:0] reserved_2_c110_wd; - logic reserved_2_c110_we; - logic channel_flags_c110_intr_enable_qs; - logic channel_flags_c110_intr_enable_wd; - logic channel_flags_c110_intr_enable_we; - logic [30:0] channel_flags_c110_field1_qs; - logic [30:0] channel_flags_c110_field1_wd; - logic channel_flags_c110_field1_we; - logic [31:0] length_c110_qs; - logic [31:0] length_c110_wd; - logic length_c110_we; - logic [7:0] message_header_c110_message_id_qs; - logic [7:0] message_header_c110_message_id_wd; - logic message_header_c110_message_id_we; - logic [1:0] message_header_c110_message_type_qs; - logic [1:0] message_header_c110_message_type_wd; - logic message_header_c110_message_type_we; - logic [7:0] message_header_c110_protocol_id_qs; - logic [7:0] message_header_c110_protocol_id_wd; - logic message_header_c110_protocol_id_we; - logic [9:0] message_header_c110_token_qs; - logic [9:0] message_header_c110_token_wd; - logic message_header_c110_token_we; - logic [3:0] message_header_c110_field1_qs; - logic [3:0] message_header_c110_field1_wd; - logic message_header_c110_field1_we; - logic [31:0] message_payload_1_c110_qs; - logic [31:0] message_payload_1_c110_wd; - logic message_payload_1_c110_we; - logic doorbell_c110_intr_qs; - logic doorbell_c110_intr_wd; - logic doorbell_c110_intr_we; - logic [30:0] doorbell_c110_preserve_mask_qs; - logic [30:0] doorbell_c110_preserve_mask_wd; - logic doorbell_c110_preserve_mask_we; - logic completion_interrupt_c110_intr_qs; - logic completion_interrupt_c110_intr_wd; - logic completion_interrupt_c110_intr_we; - logic [30:0] completion_interrupt_c110_preserve_mask_qs; - logic [30:0] completion_interrupt_c110_preserve_mask_wd; - logic completion_interrupt_c110_preserve_mask_we; - logic [31:0] reserved_1_c111_qs; - logic [31:0] reserved_1_c111_wd; - logic reserved_1_c111_we; - logic channel_status_c111_channel_free_qs; - logic channel_status_c111_channel_free_wd; - logic channel_status_c111_channel_free_we; - logic channel_status_c111_channel_error_qs; - logic channel_status_c111_channel_error_wd; - logic channel_status_c111_channel_error_we; - logic [29:0] channel_status_c111_field1_qs; - logic [29:0] channel_status_c111_field1_wd; - logic channel_status_c111_field1_we; - logic [31:0] reserved_2_c111_qs; - logic [31:0] reserved_2_c111_wd; - logic reserved_2_c111_we; - logic channel_flags_c111_intr_enable_qs; - logic channel_flags_c111_intr_enable_wd; - logic channel_flags_c111_intr_enable_we; - logic [30:0] channel_flags_c111_field1_qs; - logic [30:0] channel_flags_c111_field1_wd; - logic channel_flags_c111_field1_we; - logic [31:0] length_c111_qs; - logic [31:0] length_c111_wd; - logic length_c111_we; - logic [7:0] message_header_c111_message_id_qs; - logic [7:0] message_header_c111_message_id_wd; - logic message_header_c111_message_id_we; - logic [1:0] message_header_c111_message_type_qs; - logic [1:0] message_header_c111_message_type_wd; - logic message_header_c111_message_type_we; - logic [7:0] message_header_c111_protocol_id_qs; - logic [7:0] message_header_c111_protocol_id_wd; - logic message_header_c111_protocol_id_we; - logic [9:0] message_header_c111_token_qs; - logic [9:0] message_header_c111_token_wd; - logic message_header_c111_token_we; - logic [3:0] message_header_c111_field1_qs; - logic [3:0] message_header_c111_field1_wd; - logic message_header_c111_field1_we; - logic [31:0] message_payload_1_c111_qs; - logic [31:0] message_payload_1_c111_wd; - logic message_payload_1_c111_we; - logic doorbell_c111_intr_qs; - logic doorbell_c111_intr_wd; - logic doorbell_c111_intr_we; - logic [30:0] doorbell_c111_preserve_mask_qs; - logic [30:0] doorbell_c111_preserve_mask_wd; - logic doorbell_c111_preserve_mask_we; - logic completion_interrupt_c111_intr_qs; - logic completion_interrupt_c111_intr_wd; - logic completion_interrupt_c111_intr_we; - logic [30:0] completion_interrupt_c111_preserve_mask_qs; - logic [30:0] completion_interrupt_c111_preserve_mask_wd; - logic completion_interrupt_c111_preserve_mask_we; - logic [31:0] reserved_1_c112_qs; - logic [31:0] reserved_1_c112_wd; - logic reserved_1_c112_we; - logic channel_status_c112_channel_free_qs; - logic channel_status_c112_channel_free_wd; - logic channel_status_c112_channel_free_we; - logic channel_status_c112_channel_error_qs; - logic channel_status_c112_channel_error_wd; - logic channel_status_c112_channel_error_we; - logic [29:0] channel_status_c112_field1_qs; - logic [29:0] channel_status_c112_field1_wd; - logic channel_status_c112_field1_we; - logic [31:0] reserved_2_c112_qs; - logic [31:0] reserved_2_c112_wd; - logic reserved_2_c112_we; - logic channel_flags_c112_intr_enable_qs; - logic channel_flags_c112_intr_enable_wd; - logic channel_flags_c112_intr_enable_we; - logic [30:0] channel_flags_c112_field1_qs; - logic [30:0] channel_flags_c112_field1_wd; - logic channel_flags_c112_field1_we; - logic [31:0] length_c112_qs; - logic [31:0] length_c112_wd; - logic length_c112_we; - logic [7:0] message_header_c112_message_id_qs; - logic [7:0] message_header_c112_message_id_wd; - logic message_header_c112_message_id_we; - logic [1:0] message_header_c112_message_type_qs; - logic [1:0] message_header_c112_message_type_wd; - logic message_header_c112_message_type_we; - logic [7:0] message_header_c112_protocol_id_qs; - logic [7:0] message_header_c112_protocol_id_wd; - logic message_header_c112_protocol_id_we; - logic [9:0] message_header_c112_token_qs; - logic [9:0] message_header_c112_token_wd; - logic message_header_c112_token_we; - logic [3:0] message_header_c112_field1_qs; - logic [3:0] message_header_c112_field1_wd; - logic message_header_c112_field1_we; - logic [31:0] message_payload_1_c112_qs; - logic [31:0] message_payload_1_c112_wd; - logic message_payload_1_c112_we; - logic doorbell_c112_intr_qs; - logic doorbell_c112_intr_wd; - logic doorbell_c112_intr_we; - logic [30:0] doorbell_c112_preserve_mask_qs; - logic [30:0] doorbell_c112_preserve_mask_wd; - logic doorbell_c112_preserve_mask_we; - logic completion_interrupt_c112_intr_qs; - logic completion_interrupt_c112_intr_wd; - logic completion_interrupt_c112_intr_we; - logic [30:0] completion_interrupt_c112_preserve_mask_qs; - logic [30:0] completion_interrupt_c112_preserve_mask_wd; - logic completion_interrupt_c112_preserve_mask_we; - logic [31:0] reserved_1_c113_qs; - logic [31:0] reserved_1_c113_wd; - logic reserved_1_c113_we; - logic channel_status_c113_channel_free_qs; - logic channel_status_c113_channel_free_wd; - logic channel_status_c113_channel_free_we; - logic channel_status_c113_channel_error_qs; - logic channel_status_c113_channel_error_wd; - logic channel_status_c113_channel_error_we; - logic [29:0] channel_status_c113_field1_qs; - logic [29:0] channel_status_c113_field1_wd; - logic channel_status_c113_field1_we; - logic [31:0] reserved_2_c113_qs; - logic [31:0] reserved_2_c113_wd; - logic reserved_2_c113_we; - logic channel_flags_c113_intr_enable_qs; - logic channel_flags_c113_intr_enable_wd; - logic channel_flags_c113_intr_enable_we; - logic [30:0] channel_flags_c113_field1_qs; - logic [30:0] channel_flags_c113_field1_wd; - logic channel_flags_c113_field1_we; - logic [31:0] length_c113_qs; - logic [31:0] length_c113_wd; - logic length_c113_we; - logic [7:0] message_header_c113_message_id_qs; - logic [7:0] message_header_c113_message_id_wd; - logic message_header_c113_message_id_we; - logic [1:0] message_header_c113_message_type_qs; - logic [1:0] message_header_c113_message_type_wd; - logic message_header_c113_message_type_we; - logic [7:0] message_header_c113_protocol_id_qs; - logic [7:0] message_header_c113_protocol_id_wd; - logic message_header_c113_protocol_id_we; - logic [9:0] message_header_c113_token_qs; - logic [9:0] message_header_c113_token_wd; - logic message_header_c113_token_we; - logic [3:0] message_header_c113_field1_qs; - logic [3:0] message_header_c113_field1_wd; - logic message_header_c113_field1_we; - logic [31:0] message_payload_1_c113_qs; - logic [31:0] message_payload_1_c113_wd; - logic message_payload_1_c113_we; - logic doorbell_c113_intr_qs; - logic doorbell_c113_intr_wd; - logic doorbell_c113_intr_we; - logic [30:0] doorbell_c113_preserve_mask_qs; - logic [30:0] doorbell_c113_preserve_mask_wd; - logic doorbell_c113_preserve_mask_we; - logic completion_interrupt_c113_intr_qs; - logic completion_interrupt_c113_intr_wd; - logic completion_interrupt_c113_intr_we; - logic [30:0] completion_interrupt_c113_preserve_mask_qs; - logic [30:0] completion_interrupt_c113_preserve_mask_wd; - logic completion_interrupt_c113_preserve_mask_we; - logic [31:0] reserved_1_c114_qs; - logic [31:0] reserved_1_c114_wd; - logic reserved_1_c114_we; - logic channel_status_c114_channel_free_qs; - logic channel_status_c114_channel_free_wd; - logic channel_status_c114_channel_free_we; - logic channel_status_c114_channel_error_qs; - logic channel_status_c114_channel_error_wd; - logic channel_status_c114_channel_error_we; - logic [29:0] channel_status_c114_field1_qs; - logic [29:0] channel_status_c114_field1_wd; - logic channel_status_c114_field1_we; - logic [31:0] reserved_2_c114_qs; - logic [31:0] reserved_2_c114_wd; - logic reserved_2_c114_we; - logic channel_flags_c114_intr_enable_qs; - logic channel_flags_c114_intr_enable_wd; - logic channel_flags_c114_intr_enable_we; - logic [30:0] channel_flags_c114_field1_qs; - logic [30:0] channel_flags_c114_field1_wd; - logic channel_flags_c114_field1_we; - logic [31:0] length_c114_qs; - logic [31:0] length_c114_wd; - logic length_c114_we; - logic [7:0] message_header_c114_message_id_qs; - logic [7:0] message_header_c114_message_id_wd; - logic message_header_c114_message_id_we; - logic [1:0] message_header_c114_message_type_qs; - logic [1:0] message_header_c114_message_type_wd; - logic message_header_c114_message_type_we; - logic [7:0] message_header_c114_protocol_id_qs; - logic [7:0] message_header_c114_protocol_id_wd; - logic message_header_c114_protocol_id_we; - logic [9:0] message_header_c114_token_qs; - logic [9:0] message_header_c114_token_wd; - logic message_header_c114_token_we; - logic [3:0] message_header_c114_field1_qs; - logic [3:0] message_header_c114_field1_wd; - logic message_header_c114_field1_we; - logic [31:0] message_payload_1_c114_qs; - logic [31:0] message_payload_1_c114_wd; - logic message_payload_1_c114_we; - logic doorbell_c114_intr_qs; - logic doorbell_c114_intr_wd; - logic doorbell_c114_intr_we; - logic [30:0] doorbell_c114_preserve_mask_qs; - logic [30:0] doorbell_c114_preserve_mask_wd; - logic doorbell_c114_preserve_mask_we; - logic completion_interrupt_c114_intr_qs; - logic completion_interrupt_c114_intr_wd; - logic completion_interrupt_c114_intr_we; - logic [30:0] completion_interrupt_c114_preserve_mask_qs; - logic [30:0] completion_interrupt_c114_preserve_mask_wd; - logic completion_interrupt_c114_preserve_mask_we; - logic [31:0] reserved_1_c115_qs; - logic [31:0] reserved_1_c115_wd; - logic reserved_1_c115_we; - logic channel_status_c115_channel_free_qs; - logic channel_status_c115_channel_free_wd; - logic channel_status_c115_channel_free_we; - logic channel_status_c115_channel_error_qs; - logic channel_status_c115_channel_error_wd; - logic channel_status_c115_channel_error_we; - logic [29:0] channel_status_c115_field1_qs; - logic [29:0] channel_status_c115_field1_wd; - logic channel_status_c115_field1_we; - logic [31:0] reserved_2_c115_qs; - logic [31:0] reserved_2_c115_wd; - logic reserved_2_c115_we; - logic channel_flags_c115_intr_enable_qs; - logic channel_flags_c115_intr_enable_wd; - logic channel_flags_c115_intr_enable_we; - logic [30:0] channel_flags_c115_field1_qs; - logic [30:0] channel_flags_c115_field1_wd; - logic channel_flags_c115_field1_we; - logic [31:0] length_c115_qs; - logic [31:0] length_c115_wd; - logic length_c115_we; - logic [7:0] message_header_c115_message_id_qs; - logic [7:0] message_header_c115_message_id_wd; - logic message_header_c115_message_id_we; - logic [1:0] message_header_c115_message_type_qs; - logic [1:0] message_header_c115_message_type_wd; - logic message_header_c115_message_type_we; - logic [7:0] message_header_c115_protocol_id_qs; - logic [7:0] message_header_c115_protocol_id_wd; - logic message_header_c115_protocol_id_we; - logic [9:0] message_header_c115_token_qs; - logic [9:0] message_header_c115_token_wd; - logic message_header_c115_token_we; - logic [3:0] message_header_c115_field1_qs; - logic [3:0] message_header_c115_field1_wd; - logic message_header_c115_field1_we; - logic [31:0] message_payload_1_c115_qs; - logic [31:0] message_payload_1_c115_wd; - logic message_payload_1_c115_we; - logic doorbell_c115_intr_qs; - logic doorbell_c115_intr_wd; - logic doorbell_c115_intr_we; - logic [30:0] doorbell_c115_preserve_mask_qs; - logic [30:0] doorbell_c115_preserve_mask_wd; - logic doorbell_c115_preserve_mask_we; - logic completion_interrupt_c115_intr_qs; - logic completion_interrupt_c115_intr_wd; - logic completion_interrupt_c115_intr_we; - logic [30:0] completion_interrupt_c115_preserve_mask_qs; - logic [30:0] completion_interrupt_c115_preserve_mask_wd; - logic completion_interrupt_c115_preserve_mask_we; - logic [31:0] reserved_1_c116_qs; - logic [31:0] reserved_1_c116_wd; - logic reserved_1_c116_we; - logic channel_status_c116_channel_free_qs; - logic channel_status_c116_channel_free_wd; - logic channel_status_c116_channel_free_we; - logic channel_status_c116_channel_error_qs; - logic channel_status_c116_channel_error_wd; - logic channel_status_c116_channel_error_we; - logic [29:0] channel_status_c116_field1_qs; - logic [29:0] channel_status_c116_field1_wd; - logic channel_status_c116_field1_we; - logic [31:0] reserved_2_c116_qs; - logic [31:0] reserved_2_c116_wd; - logic reserved_2_c116_we; - logic channel_flags_c116_intr_enable_qs; - logic channel_flags_c116_intr_enable_wd; - logic channel_flags_c116_intr_enable_we; - logic [30:0] channel_flags_c116_field1_qs; - logic [30:0] channel_flags_c116_field1_wd; - logic channel_flags_c116_field1_we; - logic [31:0] length_c116_qs; - logic [31:0] length_c116_wd; - logic length_c116_we; - logic [7:0] message_header_c116_message_id_qs; - logic [7:0] message_header_c116_message_id_wd; - logic message_header_c116_message_id_we; - logic [1:0] message_header_c116_message_type_qs; - logic [1:0] message_header_c116_message_type_wd; - logic message_header_c116_message_type_we; - logic [7:0] message_header_c116_protocol_id_qs; - logic [7:0] message_header_c116_protocol_id_wd; - logic message_header_c116_protocol_id_we; - logic [9:0] message_header_c116_token_qs; - logic [9:0] message_header_c116_token_wd; - logic message_header_c116_token_we; - logic [3:0] message_header_c116_field1_qs; - logic [3:0] message_header_c116_field1_wd; - logic message_header_c116_field1_we; - logic [31:0] message_payload_1_c116_qs; - logic [31:0] message_payload_1_c116_wd; - logic message_payload_1_c116_we; - logic doorbell_c116_intr_qs; - logic doorbell_c116_intr_wd; - logic doorbell_c116_intr_we; - logic [30:0] doorbell_c116_preserve_mask_qs; - logic [30:0] doorbell_c116_preserve_mask_wd; - logic doorbell_c116_preserve_mask_we; - logic completion_interrupt_c116_intr_qs; - logic completion_interrupt_c116_intr_wd; - logic completion_interrupt_c116_intr_we; - logic [30:0] completion_interrupt_c116_preserve_mask_qs; - logic [30:0] completion_interrupt_c116_preserve_mask_wd; - logic completion_interrupt_c116_preserve_mask_we; - logic [31:0] reserved_1_c117_qs; - logic [31:0] reserved_1_c117_wd; - logic reserved_1_c117_we; - logic channel_status_c117_channel_free_qs; - logic channel_status_c117_channel_free_wd; - logic channel_status_c117_channel_free_we; - logic channel_status_c117_channel_error_qs; - logic channel_status_c117_channel_error_wd; - logic channel_status_c117_channel_error_we; - logic [29:0] channel_status_c117_field1_qs; - logic [29:0] channel_status_c117_field1_wd; - logic channel_status_c117_field1_we; - logic [31:0] reserved_2_c117_qs; - logic [31:0] reserved_2_c117_wd; - logic reserved_2_c117_we; - logic channel_flags_c117_intr_enable_qs; - logic channel_flags_c117_intr_enable_wd; - logic channel_flags_c117_intr_enable_we; - logic [30:0] channel_flags_c117_field1_qs; - logic [30:0] channel_flags_c117_field1_wd; - logic channel_flags_c117_field1_we; - logic [31:0] length_c117_qs; - logic [31:0] length_c117_wd; - logic length_c117_we; - logic [7:0] message_header_c117_message_id_qs; - logic [7:0] message_header_c117_message_id_wd; - logic message_header_c117_message_id_we; - logic [1:0] message_header_c117_message_type_qs; - logic [1:0] message_header_c117_message_type_wd; - logic message_header_c117_message_type_we; - logic [7:0] message_header_c117_protocol_id_qs; - logic [7:0] message_header_c117_protocol_id_wd; - logic message_header_c117_protocol_id_we; - logic [9:0] message_header_c117_token_qs; - logic [9:0] message_header_c117_token_wd; - logic message_header_c117_token_we; - logic [3:0] message_header_c117_field1_qs; - logic [3:0] message_header_c117_field1_wd; - logic message_header_c117_field1_we; - logic [31:0] message_payload_1_c117_qs; - logic [31:0] message_payload_1_c117_wd; - logic message_payload_1_c117_we; - logic doorbell_c117_intr_qs; - logic doorbell_c117_intr_wd; - logic doorbell_c117_intr_we; - logic [30:0] doorbell_c117_preserve_mask_qs; - logic [30:0] doorbell_c117_preserve_mask_wd; - logic doorbell_c117_preserve_mask_we; - logic completion_interrupt_c117_intr_qs; - logic completion_interrupt_c117_intr_wd; - logic completion_interrupt_c117_intr_we; - logic [30:0] completion_interrupt_c117_preserve_mask_qs; - logic [30:0] completion_interrupt_c117_preserve_mask_wd; - logic completion_interrupt_c117_preserve_mask_we; - logic [31:0] reserved_1_c118_qs; - logic [31:0] reserved_1_c118_wd; - logic reserved_1_c118_we; - logic channel_status_c118_channel_free_qs; - logic channel_status_c118_channel_free_wd; - logic channel_status_c118_channel_free_we; - logic channel_status_c118_channel_error_qs; - logic channel_status_c118_channel_error_wd; - logic channel_status_c118_channel_error_we; - logic [29:0] channel_status_c118_field1_qs; - logic [29:0] channel_status_c118_field1_wd; - logic channel_status_c118_field1_we; - logic [31:0] reserved_2_c118_qs; - logic [31:0] reserved_2_c118_wd; - logic reserved_2_c118_we; - logic channel_flags_c118_intr_enable_qs; - logic channel_flags_c118_intr_enable_wd; - logic channel_flags_c118_intr_enable_we; - logic [30:0] channel_flags_c118_field1_qs; - logic [30:0] channel_flags_c118_field1_wd; - logic channel_flags_c118_field1_we; - logic [31:0] length_c118_qs; - logic [31:0] length_c118_wd; - logic length_c118_we; - logic [7:0] message_header_c118_message_id_qs; - logic [7:0] message_header_c118_message_id_wd; - logic message_header_c118_message_id_we; - logic [1:0] message_header_c118_message_type_qs; - logic [1:0] message_header_c118_message_type_wd; - logic message_header_c118_message_type_we; - logic [7:0] message_header_c118_protocol_id_qs; - logic [7:0] message_header_c118_protocol_id_wd; - logic message_header_c118_protocol_id_we; - logic [9:0] message_header_c118_token_qs; - logic [9:0] message_header_c118_token_wd; - logic message_header_c118_token_we; - logic [3:0] message_header_c118_field1_qs; - logic [3:0] message_header_c118_field1_wd; - logic message_header_c118_field1_we; - logic [31:0] message_payload_1_c118_qs; - logic [31:0] message_payload_1_c118_wd; - logic message_payload_1_c118_we; - logic doorbell_c118_intr_qs; - logic doorbell_c118_intr_wd; - logic doorbell_c118_intr_we; - logic [30:0] doorbell_c118_preserve_mask_qs; - logic [30:0] doorbell_c118_preserve_mask_wd; - logic doorbell_c118_preserve_mask_we; - logic completion_interrupt_c118_intr_qs; - logic completion_interrupt_c118_intr_wd; - logic completion_interrupt_c118_intr_we; - logic [30:0] completion_interrupt_c118_preserve_mask_qs; - logic [30:0] completion_interrupt_c118_preserve_mask_wd; - logic completion_interrupt_c118_preserve_mask_we; - logic [31:0] reserved_1_c119_qs; - logic [31:0] reserved_1_c119_wd; - logic reserved_1_c119_we; - logic channel_status_c119_channel_free_qs; - logic channel_status_c119_channel_free_wd; - logic channel_status_c119_channel_free_we; - logic channel_status_c119_channel_error_qs; - logic channel_status_c119_channel_error_wd; - logic channel_status_c119_channel_error_we; - logic [29:0] channel_status_c119_field1_qs; - logic [29:0] channel_status_c119_field1_wd; - logic channel_status_c119_field1_we; - logic [31:0] reserved_2_c119_qs; - logic [31:0] reserved_2_c119_wd; - logic reserved_2_c119_we; - logic channel_flags_c119_intr_enable_qs; - logic channel_flags_c119_intr_enable_wd; - logic channel_flags_c119_intr_enable_we; - logic [30:0] channel_flags_c119_field1_qs; - logic [30:0] channel_flags_c119_field1_wd; - logic channel_flags_c119_field1_we; - logic [31:0] length_c119_qs; - logic [31:0] length_c119_wd; - logic length_c119_we; - logic [7:0] message_header_c119_message_id_qs; - logic [7:0] message_header_c119_message_id_wd; - logic message_header_c119_message_id_we; - logic [1:0] message_header_c119_message_type_qs; - logic [1:0] message_header_c119_message_type_wd; - logic message_header_c119_message_type_we; - logic [7:0] message_header_c119_protocol_id_qs; - logic [7:0] message_header_c119_protocol_id_wd; - logic message_header_c119_protocol_id_we; - logic [9:0] message_header_c119_token_qs; - logic [9:0] message_header_c119_token_wd; - logic message_header_c119_token_we; - logic [3:0] message_header_c119_field1_qs; - logic [3:0] message_header_c119_field1_wd; - logic message_header_c119_field1_we; - logic [31:0] message_payload_1_c119_qs; - logic [31:0] message_payload_1_c119_wd; - logic message_payload_1_c119_we; - logic doorbell_c119_intr_qs; - logic doorbell_c119_intr_wd; - logic doorbell_c119_intr_we; - logic [30:0] doorbell_c119_preserve_mask_qs; - logic [30:0] doorbell_c119_preserve_mask_wd; - logic doorbell_c119_preserve_mask_we; - logic completion_interrupt_c119_intr_qs; - logic completion_interrupt_c119_intr_wd; - logic completion_interrupt_c119_intr_we; - logic [30:0] completion_interrupt_c119_preserve_mask_qs; - logic [30:0] completion_interrupt_c119_preserve_mask_wd; - logic completion_interrupt_c119_preserve_mask_we; - logic [31:0] reserved_1_c120_qs; - logic [31:0] reserved_1_c120_wd; - logic reserved_1_c120_we; - logic channel_status_c120_channel_free_qs; - logic channel_status_c120_channel_free_wd; - logic channel_status_c120_channel_free_we; - logic channel_status_c120_channel_error_qs; - logic channel_status_c120_channel_error_wd; - logic channel_status_c120_channel_error_we; - logic [29:0] channel_status_c120_field1_qs; - logic [29:0] channel_status_c120_field1_wd; - logic channel_status_c120_field1_we; - logic [31:0] reserved_2_c120_qs; - logic [31:0] reserved_2_c120_wd; - logic reserved_2_c120_we; - logic channel_flags_c120_intr_enable_qs; - logic channel_flags_c120_intr_enable_wd; - logic channel_flags_c120_intr_enable_we; - logic [30:0] channel_flags_c120_field1_qs; - logic [30:0] channel_flags_c120_field1_wd; - logic channel_flags_c120_field1_we; - logic [31:0] length_c120_qs; - logic [31:0] length_c120_wd; - logic length_c120_we; - logic [7:0] message_header_c120_message_id_qs; - logic [7:0] message_header_c120_message_id_wd; - logic message_header_c120_message_id_we; - logic [1:0] message_header_c120_message_type_qs; - logic [1:0] message_header_c120_message_type_wd; - logic message_header_c120_message_type_we; - logic [7:0] message_header_c120_protocol_id_qs; - logic [7:0] message_header_c120_protocol_id_wd; - logic message_header_c120_protocol_id_we; - logic [9:0] message_header_c120_token_qs; - logic [9:0] message_header_c120_token_wd; - logic message_header_c120_token_we; - logic [3:0] message_header_c120_field1_qs; - logic [3:0] message_header_c120_field1_wd; - logic message_header_c120_field1_we; - logic [31:0] message_payload_1_c120_qs; - logic [31:0] message_payload_1_c120_wd; - logic message_payload_1_c120_we; - logic doorbell_c120_intr_qs; - logic doorbell_c120_intr_wd; - logic doorbell_c120_intr_we; - logic [30:0] doorbell_c120_preserve_mask_qs; - logic [30:0] doorbell_c120_preserve_mask_wd; - logic doorbell_c120_preserve_mask_we; - logic completion_interrupt_c120_intr_qs; - logic completion_interrupt_c120_intr_wd; - logic completion_interrupt_c120_intr_we; - logic [30:0] completion_interrupt_c120_preserve_mask_qs; - logic [30:0] completion_interrupt_c120_preserve_mask_wd; - logic completion_interrupt_c120_preserve_mask_we; - logic [31:0] reserved_1_c121_qs; - logic [31:0] reserved_1_c121_wd; - logic reserved_1_c121_we; - logic channel_status_c121_channel_free_qs; - logic channel_status_c121_channel_free_wd; - logic channel_status_c121_channel_free_we; - logic channel_status_c121_channel_error_qs; - logic channel_status_c121_channel_error_wd; - logic channel_status_c121_channel_error_we; - logic [29:0] channel_status_c121_field1_qs; - logic [29:0] channel_status_c121_field1_wd; - logic channel_status_c121_field1_we; - logic [31:0] reserved_2_c121_qs; - logic [31:0] reserved_2_c121_wd; - logic reserved_2_c121_we; - logic channel_flags_c121_intr_enable_qs; - logic channel_flags_c121_intr_enable_wd; - logic channel_flags_c121_intr_enable_we; - logic [30:0] channel_flags_c121_field1_qs; - logic [30:0] channel_flags_c121_field1_wd; - logic channel_flags_c121_field1_we; - logic [31:0] length_c121_qs; - logic [31:0] length_c121_wd; - logic length_c121_we; - logic [7:0] message_header_c121_message_id_qs; - logic [7:0] message_header_c121_message_id_wd; - logic message_header_c121_message_id_we; - logic [1:0] message_header_c121_message_type_qs; - logic [1:0] message_header_c121_message_type_wd; - logic message_header_c121_message_type_we; - logic [7:0] message_header_c121_protocol_id_qs; - logic [7:0] message_header_c121_protocol_id_wd; - logic message_header_c121_protocol_id_we; - logic [9:0] message_header_c121_token_qs; - logic [9:0] message_header_c121_token_wd; - logic message_header_c121_token_we; - logic [3:0] message_header_c121_field1_qs; - logic [3:0] message_header_c121_field1_wd; - logic message_header_c121_field1_we; - logic [31:0] message_payload_1_c121_qs; - logic [31:0] message_payload_1_c121_wd; - logic message_payload_1_c121_we; - logic doorbell_c121_intr_qs; - logic doorbell_c121_intr_wd; - logic doorbell_c121_intr_we; - logic [30:0] doorbell_c121_preserve_mask_qs; - logic [30:0] doorbell_c121_preserve_mask_wd; - logic doorbell_c121_preserve_mask_we; - logic completion_interrupt_c121_intr_qs; - logic completion_interrupt_c121_intr_wd; - logic completion_interrupt_c121_intr_we; - logic [30:0] completion_interrupt_c121_preserve_mask_qs; - logic [30:0] completion_interrupt_c121_preserve_mask_wd; - logic completion_interrupt_c121_preserve_mask_we; - logic [31:0] reserved_1_c122_qs; - logic [31:0] reserved_1_c122_wd; - logic reserved_1_c122_we; - logic channel_status_c122_channel_free_qs; - logic channel_status_c122_channel_free_wd; - logic channel_status_c122_channel_free_we; - logic channel_status_c122_channel_error_qs; - logic channel_status_c122_channel_error_wd; - logic channel_status_c122_channel_error_we; - logic [29:0] channel_status_c122_field1_qs; - logic [29:0] channel_status_c122_field1_wd; - logic channel_status_c122_field1_we; - logic [31:0] reserved_2_c122_qs; - logic [31:0] reserved_2_c122_wd; - logic reserved_2_c122_we; - logic channel_flags_c122_intr_enable_qs; - logic channel_flags_c122_intr_enable_wd; - logic channel_flags_c122_intr_enable_we; - logic [30:0] channel_flags_c122_field1_qs; - logic [30:0] channel_flags_c122_field1_wd; - logic channel_flags_c122_field1_we; - logic [31:0] length_c122_qs; - logic [31:0] length_c122_wd; - logic length_c122_we; - logic [7:0] message_header_c122_message_id_qs; - logic [7:0] message_header_c122_message_id_wd; - logic message_header_c122_message_id_we; - logic [1:0] message_header_c122_message_type_qs; - logic [1:0] message_header_c122_message_type_wd; - logic message_header_c122_message_type_we; - logic [7:0] message_header_c122_protocol_id_qs; - logic [7:0] message_header_c122_protocol_id_wd; - logic message_header_c122_protocol_id_we; - logic [9:0] message_header_c122_token_qs; - logic [9:0] message_header_c122_token_wd; - logic message_header_c122_token_we; - logic [3:0] message_header_c122_field1_qs; - logic [3:0] message_header_c122_field1_wd; - logic message_header_c122_field1_we; - logic [31:0] message_payload_1_c122_qs; - logic [31:0] message_payload_1_c122_wd; - logic message_payload_1_c122_we; - logic doorbell_c122_intr_qs; - logic doorbell_c122_intr_wd; - logic doorbell_c122_intr_we; - logic [30:0] doorbell_c122_preserve_mask_qs; - logic [30:0] doorbell_c122_preserve_mask_wd; - logic doorbell_c122_preserve_mask_we; - logic completion_interrupt_c122_intr_qs; - logic completion_interrupt_c122_intr_wd; - logic completion_interrupt_c122_intr_we; - logic [30:0] completion_interrupt_c122_preserve_mask_qs; - logic [30:0] completion_interrupt_c122_preserve_mask_wd; - logic completion_interrupt_c122_preserve_mask_we; - logic [31:0] reserved_1_c123_qs; - logic [31:0] reserved_1_c123_wd; - logic reserved_1_c123_we; - logic channel_status_c123_channel_free_qs; - logic channel_status_c123_channel_free_wd; - logic channel_status_c123_channel_free_we; - logic channel_status_c123_channel_error_qs; - logic channel_status_c123_channel_error_wd; - logic channel_status_c123_channel_error_we; - logic [29:0] channel_status_c123_field1_qs; - logic [29:0] channel_status_c123_field1_wd; - logic channel_status_c123_field1_we; - logic [31:0] reserved_2_c123_qs; - logic [31:0] reserved_2_c123_wd; - logic reserved_2_c123_we; - logic channel_flags_c123_intr_enable_qs; - logic channel_flags_c123_intr_enable_wd; - logic channel_flags_c123_intr_enable_we; - logic [30:0] channel_flags_c123_field1_qs; - logic [30:0] channel_flags_c123_field1_wd; - logic channel_flags_c123_field1_we; - logic [31:0] length_c123_qs; - logic [31:0] length_c123_wd; - logic length_c123_we; - logic [7:0] message_header_c123_message_id_qs; - logic [7:0] message_header_c123_message_id_wd; - logic message_header_c123_message_id_we; - logic [1:0] message_header_c123_message_type_qs; - logic [1:0] message_header_c123_message_type_wd; - logic message_header_c123_message_type_we; - logic [7:0] message_header_c123_protocol_id_qs; - logic [7:0] message_header_c123_protocol_id_wd; - logic message_header_c123_protocol_id_we; - logic [9:0] message_header_c123_token_qs; - logic [9:0] message_header_c123_token_wd; - logic message_header_c123_token_we; - logic [3:0] message_header_c123_field1_qs; - logic [3:0] message_header_c123_field1_wd; - logic message_header_c123_field1_we; - logic [31:0] message_payload_1_c123_qs; - logic [31:0] message_payload_1_c123_wd; - logic message_payload_1_c123_we; - logic doorbell_c123_intr_qs; - logic doorbell_c123_intr_wd; - logic doorbell_c123_intr_we; - logic [30:0] doorbell_c123_preserve_mask_qs; - logic [30:0] doorbell_c123_preserve_mask_wd; - logic doorbell_c123_preserve_mask_we; - logic completion_interrupt_c123_intr_qs; - logic completion_interrupt_c123_intr_wd; - logic completion_interrupt_c123_intr_we; - logic [30:0] completion_interrupt_c123_preserve_mask_qs; - logic [30:0] completion_interrupt_c123_preserve_mask_wd; - logic completion_interrupt_c123_preserve_mask_we; - logic [31:0] reserved_1_c124_qs; - logic [31:0] reserved_1_c124_wd; - logic reserved_1_c124_we; - logic channel_status_c124_channel_free_qs; - logic channel_status_c124_channel_free_wd; - logic channel_status_c124_channel_free_we; - logic channel_status_c124_channel_error_qs; - logic channel_status_c124_channel_error_wd; - logic channel_status_c124_channel_error_we; - logic [29:0] channel_status_c124_field1_qs; - logic [29:0] channel_status_c124_field1_wd; - logic channel_status_c124_field1_we; - logic [31:0] reserved_2_c124_qs; - logic [31:0] reserved_2_c124_wd; - logic reserved_2_c124_we; - logic channel_flags_c124_intr_enable_qs; - logic channel_flags_c124_intr_enable_wd; - logic channel_flags_c124_intr_enable_we; - logic [30:0] channel_flags_c124_field1_qs; - logic [30:0] channel_flags_c124_field1_wd; - logic channel_flags_c124_field1_we; - logic [31:0] length_c124_qs; - logic [31:0] length_c124_wd; - logic length_c124_we; - logic [7:0] message_header_c124_message_id_qs; - logic [7:0] message_header_c124_message_id_wd; - logic message_header_c124_message_id_we; - logic [1:0] message_header_c124_message_type_qs; - logic [1:0] message_header_c124_message_type_wd; - logic message_header_c124_message_type_we; - logic [7:0] message_header_c124_protocol_id_qs; - logic [7:0] message_header_c124_protocol_id_wd; - logic message_header_c124_protocol_id_we; - logic [9:0] message_header_c124_token_qs; - logic [9:0] message_header_c124_token_wd; - logic message_header_c124_token_we; - logic [3:0] message_header_c124_field1_qs; - logic [3:0] message_header_c124_field1_wd; - logic message_header_c124_field1_we; - logic [31:0] message_payload_1_c124_qs; - logic [31:0] message_payload_1_c124_wd; - logic message_payload_1_c124_we; - logic doorbell_c124_intr_qs; - logic doorbell_c124_intr_wd; - logic doorbell_c124_intr_we; - logic [30:0] doorbell_c124_preserve_mask_qs; - logic [30:0] doorbell_c124_preserve_mask_wd; - logic doorbell_c124_preserve_mask_we; - logic completion_interrupt_c124_intr_qs; - logic completion_interrupt_c124_intr_wd; - logic completion_interrupt_c124_intr_we; - logic [30:0] completion_interrupt_c124_preserve_mask_qs; - logic [30:0] completion_interrupt_c124_preserve_mask_wd; - logic completion_interrupt_c124_preserve_mask_we; - logic [31:0] reserved_1_c125_qs; - logic [31:0] reserved_1_c125_wd; - logic reserved_1_c125_we; - logic channel_status_c125_channel_free_qs; - logic channel_status_c125_channel_free_wd; - logic channel_status_c125_channel_free_we; - logic channel_status_c125_channel_error_qs; - logic channel_status_c125_channel_error_wd; - logic channel_status_c125_channel_error_we; - logic [29:0] channel_status_c125_field1_qs; - logic [29:0] channel_status_c125_field1_wd; - logic channel_status_c125_field1_we; - logic [31:0] reserved_2_c125_qs; - logic [31:0] reserved_2_c125_wd; - logic reserved_2_c125_we; - logic channel_flags_c125_intr_enable_qs; - logic channel_flags_c125_intr_enable_wd; - logic channel_flags_c125_intr_enable_we; - logic [30:0] channel_flags_c125_field1_qs; - logic [30:0] channel_flags_c125_field1_wd; - logic channel_flags_c125_field1_we; - logic [31:0] length_c125_qs; - logic [31:0] length_c125_wd; - logic length_c125_we; - logic [7:0] message_header_c125_message_id_qs; - logic [7:0] message_header_c125_message_id_wd; - logic message_header_c125_message_id_we; - logic [1:0] message_header_c125_message_type_qs; - logic [1:0] message_header_c125_message_type_wd; - logic message_header_c125_message_type_we; - logic [7:0] message_header_c125_protocol_id_qs; - logic [7:0] message_header_c125_protocol_id_wd; - logic message_header_c125_protocol_id_we; - logic [9:0] message_header_c125_token_qs; - logic [9:0] message_header_c125_token_wd; - logic message_header_c125_token_we; - logic [3:0] message_header_c125_field1_qs; - logic [3:0] message_header_c125_field1_wd; - logic message_header_c125_field1_we; - logic [31:0] message_payload_1_c125_qs; - logic [31:0] message_payload_1_c125_wd; - logic message_payload_1_c125_we; - logic doorbell_c125_intr_qs; - logic doorbell_c125_intr_wd; - logic doorbell_c125_intr_we; - logic [30:0] doorbell_c125_preserve_mask_qs; - logic [30:0] doorbell_c125_preserve_mask_wd; - logic doorbell_c125_preserve_mask_we; - logic completion_interrupt_c125_intr_qs; - logic completion_interrupt_c125_intr_wd; - logic completion_interrupt_c125_intr_we; - logic [30:0] completion_interrupt_c125_preserve_mask_qs; - logic [30:0] completion_interrupt_c125_preserve_mask_wd; - logic completion_interrupt_c125_preserve_mask_we; - logic [31:0] reserved_1_c126_qs; - logic [31:0] reserved_1_c126_wd; - logic reserved_1_c126_we; - logic channel_status_c126_channel_free_qs; - logic channel_status_c126_channel_free_wd; - logic channel_status_c126_channel_free_we; - logic channel_status_c126_channel_error_qs; - logic channel_status_c126_channel_error_wd; - logic channel_status_c126_channel_error_we; - logic [29:0] channel_status_c126_field1_qs; - logic [29:0] channel_status_c126_field1_wd; - logic channel_status_c126_field1_we; - logic [31:0] reserved_2_c126_qs; - logic [31:0] reserved_2_c126_wd; - logic reserved_2_c126_we; - logic channel_flags_c126_intr_enable_qs; - logic channel_flags_c126_intr_enable_wd; - logic channel_flags_c126_intr_enable_we; - logic [30:0] channel_flags_c126_field1_qs; - logic [30:0] channel_flags_c126_field1_wd; - logic channel_flags_c126_field1_we; - logic [31:0] length_c126_qs; - logic [31:0] length_c126_wd; - logic length_c126_we; - logic [7:0] message_header_c126_message_id_qs; - logic [7:0] message_header_c126_message_id_wd; - logic message_header_c126_message_id_we; - logic [1:0] message_header_c126_message_type_qs; - logic [1:0] message_header_c126_message_type_wd; - logic message_header_c126_message_type_we; - logic [7:0] message_header_c126_protocol_id_qs; - logic [7:0] message_header_c126_protocol_id_wd; - logic message_header_c126_protocol_id_we; - logic [9:0] message_header_c126_token_qs; - logic [9:0] message_header_c126_token_wd; - logic message_header_c126_token_we; - logic [3:0] message_header_c126_field1_qs; - logic [3:0] message_header_c126_field1_wd; - logic message_header_c126_field1_we; - logic [31:0] message_payload_1_c126_qs; - logic [31:0] message_payload_1_c126_wd; - logic message_payload_1_c126_we; - logic doorbell_c126_intr_qs; - logic doorbell_c126_intr_wd; - logic doorbell_c126_intr_we; - logic [30:0] doorbell_c126_preserve_mask_qs; - logic [30:0] doorbell_c126_preserve_mask_wd; - logic doorbell_c126_preserve_mask_we; - logic completion_interrupt_c126_intr_qs; - logic completion_interrupt_c126_intr_wd; - logic completion_interrupt_c126_intr_we; - logic [30:0] completion_interrupt_c126_preserve_mask_qs; - logic [30:0] completion_interrupt_c126_preserve_mask_wd; - logic completion_interrupt_c126_preserve_mask_we; - logic [31:0] reserved_1_c127_qs; - logic [31:0] reserved_1_c127_wd; - logic reserved_1_c127_we; - logic channel_status_c127_channel_free_qs; - logic channel_status_c127_channel_free_wd; - logic channel_status_c127_channel_free_we; - logic channel_status_c127_channel_error_qs; - logic channel_status_c127_channel_error_wd; - logic channel_status_c127_channel_error_we; - logic [29:0] channel_status_c127_field1_qs; - logic [29:0] channel_status_c127_field1_wd; - logic channel_status_c127_field1_we; - logic [31:0] reserved_2_c127_qs; - logic [31:0] reserved_2_c127_wd; - logic reserved_2_c127_we; - logic channel_flags_c127_intr_enable_qs; - logic channel_flags_c127_intr_enable_wd; - logic channel_flags_c127_intr_enable_we; - logic [30:0] channel_flags_c127_field1_qs; - logic [30:0] channel_flags_c127_field1_wd; - logic channel_flags_c127_field1_we; - logic [31:0] length_c127_qs; - logic [31:0] length_c127_wd; - logic length_c127_we; - logic [7:0] message_header_c127_message_id_qs; - logic [7:0] message_header_c127_message_id_wd; - logic message_header_c127_message_id_we; - logic [1:0] message_header_c127_message_type_qs; - logic [1:0] message_header_c127_message_type_wd; - logic message_header_c127_message_type_we; - logic [7:0] message_header_c127_protocol_id_qs; - logic [7:0] message_header_c127_protocol_id_wd; - logic message_header_c127_protocol_id_we; - logic [9:0] message_header_c127_token_qs; - logic [9:0] message_header_c127_token_wd; - logic message_header_c127_token_we; - logic [3:0] message_header_c127_field1_qs; - logic [3:0] message_header_c127_field1_wd; - logic message_header_c127_field1_we; - logic [31:0] message_payload_1_c127_qs; - logic [31:0] message_payload_1_c127_wd; - logic message_payload_1_c127_we; - logic doorbell_c127_intr_qs; - logic doorbell_c127_intr_wd; - logic doorbell_c127_intr_we; - logic [30:0] doorbell_c127_preserve_mask_qs; - logic [30:0] doorbell_c127_preserve_mask_wd; - logic doorbell_c127_preserve_mask_we; - logic completion_interrupt_c127_intr_qs; - logic completion_interrupt_c127_intr_wd; - logic completion_interrupt_c127_intr_we; - logic [30:0] completion_interrupt_c127_preserve_mask_qs; - logic [30:0] completion_interrupt_c127_preserve_mask_wd; - logic completion_interrupt_c127_preserve_mask_we; - logic [31:0] reserved_1_c128_qs; - logic [31:0] reserved_1_c128_wd; - logic reserved_1_c128_we; - logic channel_status_c128_channel_free_qs; - logic channel_status_c128_channel_free_wd; - logic channel_status_c128_channel_free_we; - logic channel_status_c128_channel_error_qs; - logic channel_status_c128_channel_error_wd; - logic channel_status_c128_channel_error_we; - logic [29:0] channel_status_c128_field1_qs; - logic [29:0] channel_status_c128_field1_wd; - logic channel_status_c128_field1_we; - logic [31:0] reserved_2_c128_qs; - logic [31:0] reserved_2_c128_wd; - logic reserved_2_c128_we; - logic channel_flags_c128_intr_enable_qs; - logic channel_flags_c128_intr_enable_wd; - logic channel_flags_c128_intr_enable_we; - logic [30:0] channel_flags_c128_field1_qs; - logic [30:0] channel_flags_c128_field1_wd; - logic channel_flags_c128_field1_we; - logic [31:0] length_c128_qs; - logic [31:0] length_c128_wd; - logic length_c128_we; - logic [7:0] message_header_c128_message_id_qs; - logic [7:0] message_header_c128_message_id_wd; - logic message_header_c128_message_id_we; - logic [1:0] message_header_c128_message_type_qs; - logic [1:0] message_header_c128_message_type_wd; - logic message_header_c128_message_type_we; - logic [7:0] message_header_c128_protocol_id_qs; - logic [7:0] message_header_c128_protocol_id_wd; - logic message_header_c128_protocol_id_we; - logic [9:0] message_header_c128_token_qs; - logic [9:0] message_header_c128_token_wd; - logic message_header_c128_token_we; - logic [3:0] message_header_c128_field1_qs; - logic [3:0] message_header_c128_field1_wd; - logic message_header_c128_field1_we; - logic [31:0] message_payload_1_c128_qs; - logic [31:0] message_payload_1_c128_wd; - logic message_payload_1_c128_we; - logic doorbell_c128_intr_qs; - logic doorbell_c128_intr_wd; - logic doorbell_c128_intr_we; - logic [30:0] doorbell_c128_preserve_mask_qs; - logic [30:0] doorbell_c128_preserve_mask_wd; - logic doorbell_c128_preserve_mask_we; - logic completion_interrupt_c128_intr_qs; - logic completion_interrupt_c128_intr_wd; - logic completion_interrupt_c128_intr_we; - logic [30:0] completion_interrupt_c128_preserve_mask_qs; - logic [30:0] completion_interrupt_c128_preserve_mask_wd; - logic completion_interrupt_c128_preserve_mask_we; - logic [31:0] reserved_1_c129_qs; - logic [31:0] reserved_1_c129_wd; - logic reserved_1_c129_we; - logic channel_status_c129_channel_free_qs; - logic channel_status_c129_channel_free_wd; - logic channel_status_c129_channel_free_we; - logic channel_status_c129_channel_error_qs; - logic channel_status_c129_channel_error_wd; - logic channel_status_c129_channel_error_we; - logic [29:0] channel_status_c129_field1_qs; - logic [29:0] channel_status_c129_field1_wd; - logic channel_status_c129_field1_we; - logic [31:0] reserved_2_c129_qs; - logic [31:0] reserved_2_c129_wd; - logic reserved_2_c129_we; - logic channel_flags_c129_intr_enable_qs; - logic channel_flags_c129_intr_enable_wd; - logic channel_flags_c129_intr_enable_we; - logic [30:0] channel_flags_c129_field1_qs; - logic [30:0] channel_flags_c129_field1_wd; - logic channel_flags_c129_field1_we; - logic [31:0] length_c129_qs; - logic [31:0] length_c129_wd; - logic length_c129_we; - logic [7:0] message_header_c129_message_id_qs; - logic [7:0] message_header_c129_message_id_wd; - logic message_header_c129_message_id_we; - logic [1:0] message_header_c129_message_type_qs; - logic [1:0] message_header_c129_message_type_wd; - logic message_header_c129_message_type_we; - logic [7:0] message_header_c129_protocol_id_qs; - logic [7:0] message_header_c129_protocol_id_wd; - logic message_header_c129_protocol_id_we; - logic [9:0] message_header_c129_token_qs; - logic [9:0] message_header_c129_token_wd; - logic message_header_c129_token_we; - logic [3:0] message_header_c129_field1_qs; - logic [3:0] message_header_c129_field1_wd; - logic message_header_c129_field1_we; - logic [31:0] message_payload_1_c129_qs; - logic [31:0] message_payload_1_c129_wd; - logic message_payload_1_c129_we; - logic doorbell_c129_intr_qs; - logic doorbell_c129_intr_wd; - logic doorbell_c129_intr_we; - logic [30:0] doorbell_c129_preserve_mask_qs; - logic [30:0] doorbell_c129_preserve_mask_wd; - logic doorbell_c129_preserve_mask_we; - logic completion_interrupt_c129_intr_qs; - logic completion_interrupt_c129_intr_wd; - logic completion_interrupt_c129_intr_we; - logic [30:0] completion_interrupt_c129_preserve_mask_qs; - logic [30:0] completion_interrupt_c129_preserve_mask_wd; - logic completion_interrupt_c129_preserve_mask_we; - logic [31:0] reserved_1_c130_qs; - logic [31:0] reserved_1_c130_wd; - logic reserved_1_c130_we; - logic channel_status_c130_channel_free_qs; - logic channel_status_c130_channel_free_wd; - logic channel_status_c130_channel_free_we; - logic channel_status_c130_channel_error_qs; - logic channel_status_c130_channel_error_wd; - logic channel_status_c130_channel_error_we; - logic [29:0] channel_status_c130_field1_qs; - logic [29:0] channel_status_c130_field1_wd; - logic channel_status_c130_field1_we; - logic [31:0] reserved_2_c130_qs; - logic [31:0] reserved_2_c130_wd; - logic reserved_2_c130_we; - logic channel_flags_c130_intr_enable_qs; - logic channel_flags_c130_intr_enable_wd; - logic channel_flags_c130_intr_enable_we; - logic [30:0] channel_flags_c130_field1_qs; - logic [30:0] channel_flags_c130_field1_wd; - logic channel_flags_c130_field1_we; - logic [31:0] length_c130_qs; - logic [31:0] length_c130_wd; - logic length_c130_we; - logic [7:0] message_header_c130_message_id_qs; - logic [7:0] message_header_c130_message_id_wd; - logic message_header_c130_message_id_we; - logic [1:0] message_header_c130_message_type_qs; - logic [1:0] message_header_c130_message_type_wd; - logic message_header_c130_message_type_we; - logic [7:0] message_header_c130_protocol_id_qs; - logic [7:0] message_header_c130_protocol_id_wd; - logic message_header_c130_protocol_id_we; - logic [9:0] message_header_c130_token_qs; - logic [9:0] message_header_c130_token_wd; - logic message_header_c130_token_we; - logic [3:0] message_header_c130_field1_qs; - logic [3:0] message_header_c130_field1_wd; - logic message_header_c130_field1_we; - logic [31:0] message_payload_1_c130_qs; - logic [31:0] message_payload_1_c130_wd; - logic message_payload_1_c130_we; - logic doorbell_c130_intr_qs; - logic doorbell_c130_intr_wd; - logic doorbell_c130_intr_we; - logic [30:0] doorbell_c130_preserve_mask_qs; - logic [30:0] doorbell_c130_preserve_mask_wd; - logic doorbell_c130_preserve_mask_we; - logic completion_interrupt_c130_intr_qs; - logic completion_interrupt_c130_intr_wd; - logic completion_interrupt_c130_intr_we; - logic [30:0] completion_interrupt_c130_preserve_mask_qs; - logic [30:0] completion_interrupt_c130_preserve_mask_wd; - logic completion_interrupt_c130_preserve_mask_we; - logic [31:0] reserved_1_c131_qs; - logic [31:0] reserved_1_c131_wd; - logic reserved_1_c131_we; - logic channel_status_c131_channel_free_qs; - logic channel_status_c131_channel_free_wd; - logic channel_status_c131_channel_free_we; - logic channel_status_c131_channel_error_qs; - logic channel_status_c131_channel_error_wd; - logic channel_status_c131_channel_error_we; - logic [29:0] channel_status_c131_field1_qs; - logic [29:0] channel_status_c131_field1_wd; - logic channel_status_c131_field1_we; - logic [31:0] reserved_2_c131_qs; - logic [31:0] reserved_2_c131_wd; - logic reserved_2_c131_we; - logic channel_flags_c131_intr_enable_qs; - logic channel_flags_c131_intr_enable_wd; - logic channel_flags_c131_intr_enable_we; - logic [30:0] channel_flags_c131_field1_qs; - logic [30:0] channel_flags_c131_field1_wd; - logic channel_flags_c131_field1_we; - logic [31:0] length_c131_qs; - logic [31:0] length_c131_wd; - logic length_c131_we; - logic [7:0] message_header_c131_message_id_qs; - logic [7:0] message_header_c131_message_id_wd; - logic message_header_c131_message_id_we; - logic [1:0] message_header_c131_message_type_qs; - logic [1:0] message_header_c131_message_type_wd; - logic message_header_c131_message_type_we; - logic [7:0] message_header_c131_protocol_id_qs; - logic [7:0] message_header_c131_protocol_id_wd; - logic message_header_c131_protocol_id_we; - logic [9:0] message_header_c131_token_qs; - logic [9:0] message_header_c131_token_wd; - logic message_header_c131_token_we; - logic [3:0] message_header_c131_field1_qs; - logic [3:0] message_header_c131_field1_wd; - logic message_header_c131_field1_we; - logic [31:0] message_payload_1_c131_qs; - logic [31:0] message_payload_1_c131_wd; - logic message_payload_1_c131_we; - logic doorbell_c131_intr_qs; - logic doorbell_c131_intr_wd; - logic doorbell_c131_intr_we; - logic [30:0] doorbell_c131_preserve_mask_qs; - logic [30:0] doorbell_c131_preserve_mask_wd; - logic doorbell_c131_preserve_mask_we; - logic completion_interrupt_c131_intr_qs; - logic completion_interrupt_c131_intr_wd; - logic completion_interrupt_c131_intr_we; - logic [30:0] completion_interrupt_c131_preserve_mask_qs; - logic [30:0] completion_interrupt_c131_preserve_mask_wd; - logic completion_interrupt_c131_preserve_mask_we; - logic [31:0] reserved_1_c132_qs; - logic [31:0] reserved_1_c132_wd; - logic reserved_1_c132_we; - logic channel_status_c132_channel_free_qs; - logic channel_status_c132_channel_free_wd; - logic channel_status_c132_channel_free_we; - logic channel_status_c132_channel_error_qs; - logic channel_status_c132_channel_error_wd; - logic channel_status_c132_channel_error_we; - logic [29:0] channel_status_c132_field1_qs; - logic [29:0] channel_status_c132_field1_wd; - logic channel_status_c132_field1_we; - logic [31:0] reserved_2_c132_qs; - logic [31:0] reserved_2_c132_wd; - logic reserved_2_c132_we; - logic channel_flags_c132_intr_enable_qs; - logic channel_flags_c132_intr_enable_wd; - logic channel_flags_c132_intr_enable_we; - logic [30:0] channel_flags_c132_field1_qs; - logic [30:0] channel_flags_c132_field1_wd; - logic channel_flags_c132_field1_we; - logic [31:0] length_c132_qs; - logic [31:0] length_c132_wd; - logic length_c132_we; - logic [7:0] message_header_c132_message_id_qs; - logic [7:0] message_header_c132_message_id_wd; - logic message_header_c132_message_id_we; - logic [1:0] message_header_c132_message_type_qs; - logic [1:0] message_header_c132_message_type_wd; - logic message_header_c132_message_type_we; - logic [7:0] message_header_c132_protocol_id_qs; - logic [7:0] message_header_c132_protocol_id_wd; - logic message_header_c132_protocol_id_we; - logic [9:0] message_header_c132_token_qs; - logic [9:0] message_header_c132_token_wd; - logic message_header_c132_token_we; - logic [3:0] message_header_c132_field1_qs; - logic [3:0] message_header_c132_field1_wd; - logic message_header_c132_field1_we; - logic [31:0] message_payload_1_c132_qs; - logic [31:0] message_payload_1_c132_wd; - logic message_payload_1_c132_we; - logic doorbell_c132_intr_qs; - logic doorbell_c132_intr_wd; - logic doorbell_c132_intr_we; - logic [30:0] doorbell_c132_preserve_mask_qs; - logic [30:0] doorbell_c132_preserve_mask_wd; - logic doorbell_c132_preserve_mask_we; - logic completion_interrupt_c132_intr_qs; - logic completion_interrupt_c132_intr_wd; - logic completion_interrupt_c132_intr_we; - logic [30:0] completion_interrupt_c132_preserve_mask_qs; - logic [30:0] completion_interrupt_c132_preserve_mask_wd; - logic completion_interrupt_c132_preserve_mask_we; - logic [31:0] reserved_1_c133_qs; - logic [31:0] reserved_1_c133_wd; - logic reserved_1_c133_we; - logic channel_status_c133_channel_free_qs; - logic channel_status_c133_channel_free_wd; - logic channel_status_c133_channel_free_we; - logic channel_status_c133_channel_error_qs; - logic channel_status_c133_channel_error_wd; - logic channel_status_c133_channel_error_we; - logic [29:0] channel_status_c133_field1_qs; - logic [29:0] channel_status_c133_field1_wd; - logic channel_status_c133_field1_we; - logic [31:0] reserved_2_c133_qs; - logic [31:0] reserved_2_c133_wd; - logic reserved_2_c133_we; - logic channel_flags_c133_intr_enable_qs; - logic channel_flags_c133_intr_enable_wd; - logic channel_flags_c133_intr_enable_we; - logic [30:0] channel_flags_c133_field1_qs; - logic [30:0] channel_flags_c133_field1_wd; - logic channel_flags_c133_field1_we; - logic [31:0] length_c133_qs; - logic [31:0] length_c133_wd; - logic length_c133_we; - logic [7:0] message_header_c133_message_id_qs; - logic [7:0] message_header_c133_message_id_wd; - logic message_header_c133_message_id_we; - logic [1:0] message_header_c133_message_type_qs; - logic [1:0] message_header_c133_message_type_wd; - logic message_header_c133_message_type_we; - logic [7:0] message_header_c133_protocol_id_qs; - logic [7:0] message_header_c133_protocol_id_wd; - logic message_header_c133_protocol_id_we; - logic [9:0] message_header_c133_token_qs; - logic [9:0] message_header_c133_token_wd; - logic message_header_c133_token_we; - logic [3:0] message_header_c133_field1_qs; - logic [3:0] message_header_c133_field1_wd; - logic message_header_c133_field1_we; - logic [31:0] message_payload_1_c133_qs; - logic [31:0] message_payload_1_c133_wd; - logic message_payload_1_c133_we; - logic doorbell_c133_intr_qs; - logic doorbell_c133_intr_wd; - logic doorbell_c133_intr_we; - logic [30:0] doorbell_c133_preserve_mask_qs; - logic [30:0] doorbell_c133_preserve_mask_wd; - logic doorbell_c133_preserve_mask_we; - logic completion_interrupt_c133_intr_qs; - logic completion_interrupt_c133_intr_wd; - logic completion_interrupt_c133_intr_we; - logic [30:0] completion_interrupt_c133_preserve_mask_qs; - logic [30:0] completion_interrupt_c133_preserve_mask_wd; - logic completion_interrupt_c133_preserve_mask_we; - logic [31:0] reserved_1_c134_qs; - logic [31:0] reserved_1_c134_wd; - logic reserved_1_c134_we; - logic channel_status_c134_channel_free_qs; - logic channel_status_c134_channel_free_wd; - logic channel_status_c134_channel_free_we; - logic channel_status_c134_channel_error_qs; - logic channel_status_c134_channel_error_wd; - logic channel_status_c134_channel_error_we; - logic [29:0] channel_status_c134_field1_qs; - logic [29:0] channel_status_c134_field1_wd; - logic channel_status_c134_field1_we; - logic [31:0] reserved_2_c134_qs; - logic [31:0] reserved_2_c134_wd; - logic reserved_2_c134_we; - logic channel_flags_c134_intr_enable_qs; - logic channel_flags_c134_intr_enable_wd; - logic channel_flags_c134_intr_enable_we; - logic [30:0] channel_flags_c134_field1_qs; - logic [30:0] channel_flags_c134_field1_wd; - logic channel_flags_c134_field1_we; - logic [31:0] length_c134_qs; - logic [31:0] length_c134_wd; - logic length_c134_we; - logic [7:0] message_header_c134_message_id_qs; - logic [7:0] message_header_c134_message_id_wd; - logic message_header_c134_message_id_we; - logic [1:0] message_header_c134_message_type_qs; - logic [1:0] message_header_c134_message_type_wd; - logic message_header_c134_message_type_we; - logic [7:0] message_header_c134_protocol_id_qs; - logic [7:0] message_header_c134_protocol_id_wd; - logic message_header_c134_protocol_id_we; - logic [9:0] message_header_c134_token_qs; - logic [9:0] message_header_c134_token_wd; - logic message_header_c134_token_we; - logic [3:0] message_header_c134_field1_qs; - logic [3:0] message_header_c134_field1_wd; - logic message_header_c134_field1_we; - logic [31:0] message_payload_1_c134_qs; - logic [31:0] message_payload_1_c134_wd; - logic message_payload_1_c134_we; - logic doorbell_c134_intr_qs; - logic doorbell_c134_intr_wd; - logic doorbell_c134_intr_we; - logic [30:0] doorbell_c134_preserve_mask_qs; - logic [30:0] doorbell_c134_preserve_mask_wd; - logic doorbell_c134_preserve_mask_we; - logic completion_interrupt_c134_intr_qs; - logic completion_interrupt_c134_intr_wd; - logic completion_interrupt_c134_intr_we; - logic [30:0] completion_interrupt_c134_preserve_mask_qs; - logic [30:0] completion_interrupt_c134_preserve_mask_wd; - logic completion_interrupt_c134_preserve_mask_we; - logic [31:0] reserved_1_c135_qs; - logic [31:0] reserved_1_c135_wd; - logic reserved_1_c135_we; - logic channel_status_c135_channel_free_qs; - logic channel_status_c135_channel_free_wd; - logic channel_status_c135_channel_free_we; - logic channel_status_c135_channel_error_qs; - logic channel_status_c135_channel_error_wd; - logic channel_status_c135_channel_error_we; - logic [29:0] channel_status_c135_field1_qs; - logic [29:0] channel_status_c135_field1_wd; - logic channel_status_c135_field1_we; - logic [31:0] reserved_2_c135_qs; - logic [31:0] reserved_2_c135_wd; - logic reserved_2_c135_we; - logic channel_flags_c135_intr_enable_qs; - logic channel_flags_c135_intr_enable_wd; - logic channel_flags_c135_intr_enable_we; - logic [30:0] channel_flags_c135_field1_qs; - logic [30:0] channel_flags_c135_field1_wd; - logic channel_flags_c135_field1_we; - logic [31:0] length_c135_qs; - logic [31:0] length_c135_wd; - logic length_c135_we; - logic [7:0] message_header_c135_message_id_qs; - logic [7:0] message_header_c135_message_id_wd; - logic message_header_c135_message_id_we; - logic [1:0] message_header_c135_message_type_qs; - logic [1:0] message_header_c135_message_type_wd; - logic message_header_c135_message_type_we; - logic [7:0] message_header_c135_protocol_id_qs; - logic [7:0] message_header_c135_protocol_id_wd; - logic message_header_c135_protocol_id_we; - logic [9:0] message_header_c135_token_qs; - logic [9:0] message_header_c135_token_wd; - logic message_header_c135_token_we; - logic [3:0] message_header_c135_field1_qs; - logic [3:0] message_header_c135_field1_wd; - logic message_header_c135_field1_we; - logic [31:0] message_payload_1_c135_qs; - logic [31:0] message_payload_1_c135_wd; - logic message_payload_1_c135_we; - logic doorbell_c135_intr_qs; - logic doorbell_c135_intr_wd; - logic doorbell_c135_intr_we; - logic [30:0] doorbell_c135_preserve_mask_qs; - logic [30:0] doorbell_c135_preserve_mask_wd; - logic doorbell_c135_preserve_mask_we; - logic completion_interrupt_c135_intr_qs; - logic completion_interrupt_c135_intr_wd; - logic completion_interrupt_c135_intr_we; - logic [30:0] completion_interrupt_c135_preserve_mask_qs; - logic [30:0] completion_interrupt_c135_preserve_mask_wd; - logic completion_interrupt_c135_preserve_mask_we; - logic [31:0] reserved_1_c136_qs; - logic [31:0] reserved_1_c136_wd; - logic reserved_1_c136_we; - logic channel_status_c136_channel_free_qs; - logic channel_status_c136_channel_free_wd; - logic channel_status_c136_channel_free_we; - logic channel_status_c136_channel_error_qs; - logic channel_status_c136_channel_error_wd; - logic channel_status_c136_channel_error_we; - logic [29:0] channel_status_c136_field1_qs; - logic [29:0] channel_status_c136_field1_wd; - logic channel_status_c136_field1_we; - logic [31:0] reserved_2_c136_qs; - logic [31:0] reserved_2_c136_wd; - logic reserved_2_c136_we; - logic channel_flags_c136_intr_enable_qs; - logic channel_flags_c136_intr_enable_wd; - logic channel_flags_c136_intr_enable_we; - logic [30:0] channel_flags_c136_field1_qs; - logic [30:0] channel_flags_c136_field1_wd; - logic channel_flags_c136_field1_we; - logic [31:0] length_c136_qs; - logic [31:0] length_c136_wd; - logic length_c136_we; - logic [7:0] message_header_c136_message_id_qs; - logic [7:0] message_header_c136_message_id_wd; - logic message_header_c136_message_id_we; - logic [1:0] message_header_c136_message_type_qs; - logic [1:0] message_header_c136_message_type_wd; - logic message_header_c136_message_type_we; - logic [7:0] message_header_c136_protocol_id_qs; - logic [7:0] message_header_c136_protocol_id_wd; - logic message_header_c136_protocol_id_we; - logic [9:0] message_header_c136_token_qs; - logic [9:0] message_header_c136_token_wd; - logic message_header_c136_token_we; - logic [3:0] message_header_c136_field1_qs; - logic [3:0] message_header_c136_field1_wd; - logic message_header_c136_field1_we; - logic [31:0] message_payload_1_c136_qs; - logic [31:0] message_payload_1_c136_wd; - logic message_payload_1_c136_we; - logic doorbell_c136_intr_qs; - logic doorbell_c136_intr_wd; - logic doorbell_c136_intr_we; - logic [30:0] doorbell_c136_preserve_mask_qs; - logic [30:0] doorbell_c136_preserve_mask_wd; - logic doorbell_c136_preserve_mask_we; - logic completion_interrupt_c136_intr_qs; - logic completion_interrupt_c136_intr_wd; - logic completion_interrupt_c136_intr_we; - logic [30:0] completion_interrupt_c136_preserve_mask_qs; - logic [30:0] completion_interrupt_c136_preserve_mask_wd; - logic completion_interrupt_c136_preserve_mask_we; - logic [31:0] reserved_1_c137_qs; - logic [31:0] reserved_1_c137_wd; - logic reserved_1_c137_we; - logic channel_status_c137_channel_free_qs; - logic channel_status_c137_channel_free_wd; - logic channel_status_c137_channel_free_we; - logic channel_status_c137_channel_error_qs; - logic channel_status_c137_channel_error_wd; - logic channel_status_c137_channel_error_we; - logic [29:0] channel_status_c137_field1_qs; - logic [29:0] channel_status_c137_field1_wd; - logic channel_status_c137_field1_we; - logic [31:0] reserved_2_c137_qs; - logic [31:0] reserved_2_c137_wd; - logic reserved_2_c137_we; - logic channel_flags_c137_intr_enable_qs; - logic channel_flags_c137_intr_enable_wd; - logic channel_flags_c137_intr_enable_we; - logic [30:0] channel_flags_c137_field1_qs; - logic [30:0] channel_flags_c137_field1_wd; - logic channel_flags_c137_field1_we; - logic [31:0] length_c137_qs; - logic [31:0] length_c137_wd; - logic length_c137_we; - logic [7:0] message_header_c137_message_id_qs; - logic [7:0] message_header_c137_message_id_wd; - logic message_header_c137_message_id_we; - logic [1:0] message_header_c137_message_type_qs; - logic [1:0] message_header_c137_message_type_wd; - logic message_header_c137_message_type_we; - logic [7:0] message_header_c137_protocol_id_qs; - logic [7:0] message_header_c137_protocol_id_wd; - logic message_header_c137_protocol_id_we; - logic [9:0] message_header_c137_token_qs; - logic [9:0] message_header_c137_token_wd; - logic message_header_c137_token_we; - logic [3:0] message_header_c137_field1_qs; - logic [3:0] message_header_c137_field1_wd; - logic message_header_c137_field1_we; - logic [31:0] message_payload_1_c137_qs; - logic [31:0] message_payload_1_c137_wd; - logic message_payload_1_c137_we; - logic doorbell_c137_intr_qs; - logic doorbell_c137_intr_wd; - logic doorbell_c137_intr_we; - logic [30:0] doorbell_c137_preserve_mask_qs; - logic [30:0] doorbell_c137_preserve_mask_wd; - logic doorbell_c137_preserve_mask_we; - logic completion_interrupt_c137_intr_qs; - logic completion_interrupt_c137_intr_wd; - logic completion_interrupt_c137_intr_we; - logic [30:0] completion_interrupt_c137_preserve_mask_qs; - logic [30:0] completion_interrupt_c137_preserve_mask_wd; - logic completion_interrupt_c137_preserve_mask_we; - logic [31:0] reserved_1_c138_qs; - logic [31:0] reserved_1_c138_wd; - logic reserved_1_c138_we; - logic channel_status_c138_channel_free_qs; - logic channel_status_c138_channel_free_wd; - logic channel_status_c138_channel_free_we; - logic channel_status_c138_channel_error_qs; - logic channel_status_c138_channel_error_wd; - logic channel_status_c138_channel_error_we; - logic [29:0] channel_status_c138_field1_qs; - logic [29:0] channel_status_c138_field1_wd; - logic channel_status_c138_field1_we; - logic [31:0] reserved_2_c138_qs; - logic [31:0] reserved_2_c138_wd; - logic reserved_2_c138_we; - logic channel_flags_c138_intr_enable_qs; - logic channel_flags_c138_intr_enable_wd; - logic channel_flags_c138_intr_enable_we; - logic [30:0] channel_flags_c138_field1_qs; - logic [30:0] channel_flags_c138_field1_wd; - logic channel_flags_c138_field1_we; - logic [31:0] length_c138_qs; - logic [31:0] length_c138_wd; - logic length_c138_we; - logic [7:0] message_header_c138_message_id_qs; - logic [7:0] message_header_c138_message_id_wd; - logic message_header_c138_message_id_we; - logic [1:0] message_header_c138_message_type_qs; - logic [1:0] message_header_c138_message_type_wd; - logic message_header_c138_message_type_we; - logic [7:0] message_header_c138_protocol_id_qs; - logic [7:0] message_header_c138_protocol_id_wd; - logic message_header_c138_protocol_id_we; - logic [9:0] message_header_c138_token_qs; - logic [9:0] message_header_c138_token_wd; - logic message_header_c138_token_we; - logic [3:0] message_header_c138_field1_qs; - logic [3:0] message_header_c138_field1_wd; - logic message_header_c138_field1_we; - logic [31:0] message_payload_1_c138_qs; - logic [31:0] message_payload_1_c138_wd; - logic message_payload_1_c138_we; - logic doorbell_c138_intr_qs; - logic doorbell_c138_intr_wd; - logic doorbell_c138_intr_we; - logic [30:0] doorbell_c138_preserve_mask_qs; - logic [30:0] doorbell_c138_preserve_mask_wd; - logic doorbell_c138_preserve_mask_we; - logic completion_interrupt_c138_intr_qs; - logic completion_interrupt_c138_intr_wd; - logic completion_interrupt_c138_intr_we; - logic [30:0] completion_interrupt_c138_preserve_mask_qs; - logic [30:0] completion_interrupt_c138_preserve_mask_wd; - logic completion_interrupt_c138_preserve_mask_we; - logic [31:0] reserved_1_c139_qs; - logic [31:0] reserved_1_c139_wd; - logic reserved_1_c139_we; - logic channel_status_c139_channel_free_qs; - logic channel_status_c139_channel_free_wd; - logic channel_status_c139_channel_free_we; - logic channel_status_c139_channel_error_qs; - logic channel_status_c139_channel_error_wd; - logic channel_status_c139_channel_error_we; - logic [29:0] channel_status_c139_field1_qs; - logic [29:0] channel_status_c139_field1_wd; - logic channel_status_c139_field1_we; - logic [31:0] reserved_2_c139_qs; - logic [31:0] reserved_2_c139_wd; - logic reserved_2_c139_we; - logic channel_flags_c139_intr_enable_qs; - logic channel_flags_c139_intr_enable_wd; - logic channel_flags_c139_intr_enable_we; - logic [30:0] channel_flags_c139_field1_qs; - logic [30:0] channel_flags_c139_field1_wd; - logic channel_flags_c139_field1_we; - logic [31:0] length_c139_qs; - logic [31:0] length_c139_wd; - logic length_c139_we; - logic [7:0] message_header_c139_message_id_qs; - logic [7:0] message_header_c139_message_id_wd; - logic message_header_c139_message_id_we; - logic [1:0] message_header_c139_message_type_qs; - logic [1:0] message_header_c139_message_type_wd; - logic message_header_c139_message_type_we; - logic [7:0] message_header_c139_protocol_id_qs; - logic [7:0] message_header_c139_protocol_id_wd; - logic message_header_c139_protocol_id_we; - logic [9:0] message_header_c139_token_qs; - logic [9:0] message_header_c139_token_wd; - logic message_header_c139_token_we; - logic [3:0] message_header_c139_field1_qs; - logic [3:0] message_header_c139_field1_wd; - logic message_header_c139_field1_we; - logic [31:0] message_payload_1_c139_qs; - logic [31:0] message_payload_1_c139_wd; - logic message_payload_1_c139_we; - logic doorbell_c139_intr_qs; - logic doorbell_c139_intr_wd; - logic doorbell_c139_intr_we; - logic [30:0] doorbell_c139_preserve_mask_qs; - logic [30:0] doorbell_c139_preserve_mask_wd; - logic doorbell_c139_preserve_mask_we; - logic completion_interrupt_c139_intr_qs; - logic completion_interrupt_c139_intr_wd; - logic completion_interrupt_c139_intr_we; - logic [30:0] completion_interrupt_c139_preserve_mask_qs; - logic [30:0] completion_interrupt_c139_preserve_mask_wd; - logic completion_interrupt_c139_preserve_mask_we; - logic [31:0] reserved_1_c140_qs; - logic [31:0] reserved_1_c140_wd; - logic reserved_1_c140_we; - logic channel_status_c140_channel_free_qs; - logic channel_status_c140_channel_free_wd; - logic channel_status_c140_channel_free_we; - logic channel_status_c140_channel_error_qs; - logic channel_status_c140_channel_error_wd; - logic channel_status_c140_channel_error_we; - logic [29:0] channel_status_c140_field1_qs; - logic [29:0] channel_status_c140_field1_wd; - logic channel_status_c140_field1_we; - logic [31:0] reserved_2_c140_qs; - logic [31:0] reserved_2_c140_wd; - logic reserved_2_c140_we; - logic channel_flags_c140_intr_enable_qs; - logic channel_flags_c140_intr_enable_wd; - logic channel_flags_c140_intr_enable_we; - logic [30:0] channel_flags_c140_field1_qs; - logic [30:0] channel_flags_c140_field1_wd; - logic channel_flags_c140_field1_we; - logic [31:0] length_c140_qs; - logic [31:0] length_c140_wd; - logic length_c140_we; - logic [7:0] message_header_c140_message_id_qs; - logic [7:0] message_header_c140_message_id_wd; - logic message_header_c140_message_id_we; - logic [1:0] message_header_c140_message_type_qs; - logic [1:0] message_header_c140_message_type_wd; - logic message_header_c140_message_type_we; - logic [7:0] message_header_c140_protocol_id_qs; - logic [7:0] message_header_c140_protocol_id_wd; - logic message_header_c140_protocol_id_we; - logic [9:0] message_header_c140_token_qs; - logic [9:0] message_header_c140_token_wd; - logic message_header_c140_token_we; - logic [3:0] message_header_c140_field1_qs; - logic [3:0] message_header_c140_field1_wd; - logic message_header_c140_field1_we; - logic [31:0] message_payload_1_c140_qs; - logic [31:0] message_payload_1_c140_wd; - logic message_payload_1_c140_we; - logic doorbell_c140_intr_qs; - logic doorbell_c140_intr_wd; - logic doorbell_c140_intr_we; - logic [30:0] doorbell_c140_preserve_mask_qs; - logic [30:0] doorbell_c140_preserve_mask_wd; - logic doorbell_c140_preserve_mask_we; - logic completion_interrupt_c140_intr_qs; - logic completion_interrupt_c140_intr_wd; - logic completion_interrupt_c140_intr_we; - logic [30:0] completion_interrupt_c140_preserve_mask_qs; - logic [30:0] completion_interrupt_c140_preserve_mask_wd; - logic completion_interrupt_c140_preserve_mask_we; - logic [31:0] reserved_1_c141_qs; - logic [31:0] reserved_1_c141_wd; - logic reserved_1_c141_we; - logic channel_status_c141_channel_free_qs; - logic channel_status_c141_channel_free_wd; - logic channel_status_c141_channel_free_we; - logic channel_status_c141_channel_error_qs; - logic channel_status_c141_channel_error_wd; - logic channel_status_c141_channel_error_we; - logic [29:0] channel_status_c141_field1_qs; - logic [29:0] channel_status_c141_field1_wd; - logic channel_status_c141_field1_we; - logic [31:0] reserved_2_c141_qs; - logic [31:0] reserved_2_c141_wd; - logic reserved_2_c141_we; - logic channel_flags_c141_intr_enable_qs; - logic channel_flags_c141_intr_enable_wd; - logic channel_flags_c141_intr_enable_we; - logic [30:0] channel_flags_c141_field1_qs; - logic [30:0] channel_flags_c141_field1_wd; - logic channel_flags_c141_field1_we; - logic [31:0] length_c141_qs; - logic [31:0] length_c141_wd; - logic length_c141_we; - logic [7:0] message_header_c141_message_id_qs; - logic [7:0] message_header_c141_message_id_wd; - logic message_header_c141_message_id_we; - logic [1:0] message_header_c141_message_type_qs; - logic [1:0] message_header_c141_message_type_wd; - logic message_header_c141_message_type_we; - logic [7:0] message_header_c141_protocol_id_qs; - logic [7:0] message_header_c141_protocol_id_wd; - logic message_header_c141_protocol_id_we; - logic [9:0] message_header_c141_token_qs; - logic [9:0] message_header_c141_token_wd; - logic message_header_c141_token_we; - logic [3:0] message_header_c141_field1_qs; - logic [3:0] message_header_c141_field1_wd; - logic message_header_c141_field1_we; - logic [31:0] message_payload_1_c141_qs; - logic [31:0] message_payload_1_c141_wd; - logic message_payload_1_c141_we; - logic doorbell_c141_intr_qs; - logic doorbell_c141_intr_wd; - logic doorbell_c141_intr_we; - logic [30:0] doorbell_c141_preserve_mask_qs; - logic [30:0] doorbell_c141_preserve_mask_wd; - logic doorbell_c141_preserve_mask_we; - logic completion_interrupt_c141_intr_qs; - logic completion_interrupt_c141_intr_wd; - logic completion_interrupt_c141_intr_we; - logic [30:0] completion_interrupt_c141_preserve_mask_qs; - logic [30:0] completion_interrupt_c141_preserve_mask_wd; - logic completion_interrupt_c141_preserve_mask_we; - logic [31:0] reserved_1_c142_qs; - logic [31:0] reserved_1_c142_wd; - logic reserved_1_c142_we; - logic channel_status_c142_channel_free_qs; - logic channel_status_c142_channel_free_wd; - logic channel_status_c142_channel_free_we; - logic channel_status_c142_channel_error_qs; - logic channel_status_c142_channel_error_wd; - logic channel_status_c142_channel_error_we; - logic [29:0] channel_status_c142_field1_qs; - logic [29:0] channel_status_c142_field1_wd; - logic channel_status_c142_field1_we; - logic [31:0] reserved_2_c142_qs; - logic [31:0] reserved_2_c142_wd; - logic reserved_2_c142_we; - logic channel_flags_c142_intr_enable_qs; - logic channel_flags_c142_intr_enable_wd; - logic channel_flags_c142_intr_enable_we; - logic [30:0] channel_flags_c142_field1_qs; - logic [30:0] channel_flags_c142_field1_wd; - logic channel_flags_c142_field1_we; - logic [31:0] length_c142_qs; - logic [31:0] length_c142_wd; - logic length_c142_we; - logic [7:0] message_header_c142_message_id_qs; - logic [7:0] message_header_c142_message_id_wd; - logic message_header_c142_message_id_we; - logic [1:0] message_header_c142_message_type_qs; - logic [1:0] message_header_c142_message_type_wd; - logic message_header_c142_message_type_we; - logic [7:0] message_header_c142_protocol_id_qs; - logic [7:0] message_header_c142_protocol_id_wd; - logic message_header_c142_protocol_id_we; - logic [9:0] message_header_c142_token_qs; - logic [9:0] message_header_c142_token_wd; - logic message_header_c142_token_we; - logic [3:0] message_header_c142_field1_qs; - logic [3:0] message_header_c142_field1_wd; - logic message_header_c142_field1_we; - logic [31:0] message_payload_1_c142_qs; - logic [31:0] message_payload_1_c142_wd; - logic message_payload_1_c142_we; - logic doorbell_c142_intr_qs; - logic doorbell_c142_intr_wd; - logic doorbell_c142_intr_we; - logic [30:0] doorbell_c142_preserve_mask_qs; - logic [30:0] doorbell_c142_preserve_mask_wd; - logic doorbell_c142_preserve_mask_we; - logic completion_interrupt_c142_intr_qs; - logic completion_interrupt_c142_intr_wd; - logic completion_interrupt_c142_intr_we; - logic [30:0] completion_interrupt_c142_preserve_mask_qs; - logic [30:0] completion_interrupt_c142_preserve_mask_wd; - logic completion_interrupt_c142_preserve_mask_we; - logic [31:0] reserved_1_c143_qs; - logic [31:0] reserved_1_c143_wd; - logic reserved_1_c143_we; - logic channel_status_c143_channel_free_qs; - logic channel_status_c143_channel_free_wd; - logic channel_status_c143_channel_free_we; - logic channel_status_c143_channel_error_qs; - logic channel_status_c143_channel_error_wd; - logic channel_status_c143_channel_error_we; - logic [29:0] channel_status_c143_field1_qs; - logic [29:0] channel_status_c143_field1_wd; - logic channel_status_c143_field1_we; - logic [31:0] reserved_2_c143_qs; - logic [31:0] reserved_2_c143_wd; - logic reserved_2_c143_we; - logic channel_flags_c143_intr_enable_qs; - logic channel_flags_c143_intr_enable_wd; - logic channel_flags_c143_intr_enable_we; - logic [30:0] channel_flags_c143_field1_qs; - logic [30:0] channel_flags_c143_field1_wd; - logic channel_flags_c143_field1_we; - logic [31:0] length_c143_qs; - logic [31:0] length_c143_wd; - logic length_c143_we; - logic [7:0] message_header_c143_message_id_qs; - logic [7:0] message_header_c143_message_id_wd; - logic message_header_c143_message_id_we; - logic [1:0] message_header_c143_message_type_qs; - logic [1:0] message_header_c143_message_type_wd; - logic message_header_c143_message_type_we; - logic [7:0] message_header_c143_protocol_id_qs; - logic [7:0] message_header_c143_protocol_id_wd; - logic message_header_c143_protocol_id_we; - logic [9:0] message_header_c143_token_qs; - logic [9:0] message_header_c143_token_wd; - logic message_header_c143_token_we; - logic [3:0] message_header_c143_field1_qs; - logic [3:0] message_header_c143_field1_wd; - logic message_header_c143_field1_we; - logic [31:0] message_payload_1_c143_qs; - logic [31:0] message_payload_1_c143_wd; - logic message_payload_1_c143_we; - logic doorbell_c143_intr_qs; - logic doorbell_c143_intr_wd; - logic doorbell_c143_intr_we; - logic [30:0] doorbell_c143_preserve_mask_qs; - logic [30:0] doorbell_c143_preserve_mask_wd; - logic doorbell_c143_preserve_mask_we; - logic completion_interrupt_c143_intr_qs; - logic completion_interrupt_c143_intr_wd; - logic completion_interrupt_c143_intr_we; - logic [30:0] completion_interrupt_c143_preserve_mask_qs; - logic [30:0] completion_interrupt_c143_preserve_mask_wd; - logic completion_interrupt_c143_preserve_mask_we; - logic [31:0] reserved_1_c144_qs; - logic [31:0] reserved_1_c144_wd; - logic reserved_1_c144_we; - logic channel_status_c144_channel_free_qs; - logic channel_status_c144_channel_free_wd; - logic channel_status_c144_channel_free_we; - logic channel_status_c144_channel_error_qs; - logic channel_status_c144_channel_error_wd; - logic channel_status_c144_channel_error_we; - logic [29:0] channel_status_c144_field1_qs; - logic [29:0] channel_status_c144_field1_wd; - logic channel_status_c144_field1_we; - logic [31:0] reserved_2_c144_qs; - logic [31:0] reserved_2_c144_wd; - logic reserved_2_c144_we; - logic channel_flags_c144_intr_enable_qs; - logic channel_flags_c144_intr_enable_wd; - logic channel_flags_c144_intr_enable_we; - logic [30:0] channel_flags_c144_field1_qs; - logic [30:0] channel_flags_c144_field1_wd; - logic channel_flags_c144_field1_we; - logic [31:0] length_c144_qs; - logic [31:0] length_c144_wd; - logic length_c144_we; - logic [7:0] message_header_c144_message_id_qs; - logic [7:0] message_header_c144_message_id_wd; - logic message_header_c144_message_id_we; - logic [1:0] message_header_c144_message_type_qs; - logic [1:0] message_header_c144_message_type_wd; - logic message_header_c144_message_type_we; - logic [7:0] message_header_c144_protocol_id_qs; - logic [7:0] message_header_c144_protocol_id_wd; - logic message_header_c144_protocol_id_we; - logic [9:0] message_header_c144_token_qs; - logic [9:0] message_header_c144_token_wd; - logic message_header_c144_token_we; - logic [3:0] message_header_c144_field1_qs; - logic [3:0] message_header_c144_field1_wd; - logic message_header_c144_field1_we; - logic [31:0] message_payload_1_c144_qs; - logic [31:0] message_payload_1_c144_wd; - logic message_payload_1_c144_we; - logic doorbell_c144_intr_qs; - logic doorbell_c144_intr_wd; - logic doorbell_c144_intr_we; - logic [30:0] doorbell_c144_preserve_mask_qs; - logic [30:0] doorbell_c144_preserve_mask_wd; - logic doorbell_c144_preserve_mask_we; - logic completion_interrupt_c144_intr_qs; - logic completion_interrupt_c144_intr_wd; - logic completion_interrupt_c144_intr_we; - logic [30:0] completion_interrupt_c144_preserve_mask_qs; - logic [30:0] completion_interrupt_c144_preserve_mask_wd; - logic completion_interrupt_c144_preserve_mask_we; - logic [31:0] reserved_1_c145_qs; - logic [31:0] reserved_1_c145_wd; - logic reserved_1_c145_we; - logic channel_status_c145_channel_free_qs; - logic channel_status_c145_channel_free_wd; - logic channel_status_c145_channel_free_we; - logic channel_status_c145_channel_error_qs; - logic channel_status_c145_channel_error_wd; - logic channel_status_c145_channel_error_we; - logic [29:0] channel_status_c145_field1_qs; - logic [29:0] channel_status_c145_field1_wd; - logic channel_status_c145_field1_we; - logic [31:0] reserved_2_c145_qs; - logic [31:0] reserved_2_c145_wd; - logic reserved_2_c145_we; - logic channel_flags_c145_intr_enable_qs; - logic channel_flags_c145_intr_enable_wd; - logic channel_flags_c145_intr_enable_we; - logic [30:0] channel_flags_c145_field1_qs; - logic [30:0] channel_flags_c145_field1_wd; - logic channel_flags_c145_field1_we; - logic [31:0] length_c145_qs; - logic [31:0] length_c145_wd; - logic length_c145_we; - logic [7:0] message_header_c145_message_id_qs; - logic [7:0] message_header_c145_message_id_wd; - logic message_header_c145_message_id_we; - logic [1:0] message_header_c145_message_type_qs; - logic [1:0] message_header_c145_message_type_wd; - logic message_header_c145_message_type_we; - logic [7:0] message_header_c145_protocol_id_qs; - logic [7:0] message_header_c145_protocol_id_wd; - logic message_header_c145_protocol_id_we; - logic [9:0] message_header_c145_token_qs; - logic [9:0] message_header_c145_token_wd; - logic message_header_c145_token_we; - logic [3:0] message_header_c145_field1_qs; - logic [3:0] message_header_c145_field1_wd; - logic message_header_c145_field1_we; - logic [31:0] message_payload_1_c145_qs; - logic [31:0] message_payload_1_c145_wd; - logic message_payload_1_c145_we; - logic doorbell_c145_intr_qs; - logic doorbell_c145_intr_wd; - logic doorbell_c145_intr_we; - logic [30:0] doorbell_c145_preserve_mask_qs; - logic [30:0] doorbell_c145_preserve_mask_wd; - logic doorbell_c145_preserve_mask_we; - logic completion_interrupt_c145_intr_qs; - logic completion_interrupt_c145_intr_wd; - logic completion_interrupt_c145_intr_we; - logic [30:0] completion_interrupt_c145_preserve_mask_qs; - logic [30:0] completion_interrupt_c145_preserve_mask_wd; - logic completion_interrupt_c145_preserve_mask_we; - logic [31:0] reserved_1_c146_qs; - logic [31:0] reserved_1_c146_wd; - logic reserved_1_c146_we; - logic channel_status_c146_channel_free_qs; - logic channel_status_c146_channel_free_wd; - logic channel_status_c146_channel_free_we; - logic channel_status_c146_channel_error_qs; - logic channel_status_c146_channel_error_wd; - logic channel_status_c146_channel_error_we; - logic [29:0] channel_status_c146_field1_qs; - logic [29:0] channel_status_c146_field1_wd; - logic channel_status_c146_field1_we; - logic [31:0] reserved_2_c146_qs; - logic [31:0] reserved_2_c146_wd; - logic reserved_2_c146_we; - logic channel_flags_c146_intr_enable_qs; - logic channel_flags_c146_intr_enable_wd; - logic channel_flags_c146_intr_enable_we; - logic [30:0] channel_flags_c146_field1_qs; - logic [30:0] channel_flags_c146_field1_wd; - logic channel_flags_c146_field1_we; - logic [31:0] length_c146_qs; - logic [31:0] length_c146_wd; - logic length_c146_we; - logic [7:0] message_header_c146_message_id_qs; - logic [7:0] message_header_c146_message_id_wd; - logic message_header_c146_message_id_we; - logic [1:0] message_header_c146_message_type_qs; - logic [1:0] message_header_c146_message_type_wd; - logic message_header_c146_message_type_we; - logic [7:0] message_header_c146_protocol_id_qs; - logic [7:0] message_header_c146_protocol_id_wd; - logic message_header_c146_protocol_id_we; - logic [9:0] message_header_c146_token_qs; - logic [9:0] message_header_c146_token_wd; - logic message_header_c146_token_we; - logic [3:0] message_header_c146_field1_qs; - logic [3:0] message_header_c146_field1_wd; - logic message_header_c146_field1_we; - logic [31:0] message_payload_1_c146_qs; - logic [31:0] message_payload_1_c146_wd; - logic message_payload_1_c146_we; - logic doorbell_c146_intr_qs; - logic doorbell_c146_intr_wd; - logic doorbell_c146_intr_we; - logic [30:0] doorbell_c146_preserve_mask_qs; - logic [30:0] doorbell_c146_preserve_mask_wd; - logic doorbell_c146_preserve_mask_we; - logic completion_interrupt_c146_intr_qs; - logic completion_interrupt_c146_intr_wd; - logic completion_interrupt_c146_intr_we; - logic [30:0] completion_interrupt_c146_preserve_mask_qs; - logic [30:0] completion_interrupt_c146_preserve_mask_wd; - logic completion_interrupt_c146_preserve_mask_we; + logic [31:0] message_payload_2_c0_qs; + logic [31:0] message_payload_2_c0_wd; + logic message_payload_2_c0_we; + logic [31:0] message_payload_3_c0_qs; + logic [31:0] message_payload_3_c0_wd; + logic message_payload_3_c0_we; + logic [31:0] message_payload_4_c0_qs; + logic [31:0] message_payload_4_c0_wd; + logic message_payload_4_c0_we; + logic [31:0] message_payload_5_c0_qs; + logic [31:0] message_payload_5_c0_wd; + logic message_payload_5_c0_we; + logic [31:0] message_payload_6_c0_qs; + logic [31:0] message_payload_6_c0_wd; + logic message_payload_6_c0_we; + logic [31:0] message_payload_7_c0_qs; + logic [31:0] message_payload_7_c0_wd; + logic message_payload_7_c0_we; + logic [31:0] message_payload_8_c0_qs; + logic [31:0] message_payload_8_c0_wd; + logic message_payload_8_c0_we; + logic [31:0] message_payload_9_c0_qs; + logic [31:0] message_payload_9_c0_wd; + logic message_payload_9_c0_we; + logic [31:0] message_payload_10_c0_qs; + logic [31:0] message_payload_10_c0_wd; + logic message_payload_10_c0_we; + logic [31:0] message_payload_11_c0_qs; + logic [31:0] message_payload_11_c0_wd; + logic message_payload_11_c0_we; + logic [31:0] message_payload_12_c0_qs; + logic [31:0] message_payload_12_c0_wd; + logic message_payload_12_c0_we; + logic [31:0] message_payload_13_c0_qs; + logic [31:0] message_payload_13_c0_wd; + logic message_payload_13_c0_we; + logic [31:0] message_payload_14_c0_qs; + logic [31:0] message_payload_14_c0_wd; + logic message_payload_14_c0_we; + logic [31:0] message_payload_15_c0_qs; + logic [31:0] message_payload_15_c0_wd; + logic message_payload_15_c0_we; + logic [31:0] message_payload_16_c0_qs; + logic [31:0] message_payload_16_c0_wd; + logic message_payload_16_c0_we; + logic [31:0] message_payload_17_c0_qs; + logic [31:0] message_payload_17_c0_wd; + logic message_payload_17_c0_we; + logic [31:0] message_payload_18_c0_qs; + logic [31:0] message_payload_18_c0_wd; + logic message_payload_18_c0_we; + logic [31:0] message_payload_19_c0_qs; + logic [31:0] message_payload_19_c0_wd; + logic message_payload_19_c0_we; + logic [31:0] message_payload_20_c0_qs; + logic [31:0] message_payload_20_c0_wd; + logic message_payload_20_c0_we; + logic [31:0] message_payload_21_c0_qs; + logic [31:0] message_payload_21_c0_wd; + logic message_payload_21_c0_we; + logic [31:0] message_payload_22_c0_qs; + logic [31:0] message_payload_22_c0_wd; + logic message_payload_22_c0_we; + logic [31:0] message_payload_23_c0_qs; + logic [31:0] message_payload_23_c0_wd; + logic message_payload_23_c0_we; + logic [31:0] message_payload_24_c0_qs; + logic [31:0] message_payload_24_c0_wd; + logic message_payload_24_c0_we; + logic [31:0] message_payload_25_c0_qs; + logic [31:0] message_payload_25_c0_wd; + logic message_payload_25_c0_we; + logic [31:0] message_payload_26_c0_qs; + logic [31:0] message_payload_26_c0_wd; + logic message_payload_26_c0_we; + logic [31:0] message_payload_27_c0_qs; + logic [31:0] message_payload_27_c0_wd; + logic message_payload_27_c0_we; + logic [31:0] message_payload_28_c0_qs; + logic [31:0] message_payload_28_c0_wd; + logic message_payload_28_c0_we; + logic [31:0] message_payload_29_c0_qs; + logic [31:0] message_payload_29_c0_wd; + logic message_payload_29_c0_we; + logic [31:0] message_payload_30_c0_qs; + logic [31:0] message_payload_30_c0_wd; + logic message_payload_30_c0_we; + logic [31:0] message_payload_31_c0_qs; + logic [31:0] message_payload_31_c0_wd; + logic message_payload_31_c0_we; + logic [31:0] message_payload_32_c0_qs; + logic [31:0] message_payload_32_c0_wd; + logic message_payload_32_c0_we; + logic [31:0] doorbell_c0_qs; + logic [31:0] doorbell_c0_wd; + logic doorbell_c0_we; + logic [31:0] completion_interrupt_c0_qs; + logic [31:0] completion_interrupt_c0_wd; + logic completion_interrupt_c0_we; // Register instances // R[reserved_1_c0]: V(False) @@ -8145,14 +354,15 @@ module scmi_reg_top #( prim_subreg #( .DW (32), - .SWACCESS("NONE"), + .SWACCESS("RW"), .RESVAL (32'h0) ) u_reserved_3_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .we (1'b0), - .wd ('0 ), + // from register interface + .we (reserved_3_c0_we), + .wd (reserved_3_c0_wd), // from internal hardware .de (1'b0), @@ -8162,7 +372,8 @@ module scmi_reg_top #( .qe (), .q (), - .qs () + // to register interface (read) + .qs (reserved_3_c0_qs) ); @@ -8379,19 +590,19 @@ module scmi_reg_top #( ); - // R[message_payload_1_c0]: V(False) + // R[message_payload_0_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_message_payload_1_c0 ( + ) u_message_payload_0_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_payload_1_c0_we), - .wd (message_payload_1_c0_wd), + .we (message_payload_0_c0_we), + .wd (message_payload_0_c0_wd), // from internal hardware .de (1'b0), @@ -8402,50 +613,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_payload_1_c0_qs) + .qs (message_payload_0_c0_qs) ); - // R[doorbell_c0]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c0_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c0_intr_we), - .wd (doorbell_c0_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c0.intr.q ), - - // to register interface (read) - .qs (doorbell_c0_intr_qs) - ); - + // R[message_payload_1_c0]: V(False) - // F[preserve_mask]: 31:1 prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c0_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_1_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (doorbell_c0_preserve_mask_we), - .wd (doorbell_c0_preserve_mask_wd), + .we (message_payload_1_c0_we), + .wd (message_payload_1_c0_wd), // from internal hardware .de (1'b0), @@ -8453,53 +637,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.doorbell_c0.preserve_mask.q ), + .q (), // to register interface (read) - .qs (doorbell_c0_preserve_mask_qs) + .qs (message_payload_1_c0_qs) ); - // R[completion_interrupt_c0]: V(False) + // R[message_payload_2_c0]: V(False) - // F[intr]: 0:0 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c0_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c0_intr_we), - .wd (completion_interrupt_c0_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c0.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c0_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c0_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_2_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (completion_interrupt_c0_preserve_mask_we), - .wd (completion_interrupt_c0_preserve_mask_wd), + .we (message_payload_2_c0_we), + .wd (message_payload_2_c0_wd), // from internal hardware .de (1'b0), @@ -8507,26 +664,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.completion_interrupt_c0.preserve_mask.q ), + .q (), // to register interface (read) - .qs (completion_interrupt_c0_preserve_mask_qs) + .qs (message_payload_2_c0_qs) ); - // R[reserved_1_c1]: V(False) + // R[message_payload_3_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_1_c1 ( + ) u_message_payload_3_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_1_c1_we), - .wd (reserved_1_c1_wd), + .we (message_payload_3_c0_we), + .wd (message_payload_3_c0_wd), // from internal hardware .de (1'b0), @@ -8537,24 +694,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (reserved_1_c1_qs) + .qs (message_payload_3_c0_qs) ); - // R[channel_status_c1]: V(False) + // R[message_payload_4_c0]: V(False) - // F[channel_free]: 0:0 prim_subreg #( - .DW (1), + .DW (32), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c1_channel_free ( + .RESVAL (32'h0) + ) u_message_payload_4_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c1_channel_free_we), - .wd (channel_status_c1_channel_free_wd), + .we (message_payload_4_c0_we), + .wd (message_payload_4_c0_wd), // from internal hardware .de (1'b0), @@ -8565,48 +721,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c1_channel_free_qs) + .qs (message_payload_4_c0_qs) ); - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c1_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c1_channel_error_we), - .wd (channel_status_c1_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), + // R[message_payload_5_c0]: V(False) - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c1_channel_error_qs) - ); - - - // F[field1]: 31:2 prim_subreg #( - .DW (30), + .DW (32), .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c1_field1 ( + .RESVAL (32'h0) + ) u_message_payload_5_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c1_field1_we), - .wd (channel_status_c1_field1_wd), + .we (message_payload_5_c0_we), + .wd (message_payload_5_c0_wd), // from internal hardware .de (1'b0), @@ -8617,23 +748,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c1_field1_qs) + .qs (message_payload_5_c0_qs) ); - // R[reserved_2_c1]: V(False) + // R[message_payload_6_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_2_c1 ( + ) u_message_payload_6_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_2_c1_we), - .wd (reserved_2_c1_wd), + .we (message_payload_6_c0_we), + .wd (message_payload_6_c0_wd), // from internal hardware .de (1'b0), @@ -8644,49 +775,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (reserved_2_c1_qs) + .qs (message_payload_6_c0_qs) ); - // R[reserved_3_c1]: V(False) + // R[message_payload_7_c0]: V(False) prim_subreg #( .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c1]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c1_intr_enable ( + .RESVAL (32'h0) + ) u_message_payload_7_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_flags_c1_intr_enable_we), - .wd (channel_flags_c1_intr_enable_wd), + .we (message_payload_7_c0_we), + .wd (message_payload_7_c0_wd), // from internal hardware .de (1'b0), @@ -8697,22 +802,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_flags_c1_intr_enable_qs) + .qs (message_payload_7_c0_qs) ); - // F[field1]: 31:1 + // R[message_payload_8_c0]: V(False) + prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c1_field1 ( + .RESVAL (32'h0) + ) u_message_payload_8_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_flags_c1_field1_we), - .wd (channel_flags_c1_field1_wd), + .we (message_payload_8_c0_we), + .wd (message_payload_8_c0_wd), // from internal hardware .de (1'b0), @@ -8723,23 +829,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_flags_c1_field1_qs) + .qs (message_payload_8_c0_qs) ); - // R[length_c1]: V(False) + // R[message_payload_9_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_length_c1 ( + ) u_message_payload_9_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (length_c1_we), - .wd (length_c1_wd), + .we (message_payload_9_c0_we), + .wd (message_payload_9_c0_wd), // from internal hardware .de (1'b0), @@ -8750,24 +856,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (length_c1_qs) + .qs (message_payload_9_c0_qs) ); - // R[message_header_c1]: V(False) + // R[message_payload_10_c0]: V(False) - // F[message_id]: 7:0 prim_subreg #( - .DW (8), + .DW (32), .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c1_message_id ( + .RESVAL (32'h0) + ) u_message_payload_10_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c1_message_id_we), - .wd (message_header_c1_message_id_wd), + .we (message_payload_10_c0_we), + .wd (message_payload_10_c0_wd), // from internal hardware .de (1'b0), @@ -8778,48 +883,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c1_message_id_qs) + .qs (message_payload_10_c0_qs) ); - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c1_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c1_message_type_we), - .wd (message_header_c1_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), + // R[message_payload_11_c0]: V(False) - // to register interface (read) - .qs (message_header_c1_message_type_qs) - ); - - - // F[protocol_id]: 17:10 prim_subreg #( - .DW (8), + .DW (32), .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c1_protocol_id ( + .RESVAL (32'h0) + ) u_message_payload_11_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c1_protocol_id_we), - .wd (message_header_c1_protocol_id_wd), + .we (message_payload_11_c0_we), + .wd (message_payload_11_c0_wd), // from internal hardware .de (1'b0), @@ -8830,48 +910,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c1_protocol_id_qs) + .qs (message_payload_11_c0_qs) ); - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c1_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c1_token_we), - .wd (message_header_c1_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), + // R[message_payload_12_c0]: V(False) - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c1_token_qs) - ); - - - // F[field1]: 31:28 prim_subreg #( - .DW (4), + .DW (32), .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c1_field1 ( + .RESVAL (32'h0) + ) u_message_payload_12_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c1_field1_we), - .wd (message_header_c1_field1_wd), + .we (message_payload_12_c0_we), + .wd (message_payload_12_c0_wd), // from internal hardware .de (1'b0), @@ -8882,23 +937,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c1_field1_qs) + .qs (message_payload_12_c0_qs) ); - // R[message_payload_1_c1]: V(False) + // R[message_payload_13_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_message_payload_1_c1 ( + ) u_message_payload_13_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_payload_1_c1_we), - .wd (message_payload_1_c1_wd), + .we (message_payload_13_c0_we), + .wd (message_payload_13_c0_wd), // from internal hardware .de (1'b0), @@ -8909,50 +964,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_payload_1_c1_qs) + .qs (message_payload_13_c0_qs) ); - // R[doorbell_c1]: V(False) + // R[message_payload_14_c0]: V(False) - // F[intr]: 0:0 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c1_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c1_intr_we), - .wd (doorbell_c1_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c1.intr.q ), - - // to register interface (read) - .qs (doorbell_c1_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c1_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_14_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (doorbell_c1_preserve_mask_we), - .wd (doorbell_c1_preserve_mask_wd), + .we (message_payload_14_c0_we), + .wd (message_payload_14_c0_wd), // from internal hardware .de (1'b0), @@ -8960,53 +988,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.doorbell_c1.preserve_mask.q ), + .q (), // to register interface (read) - .qs (doorbell_c1_preserve_mask_qs) + .qs (message_payload_14_c0_qs) ); - // R[completion_interrupt_c1]: V(False) + // R[message_payload_15_c0]: V(False) - // F[intr]: 0:0 prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c1_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c1_intr_we), - .wd (completion_interrupt_c1_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c1.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c1_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c1_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_15_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (completion_interrupt_c1_preserve_mask_we), - .wd (completion_interrupt_c1_preserve_mask_wd), + .we (message_payload_15_c0_we), + .wd (message_payload_15_c0_wd), // from internal hardware .de (1'b0), @@ -9014,26 +1015,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.completion_interrupt_c1.preserve_mask.q ), + .q (), // to register interface (read) - .qs (completion_interrupt_c1_preserve_mask_qs) + .qs (message_payload_15_c0_qs) ); - // R[reserved_1_c2]: V(False) + // R[message_payload_16_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_1_c2 ( + ) u_message_payload_16_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_1_c2_we), - .wd (reserved_1_c2_wd), + .we (message_payload_16_c0_we), + .wd (message_payload_16_c0_wd), // from internal hardware .de (1'b0), @@ -9044,24 +1045,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (reserved_1_c2_qs) + .qs (message_payload_16_c0_qs) ); - // R[channel_status_c2]: V(False) + // R[message_payload_17_c0]: V(False) - // F[channel_free]: 0:0 prim_subreg #( - .DW (1), + .DW (32), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c2_channel_free ( + .RESVAL (32'h0) + ) u_message_payload_17_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c2_channel_free_we), - .wd (channel_status_c2_channel_free_wd), + .we (message_payload_17_c0_we), + .wd (message_payload_17_c0_wd), // from internal hardware .de (1'b0), @@ -9072,22 +1072,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c2_channel_free_qs) + .qs (message_payload_17_c0_qs) ); - // F[channel_error]: 1:1 + // R[message_payload_18_c0]: V(False) + prim_subreg #( - .DW (1), + .DW (32), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c2_channel_error ( + .RESVAL (32'h0) + ) u_message_payload_18_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c2_channel_error_we), - .wd (channel_status_c2_channel_error_wd), + .we (message_payload_18_c0_we), + .wd (message_payload_18_c0_wd), // from internal hardware .de (1'b0), @@ -9098,22 +1099,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c2_channel_error_qs) + .qs (message_payload_18_c0_qs) ); - // F[field1]: 31:2 + // R[message_payload_19_c0]: V(False) + prim_subreg #( - .DW (30), + .DW (32), .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c2_field1 ( + .RESVAL (32'h0) + ) u_message_payload_19_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c2_field1_we), - .wd (channel_status_c2_field1_wd), + .we (message_payload_19_c0_we), + .wd (message_payload_19_c0_wd), // from internal hardware .de (1'b0), @@ -9124,23 +1126,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c2_field1_qs) + .qs (message_payload_19_c0_qs) ); - // R[reserved_2_c2]: V(False) + // R[message_payload_20_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_2_c2 ( + ) u_message_payload_20_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_2_c2_we), - .wd (reserved_2_c2_wd), + .we (message_payload_20_c0_we), + .wd (message_payload_20_c0_wd), // from internal hardware .de (1'b0), @@ -9151,22 +1153,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (reserved_2_c2_qs) + .qs (message_payload_20_c0_qs) ); - // R[reserved_3_c2]: V(False) + // R[message_payload_21_c0]: V(False) prim_subreg #( .DW (32), - .SWACCESS("NONE"), + .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_3_c2 ( + ) u_message_payload_21_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .we (1'b0), - .wd ('0 ), + // from register interface + .we (message_payload_21_c0_we), + .wd (message_payload_21_c0_wd), // from internal hardware .de (1'b0), @@ -9176,24 +1179,24 @@ module scmi_reg_top #( .qe (), .q (), - .qs () + // to register interface (read) + .qs (message_payload_21_c0_qs) ); - // R[channel_flags_c2]: V(False) + // R[message_payload_22_c0]: V(False) - // F[intr_enable]: 0:0 prim_subreg #( - .DW (1), + .DW (32), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c2_intr_enable ( + .RESVAL (32'h0) + ) u_message_payload_22_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_flags_c2_intr_enable_we), - .wd (channel_flags_c2_intr_enable_wd), + .we (message_payload_22_c0_we), + .wd (message_payload_22_c0_wd), // from internal hardware .de (1'b0), @@ -9204,22 +1207,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_flags_c2_intr_enable_qs) + .qs (message_payload_22_c0_qs) ); - // F[field1]: 31:1 + // R[message_payload_23_c0]: V(False) + prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c2_field1 ( + .RESVAL (32'h0) + ) u_message_payload_23_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_flags_c2_field1_we), - .wd (channel_flags_c2_field1_wd), + .we (message_payload_23_c0_we), + .wd (message_payload_23_c0_wd), // from internal hardware .de (1'b0), @@ -9230,23 +1234,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_flags_c2_field1_qs) + .qs (message_payload_23_c0_qs) ); - // R[length_c2]: V(False) + // R[message_payload_24_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_length_c2 ( + ) u_message_payload_24_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (length_c2_we), - .wd (length_c2_wd), + .we (message_payload_24_c0_we), + .wd (message_payload_24_c0_wd), // from internal hardware .de (1'b0), @@ -9257,24 +1261,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (length_c2_qs) + .qs (message_payload_24_c0_qs) ); - // R[message_header_c2]: V(False) + // R[message_payload_25_c0]: V(False) - // F[message_id]: 7:0 prim_subreg #( - .DW (8), + .DW (32), .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c2_message_id ( + .RESVAL (32'h0) + ) u_message_payload_25_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c2_message_id_we), - .wd (message_header_c2_message_id_wd), + .we (message_payload_25_c0_we), + .wd (message_payload_25_c0_wd), // from internal hardware .de (1'b0), @@ -9285,48 +1288,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c2_message_id_qs) + .qs (message_payload_25_c0_qs) ); - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c2_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c2_message_type_we), - .wd (message_header_c2_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c2_message_type_qs) - ); - + // R[message_payload_26_c0]: V(False) - // F[protocol_id]: 17:10 prim_subreg #( - .DW (8), + .DW (32), .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c2_protocol_id ( + .RESVAL (32'h0) + ) u_message_payload_26_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c2_protocol_id_we), - .wd (message_header_c2_protocol_id_wd), + .we (message_payload_26_c0_we), + .wd (message_payload_26_c0_wd), // from internal hardware .de (1'b0), @@ -9337,48 +1315,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c2_protocol_id_qs) + .qs (message_payload_26_c0_qs) ); - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c2_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c2_token_we), - .wd (message_header_c2_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c2_token_qs) - ); - + // R[message_payload_27_c0]: V(False) - // F[field1]: 31:28 prim_subreg #( - .DW (4), + .DW (32), .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c2_field1 ( + .RESVAL (32'h0) + ) u_message_payload_27_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_header_c2_field1_we), - .wd (message_header_c2_field1_wd), + .we (message_payload_27_c0_we), + .wd (message_payload_27_c0_wd), // from internal hardware .de (1'b0), @@ -9389,23 +1342,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_header_c2_field1_qs) + .qs (message_payload_27_c0_qs) ); - // R[message_payload_1_c2]: V(False) + // R[message_payload_28_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_message_payload_1_c2 ( + ) u_message_payload_28_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (message_payload_1_c2_we), - .wd (message_payload_1_c2_wd), + .we (message_payload_28_c0_we), + .wd (message_payload_28_c0_wd), // from internal hardware .de (1'b0), @@ -9416,50 +1369,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (message_payload_1_c2_qs) + .qs (message_payload_28_c0_qs) ); - // R[doorbell_c2]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c2_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c2_intr_we), - .wd (doorbell_c2_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c2.intr.q ), - - // to register interface (read) - .qs (doorbell_c2_intr_qs) - ); - + // R[message_payload_29_c0]: V(False) - // F[preserve_mask]: 31:1 prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c2_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_29_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (doorbell_c2_preserve_mask_we), - .wd (doorbell_c2_preserve_mask_wd), + .we (message_payload_29_c0_we), + .wd (message_payload_29_c0_wd), // from internal hardware .de (1'b0), @@ -9467,53 +1393,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.doorbell_c2.preserve_mask.q ), + .q (), // to register interface (read) - .qs (doorbell_c2_preserve_mask_qs) + .qs (message_payload_29_c0_qs) ); - // R[completion_interrupt_c2]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c2_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c2_intr_we), - .wd (completion_interrupt_c2_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c2.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c2_intr_qs) - ); - + // R[message_payload_30_c0]: V(False) - // F[preserve_mask]: 31:1 prim_subreg #( - .DW (31), + .DW (32), .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c2_preserve_mask ( + .RESVAL (32'h0) + ) u_message_payload_30_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (completion_interrupt_c2_preserve_mask_we), - .wd (completion_interrupt_c2_preserve_mask_wd), + .we (message_payload_30_c0_we), + .wd (message_payload_30_c0_wd), // from internal hardware .de (1'b0), @@ -9521,26 +1420,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (reg2hw.completion_interrupt_c2.preserve_mask.q ), + .q (), // to register interface (read) - .qs (completion_interrupt_c2_preserve_mask_qs) + .qs (message_payload_30_c0_qs) ); - // R[reserved_1_c3]: V(False) + // R[message_payload_31_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_1_c3 ( + ) u_message_payload_31_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_1_c3_we), - .wd (reserved_1_c3_wd), + .we (message_payload_31_c0_we), + .wd (message_payload_31_c0_wd), // from internal hardware .de (1'b0), @@ -9551,24 +1450,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (reserved_1_c3_qs) + .qs (message_payload_31_c0_qs) ); - // R[channel_status_c3]: V(False) + // R[message_payload_32_c0]: V(False) - // F[channel_free]: 0:0 prim_subreg #( - .DW (1), + .DW (32), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c3_channel_free ( + .RESVAL (32'h0) + ) u_message_payload_32_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c3_channel_free_we), - .wd (channel_status_c3_channel_free_wd), + .we (message_payload_32_c0_we), + .wd (message_payload_32_c0_wd), // from internal hardware .de (1'b0), @@ -9579,48 +1477,23 @@ module scmi_reg_top #( .q (), // to register interface (read) - .qs (channel_status_c3_channel_free_qs) + .qs (message_payload_32_c0_qs) ); - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c3_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c3_channel_error_we), - .wd (channel_status_c3_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c3_channel_error_qs) - ); - + // R[doorbell_c0]: V(False) - // F[field1]: 31:2 prim_subreg #( - .DW (30), + .DW (32), .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c3_field1 ( + .RESVAL (32'h0) + ) u_doorbell_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (channel_status_c3_field1_we), - .wd (channel_status_c3_field1_wd), + .we (doorbell_c0_we), + .wd (doorbell_c0_wd), // from internal hardware .de (1'b0), @@ -9628,26 +1501,26 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (), + .q (reg2hw.doorbell_c0.q ), // to register interface (read) - .qs (channel_status_c3_field1_qs) + .qs (doorbell_c0_qs) ); - // R[reserved_2_c3]: V(False) + // R[completion_interrupt_c0]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_reserved_2_c3 ( + ) u_completion_interrupt_c0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (reserved_2_c3_we), - .wd (reserved_2_c3_wd), + .we (completion_interrupt_c0_we), + .wd (completion_interrupt_c0_wd), // from internal hardware .de (1'b0), @@ -9655,90984 +1528,435 @@ module scmi_reg_top #( // to internal hardware .qe (), - .q (), + .q (reg2hw.completion_interrupt_c0.q ), // to register interface (read) - .qs (reserved_2_c3_qs) + .qs (completion_interrupt_c0_qs) ); - // R[reserved_3_c3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - .qs () - ); + logic [41:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == SCMI_RESERVED_1_C0_OFFSET); + addr_hit[ 1] = (reg_addr == SCMI_CHANNEL_STATUS_C0_OFFSET); + addr_hit[ 2] = (reg_addr == SCMI_RESERVED_2_C0_OFFSET); + addr_hit[ 3] = (reg_addr == SCMI_RESERVED_3_C0_OFFSET); + addr_hit[ 4] = (reg_addr == SCMI_CHANNEL_FLAGS_C0_OFFSET); + addr_hit[ 5] = (reg_addr == SCMI_LENGTH_C0_OFFSET); + addr_hit[ 6] = (reg_addr == SCMI_MESSAGE_HEADER_C0_OFFSET); + addr_hit[ 7] = (reg_addr == SCMI_MESSAGE_PAYLOAD_0_C0_OFFSET); + addr_hit[ 8] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C0_OFFSET); + addr_hit[ 9] = (reg_addr == SCMI_MESSAGE_PAYLOAD_2_C0_OFFSET); + addr_hit[10] = (reg_addr == SCMI_MESSAGE_PAYLOAD_3_C0_OFFSET); + addr_hit[11] = (reg_addr == SCMI_MESSAGE_PAYLOAD_4_C0_OFFSET); + addr_hit[12] = (reg_addr == SCMI_MESSAGE_PAYLOAD_5_C0_OFFSET); + addr_hit[13] = (reg_addr == SCMI_MESSAGE_PAYLOAD_6_C0_OFFSET); + addr_hit[14] = (reg_addr == SCMI_MESSAGE_PAYLOAD_7_C0_OFFSET); + addr_hit[15] = (reg_addr == SCMI_MESSAGE_PAYLOAD_8_C0_OFFSET); + addr_hit[16] = (reg_addr == SCMI_MESSAGE_PAYLOAD_9_C0_OFFSET); + addr_hit[17] = (reg_addr == SCMI_MESSAGE_PAYLOAD_10_C0_OFFSET); + addr_hit[18] = (reg_addr == SCMI_MESSAGE_PAYLOAD_11_C0_OFFSET); + addr_hit[19] = (reg_addr == SCMI_MESSAGE_PAYLOAD_12_C0_OFFSET); + addr_hit[20] = (reg_addr == SCMI_MESSAGE_PAYLOAD_13_C0_OFFSET); + addr_hit[21] = (reg_addr == SCMI_MESSAGE_PAYLOAD_14_C0_OFFSET); + addr_hit[22] = (reg_addr == SCMI_MESSAGE_PAYLOAD_15_C0_OFFSET); + addr_hit[23] = (reg_addr == SCMI_MESSAGE_PAYLOAD_16_C0_OFFSET); + addr_hit[24] = (reg_addr == SCMI_MESSAGE_PAYLOAD_17_C0_OFFSET); + addr_hit[25] = (reg_addr == SCMI_MESSAGE_PAYLOAD_18_C0_OFFSET); + addr_hit[26] = (reg_addr == SCMI_MESSAGE_PAYLOAD_19_C0_OFFSET); + addr_hit[27] = (reg_addr == SCMI_MESSAGE_PAYLOAD_20_C0_OFFSET); + addr_hit[28] = (reg_addr == SCMI_MESSAGE_PAYLOAD_21_C0_OFFSET); + addr_hit[29] = (reg_addr == SCMI_MESSAGE_PAYLOAD_22_C0_OFFSET); + addr_hit[30] = (reg_addr == SCMI_MESSAGE_PAYLOAD_23_C0_OFFSET); + addr_hit[31] = (reg_addr == SCMI_MESSAGE_PAYLOAD_24_C0_OFFSET); + addr_hit[32] = (reg_addr == SCMI_MESSAGE_PAYLOAD_25_C0_OFFSET); + addr_hit[33] = (reg_addr == SCMI_MESSAGE_PAYLOAD_26_C0_OFFSET); + addr_hit[34] = (reg_addr == SCMI_MESSAGE_PAYLOAD_27_C0_OFFSET); + addr_hit[35] = (reg_addr == SCMI_MESSAGE_PAYLOAD_28_C0_OFFSET); + addr_hit[36] = (reg_addr == SCMI_MESSAGE_PAYLOAD_29_C0_OFFSET); + addr_hit[37] = (reg_addr == SCMI_MESSAGE_PAYLOAD_30_C0_OFFSET); + addr_hit[38] = (reg_addr == SCMI_MESSAGE_PAYLOAD_31_C0_OFFSET); + addr_hit[39] = (reg_addr == SCMI_MESSAGE_PAYLOAD_32_C0_OFFSET); + addr_hit[40] = (reg_addr == SCMI_DOORBELL_C0_OFFSET); + addr_hit[41] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C0_OFFSET); + end - // R[channel_flags_c3]: V(False) + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c3_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(SCMI_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(SCMI_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(SCMI_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(SCMI_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(SCMI_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(SCMI_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(SCMI_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(SCMI_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(SCMI_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(SCMI_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(SCMI_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(SCMI_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(SCMI_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(SCMI_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(SCMI_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(SCMI_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(SCMI_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(SCMI_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(SCMI_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(SCMI_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(SCMI_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(SCMI_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(SCMI_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(SCMI_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(SCMI_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(SCMI_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(SCMI_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(SCMI_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(SCMI_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(SCMI_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(SCMI_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(SCMI_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(SCMI_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(SCMI_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(SCMI_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(SCMI_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(SCMI_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(SCMI_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(SCMI_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(SCMI_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(SCMI_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(SCMI_PERMIT[41] & ~reg_be))))); + end - // from register interface - .we (channel_flags_c3_intr_enable_we), - .wd (channel_flags_c3_intr_enable_wd), + assign reserved_1_c0_we = addr_hit[0] & reg_we & !reg_error; + assign reserved_1_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign channel_status_c0_channel_free_we = addr_hit[1] & reg_we & !reg_error; + assign channel_status_c0_channel_free_wd = reg_wdata[0]; - // to internal hardware - .qe (), - .q (), + assign channel_status_c0_channel_error_we = addr_hit[1] & reg_we & !reg_error; + assign channel_status_c0_channel_error_wd = reg_wdata[1]; - // to register interface (read) - .qs (channel_flags_c3_intr_enable_qs) - ); + assign channel_status_c0_field1_we = addr_hit[1] & reg_we & !reg_error; + assign channel_status_c0_field1_wd = reg_wdata[31:2]; + assign reserved_2_c0_we = addr_hit[2] & reg_we & !reg_error; + assign reserved_2_c0_wd = reg_wdata[31:0]; - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c3_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign reserved_3_c0_we = addr_hit[3] & reg_we & !reg_error; + assign reserved_3_c0_wd = reg_wdata[31:0]; - // from register interface - .we (channel_flags_c3_field1_we), - .wd (channel_flags_c3_field1_wd), + assign channel_flags_c0_intr_enable_we = addr_hit[4] & reg_we & !reg_error; + assign channel_flags_c0_intr_enable_wd = reg_wdata[0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign channel_flags_c0_field1_we = addr_hit[4] & reg_we & !reg_error; + assign channel_flags_c0_field1_wd = reg_wdata[31:1]; - // to internal hardware - .qe (), - .q (), + assign length_c0_we = addr_hit[5] & reg_we & !reg_error; + assign length_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (channel_flags_c3_field1_qs) - ); + assign message_header_c0_message_id_we = addr_hit[6] & reg_we & !reg_error; + assign message_header_c0_message_id_wd = reg_wdata[7:0]; + assign message_header_c0_message_type_we = addr_hit[6] & reg_we & !reg_error; + assign message_header_c0_message_type_wd = reg_wdata[9:8]; - // R[length_c3]: V(False) + assign message_header_c0_protocol_id_we = addr_hit[6] & reg_we & !reg_error; + assign message_header_c0_protocol_id_wd = reg_wdata[17:10]; - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_header_c0_token_we = addr_hit[6] & reg_we & !reg_error; + assign message_header_c0_token_wd = reg_wdata[27:18]; - // from register interface - .we (length_c3_we), - .wd (length_c3_wd), + assign message_header_c0_field1_we = addr_hit[6] & reg_we & !reg_error; + assign message_header_c0_field1_wd = reg_wdata[31:28]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_0_c0_we = addr_hit[7] & reg_we & !reg_error; + assign message_payload_0_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_1_c0_we = addr_hit[8] & reg_we & !reg_error; + assign message_payload_1_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (length_c3_qs) - ); + assign message_payload_2_c0_we = addr_hit[9] & reg_we & !reg_error; + assign message_payload_2_c0_wd = reg_wdata[31:0]; + assign message_payload_3_c0_we = addr_hit[10] & reg_we & !reg_error; + assign message_payload_3_c0_wd = reg_wdata[31:0]; - // R[message_header_c3]: V(False) + assign message_payload_4_c0_we = addr_hit[11] & reg_we & !reg_error; + assign message_payload_4_c0_wd = reg_wdata[31:0]; - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c3_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_payload_5_c0_we = addr_hit[12] & reg_we & !reg_error; + assign message_payload_5_c0_wd = reg_wdata[31:0]; - // from register interface - .we (message_header_c3_message_id_we), - .wd (message_header_c3_message_id_wd), + assign message_payload_6_c0_we = addr_hit[13] & reg_we & !reg_error; + assign message_payload_6_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_7_c0_we = addr_hit[14] & reg_we & !reg_error; + assign message_payload_7_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_8_c0_we = addr_hit[15] & reg_we & !reg_error; + assign message_payload_8_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (message_header_c3_message_id_qs) - ); + assign message_payload_9_c0_we = addr_hit[16] & reg_we & !reg_error; + assign message_payload_9_c0_wd = reg_wdata[31:0]; + assign message_payload_10_c0_we = addr_hit[17] & reg_we & !reg_error; + assign message_payload_10_c0_wd = reg_wdata[31:0]; - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c3_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_payload_11_c0_we = addr_hit[18] & reg_we & !reg_error; + assign message_payload_11_c0_wd = reg_wdata[31:0]; - // from register interface - .we (message_header_c3_message_type_we), - .wd (message_header_c3_message_type_wd), + assign message_payload_12_c0_we = addr_hit[19] & reg_we & !reg_error; + assign message_payload_12_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_13_c0_we = addr_hit[20] & reg_we & !reg_error; + assign message_payload_13_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_14_c0_we = addr_hit[21] & reg_we & !reg_error; + assign message_payload_14_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (message_header_c3_message_type_qs) - ); + assign message_payload_15_c0_we = addr_hit[22] & reg_we & !reg_error; + assign message_payload_15_c0_wd = reg_wdata[31:0]; + assign message_payload_16_c0_we = addr_hit[23] & reg_we & !reg_error; + assign message_payload_16_c0_wd = reg_wdata[31:0]; - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c3_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_payload_17_c0_we = addr_hit[24] & reg_we & !reg_error; + assign message_payload_17_c0_wd = reg_wdata[31:0]; - // from register interface - .we (message_header_c3_protocol_id_we), - .wd (message_header_c3_protocol_id_wd), + assign message_payload_18_c0_we = addr_hit[25] & reg_we & !reg_error; + assign message_payload_18_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_19_c0_we = addr_hit[26] & reg_we & !reg_error; + assign message_payload_19_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_20_c0_we = addr_hit[27] & reg_we & !reg_error; + assign message_payload_20_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (message_header_c3_protocol_id_qs) - ); + assign message_payload_21_c0_we = addr_hit[28] & reg_we & !reg_error; + assign message_payload_21_c0_wd = reg_wdata[31:0]; + assign message_payload_22_c0_we = addr_hit[29] & reg_we & !reg_error; + assign message_payload_22_c0_wd = reg_wdata[31:0]; - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c3_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_payload_23_c0_we = addr_hit[30] & reg_we & !reg_error; + assign message_payload_23_c0_wd = reg_wdata[31:0]; - // from register interface - .we (message_header_c3_token_we), - .wd (message_header_c3_token_wd), + assign message_payload_24_c0_we = addr_hit[31] & reg_we & !reg_error; + assign message_payload_24_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_25_c0_we = addr_hit[32] & reg_we & !reg_error; + assign message_payload_25_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_26_c0_we = addr_hit[33] & reg_we & !reg_error; + assign message_payload_26_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (message_header_c3_token_qs) - ); + assign message_payload_27_c0_we = addr_hit[34] & reg_we & !reg_error; + assign message_payload_27_c0_wd = reg_wdata[31:0]; + assign message_payload_28_c0_we = addr_hit[35] & reg_we & !reg_error; + assign message_payload_28_c0_wd = reg_wdata[31:0]; - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c3_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + assign message_payload_29_c0_we = addr_hit[36] & reg_we & !reg_error; + assign message_payload_29_c0_wd = reg_wdata[31:0]; - // from register interface - .we (message_header_c3_field1_we), - .wd (message_header_c3_field1_wd), + assign message_payload_30_c0_we = addr_hit[37] & reg_we & !reg_error; + assign message_payload_30_c0_wd = reg_wdata[31:0]; - // from internal hardware - .de (1'b0), - .d ('0 ), + assign message_payload_31_c0_we = addr_hit[38] & reg_we & !reg_error; + assign message_payload_31_c0_wd = reg_wdata[31:0]; - // to internal hardware - .qe (), - .q (), + assign message_payload_32_c0_we = addr_hit[39] & reg_we & !reg_error; + assign message_payload_32_c0_wd = reg_wdata[31:0]; - // to register interface (read) - .qs (message_header_c3_field1_qs) - ); + assign doorbell_c0_we = addr_hit[40] & reg_we & !reg_error; + assign doorbell_c0_wd = reg_wdata[31:0]; + assign completion_interrupt_c0_we = addr_hit[41] & reg_we & !reg_error; + assign completion_interrupt_c0_wd = reg_wdata[31:0]; - // R[message_payload_1_c3]: V(False) + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = reserved_1_c0_qs; + end - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[1]: begin + reg_rdata_next[0] = channel_status_c0_channel_free_qs; + reg_rdata_next[1] = channel_status_c0_channel_error_qs; + reg_rdata_next[31:2] = channel_status_c0_field1_qs; + end - // from register interface - .we (message_payload_1_c3_we), - .wd (message_payload_1_c3_wd), + addr_hit[2]: begin + reg_rdata_next[31:0] = reserved_2_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[3]: begin + reg_rdata_next[31:0] = reserved_3_c0_qs; + end - // to internal hardware - .qe (), - .q (), + addr_hit[4]: begin + reg_rdata_next[0] = channel_flags_c0_intr_enable_qs; + reg_rdata_next[31:1] = channel_flags_c0_field1_qs; + end - // to register interface (read) - .qs (message_payload_1_c3_qs) - ); + addr_hit[5]: begin + reg_rdata_next[31:0] = length_c0_qs; + end + addr_hit[6]: begin + reg_rdata_next[7:0] = message_header_c0_message_id_qs; + reg_rdata_next[9:8] = message_header_c0_message_type_qs; + reg_rdata_next[17:10] = message_header_c0_protocol_id_qs; + reg_rdata_next[27:18] = message_header_c0_token_qs; + reg_rdata_next[31:28] = message_header_c0_field1_qs; + end - // R[doorbell_c3]: V(False) + addr_hit[7]: begin + reg_rdata_next[31:0] = message_payload_0_c0_qs; + end - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c3_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[8]: begin + reg_rdata_next[31:0] = message_payload_1_c0_qs; + end - // from register interface - .we (doorbell_c3_intr_we), - .wd (doorbell_c3_intr_wd), + addr_hit[9]: begin + reg_rdata_next[31:0] = message_payload_2_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[10]: begin + reg_rdata_next[31:0] = message_payload_3_c0_qs; + end - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c3.intr.q ), + addr_hit[11]: begin + reg_rdata_next[31:0] = message_payload_4_c0_qs; + end - // to register interface (read) - .qs (doorbell_c3_intr_qs) - ); + addr_hit[12]: begin + reg_rdata_next[31:0] = message_payload_5_c0_qs; + end + addr_hit[13]: begin + reg_rdata_next[31:0] = message_payload_6_c0_qs; + end - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c3_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[14]: begin + reg_rdata_next[31:0] = message_payload_7_c0_qs; + end - // from register interface - .we (doorbell_c3_preserve_mask_we), - .wd (doorbell_c3_preserve_mask_wd), + addr_hit[15]: begin + reg_rdata_next[31:0] = message_payload_8_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[16]: begin + reg_rdata_next[31:0] = message_payload_9_c0_qs; + end - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c3.preserve_mask.q ), + addr_hit[17]: begin + reg_rdata_next[31:0] = message_payload_10_c0_qs; + end - // to register interface (read) - .qs (doorbell_c3_preserve_mask_qs) - ); + addr_hit[18]: begin + reg_rdata_next[31:0] = message_payload_11_c0_qs; + end + addr_hit[19]: begin + reg_rdata_next[31:0] = message_payload_12_c0_qs; + end - // R[completion_interrupt_c3]: V(False) + addr_hit[20]: begin + reg_rdata_next[31:0] = message_payload_13_c0_qs; + end - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c3_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[21]: begin + reg_rdata_next[31:0] = message_payload_14_c0_qs; + end - // from register interface - .we (completion_interrupt_c3_intr_we), - .wd (completion_interrupt_c3_intr_wd), + addr_hit[22]: begin + reg_rdata_next[31:0] = message_payload_15_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[23]: begin + reg_rdata_next[31:0] = message_payload_16_c0_qs; + end - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c3.intr.q ), + addr_hit[24]: begin + reg_rdata_next[31:0] = message_payload_17_c0_qs; + end - // to register interface (read) - .qs (completion_interrupt_c3_intr_qs) - ); + addr_hit[25]: begin + reg_rdata_next[31:0] = message_payload_18_c0_qs; + end + addr_hit[26]: begin + reg_rdata_next[31:0] = message_payload_19_c0_qs; + end - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c3_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[27]: begin + reg_rdata_next[31:0] = message_payload_20_c0_qs; + end - // from register interface - .we (completion_interrupt_c3_preserve_mask_we), - .wd (completion_interrupt_c3_preserve_mask_wd), + addr_hit[28]: begin + reg_rdata_next[31:0] = message_payload_21_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[29]: begin + reg_rdata_next[31:0] = message_payload_22_c0_qs; + end - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c3.preserve_mask.q ), + addr_hit[30]: begin + reg_rdata_next[31:0] = message_payload_23_c0_qs; + end - // to register interface (read) - .qs (completion_interrupt_c3_preserve_mask_qs) - ); + addr_hit[31]: begin + reg_rdata_next[31:0] = message_payload_24_c0_qs; + end + addr_hit[32]: begin + reg_rdata_next[31:0] = message_payload_25_c0_qs; + end - // R[reserved_1_c4]: V(False) + addr_hit[33]: begin + reg_rdata_next[31:0] = message_payload_26_c0_qs; + end - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + addr_hit[34]: begin + reg_rdata_next[31:0] = message_payload_27_c0_qs; + end - // from register interface - .we (reserved_1_c4_we), - .wd (reserved_1_c4_wd), + addr_hit[35]: begin + reg_rdata_next[31:0] = message_payload_28_c0_qs; + end - // from internal hardware - .de (1'b0), - .d ('0 ), + addr_hit[36]: begin + reg_rdata_next[31:0] = message_payload_29_c0_qs; + end - // to internal hardware - .qe (), - .q (), + addr_hit[37]: begin + reg_rdata_next[31:0] = message_payload_30_c0_qs; + end - // to register interface (read) - .qs (reserved_1_c4_qs) - ); + addr_hit[38]: begin + reg_rdata_next[31:0] = message_payload_31_c0_qs; + end + addr_hit[39]: begin + reg_rdata_next[31:0] = message_payload_32_c0_qs; + end - // R[channel_status_c4]: V(False) + addr_hit[40]: begin + reg_rdata_next[31:0] = doorbell_c0_qs; + end - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c4_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c4_channel_free_we), - .wd (channel_status_c4_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c4_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c4_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c4_channel_error_we), - .wd (channel_status_c4_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c4_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c4_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c4_field1_we), - .wd (channel_status_c4_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c4_field1_qs) - ); - - - // R[reserved_2_c4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c4_we), - .wd (reserved_2_c4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c4_qs) - ); - - - // R[reserved_3_c4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c4]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c4_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c4_intr_enable_we), - .wd (channel_flags_c4_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c4_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c4_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c4_field1_we), - .wd (channel_flags_c4_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c4_field1_qs) - ); - - - // R[length_c4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c4_we), - .wd (length_c4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c4_qs) - ); - - - // R[message_header_c4]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c4_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c4_message_id_we), - .wd (message_header_c4_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c4_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c4_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c4_message_type_we), - .wd (message_header_c4_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c4_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c4_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c4_protocol_id_we), - .wd (message_header_c4_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c4_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c4_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c4_token_we), - .wd (message_header_c4_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c4_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c4_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c4_field1_we), - .wd (message_header_c4_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c4_field1_qs) - ); - - - // R[message_payload_1_c4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c4_we), - .wd (message_payload_1_c4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c4_qs) - ); - - - // R[doorbell_c4]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c4_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c4_intr_we), - .wd (doorbell_c4_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c4.intr.q ), - - // to register interface (read) - .qs (doorbell_c4_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c4_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c4_preserve_mask_we), - .wd (doorbell_c4_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c4.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c4_preserve_mask_qs) - ); - - - // R[completion_interrupt_c4]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c4_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c4_intr_we), - .wd (completion_interrupt_c4_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c4.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c4_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c4_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c4_preserve_mask_we), - .wd (completion_interrupt_c4_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c4.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c4_preserve_mask_qs) - ); - - - // R[reserved_1_c5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c5_we), - .wd (reserved_1_c5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c5_qs) - ); - - - // R[channel_status_c5]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c5_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c5_channel_free_we), - .wd (channel_status_c5_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c5_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c5_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c5_channel_error_we), - .wd (channel_status_c5_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c5_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c5_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c5_field1_we), - .wd (channel_status_c5_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c5_field1_qs) - ); - - - // R[reserved_2_c5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c5_we), - .wd (reserved_2_c5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c5_qs) - ); - - - // R[reserved_3_c5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c5]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c5_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c5_intr_enable_we), - .wd (channel_flags_c5_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c5_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c5_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c5_field1_we), - .wd (channel_flags_c5_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c5_field1_qs) - ); - - - // R[length_c5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c5_we), - .wd (length_c5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c5_qs) - ); - - - // R[message_header_c5]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c5_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c5_message_id_we), - .wd (message_header_c5_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c5_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c5_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c5_message_type_we), - .wd (message_header_c5_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c5_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c5_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c5_protocol_id_we), - .wd (message_header_c5_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c5_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c5_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c5_token_we), - .wd (message_header_c5_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c5_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c5_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c5_field1_we), - .wd (message_header_c5_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c5_field1_qs) - ); - - - // R[message_payload_1_c5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c5_we), - .wd (message_payload_1_c5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c5_qs) - ); - - - // R[doorbell_c5]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c5_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c5_intr_we), - .wd (doorbell_c5_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c5.intr.q ), - - // to register interface (read) - .qs (doorbell_c5_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c5_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c5_preserve_mask_we), - .wd (doorbell_c5_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c5.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c5_preserve_mask_qs) - ); - - - // R[completion_interrupt_c5]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c5_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c5_intr_we), - .wd (completion_interrupt_c5_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c5.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c5_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c5_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c5_preserve_mask_we), - .wd (completion_interrupt_c5_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c5.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c5_preserve_mask_qs) - ); - - - // R[reserved_1_c6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c6_we), - .wd (reserved_1_c6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c6_qs) - ); - - - // R[channel_status_c6]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c6_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c6_channel_free_we), - .wd (channel_status_c6_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c6_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c6_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c6_channel_error_we), - .wd (channel_status_c6_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c6_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c6_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c6_field1_we), - .wd (channel_status_c6_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c6_field1_qs) - ); - - - // R[reserved_2_c6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c6_we), - .wd (reserved_2_c6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c6_qs) - ); - - - // R[reserved_3_c6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c6]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c6_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c6_intr_enable_we), - .wd (channel_flags_c6_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c6_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c6_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c6_field1_we), - .wd (channel_flags_c6_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c6_field1_qs) - ); - - - // R[length_c6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c6_we), - .wd (length_c6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c6_qs) - ); - - - // R[message_header_c6]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c6_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c6_message_id_we), - .wd (message_header_c6_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c6_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c6_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c6_message_type_we), - .wd (message_header_c6_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c6_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c6_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c6_protocol_id_we), - .wd (message_header_c6_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c6_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c6_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c6_token_we), - .wd (message_header_c6_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c6_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c6_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c6_field1_we), - .wd (message_header_c6_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c6_field1_qs) - ); - - - // R[message_payload_1_c6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c6_we), - .wd (message_payload_1_c6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c6_qs) - ); - - - // R[doorbell_c6]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c6_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c6_intr_we), - .wd (doorbell_c6_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c6.intr.q ), - - // to register interface (read) - .qs (doorbell_c6_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c6_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c6_preserve_mask_we), - .wd (doorbell_c6_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c6.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c6_preserve_mask_qs) - ); - - - // R[completion_interrupt_c6]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c6_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c6_intr_we), - .wd (completion_interrupt_c6_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c6.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c6_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c6_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c6_preserve_mask_we), - .wd (completion_interrupt_c6_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c6.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c6_preserve_mask_qs) - ); - - - // R[reserved_1_c7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c7_we), - .wd (reserved_1_c7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c7_qs) - ); - - - // R[channel_status_c7]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c7_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c7_channel_free_we), - .wd (channel_status_c7_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c7_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c7_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c7_channel_error_we), - .wd (channel_status_c7_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c7_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c7_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c7_field1_we), - .wd (channel_status_c7_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c7_field1_qs) - ); - - - // R[reserved_2_c7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c7_we), - .wd (reserved_2_c7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c7_qs) - ); - - - // R[reserved_3_c7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c7]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c7_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c7_intr_enable_we), - .wd (channel_flags_c7_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c7_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c7_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c7_field1_we), - .wd (channel_flags_c7_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c7_field1_qs) - ); - - - // R[length_c7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c7_we), - .wd (length_c7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c7_qs) - ); - - - // R[message_header_c7]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c7_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c7_message_id_we), - .wd (message_header_c7_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c7_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c7_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c7_message_type_we), - .wd (message_header_c7_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c7_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c7_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c7_protocol_id_we), - .wd (message_header_c7_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c7_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c7_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c7_token_we), - .wd (message_header_c7_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c7_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c7_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c7_field1_we), - .wd (message_header_c7_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c7_field1_qs) - ); - - - // R[message_payload_1_c7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c7_we), - .wd (message_payload_1_c7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c7_qs) - ); - - - // R[doorbell_c7]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c7_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c7_intr_we), - .wd (doorbell_c7_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c7.intr.q ), - - // to register interface (read) - .qs (doorbell_c7_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c7_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c7_preserve_mask_we), - .wd (doorbell_c7_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c7.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c7_preserve_mask_qs) - ); - - - // R[completion_interrupt_c7]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c7_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c7_intr_we), - .wd (completion_interrupt_c7_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c7.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c7_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c7_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c7_preserve_mask_we), - .wd (completion_interrupt_c7_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c7.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c7_preserve_mask_qs) - ); - - - // R[reserved_1_c8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c8_we), - .wd (reserved_1_c8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c8_qs) - ); - - - // R[channel_status_c8]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c8_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c8_channel_free_we), - .wd (channel_status_c8_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c8_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c8_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c8_channel_error_we), - .wd (channel_status_c8_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c8_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c8_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c8_field1_we), - .wd (channel_status_c8_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c8_field1_qs) - ); - - - // R[reserved_2_c8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c8_we), - .wd (reserved_2_c8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c8_qs) - ); - - - // R[reserved_3_c8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c8]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c8_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c8_intr_enable_we), - .wd (channel_flags_c8_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c8_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c8_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c8_field1_we), - .wd (channel_flags_c8_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c8_field1_qs) - ); - - - // R[length_c8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c8_we), - .wd (length_c8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c8_qs) - ); - - - // R[message_header_c8]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c8_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c8_message_id_we), - .wd (message_header_c8_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c8_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c8_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c8_message_type_we), - .wd (message_header_c8_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c8_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c8_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c8_protocol_id_we), - .wd (message_header_c8_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c8_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c8_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c8_token_we), - .wd (message_header_c8_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c8_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c8_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c8_field1_we), - .wd (message_header_c8_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c8_field1_qs) - ); - - - // R[message_payload_1_c8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c8_we), - .wd (message_payload_1_c8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c8_qs) - ); - - - // R[doorbell_c8]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c8_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c8_intr_we), - .wd (doorbell_c8_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c8.intr.q ), - - // to register interface (read) - .qs (doorbell_c8_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c8_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c8_preserve_mask_we), - .wd (doorbell_c8_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c8.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c8_preserve_mask_qs) - ); - - - // R[completion_interrupt_c8]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c8_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c8_intr_we), - .wd (completion_interrupt_c8_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c8.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c8_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c8_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c8_preserve_mask_we), - .wd (completion_interrupt_c8_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c8.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c8_preserve_mask_qs) - ); - - - // R[reserved_1_c9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c9_we), - .wd (reserved_1_c9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c9_qs) - ); - - - // R[channel_status_c9]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c9_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c9_channel_free_we), - .wd (channel_status_c9_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c9_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c9_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c9_channel_error_we), - .wd (channel_status_c9_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c9_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c9_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c9_field1_we), - .wd (channel_status_c9_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c9_field1_qs) - ); - - - // R[reserved_2_c9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c9_we), - .wd (reserved_2_c9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c9_qs) - ); - - - // R[reserved_3_c9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c9]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c9_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c9_intr_enable_we), - .wd (channel_flags_c9_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c9_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c9_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c9_field1_we), - .wd (channel_flags_c9_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c9_field1_qs) - ); - - - // R[length_c9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c9_we), - .wd (length_c9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c9_qs) - ); - - - // R[message_header_c9]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c9_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c9_message_id_we), - .wd (message_header_c9_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c9_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c9_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c9_message_type_we), - .wd (message_header_c9_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c9_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c9_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c9_protocol_id_we), - .wd (message_header_c9_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c9_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c9_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c9_token_we), - .wd (message_header_c9_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c9_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c9_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c9_field1_we), - .wd (message_header_c9_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c9_field1_qs) - ); - - - // R[message_payload_1_c9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c9_we), - .wd (message_payload_1_c9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c9_qs) - ); - - - // R[doorbell_c9]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c9_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c9_intr_we), - .wd (doorbell_c9_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c9.intr.q ), - - // to register interface (read) - .qs (doorbell_c9_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c9_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c9_preserve_mask_we), - .wd (doorbell_c9_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c9.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c9_preserve_mask_qs) - ); - - - // R[completion_interrupt_c9]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c9_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c9_intr_we), - .wd (completion_interrupt_c9_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c9.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c9_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c9_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c9_preserve_mask_we), - .wd (completion_interrupt_c9_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c9.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c9_preserve_mask_qs) - ); - - - // R[reserved_1_c10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c10_we), - .wd (reserved_1_c10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c10_qs) - ); - - - // R[channel_status_c10]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c10_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c10_channel_free_we), - .wd (channel_status_c10_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c10_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c10_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c10_channel_error_we), - .wd (channel_status_c10_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c10_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c10_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c10_field1_we), - .wd (channel_status_c10_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c10_field1_qs) - ); - - - // R[reserved_2_c10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c10_we), - .wd (reserved_2_c10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c10_qs) - ); - - - // R[reserved_3_c10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c10]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c10_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c10_intr_enable_we), - .wd (channel_flags_c10_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c10_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c10_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c10_field1_we), - .wd (channel_flags_c10_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c10_field1_qs) - ); - - - // R[length_c10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c10_we), - .wd (length_c10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c10_qs) - ); - - - // R[message_header_c10]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c10_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c10_message_id_we), - .wd (message_header_c10_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c10_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c10_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c10_message_type_we), - .wd (message_header_c10_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c10_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c10_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c10_protocol_id_we), - .wd (message_header_c10_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c10_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c10_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c10_token_we), - .wd (message_header_c10_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c10_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c10_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c10_field1_we), - .wd (message_header_c10_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c10_field1_qs) - ); - - - // R[message_payload_1_c10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c10_we), - .wd (message_payload_1_c10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c10_qs) - ); - - - // R[doorbell_c10]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c10_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c10_intr_we), - .wd (doorbell_c10_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c10.intr.q ), - - // to register interface (read) - .qs (doorbell_c10_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c10_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c10_preserve_mask_we), - .wd (doorbell_c10_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c10.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c10_preserve_mask_qs) - ); - - - // R[completion_interrupt_c10]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c10_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c10_intr_we), - .wd (completion_interrupt_c10_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c10.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c10_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c10_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c10_preserve_mask_we), - .wd (completion_interrupt_c10_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c10.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c10_preserve_mask_qs) - ); - - - // R[reserved_1_c11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c11_we), - .wd (reserved_1_c11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c11_qs) - ); - - - // R[channel_status_c11]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c11_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c11_channel_free_we), - .wd (channel_status_c11_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c11_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c11_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c11_channel_error_we), - .wd (channel_status_c11_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c11_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c11_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c11_field1_we), - .wd (channel_status_c11_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c11_field1_qs) - ); - - - // R[reserved_2_c11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c11_we), - .wd (reserved_2_c11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c11_qs) - ); - - - // R[reserved_3_c11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c11]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c11_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c11_intr_enable_we), - .wd (channel_flags_c11_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c11_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c11_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c11_field1_we), - .wd (channel_flags_c11_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c11_field1_qs) - ); - - - // R[length_c11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c11_we), - .wd (length_c11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c11_qs) - ); - - - // R[message_header_c11]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c11_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c11_message_id_we), - .wd (message_header_c11_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c11_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c11_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c11_message_type_we), - .wd (message_header_c11_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c11_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c11_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c11_protocol_id_we), - .wd (message_header_c11_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c11_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c11_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c11_token_we), - .wd (message_header_c11_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c11_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c11_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c11_field1_we), - .wd (message_header_c11_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c11_field1_qs) - ); - - - // R[message_payload_1_c11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c11_we), - .wd (message_payload_1_c11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c11_qs) - ); - - - // R[doorbell_c11]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c11_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c11_intr_we), - .wd (doorbell_c11_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c11.intr.q ), - - // to register interface (read) - .qs (doorbell_c11_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c11_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c11_preserve_mask_we), - .wd (doorbell_c11_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c11.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c11_preserve_mask_qs) - ); - - - // R[completion_interrupt_c11]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c11_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c11_intr_we), - .wd (completion_interrupt_c11_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c11.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c11_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c11_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c11_preserve_mask_we), - .wd (completion_interrupt_c11_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c11.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c11_preserve_mask_qs) - ); - - - // R[reserved_1_c12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c12_we), - .wd (reserved_1_c12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c12_qs) - ); - - - // R[channel_status_c12]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c12_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c12_channel_free_we), - .wd (channel_status_c12_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c12_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c12_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c12_channel_error_we), - .wd (channel_status_c12_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c12_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c12_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c12_field1_we), - .wd (channel_status_c12_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c12_field1_qs) - ); - - - // R[reserved_2_c12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c12_we), - .wd (reserved_2_c12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c12_qs) - ); - - - // R[reserved_3_c12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c12]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c12_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c12_intr_enable_we), - .wd (channel_flags_c12_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c12_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c12_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c12_field1_we), - .wd (channel_flags_c12_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c12_field1_qs) - ); - - - // R[length_c12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c12_we), - .wd (length_c12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c12_qs) - ); - - - // R[message_header_c12]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c12_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c12_message_id_we), - .wd (message_header_c12_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c12_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c12_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c12_message_type_we), - .wd (message_header_c12_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c12_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c12_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c12_protocol_id_we), - .wd (message_header_c12_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c12_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c12_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c12_token_we), - .wd (message_header_c12_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c12_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c12_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c12_field1_we), - .wd (message_header_c12_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c12_field1_qs) - ); - - - // R[message_payload_1_c12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c12_we), - .wd (message_payload_1_c12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c12_qs) - ); - - - // R[doorbell_c12]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c12_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c12_intr_we), - .wd (doorbell_c12_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c12.intr.q ), - - // to register interface (read) - .qs (doorbell_c12_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c12_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c12_preserve_mask_we), - .wd (doorbell_c12_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c12.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c12_preserve_mask_qs) - ); - - - // R[completion_interrupt_c12]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c12_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c12_intr_we), - .wd (completion_interrupt_c12_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c12.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c12_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c12_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c12_preserve_mask_we), - .wd (completion_interrupt_c12_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c12.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c12_preserve_mask_qs) - ); - - - // R[reserved_1_c13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c13_we), - .wd (reserved_1_c13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c13_qs) - ); - - - // R[channel_status_c13]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c13_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c13_channel_free_we), - .wd (channel_status_c13_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c13_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c13_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c13_channel_error_we), - .wd (channel_status_c13_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c13_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c13_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c13_field1_we), - .wd (channel_status_c13_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c13_field1_qs) - ); - - - // R[reserved_2_c13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c13_we), - .wd (reserved_2_c13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c13_qs) - ); - - - // R[reserved_3_c13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c13]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c13_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c13_intr_enable_we), - .wd (channel_flags_c13_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c13_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c13_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c13_field1_we), - .wd (channel_flags_c13_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c13_field1_qs) - ); - - - // R[length_c13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c13_we), - .wd (length_c13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c13_qs) - ); - - - // R[message_header_c13]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c13_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c13_message_id_we), - .wd (message_header_c13_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c13_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c13_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c13_message_type_we), - .wd (message_header_c13_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c13_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c13_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c13_protocol_id_we), - .wd (message_header_c13_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c13_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c13_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c13_token_we), - .wd (message_header_c13_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c13_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c13_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c13_field1_we), - .wd (message_header_c13_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c13_field1_qs) - ); - - - // R[message_payload_1_c13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c13_we), - .wd (message_payload_1_c13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c13_qs) - ); - - - // R[doorbell_c13]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c13_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c13_intr_we), - .wd (doorbell_c13_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c13.intr.q ), - - // to register interface (read) - .qs (doorbell_c13_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c13_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c13_preserve_mask_we), - .wd (doorbell_c13_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c13.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c13_preserve_mask_qs) - ); - - - // R[completion_interrupt_c13]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c13_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c13_intr_we), - .wd (completion_interrupt_c13_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c13.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c13_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c13_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c13_preserve_mask_we), - .wd (completion_interrupt_c13_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c13.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c13_preserve_mask_qs) - ); - - - // R[reserved_1_c14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c14_we), - .wd (reserved_1_c14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c14_qs) - ); - - - // R[channel_status_c14]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c14_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c14_channel_free_we), - .wd (channel_status_c14_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c14_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c14_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c14_channel_error_we), - .wd (channel_status_c14_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c14_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c14_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c14_field1_we), - .wd (channel_status_c14_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c14_field1_qs) - ); - - - // R[reserved_2_c14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c14_we), - .wd (reserved_2_c14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c14_qs) - ); - - - // R[reserved_3_c14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c14]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c14_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c14_intr_enable_we), - .wd (channel_flags_c14_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c14_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c14_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c14_field1_we), - .wd (channel_flags_c14_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c14_field1_qs) - ); - - - // R[length_c14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c14_we), - .wd (length_c14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c14_qs) - ); - - - // R[message_header_c14]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c14_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c14_message_id_we), - .wd (message_header_c14_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c14_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c14_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c14_message_type_we), - .wd (message_header_c14_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c14_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c14_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c14_protocol_id_we), - .wd (message_header_c14_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c14_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c14_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c14_token_we), - .wd (message_header_c14_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c14_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c14_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c14_field1_we), - .wd (message_header_c14_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c14_field1_qs) - ); - - - // R[message_payload_1_c14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c14_we), - .wd (message_payload_1_c14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c14_qs) - ); - - - // R[doorbell_c14]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c14_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c14_intr_we), - .wd (doorbell_c14_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c14.intr.q ), - - // to register interface (read) - .qs (doorbell_c14_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c14_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c14_preserve_mask_we), - .wd (doorbell_c14_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c14.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c14_preserve_mask_qs) - ); - - - // R[completion_interrupt_c14]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c14_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c14_intr_we), - .wd (completion_interrupt_c14_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c14.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c14_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c14_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c14_preserve_mask_we), - .wd (completion_interrupt_c14_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c14.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c14_preserve_mask_qs) - ); - - - // R[reserved_1_c15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c15_we), - .wd (reserved_1_c15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c15_qs) - ); - - - // R[channel_status_c15]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c15_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c15_channel_free_we), - .wd (channel_status_c15_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c15_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c15_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c15_channel_error_we), - .wd (channel_status_c15_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c15_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c15_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c15_field1_we), - .wd (channel_status_c15_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c15_field1_qs) - ); - - - // R[reserved_2_c15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c15_we), - .wd (reserved_2_c15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c15_qs) - ); - - - // R[reserved_3_c15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c15]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c15_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c15_intr_enable_we), - .wd (channel_flags_c15_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c15_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c15_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c15_field1_we), - .wd (channel_flags_c15_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c15_field1_qs) - ); - - - // R[length_c15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c15_we), - .wd (length_c15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c15_qs) - ); - - - // R[message_header_c15]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c15_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c15_message_id_we), - .wd (message_header_c15_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c15_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c15_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c15_message_type_we), - .wd (message_header_c15_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c15_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c15_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c15_protocol_id_we), - .wd (message_header_c15_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c15_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c15_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c15_token_we), - .wd (message_header_c15_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c15_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c15_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c15_field1_we), - .wd (message_header_c15_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c15_field1_qs) - ); - - - // R[message_payload_1_c15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c15_we), - .wd (message_payload_1_c15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c15_qs) - ); - - - // R[doorbell_c15]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c15_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c15_intr_we), - .wd (doorbell_c15_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c15.intr.q ), - - // to register interface (read) - .qs (doorbell_c15_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c15_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c15_preserve_mask_we), - .wd (doorbell_c15_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c15.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c15_preserve_mask_qs) - ); - - - // R[completion_interrupt_c15]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c15_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c15_intr_we), - .wd (completion_interrupt_c15_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c15.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c15_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c15_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c15_preserve_mask_we), - .wd (completion_interrupt_c15_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c15.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c15_preserve_mask_qs) - ); - - - // R[reserved_1_c16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c16_we), - .wd (reserved_1_c16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c16_qs) - ); - - - // R[channel_status_c16]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c16_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c16_channel_free_we), - .wd (channel_status_c16_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c16_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c16_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c16_channel_error_we), - .wd (channel_status_c16_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c16_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c16_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c16_field1_we), - .wd (channel_status_c16_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c16_field1_qs) - ); - - - // R[reserved_2_c16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c16_we), - .wd (reserved_2_c16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c16_qs) - ); - - - // R[reserved_3_c16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c16]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c16_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c16_intr_enable_we), - .wd (channel_flags_c16_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c16_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c16_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c16_field1_we), - .wd (channel_flags_c16_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c16_field1_qs) - ); - - - // R[length_c16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c16_we), - .wd (length_c16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c16_qs) - ); - - - // R[message_header_c16]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c16_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c16_message_id_we), - .wd (message_header_c16_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c16_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c16_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c16_message_type_we), - .wd (message_header_c16_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c16_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c16_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c16_protocol_id_we), - .wd (message_header_c16_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c16_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c16_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c16_token_we), - .wd (message_header_c16_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c16_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c16_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c16_field1_we), - .wd (message_header_c16_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c16_field1_qs) - ); - - - // R[message_payload_1_c16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c16_we), - .wd (message_payload_1_c16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c16_qs) - ); - - - // R[doorbell_c16]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c16_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c16_intr_we), - .wd (doorbell_c16_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c16.intr.q ), - - // to register interface (read) - .qs (doorbell_c16_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c16_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c16_preserve_mask_we), - .wd (doorbell_c16_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c16.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c16_preserve_mask_qs) - ); - - - // R[completion_interrupt_c16]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c16_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c16_intr_we), - .wd (completion_interrupt_c16_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c16.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c16_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c16_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c16_preserve_mask_we), - .wd (completion_interrupt_c16_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c16.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c16_preserve_mask_qs) - ); - - - // R[reserved_1_c17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c17_we), - .wd (reserved_1_c17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c17_qs) - ); - - - // R[channel_status_c17]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c17_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c17_channel_free_we), - .wd (channel_status_c17_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c17_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c17_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c17_channel_error_we), - .wd (channel_status_c17_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c17_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c17_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c17_field1_we), - .wd (channel_status_c17_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c17_field1_qs) - ); - - - // R[reserved_2_c17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c17_we), - .wd (reserved_2_c17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c17_qs) - ); - - - // R[reserved_3_c17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c17]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c17_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c17_intr_enable_we), - .wd (channel_flags_c17_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c17_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c17_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c17_field1_we), - .wd (channel_flags_c17_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c17_field1_qs) - ); - - - // R[length_c17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c17_we), - .wd (length_c17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c17_qs) - ); - - - // R[message_header_c17]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c17_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c17_message_id_we), - .wd (message_header_c17_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c17_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c17_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c17_message_type_we), - .wd (message_header_c17_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c17_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c17_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c17_protocol_id_we), - .wd (message_header_c17_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c17_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c17_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c17_token_we), - .wd (message_header_c17_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c17_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c17_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c17_field1_we), - .wd (message_header_c17_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c17_field1_qs) - ); - - - // R[message_payload_1_c17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c17_we), - .wd (message_payload_1_c17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c17_qs) - ); - - - // R[doorbell_c17]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c17_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c17_intr_we), - .wd (doorbell_c17_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c17.intr.q ), - - // to register interface (read) - .qs (doorbell_c17_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c17_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c17_preserve_mask_we), - .wd (doorbell_c17_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c17.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c17_preserve_mask_qs) - ); - - - // R[completion_interrupt_c17]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c17_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c17_intr_we), - .wd (completion_interrupt_c17_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c17.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c17_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c17_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c17_preserve_mask_we), - .wd (completion_interrupt_c17_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c17.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c17_preserve_mask_qs) - ); - - - // R[reserved_1_c18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c18_we), - .wd (reserved_1_c18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c18_qs) - ); - - - // R[channel_status_c18]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c18_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c18_channel_free_we), - .wd (channel_status_c18_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c18_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c18_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c18_channel_error_we), - .wd (channel_status_c18_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c18_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c18_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c18_field1_we), - .wd (channel_status_c18_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c18_field1_qs) - ); - - - // R[reserved_2_c18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c18_we), - .wd (reserved_2_c18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c18_qs) - ); - - - // R[reserved_3_c18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c18]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c18_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c18_intr_enable_we), - .wd (channel_flags_c18_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c18_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c18_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c18_field1_we), - .wd (channel_flags_c18_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c18_field1_qs) - ); - - - // R[length_c18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c18_we), - .wd (length_c18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c18_qs) - ); - - - // R[message_header_c18]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c18_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c18_message_id_we), - .wd (message_header_c18_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c18_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c18_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c18_message_type_we), - .wd (message_header_c18_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c18_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c18_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c18_protocol_id_we), - .wd (message_header_c18_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c18_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c18_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c18_token_we), - .wd (message_header_c18_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c18_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c18_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c18_field1_we), - .wd (message_header_c18_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c18_field1_qs) - ); - - - // R[message_payload_1_c18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c18_we), - .wd (message_payload_1_c18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c18_qs) - ); - - - // R[doorbell_c18]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c18_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c18_intr_we), - .wd (doorbell_c18_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c18.intr.q ), - - // to register interface (read) - .qs (doorbell_c18_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c18_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c18_preserve_mask_we), - .wd (doorbell_c18_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c18.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c18_preserve_mask_qs) - ); - - - // R[completion_interrupt_c18]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c18_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c18_intr_we), - .wd (completion_interrupt_c18_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c18.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c18_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c18_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c18_preserve_mask_we), - .wd (completion_interrupt_c18_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c18.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c18_preserve_mask_qs) - ); - - - // R[reserved_1_c19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c19_we), - .wd (reserved_1_c19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c19_qs) - ); - - - // R[channel_status_c19]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c19_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c19_channel_free_we), - .wd (channel_status_c19_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c19_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c19_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c19_channel_error_we), - .wd (channel_status_c19_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c19_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c19_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c19_field1_we), - .wd (channel_status_c19_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c19_field1_qs) - ); - - - // R[reserved_2_c19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c19_we), - .wd (reserved_2_c19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c19_qs) - ); - - - // R[reserved_3_c19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c19]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c19_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c19_intr_enable_we), - .wd (channel_flags_c19_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c19_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c19_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c19_field1_we), - .wd (channel_flags_c19_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c19_field1_qs) - ); - - - // R[length_c19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c19_we), - .wd (length_c19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c19_qs) - ); - - - // R[message_header_c19]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c19_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c19_message_id_we), - .wd (message_header_c19_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c19_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c19_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c19_message_type_we), - .wd (message_header_c19_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c19_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c19_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c19_protocol_id_we), - .wd (message_header_c19_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c19_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c19_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c19_token_we), - .wd (message_header_c19_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c19_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c19_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c19_field1_we), - .wd (message_header_c19_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c19_field1_qs) - ); - - - // R[message_payload_1_c19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c19_we), - .wd (message_payload_1_c19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c19_qs) - ); - - - // R[doorbell_c19]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c19_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c19_intr_we), - .wd (doorbell_c19_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c19.intr.q ), - - // to register interface (read) - .qs (doorbell_c19_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c19_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c19_preserve_mask_we), - .wd (doorbell_c19_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c19.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c19_preserve_mask_qs) - ); - - - // R[completion_interrupt_c19]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c19_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c19_intr_we), - .wd (completion_interrupt_c19_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c19.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c19_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c19_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c19_preserve_mask_we), - .wd (completion_interrupt_c19_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c19.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c19_preserve_mask_qs) - ); - - - // R[reserved_1_c20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c20_we), - .wd (reserved_1_c20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c20_qs) - ); - - - // R[channel_status_c20]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c20_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c20_channel_free_we), - .wd (channel_status_c20_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c20_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c20_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c20_channel_error_we), - .wd (channel_status_c20_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c20_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c20_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c20_field1_we), - .wd (channel_status_c20_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c20_field1_qs) - ); - - - // R[reserved_2_c20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c20_we), - .wd (reserved_2_c20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c20_qs) - ); - - - // R[reserved_3_c20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c20]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c20_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c20_intr_enable_we), - .wd (channel_flags_c20_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c20_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c20_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c20_field1_we), - .wd (channel_flags_c20_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c20_field1_qs) - ); - - - // R[length_c20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c20_we), - .wd (length_c20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c20_qs) - ); - - - // R[message_header_c20]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c20_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c20_message_id_we), - .wd (message_header_c20_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c20_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c20_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c20_message_type_we), - .wd (message_header_c20_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c20_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c20_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c20_protocol_id_we), - .wd (message_header_c20_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c20_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c20_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c20_token_we), - .wd (message_header_c20_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c20_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c20_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c20_field1_we), - .wd (message_header_c20_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c20_field1_qs) - ); - - - // R[message_payload_1_c20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c20_we), - .wd (message_payload_1_c20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c20_qs) - ); - - - // R[doorbell_c20]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c20_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c20_intr_we), - .wd (doorbell_c20_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c20.intr.q ), - - // to register interface (read) - .qs (doorbell_c20_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c20_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c20_preserve_mask_we), - .wd (doorbell_c20_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c20.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c20_preserve_mask_qs) - ); - - - // R[completion_interrupt_c20]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c20_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c20_intr_we), - .wd (completion_interrupt_c20_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c20.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c20_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c20_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c20_preserve_mask_we), - .wd (completion_interrupt_c20_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c20.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c20_preserve_mask_qs) - ); - - - // R[reserved_1_c21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c21_we), - .wd (reserved_1_c21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c21_qs) - ); - - - // R[channel_status_c21]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c21_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c21_channel_free_we), - .wd (channel_status_c21_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c21_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c21_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c21_channel_error_we), - .wd (channel_status_c21_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c21_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c21_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c21_field1_we), - .wd (channel_status_c21_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c21_field1_qs) - ); - - - // R[reserved_2_c21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c21_we), - .wd (reserved_2_c21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c21_qs) - ); - - - // R[reserved_3_c21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c21]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c21_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c21_intr_enable_we), - .wd (channel_flags_c21_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c21_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c21_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c21_field1_we), - .wd (channel_flags_c21_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c21_field1_qs) - ); - - - // R[length_c21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c21_we), - .wd (length_c21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c21_qs) - ); - - - // R[message_header_c21]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c21_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c21_message_id_we), - .wd (message_header_c21_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c21_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c21_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c21_message_type_we), - .wd (message_header_c21_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c21_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c21_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c21_protocol_id_we), - .wd (message_header_c21_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c21_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c21_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c21_token_we), - .wd (message_header_c21_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c21_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c21_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c21_field1_we), - .wd (message_header_c21_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c21_field1_qs) - ); - - - // R[message_payload_1_c21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c21_we), - .wd (message_payload_1_c21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c21_qs) - ); - - - // R[doorbell_c21]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c21_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c21_intr_we), - .wd (doorbell_c21_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c21.intr.q ), - - // to register interface (read) - .qs (doorbell_c21_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c21_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c21_preserve_mask_we), - .wd (doorbell_c21_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c21.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c21_preserve_mask_qs) - ); - - - // R[completion_interrupt_c21]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c21_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c21_intr_we), - .wd (completion_interrupt_c21_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c21.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c21_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c21_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c21_preserve_mask_we), - .wd (completion_interrupt_c21_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c21.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c21_preserve_mask_qs) - ); - - - // R[reserved_1_c22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c22_we), - .wd (reserved_1_c22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c22_qs) - ); - - - // R[channel_status_c22]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c22_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c22_channel_free_we), - .wd (channel_status_c22_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c22_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c22_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c22_channel_error_we), - .wd (channel_status_c22_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c22_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c22_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c22_field1_we), - .wd (channel_status_c22_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c22_field1_qs) - ); - - - // R[reserved_2_c22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c22_we), - .wd (reserved_2_c22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c22_qs) - ); - - - // R[reserved_3_c22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c22]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c22_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c22_intr_enable_we), - .wd (channel_flags_c22_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c22_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c22_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c22_field1_we), - .wd (channel_flags_c22_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c22_field1_qs) - ); - - - // R[length_c22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c22_we), - .wd (length_c22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c22_qs) - ); - - - // R[message_header_c22]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c22_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c22_message_id_we), - .wd (message_header_c22_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c22_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c22_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c22_message_type_we), - .wd (message_header_c22_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c22_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c22_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c22_protocol_id_we), - .wd (message_header_c22_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c22_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c22_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c22_token_we), - .wd (message_header_c22_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c22_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c22_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c22_field1_we), - .wd (message_header_c22_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c22_field1_qs) - ); - - - // R[message_payload_1_c22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c22_we), - .wd (message_payload_1_c22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c22_qs) - ); - - - // R[doorbell_c22]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c22_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c22_intr_we), - .wd (doorbell_c22_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c22.intr.q ), - - // to register interface (read) - .qs (doorbell_c22_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c22_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c22_preserve_mask_we), - .wd (doorbell_c22_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c22.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c22_preserve_mask_qs) - ); - - - // R[completion_interrupt_c22]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c22_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c22_intr_we), - .wd (completion_interrupt_c22_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c22.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c22_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c22_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c22_preserve_mask_we), - .wd (completion_interrupt_c22_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c22.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c22_preserve_mask_qs) - ); - - - // R[reserved_1_c23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c23_we), - .wd (reserved_1_c23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c23_qs) - ); - - - // R[channel_status_c23]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c23_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c23_channel_free_we), - .wd (channel_status_c23_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c23_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c23_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c23_channel_error_we), - .wd (channel_status_c23_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c23_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c23_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c23_field1_we), - .wd (channel_status_c23_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c23_field1_qs) - ); - - - // R[reserved_2_c23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c23_we), - .wd (reserved_2_c23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c23_qs) - ); - - - // R[reserved_3_c23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c23]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c23_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c23_intr_enable_we), - .wd (channel_flags_c23_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c23_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c23_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c23_field1_we), - .wd (channel_flags_c23_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c23_field1_qs) - ); - - - // R[length_c23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c23_we), - .wd (length_c23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c23_qs) - ); - - - // R[message_header_c23]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c23_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c23_message_id_we), - .wd (message_header_c23_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c23_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c23_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c23_message_type_we), - .wd (message_header_c23_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c23_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c23_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c23_protocol_id_we), - .wd (message_header_c23_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c23_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c23_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c23_token_we), - .wd (message_header_c23_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c23_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c23_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c23_field1_we), - .wd (message_header_c23_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c23_field1_qs) - ); - - - // R[message_payload_1_c23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c23_we), - .wd (message_payload_1_c23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c23_qs) - ); - - - // R[doorbell_c23]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c23_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c23_intr_we), - .wd (doorbell_c23_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c23.intr.q ), - - // to register interface (read) - .qs (doorbell_c23_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c23_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c23_preserve_mask_we), - .wd (doorbell_c23_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c23.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c23_preserve_mask_qs) - ); - - - // R[completion_interrupt_c23]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c23_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c23_intr_we), - .wd (completion_interrupt_c23_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c23.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c23_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c23_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c23_preserve_mask_we), - .wd (completion_interrupt_c23_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c23.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c23_preserve_mask_qs) - ); - - - // R[reserved_1_c24]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c24_we), - .wd (reserved_1_c24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c24_qs) - ); - - - // R[channel_status_c24]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c24_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c24_channel_free_we), - .wd (channel_status_c24_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c24_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c24_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c24_channel_error_we), - .wd (channel_status_c24_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c24_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c24_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c24_field1_we), - .wd (channel_status_c24_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c24_field1_qs) - ); - - - // R[reserved_2_c24]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c24_we), - .wd (reserved_2_c24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c24_qs) - ); - - - // R[reserved_3_c24]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c24]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c24_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c24_intr_enable_we), - .wd (channel_flags_c24_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c24_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c24_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c24_field1_we), - .wd (channel_flags_c24_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c24_field1_qs) - ); - - - // R[length_c24]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c24_we), - .wd (length_c24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c24_qs) - ); - - - // R[message_header_c24]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c24_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c24_message_id_we), - .wd (message_header_c24_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c24_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c24_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c24_message_type_we), - .wd (message_header_c24_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c24_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c24_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c24_protocol_id_we), - .wd (message_header_c24_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c24_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c24_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c24_token_we), - .wd (message_header_c24_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c24_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c24_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c24_field1_we), - .wd (message_header_c24_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c24_field1_qs) - ); - - - // R[message_payload_1_c24]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c24 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c24_we), - .wd (message_payload_1_c24_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c24_qs) - ); - - - // R[doorbell_c24]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c24_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c24_intr_we), - .wd (doorbell_c24_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c24.intr.q ), - - // to register interface (read) - .qs (doorbell_c24_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c24_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c24_preserve_mask_we), - .wd (doorbell_c24_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c24.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c24_preserve_mask_qs) - ); - - - // R[completion_interrupt_c24]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c24_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c24_intr_we), - .wd (completion_interrupt_c24_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c24.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c24_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c24_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c24_preserve_mask_we), - .wd (completion_interrupt_c24_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c24.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c24_preserve_mask_qs) - ); - - - // R[reserved_1_c25]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c25_we), - .wd (reserved_1_c25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c25_qs) - ); - - - // R[channel_status_c25]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c25_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c25_channel_free_we), - .wd (channel_status_c25_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c25_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c25_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c25_channel_error_we), - .wd (channel_status_c25_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c25_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c25_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c25_field1_we), - .wd (channel_status_c25_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c25_field1_qs) - ); - - - // R[reserved_2_c25]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c25_we), - .wd (reserved_2_c25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c25_qs) - ); - - - // R[reserved_3_c25]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c25]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c25_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c25_intr_enable_we), - .wd (channel_flags_c25_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c25_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c25_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c25_field1_we), - .wd (channel_flags_c25_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c25_field1_qs) - ); - - - // R[length_c25]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c25_we), - .wd (length_c25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c25_qs) - ); - - - // R[message_header_c25]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c25_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c25_message_id_we), - .wd (message_header_c25_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c25_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c25_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c25_message_type_we), - .wd (message_header_c25_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c25_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c25_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c25_protocol_id_we), - .wd (message_header_c25_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c25_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c25_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c25_token_we), - .wd (message_header_c25_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c25_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c25_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c25_field1_we), - .wd (message_header_c25_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c25_field1_qs) - ); - - - // R[message_payload_1_c25]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c25 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c25_we), - .wd (message_payload_1_c25_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c25_qs) - ); - - - // R[doorbell_c25]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c25_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c25_intr_we), - .wd (doorbell_c25_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c25.intr.q ), - - // to register interface (read) - .qs (doorbell_c25_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c25_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c25_preserve_mask_we), - .wd (doorbell_c25_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c25.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c25_preserve_mask_qs) - ); - - - // R[completion_interrupt_c25]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c25_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c25_intr_we), - .wd (completion_interrupt_c25_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c25.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c25_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c25_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c25_preserve_mask_we), - .wd (completion_interrupt_c25_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c25.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c25_preserve_mask_qs) - ); - - - // R[reserved_1_c26]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c26_we), - .wd (reserved_1_c26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c26_qs) - ); - - - // R[channel_status_c26]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c26_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c26_channel_free_we), - .wd (channel_status_c26_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c26_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c26_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c26_channel_error_we), - .wd (channel_status_c26_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c26_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c26_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c26_field1_we), - .wd (channel_status_c26_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c26_field1_qs) - ); - - - // R[reserved_2_c26]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c26_we), - .wd (reserved_2_c26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c26_qs) - ); - - - // R[reserved_3_c26]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c26]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c26_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c26_intr_enable_we), - .wd (channel_flags_c26_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c26_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c26_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c26_field1_we), - .wd (channel_flags_c26_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c26_field1_qs) - ); - - - // R[length_c26]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c26_we), - .wd (length_c26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c26_qs) - ); - - - // R[message_header_c26]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c26_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c26_message_id_we), - .wd (message_header_c26_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c26_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c26_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c26_message_type_we), - .wd (message_header_c26_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c26_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c26_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c26_protocol_id_we), - .wd (message_header_c26_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c26_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c26_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c26_token_we), - .wd (message_header_c26_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c26_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c26_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c26_field1_we), - .wd (message_header_c26_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c26_field1_qs) - ); - - - // R[message_payload_1_c26]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c26 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c26_we), - .wd (message_payload_1_c26_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c26_qs) - ); - - - // R[doorbell_c26]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c26_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c26_intr_we), - .wd (doorbell_c26_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c26.intr.q ), - - // to register interface (read) - .qs (doorbell_c26_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c26_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c26_preserve_mask_we), - .wd (doorbell_c26_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c26.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c26_preserve_mask_qs) - ); - - - // R[completion_interrupt_c26]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c26_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c26_intr_we), - .wd (completion_interrupt_c26_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c26.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c26_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c26_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c26_preserve_mask_we), - .wd (completion_interrupt_c26_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c26.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c26_preserve_mask_qs) - ); - - - // R[reserved_1_c27]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c27_we), - .wd (reserved_1_c27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c27_qs) - ); - - - // R[channel_status_c27]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c27_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c27_channel_free_we), - .wd (channel_status_c27_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c27_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c27_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c27_channel_error_we), - .wd (channel_status_c27_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c27_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c27_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c27_field1_we), - .wd (channel_status_c27_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c27_field1_qs) - ); - - - // R[reserved_2_c27]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c27_we), - .wd (reserved_2_c27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c27_qs) - ); - - - // R[reserved_3_c27]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c27]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c27_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c27_intr_enable_we), - .wd (channel_flags_c27_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c27_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c27_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c27_field1_we), - .wd (channel_flags_c27_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c27_field1_qs) - ); - - - // R[length_c27]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c27_we), - .wd (length_c27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c27_qs) - ); - - - // R[message_header_c27]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c27_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c27_message_id_we), - .wd (message_header_c27_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c27_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c27_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c27_message_type_we), - .wd (message_header_c27_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c27_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c27_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c27_protocol_id_we), - .wd (message_header_c27_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c27_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c27_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c27_token_we), - .wd (message_header_c27_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c27_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c27_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c27_field1_we), - .wd (message_header_c27_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c27_field1_qs) - ); - - - // R[message_payload_1_c27]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c27 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c27_we), - .wd (message_payload_1_c27_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c27_qs) - ); - - - // R[doorbell_c27]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c27_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c27_intr_we), - .wd (doorbell_c27_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c27.intr.q ), - - // to register interface (read) - .qs (doorbell_c27_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c27_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c27_preserve_mask_we), - .wd (doorbell_c27_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c27.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c27_preserve_mask_qs) - ); - - - // R[completion_interrupt_c27]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c27_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c27_intr_we), - .wd (completion_interrupt_c27_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c27.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c27_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c27_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c27_preserve_mask_we), - .wd (completion_interrupt_c27_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c27.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c27_preserve_mask_qs) - ); - - - // R[reserved_1_c28]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c28_we), - .wd (reserved_1_c28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c28_qs) - ); - - - // R[channel_status_c28]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c28_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c28_channel_free_we), - .wd (channel_status_c28_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c28_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c28_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c28_channel_error_we), - .wd (channel_status_c28_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c28_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c28_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c28_field1_we), - .wd (channel_status_c28_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c28_field1_qs) - ); - - - // R[reserved_2_c28]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c28_we), - .wd (reserved_2_c28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c28_qs) - ); - - - // R[reserved_3_c28]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c28]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c28_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c28_intr_enable_we), - .wd (channel_flags_c28_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c28_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c28_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c28_field1_we), - .wd (channel_flags_c28_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c28_field1_qs) - ); - - - // R[length_c28]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c28_we), - .wd (length_c28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c28_qs) - ); - - - // R[message_header_c28]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c28_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c28_message_id_we), - .wd (message_header_c28_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c28_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c28_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c28_message_type_we), - .wd (message_header_c28_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c28_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c28_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c28_protocol_id_we), - .wd (message_header_c28_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c28_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c28_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c28_token_we), - .wd (message_header_c28_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c28_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c28_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c28_field1_we), - .wd (message_header_c28_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c28_field1_qs) - ); - - - // R[message_payload_1_c28]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c28 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c28_we), - .wd (message_payload_1_c28_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c28_qs) - ); - - - // R[doorbell_c28]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c28_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c28_intr_we), - .wd (doorbell_c28_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c28.intr.q ), - - // to register interface (read) - .qs (doorbell_c28_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c28_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c28_preserve_mask_we), - .wd (doorbell_c28_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c28.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c28_preserve_mask_qs) - ); - - - // R[completion_interrupt_c28]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c28_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c28_intr_we), - .wd (completion_interrupt_c28_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c28.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c28_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c28_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c28_preserve_mask_we), - .wd (completion_interrupt_c28_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c28.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c28_preserve_mask_qs) - ); - - - // R[reserved_1_c29]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c29_we), - .wd (reserved_1_c29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c29_qs) - ); - - - // R[channel_status_c29]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c29_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c29_channel_free_we), - .wd (channel_status_c29_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c29_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c29_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c29_channel_error_we), - .wd (channel_status_c29_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c29_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c29_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c29_field1_we), - .wd (channel_status_c29_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c29_field1_qs) - ); - - - // R[reserved_2_c29]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c29_we), - .wd (reserved_2_c29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c29_qs) - ); - - - // R[reserved_3_c29]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c29]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c29_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c29_intr_enable_we), - .wd (channel_flags_c29_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c29_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c29_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c29_field1_we), - .wd (channel_flags_c29_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c29_field1_qs) - ); - - - // R[length_c29]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c29_we), - .wd (length_c29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c29_qs) - ); - - - // R[message_header_c29]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c29_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c29_message_id_we), - .wd (message_header_c29_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c29_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c29_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c29_message_type_we), - .wd (message_header_c29_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c29_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c29_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c29_protocol_id_we), - .wd (message_header_c29_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c29_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c29_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c29_token_we), - .wd (message_header_c29_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c29_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c29_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c29_field1_we), - .wd (message_header_c29_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c29_field1_qs) - ); - - - // R[message_payload_1_c29]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c29 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c29_we), - .wd (message_payload_1_c29_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c29_qs) - ); - - - // R[doorbell_c29]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c29_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c29_intr_we), - .wd (doorbell_c29_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c29.intr.q ), - - // to register interface (read) - .qs (doorbell_c29_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c29_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c29_preserve_mask_we), - .wd (doorbell_c29_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c29.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c29_preserve_mask_qs) - ); - - - // R[completion_interrupt_c29]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c29_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c29_intr_we), - .wd (completion_interrupt_c29_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c29.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c29_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c29_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c29_preserve_mask_we), - .wd (completion_interrupt_c29_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c29.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c29_preserve_mask_qs) - ); - - - // R[reserved_1_c30]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c30_we), - .wd (reserved_1_c30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c30_qs) - ); - - - // R[channel_status_c30]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c30_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c30_channel_free_we), - .wd (channel_status_c30_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c30_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c30_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c30_channel_error_we), - .wd (channel_status_c30_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c30_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c30_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c30_field1_we), - .wd (channel_status_c30_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c30_field1_qs) - ); - - - // R[reserved_2_c30]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c30_we), - .wd (reserved_2_c30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c30_qs) - ); - - - // R[reserved_3_c30]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c30]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c30_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c30_intr_enable_we), - .wd (channel_flags_c30_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c30_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c30_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c30_field1_we), - .wd (channel_flags_c30_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c30_field1_qs) - ); - - - // R[length_c30]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c30_we), - .wd (length_c30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c30_qs) - ); - - - // R[message_header_c30]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c30_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c30_message_id_we), - .wd (message_header_c30_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c30_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c30_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c30_message_type_we), - .wd (message_header_c30_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c30_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c30_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c30_protocol_id_we), - .wd (message_header_c30_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c30_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c30_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c30_token_we), - .wd (message_header_c30_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c30_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c30_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c30_field1_we), - .wd (message_header_c30_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c30_field1_qs) - ); - - - // R[message_payload_1_c30]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c30 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c30_we), - .wd (message_payload_1_c30_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c30_qs) - ); - - - // R[doorbell_c30]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c30_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c30_intr_we), - .wd (doorbell_c30_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c30.intr.q ), - - // to register interface (read) - .qs (doorbell_c30_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c30_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c30_preserve_mask_we), - .wd (doorbell_c30_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c30.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c30_preserve_mask_qs) - ); - - - // R[completion_interrupt_c30]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c30_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c30_intr_we), - .wd (completion_interrupt_c30_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c30.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c30_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c30_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c30_preserve_mask_we), - .wd (completion_interrupt_c30_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c30.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c30_preserve_mask_qs) - ); - - - // R[reserved_1_c31]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c31_we), - .wd (reserved_1_c31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c31_qs) - ); - - - // R[channel_status_c31]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c31_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c31_channel_free_we), - .wd (channel_status_c31_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c31_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c31_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c31_channel_error_we), - .wd (channel_status_c31_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c31_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c31_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c31_field1_we), - .wd (channel_status_c31_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c31_field1_qs) - ); - - - // R[reserved_2_c31]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c31_we), - .wd (reserved_2_c31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c31_qs) - ); - - - // R[reserved_3_c31]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c31]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c31_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c31_intr_enable_we), - .wd (channel_flags_c31_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c31_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c31_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c31_field1_we), - .wd (channel_flags_c31_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c31_field1_qs) - ); - - - // R[length_c31]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c31_we), - .wd (length_c31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c31_qs) - ); - - - // R[message_header_c31]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c31_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c31_message_id_we), - .wd (message_header_c31_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c31_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c31_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c31_message_type_we), - .wd (message_header_c31_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c31_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c31_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c31_protocol_id_we), - .wd (message_header_c31_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c31_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c31_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c31_token_we), - .wd (message_header_c31_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c31_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c31_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c31_field1_we), - .wd (message_header_c31_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c31_field1_qs) - ); - - - // R[message_payload_1_c31]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c31 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c31_we), - .wd (message_payload_1_c31_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c31_qs) - ); - - - // R[doorbell_c31]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c31_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c31_intr_we), - .wd (doorbell_c31_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c31.intr.q ), - - // to register interface (read) - .qs (doorbell_c31_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c31_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c31_preserve_mask_we), - .wd (doorbell_c31_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c31.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c31_preserve_mask_qs) - ); - - - // R[completion_interrupt_c31]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c31_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c31_intr_we), - .wd (completion_interrupt_c31_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c31.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c31_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c31_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c31_preserve_mask_we), - .wd (completion_interrupt_c31_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c31.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c31_preserve_mask_qs) - ); - - - // R[reserved_1_c32]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c32 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c32_we), - .wd (reserved_1_c32_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c32_qs) - ); - - - // R[channel_status_c32]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c32_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c32_channel_free_we), - .wd (channel_status_c32_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c32_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c32_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c32_channel_error_we), - .wd (channel_status_c32_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c32_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c32_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c32_field1_we), - .wd (channel_status_c32_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c32_field1_qs) - ); - - - // R[reserved_2_c32]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c32 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c32_we), - .wd (reserved_2_c32_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c32_qs) - ); - - - // R[reserved_3_c32]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c32 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c32]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c32_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c32_intr_enable_we), - .wd (channel_flags_c32_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c32_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c32_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c32_field1_we), - .wd (channel_flags_c32_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c32_field1_qs) - ); - - - // R[length_c32]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c32 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c32_we), - .wd (length_c32_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c32_qs) - ); - - - // R[message_header_c32]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c32_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c32_message_id_we), - .wd (message_header_c32_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c32_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c32_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c32_message_type_we), - .wd (message_header_c32_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c32_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c32_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c32_protocol_id_we), - .wd (message_header_c32_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c32_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c32_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c32_token_we), - .wd (message_header_c32_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c32_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c32_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c32_field1_we), - .wd (message_header_c32_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c32_field1_qs) - ); - - - // R[message_payload_1_c32]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c32 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c32_we), - .wd (message_payload_1_c32_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c32_qs) - ); - - - // R[doorbell_c32]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c32_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c32_intr_we), - .wd (doorbell_c32_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c32.intr.q ), - - // to register interface (read) - .qs (doorbell_c32_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c32_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c32_preserve_mask_we), - .wd (doorbell_c32_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c32.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c32_preserve_mask_qs) - ); - - - // R[completion_interrupt_c32]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c32_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c32_intr_we), - .wd (completion_interrupt_c32_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c32.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c32_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c32_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c32_preserve_mask_we), - .wd (completion_interrupt_c32_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c32.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c32_preserve_mask_qs) - ); - - - // R[reserved_1_c33]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c33 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c33_we), - .wd (reserved_1_c33_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c33_qs) - ); - - - // R[channel_status_c33]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c33_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c33_channel_free_we), - .wd (channel_status_c33_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c33_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c33_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c33_channel_error_we), - .wd (channel_status_c33_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c33_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c33_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c33_field1_we), - .wd (channel_status_c33_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c33_field1_qs) - ); - - - // R[reserved_2_c33]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c33 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c33_we), - .wd (reserved_2_c33_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c33_qs) - ); - - - // R[reserved_3_c33]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c33 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c33]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c33_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c33_intr_enable_we), - .wd (channel_flags_c33_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c33_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c33_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c33_field1_we), - .wd (channel_flags_c33_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c33_field1_qs) - ); - - - // R[length_c33]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c33 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c33_we), - .wd (length_c33_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c33_qs) - ); - - - // R[message_header_c33]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c33_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c33_message_id_we), - .wd (message_header_c33_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c33_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c33_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c33_message_type_we), - .wd (message_header_c33_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c33_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c33_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c33_protocol_id_we), - .wd (message_header_c33_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c33_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c33_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c33_token_we), - .wd (message_header_c33_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c33_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c33_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c33_field1_we), - .wd (message_header_c33_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c33_field1_qs) - ); - - - // R[message_payload_1_c33]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c33 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c33_we), - .wd (message_payload_1_c33_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c33_qs) - ); - - - // R[doorbell_c33]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c33_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c33_intr_we), - .wd (doorbell_c33_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c33.intr.q ), - - // to register interface (read) - .qs (doorbell_c33_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c33_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c33_preserve_mask_we), - .wd (doorbell_c33_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c33.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c33_preserve_mask_qs) - ); - - - // R[completion_interrupt_c33]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c33_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c33_intr_we), - .wd (completion_interrupt_c33_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c33.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c33_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c33_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c33_preserve_mask_we), - .wd (completion_interrupt_c33_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c33.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c33_preserve_mask_qs) - ); - - - // R[reserved_1_c34]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c34 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c34_we), - .wd (reserved_1_c34_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c34_qs) - ); - - - // R[channel_status_c34]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c34_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c34_channel_free_we), - .wd (channel_status_c34_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c34_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c34_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c34_channel_error_we), - .wd (channel_status_c34_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c34_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c34_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c34_field1_we), - .wd (channel_status_c34_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c34_field1_qs) - ); - - - // R[reserved_2_c34]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c34 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c34_we), - .wd (reserved_2_c34_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c34_qs) - ); - - - // R[reserved_3_c34]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c34 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c34]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c34_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c34_intr_enable_we), - .wd (channel_flags_c34_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c34_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c34_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c34_field1_we), - .wd (channel_flags_c34_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c34_field1_qs) - ); - - - // R[length_c34]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c34 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c34_we), - .wd (length_c34_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c34_qs) - ); - - - // R[message_header_c34]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c34_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c34_message_id_we), - .wd (message_header_c34_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c34_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c34_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c34_message_type_we), - .wd (message_header_c34_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c34_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c34_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c34_protocol_id_we), - .wd (message_header_c34_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c34_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c34_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c34_token_we), - .wd (message_header_c34_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c34_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c34_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c34_field1_we), - .wd (message_header_c34_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c34_field1_qs) - ); - - - // R[message_payload_1_c34]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c34 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c34_we), - .wd (message_payload_1_c34_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c34_qs) - ); - - - // R[doorbell_c34]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c34_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c34_intr_we), - .wd (doorbell_c34_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c34.intr.q ), - - // to register interface (read) - .qs (doorbell_c34_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c34_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c34_preserve_mask_we), - .wd (doorbell_c34_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c34.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c34_preserve_mask_qs) - ); - - - // R[completion_interrupt_c34]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c34_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c34_intr_we), - .wd (completion_interrupt_c34_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c34.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c34_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c34_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c34_preserve_mask_we), - .wd (completion_interrupt_c34_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c34.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c34_preserve_mask_qs) - ); - - - // R[reserved_1_c35]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c35 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c35_we), - .wd (reserved_1_c35_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c35_qs) - ); - - - // R[channel_status_c35]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c35_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c35_channel_free_we), - .wd (channel_status_c35_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c35_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c35_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c35_channel_error_we), - .wd (channel_status_c35_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c35_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c35_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c35_field1_we), - .wd (channel_status_c35_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c35_field1_qs) - ); - - - // R[reserved_2_c35]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c35 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c35_we), - .wd (reserved_2_c35_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c35_qs) - ); - - - // R[reserved_3_c35]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c35 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c35]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c35_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c35_intr_enable_we), - .wd (channel_flags_c35_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c35_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c35_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c35_field1_we), - .wd (channel_flags_c35_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c35_field1_qs) - ); - - - // R[length_c35]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c35 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c35_we), - .wd (length_c35_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c35_qs) - ); - - - // R[message_header_c35]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c35_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c35_message_id_we), - .wd (message_header_c35_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c35_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c35_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c35_message_type_we), - .wd (message_header_c35_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c35_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c35_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c35_protocol_id_we), - .wd (message_header_c35_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c35_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c35_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c35_token_we), - .wd (message_header_c35_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c35_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c35_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c35_field1_we), - .wd (message_header_c35_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c35_field1_qs) - ); - - - // R[message_payload_1_c35]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c35 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c35_we), - .wd (message_payload_1_c35_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c35_qs) - ); - - - // R[doorbell_c35]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c35_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c35_intr_we), - .wd (doorbell_c35_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c35.intr.q ), - - // to register interface (read) - .qs (doorbell_c35_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c35_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c35_preserve_mask_we), - .wd (doorbell_c35_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c35.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c35_preserve_mask_qs) - ); - - - // R[completion_interrupt_c35]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c35_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c35_intr_we), - .wd (completion_interrupt_c35_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c35.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c35_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c35_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c35_preserve_mask_we), - .wd (completion_interrupt_c35_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c35.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c35_preserve_mask_qs) - ); - - - // R[reserved_1_c36]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c36 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c36_we), - .wd (reserved_1_c36_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c36_qs) - ); - - - // R[channel_status_c36]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c36_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c36_channel_free_we), - .wd (channel_status_c36_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c36_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c36_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c36_channel_error_we), - .wd (channel_status_c36_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c36_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c36_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c36_field1_we), - .wd (channel_status_c36_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c36_field1_qs) - ); - - - // R[reserved_2_c36]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c36 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c36_we), - .wd (reserved_2_c36_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c36_qs) - ); - - - // R[reserved_3_c36]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c36 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c36]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c36_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c36_intr_enable_we), - .wd (channel_flags_c36_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c36_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c36_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c36_field1_we), - .wd (channel_flags_c36_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c36_field1_qs) - ); - - - // R[length_c36]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c36 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c36_we), - .wd (length_c36_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c36_qs) - ); - - - // R[message_header_c36]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c36_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c36_message_id_we), - .wd (message_header_c36_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c36_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c36_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c36_message_type_we), - .wd (message_header_c36_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c36_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c36_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c36_protocol_id_we), - .wd (message_header_c36_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c36_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c36_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c36_token_we), - .wd (message_header_c36_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c36_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c36_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c36_field1_we), - .wd (message_header_c36_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c36_field1_qs) - ); - - - // R[message_payload_1_c36]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c36 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c36_we), - .wd (message_payload_1_c36_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c36_qs) - ); - - - // R[doorbell_c36]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c36_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c36_intr_we), - .wd (doorbell_c36_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c36.intr.q ), - - // to register interface (read) - .qs (doorbell_c36_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c36_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c36_preserve_mask_we), - .wd (doorbell_c36_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c36.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c36_preserve_mask_qs) - ); - - - // R[completion_interrupt_c36]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c36_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c36_intr_we), - .wd (completion_interrupt_c36_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c36.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c36_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c36_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c36_preserve_mask_we), - .wd (completion_interrupt_c36_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c36.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c36_preserve_mask_qs) - ); - - - // R[reserved_1_c37]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c37 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c37_we), - .wd (reserved_1_c37_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c37_qs) - ); - - - // R[channel_status_c37]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c37_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c37_channel_free_we), - .wd (channel_status_c37_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c37_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c37_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c37_channel_error_we), - .wd (channel_status_c37_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c37_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c37_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c37_field1_we), - .wd (channel_status_c37_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c37_field1_qs) - ); - - - // R[reserved_2_c37]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c37 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c37_we), - .wd (reserved_2_c37_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c37_qs) - ); - - - // R[reserved_3_c37]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c37 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c37]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c37_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c37_intr_enable_we), - .wd (channel_flags_c37_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c37_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c37_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c37_field1_we), - .wd (channel_flags_c37_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c37_field1_qs) - ); - - - // R[length_c37]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c37 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c37_we), - .wd (length_c37_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c37_qs) - ); - - - // R[message_header_c37]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c37_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c37_message_id_we), - .wd (message_header_c37_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c37_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c37_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c37_message_type_we), - .wd (message_header_c37_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c37_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c37_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c37_protocol_id_we), - .wd (message_header_c37_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c37_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c37_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c37_token_we), - .wd (message_header_c37_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c37_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c37_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c37_field1_we), - .wd (message_header_c37_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c37_field1_qs) - ); - - - // R[message_payload_1_c37]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c37 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c37_we), - .wd (message_payload_1_c37_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c37_qs) - ); - - - // R[doorbell_c37]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c37_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c37_intr_we), - .wd (doorbell_c37_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c37.intr.q ), - - // to register interface (read) - .qs (doorbell_c37_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c37_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c37_preserve_mask_we), - .wd (doorbell_c37_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c37.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c37_preserve_mask_qs) - ); - - - // R[completion_interrupt_c37]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c37_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c37_intr_we), - .wd (completion_interrupt_c37_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c37.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c37_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c37_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c37_preserve_mask_we), - .wd (completion_interrupt_c37_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c37.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c37_preserve_mask_qs) - ); - - - // R[reserved_1_c38]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c38 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c38_we), - .wd (reserved_1_c38_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c38_qs) - ); - - - // R[channel_status_c38]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c38_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c38_channel_free_we), - .wd (channel_status_c38_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c38_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c38_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c38_channel_error_we), - .wd (channel_status_c38_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c38_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c38_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c38_field1_we), - .wd (channel_status_c38_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c38_field1_qs) - ); - - - // R[reserved_2_c38]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c38 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c38_we), - .wd (reserved_2_c38_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c38_qs) - ); - - - // R[reserved_3_c38]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c38 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c38]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c38_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c38_intr_enable_we), - .wd (channel_flags_c38_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c38_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c38_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c38_field1_we), - .wd (channel_flags_c38_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c38_field1_qs) - ); - - - // R[length_c38]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c38 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c38_we), - .wd (length_c38_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c38_qs) - ); - - - // R[message_header_c38]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c38_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c38_message_id_we), - .wd (message_header_c38_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c38_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c38_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c38_message_type_we), - .wd (message_header_c38_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c38_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c38_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c38_protocol_id_we), - .wd (message_header_c38_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c38_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c38_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c38_token_we), - .wd (message_header_c38_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c38_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c38_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c38_field1_we), - .wd (message_header_c38_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c38_field1_qs) - ); - - - // R[message_payload_1_c38]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c38 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c38_we), - .wd (message_payload_1_c38_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c38_qs) - ); - - - // R[doorbell_c38]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c38_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c38_intr_we), - .wd (doorbell_c38_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c38.intr.q ), - - // to register interface (read) - .qs (doorbell_c38_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c38_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c38_preserve_mask_we), - .wd (doorbell_c38_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c38.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c38_preserve_mask_qs) - ); - - - // R[completion_interrupt_c38]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c38_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c38_intr_we), - .wd (completion_interrupt_c38_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c38.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c38_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c38_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c38_preserve_mask_we), - .wd (completion_interrupt_c38_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c38.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c38_preserve_mask_qs) - ); - - - // R[reserved_1_c39]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c39 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c39_we), - .wd (reserved_1_c39_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c39_qs) - ); - - - // R[channel_status_c39]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c39_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c39_channel_free_we), - .wd (channel_status_c39_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c39_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c39_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c39_channel_error_we), - .wd (channel_status_c39_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c39_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c39_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c39_field1_we), - .wd (channel_status_c39_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c39_field1_qs) - ); - - - // R[reserved_2_c39]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c39 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c39_we), - .wd (reserved_2_c39_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c39_qs) - ); - - - // R[reserved_3_c39]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c39 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c39]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c39_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c39_intr_enable_we), - .wd (channel_flags_c39_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c39_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c39_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c39_field1_we), - .wd (channel_flags_c39_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c39_field1_qs) - ); - - - // R[length_c39]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c39 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c39_we), - .wd (length_c39_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c39_qs) - ); - - - // R[message_header_c39]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c39_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c39_message_id_we), - .wd (message_header_c39_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c39_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c39_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c39_message_type_we), - .wd (message_header_c39_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c39_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c39_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c39_protocol_id_we), - .wd (message_header_c39_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c39_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c39_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c39_token_we), - .wd (message_header_c39_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c39_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c39_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c39_field1_we), - .wd (message_header_c39_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c39_field1_qs) - ); - - - // R[message_payload_1_c39]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c39 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c39_we), - .wd (message_payload_1_c39_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c39_qs) - ); - - - // R[doorbell_c39]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c39_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c39_intr_we), - .wd (doorbell_c39_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c39.intr.q ), - - // to register interface (read) - .qs (doorbell_c39_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c39_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c39_preserve_mask_we), - .wd (doorbell_c39_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c39.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c39_preserve_mask_qs) - ); - - - // R[completion_interrupt_c39]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c39_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c39_intr_we), - .wd (completion_interrupt_c39_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c39.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c39_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c39_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c39_preserve_mask_we), - .wd (completion_interrupt_c39_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c39.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c39_preserve_mask_qs) - ); - - - // R[reserved_1_c40]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c40 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c40_we), - .wd (reserved_1_c40_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c40_qs) - ); - - - // R[channel_status_c40]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c40_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c40_channel_free_we), - .wd (channel_status_c40_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c40_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c40_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c40_channel_error_we), - .wd (channel_status_c40_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c40_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c40_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c40_field1_we), - .wd (channel_status_c40_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c40_field1_qs) - ); - - - // R[reserved_2_c40]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c40 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c40_we), - .wd (reserved_2_c40_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c40_qs) - ); - - - // R[reserved_3_c40]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c40 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c40]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c40_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c40_intr_enable_we), - .wd (channel_flags_c40_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c40_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c40_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c40_field1_we), - .wd (channel_flags_c40_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c40_field1_qs) - ); - - - // R[length_c40]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c40 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c40_we), - .wd (length_c40_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c40_qs) - ); - - - // R[message_header_c40]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c40_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c40_message_id_we), - .wd (message_header_c40_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c40_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c40_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c40_message_type_we), - .wd (message_header_c40_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c40_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c40_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c40_protocol_id_we), - .wd (message_header_c40_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c40_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c40_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c40_token_we), - .wd (message_header_c40_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c40_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c40_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c40_field1_we), - .wd (message_header_c40_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c40_field1_qs) - ); - - - // R[message_payload_1_c40]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c40 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c40_we), - .wd (message_payload_1_c40_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c40_qs) - ); - - - // R[doorbell_c40]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c40_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c40_intr_we), - .wd (doorbell_c40_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c40.intr.q ), - - // to register interface (read) - .qs (doorbell_c40_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c40_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c40_preserve_mask_we), - .wd (doorbell_c40_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c40.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c40_preserve_mask_qs) - ); - - - // R[completion_interrupt_c40]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c40_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c40_intr_we), - .wd (completion_interrupt_c40_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c40.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c40_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c40_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c40_preserve_mask_we), - .wd (completion_interrupt_c40_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c40.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c40_preserve_mask_qs) - ); - - - // R[reserved_1_c41]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c41 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c41_we), - .wd (reserved_1_c41_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c41_qs) - ); - - - // R[channel_status_c41]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c41_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c41_channel_free_we), - .wd (channel_status_c41_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c41_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c41_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c41_channel_error_we), - .wd (channel_status_c41_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c41_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c41_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c41_field1_we), - .wd (channel_status_c41_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c41_field1_qs) - ); - - - // R[reserved_2_c41]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c41 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c41_we), - .wd (reserved_2_c41_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c41_qs) - ); - - - // R[reserved_3_c41]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c41 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c41]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c41_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c41_intr_enable_we), - .wd (channel_flags_c41_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c41_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c41_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c41_field1_we), - .wd (channel_flags_c41_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c41_field1_qs) - ); - - - // R[length_c41]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c41 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c41_we), - .wd (length_c41_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c41_qs) - ); - - - // R[message_header_c41]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c41_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c41_message_id_we), - .wd (message_header_c41_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c41_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c41_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c41_message_type_we), - .wd (message_header_c41_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c41_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c41_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c41_protocol_id_we), - .wd (message_header_c41_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c41_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c41_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c41_token_we), - .wd (message_header_c41_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c41_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c41_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c41_field1_we), - .wd (message_header_c41_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c41_field1_qs) - ); - - - // R[message_payload_1_c41]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c41 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c41_we), - .wd (message_payload_1_c41_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c41_qs) - ); - - - // R[doorbell_c41]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c41_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c41_intr_we), - .wd (doorbell_c41_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c41.intr.q ), - - // to register interface (read) - .qs (doorbell_c41_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c41_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c41_preserve_mask_we), - .wd (doorbell_c41_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c41.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c41_preserve_mask_qs) - ); - - - // R[completion_interrupt_c41]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c41_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c41_intr_we), - .wd (completion_interrupt_c41_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c41.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c41_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c41_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c41_preserve_mask_we), - .wd (completion_interrupt_c41_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c41.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c41_preserve_mask_qs) - ); - - - // R[reserved_1_c42]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c42 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c42_we), - .wd (reserved_1_c42_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c42_qs) - ); - - - // R[channel_status_c42]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c42_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c42_channel_free_we), - .wd (channel_status_c42_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c42_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c42_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c42_channel_error_we), - .wd (channel_status_c42_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c42_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c42_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c42_field1_we), - .wd (channel_status_c42_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c42_field1_qs) - ); - - - // R[reserved_2_c42]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c42 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c42_we), - .wd (reserved_2_c42_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c42_qs) - ); - - - // R[reserved_3_c42]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c42 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c42]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c42_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c42_intr_enable_we), - .wd (channel_flags_c42_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c42_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c42_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c42_field1_we), - .wd (channel_flags_c42_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c42_field1_qs) - ); - - - // R[length_c42]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c42 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c42_we), - .wd (length_c42_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c42_qs) - ); - - - // R[message_header_c42]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c42_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c42_message_id_we), - .wd (message_header_c42_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c42_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c42_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c42_message_type_we), - .wd (message_header_c42_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c42_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c42_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c42_protocol_id_we), - .wd (message_header_c42_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c42_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c42_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c42_token_we), - .wd (message_header_c42_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c42_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c42_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c42_field1_we), - .wd (message_header_c42_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c42_field1_qs) - ); - - - // R[message_payload_1_c42]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c42 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c42_we), - .wd (message_payload_1_c42_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c42_qs) - ); - - - // R[doorbell_c42]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c42_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c42_intr_we), - .wd (doorbell_c42_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c42.intr.q ), - - // to register interface (read) - .qs (doorbell_c42_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c42_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c42_preserve_mask_we), - .wd (doorbell_c42_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c42.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c42_preserve_mask_qs) - ); - - - // R[completion_interrupt_c42]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c42_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c42_intr_we), - .wd (completion_interrupt_c42_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c42.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c42_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c42_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c42_preserve_mask_we), - .wd (completion_interrupt_c42_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c42.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c42_preserve_mask_qs) - ); - - - // R[reserved_1_c43]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c43 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c43_we), - .wd (reserved_1_c43_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c43_qs) - ); - - - // R[channel_status_c43]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c43_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c43_channel_free_we), - .wd (channel_status_c43_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c43_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c43_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c43_channel_error_we), - .wd (channel_status_c43_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c43_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c43_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c43_field1_we), - .wd (channel_status_c43_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c43_field1_qs) - ); - - - // R[reserved_2_c43]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c43 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c43_we), - .wd (reserved_2_c43_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c43_qs) - ); - - - // R[reserved_3_c43]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c43 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c43]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c43_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c43_intr_enable_we), - .wd (channel_flags_c43_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c43_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c43_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c43_field1_we), - .wd (channel_flags_c43_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c43_field1_qs) - ); - - - // R[length_c43]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c43 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c43_we), - .wd (length_c43_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c43_qs) - ); - - - // R[message_header_c43]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c43_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c43_message_id_we), - .wd (message_header_c43_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c43_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c43_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c43_message_type_we), - .wd (message_header_c43_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c43_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c43_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c43_protocol_id_we), - .wd (message_header_c43_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c43_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c43_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c43_token_we), - .wd (message_header_c43_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c43_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c43_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c43_field1_we), - .wd (message_header_c43_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c43_field1_qs) - ); - - - // R[message_payload_1_c43]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c43 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c43_we), - .wd (message_payload_1_c43_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c43_qs) - ); - - - // R[doorbell_c43]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c43_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c43_intr_we), - .wd (doorbell_c43_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c43.intr.q ), - - // to register interface (read) - .qs (doorbell_c43_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c43_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c43_preserve_mask_we), - .wd (doorbell_c43_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c43.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c43_preserve_mask_qs) - ); - - - // R[completion_interrupt_c43]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c43_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c43_intr_we), - .wd (completion_interrupt_c43_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c43.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c43_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c43_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c43_preserve_mask_we), - .wd (completion_interrupt_c43_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c43.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c43_preserve_mask_qs) - ); - - - // R[reserved_1_c44]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c44 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c44_we), - .wd (reserved_1_c44_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c44_qs) - ); - - - // R[channel_status_c44]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c44_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c44_channel_free_we), - .wd (channel_status_c44_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c44_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c44_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c44_channel_error_we), - .wd (channel_status_c44_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c44_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c44_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c44_field1_we), - .wd (channel_status_c44_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c44_field1_qs) - ); - - - // R[reserved_2_c44]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c44 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c44_we), - .wd (reserved_2_c44_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c44_qs) - ); - - - // R[reserved_3_c44]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c44 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c44]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c44_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c44_intr_enable_we), - .wd (channel_flags_c44_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c44_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c44_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c44_field1_we), - .wd (channel_flags_c44_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c44_field1_qs) - ); - - - // R[length_c44]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c44 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c44_we), - .wd (length_c44_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c44_qs) - ); - - - // R[message_header_c44]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c44_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c44_message_id_we), - .wd (message_header_c44_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c44_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c44_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c44_message_type_we), - .wd (message_header_c44_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c44_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c44_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c44_protocol_id_we), - .wd (message_header_c44_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c44_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c44_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c44_token_we), - .wd (message_header_c44_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c44_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c44_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c44_field1_we), - .wd (message_header_c44_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c44_field1_qs) - ); - - - // R[message_payload_1_c44]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c44 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c44_we), - .wd (message_payload_1_c44_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c44_qs) - ); - - - // R[doorbell_c44]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c44_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c44_intr_we), - .wd (doorbell_c44_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c44.intr.q ), - - // to register interface (read) - .qs (doorbell_c44_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c44_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c44_preserve_mask_we), - .wd (doorbell_c44_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c44.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c44_preserve_mask_qs) - ); - - - // R[completion_interrupt_c44]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c44_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c44_intr_we), - .wd (completion_interrupt_c44_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c44.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c44_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c44_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c44_preserve_mask_we), - .wd (completion_interrupt_c44_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c44.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c44_preserve_mask_qs) - ); - - - // R[reserved_1_c45]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c45 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c45_we), - .wd (reserved_1_c45_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c45_qs) - ); - - - // R[channel_status_c45]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c45_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c45_channel_free_we), - .wd (channel_status_c45_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c45_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c45_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c45_channel_error_we), - .wd (channel_status_c45_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c45_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c45_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c45_field1_we), - .wd (channel_status_c45_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c45_field1_qs) - ); - - - // R[reserved_2_c45]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c45 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c45_we), - .wd (reserved_2_c45_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c45_qs) - ); - - - // R[reserved_3_c45]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c45 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c45]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c45_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c45_intr_enable_we), - .wd (channel_flags_c45_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c45_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c45_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c45_field1_we), - .wd (channel_flags_c45_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c45_field1_qs) - ); - - - // R[length_c45]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c45 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c45_we), - .wd (length_c45_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c45_qs) - ); - - - // R[message_header_c45]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c45_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c45_message_id_we), - .wd (message_header_c45_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c45_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c45_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c45_message_type_we), - .wd (message_header_c45_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c45_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c45_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c45_protocol_id_we), - .wd (message_header_c45_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c45_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c45_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c45_token_we), - .wd (message_header_c45_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c45_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c45_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c45_field1_we), - .wd (message_header_c45_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c45_field1_qs) - ); - - - // R[message_payload_1_c45]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c45 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c45_we), - .wd (message_payload_1_c45_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c45_qs) - ); - - - // R[doorbell_c45]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c45_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c45_intr_we), - .wd (doorbell_c45_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c45.intr.q ), - - // to register interface (read) - .qs (doorbell_c45_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c45_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c45_preserve_mask_we), - .wd (doorbell_c45_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c45.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c45_preserve_mask_qs) - ); - - - // R[completion_interrupt_c45]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c45_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c45_intr_we), - .wd (completion_interrupt_c45_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c45.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c45_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c45_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c45_preserve_mask_we), - .wd (completion_interrupt_c45_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c45.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c45_preserve_mask_qs) - ); - - - // R[reserved_1_c46]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c46 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c46_we), - .wd (reserved_1_c46_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c46_qs) - ); - - - // R[channel_status_c46]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c46_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c46_channel_free_we), - .wd (channel_status_c46_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c46_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c46_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c46_channel_error_we), - .wd (channel_status_c46_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c46_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c46_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c46_field1_we), - .wd (channel_status_c46_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c46_field1_qs) - ); - - - // R[reserved_2_c46]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c46 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c46_we), - .wd (reserved_2_c46_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c46_qs) - ); - - - // R[reserved_3_c46]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c46 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c46]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c46_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c46_intr_enable_we), - .wd (channel_flags_c46_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c46_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c46_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c46_field1_we), - .wd (channel_flags_c46_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c46_field1_qs) - ); - - - // R[length_c46]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c46 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c46_we), - .wd (length_c46_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c46_qs) - ); - - - // R[message_header_c46]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c46_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c46_message_id_we), - .wd (message_header_c46_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c46_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c46_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c46_message_type_we), - .wd (message_header_c46_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c46_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c46_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c46_protocol_id_we), - .wd (message_header_c46_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c46_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c46_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c46_token_we), - .wd (message_header_c46_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c46_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c46_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c46_field1_we), - .wd (message_header_c46_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c46_field1_qs) - ); - - - // R[message_payload_1_c46]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c46 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c46_we), - .wd (message_payload_1_c46_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c46_qs) - ); - - - // R[doorbell_c46]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c46_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c46_intr_we), - .wd (doorbell_c46_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c46.intr.q ), - - // to register interface (read) - .qs (doorbell_c46_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c46_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c46_preserve_mask_we), - .wd (doorbell_c46_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c46.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c46_preserve_mask_qs) - ); - - - // R[completion_interrupt_c46]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c46_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c46_intr_we), - .wd (completion_interrupt_c46_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c46.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c46_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c46_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c46_preserve_mask_we), - .wd (completion_interrupt_c46_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c46.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c46_preserve_mask_qs) - ); - - - // R[reserved_1_c47]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c47 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c47_we), - .wd (reserved_1_c47_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c47_qs) - ); - - - // R[channel_status_c47]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c47_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c47_channel_free_we), - .wd (channel_status_c47_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c47_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c47_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c47_channel_error_we), - .wd (channel_status_c47_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c47_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c47_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c47_field1_we), - .wd (channel_status_c47_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c47_field1_qs) - ); - - - // R[reserved_2_c47]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c47 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c47_we), - .wd (reserved_2_c47_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c47_qs) - ); - - - // R[reserved_3_c47]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c47 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c47]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c47_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c47_intr_enable_we), - .wd (channel_flags_c47_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c47_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c47_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c47_field1_we), - .wd (channel_flags_c47_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c47_field1_qs) - ); - - - // R[length_c47]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c47 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c47_we), - .wd (length_c47_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c47_qs) - ); - - - // R[message_header_c47]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c47_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c47_message_id_we), - .wd (message_header_c47_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c47_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c47_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c47_message_type_we), - .wd (message_header_c47_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c47_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c47_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c47_protocol_id_we), - .wd (message_header_c47_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c47_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c47_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c47_token_we), - .wd (message_header_c47_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c47_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c47_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c47_field1_we), - .wd (message_header_c47_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c47_field1_qs) - ); - - - // R[message_payload_1_c47]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c47 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c47_we), - .wd (message_payload_1_c47_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c47_qs) - ); - - - // R[doorbell_c47]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c47_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c47_intr_we), - .wd (doorbell_c47_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c47.intr.q ), - - // to register interface (read) - .qs (doorbell_c47_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c47_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c47_preserve_mask_we), - .wd (doorbell_c47_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c47.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c47_preserve_mask_qs) - ); - - - // R[completion_interrupt_c47]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c47_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c47_intr_we), - .wd (completion_interrupt_c47_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c47.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c47_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c47_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c47_preserve_mask_we), - .wd (completion_interrupt_c47_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c47.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c47_preserve_mask_qs) - ); - - - // R[reserved_1_c48]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c48 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c48_we), - .wd (reserved_1_c48_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c48_qs) - ); - - - // R[channel_status_c48]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c48_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c48_channel_free_we), - .wd (channel_status_c48_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c48_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c48_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c48_channel_error_we), - .wd (channel_status_c48_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c48_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c48_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c48_field1_we), - .wd (channel_status_c48_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c48_field1_qs) - ); - - - // R[reserved_2_c48]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c48 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c48_we), - .wd (reserved_2_c48_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c48_qs) - ); - - - // R[reserved_3_c48]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c48 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c48]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c48_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c48_intr_enable_we), - .wd (channel_flags_c48_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c48_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c48_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c48_field1_we), - .wd (channel_flags_c48_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c48_field1_qs) - ); - - - // R[length_c48]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c48 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c48_we), - .wd (length_c48_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c48_qs) - ); - - - // R[message_header_c48]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c48_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c48_message_id_we), - .wd (message_header_c48_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c48_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c48_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c48_message_type_we), - .wd (message_header_c48_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c48_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c48_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c48_protocol_id_we), - .wd (message_header_c48_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c48_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c48_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c48_token_we), - .wd (message_header_c48_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c48_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c48_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c48_field1_we), - .wd (message_header_c48_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c48_field1_qs) - ); - - - // R[message_payload_1_c48]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c48 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c48_we), - .wd (message_payload_1_c48_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c48_qs) - ); - - - // R[doorbell_c48]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c48_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c48_intr_we), - .wd (doorbell_c48_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c48.intr.q ), - - // to register interface (read) - .qs (doorbell_c48_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c48_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c48_preserve_mask_we), - .wd (doorbell_c48_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c48.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c48_preserve_mask_qs) - ); - - - // R[completion_interrupt_c48]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c48_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c48_intr_we), - .wd (completion_interrupt_c48_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c48.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c48_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c48_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c48_preserve_mask_we), - .wd (completion_interrupt_c48_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c48.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c48_preserve_mask_qs) - ); - - - // R[reserved_1_c49]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c49 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c49_we), - .wd (reserved_1_c49_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c49_qs) - ); - - - // R[channel_status_c49]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c49_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c49_channel_free_we), - .wd (channel_status_c49_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c49_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c49_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c49_channel_error_we), - .wd (channel_status_c49_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c49_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c49_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c49_field1_we), - .wd (channel_status_c49_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c49_field1_qs) - ); - - - // R[reserved_2_c49]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c49 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c49_we), - .wd (reserved_2_c49_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c49_qs) - ); - - - // R[reserved_3_c49]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c49 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c49]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c49_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c49_intr_enable_we), - .wd (channel_flags_c49_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c49_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c49_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c49_field1_we), - .wd (channel_flags_c49_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c49_field1_qs) - ); - - - // R[length_c49]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c49 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c49_we), - .wd (length_c49_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c49_qs) - ); - - - // R[message_header_c49]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c49_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c49_message_id_we), - .wd (message_header_c49_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c49_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c49_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c49_message_type_we), - .wd (message_header_c49_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c49_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c49_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c49_protocol_id_we), - .wd (message_header_c49_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c49_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c49_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c49_token_we), - .wd (message_header_c49_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c49_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c49_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c49_field1_we), - .wd (message_header_c49_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c49_field1_qs) - ); - - - // R[message_payload_1_c49]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c49 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c49_we), - .wd (message_payload_1_c49_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c49_qs) - ); - - - // R[doorbell_c49]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c49_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c49_intr_we), - .wd (doorbell_c49_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c49.intr.q ), - - // to register interface (read) - .qs (doorbell_c49_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c49_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c49_preserve_mask_we), - .wd (doorbell_c49_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c49.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c49_preserve_mask_qs) - ); - - - // R[completion_interrupt_c49]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c49_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c49_intr_we), - .wd (completion_interrupt_c49_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c49.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c49_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c49_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c49_preserve_mask_we), - .wd (completion_interrupt_c49_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c49.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c49_preserve_mask_qs) - ); - - - // R[reserved_1_c50]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c50 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c50_we), - .wd (reserved_1_c50_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c50_qs) - ); - - - // R[channel_status_c50]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c50_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c50_channel_free_we), - .wd (channel_status_c50_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c50_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c50_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c50_channel_error_we), - .wd (channel_status_c50_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c50_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c50_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c50_field1_we), - .wd (channel_status_c50_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c50_field1_qs) - ); - - - // R[reserved_2_c50]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c50 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c50_we), - .wd (reserved_2_c50_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c50_qs) - ); - - - // R[reserved_3_c50]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c50 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c50]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c50_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c50_intr_enable_we), - .wd (channel_flags_c50_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c50_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c50_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c50_field1_we), - .wd (channel_flags_c50_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c50_field1_qs) - ); - - - // R[length_c50]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c50 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c50_we), - .wd (length_c50_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c50_qs) - ); - - - // R[message_header_c50]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c50_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c50_message_id_we), - .wd (message_header_c50_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c50_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c50_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c50_message_type_we), - .wd (message_header_c50_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c50_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c50_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c50_protocol_id_we), - .wd (message_header_c50_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c50_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c50_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c50_token_we), - .wd (message_header_c50_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c50_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c50_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c50_field1_we), - .wd (message_header_c50_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c50_field1_qs) - ); - - - // R[message_payload_1_c50]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c50 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c50_we), - .wd (message_payload_1_c50_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c50_qs) - ); - - - // R[doorbell_c50]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c50_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c50_intr_we), - .wd (doorbell_c50_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c50.intr.q ), - - // to register interface (read) - .qs (doorbell_c50_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c50_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c50_preserve_mask_we), - .wd (doorbell_c50_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c50.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c50_preserve_mask_qs) - ); - - - // R[completion_interrupt_c50]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c50_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c50_intr_we), - .wd (completion_interrupt_c50_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c50.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c50_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c50_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c50_preserve_mask_we), - .wd (completion_interrupt_c50_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c50.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c50_preserve_mask_qs) - ); - - - // R[reserved_1_c51]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c51 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c51_we), - .wd (reserved_1_c51_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c51_qs) - ); - - - // R[channel_status_c51]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c51_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c51_channel_free_we), - .wd (channel_status_c51_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c51_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c51_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c51_channel_error_we), - .wd (channel_status_c51_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c51_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c51_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c51_field1_we), - .wd (channel_status_c51_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c51_field1_qs) - ); - - - // R[reserved_2_c51]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c51 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c51_we), - .wd (reserved_2_c51_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c51_qs) - ); - - - // R[reserved_3_c51]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c51 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c51]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c51_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c51_intr_enable_we), - .wd (channel_flags_c51_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c51_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c51_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c51_field1_we), - .wd (channel_flags_c51_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c51_field1_qs) - ); - - - // R[length_c51]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c51 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c51_we), - .wd (length_c51_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c51_qs) - ); - - - // R[message_header_c51]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c51_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c51_message_id_we), - .wd (message_header_c51_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c51_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c51_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c51_message_type_we), - .wd (message_header_c51_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c51_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c51_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c51_protocol_id_we), - .wd (message_header_c51_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c51_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c51_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c51_token_we), - .wd (message_header_c51_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c51_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c51_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c51_field1_we), - .wd (message_header_c51_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c51_field1_qs) - ); - - - // R[message_payload_1_c51]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c51 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c51_we), - .wd (message_payload_1_c51_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c51_qs) - ); - - - // R[doorbell_c51]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c51_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c51_intr_we), - .wd (doorbell_c51_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c51.intr.q ), - - // to register interface (read) - .qs (doorbell_c51_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c51_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c51_preserve_mask_we), - .wd (doorbell_c51_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c51.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c51_preserve_mask_qs) - ); - - - // R[completion_interrupt_c51]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c51_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c51_intr_we), - .wd (completion_interrupt_c51_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c51.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c51_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c51_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c51_preserve_mask_we), - .wd (completion_interrupt_c51_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c51.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c51_preserve_mask_qs) - ); - - - // R[reserved_1_c52]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c52 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c52_we), - .wd (reserved_1_c52_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c52_qs) - ); - - - // R[channel_status_c52]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c52_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c52_channel_free_we), - .wd (channel_status_c52_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c52_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c52_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c52_channel_error_we), - .wd (channel_status_c52_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c52_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c52_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c52_field1_we), - .wd (channel_status_c52_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c52_field1_qs) - ); - - - // R[reserved_2_c52]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c52 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c52_we), - .wd (reserved_2_c52_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c52_qs) - ); - - - // R[reserved_3_c52]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c52 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c52]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c52_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c52_intr_enable_we), - .wd (channel_flags_c52_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c52_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c52_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c52_field1_we), - .wd (channel_flags_c52_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c52_field1_qs) - ); - - - // R[length_c52]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c52 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c52_we), - .wd (length_c52_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c52_qs) - ); - - - // R[message_header_c52]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c52_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c52_message_id_we), - .wd (message_header_c52_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c52_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c52_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c52_message_type_we), - .wd (message_header_c52_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c52_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c52_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c52_protocol_id_we), - .wd (message_header_c52_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c52_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c52_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c52_token_we), - .wd (message_header_c52_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c52_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c52_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c52_field1_we), - .wd (message_header_c52_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c52_field1_qs) - ); - - - // R[message_payload_1_c52]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c52 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c52_we), - .wd (message_payload_1_c52_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c52_qs) - ); - - - // R[doorbell_c52]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c52_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c52_intr_we), - .wd (doorbell_c52_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c52.intr.q ), - - // to register interface (read) - .qs (doorbell_c52_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c52_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c52_preserve_mask_we), - .wd (doorbell_c52_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c52.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c52_preserve_mask_qs) - ); - - - // R[completion_interrupt_c52]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c52_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c52_intr_we), - .wd (completion_interrupt_c52_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c52.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c52_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c52_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c52_preserve_mask_we), - .wd (completion_interrupt_c52_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c52.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c52_preserve_mask_qs) - ); - - - // R[reserved_1_c53]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c53 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c53_we), - .wd (reserved_1_c53_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c53_qs) - ); - - - // R[channel_status_c53]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c53_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c53_channel_free_we), - .wd (channel_status_c53_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c53_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c53_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c53_channel_error_we), - .wd (channel_status_c53_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c53_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c53_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c53_field1_we), - .wd (channel_status_c53_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c53_field1_qs) - ); - - - // R[reserved_2_c53]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c53 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c53_we), - .wd (reserved_2_c53_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c53_qs) - ); - - - // R[reserved_3_c53]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c53 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c53]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c53_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c53_intr_enable_we), - .wd (channel_flags_c53_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c53_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c53_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c53_field1_we), - .wd (channel_flags_c53_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c53_field1_qs) - ); - - - // R[length_c53]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c53 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c53_we), - .wd (length_c53_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c53_qs) - ); - - - // R[message_header_c53]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c53_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c53_message_id_we), - .wd (message_header_c53_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c53_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c53_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c53_message_type_we), - .wd (message_header_c53_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c53_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c53_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c53_protocol_id_we), - .wd (message_header_c53_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c53_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c53_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c53_token_we), - .wd (message_header_c53_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c53_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c53_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c53_field1_we), - .wd (message_header_c53_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c53_field1_qs) - ); - - - // R[message_payload_1_c53]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c53 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c53_we), - .wd (message_payload_1_c53_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c53_qs) - ); - - - // R[doorbell_c53]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c53_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c53_intr_we), - .wd (doorbell_c53_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c53.intr.q ), - - // to register interface (read) - .qs (doorbell_c53_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c53_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c53_preserve_mask_we), - .wd (doorbell_c53_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c53.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c53_preserve_mask_qs) - ); - - - // R[completion_interrupt_c53]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c53_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c53_intr_we), - .wd (completion_interrupt_c53_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c53.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c53_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c53_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c53_preserve_mask_we), - .wd (completion_interrupt_c53_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c53.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c53_preserve_mask_qs) - ); - - - // R[reserved_1_c54]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c54 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c54_we), - .wd (reserved_1_c54_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c54_qs) - ); - - - // R[channel_status_c54]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c54_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c54_channel_free_we), - .wd (channel_status_c54_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c54_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c54_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c54_channel_error_we), - .wd (channel_status_c54_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c54_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c54_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c54_field1_we), - .wd (channel_status_c54_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c54_field1_qs) - ); - - - // R[reserved_2_c54]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c54 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c54_we), - .wd (reserved_2_c54_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c54_qs) - ); - - - // R[reserved_3_c54]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c54 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c54]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c54_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c54_intr_enable_we), - .wd (channel_flags_c54_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c54_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c54_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c54_field1_we), - .wd (channel_flags_c54_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c54_field1_qs) - ); - - - // R[length_c54]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c54 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c54_we), - .wd (length_c54_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c54_qs) - ); - - - // R[message_header_c54]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c54_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c54_message_id_we), - .wd (message_header_c54_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c54_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c54_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c54_message_type_we), - .wd (message_header_c54_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c54_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c54_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c54_protocol_id_we), - .wd (message_header_c54_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c54_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c54_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c54_token_we), - .wd (message_header_c54_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c54_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c54_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c54_field1_we), - .wd (message_header_c54_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c54_field1_qs) - ); - - - // R[message_payload_1_c54]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c54 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c54_we), - .wd (message_payload_1_c54_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c54_qs) - ); - - - // R[doorbell_c54]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c54_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c54_intr_we), - .wd (doorbell_c54_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c54.intr.q ), - - // to register interface (read) - .qs (doorbell_c54_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c54_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c54_preserve_mask_we), - .wd (doorbell_c54_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c54.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c54_preserve_mask_qs) - ); - - - // R[completion_interrupt_c54]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c54_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c54_intr_we), - .wd (completion_interrupt_c54_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c54.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c54_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c54_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c54_preserve_mask_we), - .wd (completion_interrupt_c54_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c54.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c54_preserve_mask_qs) - ); - - - // R[reserved_1_c55]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c55 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c55_we), - .wd (reserved_1_c55_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c55_qs) - ); - - - // R[channel_status_c55]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c55_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c55_channel_free_we), - .wd (channel_status_c55_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c55_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c55_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c55_channel_error_we), - .wd (channel_status_c55_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c55_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c55_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c55_field1_we), - .wd (channel_status_c55_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c55_field1_qs) - ); - - - // R[reserved_2_c55]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c55 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c55_we), - .wd (reserved_2_c55_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c55_qs) - ); - - - // R[reserved_3_c55]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c55 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c55]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c55_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c55_intr_enable_we), - .wd (channel_flags_c55_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c55_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c55_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c55_field1_we), - .wd (channel_flags_c55_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c55_field1_qs) - ); - - - // R[length_c55]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c55 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c55_we), - .wd (length_c55_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c55_qs) - ); - - - // R[message_header_c55]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c55_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c55_message_id_we), - .wd (message_header_c55_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c55_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c55_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c55_message_type_we), - .wd (message_header_c55_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c55_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c55_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c55_protocol_id_we), - .wd (message_header_c55_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c55_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c55_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c55_token_we), - .wd (message_header_c55_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c55_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c55_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c55_field1_we), - .wd (message_header_c55_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c55_field1_qs) - ); - - - // R[message_payload_1_c55]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c55 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c55_we), - .wd (message_payload_1_c55_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c55_qs) - ); - - - // R[doorbell_c55]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c55_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c55_intr_we), - .wd (doorbell_c55_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c55.intr.q ), - - // to register interface (read) - .qs (doorbell_c55_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c55_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c55_preserve_mask_we), - .wd (doorbell_c55_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c55.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c55_preserve_mask_qs) - ); - - - // R[completion_interrupt_c55]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c55_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c55_intr_we), - .wd (completion_interrupt_c55_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c55.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c55_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c55_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c55_preserve_mask_we), - .wd (completion_interrupt_c55_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c55.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c55_preserve_mask_qs) - ); - - - // R[reserved_1_c56]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c56 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c56_we), - .wd (reserved_1_c56_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c56_qs) - ); - - - // R[channel_status_c56]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c56_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c56_channel_free_we), - .wd (channel_status_c56_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c56_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c56_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c56_channel_error_we), - .wd (channel_status_c56_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c56_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c56_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c56_field1_we), - .wd (channel_status_c56_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c56_field1_qs) - ); - - - // R[reserved_2_c56]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c56 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c56_we), - .wd (reserved_2_c56_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c56_qs) - ); - - - // R[reserved_3_c56]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c56 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c56]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c56_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c56_intr_enable_we), - .wd (channel_flags_c56_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c56_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c56_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c56_field1_we), - .wd (channel_flags_c56_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c56_field1_qs) - ); - - - // R[length_c56]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c56 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c56_we), - .wd (length_c56_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c56_qs) - ); - - - // R[message_header_c56]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c56_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c56_message_id_we), - .wd (message_header_c56_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c56_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c56_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c56_message_type_we), - .wd (message_header_c56_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c56_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c56_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c56_protocol_id_we), - .wd (message_header_c56_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c56_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c56_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c56_token_we), - .wd (message_header_c56_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c56_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c56_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c56_field1_we), - .wd (message_header_c56_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c56_field1_qs) - ); - - - // R[message_payload_1_c56]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c56 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c56_we), - .wd (message_payload_1_c56_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c56_qs) - ); - - - // R[doorbell_c56]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c56_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c56_intr_we), - .wd (doorbell_c56_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c56.intr.q ), - - // to register interface (read) - .qs (doorbell_c56_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c56_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c56_preserve_mask_we), - .wd (doorbell_c56_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c56.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c56_preserve_mask_qs) - ); - - - // R[completion_interrupt_c56]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c56_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c56_intr_we), - .wd (completion_interrupt_c56_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c56.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c56_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c56_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c56_preserve_mask_we), - .wd (completion_interrupt_c56_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c56.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c56_preserve_mask_qs) - ); - - - // R[reserved_1_c57]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c57 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c57_we), - .wd (reserved_1_c57_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c57_qs) - ); - - - // R[channel_status_c57]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c57_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c57_channel_free_we), - .wd (channel_status_c57_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c57_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c57_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c57_channel_error_we), - .wd (channel_status_c57_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c57_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c57_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c57_field1_we), - .wd (channel_status_c57_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c57_field1_qs) - ); - - - // R[reserved_2_c57]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c57 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c57_we), - .wd (reserved_2_c57_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c57_qs) - ); - - - // R[reserved_3_c57]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c57 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c57]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c57_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c57_intr_enable_we), - .wd (channel_flags_c57_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c57_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c57_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c57_field1_we), - .wd (channel_flags_c57_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c57_field1_qs) - ); - - - // R[length_c57]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c57 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c57_we), - .wd (length_c57_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c57_qs) - ); - - - // R[message_header_c57]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c57_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c57_message_id_we), - .wd (message_header_c57_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c57_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c57_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c57_message_type_we), - .wd (message_header_c57_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c57_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c57_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c57_protocol_id_we), - .wd (message_header_c57_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c57_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c57_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c57_token_we), - .wd (message_header_c57_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c57_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c57_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c57_field1_we), - .wd (message_header_c57_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c57_field1_qs) - ); - - - // R[message_payload_1_c57]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c57 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c57_we), - .wd (message_payload_1_c57_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c57_qs) - ); - - - // R[doorbell_c57]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c57_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c57_intr_we), - .wd (doorbell_c57_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c57.intr.q ), - - // to register interface (read) - .qs (doorbell_c57_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c57_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c57_preserve_mask_we), - .wd (doorbell_c57_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c57.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c57_preserve_mask_qs) - ); - - - // R[completion_interrupt_c57]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c57_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c57_intr_we), - .wd (completion_interrupt_c57_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c57.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c57_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c57_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c57_preserve_mask_we), - .wd (completion_interrupt_c57_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c57.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c57_preserve_mask_qs) - ); - - - // R[reserved_1_c58]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c58 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c58_we), - .wd (reserved_1_c58_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c58_qs) - ); - - - // R[channel_status_c58]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c58_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c58_channel_free_we), - .wd (channel_status_c58_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c58_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c58_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c58_channel_error_we), - .wd (channel_status_c58_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c58_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c58_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c58_field1_we), - .wd (channel_status_c58_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c58_field1_qs) - ); - - - // R[reserved_2_c58]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c58 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c58_we), - .wd (reserved_2_c58_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c58_qs) - ); - - - // R[reserved_3_c58]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c58 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c58]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c58_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c58_intr_enable_we), - .wd (channel_flags_c58_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c58_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c58_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c58_field1_we), - .wd (channel_flags_c58_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c58_field1_qs) - ); - - - // R[length_c58]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c58 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c58_we), - .wd (length_c58_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c58_qs) - ); - - - // R[message_header_c58]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c58_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c58_message_id_we), - .wd (message_header_c58_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c58_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c58_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c58_message_type_we), - .wd (message_header_c58_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c58_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c58_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c58_protocol_id_we), - .wd (message_header_c58_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c58_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c58_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c58_token_we), - .wd (message_header_c58_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c58_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c58_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c58_field1_we), - .wd (message_header_c58_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c58_field1_qs) - ); - - - // R[message_payload_1_c58]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c58 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c58_we), - .wd (message_payload_1_c58_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c58_qs) - ); - - - // R[doorbell_c58]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c58_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c58_intr_we), - .wd (doorbell_c58_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c58.intr.q ), - - // to register interface (read) - .qs (doorbell_c58_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c58_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c58_preserve_mask_we), - .wd (doorbell_c58_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c58.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c58_preserve_mask_qs) - ); - - - // R[completion_interrupt_c58]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c58_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c58_intr_we), - .wd (completion_interrupt_c58_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c58.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c58_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c58_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c58_preserve_mask_we), - .wd (completion_interrupt_c58_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c58.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c58_preserve_mask_qs) - ); - - - // R[reserved_1_c59]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c59 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c59_we), - .wd (reserved_1_c59_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c59_qs) - ); - - - // R[channel_status_c59]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c59_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c59_channel_free_we), - .wd (channel_status_c59_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c59_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c59_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c59_channel_error_we), - .wd (channel_status_c59_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c59_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c59_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c59_field1_we), - .wd (channel_status_c59_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c59_field1_qs) - ); - - - // R[reserved_2_c59]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c59 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c59_we), - .wd (reserved_2_c59_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c59_qs) - ); - - - // R[reserved_3_c59]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c59 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c59]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c59_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c59_intr_enable_we), - .wd (channel_flags_c59_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c59_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c59_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c59_field1_we), - .wd (channel_flags_c59_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c59_field1_qs) - ); - - - // R[length_c59]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c59 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c59_we), - .wd (length_c59_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c59_qs) - ); - - - // R[message_header_c59]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c59_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c59_message_id_we), - .wd (message_header_c59_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c59_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c59_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c59_message_type_we), - .wd (message_header_c59_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c59_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c59_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c59_protocol_id_we), - .wd (message_header_c59_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c59_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c59_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c59_token_we), - .wd (message_header_c59_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c59_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c59_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c59_field1_we), - .wd (message_header_c59_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c59_field1_qs) - ); - - - // R[message_payload_1_c59]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c59 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c59_we), - .wd (message_payload_1_c59_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c59_qs) - ); - - - // R[doorbell_c59]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c59_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c59_intr_we), - .wd (doorbell_c59_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c59.intr.q ), - - // to register interface (read) - .qs (doorbell_c59_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c59_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c59_preserve_mask_we), - .wd (doorbell_c59_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c59.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c59_preserve_mask_qs) - ); - - - // R[completion_interrupt_c59]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c59_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c59_intr_we), - .wd (completion_interrupt_c59_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c59.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c59_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c59_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c59_preserve_mask_we), - .wd (completion_interrupt_c59_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c59.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c59_preserve_mask_qs) - ); - - - // R[reserved_1_c60]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c60 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c60_we), - .wd (reserved_1_c60_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c60_qs) - ); - - - // R[channel_status_c60]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c60_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c60_channel_free_we), - .wd (channel_status_c60_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c60_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c60_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c60_channel_error_we), - .wd (channel_status_c60_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c60_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c60_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c60_field1_we), - .wd (channel_status_c60_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c60_field1_qs) - ); - - - // R[reserved_2_c60]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c60 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c60_we), - .wd (reserved_2_c60_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c60_qs) - ); - - - // R[reserved_3_c60]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c60 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c60]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c60_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c60_intr_enable_we), - .wd (channel_flags_c60_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c60_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c60_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c60_field1_we), - .wd (channel_flags_c60_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c60_field1_qs) - ); - - - // R[length_c60]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c60 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c60_we), - .wd (length_c60_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c60_qs) - ); - - - // R[message_header_c60]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c60_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c60_message_id_we), - .wd (message_header_c60_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c60_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c60_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c60_message_type_we), - .wd (message_header_c60_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c60_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c60_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c60_protocol_id_we), - .wd (message_header_c60_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c60_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c60_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c60_token_we), - .wd (message_header_c60_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c60_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c60_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c60_field1_we), - .wd (message_header_c60_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c60_field1_qs) - ); - - - // R[message_payload_1_c60]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c60 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c60_we), - .wd (message_payload_1_c60_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c60_qs) - ); - - - // R[doorbell_c60]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c60_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c60_intr_we), - .wd (doorbell_c60_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c60.intr.q ), - - // to register interface (read) - .qs (doorbell_c60_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c60_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c60_preserve_mask_we), - .wd (doorbell_c60_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c60.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c60_preserve_mask_qs) - ); - - - // R[completion_interrupt_c60]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c60_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c60_intr_we), - .wd (completion_interrupt_c60_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c60.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c60_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c60_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c60_preserve_mask_we), - .wd (completion_interrupt_c60_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c60.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c60_preserve_mask_qs) - ); - - - // R[reserved_1_c61]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c61 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c61_we), - .wd (reserved_1_c61_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c61_qs) - ); - - - // R[channel_status_c61]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c61_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c61_channel_free_we), - .wd (channel_status_c61_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c61_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c61_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c61_channel_error_we), - .wd (channel_status_c61_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c61_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c61_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c61_field1_we), - .wd (channel_status_c61_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c61_field1_qs) - ); - - - // R[reserved_2_c61]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c61 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c61_we), - .wd (reserved_2_c61_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c61_qs) - ); - - - // R[reserved_3_c61]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c61 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c61]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c61_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c61_intr_enable_we), - .wd (channel_flags_c61_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c61_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c61_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c61_field1_we), - .wd (channel_flags_c61_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c61_field1_qs) - ); - - - // R[length_c61]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c61 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c61_we), - .wd (length_c61_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c61_qs) - ); - - - // R[message_header_c61]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c61_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c61_message_id_we), - .wd (message_header_c61_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c61_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c61_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c61_message_type_we), - .wd (message_header_c61_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c61_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c61_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c61_protocol_id_we), - .wd (message_header_c61_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c61_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c61_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c61_token_we), - .wd (message_header_c61_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c61_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c61_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c61_field1_we), - .wd (message_header_c61_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c61_field1_qs) - ); - - - // R[message_payload_1_c61]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c61 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c61_we), - .wd (message_payload_1_c61_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c61_qs) - ); - - - // R[doorbell_c61]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c61_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c61_intr_we), - .wd (doorbell_c61_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c61.intr.q ), - - // to register interface (read) - .qs (doorbell_c61_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c61_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c61_preserve_mask_we), - .wd (doorbell_c61_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c61.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c61_preserve_mask_qs) - ); - - - // R[completion_interrupt_c61]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c61_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c61_intr_we), - .wd (completion_interrupt_c61_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c61.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c61_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c61_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c61_preserve_mask_we), - .wd (completion_interrupt_c61_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c61.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c61_preserve_mask_qs) - ); - - - // R[reserved_1_c62]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c62 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c62_we), - .wd (reserved_1_c62_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c62_qs) - ); - - - // R[channel_status_c62]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c62_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c62_channel_free_we), - .wd (channel_status_c62_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c62_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c62_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c62_channel_error_we), - .wd (channel_status_c62_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c62_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c62_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c62_field1_we), - .wd (channel_status_c62_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c62_field1_qs) - ); - - - // R[reserved_2_c62]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c62 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c62_we), - .wd (reserved_2_c62_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c62_qs) - ); - - - // R[reserved_3_c62]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c62 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c62]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c62_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c62_intr_enable_we), - .wd (channel_flags_c62_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c62_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c62_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c62_field1_we), - .wd (channel_flags_c62_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c62_field1_qs) - ); - - - // R[length_c62]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c62 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c62_we), - .wd (length_c62_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c62_qs) - ); - - - // R[message_header_c62]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c62_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c62_message_id_we), - .wd (message_header_c62_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c62_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c62_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c62_message_type_we), - .wd (message_header_c62_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c62_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c62_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c62_protocol_id_we), - .wd (message_header_c62_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c62_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c62_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c62_token_we), - .wd (message_header_c62_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c62_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c62_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c62_field1_we), - .wd (message_header_c62_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c62_field1_qs) - ); - - - // R[message_payload_1_c62]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c62 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c62_we), - .wd (message_payload_1_c62_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c62_qs) - ); - - - // R[doorbell_c62]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c62_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c62_intr_we), - .wd (doorbell_c62_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c62.intr.q ), - - // to register interface (read) - .qs (doorbell_c62_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c62_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c62_preserve_mask_we), - .wd (doorbell_c62_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c62.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c62_preserve_mask_qs) - ); - - - // R[completion_interrupt_c62]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c62_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c62_intr_we), - .wd (completion_interrupt_c62_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c62.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c62_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c62_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c62_preserve_mask_we), - .wd (completion_interrupt_c62_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c62.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c62_preserve_mask_qs) - ); - - - // R[reserved_1_c63]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c63 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c63_we), - .wd (reserved_1_c63_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c63_qs) - ); - - - // R[channel_status_c63]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c63_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c63_channel_free_we), - .wd (channel_status_c63_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c63_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c63_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c63_channel_error_we), - .wd (channel_status_c63_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c63_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c63_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c63_field1_we), - .wd (channel_status_c63_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c63_field1_qs) - ); - - - // R[reserved_2_c63]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c63 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c63_we), - .wd (reserved_2_c63_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c63_qs) - ); - - - // R[reserved_3_c63]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c63 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c63]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c63_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c63_intr_enable_we), - .wd (channel_flags_c63_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c63_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c63_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c63_field1_we), - .wd (channel_flags_c63_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c63_field1_qs) - ); - - - // R[length_c63]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c63 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c63_we), - .wd (length_c63_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c63_qs) - ); - - - // R[message_header_c63]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c63_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c63_message_id_we), - .wd (message_header_c63_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c63_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c63_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c63_message_type_we), - .wd (message_header_c63_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c63_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c63_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c63_protocol_id_we), - .wd (message_header_c63_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c63_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c63_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c63_token_we), - .wd (message_header_c63_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c63_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c63_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c63_field1_we), - .wd (message_header_c63_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c63_field1_qs) - ); - - - // R[message_payload_1_c63]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c63 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c63_we), - .wd (message_payload_1_c63_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c63_qs) - ); - - - // R[doorbell_c63]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c63_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c63_intr_we), - .wd (doorbell_c63_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c63.intr.q ), - - // to register interface (read) - .qs (doorbell_c63_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c63_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c63_preserve_mask_we), - .wd (doorbell_c63_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c63.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c63_preserve_mask_qs) - ); - - - // R[completion_interrupt_c63]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c63_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c63_intr_we), - .wd (completion_interrupt_c63_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c63.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c63_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c63_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c63_preserve_mask_we), - .wd (completion_interrupt_c63_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c63.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c63_preserve_mask_qs) - ); - - - // R[reserved_1_c64]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c64 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c64_we), - .wd (reserved_1_c64_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c64_qs) - ); - - - // R[channel_status_c64]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c64_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c64_channel_free_we), - .wd (channel_status_c64_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c64_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c64_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c64_channel_error_we), - .wd (channel_status_c64_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c64_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c64_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c64_field1_we), - .wd (channel_status_c64_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c64_field1_qs) - ); - - - // R[reserved_2_c64]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c64 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c64_we), - .wd (reserved_2_c64_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c64_qs) - ); - - - // R[reserved_3_c64]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c64 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c64]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c64_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c64_intr_enable_we), - .wd (channel_flags_c64_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c64_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c64_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c64_field1_we), - .wd (channel_flags_c64_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c64_field1_qs) - ); - - - // R[length_c64]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c64 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c64_we), - .wd (length_c64_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c64_qs) - ); - - - // R[message_header_c64]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c64_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c64_message_id_we), - .wd (message_header_c64_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c64_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c64_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c64_message_type_we), - .wd (message_header_c64_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c64_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c64_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c64_protocol_id_we), - .wd (message_header_c64_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c64_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c64_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c64_token_we), - .wd (message_header_c64_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c64_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c64_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c64_field1_we), - .wd (message_header_c64_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c64_field1_qs) - ); - - - // R[message_payload_1_c64]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c64 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c64_we), - .wd (message_payload_1_c64_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c64_qs) - ); - - - // R[doorbell_c64]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c64_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c64_intr_we), - .wd (doorbell_c64_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c64.intr.q ), - - // to register interface (read) - .qs (doorbell_c64_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c64_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c64_preserve_mask_we), - .wd (doorbell_c64_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c64.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c64_preserve_mask_qs) - ); - - - // R[completion_interrupt_c64]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c64_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c64_intr_we), - .wd (completion_interrupt_c64_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c64.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c64_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c64_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c64_preserve_mask_we), - .wd (completion_interrupt_c64_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c64.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c64_preserve_mask_qs) - ); - - - // R[reserved_1_c65]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c65 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c65_we), - .wd (reserved_1_c65_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c65_qs) - ); - - - // R[channel_status_c65]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c65_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c65_channel_free_we), - .wd (channel_status_c65_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c65_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c65_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c65_channel_error_we), - .wd (channel_status_c65_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c65_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c65_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c65_field1_we), - .wd (channel_status_c65_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c65_field1_qs) - ); - - - // R[reserved_2_c65]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c65 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c65_we), - .wd (reserved_2_c65_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c65_qs) - ); - - - // R[reserved_3_c65]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c65 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c65]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c65_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c65_intr_enable_we), - .wd (channel_flags_c65_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c65_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c65_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c65_field1_we), - .wd (channel_flags_c65_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c65_field1_qs) - ); - - - // R[length_c65]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c65 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c65_we), - .wd (length_c65_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c65_qs) - ); - - - // R[message_header_c65]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c65_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c65_message_id_we), - .wd (message_header_c65_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c65_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c65_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c65_message_type_we), - .wd (message_header_c65_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c65_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c65_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c65_protocol_id_we), - .wd (message_header_c65_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c65_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c65_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c65_token_we), - .wd (message_header_c65_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c65_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c65_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c65_field1_we), - .wd (message_header_c65_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c65_field1_qs) - ); - - - // R[message_payload_1_c65]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c65 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c65_we), - .wd (message_payload_1_c65_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c65_qs) - ); - - - // R[doorbell_c65]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c65_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c65_intr_we), - .wd (doorbell_c65_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c65.intr.q ), - - // to register interface (read) - .qs (doorbell_c65_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c65_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c65_preserve_mask_we), - .wd (doorbell_c65_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c65.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c65_preserve_mask_qs) - ); - - - // R[completion_interrupt_c65]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c65_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c65_intr_we), - .wd (completion_interrupt_c65_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c65.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c65_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c65_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c65_preserve_mask_we), - .wd (completion_interrupt_c65_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c65.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c65_preserve_mask_qs) - ); - - - // R[reserved_1_c66]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c66 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c66_we), - .wd (reserved_1_c66_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c66_qs) - ); - - - // R[channel_status_c66]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c66_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c66_channel_free_we), - .wd (channel_status_c66_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c66_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c66_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c66_channel_error_we), - .wd (channel_status_c66_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c66_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c66_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c66_field1_we), - .wd (channel_status_c66_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c66_field1_qs) - ); - - - // R[reserved_2_c66]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c66 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c66_we), - .wd (reserved_2_c66_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c66_qs) - ); - - - // R[reserved_3_c66]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c66 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c66]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c66_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c66_intr_enable_we), - .wd (channel_flags_c66_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c66_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c66_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c66_field1_we), - .wd (channel_flags_c66_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c66_field1_qs) - ); - - - // R[length_c66]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c66 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c66_we), - .wd (length_c66_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c66_qs) - ); - - - // R[message_header_c66]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c66_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c66_message_id_we), - .wd (message_header_c66_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c66_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c66_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c66_message_type_we), - .wd (message_header_c66_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c66_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c66_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c66_protocol_id_we), - .wd (message_header_c66_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c66_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c66_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c66_token_we), - .wd (message_header_c66_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c66_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c66_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c66_field1_we), - .wd (message_header_c66_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c66_field1_qs) - ); - - - // R[message_payload_1_c66]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c66 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c66_we), - .wd (message_payload_1_c66_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c66_qs) - ); - - - // R[doorbell_c66]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c66_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c66_intr_we), - .wd (doorbell_c66_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c66.intr.q ), - - // to register interface (read) - .qs (doorbell_c66_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c66_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c66_preserve_mask_we), - .wd (doorbell_c66_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c66.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c66_preserve_mask_qs) - ); - - - // R[completion_interrupt_c66]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c66_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c66_intr_we), - .wd (completion_interrupt_c66_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c66.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c66_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c66_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c66_preserve_mask_we), - .wd (completion_interrupt_c66_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c66.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c66_preserve_mask_qs) - ); - - - // R[reserved_1_c67]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c67 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c67_we), - .wd (reserved_1_c67_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c67_qs) - ); - - - // R[channel_status_c67]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c67_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c67_channel_free_we), - .wd (channel_status_c67_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c67_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c67_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c67_channel_error_we), - .wd (channel_status_c67_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c67_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c67_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c67_field1_we), - .wd (channel_status_c67_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c67_field1_qs) - ); - - - // R[reserved_2_c67]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c67 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c67_we), - .wd (reserved_2_c67_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c67_qs) - ); - - - // R[reserved_3_c67]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c67 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c67]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c67_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c67_intr_enable_we), - .wd (channel_flags_c67_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c67_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c67_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c67_field1_we), - .wd (channel_flags_c67_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c67_field1_qs) - ); - - - // R[length_c67]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c67 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c67_we), - .wd (length_c67_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c67_qs) - ); - - - // R[message_header_c67]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c67_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c67_message_id_we), - .wd (message_header_c67_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c67_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c67_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c67_message_type_we), - .wd (message_header_c67_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c67_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c67_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c67_protocol_id_we), - .wd (message_header_c67_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c67_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c67_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c67_token_we), - .wd (message_header_c67_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c67_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c67_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c67_field1_we), - .wd (message_header_c67_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c67_field1_qs) - ); - - - // R[message_payload_1_c67]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c67 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c67_we), - .wd (message_payload_1_c67_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c67_qs) - ); - - - // R[doorbell_c67]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c67_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c67_intr_we), - .wd (doorbell_c67_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c67.intr.q ), - - // to register interface (read) - .qs (doorbell_c67_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c67_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c67_preserve_mask_we), - .wd (doorbell_c67_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c67.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c67_preserve_mask_qs) - ); - - - // R[completion_interrupt_c67]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c67_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c67_intr_we), - .wd (completion_interrupt_c67_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c67.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c67_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c67_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c67_preserve_mask_we), - .wd (completion_interrupt_c67_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c67.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c67_preserve_mask_qs) - ); - - - // R[reserved_1_c68]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c68 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c68_we), - .wd (reserved_1_c68_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c68_qs) - ); - - - // R[channel_status_c68]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c68_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c68_channel_free_we), - .wd (channel_status_c68_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c68_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c68_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c68_channel_error_we), - .wd (channel_status_c68_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c68_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c68_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c68_field1_we), - .wd (channel_status_c68_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c68_field1_qs) - ); - - - // R[reserved_2_c68]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c68 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c68_we), - .wd (reserved_2_c68_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c68_qs) - ); - - - // R[reserved_3_c68]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c68 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c68]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c68_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c68_intr_enable_we), - .wd (channel_flags_c68_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c68_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c68_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c68_field1_we), - .wd (channel_flags_c68_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c68_field1_qs) - ); - - - // R[length_c68]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c68 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c68_we), - .wd (length_c68_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c68_qs) - ); - - - // R[message_header_c68]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c68_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c68_message_id_we), - .wd (message_header_c68_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c68_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c68_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c68_message_type_we), - .wd (message_header_c68_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c68_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c68_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c68_protocol_id_we), - .wd (message_header_c68_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c68_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c68_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c68_token_we), - .wd (message_header_c68_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c68_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c68_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c68_field1_we), - .wd (message_header_c68_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c68_field1_qs) - ); - - - // R[message_payload_1_c68]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c68 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c68_we), - .wd (message_payload_1_c68_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c68_qs) - ); - - - // R[doorbell_c68]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c68_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c68_intr_we), - .wd (doorbell_c68_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c68.intr.q ), - - // to register interface (read) - .qs (doorbell_c68_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c68_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c68_preserve_mask_we), - .wd (doorbell_c68_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c68.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c68_preserve_mask_qs) - ); - - - // R[completion_interrupt_c68]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c68_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c68_intr_we), - .wd (completion_interrupt_c68_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c68.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c68_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c68_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c68_preserve_mask_we), - .wd (completion_interrupt_c68_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c68.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c68_preserve_mask_qs) - ); - - - // R[reserved_1_c69]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c69 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c69_we), - .wd (reserved_1_c69_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c69_qs) - ); - - - // R[channel_status_c69]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c69_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c69_channel_free_we), - .wd (channel_status_c69_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c69_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c69_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c69_channel_error_we), - .wd (channel_status_c69_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c69_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c69_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c69_field1_we), - .wd (channel_status_c69_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c69_field1_qs) - ); - - - // R[reserved_2_c69]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c69 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c69_we), - .wd (reserved_2_c69_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c69_qs) - ); - - - // R[reserved_3_c69]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c69 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c69]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c69_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c69_intr_enable_we), - .wd (channel_flags_c69_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c69_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c69_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c69_field1_we), - .wd (channel_flags_c69_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c69_field1_qs) - ); - - - // R[length_c69]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c69 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c69_we), - .wd (length_c69_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c69_qs) - ); - - - // R[message_header_c69]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c69_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c69_message_id_we), - .wd (message_header_c69_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c69_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c69_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c69_message_type_we), - .wd (message_header_c69_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c69_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c69_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c69_protocol_id_we), - .wd (message_header_c69_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c69_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c69_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c69_token_we), - .wd (message_header_c69_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c69_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c69_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c69_field1_we), - .wd (message_header_c69_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c69_field1_qs) - ); - - - // R[message_payload_1_c69]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c69 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c69_we), - .wd (message_payload_1_c69_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c69_qs) - ); - - - // R[doorbell_c69]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c69_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c69_intr_we), - .wd (doorbell_c69_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c69.intr.q ), - - // to register interface (read) - .qs (doorbell_c69_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c69_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c69_preserve_mask_we), - .wd (doorbell_c69_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c69.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c69_preserve_mask_qs) - ); - - - // R[completion_interrupt_c69]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c69_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c69_intr_we), - .wd (completion_interrupt_c69_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c69.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c69_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c69_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c69_preserve_mask_we), - .wd (completion_interrupt_c69_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c69.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c69_preserve_mask_qs) - ); - - - // R[reserved_1_c70]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c70 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c70_we), - .wd (reserved_1_c70_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c70_qs) - ); - - - // R[channel_status_c70]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c70_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c70_channel_free_we), - .wd (channel_status_c70_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c70_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c70_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c70_channel_error_we), - .wd (channel_status_c70_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c70_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c70_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c70_field1_we), - .wd (channel_status_c70_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c70_field1_qs) - ); - - - // R[reserved_2_c70]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c70 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c70_we), - .wd (reserved_2_c70_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c70_qs) - ); - - - // R[reserved_3_c70]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c70 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c70]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c70_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c70_intr_enable_we), - .wd (channel_flags_c70_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c70_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c70_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c70_field1_we), - .wd (channel_flags_c70_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c70_field1_qs) - ); - - - // R[length_c70]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c70 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c70_we), - .wd (length_c70_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c70_qs) - ); - - - // R[message_header_c70]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c70_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c70_message_id_we), - .wd (message_header_c70_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c70_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c70_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c70_message_type_we), - .wd (message_header_c70_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c70_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c70_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c70_protocol_id_we), - .wd (message_header_c70_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c70_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c70_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c70_token_we), - .wd (message_header_c70_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c70_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c70_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c70_field1_we), - .wd (message_header_c70_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c70_field1_qs) - ); - - - // R[message_payload_1_c70]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c70 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c70_we), - .wd (message_payload_1_c70_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c70_qs) - ); - - - // R[doorbell_c70]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c70_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c70_intr_we), - .wd (doorbell_c70_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c70.intr.q ), - - // to register interface (read) - .qs (doorbell_c70_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c70_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c70_preserve_mask_we), - .wd (doorbell_c70_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c70.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c70_preserve_mask_qs) - ); - - - // R[completion_interrupt_c70]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c70_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c70_intr_we), - .wd (completion_interrupt_c70_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c70.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c70_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c70_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c70_preserve_mask_we), - .wd (completion_interrupt_c70_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c70.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c70_preserve_mask_qs) - ); - - - // R[reserved_1_c71]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c71 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c71_we), - .wd (reserved_1_c71_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c71_qs) - ); - - - // R[channel_status_c71]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c71_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c71_channel_free_we), - .wd (channel_status_c71_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c71_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c71_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c71_channel_error_we), - .wd (channel_status_c71_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c71_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c71_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c71_field1_we), - .wd (channel_status_c71_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c71_field1_qs) - ); - - - // R[reserved_2_c71]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c71 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c71_we), - .wd (reserved_2_c71_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c71_qs) - ); - - - // R[reserved_3_c71]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c71 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c71]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c71_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c71_intr_enable_we), - .wd (channel_flags_c71_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c71_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c71_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c71_field1_we), - .wd (channel_flags_c71_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c71_field1_qs) - ); - - - // R[length_c71]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c71 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c71_we), - .wd (length_c71_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c71_qs) - ); - - - // R[message_header_c71]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c71_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c71_message_id_we), - .wd (message_header_c71_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c71_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c71_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c71_message_type_we), - .wd (message_header_c71_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c71_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c71_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c71_protocol_id_we), - .wd (message_header_c71_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c71_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c71_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c71_token_we), - .wd (message_header_c71_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c71_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c71_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c71_field1_we), - .wd (message_header_c71_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c71_field1_qs) - ); - - - // R[message_payload_1_c71]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c71 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c71_we), - .wd (message_payload_1_c71_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c71_qs) - ); - - - // R[doorbell_c71]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c71_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c71_intr_we), - .wd (doorbell_c71_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c71.intr.q ), - - // to register interface (read) - .qs (doorbell_c71_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c71_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c71_preserve_mask_we), - .wd (doorbell_c71_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c71.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c71_preserve_mask_qs) - ); - - - // R[completion_interrupt_c71]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c71_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c71_intr_we), - .wd (completion_interrupt_c71_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c71.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c71_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c71_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c71_preserve_mask_we), - .wd (completion_interrupt_c71_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c71.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c71_preserve_mask_qs) - ); - - - // R[reserved_1_c72]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c72 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c72_we), - .wd (reserved_1_c72_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c72_qs) - ); - - - // R[channel_status_c72]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c72_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c72_channel_free_we), - .wd (channel_status_c72_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c72_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c72_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c72_channel_error_we), - .wd (channel_status_c72_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c72_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c72_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c72_field1_we), - .wd (channel_status_c72_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c72_field1_qs) - ); - - - // R[reserved_2_c72]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c72 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c72_we), - .wd (reserved_2_c72_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c72_qs) - ); - - - // R[reserved_3_c72]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c72 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c72]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c72_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c72_intr_enable_we), - .wd (channel_flags_c72_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c72_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c72_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c72_field1_we), - .wd (channel_flags_c72_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c72_field1_qs) - ); - - - // R[length_c72]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c72 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c72_we), - .wd (length_c72_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c72_qs) - ); - - - // R[message_header_c72]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c72_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c72_message_id_we), - .wd (message_header_c72_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c72_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c72_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c72_message_type_we), - .wd (message_header_c72_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c72_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c72_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c72_protocol_id_we), - .wd (message_header_c72_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c72_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c72_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c72_token_we), - .wd (message_header_c72_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c72_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c72_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c72_field1_we), - .wd (message_header_c72_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c72_field1_qs) - ); - - - // R[message_payload_1_c72]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c72 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c72_we), - .wd (message_payload_1_c72_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c72_qs) - ); - - - // R[doorbell_c72]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c72_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c72_intr_we), - .wd (doorbell_c72_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c72.intr.q ), - - // to register interface (read) - .qs (doorbell_c72_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c72_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c72_preserve_mask_we), - .wd (doorbell_c72_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c72.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c72_preserve_mask_qs) - ); - - - // R[completion_interrupt_c72]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c72_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c72_intr_we), - .wd (completion_interrupt_c72_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c72.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c72_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c72_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c72_preserve_mask_we), - .wd (completion_interrupt_c72_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c72.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c72_preserve_mask_qs) - ); - - - // R[reserved_1_c73]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c73 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c73_we), - .wd (reserved_1_c73_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c73_qs) - ); - - - // R[channel_status_c73]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c73_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c73_channel_free_we), - .wd (channel_status_c73_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c73_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c73_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c73_channel_error_we), - .wd (channel_status_c73_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c73_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c73_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c73_field1_we), - .wd (channel_status_c73_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c73_field1_qs) - ); - - - // R[reserved_2_c73]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c73 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c73_we), - .wd (reserved_2_c73_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c73_qs) - ); - - - // R[reserved_3_c73]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c73 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c73]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c73_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c73_intr_enable_we), - .wd (channel_flags_c73_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c73_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c73_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c73_field1_we), - .wd (channel_flags_c73_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c73_field1_qs) - ); - - - // R[length_c73]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c73 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c73_we), - .wd (length_c73_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c73_qs) - ); - - - // R[message_header_c73]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c73_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c73_message_id_we), - .wd (message_header_c73_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c73_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c73_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c73_message_type_we), - .wd (message_header_c73_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c73_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c73_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c73_protocol_id_we), - .wd (message_header_c73_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c73_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c73_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c73_token_we), - .wd (message_header_c73_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c73_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c73_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c73_field1_we), - .wd (message_header_c73_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c73_field1_qs) - ); - - - // R[message_payload_1_c73]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c73 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c73_we), - .wd (message_payload_1_c73_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c73_qs) - ); - - - // R[doorbell_c73]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c73_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c73_intr_we), - .wd (doorbell_c73_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c73.intr.q ), - - // to register interface (read) - .qs (doorbell_c73_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c73_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c73_preserve_mask_we), - .wd (doorbell_c73_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c73.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c73_preserve_mask_qs) - ); - - - // R[completion_interrupt_c73]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c73_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c73_intr_we), - .wd (completion_interrupt_c73_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c73.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c73_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c73_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c73_preserve_mask_we), - .wd (completion_interrupt_c73_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c73.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c73_preserve_mask_qs) - ); - - - // R[reserved_1_c74]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c74 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c74_we), - .wd (reserved_1_c74_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c74_qs) - ); - - - // R[channel_status_c74]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c74_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c74_channel_free_we), - .wd (channel_status_c74_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c74_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c74_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c74_channel_error_we), - .wd (channel_status_c74_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c74_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c74_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c74_field1_we), - .wd (channel_status_c74_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c74_field1_qs) - ); - - - // R[reserved_2_c74]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c74 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c74_we), - .wd (reserved_2_c74_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c74_qs) - ); - - - // R[reserved_3_c74]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c74 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c74]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c74_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c74_intr_enable_we), - .wd (channel_flags_c74_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c74_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c74_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c74_field1_we), - .wd (channel_flags_c74_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c74_field1_qs) - ); - - - // R[length_c74]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c74 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c74_we), - .wd (length_c74_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c74_qs) - ); - - - // R[message_header_c74]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c74_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c74_message_id_we), - .wd (message_header_c74_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c74_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c74_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c74_message_type_we), - .wd (message_header_c74_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c74_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c74_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c74_protocol_id_we), - .wd (message_header_c74_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c74_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c74_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c74_token_we), - .wd (message_header_c74_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c74_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c74_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c74_field1_we), - .wd (message_header_c74_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c74_field1_qs) - ); - - - // R[message_payload_1_c74]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c74 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c74_we), - .wd (message_payload_1_c74_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c74_qs) - ); - - - // R[doorbell_c74]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c74_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c74_intr_we), - .wd (doorbell_c74_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c74.intr.q ), - - // to register interface (read) - .qs (doorbell_c74_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c74_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c74_preserve_mask_we), - .wd (doorbell_c74_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c74.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c74_preserve_mask_qs) - ); - - - // R[completion_interrupt_c74]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c74_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c74_intr_we), - .wd (completion_interrupt_c74_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c74.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c74_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c74_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c74_preserve_mask_we), - .wd (completion_interrupt_c74_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c74.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c74_preserve_mask_qs) - ); - - - // R[reserved_1_c75]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c75 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c75_we), - .wd (reserved_1_c75_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c75_qs) - ); - - - // R[channel_status_c75]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c75_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c75_channel_free_we), - .wd (channel_status_c75_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c75_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c75_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c75_channel_error_we), - .wd (channel_status_c75_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c75_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c75_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c75_field1_we), - .wd (channel_status_c75_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c75_field1_qs) - ); - - - // R[reserved_2_c75]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c75 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c75_we), - .wd (reserved_2_c75_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c75_qs) - ); - - - // R[reserved_3_c75]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c75 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c75]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c75_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c75_intr_enable_we), - .wd (channel_flags_c75_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c75_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c75_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c75_field1_we), - .wd (channel_flags_c75_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c75_field1_qs) - ); - - - // R[length_c75]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c75 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c75_we), - .wd (length_c75_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c75_qs) - ); - - - // R[message_header_c75]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c75_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c75_message_id_we), - .wd (message_header_c75_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c75_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c75_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c75_message_type_we), - .wd (message_header_c75_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c75_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c75_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c75_protocol_id_we), - .wd (message_header_c75_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c75_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c75_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c75_token_we), - .wd (message_header_c75_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c75_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c75_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c75_field1_we), - .wd (message_header_c75_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c75_field1_qs) - ); - - - // R[message_payload_1_c75]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c75 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c75_we), - .wd (message_payload_1_c75_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c75_qs) - ); - - - // R[doorbell_c75]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c75_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c75_intr_we), - .wd (doorbell_c75_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c75.intr.q ), - - // to register interface (read) - .qs (doorbell_c75_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c75_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c75_preserve_mask_we), - .wd (doorbell_c75_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c75.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c75_preserve_mask_qs) - ); - - - // R[completion_interrupt_c75]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c75_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c75_intr_we), - .wd (completion_interrupt_c75_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c75.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c75_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c75_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c75_preserve_mask_we), - .wd (completion_interrupt_c75_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c75.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c75_preserve_mask_qs) - ); - - - // R[reserved_1_c76]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c76 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c76_we), - .wd (reserved_1_c76_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c76_qs) - ); - - - // R[channel_status_c76]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c76_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c76_channel_free_we), - .wd (channel_status_c76_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c76_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c76_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c76_channel_error_we), - .wd (channel_status_c76_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c76_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c76_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c76_field1_we), - .wd (channel_status_c76_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c76_field1_qs) - ); - - - // R[reserved_2_c76]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c76 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c76_we), - .wd (reserved_2_c76_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c76_qs) - ); - - - // R[reserved_3_c76]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c76 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c76]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c76_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c76_intr_enable_we), - .wd (channel_flags_c76_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c76_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c76_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c76_field1_we), - .wd (channel_flags_c76_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c76_field1_qs) - ); - - - // R[length_c76]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c76 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c76_we), - .wd (length_c76_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c76_qs) - ); - - - // R[message_header_c76]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c76_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c76_message_id_we), - .wd (message_header_c76_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c76_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c76_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c76_message_type_we), - .wd (message_header_c76_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c76_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c76_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c76_protocol_id_we), - .wd (message_header_c76_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c76_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c76_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c76_token_we), - .wd (message_header_c76_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c76_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c76_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c76_field1_we), - .wd (message_header_c76_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c76_field1_qs) - ); - - - // R[message_payload_1_c76]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c76 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c76_we), - .wd (message_payload_1_c76_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c76_qs) - ); - - - // R[doorbell_c76]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c76_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c76_intr_we), - .wd (doorbell_c76_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c76.intr.q ), - - // to register interface (read) - .qs (doorbell_c76_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c76_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c76_preserve_mask_we), - .wd (doorbell_c76_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c76.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c76_preserve_mask_qs) - ); - - - // R[completion_interrupt_c76]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c76_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c76_intr_we), - .wd (completion_interrupt_c76_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c76.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c76_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c76_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c76_preserve_mask_we), - .wd (completion_interrupt_c76_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c76.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c76_preserve_mask_qs) - ); - - - // R[reserved_1_c77]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c77 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c77_we), - .wd (reserved_1_c77_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c77_qs) - ); - - - // R[channel_status_c77]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c77_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c77_channel_free_we), - .wd (channel_status_c77_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c77_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c77_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c77_channel_error_we), - .wd (channel_status_c77_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c77_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c77_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c77_field1_we), - .wd (channel_status_c77_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c77_field1_qs) - ); - - - // R[reserved_2_c77]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c77 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c77_we), - .wd (reserved_2_c77_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c77_qs) - ); - - - // R[reserved_3_c77]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c77 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c77]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c77_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c77_intr_enable_we), - .wd (channel_flags_c77_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c77_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c77_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c77_field1_we), - .wd (channel_flags_c77_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c77_field1_qs) - ); - - - // R[length_c77]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c77 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c77_we), - .wd (length_c77_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c77_qs) - ); - - - // R[message_header_c77]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c77_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c77_message_id_we), - .wd (message_header_c77_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c77_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c77_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c77_message_type_we), - .wd (message_header_c77_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c77_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c77_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c77_protocol_id_we), - .wd (message_header_c77_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c77_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c77_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c77_token_we), - .wd (message_header_c77_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c77_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c77_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c77_field1_we), - .wd (message_header_c77_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c77_field1_qs) - ); - - - // R[message_payload_1_c77]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c77 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c77_we), - .wd (message_payload_1_c77_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c77_qs) - ); - - - // R[doorbell_c77]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c77_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c77_intr_we), - .wd (doorbell_c77_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c77.intr.q ), - - // to register interface (read) - .qs (doorbell_c77_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c77_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c77_preserve_mask_we), - .wd (doorbell_c77_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c77.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c77_preserve_mask_qs) - ); - - - // R[completion_interrupt_c77]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c77_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c77_intr_we), - .wd (completion_interrupt_c77_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c77.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c77_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c77_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c77_preserve_mask_we), - .wd (completion_interrupt_c77_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c77.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c77_preserve_mask_qs) - ); - - - // R[reserved_1_c78]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c78 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c78_we), - .wd (reserved_1_c78_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c78_qs) - ); - - - // R[channel_status_c78]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c78_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c78_channel_free_we), - .wd (channel_status_c78_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c78_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c78_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c78_channel_error_we), - .wd (channel_status_c78_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c78_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c78_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c78_field1_we), - .wd (channel_status_c78_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c78_field1_qs) - ); - - - // R[reserved_2_c78]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c78 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c78_we), - .wd (reserved_2_c78_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c78_qs) - ); - - - // R[reserved_3_c78]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c78 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c78]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c78_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c78_intr_enable_we), - .wd (channel_flags_c78_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c78_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c78_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c78_field1_we), - .wd (channel_flags_c78_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c78_field1_qs) - ); - - - // R[length_c78]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c78 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c78_we), - .wd (length_c78_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c78_qs) - ); - - - // R[message_header_c78]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c78_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c78_message_id_we), - .wd (message_header_c78_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c78_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c78_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c78_message_type_we), - .wd (message_header_c78_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c78_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c78_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c78_protocol_id_we), - .wd (message_header_c78_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c78_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c78_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c78_token_we), - .wd (message_header_c78_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c78_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c78_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c78_field1_we), - .wd (message_header_c78_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c78_field1_qs) - ); - - - // R[message_payload_1_c78]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c78 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c78_we), - .wd (message_payload_1_c78_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c78_qs) - ); - - - // R[doorbell_c78]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c78_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c78_intr_we), - .wd (doorbell_c78_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c78.intr.q ), - - // to register interface (read) - .qs (doorbell_c78_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c78_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c78_preserve_mask_we), - .wd (doorbell_c78_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c78.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c78_preserve_mask_qs) - ); - - - // R[completion_interrupt_c78]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c78_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c78_intr_we), - .wd (completion_interrupt_c78_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c78.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c78_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c78_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c78_preserve_mask_we), - .wd (completion_interrupt_c78_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c78.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c78_preserve_mask_qs) - ); - - - // R[reserved_1_c79]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c79 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c79_we), - .wd (reserved_1_c79_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c79_qs) - ); - - - // R[channel_status_c79]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c79_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c79_channel_free_we), - .wd (channel_status_c79_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c79_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c79_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c79_channel_error_we), - .wd (channel_status_c79_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c79_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c79_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c79_field1_we), - .wd (channel_status_c79_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c79_field1_qs) - ); - - - // R[reserved_2_c79]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c79 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c79_we), - .wd (reserved_2_c79_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c79_qs) - ); - - - // R[reserved_3_c79]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c79 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c79]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c79_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c79_intr_enable_we), - .wd (channel_flags_c79_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c79_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c79_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c79_field1_we), - .wd (channel_flags_c79_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c79_field1_qs) - ); - - - // R[length_c79]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c79 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c79_we), - .wd (length_c79_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c79_qs) - ); - - - // R[message_header_c79]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c79_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c79_message_id_we), - .wd (message_header_c79_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c79_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c79_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c79_message_type_we), - .wd (message_header_c79_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c79_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c79_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c79_protocol_id_we), - .wd (message_header_c79_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c79_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c79_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c79_token_we), - .wd (message_header_c79_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c79_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c79_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c79_field1_we), - .wd (message_header_c79_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c79_field1_qs) - ); - - - // R[message_payload_1_c79]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c79 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c79_we), - .wd (message_payload_1_c79_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c79_qs) - ); - - - // R[doorbell_c79]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c79_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c79_intr_we), - .wd (doorbell_c79_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c79.intr.q ), - - // to register interface (read) - .qs (doorbell_c79_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c79_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c79_preserve_mask_we), - .wd (doorbell_c79_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c79.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c79_preserve_mask_qs) - ); - - - // R[completion_interrupt_c79]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c79_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c79_intr_we), - .wd (completion_interrupt_c79_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c79.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c79_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c79_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c79_preserve_mask_we), - .wd (completion_interrupt_c79_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c79.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c79_preserve_mask_qs) - ); - - - // R[reserved_1_c80]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c80 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c80_we), - .wd (reserved_1_c80_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c80_qs) - ); - - - // R[channel_status_c80]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c80_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c80_channel_free_we), - .wd (channel_status_c80_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c80_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c80_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c80_channel_error_we), - .wd (channel_status_c80_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c80_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c80_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c80_field1_we), - .wd (channel_status_c80_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c80_field1_qs) - ); - - - // R[reserved_2_c80]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c80 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c80_we), - .wd (reserved_2_c80_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c80_qs) - ); - - - // R[reserved_3_c80]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c80 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c80]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c80_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c80_intr_enable_we), - .wd (channel_flags_c80_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c80_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c80_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c80_field1_we), - .wd (channel_flags_c80_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c80_field1_qs) - ); - - - // R[length_c80]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c80 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c80_we), - .wd (length_c80_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c80_qs) - ); - - - // R[message_header_c80]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c80_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c80_message_id_we), - .wd (message_header_c80_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c80_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c80_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c80_message_type_we), - .wd (message_header_c80_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c80_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c80_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c80_protocol_id_we), - .wd (message_header_c80_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c80_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c80_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c80_token_we), - .wd (message_header_c80_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c80_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c80_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c80_field1_we), - .wd (message_header_c80_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c80_field1_qs) - ); - - - // R[message_payload_1_c80]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c80 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c80_we), - .wd (message_payload_1_c80_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c80_qs) - ); - - - // R[doorbell_c80]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c80_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c80_intr_we), - .wd (doorbell_c80_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c80.intr.q ), - - // to register interface (read) - .qs (doorbell_c80_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c80_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c80_preserve_mask_we), - .wd (doorbell_c80_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c80.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c80_preserve_mask_qs) - ); - - - // R[completion_interrupt_c80]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c80_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c80_intr_we), - .wd (completion_interrupt_c80_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c80.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c80_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c80_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c80_preserve_mask_we), - .wd (completion_interrupt_c80_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c80.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c80_preserve_mask_qs) - ); - - - // R[reserved_1_c81]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c81 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c81_we), - .wd (reserved_1_c81_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c81_qs) - ); - - - // R[channel_status_c81]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c81_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c81_channel_free_we), - .wd (channel_status_c81_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c81_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c81_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c81_channel_error_we), - .wd (channel_status_c81_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c81_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c81_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c81_field1_we), - .wd (channel_status_c81_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c81_field1_qs) - ); - - - // R[reserved_2_c81]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c81 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c81_we), - .wd (reserved_2_c81_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c81_qs) - ); - - - // R[reserved_3_c81]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c81 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c81]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c81_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c81_intr_enable_we), - .wd (channel_flags_c81_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c81_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c81_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c81_field1_we), - .wd (channel_flags_c81_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c81_field1_qs) - ); - - - // R[length_c81]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c81 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c81_we), - .wd (length_c81_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c81_qs) - ); - - - // R[message_header_c81]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c81_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c81_message_id_we), - .wd (message_header_c81_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c81_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c81_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c81_message_type_we), - .wd (message_header_c81_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c81_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c81_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c81_protocol_id_we), - .wd (message_header_c81_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c81_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c81_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c81_token_we), - .wd (message_header_c81_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c81_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c81_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c81_field1_we), - .wd (message_header_c81_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c81_field1_qs) - ); - - - // R[message_payload_1_c81]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c81 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c81_we), - .wd (message_payload_1_c81_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c81_qs) - ); - - - // R[doorbell_c81]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c81_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c81_intr_we), - .wd (doorbell_c81_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c81.intr.q ), - - // to register interface (read) - .qs (doorbell_c81_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c81_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c81_preserve_mask_we), - .wd (doorbell_c81_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c81.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c81_preserve_mask_qs) - ); - - - // R[completion_interrupt_c81]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c81_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c81_intr_we), - .wd (completion_interrupt_c81_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c81.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c81_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c81_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c81_preserve_mask_we), - .wd (completion_interrupt_c81_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c81.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c81_preserve_mask_qs) - ); - - - // R[reserved_1_c82]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c82 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c82_we), - .wd (reserved_1_c82_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c82_qs) - ); - - - // R[channel_status_c82]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c82_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c82_channel_free_we), - .wd (channel_status_c82_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c82_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c82_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c82_channel_error_we), - .wd (channel_status_c82_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c82_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c82_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c82_field1_we), - .wd (channel_status_c82_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c82_field1_qs) - ); - - - // R[reserved_2_c82]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c82 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c82_we), - .wd (reserved_2_c82_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c82_qs) - ); - - - // R[reserved_3_c82]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c82 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c82]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c82_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c82_intr_enable_we), - .wd (channel_flags_c82_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c82_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c82_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c82_field1_we), - .wd (channel_flags_c82_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c82_field1_qs) - ); - - - // R[length_c82]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c82 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c82_we), - .wd (length_c82_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c82_qs) - ); - - - // R[message_header_c82]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c82_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c82_message_id_we), - .wd (message_header_c82_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c82_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c82_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c82_message_type_we), - .wd (message_header_c82_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c82_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c82_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c82_protocol_id_we), - .wd (message_header_c82_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c82_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c82_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c82_token_we), - .wd (message_header_c82_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c82_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c82_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c82_field1_we), - .wd (message_header_c82_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c82_field1_qs) - ); - - - // R[message_payload_1_c82]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c82 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c82_we), - .wd (message_payload_1_c82_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c82_qs) - ); - - - // R[doorbell_c82]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c82_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c82_intr_we), - .wd (doorbell_c82_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c82.intr.q ), - - // to register interface (read) - .qs (doorbell_c82_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c82_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c82_preserve_mask_we), - .wd (doorbell_c82_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c82.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c82_preserve_mask_qs) - ); - - - // R[completion_interrupt_c82]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c82_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c82_intr_we), - .wd (completion_interrupt_c82_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c82.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c82_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c82_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c82_preserve_mask_we), - .wd (completion_interrupt_c82_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c82.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c82_preserve_mask_qs) - ); - - - // R[reserved_1_c83]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c83 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c83_we), - .wd (reserved_1_c83_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c83_qs) - ); - - - // R[channel_status_c83]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c83_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c83_channel_free_we), - .wd (channel_status_c83_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c83_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c83_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c83_channel_error_we), - .wd (channel_status_c83_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c83_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c83_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c83_field1_we), - .wd (channel_status_c83_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c83_field1_qs) - ); - - - // R[reserved_2_c83]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c83 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c83_we), - .wd (reserved_2_c83_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c83_qs) - ); - - - // R[reserved_3_c83]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c83 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c83]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c83_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c83_intr_enable_we), - .wd (channel_flags_c83_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c83_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c83_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c83_field1_we), - .wd (channel_flags_c83_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c83_field1_qs) - ); - - - // R[length_c83]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c83 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c83_we), - .wd (length_c83_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c83_qs) - ); - - - // R[message_header_c83]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c83_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c83_message_id_we), - .wd (message_header_c83_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c83_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c83_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c83_message_type_we), - .wd (message_header_c83_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c83_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c83_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c83_protocol_id_we), - .wd (message_header_c83_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c83_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c83_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c83_token_we), - .wd (message_header_c83_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c83_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c83_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c83_field1_we), - .wd (message_header_c83_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c83_field1_qs) - ); - - - // R[message_payload_1_c83]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c83 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c83_we), - .wd (message_payload_1_c83_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c83_qs) - ); - - - // R[doorbell_c83]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c83_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c83_intr_we), - .wd (doorbell_c83_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c83.intr.q ), - - // to register interface (read) - .qs (doorbell_c83_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c83_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c83_preserve_mask_we), - .wd (doorbell_c83_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c83.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c83_preserve_mask_qs) - ); - - - // R[completion_interrupt_c83]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c83_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c83_intr_we), - .wd (completion_interrupt_c83_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c83.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c83_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c83_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c83_preserve_mask_we), - .wd (completion_interrupt_c83_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c83.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c83_preserve_mask_qs) - ); - - - // R[reserved_1_c84]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c84 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c84_we), - .wd (reserved_1_c84_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c84_qs) - ); - - - // R[channel_status_c84]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c84_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c84_channel_free_we), - .wd (channel_status_c84_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c84_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c84_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c84_channel_error_we), - .wd (channel_status_c84_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c84_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c84_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c84_field1_we), - .wd (channel_status_c84_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c84_field1_qs) - ); - - - // R[reserved_2_c84]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c84 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c84_we), - .wd (reserved_2_c84_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c84_qs) - ); - - - // R[reserved_3_c84]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c84 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c84]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c84_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c84_intr_enable_we), - .wd (channel_flags_c84_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c84_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c84_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c84_field1_we), - .wd (channel_flags_c84_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c84_field1_qs) - ); - - - // R[length_c84]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c84 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c84_we), - .wd (length_c84_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c84_qs) - ); - - - // R[message_header_c84]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c84_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c84_message_id_we), - .wd (message_header_c84_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c84_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c84_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c84_message_type_we), - .wd (message_header_c84_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c84_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c84_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c84_protocol_id_we), - .wd (message_header_c84_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c84_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c84_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c84_token_we), - .wd (message_header_c84_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c84_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c84_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c84_field1_we), - .wd (message_header_c84_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c84_field1_qs) - ); - - - // R[message_payload_1_c84]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c84 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c84_we), - .wd (message_payload_1_c84_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c84_qs) - ); - - - // R[doorbell_c84]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c84_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c84_intr_we), - .wd (doorbell_c84_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c84.intr.q ), - - // to register interface (read) - .qs (doorbell_c84_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c84_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c84_preserve_mask_we), - .wd (doorbell_c84_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c84.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c84_preserve_mask_qs) - ); - - - // R[completion_interrupt_c84]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c84_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c84_intr_we), - .wd (completion_interrupt_c84_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c84.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c84_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c84_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c84_preserve_mask_we), - .wd (completion_interrupt_c84_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c84.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c84_preserve_mask_qs) - ); - - - // R[reserved_1_c85]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c85 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c85_we), - .wd (reserved_1_c85_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c85_qs) - ); - - - // R[channel_status_c85]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c85_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c85_channel_free_we), - .wd (channel_status_c85_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c85_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c85_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c85_channel_error_we), - .wd (channel_status_c85_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c85_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c85_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c85_field1_we), - .wd (channel_status_c85_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c85_field1_qs) - ); - - - // R[reserved_2_c85]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c85 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c85_we), - .wd (reserved_2_c85_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c85_qs) - ); - - - // R[reserved_3_c85]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c85 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c85]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c85_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c85_intr_enable_we), - .wd (channel_flags_c85_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c85_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c85_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c85_field1_we), - .wd (channel_flags_c85_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c85_field1_qs) - ); - - - // R[length_c85]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c85 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c85_we), - .wd (length_c85_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c85_qs) - ); - - - // R[message_header_c85]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c85_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c85_message_id_we), - .wd (message_header_c85_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c85_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c85_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c85_message_type_we), - .wd (message_header_c85_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c85_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c85_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c85_protocol_id_we), - .wd (message_header_c85_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c85_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c85_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c85_token_we), - .wd (message_header_c85_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c85_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c85_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c85_field1_we), - .wd (message_header_c85_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c85_field1_qs) - ); - - - // R[message_payload_1_c85]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c85 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c85_we), - .wd (message_payload_1_c85_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c85_qs) - ); - - - // R[doorbell_c85]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c85_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c85_intr_we), - .wd (doorbell_c85_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c85.intr.q ), - - // to register interface (read) - .qs (doorbell_c85_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c85_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c85_preserve_mask_we), - .wd (doorbell_c85_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c85.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c85_preserve_mask_qs) - ); - - - // R[completion_interrupt_c85]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c85_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c85_intr_we), - .wd (completion_interrupt_c85_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c85.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c85_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c85_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c85_preserve_mask_we), - .wd (completion_interrupt_c85_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c85.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c85_preserve_mask_qs) - ); - - - // R[reserved_1_c86]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c86 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c86_we), - .wd (reserved_1_c86_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c86_qs) - ); - - - // R[channel_status_c86]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c86_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c86_channel_free_we), - .wd (channel_status_c86_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c86_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c86_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c86_channel_error_we), - .wd (channel_status_c86_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c86_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c86_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c86_field1_we), - .wd (channel_status_c86_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c86_field1_qs) - ); - - - // R[reserved_2_c86]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c86 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c86_we), - .wd (reserved_2_c86_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c86_qs) - ); - - - // R[reserved_3_c86]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c86 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c86]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c86_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c86_intr_enable_we), - .wd (channel_flags_c86_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c86_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c86_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c86_field1_we), - .wd (channel_flags_c86_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c86_field1_qs) - ); - - - // R[length_c86]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c86 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c86_we), - .wd (length_c86_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c86_qs) - ); - - - // R[message_header_c86]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c86_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c86_message_id_we), - .wd (message_header_c86_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c86_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c86_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c86_message_type_we), - .wd (message_header_c86_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c86_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c86_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c86_protocol_id_we), - .wd (message_header_c86_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c86_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c86_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c86_token_we), - .wd (message_header_c86_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c86_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c86_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c86_field1_we), - .wd (message_header_c86_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c86_field1_qs) - ); - - - // R[message_payload_1_c86]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c86 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c86_we), - .wd (message_payload_1_c86_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c86_qs) - ); - - - // R[doorbell_c86]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c86_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c86_intr_we), - .wd (doorbell_c86_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c86.intr.q ), - - // to register interface (read) - .qs (doorbell_c86_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c86_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c86_preserve_mask_we), - .wd (doorbell_c86_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c86.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c86_preserve_mask_qs) - ); - - - // R[completion_interrupt_c86]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c86_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c86_intr_we), - .wd (completion_interrupt_c86_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c86.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c86_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c86_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c86_preserve_mask_we), - .wd (completion_interrupt_c86_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c86.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c86_preserve_mask_qs) - ); - - - // R[reserved_1_c87]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c87 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c87_we), - .wd (reserved_1_c87_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c87_qs) - ); - - - // R[channel_status_c87]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c87_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c87_channel_free_we), - .wd (channel_status_c87_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c87_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c87_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c87_channel_error_we), - .wd (channel_status_c87_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c87_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c87_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c87_field1_we), - .wd (channel_status_c87_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c87_field1_qs) - ); - - - // R[reserved_2_c87]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c87 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c87_we), - .wd (reserved_2_c87_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c87_qs) - ); - - - // R[reserved_3_c87]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c87 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c87]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c87_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c87_intr_enable_we), - .wd (channel_flags_c87_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c87_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c87_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c87_field1_we), - .wd (channel_flags_c87_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c87_field1_qs) - ); - - - // R[length_c87]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c87 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c87_we), - .wd (length_c87_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c87_qs) - ); - - - // R[message_header_c87]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c87_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c87_message_id_we), - .wd (message_header_c87_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c87_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c87_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c87_message_type_we), - .wd (message_header_c87_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c87_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c87_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c87_protocol_id_we), - .wd (message_header_c87_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c87_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c87_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c87_token_we), - .wd (message_header_c87_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c87_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c87_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c87_field1_we), - .wd (message_header_c87_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c87_field1_qs) - ); - - - // R[message_payload_1_c87]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c87 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c87_we), - .wd (message_payload_1_c87_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c87_qs) - ); - - - // R[doorbell_c87]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c87_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c87_intr_we), - .wd (doorbell_c87_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c87.intr.q ), - - // to register interface (read) - .qs (doorbell_c87_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c87_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c87_preserve_mask_we), - .wd (doorbell_c87_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c87.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c87_preserve_mask_qs) - ); - - - // R[completion_interrupt_c87]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c87_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c87_intr_we), - .wd (completion_interrupt_c87_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c87.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c87_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c87_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c87_preserve_mask_we), - .wd (completion_interrupt_c87_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c87.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c87_preserve_mask_qs) - ); - - - // R[reserved_1_c88]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c88 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c88_we), - .wd (reserved_1_c88_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c88_qs) - ); - - - // R[channel_status_c88]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c88_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c88_channel_free_we), - .wd (channel_status_c88_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c88_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c88_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c88_channel_error_we), - .wd (channel_status_c88_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c88_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c88_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c88_field1_we), - .wd (channel_status_c88_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c88_field1_qs) - ); - - - // R[reserved_2_c88]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c88 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c88_we), - .wd (reserved_2_c88_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c88_qs) - ); - - - // R[reserved_3_c88]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c88 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c88]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c88_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c88_intr_enable_we), - .wd (channel_flags_c88_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c88_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c88_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c88_field1_we), - .wd (channel_flags_c88_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c88_field1_qs) - ); - - - // R[length_c88]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c88 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c88_we), - .wd (length_c88_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c88_qs) - ); - - - // R[message_header_c88]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c88_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c88_message_id_we), - .wd (message_header_c88_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c88_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c88_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c88_message_type_we), - .wd (message_header_c88_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c88_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c88_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c88_protocol_id_we), - .wd (message_header_c88_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c88_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c88_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c88_token_we), - .wd (message_header_c88_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c88_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c88_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c88_field1_we), - .wd (message_header_c88_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c88_field1_qs) - ); - - - // R[message_payload_1_c88]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c88 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c88_we), - .wd (message_payload_1_c88_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c88_qs) - ); - - - // R[doorbell_c88]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c88_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c88_intr_we), - .wd (doorbell_c88_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c88.intr.q ), - - // to register interface (read) - .qs (doorbell_c88_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c88_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c88_preserve_mask_we), - .wd (doorbell_c88_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c88.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c88_preserve_mask_qs) - ); - - - // R[completion_interrupt_c88]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c88_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c88_intr_we), - .wd (completion_interrupt_c88_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c88.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c88_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c88_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c88_preserve_mask_we), - .wd (completion_interrupt_c88_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c88.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c88_preserve_mask_qs) - ); - - - // R[reserved_1_c89]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c89 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c89_we), - .wd (reserved_1_c89_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c89_qs) - ); - - - // R[channel_status_c89]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c89_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c89_channel_free_we), - .wd (channel_status_c89_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c89_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c89_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c89_channel_error_we), - .wd (channel_status_c89_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c89_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c89_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c89_field1_we), - .wd (channel_status_c89_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c89_field1_qs) - ); - - - // R[reserved_2_c89]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c89 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c89_we), - .wd (reserved_2_c89_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c89_qs) - ); - - - // R[reserved_3_c89]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c89 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c89]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c89_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c89_intr_enable_we), - .wd (channel_flags_c89_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c89_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c89_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c89_field1_we), - .wd (channel_flags_c89_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c89_field1_qs) - ); - - - // R[length_c89]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c89 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c89_we), - .wd (length_c89_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c89_qs) - ); - - - // R[message_header_c89]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c89_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c89_message_id_we), - .wd (message_header_c89_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c89_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c89_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c89_message_type_we), - .wd (message_header_c89_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c89_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c89_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c89_protocol_id_we), - .wd (message_header_c89_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c89_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c89_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c89_token_we), - .wd (message_header_c89_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c89_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c89_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c89_field1_we), - .wd (message_header_c89_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c89_field1_qs) - ); - - - // R[message_payload_1_c89]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c89 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c89_we), - .wd (message_payload_1_c89_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c89_qs) - ); - - - // R[doorbell_c89]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c89_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c89_intr_we), - .wd (doorbell_c89_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c89.intr.q ), - - // to register interface (read) - .qs (doorbell_c89_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c89_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c89_preserve_mask_we), - .wd (doorbell_c89_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c89.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c89_preserve_mask_qs) - ); - - - // R[completion_interrupt_c89]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c89_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c89_intr_we), - .wd (completion_interrupt_c89_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c89.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c89_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c89_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c89_preserve_mask_we), - .wd (completion_interrupt_c89_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c89.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c89_preserve_mask_qs) - ); - - - // R[reserved_1_c90]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c90 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c90_we), - .wd (reserved_1_c90_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c90_qs) - ); - - - // R[channel_status_c90]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c90_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c90_channel_free_we), - .wd (channel_status_c90_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c90_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c90_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c90_channel_error_we), - .wd (channel_status_c90_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c90_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c90_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c90_field1_we), - .wd (channel_status_c90_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c90_field1_qs) - ); - - - // R[reserved_2_c90]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c90 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c90_we), - .wd (reserved_2_c90_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c90_qs) - ); - - - // R[reserved_3_c90]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c90 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c90]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c90_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c90_intr_enable_we), - .wd (channel_flags_c90_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c90_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c90_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c90_field1_we), - .wd (channel_flags_c90_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c90_field1_qs) - ); - - - // R[length_c90]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c90 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c90_we), - .wd (length_c90_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c90_qs) - ); - - - // R[message_header_c90]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c90_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c90_message_id_we), - .wd (message_header_c90_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c90_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c90_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c90_message_type_we), - .wd (message_header_c90_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c90_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c90_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c90_protocol_id_we), - .wd (message_header_c90_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c90_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c90_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c90_token_we), - .wd (message_header_c90_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c90_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c90_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c90_field1_we), - .wd (message_header_c90_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c90_field1_qs) - ); - - - // R[message_payload_1_c90]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c90 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c90_we), - .wd (message_payload_1_c90_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c90_qs) - ); - - - // R[doorbell_c90]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c90_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c90_intr_we), - .wd (doorbell_c90_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c90.intr.q ), - - // to register interface (read) - .qs (doorbell_c90_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c90_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c90_preserve_mask_we), - .wd (doorbell_c90_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c90.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c90_preserve_mask_qs) - ); - - - // R[completion_interrupt_c90]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c90_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c90_intr_we), - .wd (completion_interrupt_c90_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c90.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c90_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c90_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c90_preserve_mask_we), - .wd (completion_interrupt_c90_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c90.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c90_preserve_mask_qs) - ); - - - // R[reserved_1_c91]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c91 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c91_we), - .wd (reserved_1_c91_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c91_qs) - ); - - - // R[channel_status_c91]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c91_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c91_channel_free_we), - .wd (channel_status_c91_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c91_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c91_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c91_channel_error_we), - .wd (channel_status_c91_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c91_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c91_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c91_field1_we), - .wd (channel_status_c91_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c91_field1_qs) - ); - - - // R[reserved_2_c91]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c91 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c91_we), - .wd (reserved_2_c91_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c91_qs) - ); - - - // R[reserved_3_c91]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c91 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c91]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c91_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c91_intr_enable_we), - .wd (channel_flags_c91_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c91_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c91_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c91_field1_we), - .wd (channel_flags_c91_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c91_field1_qs) - ); - - - // R[length_c91]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c91 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c91_we), - .wd (length_c91_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c91_qs) - ); - - - // R[message_header_c91]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c91_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c91_message_id_we), - .wd (message_header_c91_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c91_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c91_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c91_message_type_we), - .wd (message_header_c91_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c91_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c91_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c91_protocol_id_we), - .wd (message_header_c91_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c91_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c91_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c91_token_we), - .wd (message_header_c91_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c91_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c91_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c91_field1_we), - .wd (message_header_c91_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c91_field1_qs) - ); - - - // R[message_payload_1_c91]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c91 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c91_we), - .wd (message_payload_1_c91_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c91_qs) - ); - - - // R[doorbell_c91]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c91_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c91_intr_we), - .wd (doorbell_c91_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c91.intr.q ), - - // to register interface (read) - .qs (doorbell_c91_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c91_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c91_preserve_mask_we), - .wd (doorbell_c91_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c91.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c91_preserve_mask_qs) - ); - - - // R[completion_interrupt_c91]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c91_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c91_intr_we), - .wd (completion_interrupt_c91_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c91.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c91_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c91_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c91_preserve_mask_we), - .wd (completion_interrupt_c91_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c91.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c91_preserve_mask_qs) - ); - - - // R[reserved_1_c92]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c92 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c92_we), - .wd (reserved_1_c92_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c92_qs) - ); - - - // R[channel_status_c92]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c92_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c92_channel_free_we), - .wd (channel_status_c92_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c92_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c92_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c92_channel_error_we), - .wd (channel_status_c92_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c92_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c92_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c92_field1_we), - .wd (channel_status_c92_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c92_field1_qs) - ); - - - // R[reserved_2_c92]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c92 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c92_we), - .wd (reserved_2_c92_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c92_qs) - ); - - - // R[reserved_3_c92]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c92 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c92]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c92_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c92_intr_enable_we), - .wd (channel_flags_c92_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c92_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c92_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c92_field1_we), - .wd (channel_flags_c92_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c92_field1_qs) - ); - - - // R[length_c92]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c92 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c92_we), - .wd (length_c92_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c92_qs) - ); - - - // R[message_header_c92]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c92_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c92_message_id_we), - .wd (message_header_c92_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c92_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c92_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c92_message_type_we), - .wd (message_header_c92_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c92_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c92_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c92_protocol_id_we), - .wd (message_header_c92_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c92_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c92_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c92_token_we), - .wd (message_header_c92_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c92_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c92_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c92_field1_we), - .wd (message_header_c92_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c92_field1_qs) - ); - - - // R[message_payload_1_c92]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c92 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c92_we), - .wd (message_payload_1_c92_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c92_qs) - ); - - - // R[doorbell_c92]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c92_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c92_intr_we), - .wd (doorbell_c92_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c92.intr.q ), - - // to register interface (read) - .qs (doorbell_c92_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c92_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c92_preserve_mask_we), - .wd (doorbell_c92_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c92.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c92_preserve_mask_qs) - ); - - - // R[completion_interrupt_c92]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c92_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c92_intr_we), - .wd (completion_interrupt_c92_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c92.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c92_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c92_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c92_preserve_mask_we), - .wd (completion_interrupt_c92_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c92.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c92_preserve_mask_qs) - ); - - - // R[reserved_1_c93]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c93 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c93_we), - .wd (reserved_1_c93_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c93_qs) - ); - - - // R[channel_status_c93]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c93_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c93_channel_free_we), - .wd (channel_status_c93_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c93_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c93_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c93_channel_error_we), - .wd (channel_status_c93_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c93_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c93_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c93_field1_we), - .wd (channel_status_c93_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c93_field1_qs) - ); - - - // R[reserved_2_c93]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c93 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c93_we), - .wd (reserved_2_c93_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c93_qs) - ); - - - // R[reserved_3_c93]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c93 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c93]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c93_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c93_intr_enable_we), - .wd (channel_flags_c93_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c93_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c93_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c93_field1_we), - .wd (channel_flags_c93_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c93_field1_qs) - ); - - - // R[length_c93]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c93 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c93_we), - .wd (length_c93_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c93_qs) - ); - - - // R[message_header_c93]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c93_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c93_message_id_we), - .wd (message_header_c93_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c93_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c93_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c93_message_type_we), - .wd (message_header_c93_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c93_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c93_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c93_protocol_id_we), - .wd (message_header_c93_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c93_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c93_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c93_token_we), - .wd (message_header_c93_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c93_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c93_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c93_field1_we), - .wd (message_header_c93_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c93_field1_qs) - ); - - - // R[message_payload_1_c93]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c93 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c93_we), - .wd (message_payload_1_c93_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c93_qs) - ); - - - // R[doorbell_c93]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c93_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c93_intr_we), - .wd (doorbell_c93_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c93.intr.q ), - - // to register interface (read) - .qs (doorbell_c93_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c93_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c93_preserve_mask_we), - .wd (doorbell_c93_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c93.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c93_preserve_mask_qs) - ); - - - // R[completion_interrupt_c93]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c93_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c93_intr_we), - .wd (completion_interrupt_c93_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c93.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c93_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c93_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c93_preserve_mask_we), - .wd (completion_interrupt_c93_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c93.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c93_preserve_mask_qs) - ); - - - // R[reserved_1_c94]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c94 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c94_we), - .wd (reserved_1_c94_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c94_qs) - ); - - - // R[channel_status_c94]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c94_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c94_channel_free_we), - .wd (channel_status_c94_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c94_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c94_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c94_channel_error_we), - .wd (channel_status_c94_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c94_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c94_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c94_field1_we), - .wd (channel_status_c94_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c94_field1_qs) - ); - - - // R[reserved_2_c94]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c94 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c94_we), - .wd (reserved_2_c94_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c94_qs) - ); - - - // R[reserved_3_c94]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c94 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c94]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c94_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c94_intr_enable_we), - .wd (channel_flags_c94_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c94_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c94_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c94_field1_we), - .wd (channel_flags_c94_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c94_field1_qs) - ); - - - // R[length_c94]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c94 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c94_we), - .wd (length_c94_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c94_qs) - ); - - - // R[message_header_c94]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c94_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c94_message_id_we), - .wd (message_header_c94_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c94_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c94_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c94_message_type_we), - .wd (message_header_c94_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c94_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c94_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c94_protocol_id_we), - .wd (message_header_c94_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c94_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c94_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c94_token_we), - .wd (message_header_c94_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c94_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c94_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c94_field1_we), - .wd (message_header_c94_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c94_field1_qs) - ); - - - // R[message_payload_1_c94]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c94 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c94_we), - .wd (message_payload_1_c94_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c94_qs) - ); - - - // R[doorbell_c94]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c94_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c94_intr_we), - .wd (doorbell_c94_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c94.intr.q ), - - // to register interface (read) - .qs (doorbell_c94_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c94_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c94_preserve_mask_we), - .wd (doorbell_c94_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c94.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c94_preserve_mask_qs) - ); - - - // R[completion_interrupt_c94]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c94_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c94_intr_we), - .wd (completion_interrupt_c94_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c94.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c94_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c94_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c94_preserve_mask_we), - .wd (completion_interrupt_c94_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c94.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c94_preserve_mask_qs) - ); - - - // R[reserved_1_c95]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c95 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c95_we), - .wd (reserved_1_c95_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c95_qs) - ); - - - // R[channel_status_c95]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c95_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c95_channel_free_we), - .wd (channel_status_c95_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c95_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c95_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c95_channel_error_we), - .wd (channel_status_c95_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c95_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c95_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c95_field1_we), - .wd (channel_status_c95_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c95_field1_qs) - ); - - - // R[reserved_2_c95]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c95 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c95_we), - .wd (reserved_2_c95_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c95_qs) - ); - - - // R[reserved_3_c95]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c95 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c95]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c95_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c95_intr_enable_we), - .wd (channel_flags_c95_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c95_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c95_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c95_field1_we), - .wd (channel_flags_c95_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c95_field1_qs) - ); - - - // R[length_c95]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c95 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c95_we), - .wd (length_c95_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c95_qs) - ); - - - // R[message_header_c95]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c95_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c95_message_id_we), - .wd (message_header_c95_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c95_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c95_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c95_message_type_we), - .wd (message_header_c95_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c95_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c95_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c95_protocol_id_we), - .wd (message_header_c95_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c95_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c95_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c95_token_we), - .wd (message_header_c95_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c95_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c95_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c95_field1_we), - .wd (message_header_c95_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c95_field1_qs) - ); - - - // R[message_payload_1_c95]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c95 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c95_we), - .wd (message_payload_1_c95_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c95_qs) - ); - - - // R[doorbell_c95]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c95_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c95_intr_we), - .wd (doorbell_c95_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c95.intr.q ), - - // to register interface (read) - .qs (doorbell_c95_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c95_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c95_preserve_mask_we), - .wd (doorbell_c95_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c95.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c95_preserve_mask_qs) - ); - - - // R[completion_interrupt_c95]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c95_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c95_intr_we), - .wd (completion_interrupt_c95_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c95.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c95_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c95_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c95_preserve_mask_we), - .wd (completion_interrupt_c95_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c95.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c95_preserve_mask_qs) - ); - - - // R[reserved_1_c96]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c96 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c96_we), - .wd (reserved_1_c96_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c96_qs) - ); - - - // R[channel_status_c96]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c96_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c96_channel_free_we), - .wd (channel_status_c96_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c96_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c96_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c96_channel_error_we), - .wd (channel_status_c96_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c96_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c96_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c96_field1_we), - .wd (channel_status_c96_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c96_field1_qs) - ); - - - // R[reserved_2_c96]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c96 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c96_we), - .wd (reserved_2_c96_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c96_qs) - ); - - - // R[reserved_3_c96]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c96 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c96]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c96_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c96_intr_enable_we), - .wd (channel_flags_c96_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c96_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c96_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c96_field1_we), - .wd (channel_flags_c96_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c96_field1_qs) - ); - - - // R[length_c96]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c96 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c96_we), - .wd (length_c96_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c96_qs) - ); - - - // R[message_header_c96]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c96_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c96_message_id_we), - .wd (message_header_c96_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c96_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c96_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c96_message_type_we), - .wd (message_header_c96_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c96_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c96_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c96_protocol_id_we), - .wd (message_header_c96_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c96_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c96_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c96_token_we), - .wd (message_header_c96_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c96_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c96_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c96_field1_we), - .wd (message_header_c96_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c96_field1_qs) - ); - - - // R[message_payload_1_c96]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c96 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c96_we), - .wd (message_payload_1_c96_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c96_qs) - ); - - - // R[doorbell_c96]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c96_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c96_intr_we), - .wd (doorbell_c96_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c96.intr.q ), - - // to register interface (read) - .qs (doorbell_c96_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c96_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c96_preserve_mask_we), - .wd (doorbell_c96_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c96.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c96_preserve_mask_qs) - ); - - - // R[completion_interrupt_c96]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c96_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c96_intr_we), - .wd (completion_interrupt_c96_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c96.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c96_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c96_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c96_preserve_mask_we), - .wd (completion_interrupt_c96_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c96.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c96_preserve_mask_qs) - ); - - - // R[reserved_1_c97]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c97 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c97_we), - .wd (reserved_1_c97_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c97_qs) - ); - - - // R[channel_status_c97]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c97_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c97_channel_free_we), - .wd (channel_status_c97_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c97_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c97_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c97_channel_error_we), - .wd (channel_status_c97_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c97_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c97_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c97_field1_we), - .wd (channel_status_c97_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c97_field1_qs) - ); - - - // R[reserved_2_c97]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c97 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c97_we), - .wd (reserved_2_c97_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c97_qs) - ); - - - // R[reserved_3_c97]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c97 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c97]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c97_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c97_intr_enable_we), - .wd (channel_flags_c97_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c97_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c97_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c97_field1_we), - .wd (channel_flags_c97_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c97_field1_qs) - ); - - - // R[length_c97]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c97 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c97_we), - .wd (length_c97_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c97_qs) - ); - - - // R[message_header_c97]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c97_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c97_message_id_we), - .wd (message_header_c97_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c97_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c97_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c97_message_type_we), - .wd (message_header_c97_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c97_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c97_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c97_protocol_id_we), - .wd (message_header_c97_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c97_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c97_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c97_token_we), - .wd (message_header_c97_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c97_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c97_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c97_field1_we), - .wd (message_header_c97_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c97_field1_qs) - ); - - - // R[message_payload_1_c97]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c97 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c97_we), - .wd (message_payload_1_c97_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c97_qs) - ); - - - // R[doorbell_c97]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c97_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c97_intr_we), - .wd (doorbell_c97_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c97.intr.q ), - - // to register interface (read) - .qs (doorbell_c97_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c97_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c97_preserve_mask_we), - .wd (doorbell_c97_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c97.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c97_preserve_mask_qs) - ); - - - // R[completion_interrupt_c97]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c97_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c97_intr_we), - .wd (completion_interrupt_c97_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c97.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c97_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c97_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c97_preserve_mask_we), - .wd (completion_interrupt_c97_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c97.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c97_preserve_mask_qs) - ); - - - // R[reserved_1_c98]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c98 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c98_we), - .wd (reserved_1_c98_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c98_qs) - ); - - - // R[channel_status_c98]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c98_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c98_channel_free_we), - .wd (channel_status_c98_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c98_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c98_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c98_channel_error_we), - .wd (channel_status_c98_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c98_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c98_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c98_field1_we), - .wd (channel_status_c98_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c98_field1_qs) - ); - - - // R[reserved_2_c98]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c98 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c98_we), - .wd (reserved_2_c98_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c98_qs) - ); - - - // R[reserved_3_c98]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c98 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c98]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c98_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c98_intr_enable_we), - .wd (channel_flags_c98_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c98_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c98_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c98_field1_we), - .wd (channel_flags_c98_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c98_field1_qs) - ); - - - // R[length_c98]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c98 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c98_we), - .wd (length_c98_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c98_qs) - ); - - - // R[message_header_c98]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c98_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c98_message_id_we), - .wd (message_header_c98_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c98_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c98_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c98_message_type_we), - .wd (message_header_c98_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c98_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c98_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c98_protocol_id_we), - .wd (message_header_c98_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c98_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c98_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c98_token_we), - .wd (message_header_c98_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c98_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c98_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c98_field1_we), - .wd (message_header_c98_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c98_field1_qs) - ); - - - // R[message_payload_1_c98]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c98 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c98_we), - .wd (message_payload_1_c98_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c98_qs) - ); - - - // R[doorbell_c98]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c98_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c98_intr_we), - .wd (doorbell_c98_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c98.intr.q ), - - // to register interface (read) - .qs (doorbell_c98_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c98_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c98_preserve_mask_we), - .wd (doorbell_c98_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c98.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c98_preserve_mask_qs) - ); - - - // R[completion_interrupt_c98]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c98_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c98_intr_we), - .wd (completion_interrupt_c98_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c98.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c98_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c98_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c98_preserve_mask_we), - .wd (completion_interrupt_c98_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c98.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c98_preserve_mask_qs) - ); - - - // R[reserved_1_c99]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c99 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c99_we), - .wd (reserved_1_c99_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c99_qs) - ); - - - // R[channel_status_c99]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c99_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c99_channel_free_we), - .wd (channel_status_c99_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c99_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c99_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c99_channel_error_we), - .wd (channel_status_c99_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c99_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c99_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c99_field1_we), - .wd (channel_status_c99_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c99_field1_qs) - ); - - - // R[reserved_2_c99]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c99 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c99_we), - .wd (reserved_2_c99_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c99_qs) - ); - - - // R[reserved_3_c99]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c99 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c99]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c99_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c99_intr_enable_we), - .wd (channel_flags_c99_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c99_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c99_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c99_field1_we), - .wd (channel_flags_c99_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c99_field1_qs) - ); - - - // R[length_c99]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c99 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c99_we), - .wd (length_c99_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c99_qs) - ); - - - // R[message_header_c99]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c99_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c99_message_id_we), - .wd (message_header_c99_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c99_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c99_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c99_message_type_we), - .wd (message_header_c99_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c99_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c99_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c99_protocol_id_we), - .wd (message_header_c99_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c99_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c99_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c99_token_we), - .wd (message_header_c99_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c99_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c99_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c99_field1_we), - .wd (message_header_c99_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c99_field1_qs) - ); - - - // R[message_payload_1_c99]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c99 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c99_we), - .wd (message_payload_1_c99_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c99_qs) - ); - - - // R[doorbell_c99]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c99_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c99_intr_we), - .wd (doorbell_c99_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c99.intr.q ), - - // to register interface (read) - .qs (doorbell_c99_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c99_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c99_preserve_mask_we), - .wd (doorbell_c99_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c99.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c99_preserve_mask_qs) - ); - - - // R[completion_interrupt_c99]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c99_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c99_intr_we), - .wd (completion_interrupt_c99_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c99.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c99_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c99_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c99_preserve_mask_we), - .wd (completion_interrupt_c99_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c99.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c99_preserve_mask_qs) - ); - - - // R[reserved_1_c100]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c100 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c100_we), - .wd (reserved_1_c100_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c100_qs) - ); - - - // R[channel_status_c100]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c100_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c100_channel_free_we), - .wd (channel_status_c100_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c100_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c100_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c100_channel_error_we), - .wd (channel_status_c100_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c100_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c100_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c100_field1_we), - .wd (channel_status_c100_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c100_field1_qs) - ); - - - // R[reserved_2_c100]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c100 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c100_we), - .wd (reserved_2_c100_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c100_qs) - ); - - - // R[reserved_3_c100]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c100 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c100]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c100_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c100_intr_enable_we), - .wd (channel_flags_c100_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c100_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c100_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c100_field1_we), - .wd (channel_flags_c100_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c100_field1_qs) - ); - - - // R[length_c100]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c100 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c100_we), - .wd (length_c100_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c100_qs) - ); - - - // R[message_header_c100]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c100_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c100_message_id_we), - .wd (message_header_c100_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c100_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c100_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c100_message_type_we), - .wd (message_header_c100_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c100_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c100_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c100_protocol_id_we), - .wd (message_header_c100_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c100_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c100_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c100_token_we), - .wd (message_header_c100_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c100_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c100_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c100_field1_we), - .wd (message_header_c100_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c100_field1_qs) - ); - - - // R[message_payload_1_c100]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c100 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c100_we), - .wd (message_payload_1_c100_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c100_qs) - ); - - - // R[doorbell_c100]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c100_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c100_intr_we), - .wd (doorbell_c100_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c100.intr.q ), - - // to register interface (read) - .qs (doorbell_c100_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c100_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c100_preserve_mask_we), - .wd (doorbell_c100_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c100.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c100_preserve_mask_qs) - ); - - - // R[completion_interrupt_c100]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c100_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c100_intr_we), - .wd (completion_interrupt_c100_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c100.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c100_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c100_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c100_preserve_mask_we), - .wd (completion_interrupt_c100_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c100.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c100_preserve_mask_qs) - ); - - - // R[reserved_1_c101]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c101 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c101_we), - .wd (reserved_1_c101_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c101_qs) - ); - - - // R[channel_status_c101]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c101_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c101_channel_free_we), - .wd (channel_status_c101_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c101_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c101_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c101_channel_error_we), - .wd (channel_status_c101_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c101_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c101_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c101_field1_we), - .wd (channel_status_c101_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c101_field1_qs) - ); - - - // R[reserved_2_c101]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c101 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c101_we), - .wd (reserved_2_c101_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c101_qs) - ); - - - // R[reserved_3_c101]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c101 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c101]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c101_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c101_intr_enable_we), - .wd (channel_flags_c101_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c101_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c101_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c101_field1_we), - .wd (channel_flags_c101_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c101_field1_qs) - ); - - - // R[length_c101]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c101 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c101_we), - .wd (length_c101_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c101_qs) - ); - - - // R[message_header_c101]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c101_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c101_message_id_we), - .wd (message_header_c101_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c101_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c101_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c101_message_type_we), - .wd (message_header_c101_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c101_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c101_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c101_protocol_id_we), - .wd (message_header_c101_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c101_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c101_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c101_token_we), - .wd (message_header_c101_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c101_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c101_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c101_field1_we), - .wd (message_header_c101_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c101_field1_qs) - ); - - - // R[message_payload_1_c101]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c101 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c101_we), - .wd (message_payload_1_c101_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c101_qs) - ); - - - // R[doorbell_c101]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c101_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c101_intr_we), - .wd (doorbell_c101_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c101.intr.q ), - - // to register interface (read) - .qs (doorbell_c101_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c101_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c101_preserve_mask_we), - .wd (doorbell_c101_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c101.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c101_preserve_mask_qs) - ); - - - // R[completion_interrupt_c101]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c101_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c101_intr_we), - .wd (completion_interrupt_c101_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c101.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c101_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c101_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c101_preserve_mask_we), - .wd (completion_interrupt_c101_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c101.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c101_preserve_mask_qs) - ); - - - // R[reserved_1_c102]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c102 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c102_we), - .wd (reserved_1_c102_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c102_qs) - ); - - - // R[channel_status_c102]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c102_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c102_channel_free_we), - .wd (channel_status_c102_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c102_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c102_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c102_channel_error_we), - .wd (channel_status_c102_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c102_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c102_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c102_field1_we), - .wd (channel_status_c102_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c102_field1_qs) - ); - - - // R[reserved_2_c102]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c102 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c102_we), - .wd (reserved_2_c102_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c102_qs) - ); - - - // R[reserved_3_c102]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c102 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c102]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c102_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c102_intr_enable_we), - .wd (channel_flags_c102_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c102_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c102_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c102_field1_we), - .wd (channel_flags_c102_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c102_field1_qs) - ); - - - // R[length_c102]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c102 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c102_we), - .wd (length_c102_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c102_qs) - ); - - - // R[message_header_c102]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c102_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c102_message_id_we), - .wd (message_header_c102_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c102_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c102_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c102_message_type_we), - .wd (message_header_c102_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c102_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c102_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c102_protocol_id_we), - .wd (message_header_c102_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c102_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c102_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c102_token_we), - .wd (message_header_c102_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c102_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c102_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c102_field1_we), - .wd (message_header_c102_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c102_field1_qs) - ); - - - // R[message_payload_1_c102]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c102 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c102_we), - .wd (message_payload_1_c102_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c102_qs) - ); - - - // R[doorbell_c102]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c102_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c102_intr_we), - .wd (doorbell_c102_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c102.intr.q ), - - // to register interface (read) - .qs (doorbell_c102_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c102_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c102_preserve_mask_we), - .wd (doorbell_c102_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c102.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c102_preserve_mask_qs) - ); - - - // R[completion_interrupt_c102]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c102_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c102_intr_we), - .wd (completion_interrupt_c102_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c102.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c102_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c102_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c102_preserve_mask_we), - .wd (completion_interrupt_c102_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c102.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c102_preserve_mask_qs) - ); - - - // R[reserved_1_c103]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c103 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c103_we), - .wd (reserved_1_c103_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c103_qs) - ); - - - // R[channel_status_c103]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c103_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c103_channel_free_we), - .wd (channel_status_c103_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c103_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c103_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c103_channel_error_we), - .wd (channel_status_c103_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c103_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c103_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c103_field1_we), - .wd (channel_status_c103_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c103_field1_qs) - ); - - - // R[reserved_2_c103]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c103 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c103_we), - .wd (reserved_2_c103_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c103_qs) - ); - - - // R[reserved_3_c103]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c103 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c103]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c103_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c103_intr_enable_we), - .wd (channel_flags_c103_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c103_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c103_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c103_field1_we), - .wd (channel_flags_c103_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c103_field1_qs) - ); - - - // R[length_c103]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c103 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c103_we), - .wd (length_c103_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c103_qs) - ); - - - // R[message_header_c103]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c103_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c103_message_id_we), - .wd (message_header_c103_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c103_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c103_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c103_message_type_we), - .wd (message_header_c103_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c103_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c103_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c103_protocol_id_we), - .wd (message_header_c103_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c103_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c103_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c103_token_we), - .wd (message_header_c103_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c103_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c103_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c103_field1_we), - .wd (message_header_c103_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c103_field1_qs) - ); - - - // R[message_payload_1_c103]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c103 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c103_we), - .wd (message_payload_1_c103_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c103_qs) - ); - - - // R[doorbell_c103]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c103_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c103_intr_we), - .wd (doorbell_c103_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c103.intr.q ), - - // to register interface (read) - .qs (doorbell_c103_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c103_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c103_preserve_mask_we), - .wd (doorbell_c103_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c103.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c103_preserve_mask_qs) - ); - - - // R[completion_interrupt_c103]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c103_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c103_intr_we), - .wd (completion_interrupt_c103_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c103.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c103_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c103_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c103_preserve_mask_we), - .wd (completion_interrupt_c103_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c103.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c103_preserve_mask_qs) - ); - - - // R[reserved_1_c104]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c104 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c104_we), - .wd (reserved_1_c104_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c104_qs) - ); - - - // R[channel_status_c104]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c104_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c104_channel_free_we), - .wd (channel_status_c104_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c104_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c104_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c104_channel_error_we), - .wd (channel_status_c104_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c104_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c104_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c104_field1_we), - .wd (channel_status_c104_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c104_field1_qs) - ); - - - // R[reserved_2_c104]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c104 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c104_we), - .wd (reserved_2_c104_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c104_qs) - ); - - - // R[reserved_3_c104]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c104 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c104]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c104_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c104_intr_enable_we), - .wd (channel_flags_c104_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c104_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c104_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c104_field1_we), - .wd (channel_flags_c104_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c104_field1_qs) - ); - - - // R[length_c104]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c104 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c104_we), - .wd (length_c104_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c104_qs) - ); - - - // R[message_header_c104]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c104_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c104_message_id_we), - .wd (message_header_c104_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c104_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c104_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c104_message_type_we), - .wd (message_header_c104_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c104_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c104_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c104_protocol_id_we), - .wd (message_header_c104_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c104_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c104_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c104_token_we), - .wd (message_header_c104_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c104_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c104_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c104_field1_we), - .wd (message_header_c104_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c104_field1_qs) - ); - - - // R[message_payload_1_c104]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c104 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c104_we), - .wd (message_payload_1_c104_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c104_qs) - ); - - - // R[doorbell_c104]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c104_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c104_intr_we), - .wd (doorbell_c104_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c104.intr.q ), - - // to register interface (read) - .qs (doorbell_c104_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c104_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c104_preserve_mask_we), - .wd (doorbell_c104_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c104.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c104_preserve_mask_qs) - ); - - - // R[completion_interrupt_c104]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c104_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c104_intr_we), - .wd (completion_interrupt_c104_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c104.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c104_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c104_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c104_preserve_mask_we), - .wd (completion_interrupt_c104_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c104.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c104_preserve_mask_qs) - ); - - - // R[reserved_1_c105]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c105 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c105_we), - .wd (reserved_1_c105_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c105_qs) - ); - - - // R[channel_status_c105]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c105_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c105_channel_free_we), - .wd (channel_status_c105_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c105_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c105_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c105_channel_error_we), - .wd (channel_status_c105_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c105_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c105_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c105_field1_we), - .wd (channel_status_c105_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c105_field1_qs) - ); - - - // R[reserved_2_c105]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c105 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c105_we), - .wd (reserved_2_c105_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c105_qs) - ); - - - // R[reserved_3_c105]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c105 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c105]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c105_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c105_intr_enable_we), - .wd (channel_flags_c105_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c105_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c105_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c105_field1_we), - .wd (channel_flags_c105_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c105_field1_qs) - ); - - - // R[length_c105]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c105 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c105_we), - .wd (length_c105_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c105_qs) - ); - - - // R[message_header_c105]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c105_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c105_message_id_we), - .wd (message_header_c105_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c105_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c105_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c105_message_type_we), - .wd (message_header_c105_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c105_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c105_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c105_protocol_id_we), - .wd (message_header_c105_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c105_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c105_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c105_token_we), - .wd (message_header_c105_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c105_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c105_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c105_field1_we), - .wd (message_header_c105_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c105_field1_qs) - ); - - - // R[message_payload_1_c105]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c105 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c105_we), - .wd (message_payload_1_c105_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c105_qs) - ); - - - // R[doorbell_c105]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c105_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c105_intr_we), - .wd (doorbell_c105_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c105.intr.q ), - - // to register interface (read) - .qs (doorbell_c105_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c105_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c105_preserve_mask_we), - .wd (doorbell_c105_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c105.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c105_preserve_mask_qs) - ); - - - // R[completion_interrupt_c105]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c105_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c105_intr_we), - .wd (completion_interrupt_c105_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c105.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c105_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c105_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c105_preserve_mask_we), - .wd (completion_interrupt_c105_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c105.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c105_preserve_mask_qs) - ); - - - // R[reserved_1_c106]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c106 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c106_we), - .wd (reserved_1_c106_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c106_qs) - ); - - - // R[channel_status_c106]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c106_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c106_channel_free_we), - .wd (channel_status_c106_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c106_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c106_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c106_channel_error_we), - .wd (channel_status_c106_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c106_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c106_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c106_field1_we), - .wd (channel_status_c106_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c106_field1_qs) - ); - - - // R[reserved_2_c106]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c106 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c106_we), - .wd (reserved_2_c106_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c106_qs) - ); - - - // R[reserved_3_c106]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c106 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c106]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c106_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c106_intr_enable_we), - .wd (channel_flags_c106_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c106_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c106_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c106_field1_we), - .wd (channel_flags_c106_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c106_field1_qs) - ); - - - // R[length_c106]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c106 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c106_we), - .wd (length_c106_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c106_qs) - ); - - - // R[message_header_c106]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c106_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c106_message_id_we), - .wd (message_header_c106_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c106_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c106_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c106_message_type_we), - .wd (message_header_c106_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c106_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c106_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c106_protocol_id_we), - .wd (message_header_c106_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c106_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c106_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c106_token_we), - .wd (message_header_c106_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c106_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c106_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c106_field1_we), - .wd (message_header_c106_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c106_field1_qs) - ); - - - // R[message_payload_1_c106]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c106 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c106_we), - .wd (message_payload_1_c106_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c106_qs) - ); - - - // R[doorbell_c106]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c106_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c106_intr_we), - .wd (doorbell_c106_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c106.intr.q ), - - // to register interface (read) - .qs (doorbell_c106_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c106_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c106_preserve_mask_we), - .wd (doorbell_c106_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c106.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c106_preserve_mask_qs) - ); - - - // R[completion_interrupt_c106]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c106_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c106_intr_we), - .wd (completion_interrupt_c106_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c106.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c106_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c106_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c106_preserve_mask_we), - .wd (completion_interrupt_c106_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c106.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c106_preserve_mask_qs) - ); - - - // R[reserved_1_c107]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c107 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c107_we), - .wd (reserved_1_c107_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c107_qs) - ); - - - // R[channel_status_c107]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c107_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c107_channel_free_we), - .wd (channel_status_c107_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c107_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c107_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c107_channel_error_we), - .wd (channel_status_c107_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c107_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c107_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c107_field1_we), - .wd (channel_status_c107_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c107_field1_qs) - ); - - - // R[reserved_2_c107]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c107 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c107_we), - .wd (reserved_2_c107_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c107_qs) - ); - - - // R[reserved_3_c107]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c107 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c107]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c107_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c107_intr_enable_we), - .wd (channel_flags_c107_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c107_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c107_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c107_field1_we), - .wd (channel_flags_c107_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c107_field1_qs) - ); - - - // R[length_c107]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c107 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c107_we), - .wd (length_c107_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c107_qs) - ); - - - // R[message_header_c107]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c107_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c107_message_id_we), - .wd (message_header_c107_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c107_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c107_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c107_message_type_we), - .wd (message_header_c107_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c107_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c107_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c107_protocol_id_we), - .wd (message_header_c107_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c107_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c107_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c107_token_we), - .wd (message_header_c107_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c107_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c107_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c107_field1_we), - .wd (message_header_c107_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c107_field1_qs) - ); - - - // R[message_payload_1_c107]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c107 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c107_we), - .wd (message_payload_1_c107_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c107_qs) - ); - - - // R[doorbell_c107]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c107_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c107_intr_we), - .wd (doorbell_c107_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c107.intr.q ), - - // to register interface (read) - .qs (doorbell_c107_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c107_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c107_preserve_mask_we), - .wd (doorbell_c107_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c107.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c107_preserve_mask_qs) - ); - - - // R[completion_interrupt_c107]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c107_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c107_intr_we), - .wd (completion_interrupt_c107_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c107.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c107_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c107_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c107_preserve_mask_we), - .wd (completion_interrupt_c107_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c107.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c107_preserve_mask_qs) - ); - - - // R[reserved_1_c108]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c108 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c108_we), - .wd (reserved_1_c108_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c108_qs) - ); - - - // R[channel_status_c108]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c108_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c108_channel_free_we), - .wd (channel_status_c108_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c108_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c108_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c108_channel_error_we), - .wd (channel_status_c108_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c108_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c108_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c108_field1_we), - .wd (channel_status_c108_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c108_field1_qs) - ); - - - // R[reserved_2_c108]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c108 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c108_we), - .wd (reserved_2_c108_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c108_qs) - ); - - - // R[reserved_3_c108]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c108 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c108]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c108_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c108_intr_enable_we), - .wd (channel_flags_c108_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c108_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c108_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c108_field1_we), - .wd (channel_flags_c108_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c108_field1_qs) - ); - - - // R[length_c108]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c108 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c108_we), - .wd (length_c108_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c108_qs) - ); - - - // R[message_header_c108]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c108_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c108_message_id_we), - .wd (message_header_c108_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c108_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c108_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c108_message_type_we), - .wd (message_header_c108_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c108_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c108_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c108_protocol_id_we), - .wd (message_header_c108_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c108_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c108_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c108_token_we), - .wd (message_header_c108_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c108_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c108_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c108_field1_we), - .wd (message_header_c108_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c108_field1_qs) - ); - - - // R[message_payload_1_c108]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c108 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c108_we), - .wd (message_payload_1_c108_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c108_qs) - ); - - - // R[doorbell_c108]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c108_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c108_intr_we), - .wd (doorbell_c108_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c108.intr.q ), - - // to register interface (read) - .qs (doorbell_c108_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c108_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c108_preserve_mask_we), - .wd (doorbell_c108_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c108.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c108_preserve_mask_qs) - ); - - - // R[completion_interrupt_c108]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c108_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c108_intr_we), - .wd (completion_interrupt_c108_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c108.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c108_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c108_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c108_preserve_mask_we), - .wd (completion_interrupt_c108_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c108.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c108_preserve_mask_qs) - ); - - - // R[reserved_1_c109]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c109 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c109_we), - .wd (reserved_1_c109_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c109_qs) - ); - - - // R[channel_status_c109]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c109_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c109_channel_free_we), - .wd (channel_status_c109_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c109_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c109_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c109_channel_error_we), - .wd (channel_status_c109_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c109_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c109_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c109_field1_we), - .wd (channel_status_c109_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c109_field1_qs) - ); - - - // R[reserved_2_c109]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c109 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c109_we), - .wd (reserved_2_c109_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c109_qs) - ); - - - // R[reserved_3_c109]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c109 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c109]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c109_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c109_intr_enable_we), - .wd (channel_flags_c109_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c109_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c109_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c109_field1_we), - .wd (channel_flags_c109_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c109_field1_qs) - ); - - - // R[length_c109]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c109 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c109_we), - .wd (length_c109_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c109_qs) - ); - - - // R[message_header_c109]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c109_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c109_message_id_we), - .wd (message_header_c109_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c109_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c109_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c109_message_type_we), - .wd (message_header_c109_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c109_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c109_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c109_protocol_id_we), - .wd (message_header_c109_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c109_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c109_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c109_token_we), - .wd (message_header_c109_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c109_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c109_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c109_field1_we), - .wd (message_header_c109_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c109_field1_qs) - ); - - - // R[message_payload_1_c109]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c109 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c109_we), - .wd (message_payload_1_c109_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c109_qs) - ); - - - // R[doorbell_c109]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c109_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c109_intr_we), - .wd (doorbell_c109_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c109.intr.q ), - - // to register interface (read) - .qs (doorbell_c109_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c109_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c109_preserve_mask_we), - .wd (doorbell_c109_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c109.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c109_preserve_mask_qs) - ); - - - // R[completion_interrupt_c109]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c109_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c109_intr_we), - .wd (completion_interrupt_c109_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c109.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c109_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c109_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c109_preserve_mask_we), - .wd (completion_interrupt_c109_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c109.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c109_preserve_mask_qs) - ); - - - // R[reserved_1_c110]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c110 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c110_we), - .wd (reserved_1_c110_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c110_qs) - ); - - - // R[channel_status_c110]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c110_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c110_channel_free_we), - .wd (channel_status_c110_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c110_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c110_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c110_channel_error_we), - .wd (channel_status_c110_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c110_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c110_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c110_field1_we), - .wd (channel_status_c110_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c110_field1_qs) - ); - - - // R[reserved_2_c110]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c110 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c110_we), - .wd (reserved_2_c110_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c110_qs) - ); - - - // R[reserved_3_c110]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c110 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c110]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c110_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c110_intr_enable_we), - .wd (channel_flags_c110_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c110_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c110_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c110_field1_we), - .wd (channel_flags_c110_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c110_field1_qs) - ); - - - // R[length_c110]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c110 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c110_we), - .wd (length_c110_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c110_qs) - ); - - - // R[message_header_c110]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c110_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c110_message_id_we), - .wd (message_header_c110_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c110_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c110_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c110_message_type_we), - .wd (message_header_c110_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c110_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c110_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c110_protocol_id_we), - .wd (message_header_c110_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c110_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c110_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c110_token_we), - .wd (message_header_c110_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c110_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c110_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c110_field1_we), - .wd (message_header_c110_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c110_field1_qs) - ); - - - // R[message_payload_1_c110]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c110 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c110_we), - .wd (message_payload_1_c110_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c110_qs) - ); - - - // R[doorbell_c110]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c110_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c110_intr_we), - .wd (doorbell_c110_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c110.intr.q ), - - // to register interface (read) - .qs (doorbell_c110_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c110_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c110_preserve_mask_we), - .wd (doorbell_c110_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c110.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c110_preserve_mask_qs) - ); - - - // R[completion_interrupt_c110]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c110_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c110_intr_we), - .wd (completion_interrupt_c110_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c110.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c110_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c110_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c110_preserve_mask_we), - .wd (completion_interrupt_c110_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c110.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c110_preserve_mask_qs) - ); - - - // R[reserved_1_c111]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c111 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c111_we), - .wd (reserved_1_c111_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c111_qs) - ); - - - // R[channel_status_c111]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c111_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c111_channel_free_we), - .wd (channel_status_c111_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c111_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c111_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c111_channel_error_we), - .wd (channel_status_c111_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c111_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c111_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c111_field1_we), - .wd (channel_status_c111_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c111_field1_qs) - ); - - - // R[reserved_2_c111]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c111 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c111_we), - .wd (reserved_2_c111_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c111_qs) - ); - - - // R[reserved_3_c111]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c111 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c111]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c111_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c111_intr_enable_we), - .wd (channel_flags_c111_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c111_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c111_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c111_field1_we), - .wd (channel_flags_c111_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c111_field1_qs) - ); - - - // R[length_c111]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c111 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c111_we), - .wd (length_c111_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c111_qs) - ); - - - // R[message_header_c111]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c111_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c111_message_id_we), - .wd (message_header_c111_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c111_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c111_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c111_message_type_we), - .wd (message_header_c111_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c111_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c111_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c111_protocol_id_we), - .wd (message_header_c111_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c111_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c111_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c111_token_we), - .wd (message_header_c111_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c111_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c111_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c111_field1_we), - .wd (message_header_c111_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c111_field1_qs) - ); - - - // R[message_payload_1_c111]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c111 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c111_we), - .wd (message_payload_1_c111_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c111_qs) - ); - - - // R[doorbell_c111]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c111_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c111_intr_we), - .wd (doorbell_c111_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c111.intr.q ), - - // to register interface (read) - .qs (doorbell_c111_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c111_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c111_preserve_mask_we), - .wd (doorbell_c111_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c111.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c111_preserve_mask_qs) - ); - - - // R[completion_interrupt_c111]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c111_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c111_intr_we), - .wd (completion_interrupt_c111_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c111.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c111_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c111_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c111_preserve_mask_we), - .wd (completion_interrupt_c111_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c111.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c111_preserve_mask_qs) - ); - - - // R[reserved_1_c112]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c112 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c112_we), - .wd (reserved_1_c112_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c112_qs) - ); - - - // R[channel_status_c112]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c112_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c112_channel_free_we), - .wd (channel_status_c112_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c112_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c112_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c112_channel_error_we), - .wd (channel_status_c112_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c112_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c112_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c112_field1_we), - .wd (channel_status_c112_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c112_field1_qs) - ); - - - // R[reserved_2_c112]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c112 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c112_we), - .wd (reserved_2_c112_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c112_qs) - ); - - - // R[reserved_3_c112]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c112 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c112]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c112_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c112_intr_enable_we), - .wd (channel_flags_c112_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c112_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c112_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c112_field1_we), - .wd (channel_flags_c112_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c112_field1_qs) - ); - - - // R[length_c112]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c112 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c112_we), - .wd (length_c112_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c112_qs) - ); - - - // R[message_header_c112]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c112_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c112_message_id_we), - .wd (message_header_c112_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c112_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c112_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c112_message_type_we), - .wd (message_header_c112_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c112_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c112_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c112_protocol_id_we), - .wd (message_header_c112_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c112_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c112_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c112_token_we), - .wd (message_header_c112_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c112_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c112_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c112_field1_we), - .wd (message_header_c112_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c112_field1_qs) - ); - - - // R[message_payload_1_c112]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c112 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c112_we), - .wd (message_payload_1_c112_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c112_qs) - ); - - - // R[doorbell_c112]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c112_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c112_intr_we), - .wd (doorbell_c112_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c112.intr.q ), - - // to register interface (read) - .qs (doorbell_c112_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c112_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c112_preserve_mask_we), - .wd (doorbell_c112_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c112.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c112_preserve_mask_qs) - ); - - - // R[completion_interrupt_c112]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c112_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c112_intr_we), - .wd (completion_interrupt_c112_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c112.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c112_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c112_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c112_preserve_mask_we), - .wd (completion_interrupt_c112_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c112.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c112_preserve_mask_qs) - ); - - - // R[reserved_1_c113]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c113 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c113_we), - .wd (reserved_1_c113_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c113_qs) - ); - - - // R[channel_status_c113]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c113_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c113_channel_free_we), - .wd (channel_status_c113_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c113_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c113_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c113_channel_error_we), - .wd (channel_status_c113_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c113_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c113_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c113_field1_we), - .wd (channel_status_c113_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c113_field1_qs) - ); - - - // R[reserved_2_c113]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c113 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c113_we), - .wd (reserved_2_c113_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c113_qs) - ); - - - // R[reserved_3_c113]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c113 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c113]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c113_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c113_intr_enable_we), - .wd (channel_flags_c113_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c113_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c113_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c113_field1_we), - .wd (channel_flags_c113_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c113_field1_qs) - ); - - - // R[length_c113]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c113 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c113_we), - .wd (length_c113_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c113_qs) - ); - - - // R[message_header_c113]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c113_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c113_message_id_we), - .wd (message_header_c113_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c113_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c113_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c113_message_type_we), - .wd (message_header_c113_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c113_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c113_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c113_protocol_id_we), - .wd (message_header_c113_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c113_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c113_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c113_token_we), - .wd (message_header_c113_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c113_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c113_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c113_field1_we), - .wd (message_header_c113_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c113_field1_qs) - ); - - - // R[message_payload_1_c113]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c113 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c113_we), - .wd (message_payload_1_c113_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c113_qs) - ); - - - // R[doorbell_c113]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c113_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c113_intr_we), - .wd (doorbell_c113_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c113.intr.q ), - - // to register interface (read) - .qs (doorbell_c113_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c113_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c113_preserve_mask_we), - .wd (doorbell_c113_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c113.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c113_preserve_mask_qs) - ); - - - // R[completion_interrupt_c113]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c113_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c113_intr_we), - .wd (completion_interrupt_c113_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c113.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c113_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c113_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c113_preserve_mask_we), - .wd (completion_interrupt_c113_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c113.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c113_preserve_mask_qs) - ); - - - // R[reserved_1_c114]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c114 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c114_we), - .wd (reserved_1_c114_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c114_qs) - ); - - - // R[channel_status_c114]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c114_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c114_channel_free_we), - .wd (channel_status_c114_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c114_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c114_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c114_channel_error_we), - .wd (channel_status_c114_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c114_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c114_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c114_field1_we), - .wd (channel_status_c114_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c114_field1_qs) - ); - - - // R[reserved_2_c114]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c114 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c114_we), - .wd (reserved_2_c114_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c114_qs) - ); - - - // R[reserved_3_c114]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c114 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c114]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c114_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c114_intr_enable_we), - .wd (channel_flags_c114_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c114_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c114_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c114_field1_we), - .wd (channel_flags_c114_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c114_field1_qs) - ); - - - // R[length_c114]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c114 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c114_we), - .wd (length_c114_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c114_qs) - ); - - - // R[message_header_c114]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c114_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c114_message_id_we), - .wd (message_header_c114_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c114_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c114_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c114_message_type_we), - .wd (message_header_c114_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c114_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c114_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c114_protocol_id_we), - .wd (message_header_c114_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c114_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c114_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c114_token_we), - .wd (message_header_c114_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c114_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c114_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c114_field1_we), - .wd (message_header_c114_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c114_field1_qs) - ); - - - // R[message_payload_1_c114]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c114 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c114_we), - .wd (message_payload_1_c114_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c114_qs) - ); - - - // R[doorbell_c114]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c114_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c114_intr_we), - .wd (doorbell_c114_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c114.intr.q ), - - // to register interface (read) - .qs (doorbell_c114_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c114_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c114_preserve_mask_we), - .wd (doorbell_c114_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c114.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c114_preserve_mask_qs) - ); - - - // R[completion_interrupt_c114]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c114_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c114_intr_we), - .wd (completion_interrupt_c114_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c114.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c114_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c114_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c114_preserve_mask_we), - .wd (completion_interrupt_c114_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c114.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c114_preserve_mask_qs) - ); - - - // R[reserved_1_c115]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c115 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c115_we), - .wd (reserved_1_c115_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c115_qs) - ); - - - // R[channel_status_c115]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c115_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c115_channel_free_we), - .wd (channel_status_c115_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c115_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c115_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c115_channel_error_we), - .wd (channel_status_c115_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c115_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c115_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c115_field1_we), - .wd (channel_status_c115_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c115_field1_qs) - ); - - - // R[reserved_2_c115]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c115 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c115_we), - .wd (reserved_2_c115_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c115_qs) - ); - - - // R[reserved_3_c115]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c115 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c115]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c115_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c115_intr_enable_we), - .wd (channel_flags_c115_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c115_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c115_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c115_field1_we), - .wd (channel_flags_c115_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c115_field1_qs) - ); - - - // R[length_c115]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c115 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c115_we), - .wd (length_c115_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c115_qs) - ); - - - // R[message_header_c115]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c115_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c115_message_id_we), - .wd (message_header_c115_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c115_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c115_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c115_message_type_we), - .wd (message_header_c115_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c115_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c115_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c115_protocol_id_we), - .wd (message_header_c115_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c115_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c115_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c115_token_we), - .wd (message_header_c115_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c115_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c115_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c115_field1_we), - .wd (message_header_c115_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c115_field1_qs) - ); - - - // R[message_payload_1_c115]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c115 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c115_we), - .wd (message_payload_1_c115_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c115_qs) - ); - - - // R[doorbell_c115]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c115_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c115_intr_we), - .wd (doorbell_c115_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c115.intr.q ), - - // to register interface (read) - .qs (doorbell_c115_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c115_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c115_preserve_mask_we), - .wd (doorbell_c115_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c115.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c115_preserve_mask_qs) - ); - - - // R[completion_interrupt_c115]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c115_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c115_intr_we), - .wd (completion_interrupt_c115_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c115.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c115_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c115_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c115_preserve_mask_we), - .wd (completion_interrupt_c115_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c115.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c115_preserve_mask_qs) - ); - - - // R[reserved_1_c116]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c116 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c116_we), - .wd (reserved_1_c116_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c116_qs) - ); - - - // R[channel_status_c116]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c116_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c116_channel_free_we), - .wd (channel_status_c116_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c116_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c116_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c116_channel_error_we), - .wd (channel_status_c116_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c116_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c116_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c116_field1_we), - .wd (channel_status_c116_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c116_field1_qs) - ); - - - // R[reserved_2_c116]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c116 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c116_we), - .wd (reserved_2_c116_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c116_qs) - ); - - - // R[reserved_3_c116]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c116 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c116]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c116_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c116_intr_enable_we), - .wd (channel_flags_c116_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c116_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c116_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c116_field1_we), - .wd (channel_flags_c116_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c116_field1_qs) - ); - - - // R[length_c116]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c116 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c116_we), - .wd (length_c116_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c116_qs) - ); - - - // R[message_header_c116]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c116_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c116_message_id_we), - .wd (message_header_c116_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c116_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c116_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c116_message_type_we), - .wd (message_header_c116_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c116_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c116_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c116_protocol_id_we), - .wd (message_header_c116_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c116_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c116_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c116_token_we), - .wd (message_header_c116_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c116_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c116_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c116_field1_we), - .wd (message_header_c116_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c116_field1_qs) - ); - - - // R[message_payload_1_c116]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c116 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c116_we), - .wd (message_payload_1_c116_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c116_qs) - ); - - - // R[doorbell_c116]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c116_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c116_intr_we), - .wd (doorbell_c116_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c116.intr.q ), - - // to register interface (read) - .qs (doorbell_c116_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c116_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c116_preserve_mask_we), - .wd (doorbell_c116_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c116.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c116_preserve_mask_qs) - ); - - - // R[completion_interrupt_c116]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c116_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c116_intr_we), - .wd (completion_interrupt_c116_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c116.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c116_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c116_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c116_preserve_mask_we), - .wd (completion_interrupt_c116_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c116.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c116_preserve_mask_qs) - ); - - - // R[reserved_1_c117]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c117 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c117_we), - .wd (reserved_1_c117_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c117_qs) - ); - - - // R[channel_status_c117]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c117_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c117_channel_free_we), - .wd (channel_status_c117_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c117_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c117_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c117_channel_error_we), - .wd (channel_status_c117_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c117_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c117_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c117_field1_we), - .wd (channel_status_c117_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c117_field1_qs) - ); - - - // R[reserved_2_c117]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c117 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c117_we), - .wd (reserved_2_c117_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c117_qs) - ); - - - // R[reserved_3_c117]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c117 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c117]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c117_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c117_intr_enable_we), - .wd (channel_flags_c117_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c117_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c117_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c117_field1_we), - .wd (channel_flags_c117_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c117_field1_qs) - ); - - - // R[length_c117]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c117 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c117_we), - .wd (length_c117_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c117_qs) - ); - - - // R[message_header_c117]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c117_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c117_message_id_we), - .wd (message_header_c117_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c117_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c117_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c117_message_type_we), - .wd (message_header_c117_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c117_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c117_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c117_protocol_id_we), - .wd (message_header_c117_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c117_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c117_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c117_token_we), - .wd (message_header_c117_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c117_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c117_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c117_field1_we), - .wd (message_header_c117_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c117_field1_qs) - ); - - - // R[message_payload_1_c117]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c117 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c117_we), - .wd (message_payload_1_c117_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c117_qs) - ); - - - // R[doorbell_c117]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c117_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c117_intr_we), - .wd (doorbell_c117_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c117.intr.q ), - - // to register interface (read) - .qs (doorbell_c117_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c117_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c117_preserve_mask_we), - .wd (doorbell_c117_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c117.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c117_preserve_mask_qs) - ); - - - // R[completion_interrupt_c117]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c117_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c117_intr_we), - .wd (completion_interrupt_c117_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c117.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c117_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c117_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c117_preserve_mask_we), - .wd (completion_interrupt_c117_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c117.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c117_preserve_mask_qs) - ); - - - // R[reserved_1_c118]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c118 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c118_we), - .wd (reserved_1_c118_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c118_qs) - ); - - - // R[channel_status_c118]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c118_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c118_channel_free_we), - .wd (channel_status_c118_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c118_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c118_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c118_channel_error_we), - .wd (channel_status_c118_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c118_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c118_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c118_field1_we), - .wd (channel_status_c118_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c118_field1_qs) - ); - - - // R[reserved_2_c118]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c118 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c118_we), - .wd (reserved_2_c118_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c118_qs) - ); - - - // R[reserved_3_c118]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c118 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c118]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c118_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c118_intr_enable_we), - .wd (channel_flags_c118_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c118_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c118_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c118_field1_we), - .wd (channel_flags_c118_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c118_field1_qs) - ); - - - // R[length_c118]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c118 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c118_we), - .wd (length_c118_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c118_qs) - ); - - - // R[message_header_c118]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c118_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c118_message_id_we), - .wd (message_header_c118_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c118_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c118_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c118_message_type_we), - .wd (message_header_c118_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c118_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c118_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c118_protocol_id_we), - .wd (message_header_c118_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c118_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c118_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c118_token_we), - .wd (message_header_c118_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c118_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c118_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c118_field1_we), - .wd (message_header_c118_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c118_field1_qs) - ); - - - // R[message_payload_1_c118]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c118 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c118_we), - .wd (message_payload_1_c118_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c118_qs) - ); - - - // R[doorbell_c118]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c118_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c118_intr_we), - .wd (doorbell_c118_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c118.intr.q ), - - // to register interface (read) - .qs (doorbell_c118_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c118_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c118_preserve_mask_we), - .wd (doorbell_c118_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c118.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c118_preserve_mask_qs) - ); - - - // R[completion_interrupt_c118]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c118_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c118_intr_we), - .wd (completion_interrupt_c118_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c118.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c118_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c118_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c118_preserve_mask_we), - .wd (completion_interrupt_c118_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c118.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c118_preserve_mask_qs) - ); - - - // R[reserved_1_c119]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c119 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c119_we), - .wd (reserved_1_c119_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c119_qs) - ); - - - // R[channel_status_c119]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c119_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c119_channel_free_we), - .wd (channel_status_c119_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c119_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c119_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c119_channel_error_we), - .wd (channel_status_c119_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c119_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c119_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c119_field1_we), - .wd (channel_status_c119_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c119_field1_qs) - ); - - - // R[reserved_2_c119]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c119 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c119_we), - .wd (reserved_2_c119_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c119_qs) - ); - - - // R[reserved_3_c119]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c119 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c119]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c119_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c119_intr_enable_we), - .wd (channel_flags_c119_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c119_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c119_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c119_field1_we), - .wd (channel_flags_c119_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c119_field1_qs) - ); - - - // R[length_c119]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c119 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c119_we), - .wd (length_c119_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c119_qs) - ); - - - // R[message_header_c119]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c119_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c119_message_id_we), - .wd (message_header_c119_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c119_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c119_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c119_message_type_we), - .wd (message_header_c119_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c119_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c119_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c119_protocol_id_we), - .wd (message_header_c119_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c119_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c119_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c119_token_we), - .wd (message_header_c119_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c119_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c119_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c119_field1_we), - .wd (message_header_c119_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c119_field1_qs) - ); - - - // R[message_payload_1_c119]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c119 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c119_we), - .wd (message_payload_1_c119_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c119_qs) - ); - - - // R[doorbell_c119]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c119_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c119_intr_we), - .wd (doorbell_c119_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c119.intr.q ), - - // to register interface (read) - .qs (doorbell_c119_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c119_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c119_preserve_mask_we), - .wd (doorbell_c119_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c119.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c119_preserve_mask_qs) - ); - - - // R[completion_interrupt_c119]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c119_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c119_intr_we), - .wd (completion_interrupt_c119_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c119.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c119_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c119_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c119_preserve_mask_we), - .wd (completion_interrupt_c119_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c119.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c119_preserve_mask_qs) - ); - - - // R[reserved_1_c120]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c120 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c120_we), - .wd (reserved_1_c120_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c120_qs) - ); - - - // R[channel_status_c120]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c120_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c120_channel_free_we), - .wd (channel_status_c120_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c120_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c120_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c120_channel_error_we), - .wd (channel_status_c120_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c120_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c120_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c120_field1_we), - .wd (channel_status_c120_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c120_field1_qs) - ); - - - // R[reserved_2_c120]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c120 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c120_we), - .wd (reserved_2_c120_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c120_qs) - ); - - - // R[reserved_3_c120]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c120 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c120]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c120_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c120_intr_enable_we), - .wd (channel_flags_c120_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c120_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c120_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c120_field1_we), - .wd (channel_flags_c120_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c120_field1_qs) - ); - - - // R[length_c120]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c120 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c120_we), - .wd (length_c120_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c120_qs) - ); - - - // R[message_header_c120]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c120_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c120_message_id_we), - .wd (message_header_c120_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c120_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c120_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c120_message_type_we), - .wd (message_header_c120_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c120_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c120_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c120_protocol_id_we), - .wd (message_header_c120_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c120_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c120_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c120_token_we), - .wd (message_header_c120_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c120_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c120_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c120_field1_we), - .wd (message_header_c120_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c120_field1_qs) - ); - - - // R[message_payload_1_c120]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c120 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c120_we), - .wd (message_payload_1_c120_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c120_qs) - ); - - - // R[doorbell_c120]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c120_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c120_intr_we), - .wd (doorbell_c120_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c120.intr.q ), - - // to register interface (read) - .qs (doorbell_c120_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c120_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c120_preserve_mask_we), - .wd (doorbell_c120_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c120.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c120_preserve_mask_qs) - ); - - - // R[completion_interrupt_c120]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c120_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c120_intr_we), - .wd (completion_interrupt_c120_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c120.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c120_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c120_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c120_preserve_mask_we), - .wd (completion_interrupt_c120_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c120.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c120_preserve_mask_qs) - ); - - - // R[reserved_1_c121]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c121 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c121_we), - .wd (reserved_1_c121_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c121_qs) - ); - - - // R[channel_status_c121]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c121_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c121_channel_free_we), - .wd (channel_status_c121_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c121_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c121_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c121_channel_error_we), - .wd (channel_status_c121_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c121_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c121_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c121_field1_we), - .wd (channel_status_c121_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c121_field1_qs) - ); - - - // R[reserved_2_c121]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c121 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c121_we), - .wd (reserved_2_c121_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c121_qs) - ); - - - // R[reserved_3_c121]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c121 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c121]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c121_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c121_intr_enable_we), - .wd (channel_flags_c121_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c121_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c121_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c121_field1_we), - .wd (channel_flags_c121_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c121_field1_qs) - ); - - - // R[length_c121]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c121 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c121_we), - .wd (length_c121_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c121_qs) - ); - - - // R[message_header_c121]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c121_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c121_message_id_we), - .wd (message_header_c121_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c121_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c121_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c121_message_type_we), - .wd (message_header_c121_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c121_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c121_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c121_protocol_id_we), - .wd (message_header_c121_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c121_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c121_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c121_token_we), - .wd (message_header_c121_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c121_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c121_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c121_field1_we), - .wd (message_header_c121_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c121_field1_qs) - ); - - - // R[message_payload_1_c121]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c121 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c121_we), - .wd (message_payload_1_c121_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c121_qs) - ); - - - // R[doorbell_c121]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c121_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c121_intr_we), - .wd (doorbell_c121_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c121.intr.q ), - - // to register interface (read) - .qs (doorbell_c121_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c121_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c121_preserve_mask_we), - .wd (doorbell_c121_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c121.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c121_preserve_mask_qs) - ); - - - // R[completion_interrupt_c121]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c121_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c121_intr_we), - .wd (completion_interrupt_c121_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c121.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c121_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c121_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c121_preserve_mask_we), - .wd (completion_interrupt_c121_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c121.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c121_preserve_mask_qs) - ); - - - // R[reserved_1_c122]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c122 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c122_we), - .wd (reserved_1_c122_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c122_qs) - ); - - - // R[channel_status_c122]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c122_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c122_channel_free_we), - .wd (channel_status_c122_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c122_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c122_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c122_channel_error_we), - .wd (channel_status_c122_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c122_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c122_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c122_field1_we), - .wd (channel_status_c122_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c122_field1_qs) - ); - - - // R[reserved_2_c122]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c122 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c122_we), - .wd (reserved_2_c122_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c122_qs) - ); - - - // R[reserved_3_c122]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c122 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c122]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c122_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c122_intr_enable_we), - .wd (channel_flags_c122_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c122_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c122_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c122_field1_we), - .wd (channel_flags_c122_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c122_field1_qs) - ); - - - // R[length_c122]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c122 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c122_we), - .wd (length_c122_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c122_qs) - ); - - - // R[message_header_c122]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c122_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c122_message_id_we), - .wd (message_header_c122_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c122_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c122_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c122_message_type_we), - .wd (message_header_c122_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c122_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c122_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c122_protocol_id_we), - .wd (message_header_c122_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c122_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c122_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c122_token_we), - .wd (message_header_c122_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c122_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c122_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c122_field1_we), - .wd (message_header_c122_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c122_field1_qs) - ); - - - // R[message_payload_1_c122]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c122 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c122_we), - .wd (message_payload_1_c122_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c122_qs) - ); - - - // R[doorbell_c122]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c122_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c122_intr_we), - .wd (doorbell_c122_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c122.intr.q ), - - // to register interface (read) - .qs (doorbell_c122_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c122_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c122_preserve_mask_we), - .wd (doorbell_c122_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c122.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c122_preserve_mask_qs) - ); - - - // R[completion_interrupt_c122]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c122_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c122_intr_we), - .wd (completion_interrupt_c122_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c122.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c122_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c122_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c122_preserve_mask_we), - .wd (completion_interrupt_c122_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c122.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c122_preserve_mask_qs) - ); - - - // R[reserved_1_c123]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c123 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c123_we), - .wd (reserved_1_c123_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c123_qs) - ); - - - // R[channel_status_c123]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c123_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c123_channel_free_we), - .wd (channel_status_c123_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c123_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c123_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c123_channel_error_we), - .wd (channel_status_c123_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c123_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c123_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c123_field1_we), - .wd (channel_status_c123_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c123_field1_qs) - ); - - - // R[reserved_2_c123]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c123 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c123_we), - .wd (reserved_2_c123_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c123_qs) - ); - - - // R[reserved_3_c123]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c123 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c123]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c123_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c123_intr_enable_we), - .wd (channel_flags_c123_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c123_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c123_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c123_field1_we), - .wd (channel_flags_c123_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c123_field1_qs) - ); - - - // R[length_c123]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c123 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c123_we), - .wd (length_c123_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c123_qs) - ); - - - // R[message_header_c123]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c123_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c123_message_id_we), - .wd (message_header_c123_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c123_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c123_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c123_message_type_we), - .wd (message_header_c123_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c123_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c123_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c123_protocol_id_we), - .wd (message_header_c123_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c123_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c123_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c123_token_we), - .wd (message_header_c123_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c123_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c123_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c123_field1_we), - .wd (message_header_c123_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c123_field1_qs) - ); - - - // R[message_payload_1_c123]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c123 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c123_we), - .wd (message_payload_1_c123_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c123_qs) - ); - - - // R[doorbell_c123]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c123_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c123_intr_we), - .wd (doorbell_c123_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c123.intr.q ), - - // to register interface (read) - .qs (doorbell_c123_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c123_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c123_preserve_mask_we), - .wd (doorbell_c123_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c123.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c123_preserve_mask_qs) - ); - - - // R[completion_interrupt_c123]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c123_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c123_intr_we), - .wd (completion_interrupt_c123_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c123.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c123_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c123_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c123_preserve_mask_we), - .wd (completion_interrupt_c123_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c123.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c123_preserve_mask_qs) - ); - - - // R[reserved_1_c124]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c124 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c124_we), - .wd (reserved_1_c124_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c124_qs) - ); - - - // R[channel_status_c124]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c124_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c124_channel_free_we), - .wd (channel_status_c124_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c124_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c124_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c124_channel_error_we), - .wd (channel_status_c124_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c124_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c124_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c124_field1_we), - .wd (channel_status_c124_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c124_field1_qs) - ); - - - // R[reserved_2_c124]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c124 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c124_we), - .wd (reserved_2_c124_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c124_qs) - ); - - - // R[reserved_3_c124]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c124 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c124]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c124_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c124_intr_enable_we), - .wd (channel_flags_c124_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c124_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c124_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c124_field1_we), - .wd (channel_flags_c124_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c124_field1_qs) - ); - - - // R[length_c124]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c124 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c124_we), - .wd (length_c124_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c124_qs) - ); - - - // R[message_header_c124]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c124_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c124_message_id_we), - .wd (message_header_c124_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c124_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c124_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c124_message_type_we), - .wd (message_header_c124_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c124_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c124_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c124_protocol_id_we), - .wd (message_header_c124_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c124_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c124_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c124_token_we), - .wd (message_header_c124_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c124_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c124_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c124_field1_we), - .wd (message_header_c124_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c124_field1_qs) - ); - - - // R[message_payload_1_c124]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c124 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c124_we), - .wd (message_payload_1_c124_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c124_qs) - ); - - - // R[doorbell_c124]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c124_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c124_intr_we), - .wd (doorbell_c124_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c124.intr.q ), - - // to register interface (read) - .qs (doorbell_c124_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c124_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c124_preserve_mask_we), - .wd (doorbell_c124_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c124.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c124_preserve_mask_qs) - ); - - - // R[completion_interrupt_c124]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c124_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c124_intr_we), - .wd (completion_interrupt_c124_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c124.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c124_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c124_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c124_preserve_mask_we), - .wd (completion_interrupt_c124_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c124.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c124_preserve_mask_qs) - ); - - - // R[reserved_1_c125]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c125 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c125_we), - .wd (reserved_1_c125_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c125_qs) - ); - - - // R[channel_status_c125]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c125_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c125_channel_free_we), - .wd (channel_status_c125_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c125_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c125_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c125_channel_error_we), - .wd (channel_status_c125_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c125_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c125_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c125_field1_we), - .wd (channel_status_c125_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c125_field1_qs) - ); - - - // R[reserved_2_c125]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c125 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c125_we), - .wd (reserved_2_c125_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c125_qs) - ); - - - // R[reserved_3_c125]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c125 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c125]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c125_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c125_intr_enable_we), - .wd (channel_flags_c125_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c125_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c125_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c125_field1_we), - .wd (channel_flags_c125_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c125_field1_qs) - ); - - - // R[length_c125]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c125 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c125_we), - .wd (length_c125_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c125_qs) - ); - - - // R[message_header_c125]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c125_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c125_message_id_we), - .wd (message_header_c125_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c125_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c125_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c125_message_type_we), - .wd (message_header_c125_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c125_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c125_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c125_protocol_id_we), - .wd (message_header_c125_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c125_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c125_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c125_token_we), - .wd (message_header_c125_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c125_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c125_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c125_field1_we), - .wd (message_header_c125_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c125_field1_qs) - ); - - - // R[message_payload_1_c125]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c125 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c125_we), - .wd (message_payload_1_c125_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c125_qs) - ); - - - // R[doorbell_c125]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c125_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c125_intr_we), - .wd (doorbell_c125_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c125.intr.q ), - - // to register interface (read) - .qs (doorbell_c125_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c125_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c125_preserve_mask_we), - .wd (doorbell_c125_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c125.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c125_preserve_mask_qs) - ); - - - // R[completion_interrupt_c125]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c125_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c125_intr_we), - .wd (completion_interrupt_c125_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c125.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c125_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c125_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c125_preserve_mask_we), - .wd (completion_interrupt_c125_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c125.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c125_preserve_mask_qs) - ); - - - // R[reserved_1_c126]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c126 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c126_we), - .wd (reserved_1_c126_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c126_qs) - ); - - - // R[channel_status_c126]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c126_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c126_channel_free_we), - .wd (channel_status_c126_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c126_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c126_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c126_channel_error_we), - .wd (channel_status_c126_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c126_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c126_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c126_field1_we), - .wd (channel_status_c126_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c126_field1_qs) - ); - - - // R[reserved_2_c126]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c126 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c126_we), - .wd (reserved_2_c126_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c126_qs) - ); - - - // R[reserved_3_c126]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c126 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c126]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c126_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c126_intr_enable_we), - .wd (channel_flags_c126_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c126_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c126_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c126_field1_we), - .wd (channel_flags_c126_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c126_field1_qs) - ); - - - // R[length_c126]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c126 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c126_we), - .wd (length_c126_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c126_qs) - ); - - - // R[message_header_c126]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c126_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c126_message_id_we), - .wd (message_header_c126_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c126_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c126_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c126_message_type_we), - .wd (message_header_c126_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c126_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c126_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c126_protocol_id_we), - .wd (message_header_c126_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c126_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c126_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c126_token_we), - .wd (message_header_c126_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c126_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c126_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c126_field1_we), - .wd (message_header_c126_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c126_field1_qs) - ); - - - // R[message_payload_1_c126]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c126 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c126_we), - .wd (message_payload_1_c126_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c126_qs) - ); - - - // R[doorbell_c126]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c126_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c126_intr_we), - .wd (doorbell_c126_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c126.intr.q ), - - // to register interface (read) - .qs (doorbell_c126_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c126_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c126_preserve_mask_we), - .wd (doorbell_c126_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c126.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c126_preserve_mask_qs) - ); - - - // R[completion_interrupt_c126]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c126_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c126_intr_we), - .wd (completion_interrupt_c126_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c126.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c126_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c126_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c126_preserve_mask_we), - .wd (completion_interrupt_c126_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c126.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c126_preserve_mask_qs) - ); - - - // R[reserved_1_c127]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c127 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c127_we), - .wd (reserved_1_c127_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c127_qs) - ); - - - // R[channel_status_c127]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c127_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c127_channel_free_we), - .wd (channel_status_c127_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c127_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c127_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c127_channel_error_we), - .wd (channel_status_c127_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c127_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c127_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c127_field1_we), - .wd (channel_status_c127_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c127_field1_qs) - ); - - - // R[reserved_2_c127]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c127 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c127_we), - .wd (reserved_2_c127_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c127_qs) - ); - - - // R[reserved_3_c127]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c127 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c127]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c127_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c127_intr_enable_we), - .wd (channel_flags_c127_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c127_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c127_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c127_field1_we), - .wd (channel_flags_c127_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c127_field1_qs) - ); - - - // R[length_c127]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c127 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c127_we), - .wd (length_c127_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c127_qs) - ); - - - // R[message_header_c127]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c127_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c127_message_id_we), - .wd (message_header_c127_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c127_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c127_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c127_message_type_we), - .wd (message_header_c127_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c127_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c127_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c127_protocol_id_we), - .wd (message_header_c127_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c127_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c127_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c127_token_we), - .wd (message_header_c127_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c127_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c127_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c127_field1_we), - .wd (message_header_c127_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c127_field1_qs) - ); - - - // R[message_payload_1_c127]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c127 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c127_we), - .wd (message_payload_1_c127_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c127_qs) - ); - - - // R[doorbell_c127]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c127_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c127_intr_we), - .wd (doorbell_c127_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c127.intr.q ), - - // to register interface (read) - .qs (doorbell_c127_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c127_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c127_preserve_mask_we), - .wd (doorbell_c127_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c127.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c127_preserve_mask_qs) - ); - - - // R[completion_interrupt_c127]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c127_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c127_intr_we), - .wd (completion_interrupt_c127_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c127.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c127_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c127_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c127_preserve_mask_we), - .wd (completion_interrupt_c127_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c127.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c127_preserve_mask_qs) - ); - - - // R[reserved_1_c128]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c128 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c128_we), - .wd (reserved_1_c128_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c128_qs) - ); - - - // R[channel_status_c128]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c128_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c128_channel_free_we), - .wd (channel_status_c128_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c128_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c128_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c128_channel_error_we), - .wd (channel_status_c128_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c128_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c128_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c128_field1_we), - .wd (channel_status_c128_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c128_field1_qs) - ); - - - // R[reserved_2_c128]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c128 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c128_we), - .wd (reserved_2_c128_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c128_qs) - ); - - - // R[reserved_3_c128]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c128 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c128]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c128_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c128_intr_enable_we), - .wd (channel_flags_c128_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c128_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c128_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c128_field1_we), - .wd (channel_flags_c128_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c128_field1_qs) - ); - - - // R[length_c128]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c128 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c128_we), - .wd (length_c128_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c128_qs) - ); - - - // R[message_header_c128]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c128_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c128_message_id_we), - .wd (message_header_c128_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c128_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c128_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c128_message_type_we), - .wd (message_header_c128_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c128_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c128_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c128_protocol_id_we), - .wd (message_header_c128_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c128_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c128_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c128_token_we), - .wd (message_header_c128_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c128_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c128_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c128_field1_we), - .wd (message_header_c128_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c128_field1_qs) - ); - - - // R[message_payload_1_c128]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c128 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c128_we), - .wd (message_payload_1_c128_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c128_qs) - ); - - - // R[doorbell_c128]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c128_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c128_intr_we), - .wd (doorbell_c128_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c128.intr.q ), - - // to register interface (read) - .qs (doorbell_c128_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c128_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c128_preserve_mask_we), - .wd (doorbell_c128_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c128.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c128_preserve_mask_qs) - ); - - - // R[completion_interrupt_c128]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c128_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c128_intr_we), - .wd (completion_interrupt_c128_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c128.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c128_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c128_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c128_preserve_mask_we), - .wd (completion_interrupt_c128_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c128.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c128_preserve_mask_qs) - ); - - - // R[reserved_1_c129]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c129 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c129_we), - .wd (reserved_1_c129_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c129_qs) - ); - - - // R[channel_status_c129]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c129_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c129_channel_free_we), - .wd (channel_status_c129_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c129_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c129_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c129_channel_error_we), - .wd (channel_status_c129_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c129_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c129_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c129_field1_we), - .wd (channel_status_c129_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c129_field1_qs) - ); - - - // R[reserved_2_c129]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c129 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c129_we), - .wd (reserved_2_c129_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c129_qs) - ); - - - // R[reserved_3_c129]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c129 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c129]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c129_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c129_intr_enable_we), - .wd (channel_flags_c129_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c129_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c129_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c129_field1_we), - .wd (channel_flags_c129_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c129_field1_qs) - ); - - - // R[length_c129]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c129 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c129_we), - .wd (length_c129_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c129_qs) - ); - - - // R[message_header_c129]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c129_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c129_message_id_we), - .wd (message_header_c129_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c129_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c129_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c129_message_type_we), - .wd (message_header_c129_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c129_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c129_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c129_protocol_id_we), - .wd (message_header_c129_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c129_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c129_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c129_token_we), - .wd (message_header_c129_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c129_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c129_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c129_field1_we), - .wd (message_header_c129_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c129_field1_qs) - ); - - - // R[message_payload_1_c129]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c129 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c129_we), - .wd (message_payload_1_c129_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c129_qs) - ); - - - // R[doorbell_c129]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c129_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c129_intr_we), - .wd (doorbell_c129_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c129.intr.q ), - - // to register interface (read) - .qs (doorbell_c129_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c129_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c129_preserve_mask_we), - .wd (doorbell_c129_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c129.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c129_preserve_mask_qs) - ); - - - // R[completion_interrupt_c129]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c129_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c129_intr_we), - .wd (completion_interrupt_c129_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c129.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c129_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c129_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c129_preserve_mask_we), - .wd (completion_interrupt_c129_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c129.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c129_preserve_mask_qs) - ); - - - // R[reserved_1_c130]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c130 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c130_we), - .wd (reserved_1_c130_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c130_qs) - ); - - - // R[channel_status_c130]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c130_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c130_channel_free_we), - .wd (channel_status_c130_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c130_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c130_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c130_channel_error_we), - .wd (channel_status_c130_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c130_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c130_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c130_field1_we), - .wd (channel_status_c130_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c130_field1_qs) - ); - - - // R[reserved_2_c130]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c130 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c130_we), - .wd (reserved_2_c130_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c130_qs) - ); - - - // R[reserved_3_c130]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c130 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c130]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c130_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c130_intr_enable_we), - .wd (channel_flags_c130_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c130_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c130_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c130_field1_we), - .wd (channel_flags_c130_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c130_field1_qs) - ); - - - // R[length_c130]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c130 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c130_we), - .wd (length_c130_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c130_qs) - ); - - - // R[message_header_c130]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c130_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c130_message_id_we), - .wd (message_header_c130_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c130_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c130_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c130_message_type_we), - .wd (message_header_c130_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c130_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c130_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c130_protocol_id_we), - .wd (message_header_c130_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c130_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c130_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c130_token_we), - .wd (message_header_c130_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c130_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c130_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c130_field1_we), - .wd (message_header_c130_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c130_field1_qs) - ); - - - // R[message_payload_1_c130]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c130 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c130_we), - .wd (message_payload_1_c130_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c130_qs) - ); - - - // R[doorbell_c130]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c130_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c130_intr_we), - .wd (doorbell_c130_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c130.intr.q ), - - // to register interface (read) - .qs (doorbell_c130_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c130_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c130_preserve_mask_we), - .wd (doorbell_c130_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c130.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c130_preserve_mask_qs) - ); - - - // R[completion_interrupt_c130]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c130_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c130_intr_we), - .wd (completion_interrupt_c130_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c130.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c130_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c130_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c130_preserve_mask_we), - .wd (completion_interrupt_c130_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c130.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c130_preserve_mask_qs) - ); - - - // R[reserved_1_c131]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c131 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c131_we), - .wd (reserved_1_c131_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c131_qs) - ); - - - // R[channel_status_c131]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c131_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c131_channel_free_we), - .wd (channel_status_c131_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c131_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c131_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c131_channel_error_we), - .wd (channel_status_c131_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c131_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c131_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c131_field1_we), - .wd (channel_status_c131_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c131_field1_qs) - ); - - - // R[reserved_2_c131]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c131 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c131_we), - .wd (reserved_2_c131_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c131_qs) - ); - - - // R[reserved_3_c131]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c131 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c131]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c131_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c131_intr_enable_we), - .wd (channel_flags_c131_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c131_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c131_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c131_field1_we), - .wd (channel_flags_c131_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c131_field1_qs) - ); - - - // R[length_c131]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c131 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c131_we), - .wd (length_c131_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c131_qs) - ); - - - // R[message_header_c131]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c131_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c131_message_id_we), - .wd (message_header_c131_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c131_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c131_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c131_message_type_we), - .wd (message_header_c131_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c131_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c131_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c131_protocol_id_we), - .wd (message_header_c131_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c131_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c131_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c131_token_we), - .wd (message_header_c131_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c131_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c131_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c131_field1_we), - .wd (message_header_c131_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c131_field1_qs) - ); - - - // R[message_payload_1_c131]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c131 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c131_we), - .wd (message_payload_1_c131_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c131_qs) - ); - - - // R[doorbell_c131]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c131_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c131_intr_we), - .wd (doorbell_c131_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c131.intr.q ), - - // to register interface (read) - .qs (doorbell_c131_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c131_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c131_preserve_mask_we), - .wd (doorbell_c131_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c131.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c131_preserve_mask_qs) - ); - - - // R[completion_interrupt_c131]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c131_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c131_intr_we), - .wd (completion_interrupt_c131_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c131.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c131_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c131_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c131_preserve_mask_we), - .wd (completion_interrupt_c131_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c131.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c131_preserve_mask_qs) - ); - - - // R[reserved_1_c132]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c132 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c132_we), - .wd (reserved_1_c132_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c132_qs) - ); - - - // R[channel_status_c132]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c132_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c132_channel_free_we), - .wd (channel_status_c132_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c132_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c132_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c132_channel_error_we), - .wd (channel_status_c132_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c132_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c132_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c132_field1_we), - .wd (channel_status_c132_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c132_field1_qs) - ); - - - // R[reserved_2_c132]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c132 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c132_we), - .wd (reserved_2_c132_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c132_qs) - ); - - - // R[reserved_3_c132]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c132 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c132]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c132_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c132_intr_enable_we), - .wd (channel_flags_c132_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c132_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c132_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c132_field1_we), - .wd (channel_flags_c132_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c132_field1_qs) - ); - - - // R[length_c132]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c132 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c132_we), - .wd (length_c132_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c132_qs) - ); - - - // R[message_header_c132]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c132_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c132_message_id_we), - .wd (message_header_c132_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c132_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c132_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c132_message_type_we), - .wd (message_header_c132_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c132_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c132_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c132_protocol_id_we), - .wd (message_header_c132_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c132_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c132_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c132_token_we), - .wd (message_header_c132_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c132_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c132_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c132_field1_we), - .wd (message_header_c132_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c132_field1_qs) - ); - - - // R[message_payload_1_c132]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c132 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c132_we), - .wd (message_payload_1_c132_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c132_qs) - ); - - - // R[doorbell_c132]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c132_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c132_intr_we), - .wd (doorbell_c132_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c132.intr.q ), - - // to register interface (read) - .qs (doorbell_c132_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c132_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c132_preserve_mask_we), - .wd (doorbell_c132_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c132.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c132_preserve_mask_qs) - ); - - - // R[completion_interrupt_c132]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c132_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c132_intr_we), - .wd (completion_interrupt_c132_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c132.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c132_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c132_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c132_preserve_mask_we), - .wd (completion_interrupt_c132_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c132.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c132_preserve_mask_qs) - ); - - - // R[reserved_1_c133]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c133 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c133_we), - .wd (reserved_1_c133_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c133_qs) - ); - - - // R[channel_status_c133]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c133_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c133_channel_free_we), - .wd (channel_status_c133_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c133_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c133_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c133_channel_error_we), - .wd (channel_status_c133_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c133_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c133_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c133_field1_we), - .wd (channel_status_c133_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c133_field1_qs) - ); - - - // R[reserved_2_c133]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c133 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c133_we), - .wd (reserved_2_c133_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c133_qs) - ); - - - // R[reserved_3_c133]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c133 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c133]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c133_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c133_intr_enable_we), - .wd (channel_flags_c133_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c133_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c133_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c133_field1_we), - .wd (channel_flags_c133_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c133_field1_qs) - ); - - - // R[length_c133]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c133 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c133_we), - .wd (length_c133_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c133_qs) - ); - - - // R[message_header_c133]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c133_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c133_message_id_we), - .wd (message_header_c133_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c133_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c133_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c133_message_type_we), - .wd (message_header_c133_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c133_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c133_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c133_protocol_id_we), - .wd (message_header_c133_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c133_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c133_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c133_token_we), - .wd (message_header_c133_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c133_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c133_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c133_field1_we), - .wd (message_header_c133_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c133_field1_qs) - ); - - - // R[message_payload_1_c133]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c133 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c133_we), - .wd (message_payload_1_c133_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c133_qs) - ); - - - // R[doorbell_c133]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c133_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c133_intr_we), - .wd (doorbell_c133_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c133.intr.q ), - - // to register interface (read) - .qs (doorbell_c133_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c133_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c133_preserve_mask_we), - .wd (doorbell_c133_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c133.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c133_preserve_mask_qs) - ); - - - // R[completion_interrupt_c133]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c133_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c133_intr_we), - .wd (completion_interrupt_c133_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c133.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c133_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c133_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c133_preserve_mask_we), - .wd (completion_interrupt_c133_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c133.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c133_preserve_mask_qs) - ); - - - // R[reserved_1_c134]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c134 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c134_we), - .wd (reserved_1_c134_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c134_qs) - ); - - - // R[channel_status_c134]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c134_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c134_channel_free_we), - .wd (channel_status_c134_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c134_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c134_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c134_channel_error_we), - .wd (channel_status_c134_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c134_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c134_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c134_field1_we), - .wd (channel_status_c134_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c134_field1_qs) - ); - - - // R[reserved_2_c134]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c134 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c134_we), - .wd (reserved_2_c134_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c134_qs) - ); - - - // R[reserved_3_c134]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c134 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c134]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c134_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c134_intr_enable_we), - .wd (channel_flags_c134_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c134_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c134_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c134_field1_we), - .wd (channel_flags_c134_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c134_field1_qs) - ); - - - // R[length_c134]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c134 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c134_we), - .wd (length_c134_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c134_qs) - ); - - - // R[message_header_c134]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c134_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c134_message_id_we), - .wd (message_header_c134_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c134_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c134_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c134_message_type_we), - .wd (message_header_c134_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c134_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c134_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c134_protocol_id_we), - .wd (message_header_c134_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c134_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c134_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c134_token_we), - .wd (message_header_c134_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c134_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c134_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c134_field1_we), - .wd (message_header_c134_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c134_field1_qs) - ); - - - // R[message_payload_1_c134]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c134 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c134_we), - .wd (message_payload_1_c134_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c134_qs) - ); - - - // R[doorbell_c134]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c134_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c134_intr_we), - .wd (doorbell_c134_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c134.intr.q ), - - // to register interface (read) - .qs (doorbell_c134_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c134_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c134_preserve_mask_we), - .wd (doorbell_c134_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c134.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c134_preserve_mask_qs) - ); - - - // R[completion_interrupt_c134]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c134_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c134_intr_we), - .wd (completion_interrupt_c134_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c134.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c134_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c134_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c134_preserve_mask_we), - .wd (completion_interrupt_c134_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c134.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c134_preserve_mask_qs) - ); - - - // R[reserved_1_c135]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c135 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c135_we), - .wd (reserved_1_c135_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c135_qs) - ); - - - // R[channel_status_c135]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c135_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c135_channel_free_we), - .wd (channel_status_c135_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c135_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c135_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c135_channel_error_we), - .wd (channel_status_c135_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c135_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c135_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c135_field1_we), - .wd (channel_status_c135_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c135_field1_qs) - ); - - - // R[reserved_2_c135]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c135 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c135_we), - .wd (reserved_2_c135_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c135_qs) - ); - - - // R[reserved_3_c135]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c135 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c135]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c135_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c135_intr_enable_we), - .wd (channel_flags_c135_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c135_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c135_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c135_field1_we), - .wd (channel_flags_c135_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c135_field1_qs) - ); - - - // R[length_c135]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c135 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c135_we), - .wd (length_c135_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c135_qs) - ); - - - // R[message_header_c135]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c135_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c135_message_id_we), - .wd (message_header_c135_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c135_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c135_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c135_message_type_we), - .wd (message_header_c135_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c135_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c135_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c135_protocol_id_we), - .wd (message_header_c135_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c135_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c135_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c135_token_we), - .wd (message_header_c135_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c135_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c135_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c135_field1_we), - .wd (message_header_c135_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c135_field1_qs) - ); - - - // R[message_payload_1_c135]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c135 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c135_we), - .wd (message_payload_1_c135_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c135_qs) - ); - - - // R[doorbell_c135]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c135_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c135_intr_we), - .wd (doorbell_c135_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c135.intr.q ), - - // to register interface (read) - .qs (doorbell_c135_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c135_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c135_preserve_mask_we), - .wd (doorbell_c135_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c135.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c135_preserve_mask_qs) - ); - - - // R[completion_interrupt_c135]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c135_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c135_intr_we), - .wd (completion_interrupt_c135_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c135.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c135_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c135_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c135_preserve_mask_we), - .wd (completion_interrupt_c135_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c135.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c135_preserve_mask_qs) - ); - - - // R[reserved_1_c136]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c136 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c136_we), - .wd (reserved_1_c136_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c136_qs) - ); - - - // R[channel_status_c136]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c136_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c136_channel_free_we), - .wd (channel_status_c136_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c136_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c136_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c136_channel_error_we), - .wd (channel_status_c136_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c136_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c136_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c136_field1_we), - .wd (channel_status_c136_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c136_field1_qs) - ); - - - // R[reserved_2_c136]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c136 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c136_we), - .wd (reserved_2_c136_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c136_qs) - ); - - - // R[reserved_3_c136]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c136 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c136]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c136_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c136_intr_enable_we), - .wd (channel_flags_c136_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c136_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c136_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c136_field1_we), - .wd (channel_flags_c136_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c136_field1_qs) - ); - - - // R[length_c136]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c136 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c136_we), - .wd (length_c136_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c136_qs) - ); - - - // R[message_header_c136]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c136_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c136_message_id_we), - .wd (message_header_c136_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c136_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c136_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c136_message_type_we), - .wd (message_header_c136_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c136_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c136_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c136_protocol_id_we), - .wd (message_header_c136_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c136_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c136_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c136_token_we), - .wd (message_header_c136_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c136_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c136_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c136_field1_we), - .wd (message_header_c136_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c136_field1_qs) - ); - - - // R[message_payload_1_c136]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c136 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c136_we), - .wd (message_payload_1_c136_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c136_qs) - ); - - - // R[doorbell_c136]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c136_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c136_intr_we), - .wd (doorbell_c136_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c136.intr.q ), - - // to register interface (read) - .qs (doorbell_c136_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c136_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c136_preserve_mask_we), - .wd (doorbell_c136_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c136.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c136_preserve_mask_qs) - ); - - - // R[completion_interrupt_c136]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c136_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c136_intr_we), - .wd (completion_interrupt_c136_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c136.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c136_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c136_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c136_preserve_mask_we), - .wd (completion_interrupt_c136_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c136.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c136_preserve_mask_qs) - ); - - - // R[reserved_1_c137]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c137 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c137_we), - .wd (reserved_1_c137_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c137_qs) - ); - - - // R[channel_status_c137]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c137_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c137_channel_free_we), - .wd (channel_status_c137_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c137_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c137_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c137_channel_error_we), - .wd (channel_status_c137_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c137_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c137_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c137_field1_we), - .wd (channel_status_c137_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c137_field1_qs) - ); - - - // R[reserved_2_c137]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c137 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c137_we), - .wd (reserved_2_c137_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c137_qs) - ); - - - // R[reserved_3_c137]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c137 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c137]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c137_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c137_intr_enable_we), - .wd (channel_flags_c137_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c137_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c137_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c137_field1_we), - .wd (channel_flags_c137_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c137_field1_qs) - ); - - - // R[length_c137]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c137 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c137_we), - .wd (length_c137_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c137_qs) - ); - - - // R[message_header_c137]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c137_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c137_message_id_we), - .wd (message_header_c137_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c137_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c137_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c137_message_type_we), - .wd (message_header_c137_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c137_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c137_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c137_protocol_id_we), - .wd (message_header_c137_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c137_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c137_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c137_token_we), - .wd (message_header_c137_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c137_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c137_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c137_field1_we), - .wd (message_header_c137_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c137_field1_qs) - ); - - - // R[message_payload_1_c137]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c137 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c137_we), - .wd (message_payload_1_c137_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c137_qs) - ); - - - // R[doorbell_c137]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c137_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c137_intr_we), - .wd (doorbell_c137_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c137.intr.q ), - - // to register interface (read) - .qs (doorbell_c137_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c137_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c137_preserve_mask_we), - .wd (doorbell_c137_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c137.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c137_preserve_mask_qs) - ); - - - // R[completion_interrupt_c137]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c137_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c137_intr_we), - .wd (completion_interrupt_c137_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c137.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c137_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c137_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c137_preserve_mask_we), - .wd (completion_interrupt_c137_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c137.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c137_preserve_mask_qs) - ); - - - // R[reserved_1_c138]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c138 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c138_we), - .wd (reserved_1_c138_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c138_qs) - ); - - - // R[channel_status_c138]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c138_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c138_channel_free_we), - .wd (channel_status_c138_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c138_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c138_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c138_channel_error_we), - .wd (channel_status_c138_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c138_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c138_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c138_field1_we), - .wd (channel_status_c138_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c138_field1_qs) - ); - - - // R[reserved_2_c138]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c138 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c138_we), - .wd (reserved_2_c138_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c138_qs) - ); - - - // R[reserved_3_c138]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c138 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c138]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c138_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c138_intr_enable_we), - .wd (channel_flags_c138_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c138_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c138_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c138_field1_we), - .wd (channel_flags_c138_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c138_field1_qs) - ); - - - // R[length_c138]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c138 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c138_we), - .wd (length_c138_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c138_qs) - ); - - - // R[message_header_c138]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c138_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c138_message_id_we), - .wd (message_header_c138_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c138_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c138_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c138_message_type_we), - .wd (message_header_c138_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c138_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c138_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c138_protocol_id_we), - .wd (message_header_c138_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c138_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c138_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c138_token_we), - .wd (message_header_c138_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c138_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c138_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c138_field1_we), - .wd (message_header_c138_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c138_field1_qs) - ); - - - // R[message_payload_1_c138]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c138 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c138_we), - .wd (message_payload_1_c138_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c138_qs) - ); - - - // R[doorbell_c138]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c138_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c138_intr_we), - .wd (doorbell_c138_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c138.intr.q ), - - // to register interface (read) - .qs (doorbell_c138_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c138_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c138_preserve_mask_we), - .wd (doorbell_c138_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c138.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c138_preserve_mask_qs) - ); - - - // R[completion_interrupt_c138]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c138_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c138_intr_we), - .wd (completion_interrupt_c138_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c138.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c138_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c138_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c138_preserve_mask_we), - .wd (completion_interrupt_c138_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c138.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c138_preserve_mask_qs) - ); - - - // R[reserved_1_c139]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c139 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c139_we), - .wd (reserved_1_c139_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c139_qs) - ); - - - // R[channel_status_c139]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c139_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c139_channel_free_we), - .wd (channel_status_c139_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c139_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c139_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c139_channel_error_we), - .wd (channel_status_c139_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c139_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c139_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c139_field1_we), - .wd (channel_status_c139_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c139_field1_qs) - ); - - - // R[reserved_2_c139]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c139 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c139_we), - .wd (reserved_2_c139_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c139_qs) - ); - - - // R[reserved_3_c139]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c139 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c139]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c139_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c139_intr_enable_we), - .wd (channel_flags_c139_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c139_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c139_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c139_field1_we), - .wd (channel_flags_c139_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c139_field1_qs) - ); - - - // R[length_c139]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c139 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c139_we), - .wd (length_c139_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c139_qs) - ); - - - // R[message_header_c139]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c139_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c139_message_id_we), - .wd (message_header_c139_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c139_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c139_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c139_message_type_we), - .wd (message_header_c139_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c139_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c139_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c139_protocol_id_we), - .wd (message_header_c139_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c139_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c139_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c139_token_we), - .wd (message_header_c139_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c139_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c139_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c139_field1_we), - .wd (message_header_c139_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c139_field1_qs) - ); - - - // R[message_payload_1_c139]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c139 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c139_we), - .wd (message_payload_1_c139_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c139_qs) - ); - - - // R[doorbell_c139]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c139_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c139_intr_we), - .wd (doorbell_c139_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c139.intr.q ), - - // to register interface (read) - .qs (doorbell_c139_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c139_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c139_preserve_mask_we), - .wd (doorbell_c139_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c139.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c139_preserve_mask_qs) - ); - - - // R[completion_interrupt_c139]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c139_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c139_intr_we), - .wd (completion_interrupt_c139_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c139.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c139_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c139_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c139_preserve_mask_we), - .wd (completion_interrupt_c139_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c139.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c139_preserve_mask_qs) - ); - - - // R[reserved_1_c140]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c140 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c140_we), - .wd (reserved_1_c140_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c140_qs) - ); - - - // R[channel_status_c140]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c140_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c140_channel_free_we), - .wd (channel_status_c140_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c140_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c140_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c140_channel_error_we), - .wd (channel_status_c140_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c140_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c140_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c140_field1_we), - .wd (channel_status_c140_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c140_field1_qs) - ); - - - // R[reserved_2_c140]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c140 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c140_we), - .wd (reserved_2_c140_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c140_qs) - ); - - - // R[reserved_3_c140]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c140 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c140]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c140_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c140_intr_enable_we), - .wd (channel_flags_c140_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c140_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c140_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c140_field1_we), - .wd (channel_flags_c140_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c140_field1_qs) - ); - - - // R[length_c140]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c140 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c140_we), - .wd (length_c140_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c140_qs) - ); - - - // R[message_header_c140]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c140_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c140_message_id_we), - .wd (message_header_c140_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c140_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c140_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c140_message_type_we), - .wd (message_header_c140_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c140_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c140_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c140_protocol_id_we), - .wd (message_header_c140_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c140_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c140_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c140_token_we), - .wd (message_header_c140_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c140_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c140_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c140_field1_we), - .wd (message_header_c140_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c140_field1_qs) - ); - - - // R[message_payload_1_c140]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c140 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c140_we), - .wd (message_payload_1_c140_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c140_qs) - ); - - - // R[doorbell_c140]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c140_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c140_intr_we), - .wd (doorbell_c140_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c140.intr.q ), - - // to register interface (read) - .qs (doorbell_c140_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c140_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c140_preserve_mask_we), - .wd (doorbell_c140_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c140.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c140_preserve_mask_qs) - ); - - - // R[completion_interrupt_c140]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c140_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c140_intr_we), - .wd (completion_interrupt_c140_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c140.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c140_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c140_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c140_preserve_mask_we), - .wd (completion_interrupt_c140_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c140.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c140_preserve_mask_qs) - ); - - - // R[reserved_1_c141]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c141 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c141_we), - .wd (reserved_1_c141_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c141_qs) - ); - - - // R[channel_status_c141]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c141_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c141_channel_free_we), - .wd (channel_status_c141_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c141_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c141_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c141_channel_error_we), - .wd (channel_status_c141_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c141_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c141_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c141_field1_we), - .wd (channel_status_c141_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c141_field1_qs) - ); - - - // R[reserved_2_c141]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c141 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c141_we), - .wd (reserved_2_c141_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c141_qs) - ); - - - // R[reserved_3_c141]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c141 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c141]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c141_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c141_intr_enable_we), - .wd (channel_flags_c141_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c141_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c141_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c141_field1_we), - .wd (channel_flags_c141_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c141_field1_qs) - ); - - - // R[length_c141]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c141 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c141_we), - .wd (length_c141_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c141_qs) - ); - - - // R[message_header_c141]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c141_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c141_message_id_we), - .wd (message_header_c141_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c141_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c141_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c141_message_type_we), - .wd (message_header_c141_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c141_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c141_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c141_protocol_id_we), - .wd (message_header_c141_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c141_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c141_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c141_token_we), - .wd (message_header_c141_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c141_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c141_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c141_field1_we), - .wd (message_header_c141_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c141_field1_qs) - ); - - - // R[message_payload_1_c141]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c141 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c141_we), - .wd (message_payload_1_c141_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c141_qs) - ); - - - // R[doorbell_c141]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c141_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c141_intr_we), - .wd (doorbell_c141_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c141.intr.q ), - - // to register interface (read) - .qs (doorbell_c141_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c141_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c141_preserve_mask_we), - .wd (doorbell_c141_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c141.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c141_preserve_mask_qs) - ); - - - // R[completion_interrupt_c141]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c141_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c141_intr_we), - .wd (completion_interrupt_c141_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c141.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c141_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c141_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c141_preserve_mask_we), - .wd (completion_interrupt_c141_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c141.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c141_preserve_mask_qs) - ); - - - // R[reserved_1_c142]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c142 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c142_we), - .wd (reserved_1_c142_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c142_qs) - ); - - - // R[channel_status_c142]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c142_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c142_channel_free_we), - .wd (channel_status_c142_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c142_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c142_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c142_channel_error_we), - .wd (channel_status_c142_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c142_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c142_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c142_field1_we), - .wd (channel_status_c142_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c142_field1_qs) - ); - - - // R[reserved_2_c142]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c142 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c142_we), - .wd (reserved_2_c142_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c142_qs) - ); - - - // R[reserved_3_c142]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c142 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c142]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c142_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c142_intr_enable_we), - .wd (channel_flags_c142_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c142_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c142_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c142_field1_we), - .wd (channel_flags_c142_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c142_field1_qs) - ); - - - // R[length_c142]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c142 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c142_we), - .wd (length_c142_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c142_qs) - ); - - - // R[message_header_c142]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c142_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c142_message_id_we), - .wd (message_header_c142_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c142_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c142_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c142_message_type_we), - .wd (message_header_c142_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c142_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c142_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c142_protocol_id_we), - .wd (message_header_c142_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c142_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c142_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c142_token_we), - .wd (message_header_c142_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c142_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c142_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c142_field1_we), - .wd (message_header_c142_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c142_field1_qs) - ); - - - // R[message_payload_1_c142]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c142 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c142_we), - .wd (message_payload_1_c142_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c142_qs) - ); - - - // R[doorbell_c142]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c142_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c142_intr_we), - .wd (doorbell_c142_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c142.intr.q ), - - // to register interface (read) - .qs (doorbell_c142_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c142_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c142_preserve_mask_we), - .wd (doorbell_c142_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c142.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c142_preserve_mask_qs) - ); - - - // R[completion_interrupt_c142]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c142_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c142_intr_we), - .wd (completion_interrupt_c142_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c142.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c142_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c142_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c142_preserve_mask_we), - .wd (completion_interrupt_c142_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c142.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c142_preserve_mask_qs) - ); - - - // R[reserved_1_c143]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c143 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c143_we), - .wd (reserved_1_c143_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c143_qs) - ); - - - // R[channel_status_c143]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c143_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c143_channel_free_we), - .wd (channel_status_c143_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c143_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c143_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c143_channel_error_we), - .wd (channel_status_c143_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c143_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c143_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c143_field1_we), - .wd (channel_status_c143_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c143_field1_qs) - ); - - - // R[reserved_2_c143]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c143 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c143_we), - .wd (reserved_2_c143_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c143_qs) - ); - - - // R[reserved_3_c143]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c143 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c143]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c143_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c143_intr_enable_we), - .wd (channel_flags_c143_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c143_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c143_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c143_field1_we), - .wd (channel_flags_c143_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c143_field1_qs) - ); - - - // R[length_c143]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c143 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c143_we), - .wd (length_c143_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c143_qs) - ); - - - // R[message_header_c143]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c143_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c143_message_id_we), - .wd (message_header_c143_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c143_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c143_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c143_message_type_we), - .wd (message_header_c143_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c143_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c143_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c143_protocol_id_we), - .wd (message_header_c143_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c143_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c143_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c143_token_we), - .wd (message_header_c143_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c143_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c143_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c143_field1_we), - .wd (message_header_c143_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c143_field1_qs) - ); - - - // R[message_payload_1_c143]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c143 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c143_we), - .wd (message_payload_1_c143_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c143_qs) - ); - - - // R[doorbell_c143]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c143_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c143_intr_we), - .wd (doorbell_c143_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c143.intr.q ), - - // to register interface (read) - .qs (doorbell_c143_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c143_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c143_preserve_mask_we), - .wd (doorbell_c143_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c143.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c143_preserve_mask_qs) - ); - - - // R[completion_interrupt_c143]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c143_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c143_intr_we), - .wd (completion_interrupt_c143_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c143.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c143_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c143_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c143_preserve_mask_we), - .wd (completion_interrupt_c143_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c143.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c143_preserve_mask_qs) - ); - - - // R[reserved_1_c144]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c144 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c144_we), - .wd (reserved_1_c144_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c144_qs) - ); - - - // R[channel_status_c144]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c144_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c144_channel_free_we), - .wd (channel_status_c144_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c144_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c144_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c144_channel_error_we), - .wd (channel_status_c144_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c144_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c144_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c144_field1_we), - .wd (channel_status_c144_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c144_field1_qs) - ); - - - // R[reserved_2_c144]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c144 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c144_we), - .wd (reserved_2_c144_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c144_qs) - ); - - - // R[reserved_3_c144]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c144 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c144]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c144_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c144_intr_enable_we), - .wd (channel_flags_c144_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c144_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c144_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c144_field1_we), - .wd (channel_flags_c144_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c144_field1_qs) - ); - - - // R[length_c144]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c144 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c144_we), - .wd (length_c144_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c144_qs) - ); - - - // R[message_header_c144]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c144_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c144_message_id_we), - .wd (message_header_c144_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c144_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c144_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c144_message_type_we), - .wd (message_header_c144_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c144_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c144_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c144_protocol_id_we), - .wd (message_header_c144_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c144_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c144_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c144_token_we), - .wd (message_header_c144_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c144_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c144_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c144_field1_we), - .wd (message_header_c144_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c144_field1_qs) - ); - - - // R[message_payload_1_c144]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c144 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c144_we), - .wd (message_payload_1_c144_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c144_qs) - ); - - - // R[doorbell_c144]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c144_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c144_intr_we), - .wd (doorbell_c144_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c144.intr.q ), - - // to register interface (read) - .qs (doorbell_c144_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c144_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c144_preserve_mask_we), - .wd (doorbell_c144_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c144.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c144_preserve_mask_qs) - ); - - - // R[completion_interrupt_c144]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c144_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c144_intr_we), - .wd (completion_interrupt_c144_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c144.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c144_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c144_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c144_preserve_mask_we), - .wd (completion_interrupt_c144_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c144.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c144_preserve_mask_qs) - ); - - - // R[reserved_1_c145]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c145 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c145_we), - .wd (reserved_1_c145_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c145_qs) - ); - - - // R[channel_status_c145]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c145_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c145_channel_free_we), - .wd (channel_status_c145_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c145_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c145_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c145_channel_error_we), - .wd (channel_status_c145_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c145_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c145_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c145_field1_we), - .wd (channel_status_c145_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c145_field1_qs) - ); - - - // R[reserved_2_c145]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c145 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c145_we), - .wd (reserved_2_c145_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c145_qs) - ); - - - // R[reserved_3_c145]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c145 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c145]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c145_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c145_intr_enable_we), - .wd (channel_flags_c145_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c145_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c145_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c145_field1_we), - .wd (channel_flags_c145_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c145_field1_qs) - ); - - - // R[length_c145]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c145 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c145_we), - .wd (length_c145_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c145_qs) - ); - - - // R[message_header_c145]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c145_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c145_message_id_we), - .wd (message_header_c145_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c145_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c145_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c145_message_type_we), - .wd (message_header_c145_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c145_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c145_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c145_protocol_id_we), - .wd (message_header_c145_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c145_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c145_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c145_token_we), - .wd (message_header_c145_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c145_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c145_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c145_field1_we), - .wd (message_header_c145_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c145_field1_qs) - ); - - - // R[message_payload_1_c145]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c145 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c145_we), - .wd (message_payload_1_c145_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c145_qs) - ); - - - // R[doorbell_c145]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c145_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c145_intr_we), - .wd (doorbell_c145_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c145.intr.q ), - - // to register interface (read) - .qs (doorbell_c145_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c145_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c145_preserve_mask_we), - .wd (doorbell_c145_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c145.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c145_preserve_mask_qs) - ); - - - // R[completion_interrupt_c145]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c145_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c145_intr_we), - .wd (completion_interrupt_c145_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c145.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c145_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c145_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c145_preserve_mask_we), - .wd (completion_interrupt_c145_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c145.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c145_preserve_mask_qs) - ); - - - // R[reserved_1_c146]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_1_c146 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_1_c146_we), - .wd (reserved_1_c146_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_1_c146_qs) - ); - - - // R[channel_status_c146]: V(False) - - // F[channel_free]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c146_channel_free ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c146_channel_free_we), - .wd (channel_status_c146_channel_free_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c146_channel_free_qs) - ); - - - // F[channel_error]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_status_c146_channel_error ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c146_channel_error_we), - .wd (channel_status_c146_channel_error_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c146_channel_error_qs) - ); - - - // F[field1]: 31:2 - prim_subreg #( - .DW (30), - .SWACCESS("RW"), - .RESVAL (30'h0) - ) u_channel_status_c146_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_status_c146_field1_we), - .wd (channel_status_c146_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_status_c146_field1_qs) - ); - - - // R[reserved_2_c146]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_reserved_2_c146 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (reserved_2_c146_we), - .wd (reserved_2_c146_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (reserved_2_c146_qs) - ); - - - // R[reserved_3_c146]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("NONE"), - .RESVAL (32'h0) - ) u_reserved_3_c146 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - .qs () - ); - - - // R[channel_flags_c146]: V(False) - - // F[intr_enable]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_channel_flags_c146_intr_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c146_intr_enable_we), - .wd (channel_flags_c146_intr_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c146_intr_enable_qs) - ); - - - // F[field1]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_channel_flags_c146_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (channel_flags_c146_field1_we), - .wd (channel_flags_c146_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (channel_flags_c146_field1_qs) - ); - - - // R[length_c146]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_length_c146 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (length_c146_we), - .wd (length_c146_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (length_c146_qs) - ); - - - // R[message_header_c146]: V(False) - - // F[message_id]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c146_message_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c146_message_id_we), - .wd (message_header_c146_message_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c146_message_id_qs) - ); - - - // F[message_type]: 9:8 - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_message_header_c146_message_type ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c146_message_type_we), - .wd (message_header_c146_message_type_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c146_message_type_qs) - ); - - - // F[protocol_id]: 17:10 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_message_header_c146_protocol_id ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c146_protocol_id_we), - .wd (message_header_c146_protocol_id_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c146_protocol_id_qs) - ); - - - // F[token]: 27:18 - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_message_header_c146_token ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c146_token_we), - .wd (message_header_c146_token_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c146_token_qs) - ); - - - // F[field1]: 31:28 - prim_subreg #( - .DW (4), - .SWACCESS("RW"), - .RESVAL (4'h0) - ) u_message_header_c146_field1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_header_c146_field1_we), - .wd (message_header_c146_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_header_c146_field1_qs) - ); - - - // R[message_payload_1_c146]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_message_payload_1_c146 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (message_payload_1_c146_we), - .wd (message_payload_1_c146_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (message_payload_1_c146_qs) - ); - - - // R[doorbell_c146]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_doorbell_c146_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c146_intr_we), - .wd (doorbell_c146_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c146.intr.q ), - - // to register interface (read) - .qs (doorbell_c146_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_doorbell_c146_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (doorbell_c146_preserve_mask_we), - .wd (doorbell_c146_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.doorbell_c146.preserve_mask.q ), - - // to register interface (read) - .qs (doorbell_c146_preserve_mask_qs) - ); - - - // R[completion_interrupt_c146]: V(False) - - // F[intr]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_completion_interrupt_c146_intr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c146_intr_we), - .wd (completion_interrupt_c146_intr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c146.intr.q ), - - // to register interface (read) - .qs (completion_interrupt_c146_intr_qs) - ); - - - // F[preserve_mask]: 31:1 - prim_subreg #( - .DW (31), - .SWACCESS("RW"), - .RESVAL (31'h0) - ) u_completion_interrupt_c146_preserve_mask ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (completion_interrupt_c146_preserve_mask_we), - .wd (completion_interrupt_c146_preserve_mask_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.completion_interrupt_c146.preserve_mask.q ), - - // to register interface (read) - .qs (completion_interrupt_c146_preserve_mask_qs) - ); - - - - - logic [1469:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == SCMI_RESERVED_1_C0_OFFSET); - addr_hit[ 1] = (reg_addr == SCMI_CHANNEL_STATUS_C0_OFFSET); - addr_hit[ 2] = (reg_addr == SCMI_RESERVED_2_C0_OFFSET); - addr_hit[ 3] = (reg_addr == SCMI_RESERVED_3_C0_OFFSET); - addr_hit[ 4] = (reg_addr == SCMI_CHANNEL_FLAGS_C0_OFFSET); - addr_hit[ 5] = (reg_addr == SCMI_LENGTH_C0_OFFSET); - addr_hit[ 6] = (reg_addr == SCMI_MESSAGE_HEADER_C0_OFFSET); - addr_hit[ 7] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C0_OFFSET); - addr_hit[ 8] = (reg_addr == SCMI_DOORBELL_C0_OFFSET); - addr_hit[ 9] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C0_OFFSET); - addr_hit[ 10] = (reg_addr == SCMI_RESERVED_1_C1_OFFSET); - addr_hit[ 11] = (reg_addr == SCMI_CHANNEL_STATUS_C1_OFFSET); - addr_hit[ 12] = (reg_addr == SCMI_RESERVED_2_C1_OFFSET); - addr_hit[ 13] = (reg_addr == SCMI_RESERVED_3_C1_OFFSET); - addr_hit[ 14] = (reg_addr == SCMI_CHANNEL_FLAGS_C1_OFFSET); - addr_hit[ 15] = (reg_addr == SCMI_LENGTH_C1_OFFSET); - addr_hit[ 16] = (reg_addr == SCMI_MESSAGE_HEADER_C1_OFFSET); - addr_hit[ 17] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C1_OFFSET); - addr_hit[ 18] = (reg_addr == SCMI_DOORBELL_C1_OFFSET); - addr_hit[ 19] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C1_OFFSET); - addr_hit[ 20] = (reg_addr == SCMI_RESERVED_1_C2_OFFSET); - addr_hit[ 21] = (reg_addr == SCMI_CHANNEL_STATUS_C2_OFFSET); - addr_hit[ 22] = (reg_addr == SCMI_RESERVED_2_C2_OFFSET); - addr_hit[ 23] = (reg_addr == SCMI_RESERVED_3_C2_OFFSET); - addr_hit[ 24] = (reg_addr == SCMI_CHANNEL_FLAGS_C2_OFFSET); - addr_hit[ 25] = (reg_addr == SCMI_LENGTH_C2_OFFSET); - addr_hit[ 26] = (reg_addr == SCMI_MESSAGE_HEADER_C2_OFFSET); - addr_hit[ 27] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C2_OFFSET); - addr_hit[ 28] = (reg_addr == SCMI_DOORBELL_C2_OFFSET); - addr_hit[ 29] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C2_OFFSET); - addr_hit[ 30] = (reg_addr == SCMI_RESERVED_1_C3_OFFSET); - addr_hit[ 31] = (reg_addr == SCMI_CHANNEL_STATUS_C3_OFFSET); - addr_hit[ 32] = (reg_addr == SCMI_RESERVED_2_C3_OFFSET); - addr_hit[ 33] = (reg_addr == SCMI_RESERVED_3_C3_OFFSET); - addr_hit[ 34] = (reg_addr == SCMI_CHANNEL_FLAGS_C3_OFFSET); - addr_hit[ 35] = (reg_addr == SCMI_LENGTH_C3_OFFSET); - addr_hit[ 36] = (reg_addr == SCMI_MESSAGE_HEADER_C3_OFFSET); - addr_hit[ 37] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C3_OFFSET); - addr_hit[ 38] = (reg_addr == SCMI_DOORBELL_C3_OFFSET); - addr_hit[ 39] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C3_OFFSET); - addr_hit[ 40] = (reg_addr == SCMI_RESERVED_1_C4_OFFSET); - addr_hit[ 41] = (reg_addr == SCMI_CHANNEL_STATUS_C4_OFFSET); - addr_hit[ 42] = (reg_addr == SCMI_RESERVED_2_C4_OFFSET); - addr_hit[ 43] = (reg_addr == SCMI_RESERVED_3_C4_OFFSET); - addr_hit[ 44] = (reg_addr == SCMI_CHANNEL_FLAGS_C4_OFFSET); - addr_hit[ 45] = (reg_addr == SCMI_LENGTH_C4_OFFSET); - addr_hit[ 46] = (reg_addr == SCMI_MESSAGE_HEADER_C4_OFFSET); - addr_hit[ 47] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C4_OFFSET); - addr_hit[ 48] = (reg_addr == SCMI_DOORBELL_C4_OFFSET); - addr_hit[ 49] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C4_OFFSET); - addr_hit[ 50] = (reg_addr == SCMI_RESERVED_1_C5_OFFSET); - addr_hit[ 51] = (reg_addr == SCMI_CHANNEL_STATUS_C5_OFFSET); - addr_hit[ 52] = (reg_addr == SCMI_RESERVED_2_C5_OFFSET); - addr_hit[ 53] = (reg_addr == SCMI_RESERVED_3_C5_OFFSET); - addr_hit[ 54] = (reg_addr == SCMI_CHANNEL_FLAGS_C5_OFFSET); - addr_hit[ 55] = (reg_addr == SCMI_LENGTH_C5_OFFSET); - addr_hit[ 56] = (reg_addr == SCMI_MESSAGE_HEADER_C5_OFFSET); - addr_hit[ 57] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C5_OFFSET); - addr_hit[ 58] = (reg_addr == SCMI_DOORBELL_C5_OFFSET); - addr_hit[ 59] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C5_OFFSET); - addr_hit[ 60] = (reg_addr == SCMI_RESERVED_1_C6_OFFSET); - addr_hit[ 61] = (reg_addr == SCMI_CHANNEL_STATUS_C6_OFFSET); - addr_hit[ 62] = (reg_addr == SCMI_RESERVED_2_C6_OFFSET); - addr_hit[ 63] = (reg_addr == SCMI_RESERVED_3_C6_OFFSET); - addr_hit[ 64] = (reg_addr == SCMI_CHANNEL_FLAGS_C6_OFFSET); - addr_hit[ 65] = (reg_addr == SCMI_LENGTH_C6_OFFSET); - addr_hit[ 66] = (reg_addr == SCMI_MESSAGE_HEADER_C6_OFFSET); - addr_hit[ 67] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C6_OFFSET); - addr_hit[ 68] = (reg_addr == SCMI_DOORBELL_C6_OFFSET); - addr_hit[ 69] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C6_OFFSET); - addr_hit[ 70] = (reg_addr == SCMI_RESERVED_1_C7_OFFSET); - addr_hit[ 71] = (reg_addr == SCMI_CHANNEL_STATUS_C7_OFFSET); - addr_hit[ 72] = (reg_addr == SCMI_RESERVED_2_C7_OFFSET); - addr_hit[ 73] = (reg_addr == SCMI_RESERVED_3_C7_OFFSET); - addr_hit[ 74] = (reg_addr == SCMI_CHANNEL_FLAGS_C7_OFFSET); - addr_hit[ 75] = (reg_addr == SCMI_LENGTH_C7_OFFSET); - addr_hit[ 76] = (reg_addr == SCMI_MESSAGE_HEADER_C7_OFFSET); - addr_hit[ 77] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C7_OFFSET); - addr_hit[ 78] = (reg_addr == SCMI_DOORBELL_C7_OFFSET); - addr_hit[ 79] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C7_OFFSET); - addr_hit[ 80] = (reg_addr == SCMI_RESERVED_1_C8_OFFSET); - addr_hit[ 81] = (reg_addr == SCMI_CHANNEL_STATUS_C8_OFFSET); - addr_hit[ 82] = (reg_addr == SCMI_RESERVED_2_C8_OFFSET); - addr_hit[ 83] = (reg_addr == SCMI_RESERVED_3_C8_OFFSET); - addr_hit[ 84] = (reg_addr == SCMI_CHANNEL_FLAGS_C8_OFFSET); - addr_hit[ 85] = (reg_addr == SCMI_LENGTH_C8_OFFSET); - addr_hit[ 86] = (reg_addr == SCMI_MESSAGE_HEADER_C8_OFFSET); - addr_hit[ 87] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C8_OFFSET); - addr_hit[ 88] = (reg_addr == SCMI_DOORBELL_C8_OFFSET); - addr_hit[ 89] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C8_OFFSET); - addr_hit[ 90] = (reg_addr == SCMI_RESERVED_1_C9_OFFSET); - addr_hit[ 91] = (reg_addr == SCMI_CHANNEL_STATUS_C9_OFFSET); - addr_hit[ 92] = (reg_addr == SCMI_RESERVED_2_C9_OFFSET); - addr_hit[ 93] = (reg_addr == SCMI_RESERVED_3_C9_OFFSET); - addr_hit[ 94] = (reg_addr == SCMI_CHANNEL_FLAGS_C9_OFFSET); - addr_hit[ 95] = (reg_addr == SCMI_LENGTH_C9_OFFSET); - addr_hit[ 96] = (reg_addr == SCMI_MESSAGE_HEADER_C9_OFFSET); - addr_hit[ 97] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C9_OFFSET); - addr_hit[ 98] = (reg_addr == SCMI_DOORBELL_C9_OFFSET); - addr_hit[ 99] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C9_OFFSET); - addr_hit[ 100] = (reg_addr == SCMI_RESERVED_1_C10_OFFSET); - addr_hit[ 101] = (reg_addr == SCMI_CHANNEL_STATUS_C10_OFFSET); - addr_hit[ 102] = (reg_addr == SCMI_RESERVED_2_C10_OFFSET); - addr_hit[ 103] = (reg_addr == SCMI_RESERVED_3_C10_OFFSET); - addr_hit[ 104] = (reg_addr == SCMI_CHANNEL_FLAGS_C10_OFFSET); - addr_hit[ 105] = (reg_addr == SCMI_LENGTH_C10_OFFSET); - addr_hit[ 106] = (reg_addr == SCMI_MESSAGE_HEADER_C10_OFFSET); - addr_hit[ 107] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C10_OFFSET); - addr_hit[ 108] = (reg_addr == SCMI_DOORBELL_C10_OFFSET); - addr_hit[ 109] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C10_OFFSET); - addr_hit[ 110] = (reg_addr == SCMI_RESERVED_1_C11_OFFSET); - addr_hit[ 111] = (reg_addr == SCMI_CHANNEL_STATUS_C11_OFFSET); - addr_hit[ 112] = (reg_addr == SCMI_RESERVED_2_C11_OFFSET); - addr_hit[ 113] = (reg_addr == SCMI_RESERVED_3_C11_OFFSET); - addr_hit[ 114] = (reg_addr == SCMI_CHANNEL_FLAGS_C11_OFFSET); - addr_hit[ 115] = (reg_addr == SCMI_LENGTH_C11_OFFSET); - addr_hit[ 116] = (reg_addr == SCMI_MESSAGE_HEADER_C11_OFFSET); - addr_hit[ 117] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C11_OFFSET); - addr_hit[ 118] = (reg_addr == SCMI_DOORBELL_C11_OFFSET); - addr_hit[ 119] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C11_OFFSET); - addr_hit[ 120] = (reg_addr == SCMI_RESERVED_1_C12_OFFSET); - addr_hit[ 121] = (reg_addr == SCMI_CHANNEL_STATUS_C12_OFFSET); - addr_hit[ 122] = (reg_addr == SCMI_RESERVED_2_C12_OFFSET); - addr_hit[ 123] = (reg_addr == SCMI_RESERVED_3_C12_OFFSET); - addr_hit[ 124] = (reg_addr == SCMI_CHANNEL_FLAGS_C12_OFFSET); - addr_hit[ 125] = (reg_addr == SCMI_LENGTH_C12_OFFSET); - addr_hit[ 126] = (reg_addr == SCMI_MESSAGE_HEADER_C12_OFFSET); - addr_hit[ 127] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C12_OFFSET); - addr_hit[ 128] = (reg_addr == SCMI_DOORBELL_C12_OFFSET); - addr_hit[ 129] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C12_OFFSET); - addr_hit[ 130] = (reg_addr == SCMI_RESERVED_1_C13_OFFSET); - addr_hit[ 131] = (reg_addr == SCMI_CHANNEL_STATUS_C13_OFFSET); - addr_hit[ 132] = (reg_addr == SCMI_RESERVED_2_C13_OFFSET); - addr_hit[ 133] = (reg_addr == SCMI_RESERVED_3_C13_OFFSET); - addr_hit[ 134] = (reg_addr == SCMI_CHANNEL_FLAGS_C13_OFFSET); - addr_hit[ 135] = (reg_addr == SCMI_LENGTH_C13_OFFSET); - addr_hit[ 136] = (reg_addr == SCMI_MESSAGE_HEADER_C13_OFFSET); - addr_hit[ 137] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C13_OFFSET); - addr_hit[ 138] = (reg_addr == SCMI_DOORBELL_C13_OFFSET); - addr_hit[ 139] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C13_OFFSET); - addr_hit[ 140] = (reg_addr == SCMI_RESERVED_1_C14_OFFSET); - addr_hit[ 141] = (reg_addr == SCMI_CHANNEL_STATUS_C14_OFFSET); - addr_hit[ 142] = (reg_addr == SCMI_RESERVED_2_C14_OFFSET); - addr_hit[ 143] = (reg_addr == SCMI_RESERVED_3_C14_OFFSET); - addr_hit[ 144] = (reg_addr == SCMI_CHANNEL_FLAGS_C14_OFFSET); - addr_hit[ 145] = (reg_addr == SCMI_LENGTH_C14_OFFSET); - addr_hit[ 146] = (reg_addr == SCMI_MESSAGE_HEADER_C14_OFFSET); - addr_hit[ 147] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C14_OFFSET); - addr_hit[ 148] = (reg_addr == SCMI_DOORBELL_C14_OFFSET); - addr_hit[ 149] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C14_OFFSET); - addr_hit[ 150] = (reg_addr == SCMI_RESERVED_1_C15_OFFSET); - addr_hit[ 151] = (reg_addr == SCMI_CHANNEL_STATUS_C15_OFFSET); - addr_hit[ 152] = (reg_addr == SCMI_RESERVED_2_C15_OFFSET); - addr_hit[ 153] = (reg_addr == SCMI_RESERVED_3_C15_OFFSET); - addr_hit[ 154] = (reg_addr == SCMI_CHANNEL_FLAGS_C15_OFFSET); - addr_hit[ 155] = (reg_addr == SCMI_LENGTH_C15_OFFSET); - addr_hit[ 156] = (reg_addr == SCMI_MESSAGE_HEADER_C15_OFFSET); - addr_hit[ 157] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C15_OFFSET); - addr_hit[ 158] = (reg_addr == SCMI_DOORBELL_C15_OFFSET); - addr_hit[ 159] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C15_OFFSET); - addr_hit[ 160] = (reg_addr == SCMI_RESERVED_1_C16_OFFSET); - addr_hit[ 161] = (reg_addr == SCMI_CHANNEL_STATUS_C16_OFFSET); - addr_hit[ 162] = (reg_addr == SCMI_RESERVED_2_C16_OFFSET); - addr_hit[ 163] = (reg_addr == SCMI_RESERVED_3_C16_OFFSET); - addr_hit[ 164] = (reg_addr == SCMI_CHANNEL_FLAGS_C16_OFFSET); - addr_hit[ 165] = (reg_addr == SCMI_LENGTH_C16_OFFSET); - addr_hit[ 166] = (reg_addr == SCMI_MESSAGE_HEADER_C16_OFFSET); - addr_hit[ 167] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C16_OFFSET); - addr_hit[ 168] = (reg_addr == SCMI_DOORBELL_C16_OFFSET); - addr_hit[ 169] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C16_OFFSET); - addr_hit[ 170] = (reg_addr == SCMI_RESERVED_1_C17_OFFSET); - addr_hit[ 171] = (reg_addr == SCMI_CHANNEL_STATUS_C17_OFFSET); - addr_hit[ 172] = (reg_addr == SCMI_RESERVED_2_C17_OFFSET); - addr_hit[ 173] = (reg_addr == SCMI_RESERVED_3_C17_OFFSET); - addr_hit[ 174] = (reg_addr == SCMI_CHANNEL_FLAGS_C17_OFFSET); - addr_hit[ 175] = (reg_addr == SCMI_LENGTH_C17_OFFSET); - addr_hit[ 176] = (reg_addr == SCMI_MESSAGE_HEADER_C17_OFFSET); - addr_hit[ 177] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C17_OFFSET); - addr_hit[ 178] = (reg_addr == SCMI_DOORBELL_C17_OFFSET); - addr_hit[ 179] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C17_OFFSET); - addr_hit[ 180] = (reg_addr == SCMI_RESERVED_1_C18_OFFSET); - addr_hit[ 181] = (reg_addr == SCMI_CHANNEL_STATUS_C18_OFFSET); - addr_hit[ 182] = (reg_addr == SCMI_RESERVED_2_C18_OFFSET); - addr_hit[ 183] = (reg_addr == SCMI_RESERVED_3_C18_OFFSET); - addr_hit[ 184] = (reg_addr == SCMI_CHANNEL_FLAGS_C18_OFFSET); - addr_hit[ 185] = (reg_addr == SCMI_LENGTH_C18_OFFSET); - addr_hit[ 186] = (reg_addr == SCMI_MESSAGE_HEADER_C18_OFFSET); - addr_hit[ 187] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C18_OFFSET); - addr_hit[ 188] = (reg_addr == SCMI_DOORBELL_C18_OFFSET); - addr_hit[ 189] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C18_OFFSET); - addr_hit[ 190] = (reg_addr == SCMI_RESERVED_1_C19_OFFSET); - addr_hit[ 191] = (reg_addr == SCMI_CHANNEL_STATUS_C19_OFFSET); - addr_hit[ 192] = (reg_addr == SCMI_RESERVED_2_C19_OFFSET); - addr_hit[ 193] = (reg_addr == SCMI_RESERVED_3_C19_OFFSET); - addr_hit[ 194] = (reg_addr == SCMI_CHANNEL_FLAGS_C19_OFFSET); - addr_hit[ 195] = (reg_addr == SCMI_LENGTH_C19_OFFSET); - addr_hit[ 196] = (reg_addr == SCMI_MESSAGE_HEADER_C19_OFFSET); - addr_hit[ 197] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C19_OFFSET); - addr_hit[ 198] = (reg_addr == SCMI_DOORBELL_C19_OFFSET); - addr_hit[ 199] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C19_OFFSET); - addr_hit[ 200] = (reg_addr == SCMI_RESERVED_1_C20_OFFSET); - addr_hit[ 201] = (reg_addr == SCMI_CHANNEL_STATUS_C20_OFFSET); - addr_hit[ 202] = (reg_addr == SCMI_RESERVED_2_C20_OFFSET); - addr_hit[ 203] = (reg_addr == SCMI_RESERVED_3_C20_OFFSET); - addr_hit[ 204] = (reg_addr == SCMI_CHANNEL_FLAGS_C20_OFFSET); - addr_hit[ 205] = (reg_addr == SCMI_LENGTH_C20_OFFSET); - addr_hit[ 206] = (reg_addr == SCMI_MESSAGE_HEADER_C20_OFFSET); - addr_hit[ 207] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C20_OFFSET); - addr_hit[ 208] = (reg_addr == SCMI_DOORBELL_C20_OFFSET); - addr_hit[ 209] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C20_OFFSET); - addr_hit[ 210] = (reg_addr == SCMI_RESERVED_1_C21_OFFSET); - addr_hit[ 211] = (reg_addr == SCMI_CHANNEL_STATUS_C21_OFFSET); - addr_hit[ 212] = (reg_addr == SCMI_RESERVED_2_C21_OFFSET); - addr_hit[ 213] = (reg_addr == SCMI_RESERVED_3_C21_OFFSET); - addr_hit[ 214] = (reg_addr == SCMI_CHANNEL_FLAGS_C21_OFFSET); - addr_hit[ 215] = (reg_addr == SCMI_LENGTH_C21_OFFSET); - addr_hit[ 216] = (reg_addr == SCMI_MESSAGE_HEADER_C21_OFFSET); - addr_hit[ 217] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C21_OFFSET); - addr_hit[ 218] = (reg_addr == SCMI_DOORBELL_C21_OFFSET); - addr_hit[ 219] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C21_OFFSET); - addr_hit[ 220] = (reg_addr == SCMI_RESERVED_1_C22_OFFSET); - addr_hit[ 221] = (reg_addr == SCMI_CHANNEL_STATUS_C22_OFFSET); - addr_hit[ 222] = (reg_addr == SCMI_RESERVED_2_C22_OFFSET); - addr_hit[ 223] = (reg_addr == SCMI_RESERVED_3_C22_OFFSET); - addr_hit[ 224] = (reg_addr == SCMI_CHANNEL_FLAGS_C22_OFFSET); - addr_hit[ 225] = (reg_addr == SCMI_LENGTH_C22_OFFSET); - addr_hit[ 226] = (reg_addr == SCMI_MESSAGE_HEADER_C22_OFFSET); - addr_hit[ 227] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C22_OFFSET); - addr_hit[ 228] = (reg_addr == SCMI_DOORBELL_C22_OFFSET); - addr_hit[ 229] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C22_OFFSET); - addr_hit[ 230] = (reg_addr == SCMI_RESERVED_1_C23_OFFSET); - addr_hit[ 231] = (reg_addr == SCMI_CHANNEL_STATUS_C23_OFFSET); - addr_hit[ 232] = (reg_addr == SCMI_RESERVED_2_C23_OFFSET); - addr_hit[ 233] = (reg_addr == SCMI_RESERVED_3_C23_OFFSET); - addr_hit[ 234] = (reg_addr == SCMI_CHANNEL_FLAGS_C23_OFFSET); - addr_hit[ 235] = (reg_addr == SCMI_LENGTH_C23_OFFSET); - addr_hit[ 236] = (reg_addr == SCMI_MESSAGE_HEADER_C23_OFFSET); - addr_hit[ 237] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C23_OFFSET); - addr_hit[ 238] = (reg_addr == SCMI_DOORBELL_C23_OFFSET); - addr_hit[ 239] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C23_OFFSET); - addr_hit[ 240] = (reg_addr == SCMI_RESERVED_1_C24_OFFSET); - addr_hit[ 241] = (reg_addr == SCMI_CHANNEL_STATUS_C24_OFFSET); - addr_hit[ 242] = (reg_addr == SCMI_RESERVED_2_C24_OFFSET); - addr_hit[ 243] = (reg_addr == SCMI_RESERVED_3_C24_OFFSET); - addr_hit[ 244] = (reg_addr == SCMI_CHANNEL_FLAGS_C24_OFFSET); - addr_hit[ 245] = (reg_addr == SCMI_LENGTH_C24_OFFSET); - addr_hit[ 246] = (reg_addr == SCMI_MESSAGE_HEADER_C24_OFFSET); - addr_hit[ 247] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C24_OFFSET); - addr_hit[ 248] = (reg_addr == SCMI_DOORBELL_C24_OFFSET); - addr_hit[ 249] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C24_OFFSET); - addr_hit[ 250] = (reg_addr == SCMI_RESERVED_1_C25_OFFSET); - addr_hit[ 251] = (reg_addr == SCMI_CHANNEL_STATUS_C25_OFFSET); - addr_hit[ 252] = (reg_addr == SCMI_RESERVED_2_C25_OFFSET); - addr_hit[ 253] = (reg_addr == SCMI_RESERVED_3_C25_OFFSET); - addr_hit[ 254] = (reg_addr == SCMI_CHANNEL_FLAGS_C25_OFFSET); - addr_hit[ 255] = (reg_addr == SCMI_LENGTH_C25_OFFSET); - addr_hit[ 256] = (reg_addr == SCMI_MESSAGE_HEADER_C25_OFFSET); - addr_hit[ 257] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C25_OFFSET); - addr_hit[ 258] = (reg_addr == SCMI_DOORBELL_C25_OFFSET); - addr_hit[ 259] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C25_OFFSET); - addr_hit[ 260] = (reg_addr == SCMI_RESERVED_1_C26_OFFSET); - addr_hit[ 261] = (reg_addr == SCMI_CHANNEL_STATUS_C26_OFFSET); - addr_hit[ 262] = (reg_addr == SCMI_RESERVED_2_C26_OFFSET); - addr_hit[ 263] = (reg_addr == SCMI_RESERVED_3_C26_OFFSET); - addr_hit[ 264] = (reg_addr == SCMI_CHANNEL_FLAGS_C26_OFFSET); - addr_hit[ 265] = (reg_addr == SCMI_LENGTH_C26_OFFSET); - addr_hit[ 266] = (reg_addr == SCMI_MESSAGE_HEADER_C26_OFFSET); - addr_hit[ 267] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C26_OFFSET); - addr_hit[ 268] = (reg_addr == SCMI_DOORBELL_C26_OFFSET); - addr_hit[ 269] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C26_OFFSET); - addr_hit[ 270] = (reg_addr == SCMI_RESERVED_1_C27_OFFSET); - addr_hit[ 271] = (reg_addr == SCMI_CHANNEL_STATUS_C27_OFFSET); - addr_hit[ 272] = (reg_addr == SCMI_RESERVED_2_C27_OFFSET); - addr_hit[ 273] = (reg_addr == SCMI_RESERVED_3_C27_OFFSET); - addr_hit[ 274] = (reg_addr == SCMI_CHANNEL_FLAGS_C27_OFFSET); - addr_hit[ 275] = (reg_addr == SCMI_LENGTH_C27_OFFSET); - addr_hit[ 276] = (reg_addr == SCMI_MESSAGE_HEADER_C27_OFFSET); - addr_hit[ 277] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C27_OFFSET); - addr_hit[ 278] = (reg_addr == SCMI_DOORBELL_C27_OFFSET); - addr_hit[ 279] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C27_OFFSET); - addr_hit[ 280] = (reg_addr == SCMI_RESERVED_1_C28_OFFSET); - addr_hit[ 281] = (reg_addr == SCMI_CHANNEL_STATUS_C28_OFFSET); - addr_hit[ 282] = (reg_addr == SCMI_RESERVED_2_C28_OFFSET); - addr_hit[ 283] = (reg_addr == SCMI_RESERVED_3_C28_OFFSET); - addr_hit[ 284] = (reg_addr == SCMI_CHANNEL_FLAGS_C28_OFFSET); - addr_hit[ 285] = (reg_addr == SCMI_LENGTH_C28_OFFSET); - addr_hit[ 286] = (reg_addr == SCMI_MESSAGE_HEADER_C28_OFFSET); - addr_hit[ 287] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C28_OFFSET); - addr_hit[ 288] = (reg_addr == SCMI_DOORBELL_C28_OFFSET); - addr_hit[ 289] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C28_OFFSET); - addr_hit[ 290] = (reg_addr == SCMI_RESERVED_1_C29_OFFSET); - addr_hit[ 291] = (reg_addr == SCMI_CHANNEL_STATUS_C29_OFFSET); - addr_hit[ 292] = (reg_addr == SCMI_RESERVED_2_C29_OFFSET); - addr_hit[ 293] = (reg_addr == SCMI_RESERVED_3_C29_OFFSET); - addr_hit[ 294] = (reg_addr == SCMI_CHANNEL_FLAGS_C29_OFFSET); - addr_hit[ 295] = (reg_addr == SCMI_LENGTH_C29_OFFSET); - addr_hit[ 296] = (reg_addr == SCMI_MESSAGE_HEADER_C29_OFFSET); - addr_hit[ 297] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C29_OFFSET); - addr_hit[ 298] = (reg_addr == SCMI_DOORBELL_C29_OFFSET); - addr_hit[ 299] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C29_OFFSET); - addr_hit[ 300] = (reg_addr == SCMI_RESERVED_1_C30_OFFSET); - addr_hit[ 301] = (reg_addr == SCMI_CHANNEL_STATUS_C30_OFFSET); - addr_hit[ 302] = (reg_addr == SCMI_RESERVED_2_C30_OFFSET); - addr_hit[ 303] = (reg_addr == SCMI_RESERVED_3_C30_OFFSET); - addr_hit[ 304] = (reg_addr == SCMI_CHANNEL_FLAGS_C30_OFFSET); - addr_hit[ 305] = (reg_addr == SCMI_LENGTH_C30_OFFSET); - addr_hit[ 306] = (reg_addr == SCMI_MESSAGE_HEADER_C30_OFFSET); - addr_hit[ 307] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C30_OFFSET); - addr_hit[ 308] = (reg_addr == SCMI_DOORBELL_C30_OFFSET); - addr_hit[ 309] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C30_OFFSET); - addr_hit[ 310] = (reg_addr == SCMI_RESERVED_1_C31_OFFSET); - addr_hit[ 311] = (reg_addr == SCMI_CHANNEL_STATUS_C31_OFFSET); - addr_hit[ 312] = (reg_addr == SCMI_RESERVED_2_C31_OFFSET); - addr_hit[ 313] = (reg_addr == SCMI_RESERVED_3_C31_OFFSET); - addr_hit[ 314] = (reg_addr == SCMI_CHANNEL_FLAGS_C31_OFFSET); - addr_hit[ 315] = (reg_addr == SCMI_LENGTH_C31_OFFSET); - addr_hit[ 316] = (reg_addr == SCMI_MESSAGE_HEADER_C31_OFFSET); - addr_hit[ 317] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C31_OFFSET); - addr_hit[ 318] = (reg_addr == SCMI_DOORBELL_C31_OFFSET); - addr_hit[ 319] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C31_OFFSET); - addr_hit[ 320] = (reg_addr == SCMI_RESERVED_1_C32_OFFSET); - addr_hit[ 321] = (reg_addr == SCMI_CHANNEL_STATUS_C32_OFFSET); - addr_hit[ 322] = (reg_addr == SCMI_RESERVED_2_C32_OFFSET); - addr_hit[ 323] = (reg_addr == SCMI_RESERVED_3_C32_OFFSET); - addr_hit[ 324] = (reg_addr == SCMI_CHANNEL_FLAGS_C32_OFFSET); - addr_hit[ 325] = (reg_addr == SCMI_LENGTH_C32_OFFSET); - addr_hit[ 326] = (reg_addr == SCMI_MESSAGE_HEADER_C32_OFFSET); - addr_hit[ 327] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C32_OFFSET); - addr_hit[ 328] = (reg_addr == SCMI_DOORBELL_C32_OFFSET); - addr_hit[ 329] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C32_OFFSET); - addr_hit[ 330] = (reg_addr == SCMI_RESERVED_1_C33_OFFSET); - addr_hit[ 331] = (reg_addr == SCMI_CHANNEL_STATUS_C33_OFFSET); - addr_hit[ 332] = (reg_addr == SCMI_RESERVED_2_C33_OFFSET); - addr_hit[ 333] = (reg_addr == SCMI_RESERVED_3_C33_OFFSET); - addr_hit[ 334] = (reg_addr == SCMI_CHANNEL_FLAGS_C33_OFFSET); - addr_hit[ 335] = (reg_addr == SCMI_LENGTH_C33_OFFSET); - addr_hit[ 336] = (reg_addr == SCMI_MESSAGE_HEADER_C33_OFFSET); - addr_hit[ 337] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C33_OFFSET); - addr_hit[ 338] = (reg_addr == SCMI_DOORBELL_C33_OFFSET); - addr_hit[ 339] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C33_OFFSET); - addr_hit[ 340] = (reg_addr == SCMI_RESERVED_1_C34_OFFSET); - addr_hit[ 341] = (reg_addr == SCMI_CHANNEL_STATUS_C34_OFFSET); - addr_hit[ 342] = (reg_addr == SCMI_RESERVED_2_C34_OFFSET); - addr_hit[ 343] = (reg_addr == SCMI_RESERVED_3_C34_OFFSET); - addr_hit[ 344] = (reg_addr == SCMI_CHANNEL_FLAGS_C34_OFFSET); - addr_hit[ 345] = (reg_addr == SCMI_LENGTH_C34_OFFSET); - addr_hit[ 346] = (reg_addr == SCMI_MESSAGE_HEADER_C34_OFFSET); - addr_hit[ 347] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C34_OFFSET); - addr_hit[ 348] = (reg_addr == SCMI_DOORBELL_C34_OFFSET); - addr_hit[ 349] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C34_OFFSET); - addr_hit[ 350] = (reg_addr == SCMI_RESERVED_1_C35_OFFSET); - addr_hit[ 351] = (reg_addr == SCMI_CHANNEL_STATUS_C35_OFFSET); - addr_hit[ 352] = (reg_addr == SCMI_RESERVED_2_C35_OFFSET); - addr_hit[ 353] = (reg_addr == SCMI_RESERVED_3_C35_OFFSET); - addr_hit[ 354] = (reg_addr == SCMI_CHANNEL_FLAGS_C35_OFFSET); - addr_hit[ 355] = (reg_addr == SCMI_LENGTH_C35_OFFSET); - addr_hit[ 356] = (reg_addr == SCMI_MESSAGE_HEADER_C35_OFFSET); - addr_hit[ 357] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C35_OFFSET); - addr_hit[ 358] = (reg_addr == SCMI_DOORBELL_C35_OFFSET); - addr_hit[ 359] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C35_OFFSET); - addr_hit[ 360] = (reg_addr == SCMI_RESERVED_1_C36_OFFSET); - addr_hit[ 361] = (reg_addr == SCMI_CHANNEL_STATUS_C36_OFFSET); - addr_hit[ 362] = (reg_addr == SCMI_RESERVED_2_C36_OFFSET); - addr_hit[ 363] = (reg_addr == SCMI_RESERVED_3_C36_OFFSET); - addr_hit[ 364] = (reg_addr == SCMI_CHANNEL_FLAGS_C36_OFFSET); - addr_hit[ 365] = (reg_addr == SCMI_LENGTH_C36_OFFSET); - addr_hit[ 366] = (reg_addr == SCMI_MESSAGE_HEADER_C36_OFFSET); - addr_hit[ 367] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C36_OFFSET); - addr_hit[ 368] = (reg_addr == SCMI_DOORBELL_C36_OFFSET); - addr_hit[ 369] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C36_OFFSET); - addr_hit[ 370] = (reg_addr == SCMI_RESERVED_1_C37_OFFSET); - addr_hit[ 371] = (reg_addr == SCMI_CHANNEL_STATUS_C37_OFFSET); - addr_hit[ 372] = (reg_addr == SCMI_RESERVED_2_C37_OFFSET); - addr_hit[ 373] = (reg_addr == SCMI_RESERVED_3_C37_OFFSET); - addr_hit[ 374] = (reg_addr == SCMI_CHANNEL_FLAGS_C37_OFFSET); - addr_hit[ 375] = (reg_addr == SCMI_LENGTH_C37_OFFSET); - addr_hit[ 376] = (reg_addr == SCMI_MESSAGE_HEADER_C37_OFFSET); - addr_hit[ 377] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C37_OFFSET); - addr_hit[ 378] = (reg_addr == SCMI_DOORBELL_C37_OFFSET); - addr_hit[ 379] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C37_OFFSET); - addr_hit[ 380] = (reg_addr == SCMI_RESERVED_1_C38_OFFSET); - addr_hit[ 381] = (reg_addr == SCMI_CHANNEL_STATUS_C38_OFFSET); - addr_hit[ 382] = (reg_addr == SCMI_RESERVED_2_C38_OFFSET); - addr_hit[ 383] = (reg_addr == SCMI_RESERVED_3_C38_OFFSET); - addr_hit[ 384] = (reg_addr == SCMI_CHANNEL_FLAGS_C38_OFFSET); - addr_hit[ 385] = (reg_addr == SCMI_LENGTH_C38_OFFSET); - addr_hit[ 386] = (reg_addr == SCMI_MESSAGE_HEADER_C38_OFFSET); - addr_hit[ 387] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C38_OFFSET); - addr_hit[ 388] = (reg_addr == SCMI_DOORBELL_C38_OFFSET); - addr_hit[ 389] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C38_OFFSET); - addr_hit[ 390] = (reg_addr == SCMI_RESERVED_1_C39_OFFSET); - addr_hit[ 391] = (reg_addr == SCMI_CHANNEL_STATUS_C39_OFFSET); - addr_hit[ 392] = (reg_addr == SCMI_RESERVED_2_C39_OFFSET); - addr_hit[ 393] = (reg_addr == SCMI_RESERVED_3_C39_OFFSET); - addr_hit[ 394] = (reg_addr == SCMI_CHANNEL_FLAGS_C39_OFFSET); - addr_hit[ 395] = (reg_addr == SCMI_LENGTH_C39_OFFSET); - addr_hit[ 396] = (reg_addr == SCMI_MESSAGE_HEADER_C39_OFFSET); - addr_hit[ 397] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C39_OFFSET); - addr_hit[ 398] = (reg_addr == SCMI_DOORBELL_C39_OFFSET); - addr_hit[ 399] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C39_OFFSET); - addr_hit[ 400] = (reg_addr == SCMI_RESERVED_1_C40_OFFSET); - addr_hit[ 401] = (reg_addr == SCMI_CHANNEL_STATUS_C40_OFFSET); - addr_hit[ 402] = (reg_addr == SCMI_RESERVED_2_C40_OFFSET); - addr_hit[ 403] = (reg_addr == SCMI_RESERVED_3_C40_OFFSET); - addr_hit[ 404] = (reg_addr == SCMI_CHANNEL_FLAGS_C40_OFFSET); - addr_hit[ 405] = (reg_addr == SCMI_LENGTH_C40_OFFSET); - addr_hit[ 406] = (reg_addr == SCMI_MESSAGE_HEADER_C40_OFFSET); - addr_hit[ 407] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C40_OFFSET); - addr_hit[ 408] = (reg_addr == SCMI_DOORBELL_C40_OFFSET); - addr_hit[ 409] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C40_OFFSET); - addr_hit[ 410] = (reg_addr == SCMI_RESERVED_1_C41_OFFSET); - addr_hit[ 411] = (reg_addr == SCMI_CHANNEL_STATUS_C41_OFFSET); - addr_hit[ 412] = (reg_addr == SCMI_RESERVED_2_C41_OFFSET); - addr_hit[ 413] = (reg_addr == SCMI_RESERVED_3_C41_OFFSET); - addr_hit[ 414] = (reg_addr == SCMI_CHANNEL_FLAGS_C41_OFFSET); - addr_hit[ 415] = (reg_addr == SCMI_LENGTH_C41_OFFSET); - addr_hit[ 416] = (reg_addr == SCMI_MESSAGE_HEADER_C41_OFFSET); - addr_hit[ 417] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C41_OFFSET); - addr_hit[ 418] = (reg_addr == SCMI_DOORBELL_C41_OFFSET); - addr_hit[ 419] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C41_OFFSET); - addr_hit[ 420] = (reg_addr == SCMI_RESERVED_1_C42_OFFSET); - addr_hit[ 421] = (reg_addr == SCMI_CHANNEL_STATUS_C42_OFFSET); - addr_hit[ 422] = (reg_addr == SCMI_RESERVED_2_C42_OFFSET); - addr_hit[ 423] = (reg_addr == SCMI_RESERVED_3_C42_OFFSET); - addr_hit[ 424] = (reg_addr == SCMI_CHANNEL_FLAGS_C42_OFFSET); - addr_hit[ 425] = (reg_addr == SCMI_LENGTH_C42_OFFSET); - addr_hit[ 426] = (reg_addr == SCMI_MESSAGE_HEADER_C42_OFFSET); - addr_hit[ 427] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C42_OFFSET); - addr_hit[ 428] = (reg_addr == SCMI_DOORBELL_C42_OFFSET); - addr_hit[ 429] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C42_OFFSET); - addr_hit[ 430] = (reg_addr == SCMI_RESERVED_1_C43_OFFSET); - addr_hit[ 431] = (reg_addr == SCMI_CHANNEL_STATUS_C43_OFFSET); - addr_hit[ 432] = (reg_addr == SCMI_RESERVED_2_C43_OFFSET); - addr_hit[ 433] = (reg_addr == SCMI_RESERVED_3_C43_OFFSET); - addr_hit[ 434] = (reg_addr == SCMI_CHANNEL_FLAGS_C43_OFFSET); - addr_hit[ 435] = (reg_addr == SCMI_LENGTH_C43_OFFSET); - addr_hit[ 436] = (reg_addr == SCMI_MESSAGE_HEADER_C43_OFFSET); - addr_hit[ 437] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C43_OFFSET); - addr_hit[ 438] = (reg_addr == SCMI_DOORBELL_C43_OFFSET); - addr_hit[ 439] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C43_OFFSET); - addr_hit[ 440] = (reg_addr == SCMI_RESERVED_1_C44_OFFSET); - addr_hit[ 441] = (reg_addr == SCMI_CHANNEL_STATUS_C44_OFFSET); - addr_hit[ 442] = (reg_addr == SCMI_RESERVED_2_C44_OFFSET); - addr_hit[ 443] = (reg_addr == SCMI_RESERVED_3_C44_OFFSET); - addr_hit[ 444] = (reg_addr == SCMI_CHANNEL_FLAGS_C44_OFFSET); - addr_hit[ 445] = (reg_addr == SCMI_LENGTH_C44_OFFSET); - addr_hit[ 446] = (reg_addr == SCMI_MESSAGE_HEADER_C44_OFFSET); - addr_hit[ 447] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C44_OFFSET); - addr_hit[ 448] = (reg_addr == SCMI_DOORBELL_C44_OFFSET); - addr_hit[ 449] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C44_OFFSET); - addr_hit[ 450] = (reg_addr == SCMI_RESERVED_1_C45_OFFSET); - addr_hit[ 451] = (reg_addr == SCMI_CHANNEL_STATUS_C45_OFFSET); - addr_hit[ 452] = (reg_addr == SCMI_RESERVED_2_C45_OFFSET); - addr_hit[ 453] = (reg_addr == SCMI_RESERVED_3_C45_OFFSET); - addr_hit[ 454] = (reg_addr == SCMI_CHANNEL_FLAGS_C45_OFFSET); - addr_hit[ 455] = (reg_addr == SCMI_LENGTH_C45_OFFSET); - addr_hit[ 456] = (reg_addr == SCMI_MESSAGE_HEADER_C45_OFFSET); - addr_hit[ 457] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C45_OFFSET); - addr_hit[ 458] = (reg_addr == SCMI_DOORBELL_C45_OFFSET); - addr_hit[ 459] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C45_OFFSET); - addr_hit[ 460] = (reg_addr == SCMI_RESERVED_1_C46_OFFSET); - addr_hit[ 461] = (reg_addr == SCMI_CHANNEL_STATUS_C46_OFFSET); - addr_hit[ 462] = (reg_addr == SCMI_RESERVED_2_C46_OFFSET); - addr_hit[ 463] = (reg_addr == SCMI_RESERVED_3_C46_OFFSET); - addr_hit[ 464] = (reg_addr == SCMI_CHANNEL_FLAGS_C46_OFFSET); - addr_hit[ 465] = (reg_addr == SCMI_LENGTH_C46_OFFSET); - addr_hit[ 466] = (reg_addr == SCMI_MESSAGE_HEADER_C46_OFFSET); - addr_hit[ 467] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C46_OFFSET); - addr_hit[ 468] = (reg_addr == SCMI_DOORBELL_C46_OFFSET); - addr_hit[ 469] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C46_OFFSET); - addr_hit[ 470] = (reg_addr == SCMI_RESERVED_1_C47_OFFSET); - addr_hit[ 471] = (reg_addr == SCMI_CHANNEL_STATUS_C47_OFFSET); - addr_hit[ 472] = (reg_addr == SCMI_RESERVED_2_C47_OFFSET); - addr_hit[ 473] = (reg_addr == SCMI_RESERVED_3_C47_OFFSET); - addr_hit[ 474] = (reg_addr == SCMI_CHANNEL_FLAGS_C47_OFFSET); - addr_hit[ 475] = (reg_addr == SCMI_LENGTH_C47_OFFSET); - addr_hit[ 476] = (reg_addr == SCMI_MESSAGE_HEADER_C47_OFFSET); - addr_hit[ 477] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C47_OFFSET); - addr_hit[ 478] = (reg_addr == SCMI_DOORBELL_C47_OFFSET); - addr_hit[ 479] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C47_OFFSET); - addr_hit[ 480] = (reg_addr == SCMI_RESERVED_1_C48_OFFSET); - addr_hit[ 481] = (reg_addr == SCMI_CHANNEL_STATUS_C48_OFFSET); - addr_hit[ 482] = (reg_addr == SCMI_RESERVED_2_C48_OFFSET); - addr_hit[ 483] = (reg_addr == SCMI_RESERVED_3_C48_OFFSET); - addr_hit[ 484] = (reg_addr == SCMI_CHANNEL_FLAGS_C48_OFFSET); - addr_hit[ 485] = (reg_addr == SCMI_LENGTH_C48_OFFSET); - addr_hit[ 486] = (reg_addr == SCMI_MESSAGE_HEADER_C48_OFFSET); - addr_hit[ 487] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C48_OFFSET); - addr_hit[ 488] = (reg_addr == SCMI_DOORBELL_C48_OFFSET); - addr_hit[ 489] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C48_OFFSET); - addr_hit[ 490] = (reg_addr == SCMI_RESERVED_1_C49_OFFSET); - addr_hit[ 491] = (reg_addr == SCMI_CHANNEL_STATUS_C49_OFFSET); - addr_hit[ 492] = (reg_addr == SCMI_RESERVED_2_C49_OFFSET); - addr_hit[ 493] = (reg_addr == SCMI_RESERVED_3_C49_OFFSET); - addr_hit[ 494] = (reg_addr == SCMI_CHANNEL_FLAGS_C49_OFFSET); - addr_hit[ 495] = (reg_addr == SCMI_LENGTH_C49_OFFSET); - addr_hit[ 496] = (reg_addr == SCMI_MESSAGE_HEADER_C49_OFFSET); - addr_hit[ 497] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C49_OFFSET); - addr_hit[ 498] = (reg_addr == SCMI_DOORBELL_C49_OFFSET); - addr_hit[ 499] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C49_OFFSET); - addr_hit[ 500] = (reg_addr == SCMI_RESERVED_1_C50_OFFSET); - addr_hit[ 501] = (reg_addr == SCMI_CHANNEL_STATUS_C50_OFFSET); - addr_hit[ 502] = (reg_addr == SCMI_RESERVED_2_C50_OFFSET); - addr_hit[ 503] = (reg_addr == SCMI_RESERVED_3_C50_OFFSET); - addr_hit[ 504] = (reg_addr == SCMI_CHANNEL_FLAGS_C50_OFFSET); - addr_hit[ 505] = (reg_addr == SCMI_LENGTH_C50_OFFSET); - addr_hit[ 506] = (reg_addr == SCMI_MESSAGE_HEADER_C50_OFFSET); - addr_hit[ 507] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C50_OFFSET); - addr_hit[ 508] = (reg_addr == SCMI_DOORBELL_C50_OFFSET); - addr_hit[ 509] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C50_OFFSET); - addr_hit[ 510] = (reg_addr == SCMI_RESERVED_1_C51_OFFSET); - addr_hit[ 511] = (reg_addr == SCMI_CHANNEL_STATUS_C51_OFFSET); - addr_hit[ 512] = (reg_addr == SCMI_RESERVED_2_C51_OFFSET); - addr_hit[ 513] = (reg_addr == SCMI_RESERVED_3_C51_OFFSET); - addr_hit[ 514] = (reg_addr == SCMI_CHANNEL_FLAGS_C51_OFFSET); - addr_hit[ 515] = (reg_addr == SCMI_LENGTH_C51_OFFSET); - addr_hit[ 516] = (reg_addr == SCMI_MESSAGE_HEADER_C51_OFFSET); - addr_hit[ 517] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C51_OFFSET); - addr_hit[ 518] = (reg_addr == SCMI_DOORBELL_C51_OFFSET); - addr_hit[ 519] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C51_OFFSET); - addr_hit[ 520] = (reg_addr == SCMI_RESERVED_1_C52_OFFSET); - addr_hit[ 521] = (reg_addr == SCMI_CHANNEL_STATUS_C52_OFFSET); - addr_hit[ 522] = (reg_addr == SCMI_RESERVED_2_C52_OFFSET); - addr_hit[ 523] = (reg_addr == SCMI_RESERVED_3_C52_OFFSET); - addr_hit[ 524] = (reg_addr == SCMI_CHANNEL_FLAGS_C52_OFFSET); - addr_hit[ 525] = (reg_addr == SCMI_LENGTH_C52_OFFSET); - addr_hit[ 526] = (reg_addr == SCMI_MESSAGE_HEADER_C52_OFFSET); - addr_hit[ 527] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C52_OFFSET); - addr_hit[ 528] = (reg_addr == SCMI_DOORBELL_C52_OFFSET); - addr_hit[ 529] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C52_OFFSET); - addr_hit[ 530] = (reg_addr == SCMI_RESERVED_1_C53_OFFSET); - addr_hit[ 531] = (reg_addr == SCMI_CHANNEL_STATUS_C53_OFFSET); - addr_hit[ 532] = (reg_addr == SCMI_RESERVED_2_C53_OFFSET); - addr_hit[ 533] = (reg_addr == SCMI_RESERVED_3_C53_OFFSET); - addr_hit[ 534] = (reg_addr == SCMI_CHANNEL_FLAGS_C53_OFFSET); - addr_hit[ 535] = (reg_addr == SCMI_LENGTH_C53_OFFSET); - addr_hit[ 536] = (reg_addr == SCMI_MESSAGE_HEADER_C53_OFFSET); - addr_hit[ 537] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C53_OFFSET); - addr_hit[ 538] = (reg_addr == SCMI_DOORBELL_C53_OFFSET); - addr_hit[ 539] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C53_OFFSET); - addr_hit[ 540] = (reg_addr == SCMI_RESERVED_1_C54_OFFSET); - addr_hit[ 541] = (reg_addr == SCMI_CHANNEL_STATUS_C54_OFFSET); - addr_hit[ 542] = (reg_addr == SCMI_RESERVED_2_C54_OFFSET); - addr_hit[ 543] = (reg_addr == SCMI_RESERVED_3_C54_OFFSET); - addr_hit[ 544] = (reg_addr == SCMI_CHANNEL_FLAGS_C54_OFFSET); - addr_hit[ 545] = (reg_addr == SCMI_LENGTH_C54_OFFSET); - addr_hit[ 546] = (reg_addr == SCMI_MESSAGE_HEADER_C54_OFFSET); - addr_hit[ 547] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C54_OFFSET); - addr_hit[ 548] = (reg_addr == SCMI_DOORBELL_C54_OFFSET); - addr_hit[ 549] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C54_OFFSET); - addr_hit[ 550] = (reg_addr == SCMI_RESERVED_1_C55_OFFSET); - addr_hit[ 551] = (reg_addr == SCMI_CHANNEL_STATUS_C55_OFFSET); - addr_hit[ 552] = (reg_addr == SCMI_RESERVED_2_C55_OFFSET); - addr_hit[ 553] = (reg_addr == SCMI_RESERVED_3_C55_OFFSET); - addr_hit[ 554] = (reg_addr == SCMI_CHANNEL_FLAGS_C55_OFFSET); - addr_hit[ 555] = (reg_addr == SCMI_LENGTH_C55_OFFSET); - addr_hit[ 556] = (reg_addr == SCMI_MESSAGE_HEADER_C55_OFFSET); - addr_hit[ 557] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C55_OFFSET); - addr_hit[ 558] = (reg_addr == SCMI_DOORBELL_C55_OFFSET); - addr_hit[ 559] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C55_OFFSET); - addr_hit[ 560] = (reg_addr == SCMI_RESERVED_1_C56_OFFSET); - addr_hit[ 561] = (reg_addr == SCMI_CHANNEL_STATUS_C56_OFFSET); - addr_hit[ 562] = (reg_addr == SCMI_RESERVED_2_C56_OFFSET); - addr_hit[ 563] = (reg_addr == SCMI_RESERVED_3_C56_OFFSET); - addr_hit[ 564] = (reg_addr == SCMI_CHANNEL_FLAGS_C56_OFFSET); - addr_hit[ 565] = (reg_addr == SCMI_LENGTH_C56_OFFSET); - addr_hit[ 566] = (reg_addr == SCMI_MESSAGE_HEADER_C56_OFFSET); - addr_hit[ 567] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C56_OFFSET); - addr_hit[ 568] = (reg_addr == SCMI_DOORBELL_C56_OFFSET); - addr_hit[ 569] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C56_OFFSET); - addr_hit[ 570] = (reg_addr == SCMI_RESERVED_1_C57_OFFSET); - addr_hit[ 571] = (reg_addr == SCMI_CHANNEL_STATUS_C57_OFFSET); - addr_hit[ 572] = (reg_addr == SCMI_RESERVED_2_C57_OFFSET); - addr_hit[ 573] = (reg_addr == SCMI_RESERVED_3_C57_OFFSET); - addr_hit[ 574] = (reg_addr == SCMI_CHANNEL_FLAGS_C57_OFFSET); - addr_hit[ 575] = (reg_addr == SCMI_LENGTH_C57_OFFSET); - addr_hit[ 576] = (reg_addr == SCMI_MESSAGE_HEADER_C57_OFFSET); - addr_hit[ 577] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C57_OFFSET); - addr_hit[ 578] = (reg_addr == SCMI_DOORBELL_C57_OFFSET); - addr_hit[ 579] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C57_OFFSET); - addr_hit[ 580] = (reg_addr == SCMI_RESERVED_1_C58_OFFSET); - addr_hit[ 581] = (reg_addr == SCMI_CHANNEL_STATUS_C58_OFFSET); - addr_hit[ 582] = (reg_addr == SCMI_RESERVED_2_C58_OFFSET); - addr_hit[ 583] = (reg_addr == SCMI_RESERVED_3_C58_OFFSET); - addr_hit[ 584] = (reg_addr == SCMI_CHANNEL_FLAGS_C58_OFFSET); - addr_hit[ 585] = (reg_addr == SCMI_LENGTH_C58_OFFSET); - addr_hit[ 586] = (reg_addr == SCMI_MESSAGE_HEADER_C58_OFFSET); - addr_hit[ 587] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C58_OFFSET); - addr_hit[ 588] = (reg_addr == SCMI_DOORBELL_C58_OFFSET); - addr_hit[ 589] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C58_OFFSET); - addr_hit[ 590] = (reg_addr == SCMI_RESERVED_1_C59_OFFSET); - addr_hit[ 591] = (reg_addr == SCMI_CHANNEL_STATUS_C59_OFFSET); - addr_hit[ 592] = (reg_addr == SCMI_RESERVED_2_C59_OFFSET); - addr_hit[ 593] = (reg_addr == SCMI_RESERVED_3_C59_OFFSET); - addr_hit[ 594] = (reg_addr == SCMI_CHANNEL_FLAGS_C59_OFFSET); - addr_hit[ 595] = (reg_addr == SCMI_LENGTH_C59_OFFSET); - addr_hit[ 596] = (reg_addr == SCMI_MESSAGE_HEADER_C59_OFFSET); - addr_hit[ 597] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C59_OFFSET); - addr_hit[ 598] = (reg_addr == SCMI_DOORBELL_C59_OFFSET); - addr_hit[ 599] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C59_OFFSET); - addr_hit[ 600] = (reg_addr == SCMI_RESERVED_1_C60_OFFSET); - addr_hit[ 601] = (reg_addr == SCMI_CHANNEL_STATUS_C60_OFFSET); - addr_hit[ 602] = (reg_addr == SCMI_RESERVED_2_C60_OFFSET); - addr_hit[ 603] = (reg_addr == SCMI_RESERVED_3_C60_OFFSET); - addr_hit[ 604] = (reg_addr == SCMI_CHANNEL_FLAGS_C60_OFFSET); - addr_hit[ 605] = (reg_addr == SCMI_LENGTH_C60_OFFSET); - addr_hit[ 606] = (reg_addr == SCMI_MESSAGE_HEADER_C60_OFFSET); - addr_hit[ 607] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C60_OFFSET); - addr_hit[ 608] = (reg_addr == SCMI_DOORBELL_C60_OFFSET); - addr_hit[ 609] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C60_OFFSET); - addr_hit[ 610] = (reg_addr == SCMI_RESERVED_1_C61_OFFSET); - addr_hit[ 611] = (reg_addr == SCMI_CHANNEL_STATUS_C61_OFFSET); - addr_hit[ 612] = (reg_addr == SCMI_RESERVED_2_C61_OFFSET); - addr_hit[ 613] = (reg_addr == SCMI_RESERVED_3_C61_OFFSET); - addr_hit[ 614] = (reg_addr == SCMI_CHANNEL_FLAGS_C61_OFFSET); - addr_hit[ 615] = (reg_addr == SCMI_LENGTH_C61_OFFSET); - addr_hit[ 616] = (reg_addr == SCMI_MESSAGE_HEADER_C61_OFFSET); - addr_hit[ 617] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C61_OFFSET); - addr_hit[ 618] = (reg_addr == SCMI_DOORBELL_C61_OFFSET); - addr_hit[ 619] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C61_OFFSET); - addr_hit[ 620] = (reg_addr == SCMI_RESERVED_1_C62_OFFSET); - addr_hit[ 621] = (reg_addr == SCMI_CHANNEL_STATUS_C62_OFFSET); - addr_hit[ 622] = (reg_addr == SCMI_RESERVED_2_C62_OFFSET); - addr_hit[ 623] = (reg_addr == SCMI_RESERVED_3_C62_OFFSET); - addr_hit[ 624] = (reg_addr == SCMI_CHANNEL_FLAGS_C62_OFFSET); - addr_hit[ 625] = (reg_addr == SCMI_LENGTH_C62_OFFSET); - addr_hit[ 626] = (reg_addr == SCMI_MESSAGE_HEADER_C62_OFFSET); - addr_hit[ 627] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C62_OFFSET); - addr_hit[ 628] = (reg_addr == SCMI_DOORBELL_C62_OFFSET); - addr_hit[ 629] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C62_OFFSET); - addr_hit[ 630] = (reg_addr == SCMI_RESERVED_1_C63_OFFSET); - addr_hit[ 631] = (reg_addr == SCMI_CHANNEL_STATUS_C63_OFFSET); - addr_hit[ 632] = (reg_addr == SCMI_RESERVED_2_C63_OFFSET); - addr_hit[ 633] = (reg_addr == SCMI_RESERVED_3_C63_OFFSET); - addr_hit[ 634] = (reg_addr == SCMI_CHANNEL_FLAGS_C63_OFFSET); - addr_hit[ 635] = (reg_addr == SCMI_LENGTH_C63_OFFSET); - addr_hit[ 636] = (reg_addr == SCMI_MESSAGE_HEADER_C63_OFFSET); - addr_hit[ 637] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C63_OFFSET); - addr_hit[ 638] = (reg_addr == SCMI_DOORBELL_C63_OFFSET); - addr_hit[ 639] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C63_OFFSET); - addr_hit[ 640] = (reg_addr == SCMI_RESERVED_1_C64_OFFSET); - addr_hit[ 641] = (reg_addr == SCMI_CHANNEL_STATUS_C64_OFFSET); - addr_hit[ 642] = (reg_addr == SCMI_RESERVED_2_C64_OFFSET); - addr_hit[ 643] = (reg_addr == SCMI_RESERVED_3_C64_OFFSET); - addr_hit[ 644] = (reg_addr == SCMI_CHANNEL_FLAGS_C64_OFFSET); - addr_hit[ 645] = (reg_addr == SCMI_LENGTH_C64_OFFSET); - addr_hit[ 646] = (reg_addr == SCMI_MESSAGE_HEADER_C64_OFFSET); - addr_hit[ 647] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C64_OFFSET); - addr_hit[ 648] = (reg_addr == SCMI_DOORBELL_C64_OFFSET); - addr_hit[ 649] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C64_OFFSET); - addr_hit[ 650] = (reg_addr == SCMI_RESERVED_1_C65_OFFSET); - addr_hit[ 651] = (reg_addr == SCMI_CHANNEL_STATUS_C65_OFFSET); - addr_hit[ 652] = (reg_addr == SCMI_RESERVED_2_C65_OFFSET); - addr_hit[ 653] = (reg_addr == SCMI_RESERVED_3_C65_OFFSET); - addr_hit[ 654] = (reg_addr == SCMI_CHANNEL_FLAGS_C65_OFFSET); - addr_hit[ 655] = (reg_addr == SCMI_LENGTH_C65_OFFSET); - addr_hit[ 656] = (reg_addr == SCMI_MESSAGE_HEADER_C65_OFFSET); - addr_hit[ 657] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C65_OFFSET); - addr_hit[ 658] = (reg_addr == SCMI_DOORBELL_C65_OFFSET); - addr_hit[ 659] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C65_OFFSET); - addr_hit[ 660] = (reg_addr == SCMI_RESERVED_1_C66_OFFSET); - addr_hit[ 661] = (reg_addr == SCMI_CHANNEL_STATUS_C66_OFFSET); - addr_hit[ 662] = (reg_addr == SCMI_RESERVED_2_C66_OFFSET); - addr_hit[ 663] = (reg_addr == SCMI_RESERVED_3_C66_OFFSET); - addr_hit[ 664] = (reg_addr == SCMI_CHANNEL_FLAGS_C66_OFFSET); - addr_hit[ 665] = (reg_addr == SCMI_LENGTH_C66_OFFSET); - addr_hit[ 666] = (reg_addr == SCMI_MESSAGE_HEADER_C66_OFFSET); - addr_hit[ 667] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C66_OFFSET); - addr_hit[ 668] = (reg_addr == SCMI_DOORBELL_C66_OFFSET); - addr_hit[ 669] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C66_OFFSET); - addr_hit[ 670] = (reg_addr == SCMI_RESERVED_1_C67_OFFSET); - addr_hit[ 671] = (reg_addr == SCMI_CHANNEL_STATUS_C67_OFFSET); - addr_hit[ 672] = (reg_addr == SCMI_RESERVED_2_C67_OFFSET); - addr_hit[ 673] = (reg_addr == SCMI_RESERVED_3_C67_OFFSET); - addr_hit[ 674] = (reg_addr == SCMI_CHANNEL_FLAGS_C67_OFFSET); - addr_hit[ 675] = (reg_addr == SCMI_LENGTH_C67_OFFSET); - addr_hit[ 676] = (reg_addr == SCMI_MESSAGE_HEADER_C67_OFFSET); - addr_hit[ 677] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C67_OFFSET); - addr_hit[ 678] = (reg_addr == SCMI_DOORBELL_C67_OFFSET); - addr_hit[ 679] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C67_OFFSET); - addr_hit[ 680] = (reg_addr == SCMI_RESERVED_1_C68_OFFSET); - addr_hit[ 681] = (reg_addr == SCMI_CHANNEL_STATUS_C68_OFFSET); - addr_hit[ 682] = (reg_addr == SCMI_RESERVED_2_C68_OFFSET); - addr_hit[ 683] = (reg_addr == SCMI_RESERVED_3_C68_OFFSET); - addr_hit[ 684] = (reg_addr == SCMI_CHANNEL_FLAGS_C68_OFFSET); - addr_hit[ 685] = (reg_addr == SCMI_LENGTH_C68_OFFSET); - addr_hit[ 686] = (reg_addr == SCMI_MESSAGE_HEADER_C68_OFFSET); - addr_hit[ 687] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C68_OFFSET); - addr_hit[ 688] = (reg_addr == SCMI_DOORBELL_C68_OFFSET); - addr_hit[ 689] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C68_OFFSET); - addr_hit[ 690] = (reg_addr == SCMI_RESERVED_1_C69_OFFSET); - addr_hit[ 691] = (reg_addr == SCMI_CHANNEL_STATUS_C69_OFFSET); - addr_hit[ 692] = (reg_addr == SCMI_RESERVED_2_C69_OFFSET); - addr_hit[ 693] = (reg_addr == SCMI_RESERVED_3_C69_OFFSET); - addr_hit[ 694] = (reg_addr == SCMI_CHANNEL_FLAGS_C69_OFFSET); - addr_hit[ 695] = (reg_addr == SCMI_LENGTH_C69_OFFSET); - addr_hit[ 696] = (reg_addr == SCMI_MESSAGE_HEADER_C69_OFFSET); - addr_hit[ 697] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C69_OFFSET); - addr_hit[ 698] = (reg_addr == SCMI_DOORBELL_C69_OFFSET); - addr_hit[ 699] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C69_OFFSET); - addr_hit[ 700] = (reg_addr == SCMI_RESERVED_1_C70_OFFSET); - addr_hit[ 701] = (reg_addr == SCMI_CHANNEL_STATUS_C70_OFFSET); - addr_hit[ 702] = (reg_addr == SCMI_RESERVED_2_C70_OFFSET); - addr_hit[ 703] = (reg_addr == SCMI_RESERVED_3_C70_OFFSET); - addr_hit[ 704] = (reg_addr == SCMI_CHANNEL_FLAGS_C70_OFFSET); - addr_hit[ 705] = (reg_addr == SCMI_LENGTH_C70_OFFSET); - addr_hit[ 706] = (reg_addr == SCMI_MESSAGE_HEADER_C70_OFFSET); - addr_hit[ 707] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C70_OFFSET); - addr_hit[ 708] = (reg_addr == SCMI_DOORBELL_C70_OFFSET); - addr_hit[ 709] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C70_OFFSET); - addr_hit[ 710] = (reg_addr == SCMI_RESERVED_1_C71_OFFSET); - addr_hit[ 711] = (reg_addr == SCMI_CHANNEL_STATUS_C71_OFFSET); - addr_hit[ 712] = (reg_addr == SCMI_RESERVED_2_C71_OFFSET); - addr_hit[ 713] = (reg_addr == SCMI_RESERVED_3_C71_OFFSET); - addr_hit[ 714] = (reg_addr == SCMI_CHANNEL_FLAGS_C71_OFFSET); - addr_hit[ 715] = (reg_addr == SCMI_LENGTH_C71_OFFSET); - addr_hit[ 716] = (reg_addr == SCMI_MESSAGE_HEADER_C71_OFFSET); - addr_hit[ 717] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C71_OFFSET); - addr_hit[ 718] = (reg_addr == SCMI_DOORBELL_C71_OFFSET); - addr_hit[ 719] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C71_OFFSET); - addr_hit[ 720] = (reg_addr == SCMI_RESERVED_1_C72_OFFSET); - addr_hit[ 721] = (reg_addr == SCMI_CHANNEL_STATUS_C72_OFFSET); - addr_hit[ 722] = (reg_addr == SCMI_RESERVED_2_C72_OFFSET); - addr_hit[ 723] = (reg_addr == SCMI_RESERVED_3_C72_OFFSET); - addr_hit[ 724] = (reg_addr == SCMI_CHANNEL_FLAGS_C72_OFFSET); - addr_hit[ 725] = (reg_addr == SCMI_LENGTH_C72_OFFSET); - addr_hit[ 726] = (reg_addr == SCMI_MESSAGE_HEADER_C72_OFFSET); - addr_hit[ 727] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C72_OFFSET); - addr_hit[ 728] = (reg_addr == SCMI_DOORBELL_C72_OFFSET); - addr_hit[ 729] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C72_OFFSET); - addr_hit[ 730] = (reg_addr == SCMI_RESERVED_1_C73_OFFSET); - addr_hit[ 731] = (reg_addr == SCMI_CHANNEL_STATUS_C73_OFFSET); - addr_hit[ 732] = (reg_addr == SCMI_RESERVED_2_C73_OFFSET); - addr_hit[ 733] = (reg_addr == SCMI_RESERVED_3_C73_OFFSET); - addr_hit[ 734] = (reg_addr == SCMI_CHANNEL_FLAGS_C73_OFFSET); - addr_hit[ 735] = (reg_addr == SCMI_LENGTH_C73_OFFSET); - addr_hit[ 736] = (reg_addr == SCMI_MESSAGE_HEADER_C73_OFFSET); - addr_hit[ 737] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C73_OFFSET); - addr_hit[ 738] = (reg_addr == SCMI_DOORBELL_C73_OFFSET); - addr_hit[ 739] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C73_OFFSET); - addr_hit[ 740] = (reg_addr == SCMI_RESERVED_1_C74_OFFSET); - addr_hit[ 741] = (reg_addr == SCMI_CHANNEL_STATUS_C74_OFFSET); - addr_hit[ 742] = (reg_addr == SCMI_RESERVED_2_C74_OFFSET); - addr_hit[ 743] = (reg_addr == SCMI_RESERVED_3_C74_OFFSET); - addr_hit[ 744] = (reg_addr == SCMI_CHANNEL_FLAGS_C74_OFFSET); - addr_hit[ 745] = (reg_addr == SCMI_LENGTH_C74_OFFSET); - addr_hit[ 746] = (reg_addr == SCMI_MESSAGE_HEADER_C74_OFFSET); - addr_hit[ 747] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C74_OFFSET); - addr_hit[ 748] = (reg_addr == SCMI_DOORBELL_C74_OFFSET); - addr_hit[ 749] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C74_OFFSET); - addr_hit[ 750] = (reg_addr == SCMI_RESERVED_1_C75_OFFSET); - addr_hit[ 751] = (reg_addr == SCMI_CHANNEL_STATUS_C75_OFFSET); - addr_hit[ 752] = (reg_addr == SCMI_RESERVED_2_C75_OFFSET); - addr_hit[ 753] = (reg_addr == SCMI_RESERVED_3_C75_OFFSET); - addr_hit[ 754] = (reg_addr == SCMI_CHANNEL_FLAGS_C75_OFFSET); - addr_hit[ 755] = (reg_addr == SCMI_LENGTH_C75_OFFSET); - addr_hit[ 756] = (reg_addr == SCMI_MESSAGE_HEADER_C75_OFFSET); - addr_hit[ 757] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C75_OFFSET); - addr_hit[ 758] = (reg_addr == SCMI_DOORBELL_C75_OFFSET); - addr_hit[ 759] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C75_OFFSET); - addr_hit[ 760] = (reg_addr == SCMI_RESERVED_1_C76_OFFSET); - addr_hit[ 761] = (reg_addr == SCMI_CHANNEL_STATUS_C76_OFFSET); - addr_hit[ 762] = (reg_addr == SCMI_RESERVED_2_C76_OFFSET); - addr_hit[ 763] = (reg_addr == SCMI_RESERVED_3_C76_OFFSET); - addr_hit[ 764] = (reg_addr == SCMI_CHANNEL_FLAGS_C76_OFFSET); - addr_hit[ 765] = (reg_addr == SCMI_LENGTH_C76_OFFSET); - addr_hit[ 766] = (reg_addr == SCMI_MESSAGE_HEADER_C76_OFFSET); - addr_hit[ 767] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C76_OFFSET); - addr_hit[ 768] = (reg_addr == SCMI_DOORBELL_C76_OFFSET); - addr_hit[ 769] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C76_OFFSET); - addr_hit[ 770] = (reg_addr == SCMI_RESERVED_1_C77_OFFSET); - addr_hit[ 771] = (reg_addr == SCMI_CHANNEL_STATUS_C77_OFFSET); - addr_hit[ 772] = (reg_addr == SCMI_RESERVED_2_C77_OFFSET); - addr_hit[ 773] = (reg_addr == SCMI_RESERVED_3_C77_OFFSET); - addr_hit[ 774] = (reg_addr == SCMI_CHANNEL_FLAGS_C77_OFFSET); - addr_hit[ 775] = (reg_addr == SCMI_LENGTH_C77_OFFSET); - addr_hit[ 776] = (reg_addr == SCMI_MESSAGE_HEADER_C77_OFFSET); - addr_hit[ 777] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C77_OFFSET); - addr_hit[ 778] = (reg_addr == SCMI_DOORBELL_C77_OFFSET); - addr_hit[ 779] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C77_OFFSET); - addr_hit[ 780] = (reg_addr == SCMI_RESERVED_1_C78_OFFSET); - addr_hit[ 781] = (reg_addr == SCMI_CHANNEL_STATUS_C78_OFFSET); - addr_hit[ 782] = (reg_addr == SCMI_RESERVED_2_C78_OFFSET); - addr_hit[ 783] = (reg_addr == SCMI_RESERVED_3_C78_OFFSET); - addr_hit[ 784] = (reg_addr == SCMI_CHANNEL_FLAGS_C78_OFFSET); - addr_hit[ 785] = (reg_addr == SCMI_LENGTH_C78_OFFSET); - addr_hit[ 786] = (reg_addr == SCMI_MESSAGE_HEADER_C78_OFFSET); - addr_hit[ 787] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C78_OFFSET); - addr_hit[ 788] = (reg_addr == SCMI_DOORBELL_C78_OFFSET); - addr_hit[ 789] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C78_OFFSET); - addr_hit[ 790] = (reg_addr == SCMI_RESERVED_1_C79_OFFSET); - addr_hit[ 791] = (reg_addr == SCMI_CHANNEL_STATUS_C79_OFFSET); - addr_hit[ 792] = (reg_addr == SCMI_RESERVED_2_C79_OFFSET); - addr_hit[ 793] = (reg_addr == SCMI_RESERVED_3_C79_OFFSET); - addr_hit[ 794] = (reg_addr == SCMI_CHANNEL_FLAGS_C79_OFFSET); - addr_hit[ 795] = (reg_addr == SCMI_LENGTH_C79_OFFSET); - addr_hit[ 796] = (reg_addr == SCMI_MESSAGE_HEADER_C79_OFFSET); - addr_hit[ 797] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C79_OFFSET); - addr_hit[ 798] = (reg_addr == SCMI_DOORBELL_C79_OFFSET); - addr_hit[ 799] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C79_OFFSET); - addr_hit[ 800] = (reg_addr == SCMI_RESERVED_1_C80_OFFSET); - addr_hit[ 801] = (reg_addr == SCMI_CHANNEL_STATUS_C80_OFFSET); - addr_hit[ 802] = (reg_addr == SCMI_RESERVED_2_C80_OFFSET); - addr_hit[ 803] = (reg_addr == SCMI_RESERVED_3_C80_OFFSET); - addr_hit[ 804] = (reg_addr == SCMI_CHANNEL_FLAGS_C80_OFFSET); - addr_hit[ 805] = (reg_addr == SCMI_LENGTH_C80_OFFSET); - addr_hit[ 806] = (reg_addr == SCMI_MESSAGE_HEADER_C80_OFFSET); - addr_hit[ 807] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C80_OFFSET); - addr_hit[ 808] = (reg_addr == SCMI_DOORBELL_C80_OFFSET); - addr_hit[ 809] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C80_OFFSET); - addr_hit[ 810] = (reg_addr == SCMI_RESERVED_1_C81_OFFSET); - addr_hit[ 811] = (reg_addr == SCMI_CHANNEL_STATUS_C81_OFFSET); - addr_hit[ 812] = (reg_addr == SCMI_RESERVED_2_C81_OFFSET); - addr_hit[ 813] = (reg_addr == SCMI_RESERVED_3_C81_OFFSET); - addr_hit[ 814] = (reg_addr == SCMI_CHANNEL_FLAGS_C81_OFFSET); - addr_hit[ 815] = (reg_addr == SCMI_LENGTH_C81_OFFSET); - addr_hit[ 816] = (reg_addr == SCMI_MESSAGE_HEADER_C81_OFFSET); - addr_hit[ 817] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C81_OFFSET); - addr_hit[ 818] = (reg_addr == SCMI_DOORBELL_C81_OFFSET); - addr_hit[ 819] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C81_OFFSET); - addr_hit[ 820] = (reg_addr == SCMI_RESERVED_1_C82_OFFSET); - addr_hit[ 821] = (reg_addr == SCMI_CHANNEL_STATUS_C82_OFFSET); - addr_hit[ 822] = (reg_addr == SCMI_RESERVED_2_C82_OFFSET); - addr_hit[ 823] = (reg_addr == SCMI_RESERVED_3_C82_OFFSET); - addr_hit[ 824] = (reg_addr == SCMI_CHANNEL_FLAGS_C82_OFFSET); - addr_hit[ 825] = (reg_addr == SCMI_LENGTH_C82_OFFSET); - addr_hit[ 826] = (reg_addr == SCMI_MESSAGE_HEADER_C82_OFFSET); - addr_hit[ 827] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C82_OFFSET); - addr_hit[ 828] = (reg_addr == SCMI_DOORBELL_C82_OFFSET); - addr_hit[ 829] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C82_OFFSET); - addr_hit[ 830] = (reg_addr == SCMI_RESERVED_1_C83_OFFSET); - addr_hit[ 831] = (reg_addr == SCMI_CHANNEL_STATUS_C83_OFFSET); - addr_hit[ 832] = (reg_addr == SCMI_RESERVED_2_C83_OFFSET); - addr_hit[ 833] = (reg_addr == SCMI_RESERVED_3_C83_OFFSET); - addr_hit[ 834] = (reg_addr == SCMI_CHANNEL_FLAGS_C83_OFFSET); - addr_hit[ 835] = (reg_addr == SCMI_LENGTH_C83_OFFSET); - addr_hit[ 836] = (reg_addr == SCMI_MESSAGE_HEADER_C83_OFFSET); - addr_hit[ 837] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C83_OFFSET); - addr_hit[ 838] = (reg_addr == SCMI_DOORBELL_C83_OFFSET); - addr_hit[ 839] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C83_OFFSET); - addr_hit[ 840] = (reg_addr == SCMI_RESERVED_1_C84_OFFSET); - addr_hit[ 841] = (reg_addr == SCMI_CHANNEL_STATUS_C84_OFFSET); - addr_hit[ 842] = (reg_addr == SCMI_RESERVED_2_C84_OFFSET); - addr_hit[ 843] = (reg_addr == SCMI_RESERVED_3_C84_OFFSET); - addr_hit[ 844] = (reg_addr == SCMI_CHANNEL_FLAGS_C84_OFFSET); - addr_hit[ 845] = (reg_addr == SCMI_LENGTH_C84_OFFSET); - addr_hit[ 846] = (reg_addr == SCMI_MESSAGE_HEADER_C84_OFFSET); - addr_hit[ 847] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C84_OFFSET); - addr_hit[ 848] = (reg_addr == SCMI_DOORBELL_C84_OFFSET); - addr_hit[ 849] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C84_OFFSET); - addr_hit[ 850] = (reg_addr == SCMI_RESERVED_1_C85_OFFSET); - addr_hit[ 851] = (reg_addr == SCMI_CHANNEL_STATUS_C85_OFFSET); - addr_hit[ 852] = (reg_addr == SCMI_RESERVED_2_C85_OFFSET); - addr_hit[ 853] = (reg_addr == SCMI_RESERVED_3_C85_OFFSET); - addr_hit[ 854] = (reg_addr == SCMI_CHANNEL_FLAGS_C85_OFFSET); - addr_hit[ 855] = (reg_addr == SCMI_LENGTH_C85_OFFSET); - addr_hit[ 856] = (reg_addr == SCMI_MESSAGE_HEADER_C85_OFFSET); - addr_hit[ 857] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C85_OFFSET); - addr_hit[ 858] = (reg_addr == SCMI_DOORBELL_C85_OFFSET); - addr_hit[ 859] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C85_OFFSET); - addr_hit[ 860] = (reg_addr == SCMI_RESERVED_1_C86_OFFSET); - addr_hit[ 861] = (reg_addr == SCMI_CHANNEL_STATUS_C86_OFFSET); - addr_hit[ 862] = (reg_addr == SCMI_RESERVED_2_C86_OFFSET); - addr_hit[ 863] = (reg_addr == SCMI_RESERVED_3_C86_OFFSET); - addr_hit[ 864] = (reg_addr == SCMI_CHANNEL_FLAGS_C86_OFFSET); - addr_hit[ 865] = (reg_addr == SCMI_LENGTH_C86_OFFSET); - addr_hit[ 866] = (reg_addr == SCMI_MESSAGE_HEADER_C86_OFFSET); - addr_hit[ 867] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C86_OFFSET); - addr_hit[ 868] = (reg_addr == SCMI_DOORBELL_C86_OFFSET); - addr_hit[ 869] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C86_OFFSET); - addr_hit[ 870] = (reg_addr == SCMI_RESERVED_1_C87_OFFSET); - addr_hit[ 871] = (reg_addr == SCMI_CHANNEL_STATUS_C87_OFFSET); - addr_hit[ 872] = (reg_addr == SCMI_RESERVED_2_C87_OFFSET); - addr_hit[ 873] = (reg_addr == SCMI_RESERVED_3_C87_OFFSET); - addr_hit[ 874] = (reg_addr == SCMI_CHANNEL_FLAGS_C87_OFFSET); - addr_hit[ 875] = (reg_addr == SCMI_LENGTH_C87_OFFSET); - addr_hit[ 876] = (reg_addr == SCMI_MESSAGE_HEADER_C87_OFFSET); - addr_hit[ 877] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C87_OFFSET); - addr_hit[ 878] = (reg_addr == SCMI_DOORBELL_C87_OFFSET); - addr_hit[ 879] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C87_OFFSET); - addr_hit[ 880] = (reg_addr == SCMI_RESERVED_1_C88_OFFSET); - addr_hit[ 881] = (reg_addr == SCMI_CHANNEL_STATUS_C88_OFFSET); - addr_hit[ 882] = (reg_addr == SCMI_RESERVED_2_C88_OFFSET); - addr_hit[ 883] = (reg_addr == SCMI_RESERVED_3_C88_OFFSET); - addr_hit[ 884] = (reg_addr == SCMI_CHANNEL_FLAGS_C88_OFFSET); - addr_hit[ 885] = (reg_addr == SCMI_LENGTH_C88_OFFSET); - addr_hit[ 886] = (reg_addr == SCMI_MESSAGE_HEADER_C88_OFFSET); - addr_hit[ 887] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C88_OFFSET); - addr_hit[ 888] = (reg_addr == SCMI_DOORBELL_C88_OFFSET); - addr_hit[ 889] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C88_OFFSET); - addr_hit[ 890] = (reg_addr == SCMI_RESERVED_1_C89_OFFSET); - addr_hit[ 891] = (reg_addr == SCMI_CHANNEL_STATUS_C89_OFFSET); - addr_hit[ 892] = (reg_addr == SCMI_RESERVED_2_C89_OFFSET); - addr_hit[ 893] = (reg_addr == SCMI_RESERVED_3_C89_OFFSET); - addr_hit[ 894] = (reg_addr == SCMI_CHANNEL_FLAGS_C89_OFFSET); - addr_hit[ 895] = (reg_addr == SCMI_LENGTH_C89_OFFSET); - addr_hit[ 896] = (reg_addr == SCMI_MESSAGE_HEADER_C89_OFFSET); - addr_hit[ 897] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C89_OFFSET); - addr_hit[ 898] = (reg_addr == SCMI_DOORBELL_C89_OFFSET); - addr_hit[ 899] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C89_OFFSET); - addr_hit[ 900] = (reg_addr == SCMI_RESERVED_1_C90_OFFSET); - addr_hit[ 901] = (reg_addr == SCMI_CHANNEL_STATUS_C90_OFFSET); - addr_hit[ 902] = (reg_addr == SCMI_RESERVED_2_C90_OFFSET); - addr_hit[ 903] = (reg_addr == SCMI_RESERVED_3_C90_OFFSET); - addr_hit[ 904] = (reg_addr == SCMI_CHANNEL_FLAGS_C90_OFFSET); - addr_hit[ 905] = (reg_addr == SCMI_LENGTH_C90_OFFSET); - addr_hit[ 906] = (reg_addr == SCMI_MESSAGE_HEADER_C90_OFFSET); - addr_hit[ 907] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C90_OFFSET); - addr_hit[ 908] = (reg_addr == SCMI_DOORBELL_C90_OFFSET); - addr_hit[ 909] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C90_OFFSET); - addr_hit[ 910] = (reg_addr == SCMI_RESERVED_1_C91_OFFSET); - addr_hit[ 911] = (reg_addr == SCMI_CHANNEL_STATUS_C91_OFFSET); - addr_hit[ 912] = (reg_addr == SCMI_RESERVED_2_C91_OFFSET); - addr_hit[ 913] = (reg_addr == SCMI_RESERVED_3_C91_OFFSET); - addr_hit[ 914] = (reg_addr == SCMI_CHANNEL_FLAGS_C91_OFFSET); - addr_hit[ 915] = (reg_addr == SCMI_LENGTH_C91_OFFSET); - addr_hit[ 916] = (reg_addr == SCMI_MESSAGE_HEADER_C91_OFFSET); - addr_hit[ 917] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C91_OFFSET); - addr_hit[ 918] = (reg_addr == SCMI_DOORBELL_C91_OFFSET); - addr_hit[ 919] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C91_OFFSET); - addr_hit[ 920] = (reg_addr == SCMI_RESERVED_1_C92_OFFSET); - addr_hit[ 921] = (reg_addr == SCMI_CHANNEL_STATUS_C92_OFFSET); - addr_hit[ 922] = (reg_addr == SCMI_RESERVED_2_C92_OFFSET); - addr_hit[ 923] = (reg_addr == SCMI_RESERVED_3_C92_OFFSET); - addr_hit[ 924] = (reg_addr == SCMI_CHANNEL_FLAGS_C92_OFFSET); - addr_hit[ 925] = (reg_addr == SCMI_LENGTH_C92_OFFSET); - addr_hit[ 926] = (reg_addr == SCMI_MESSAGE_HEADER_C92_OFFSET); - addr_hit[ 927] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C92_OFFSET); - addr_hit[ 928] = (reg_addr == SCMI_DOORBELL_C92_OFFSET); - addr_hit[ 929] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C92_OFFSET); - addr_hit[ 930] = (reg_addr == SCMI_RESERVED_1_C93_OFFSET); - addr_hit[ 931] = (reg_addr == SCMI_CHANNEL_STATUS_C93_OFFSET); - addr_hit[ 932] = (reg_addr == SCMI_RESERVED_2_C93_OFFSET); - addr_hit[ 933] = (reg_addr == SCMI_RESERVED_3_C93_OFFSET); - addr_hit[ 934] = (reg_addr == SCMI_CHANNEL_FLAGS_C93_OFFSET); - addr_hit[ 935] = (reg_addr == SCMI_LENGTH_C93_OFFSET); - addr_hit[ 936] = (reg_addr == SCMI_MESSAGE_HEADER_C93_OFFSET); - addr_hit[ 937] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C93_OFFSET); - addr_hit[ 938] = (reg_addr == SCMI_DOORBELL_C93_OFFSET); - addr_hit[ 939] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C93_OFFSET); - addr_hit[ 940] = (reg_addr == SCMI_RESERVED_1_C94_OFFSET); - addr_hit[ 941] = (reg_addr == SCMI_CHANNEL_STATUS_C94_OFFSET); - addr_hit[ 942] = (reg_addr == SCMI_RESERVED_2_C94_OFFSET); - addr_hit[ 943] = (reg_addr == SCMI_RESERVED_3_C94_OFFSET); - addr_hit[ 944] = (reg_addr == SCMI_CHANNEL_FLAGS_C94_OFFSET); - addr_hit[ 945] = (reg_addr == SCMI_LENGTH_C94_OFFSET); - addr_hit[ 946] = (reg_addr == SCMI_MESSAGE_HEADER_C94_OFFSET); - addr_hit[ 947] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C94_OFFSET); - addr_hit[ 948] = (reg_addr == SCMI_DOORBELL_C94_OFFSET); - addr_hit[ 949] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C94_OFFSET); - addr_hit[ 950] = (reg_addr == SCMI_RESERVED_1_C95_OFFSET); - addr_hit[ 951] = (reg_addr == SCMI_CHANNEL_STATUS_C95_OFFSET); - addr_hit[ 952] = (reg_addr == SCMI_RESERVED_2_C95_OFFSET); - addr_hit[ 953] = (reg_addr == SCMI_RESERVED_3_C95_OFFSET); - addr_hit[ 954] = (reg_addr == SCMI_CHANNEL_FLAGS_C95_OFFSET); - addr_hit[ 955] = (reg_addr == SCMI_LENGTH_C95_OFFSET); - addr_hit[ 956] = (reg_addr == SCMI_MESSAGE_HEADER_C95_OFFSET); - addr_hit[ 957] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C95_OFFSET); - addr_hit[ 958] = (reg_addr == SCMI_DOORBELL_C95_OFFSET); - addr_hit[ 959] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C95_OFFSET); - addr_hit[ 960] = (reg_addr == SCMI_RESERVED_1_C96_OFFSET); - addr_hit[ 961] = (reg_addr == SCMI_CHANNEL_STATUS_C96_OFFSET); - addr_hit[ 962] = (reg_addr == SCMI_RESERVED_2_C96_OFFSET); - addr_hit[ 963] = (reg_addr == SCMI_RESERVED_3_C96_OFFSET); - addr_hit[ 964] = (reg_addr == SCMI_CHANNEL_FLAGS_C96_OFFSET); - addr_hit[ 965] = (reg_addr == SCMI_LENGTH_C96_OFFSET); - addr_hit[ 966] = (reg_addr == SCMI_MESSAGE_HEADER_C96_OFFSET); - addr_hit[ 967] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C96_OFFSET); - addr_hit[ 968] = (reg_addr == SCMI_DOORBELL_C96_OFFSET); - addr_hit[ 969] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C96_OFFSET); - addr_hit[ 970] = (reg_addr == SCMI_RESERVED_1_C97_OFFSET); - addr_hit[ 971] = (reg_addr == SCMI_CHANNEL_STATUS_C97_OFFSET); - addr_hit[ 972] = (reg_addr == SCMI_RESERVED_2_C97_OFFSET); - addr_hit[ 973] = (reg_addr == SCMI_RESERVED_3_C97_OFFSET); - addr_hit[ 974] = (reg_addr == SCMI_CHANNEL_FLAGS_C97_OFFSET); - addr_hit[ 975] = (reg_addr == SCMI_LENGTH_C97_OFFSET); - addr_hit[ 976] = (reg_addr == SCMI_MESSAGE_HEADER_C97_OFFSET); - addr_hit[ 977] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C97_OFFSET); - addr_hit[ 978] = (reg_addr == SCMI_DOORBELL_C97_OFFSET); - addr_hit[ 979] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C97_OFFSET); - addr_hit[ 980] = (reg_addr == SCMI_RESERVED_1_C98_OFFSET); - addr_hit[ 981] = (reg_addr == SCMI_CHANNEL_STATUS_C98_OFFSET); - addr_hit[ 982] = (reg_addr == SCMI_RESERVED_2_C98_OFFSET); - addr_hit[ 983] = (reg_addr == SCMI_RESERVED_3_C98_OFFSET); - addr_hit[ 984] = (reg_addr == SCMI_CHANNEL_FLAGS_C98_OFFSET); - addr_hit[ 985] = (reg_addr == SCMI_LENGTH_C98_OFFSET); - addr_hit[ 986] = (reg_addr == SCMI_MESSAGE_HEADER_C98_OFFSET); - addr_hit[ 987] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C98_OFFSET); - addr_hit[ 988] = (reg_addr == SCMI_DOORBELL_C98_OFFSET); - addr_hit[ 989] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C98_OFFSET); - addr_hit[ 990] = (reg_addr == SCMI_RESERVED_1_C99_OFFSET); - addr_hit[ 991] = (reg_addr == SCMI_CHANNEL_STATUS_C99_OFFSET); - addr_hit[ 992] = (reg_addr == SCMI_RESERVED_2_C99_OFFSET); - addr_hit[ 993] = (reg_addr == SCMI_RESERVED_3_C99_OFFSET); - addr_hit[ 994] = (reg_addr == SCMI_CHANNEL_FLAGS_C99_OFFSET); - addr_hit[ 995] = (reg_addr == SCMI_LENGTH_C99_OFFSET); - addr_hit[ 996] = (reg_addr == SCMI_MESSAGE_HEADER_C99_OFFSET); - addr_hit[ 997] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C99_OFFSET); - addr_hit[ 998] = (reg_addr == SCMI_DOORBELL_C99_OFFSET); - addr_hit[ 999] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C99_OFFSET); - addr_hit[1000] = (reg_addr == SCMI_RESERVED_1_C100_OFFSET); - addr_hit[1001] = (reg_addr == SCMI_CHANNEL_STATUS_C100_OFFSET); - addr_hit[1002] = (reg_addr == SCMI_RESERVED_2_C100_OFFSET); - addr_hit[1003] = (reg_addr == SCMI_RESERVED_3_C100_OFFSET); - addr_hit[1004] = (reg_addr == SCMI_CHANNEL_FLAGS_C100_OFFSET); - addr_hit[1005] = (reg_addr == SCMI_LENGTH_C100_OFFSET); - addr_hit[1006] = (reg_addr == SCMI_MESSAGE_HEADER_C100_OFFSET); - addr_hit[1007] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C100_OFFSET); - addr_hit[1008] = (reg_addr == SCMI_DOORBELL_C100_OFFSET); - addr_hit[1009] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C100_OFFSET); - addr_hit[1010] = (reg_addr == SCMI_RESERVED_1_C101_OFFSET); - addr_hit[1011] = (reg_addr == SCMI_CHANNEL_STATUS_C101_OFFSET); - addr_hit[1012] = (reg_addr == SCMI_RESERVED_2_C101_OFFSET); - addr_hit[1013] = (reg_addr == SCMI_RESERVED_3_C101_OFFSET); - addr_hit[1014] = (reg_addr == SCMI_CHANNEL_FLAGS_C101_OFFSET); - addr_hit[1015] = (reg_addr == SCMI_LENGTH_C101_OFFSET); - addr_hit[1016] = (reg_addr == SCMI_MESSAGE_HEADER_C101_OFFSET); - addr_hit[1017] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C101_OFFSET); - addr_hit[1018] = (reg_addr == SCMI_DOORBELL_C101_OFFSET); - addr_hit[1019] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C101_OFFSET); - addr_hit[1020] = (reg_addr == SCMI_RESERVED_1_C102_OFFSET); - addr_hit[1021] = (reg_addr == SCMI_CHANNEL_STATUS_C102_OFFSET); - addr_hit[1022] = (reg_addr == SCMI_RESERVED_2_C102_OFFSET); - addr_hit[1023] = (reg_addr == SCMI_RESERVED_3_C102_OFFSET); - addr_hit[1024] = (reg_addr == SCMI_CHANNEL_FLAGS_C102_OFFSET); - addr_hit[1025] = (reg_addr == SCMI_LENGTH_C102_OFFSET); - addr_hit[1026] = (reg_addr == SCMI_MESSAGE_HEADER_C102_OFFSET); - addr_hit[1027] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C102_OFFSET); - addr_hit[1028] = (reg_addr == SCMI_DOORBELL_C102_OFFSET); - addr_hit[1029] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C102_OFFSET); - addr_hit[1030] = (reg_addr == SCMI_RESERVED_1_C103_OFFSET); - addr_hit[1031] = (reg_addr == SCMI_CHANNEL_STATUS_C103_OFFSET); - addr_hit[1032] = (reg_addr == SCMI_RESERVED_2_C103_OFFSET); - addr_hit[1033] = (reg_addr == SCMI_RESERVED_3_C103_OFFSET); - addr_hit[1034] = (reg_addr == SCMI_CHANNEL_FLAGS_C103_OFFSET); - addr_hit[1035] = (reg_addr == SCMI_LENGTH_C103_OFFSET); - addr_hit[1036] = (reg_addr == SCMI_MESSAGE_HEADER_C103_OFFSET); - addr_hit[1037] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C103_OFFSET); - addr_hit[1038] = (reg_addr == SCMI_DOORBELL_C103_OFFSET); - addr_hit[1039] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C103_OFFSET); - addr_hit[1040] = (reg_addr == SCMI_RESERVED_1_C104_OFFSET); - addr_hit[1041] = (reg_addr == SCMI_CHANNEL_STATUS_C104_OFFSET); - addr_hit[1042] = (reg_addr == SCMI_RESERVED_2_C104_OFFSET); - addr_hit[1043] = (reg_addr == SCMI_RESERVED_3_C104_OFFSET); - addr_hit[1044] = (reg_addr == SCMI_CHANNEL_FLAGS_C104_OFFSET); - addr_hit[1045] = (reg_addr == SCMI_LENGTH_C104_OFFSET); - addr_hit[1046] = (reg_addr == SCMI_MESSAGE_HEADER_C104_OFFSET); - addr_hit[1047] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C104_OFFSET); - addr_hit[1048] = (reg_addr == SCMI_DOORBELL_C104_OFFSET); - addr_hit[1049] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C104_OFFSET); - addr_hit[1050] = (reg_addr == SCMI_RESERVED_1_C105_OFFSET); - addr_hit[1051] = (reg_addr == SCMI_CHANNEL_STATUS_C105_OFFSET); - addr_hit[1052] = (reg_addr == SCMI_RESERVED_2_C105_OFFSET); - addr_hit[1053] = (reg_addr == SCMI_RESERVED_3_C105_OFFSET); - addr_hit[1054] = (reg_addr == SCMI_CHANNEL_FLAGS_C105_OFFSET); - addr_hit[1055] = (reg_addr == SCMI_LENGTH_C105_OFFSET); - addr_hit[1056] = (reg_addr == SCMI_MESSAGE_HEADER_C105_OFFSET); - addr_hit[1057] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C105_OFFSET); - addr_hit[1058] = (reg_addr == SCMI_DOORBELL_C105_OFFSET); - addr_hit[1059] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C105_OFFSET); - addr_hit[1060] = (reg_addr == SCMI_RESERVED_1_C106_OFFSET); - addr_hit[1061] = (reg_addr == SCMI_CHANNEL_STATUS_C106_OFFSET); - addr_hit[1062] = (reg_addr == SCMI_RESERVED_2_C106_OFFSET); - addr_hit[1063] = (reg_addr == SCMI_RESERVED_3_C106_OFFSET); - addr_hit[1064] = (reg_addr == SCMI_CHANNEL_FLAGS_C106_OFFSET); - addr_hit[1065] = (reg_addr == SCMI_LENGTH_C106_OFFSET); - addr_hit[1066] = (reg_addr == SCMI_MESSAGE_HEADER_C106_OFFSET); - addr_hit[1067] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C106_OFFSET); - addr_hit[1068] = (reg_addr == SCMI_DOORBELL_C106_OFFSET); - addr_hit[1069] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C106_OFFSET); - addr_hit[1070] = (reg_addr == SCMI_RESERVED_1_C107_OFFSET); - addr_hit[1071] = (reg_addr == SCMI_CHANNEL_STATUS_C107_OFFSET); - addr_hit[1072] = (reg_addr == SCMI_RESERVED_2_C107_OFFSET); - addr_hit[1073] = (reg_addr == SCMI_RESERVED_3_C107_OFFSET); - addr_hit[1074] = (reg_addr == SCMI_CHANNEL_FLAGS_C107_OFFSET); - addr_hit[1075] = (reg_addr == SCMI_LENGTH_C107_OFFSET); - addr_hit[1076] = (reg_addr == SCMI_MESSAGE_HEADER_C107_OFFSET); - addr_hit[1077] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C107_OFFSET); - addr_hit[1078] = (reg_addr == SCMI_DOORBELL_C107_OFFSET); - addr_hit[1079] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C107_OFFSET); - addr_hit[1080] = (reg_addr == SCMI_RESERVED_1_C108_OFFSET); - addr_hit[1081] = (reg_addr == SCMI_CHANNEL_STATUS_C108_OFFSET); - addr_hit[1082] = (reg_addr == SCMI_RESERVED_2_C108_OFFSET); - addr_hit[1083] = (reg_addr == SCMI_RESERVED_3_C108_OFFSET); - addr_hit[1084] = (reg_addr == SCMI_CHANNEL_FLAGS_C108_OFFSET); - addr_hit[1085] = (reg_addr == SCMI_LENGTH_C108_OFFSET); - addr_hit[1086] = (reg_addr == SCMI_MESSAGE_HEADER_C108_OFFSET); - addr_hit[1087] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C108_OFFSET); - addr_hit[1088] = (reg_addr == SCMI_DOORBELL_C108_OFFSET); - addr_hit[1089] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C108_OFFSET); - addr_hit[1090] = (reg_addr == SCMI_RESERVED_1_C109_OFFSET); - addr_hit[1091] = (reg_addr == SCMI_CHANNEL_STATUS_C109_OFFSET); - addr_hit[1092] = (reg_addr == SCMI_RESERVED_2_C109_OFFSET); - addr_hit[1093] = (reg_addr == SCMI_RESERVED_3_C109_OFFSET); - addr_hit[1094] = (reg_addr == SCMI_CHANNEL_FLAGS_C109_OFFSET); - addr_hit[1095] = (reg_addr == SCMI_LENGTH_C109_OFFSET); - addr_hit[1096] = (reg_addr == SCMI_MESSAGE_HEADER_C109_OFFSET); - addr_hit[1097] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C109_OFFSET); - addr_hit[1098] = (reg_addr == SCMI_DOORBELL_C109_OFFSET); - addr_hit[1099] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C109_OFFSET); - addr_hit[1100] = (reg_addr == SCMI_RESERVED_1_C110_OFFSET); - addr_hit[1101] = (reg_addr == SCMI_CHANNEL_STATUS_C110_OFFSET); - addr_hit[1102] = (reg_addr == SCMI_RESERVED_2_C110_OFFSET); - addr_hit[1103] = (reg_addr == SCMI_RESERVED_3_C110_OFFSET); - addr_hit[1104] = (reg_addr == SCMI_CHANNEL_FLAGS_C110_OFFSET); - addr_hit[1105] = (reg_addr == SCMI_LENGTH_C110_OFFSET); - addr_hit[1106] = (reg_addr == SCMI_MESSAGE_HEADER_C110_OFFSET); - addr_hit[1107] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C110_OFFSET); - addr_hit[1108] = (reg_addr == SCMI_DOORBELL_C110_OFFSET); - addr_hit[1109] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C110_OFFSET); - addr_hit[1110] = (reg_addr == SCMI_RESERVED_1_C111_OFFSET); - addr_hit[1111] = (reg_addr == SCMI_CHANNEL_STATUS_C111_OFFSET); - addr_hit[1112] = (reg_addr == SCMI_RESERVED_2_C111_OFFSET); - addr_hit[1113] = (reg_addr == SCMI_RESERVED_3_C111_OFFSET); - addr_hit[1114] = (reg_addr == SCMI_CHANNEL_FLAGS_C111_OFFSET); - addr_hit[1115] = (reg_addr == SCMI_LENGTH_C111_OFFSET); - addr_hit[1116] = (reg_addr == SCMI_MESSAGE_HEADER_C111_OFFSET); - addr_hit[1117] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C111_OFFSET); - addr_hit[1118] = (reg_addr == SCMI_DOORBELL_C111_OFFSET); - addr_hit[1119] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C111_OFFSET); - addr_hit[1120] = (reg_addr == SCMI_RESERVED_1_C112_OFFSET); - addr_hit[1121] = (reg_addr == SCMI_CHANNEL_STATUS_C112_OFFSET); - addr_hit[1122] = (reg_addr == SCMI_RESERVED_2_C112_OFFSET); - addr_hit[1123] = (reg_addr == SCMI_RESERVED_3_C112_OFFSET); - addr_hit[1124] = (reg_addr == SCMI_CHANNEL_FLAGS_C112_OFFSET); - addr_hit[1125] = (reg_addr == SCMI_LENGTH_C112_OFFSET); - addr_hit[1126] = (reg_addr == SCMI_MESSAGE_HEADER_C112_OFFSET); - addr_hit[1127] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C112_OFFSET); - addr_hit[1128] = (reg_addr == SCMI_DOORBELL_C112_OFFSET); - addr_hit[1129] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C112_OFFSET); - addr_hit[1130] = (reg_addr == SCMI_RESERVED_1_C113_OFFSET); - addr_hit[1131] = (reg_addr == SCMI_CHANNEL_STATUS_C113_OFFSET); - addr_hit[1132] = (reg_addr == SCMI_RESERVED_2_C113_OFFSET); - addr_hit[1133] = (reg_addr == SCMI_RESERVED_3_C113_OFFSET); - addr_hit[1134] = (reg_addr == SCMI_CHANNEL_FLAGS_C113_OFFSET); - addr_hit[1135] = (reg_addr == SCMI_LENGTH_C113_OFFSET); - addr_hit[1136] = (reg_addr == SCMI_MESSAGE_HEADER_C113_OFFSET); - addr_hit[1137] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C113_OFFSET); - addr_hit[1138] = (reg_addr == SCMI_DOORBELL_C113_OFFSET); - addr_hit[1139] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C113_OFFSET); - addr_hit[1140] = (reg_addr == SCMI_RESERVED_1_C114_OFFSET); - addr_hit[1141] = (reg_addr == SCMI_CHANNEL_STATUS_C114_OFFSET); - addr_hit[1142] = (reg_addr == SCMI_RESERVED_2_C114_OFFSET); - addr_hit[1143] = (reg_addr == SCMI_RESERVED_3_C114_OFFSET); - addr_hit[1144] = (reg_addr == SCMI_CHANNEL_FLAGS_C114_OFFSET); - addr_hit[1145] = (reg_addr == SCMI_LENGTH_C114_OFFSET); - addr_hit[1146] = (reg_addr == SCMI_MESSAGE_HEADER_C114_OFFSET); - addr_hit[1147] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C114_OFFSET); - addr_hit[1148] = (reg_addr == SCMI_DOORBELL_C114_OFFSET); - addr_hit[1149] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C114_OFFSET); - addr_hit[1150] = (reg_addr == SCMI_RESERVED_1_C115_OFFSET); - addr_hit[1151] = (reg_addr == SCMI_CHANNEL_STATUS_C115_OFFSET); - addr_hit[1152] = (reg_addr == SCMI_RESERVED_2_C115_OFFSET); - addr_hit[1153] = (reg_addr == SCMI_RESERVED_3_C115_OFFSET); - addr_hit[1154] = (reg_addr == SCMI_CHANNEL_FLAGS_C115_OFFSET); - addr_hit[1155] = (reg_addr == SCMI_LENGTH_C115_OFFSET); - addr_hit[1156] = (reg_addr == SCMI_MESSAGE_HEADER_C115_OFFSET); - addr_hit[1157] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C115_OFFSET); - addr_hit[1158] = (reg_addr == SCMI_DOORBELL_C115_OFFSET); - addr_hit[1159] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C115_OFFSET); - addr_hit[1160] = (reg_addr == SCMI_RESERVED_1_C116_OFFSET); - addr_hit[1161] = (reg_addr == SCMI_CHANNEL_STATUS_C116_OFFSET); - addr_hit[1162] = (reg_addr == SCMI_RESERVED_2_C116_OFFSET); - addr_hit[1163] = (reg_addr == SCMI_RESERVED_3_C116_OFFSET); - addr_hit[1164] = (reg_addr == SCMI_CHANNEL_FLAGS_C116_OFFSET); - addr_hit[1165] = (reg_addr == SCMI_LENGTH_C116_OFFSET); - addr_hit[1166] = (reg_addr == SCMI_MESSAGE_HEADER_C116_OFFSET); - addr_hit[1167] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C116_OFFSET); - addr_hit[1168] = (reg_addr == SCMI_DOORBELL_C116_OFFSET); - addr_hit[1169] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C116_OFFSET); - addr_hit[1170] = (reg_addr == SCMI_RESERVED_1_C117_OFFSET); - addr_hit[1171] = (reg_addr == SCMI_CHANNEL_STATUS_C117_OFFSET); - addr_hit[1172] = (reg_addr == SCMI_RESERVED_2_C117_OFFSET); - addr_hit[1173] = (reg_addr == SCMI_RESERVED_3_C117_OFFSET); - addr_hit[1174] = (reg_addr == SCMI_CHANNEL_FLAGS_C117_OFFSET); - addr_hit[1175] = (reg_addr == SCMI_LENGTH_C117_OFFSET); - addr_hit[1176] = (reg_addr == SCMI_MESSAGE_HEADER_C117_OFFSET); - addr_hit[1177] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C117_OFFSET); - addr_hit[1178] = (reg_addr == SCMI_DOORBELL_C117_OFFSET); - addr_hit[1179] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C117_OFFSET); - addr_hit[1180] = (reg_addr == SCMI_RESERVED_1_C118_OFFSET); - addr_hit[1181] = (reg_addr == SCMI_CHANNEL_STATUS_C118_OFFSET); - addr_hit[1182] = (reg_addr == SCMI_RESERVED_2_C118_OFFSET); - addr_hit[1183] = (reg_addr == SCMI_RESERVED_3_C118_OFFSET); - addr_hit[1184] = (reg_addr == SCMI_CHANNEL_FLAGS_C118_OFFSET); - addr_hit[1185] = (reg_addr == SCMI_LENGTH_C118_OFFSET); - addr_hit[1186] = (reg_addr == SCMI_MESSAGE_HEADER_C118_OFFSET); - addr_hit[1187] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C118_OFFSET); - addr_hit[1188] = (reg_addr == SCMI_DOORBELL_C118_OFFSET); - addr_hit[1189] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C118_OFFSET); - addr_hit[1190] = (reg_addr == SCMI_RESERVED_1_C119_OFFSET); - addr_hit[1191] = (reg_addr == SCMI_CHANNEL_STATUS_C119_OFFSET); - addr_hit[1192] = (reg_addr == SCMI_RESERVED_2_C119_OFFSET); - addr_hit[1193] = (reg_addr == SCMI_RESERVED_3_C119_OFFSET); - addr_hit[1194] = (reg_addr == SCMI_CHANNEL_FLAGS_C119_OFFSET); - addr_hit[1195] = (reg_addr == SCMI_LENGTH_C119_OFFSET); - addr_hit[1196] = (reg_addr == SCMI_MESSAGE_HEADER_C119_OFFSET); - addr_hit[1197] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C119_OFFSET); - addr_hit[1198] = (reg_addr == SCMI_DOORBELL_C119_OFFSET); - addr_hit[1199] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C119_OFFSET); - addr_hit[1200] = (reg_addr == SCMI_RESERVED_1_C120_OFFSET); - addr_hit[1201] = (reg_addr == SCMI_CHANNEL_STATUS_C120_OFFSET); - addr_hit[1202] = (reg_addr == SCMI_RESERVED_2_C120_OFFSET); - addr_hit[1203] = (reg_addr == SCMI_RESERVED_3_C120_OFFSET); - addr_hit[1204] = (reg_addr == SCMI_CHANNEL_FLAGS_C120_OFFSET); - addr_hit[1205] = (reg_addr == SCMI_LENGTH_C120_OFFSET); - addr_hit[1206] = (reg_addr == SCMI_MESSAGE_HEADER_C120_OFFSET); - addr_hit[1207] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C120_OFFSET); - addr_hit[1208] = (reg_addr == SCMI_DOORBELL_C120_OFFSET); - addr_hit[1209] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C120_OFFSET); - addr_hit[1210] = (reg_addr == SCMI_RESERVED_1_C121_OFFSET); - addr_hit[1211] = (reg_addr == SCMI_CHANNEL_STATUS_C121_OFFSET); - addr_hit[1212] = (reg_addr == SCMI_RESERVED_2_C121_OFFSET); - addr_hit[1213] = (reg_addr == SCMI_RESERVED_3_C121_OFFSET); - addr_hit[1214] = (reg_addr == SCMI_CHANNEL_FLAGS_C121_OFFSET); - addr_hit[1215] = (reg_addr == SCMI_LENGTH_C121_OFFSET); - addr_hit[1216] = (reg_addr == SCMI_MESSAGE_HEADER_C121_OFFSET); - addr_hit[1217] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C121_OFFSET); - addr_hit[1218] = (reg_addr == SCMI_DOORBELL_C121_OFFSET); - addr_hit[1219] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C121_OFFSET); - addr_hit[1220] = (reg_addr == SCMI_RESERVED_1_C122_OFFSET); - addr_hit[1221] = (reg_addr == SCMI_CHANNEL_STATUS_C122_OFFSET); - addr_hit[1222] = (reg_addr == SCMI_RESERVED_2_C122_OFFSET); - addr_hit[1223] = (reg_addr == SCMI_RESERVED_3_C122_OFFSET); - addr_hit[1224] = (reg_addr == SCMI_CHANNEL_FLAGS_C122_OFFSET); - addr_hit[1225] = (reg_addr == SCMI_LENGTH_C122_OFFSET); - addr_hit[1226] = (reg_addr == SCMI_MESSAGE_HEADER_C122_OFFSET); - addr_hit[1227] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C122_OFFSET); - addr_hit[1228] = (reg_addr == SCMI_DOORBELL_C122_OFFSET); - addr_hit[1229] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C122_OFFSET); - addr_hit[1230] = (reg_addr == SCMI_RESERVED_1_C123_OFFSET); - addr_hit[1231] = (reg_addr == SCMI_CHANNEL_STATUS_C123_OFFSET); - addr_hit[1232] = (reg_addr == SCMI_RESERVED_2_C123_OFFSET); - addr_hit[1233] = (reg_addr == SCMI_RESERVED_3_C123_OFFSET); - addr_hit[1234] = (reg_addr == SCMI_CHANNEL_FLAGS_C123_OFFSET); - addr_hit[1235] = (reg_addr == SCMI_LENGTH_C123_OFFSET); - addr_hit[1236] = (reg_addr == SCMI_MESSAGE_HEADER_C123_OFFSET); - addr_hit[1237] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C123_OFFSET); - addr_hit[1238] = (reg_addr == SCMI_DOORBELL_C123_OFFSET); - addr_hit[1239] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C123_OFFSET); - addr_hit[1240] = (reg_addr == SCMI_RESERVED_1_C124_OFFSET); - addr_hit[1241] = (reg_addr == SCMI_CHANNEL_STATUS_C124_OFFSET); - addr_hit[1242] = (reg_addr == SCMI_RESERVED_2_C124_OFFSET); - addr_hit[1243] = (reg_addr == SCMI_RESERVED_3_C124_OFFSET); - addr_hit[1244] = (reg_addr == SCMI_CHANNEL_FLAGS_C124_OFFSET); - addr_hit[1245] = (reg_addr == SCMI_LENGTH_C124_OFFSET); - addr_hit[1246] = (reg_addr == SCMI_MESSAGE_HEADER_C124_OFFSET); - addr_hit[1247] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C124_OFFSET); - addr_hit[1248] = (reg_addr == SCMI_DOORBELL_C124_OFFSET); - addr_hit[1249] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C124_OFFSET); - addr_hit[1250] = (reg_addr == SCMI_RESERVED_1_C125_OFFSET); - addr_hit[1251] = (reg_addr == SCMI_CHANNEL_STATUS_C125_OFFSET); - addr_hit[1252] = (reg_addr == SCMI_RESERVED_2_C125_OFFSET); - addr_hit[1253] = (reg_addr == SCMI_RESERVED_3_C125_OFFSET); - addr_hit[1254] = (reg_addr == SCMI_CHANNEL_FLAGS_C125_OFFSET); - addr_hit[1255] = (reg_addr == SCMI_LENGTH_C125_OFFSET); - addr_hit[1256] = (reg_addr == SCMI_MESSAGE_HEADER_C125_OFFSET); - addr_hit[1257] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C125_OFFSET); - addr_hit[1258] = (reg_addr == SCMI_DOORBELL_C125_OFFSET); - addr_hit[1259] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C125_OFFSET); - addr_hit[1260] = (reg_addr == SCMI_RESERVED_1_C126_OFFSET); - addr_hit[1261] = (reg_addr == SCMI_CHANNEL_STATUS_C126_OFFSET); - addr_hit[1262] = (reg_addr == SCMI_RESERVED_2_C126_OFFSET); - addr_hit[1263] = (reg_addr == SCMI_RESERVED_3_C126_OFFSET); - addr_hit[1264] = (reg_addr == SCMI_CHANNEL_FLAGS_C126_OFFSET); - addr_hit[1265] = (reg_addr == SCMI_LENGTH_C126_OFFSET); - addr_hit[1266] = (reg_addr == SCMI_MESSAGE_HEADER_C126_OFFSET); - addr_hit[1267] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C126_OFFSET); - addr_hit[1268] = (reg_addr == SCMI_DOORBELL_C126_OFFSET); - addr_hit[1269] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C126_OFFSET); - addr_hit[1270] = (reg_addr == SCMI_RESERVED_1_C127_OFFSET); - addr_hit[1271] = (reg_addr == SCMI_CHANNEL_STATUS_C127_OFFSET); - addr_hit[1272] = (reg_addr == SCMI_RESERVED_2_C127_OFFSET); - addr_hit[1273] = (reg_addr == SCMI_RESERVED_3_C127_OFFSET); - addr_hit[1274] = (reg_addr == SCMI_CHANNEL_FLAGS_C127_OFFSET); - addr_hit[1275] = (reg_addr == SCMI_LENGTH_C127_OFFSET); - addr_hit[1276] = (reg_addr == SCMI_MESSAGE_HEADER_C127_OFFSET); - addr_hit[1277] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C127_OFFSET); - addr_hit[1278] = (reg_addr == SCMI_DOORBELL_C127_OFFSET); - addr_hit[1279] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C127_OFFSET); - addr_hit[1280] = (reg_addr == SCMI_RESERVED_1_C128_OFFSET); - addr_hit[1281] = (reg_addr == SCMI_CHANNEL_STATUS_C128_OFFSET); - addr_hit[1282] = (reg_addr == SCMI_RESERVED_2_C128_OFFSET); - addr_hit[1283] = (reg_addr == SCMI_RESERVED_3_C128_OFFSET); - addr_hit[1284] = (reg_addr == SCMI_CHANNEL_FLAGS_C128_OFFSET); - addr_hit[1285] = (reg_addr == SCMI_LENGTH_C128_OFFSET); - addr_hit[1286] = (reg_addr == SCMI_MESSAGE_HEADER_C128_OFFSET); - addr_hit[1287] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C128_OFFSET); - addr_hit[1288] = (reg_addr == SCMI_DOORBELL_C128_OFFSET); - addr_hit[1289] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C128_OFFSET); - addr_hit[1290] = (reg_addr == SCMI_RESERVED_1_C129_OFFSET); - addr_hit[1291] = (reg_addr == SCMI_CHANNEL_STATUS_C129_OFFSET); - addr_hit[1292] = (reg_addr == SCMI_RESERVED_2_C129_OFFSET); - addr_hit[1293] = (reg_addr == SCMI_RESERVED_3_C129_OFFSET); - addr_hit[1294] = (reg_addr == SCMI_CHANNEL_FLAGS_C129_OFFSET); - addr_hit[1295] = (reg_addr == SCMI_LENGTH_C129_OFFSET); - addr_hit[1296] = (reg_addr == SCMI_MESSAGE_HEADER_C129_OFFSET); - addr_hit[1297] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C129_OFFSET); - addr_hit[1298] = (reg_addr == SCMI_DOORBELL_C129_OFFSET); - addr_hit[1299] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C129_OFFSET); - addr_hit[1300] = (reg_addr == SCMI_RESERVED_1_C130_OFFSET); - addr_hit[1301] = (reg_addr == SCMI_CHANNEL_STATUS_C130_OFFSET); - addr_hit[1302] = (reg_addr == SCMI_RESERVED_2_C130_OFFSET); - addr_hit[1303] = (reg_addr == SCMI_RESERVED_3_C130_OFFSET); - addr_hit[1304] = (reg_addr == SCMI_CHANNEL_FLAGS_C130_OFFSET); - addr_hit[1305] = (reg_addr == SCMI_LENGTH_C130_OFFSET); - addr_hit[1306] = (reg_addr == SCMI_MESSAGE_HEADER_C130_OFFSET); - addr_hit[1307] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C130_OFFSET); - addr_hit[1308] = (reg_addr == SCMI_DOORBELL_C130_OFFSET); - addr_hit[1309] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C130_OFFSET); - addr_hit[1310] = (reg_addr == SCMI_RESERVED_1_C131_OFFSET); - addr_hit[1311] = (reg_addr == SCMI_CHANNEL_STATUS_C131_OFFSET); - addr_hit[1312] = (reg_addr == SCMI_RESERVED_2_C131_OFFSET); - addr_hit[1313] = (reg_addr == SCMI_RESERVED_3_C131_OFFSET); - addr_hit[1314] = (reg_addr == SCMI_CHANNEL_FLAGS_C131_OFFSET); - addr_hit[1315] = (reg_addr == SCMI_LENGTH_C131_OFFSET); - addr_hit[1316] = (reg_addr == SCMI_MESSAGE_HEADER_C131_OFFSET); - addr_hit[1317] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C131_OFFSET); - addr_hit[1318] = (reg_addr == SCMI_DOORBELL_C131_OFFSET); - addr_hit[1319] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C131_OFFSET); - addr_hit[1320] = (reg_addr == SCMI_RESERVED_1_C132_OFFSET); - addr_hit[1321] = (reg_addr == SCMI_CHANNEL_STATUS_C132_OFFSET); - addr_hit[1322] = (reg_addr == SCMI_RESERVED_2_C132_OFFSET); - addr_hit[1323] = (reg_addr == SCMI_RESERVED_3_C132_OFFSET); - addr_hit[1324] = (reg_addr == SCMI_CHANNEL_FLAGS_C132_OFFSET); - addr_hit[1325] = (reg_addr == SCMI_LENGTH_C132_OFFSET); - addr_hit[1326] = (reg_addr == SCMI_MESSAGE_HEADER_C132_OFFSET); - addr_hit[1327] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C132_OFFSET); - addr_hit[1328] = (reg_addr == SCMI_DOORBELL_C132_OFFSET); - addr_hit[1329] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C132_OFFSET); - addr_hit[1330] = (reg_addr == SCMI_RESERVED_1_C133_OFFSET); - addr_hit[1331] = (reg_addr == SCMI_CHANNEL_STATUS_C133_OFFSET); - addr_hit[1332] = (reg_addr == SCMI_RESERVED_2_C133_OFFSET); - addr_hit[1333] = (reg_addr == SCMI_RESERVED_3_C133_OFFSET); - addr_hit[1334] = (reg_addr == SCMI_CHANNEL_FLAGS_C133_OFFSET); - addr_hit[1335] = (reg_addr == SCMI_LENGTH_C133_OFFSET); - addr_hit[1336] = (reg_addr == SCMI_MESSAGE_HEADER_C133_OFFSET); - addr_hit[1337] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C133_OFFSET); - addr_hit[1338] = (reg_addr == SCMI_DOORBELL_C133_OFFSET); - addr_hit[1339] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C133_OFFSET); - addr_hit[1340] = (reg_addr == SCMI_RESERVED_1_C134_OFFSET); - addr_hit[1341] = (reg_addr == SCMI_CHANNEL_STATUS_C134_OFFSET); - addr_hit[1342] = (reg_addr == SCMI_RESERVED_2_C134_OFFSET); - addr_hit[1343] = (reg_addr == SCMI_RESERVED_3_C134_OFFSET); - addr_hit[1344] = (reg_addr == SCMI_CHANNEL_FLAGS_C134_OFFSET); - addr_hit[1345] = (reg_addr == SCMI_LENGTH_C134_OFFSET); - addr_hit[1346] = (reg_addr == SCMI_MESSAGE_HEADER_C134_OFFSET); - addr_hit[1347] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C134_OFFSET); - addr_hit[1348] = (reg_addr == SCMI_DOORBELL_C134_OFFSET); - addr_hit[1349] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C134_OFFSET); - addr_hit[1350] = (reg_addr == SCMI_RESERVED_1_C135_OFFSET); - addr_hit[1351] = (reg_addr == SCMI_CHANNEL_STATUS_C135_OFFSET); - addr_hit[1352] = (reg_addr == SCMI_RESERVED_2_C135_OFFSET); - addr_hit[1353] = (reg_addr == SCMI_RESERVED_3_C135_OFFSET); - addr_hit[1354] = (reg_addr == SCMI_CHANNEL_FLAGS_C135_OFFSET); - addr_hit[1355] = (reg_addr == SCMI_LENGTH_C135_OFFSET); - addr_hit[1356] = (reg_addr == SCMI_MESSAGE_HEADER_C135_OFFSET); - addr_hit[1357] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C135_OFFSET); - addr_hit[1358] = (reg_addr == SCMI_DOORBELL_C135_OFFSET); - addr_hit[1359] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C135_OFFSET); - addr_hit[1360] = (reg_addr == SCMI_RESERVED_1_C136_OFFSET); - addr_hit[1361] = (reg_addr == SCMI_CHANNEL_STATUS_C136_OFFSET); - addr_hit[1362] = (reg_addr == SCMI_RESERVED_2_C136_OFFSET); - addr_hit[1363] = (reg_addr == SCMI_RESERVED_3_C136_OFFSET); - addr_hit[1364] = (reg_addr == SCMI_CHANNEL_FLAGS_C136_OFFSET); - addr_hit[1365] = (reg_addr == SCMI_LENGTH_C136_OFFSET); - addr_hit[1366] = (reg_addr == SCMI_MESSAGE_HEADER_C136_OFFSET); - addr_hit[1367] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C136_OFFSET); - addr_hit[1368] = (reg_addr == SCMI_DOORBELL_C136_OFFSET); - addr_hit[1369] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C136_OFFSET); - addr_hit[1370] = (reg_addr == SCMI_RESERVED_1_C137_OFFSET); - addr_hit[1371] = (reg_addr == SCMI_CHANNEL_STATUS_C137_OFFSET); - addr_hit[1372] = (reg_addr == SCMI_RESERVED_2_C137_OFFSET); - addr_hit[1373] = (reg_addr == SCMI_RESERVED_3_C137_OFFSET); - addr_hit[1374] = (reg_addr == SCMI_CHANNEL_FLAGS_C137_OFFSET); - addr_hit[1375] = (reg_addr == SCMI_LENGTH_C137_OFFSET); - addr_hit[1376] = (reg_addr == SCMI_MESSAGE_HEADER_C137_OFFSET); - addr_hit[1377] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C137_OFFSET); - addr_hit[1378] = (reg_addr == SCMI_DOORBELL_C137_OFFSET); - addr_hit[1379] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C137_OFFSET); - addr_hit[1380] = (reg_addr == SCMI_RESERVED_1_C138_OFFSET); - addr_hit[1381] = (reg_addr == SCMI_CHANNEL_STATUS_C138_OFFSET); - addr_hit[1382] = (reg_addr == SCMI_RESERVED_2_C138_OFFSET); - addr_hit[1383] = (reg_addr == SCMI_RESERVED_3_C138_OFFSET); - addr_hit[1384] = (reg_addr == SCMI_CHANNEL_FLAGS_C138_OFFSET); - addr_hit[1385] = (reg_addr == SCMI_LENGTH_C138_OFFSET); - addr_hit[1386] = (reg_addr == SCMI_MESSAGE_HEADER_C138_OFFSET); - addr_hit[1387] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C138_OFFSET); - addr_hit[1388] = (reg_addr == SCMI_DOORBELL_C138_OFFSET); - addr_hit[1389] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C138_OFFSET); - addr_hit[1390] = (reg_addr == SCMI_RESERVED_1_C139_OFFSET); - addr_hit[1391] = (reg_addr == SCMI_CHANNEL_STATUS_C139_OFFSET); - addr_hit[1392] = (reg_addr == SCMI_RESERVED_2_C139_OFFSET); - addr_hit[1393] = (reg_addr == SCMI_RESERVED_3_C139_OFFSET); - addr_hit[1394] = (reg_addr == SCMI_CHANNEL_FLAGS_C139_OFFSET); - addr_hit[1395] = (reg_addr == SCMI_LENGTH_C139_OFFSET); - addr_hit[1396] = (reg_addr == SCMI_MESSAGE_HEADER_C139_OFFSET); - addr_hit[1397] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C139_OFFSET); - addr_hit[1398] = (reg_addr == SCMI_DOORBELL_C139_OFFSET); - addr_hit[1399] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C139_OFFSET); - addr_hit[1400] = (reg_addr == SCMI_RESERVED_1_C140_OFFSET); - addr_hit[1401] = (reg_addr == SCMI_CHANNEL_STATUS_C140_OFFSET); - addr_hit[1402] = (reg_addr == SCMI_RESERVED_2_C140_OFFSET); - addr_hit[1403] = (reg_addr == SCMI_RESERVED_3_C140_OFFSET); - addr_hit[1404] = (reg_addr == SCMI_CHANNEL_FLAGS_C140_OFFSET); - addr_hit[1405] = (reg_addr == SCMI_LENGTH_C140_OFFSET); - addr_hit[1406] = (reg_addr == SCMI_MESSAGE_HEADER_C140_OFFSET); - addr_hit[1407] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C140_OFFSET); - addr_hit[1408] = (reg_addr == SCMI_DOORBELL_C140_OFFSET); - addr_hit[1409] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C140_OFFSET); - addr_hit[1410] = (reg_addr == SCMI_RESERVED_1_C141_OFFSET); - addr_hit[1411] = (reg_addr == SCMI_CHANNEL_STATUS_C141_OFFSET); - addr_hit[1412] = (reg_addr == SCMI_RESERVED_2_C141_OFFSET); - addr_hit[1413] = (reg_addr == SCMI_RESERVED_3_C141_OFFSET); - addr_hit[1414] = (reg_addr == SCMI_CHANNEL_FLAGS_C141_OFFSET); - addr_hit[1415] = (reg_addr == SCMI_LENGTH_C141_OFFSET); - addr_hit[1416] = (reg_addr == SCMI_MESSAGE_HEADER_C141_OFFSET); - addr_hit[1417] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C141_OFFSET); - addr_hit[1418] = (reg_addr == SCMI_DOORBELL_C141_OFFSET); - addr_hit[1419] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C141_OFFSET); - addr_hit[1420] = (reg_addr == SCMI_RESERVED_1_C142_OFFSET); - addr_hit[1421] = (reg_addr == SCMI_CHANNEL_STATUS_C142_OFFSET); - addr_hit[1422] = (reg_addr == SCMI_RESERVED_2_C142_OFFSET); - addr_hit[1423] = (reg_addr == SCMI_RESERVED_3_C142_OFFSET); - addr_hit[1424] = (reg_addr == SCMI_CHANNEL_FLAGS_C142_OFFSET); - addr_hit[1425] = (reg_addr == SCMI_LENGTH_C142_OFFSET); - addr_hit[1426] = (reg_addr == SCMI_MESSAGE_HEADER_C142_OFFSET); - addr_hit[1427] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C142_OFFSET); - addr_hit[1428] = (reg_addr == SCMI_DOORBELL_C142_OFFSET); - addr_hit[1429] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C142_OFFSET); - addr_hit[1430] = (reg_addr == SCMI_RESERVED_1_C143_OFFSET); - addr_hit[1431] = (reg_addr == SCMI_CHANNEL_STATUS_C143_OFFSET); - addr_hit[1432] = (reg_addr == SCMI_RESERVED_2_C143_OFFSET); - addr_hit[1433] = (reg_addr == SCMI_RESERVED_3_C143_OFFSET); - addr_hit[1434] = (reg_addr == SCMI_CHANNEL_FLAGS_C143_OFFSET); - addr_hit[1435] = (reg_addr == SCMI_LENGTH_C143_OFFSET); - addr_hit[1436] = (reg_addr == SCMI_MESSAGE_HEADER_C143_OFFSET); - addr_hit[1437] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C143_OFFSET); - addr_hit[1438] = (reg_addr == SCMI_DOORBELL_C143_OFFSET); - addr_hit[1439] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C143_OFFSET); - addr_hit[1440] = (reg_addr == SCMI_RESERVED_1_C144_OFFSET); - addr_hit[1441] = (reg_addr == SCMI_CHANNEL_STATUS_C144_OFFSET); - addr_hit[1442] = (reg_addr == SCMI_RESERVED_2_C144_OFFSET); - addr_hit[1443] = (reg_addr == SCMI_RESERVED_3_C144_OFFSET); - addr_hit[1444] = (reg_addr == SCMI_CHANNEL_FLAGS_C144_OFFSET); - addr_hit[1445] = (reg_addr == SCMI_LENGTH_C144_OFFSET); - addr_hit[1446] = (reg_addr == SCMI_MESSAGE_HEADER_C144_OFFSET); - addr_hit[1447] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C144_OFFSET); - addr_hit[1448] = (reg_addr == SCMI_DOORBELL_C144_OFFSET); - addr_hit[1449] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C144_OFFSET); - addr_hit[1450] = (reg_addr == SCMI_RESERVED_1_C145_OFFSET); - addr_hit[1451] = (reg_addr == SCMI_CHANNEL_STATUS_C145_OFFSET); - addr_hit[1452] = (reg_addr == SCMI_RESERVED_2_C145_OFFSET); - addr_hit[1453] = (reg_addr == SCMI_RESERVED_3_C145_OFFSET); - addr_hit[1454] = (reg_addr == SCMI_CHANNEL_FLAGS_C145_OFFSET); - addr_hit[1455] = (reg_addr == SCMI_LENGTH_C145_OFFSET); - addr_hit[1456] = (reg_addr == SCMI_MESSAGE_HEADER_C145_OFFSET); - addr_hit[1457] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C145_OFFSET); - addr_hit[1458] = (reg_addr == SCMI_DOORBELL_C145_OFFSET); - addr_hit[1459] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C145_OFFSET); - addr_hit[1460] = (reg_addr == SCMI_RESERVED_1_C146_OFFSET); - addr_hit[1461] = (reg_addr == SCMI_CHANNEL_STATUS_C146_OFFSET); - addr_hit[1462] = (reg_addr == SCMI_RESERVED_2_C146_OFFSET); - addr_hit[1463] = (reg_addr == SCMI_RESERVED_3_C146_OFFSET); - addr_hit[1464] = (reg_addr == SCMI_CHANNEL_FLAGS_C146_OFFSET); - addr_hit[1465] = (reg_addr == SCMI_LENGTH_C146_OFFSET); - addr_hit[1466] = (reg_addr == SCMI_MESSAGE_HEADER_C146_OFFSET); - addr_hit[1467] = (reg_addr == SCMI_MESSAGE_PAYLOAD_1_C146_OFFSET); - addr_hit[1468] = (reg_addr == SCMI_DOORBELL_C146_OFFSET); - addr_hit[1469] = (reg_addr == SCMI_COMPLETION_INTERRUPT_C146_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(SCMI_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(SCMI_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(SCMI_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(SCMI_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(SCMI_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(SCMI_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(SCMI_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(SCMI_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(SCMI_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(SCMI_PERMIT[ 9] & ~reg_be))) | - (addr_hit[ 10] & (|(SCMI_PERMIT[ 10] & ~reg_be))) | - (addr_hit[ 11] & (|(SCMI_PERMIT[ 11] & ~reg_be))) | - (addr_hit[ 12] & (|(SCMI_PERMIT[ 12] & ~reg_be))) | - (addr_hit[ 13] & (|(SCMI_PERMIT[ 13] & ~reg_be))) | - (addr_hit[ 14] & (|(SCMI_PERMIT[ 14] & ~reg_be))) | - (addr_hit[ 15] & (|(SCMI_PERMIT[ 15] & ~reg_be))) | - (addr_hit[ 16] & (|(SCMI_PERMIT[ 16] & ~reg_be))) | - (addr_hit[ 17] & (|(SCMI_PERMIT[ 17] & ~reg_be))) | - (addr_hit[ 18] & (|(SCMI_PERMIT[ 18] & ~reg_be))) | - (addr_hit[ 19] & (|(SCMI_PERMIT[ 19] & ~reg_be))) | - (addr_hit[ 20] & (|(SCMI_PERMIT[ 20] & ~reg_be))) | - (addr_hit[ 21] & (|(SCMI_PERMIT[ 21] & ~reg_be))) | - (addr_hit[ 22] & (|(SCMI_PERMIT[ 22] & ~reg_be))) | - (addr_hit[ 23] & (|(SCMI_PERMIT[ 23] & ~reg_be))) | - (addr_hit[ 24] & (|(SCMI_PERMIT[ 24] & ~reg_be))) | - (addr_hit[ 25] & (|(SCMI_PERMIT[ 25] & ~reg_be))) | - (addr_hit[ 26] & (|(SCMI_PERMIT[ 26] & ~reg_be))) | - (addr_hit[ 27] & (|(SCMI_PERMIT[ 27] & ~reg_be))) | - (addr_hit[ 28] & (|(SCMI_PERMIT[ 28] & ~reg_be))) | - (addr_hit[ 29] & (|(SCMI_PERMIT[ 29] & ~reg_be))) | - (addr_hit[ 30] & (|(SCMI_PERMIT[ 30] & ~reg_be))) | - (addr_hit[ 31] & (|(SCMI_PERMIT[ 31] & ~reg_be))) | - (addr_hit[ 32] & (|(SCMI_PERMIT[ 32] & ~reg_be))) | - (addr_hit[ 33] & (|(SCMI_PERMIT[ 33] & ~reg_be))) | - (addr_hit[ 34] & (|(SCMI_PERMIT[ 34] & ~reg_be))) | - (addr_hit[ 35] & (|(SCMI_PERMIT[ 35] & ~reg_be))) | - (addr_hit[ 36] & (|(SCMI_PERMIT[ 36] & ~reg_be))) | - (addr_hit[ 37] & (|(SCMI_PERMIT[ 37] & ~reg_be))) | - (addr_hit[ 38] & (|(SCMI_PERMIT[ 38] & ~reg_be))) | - (addr_hit[ 39] & (|(SCMI_PERMIT[ 39] & ~reg_be))) | - (addr_hit[ 40] & (|(SCMI_PERMIT[ 40] & ~reg_be))) | - (addr_hit[ 41] & (|(SCMI_PERMIT[ 41] & ~reg_be))) | - (addr_hit[ 42] & (|(SCMI_PERMIT[ 42] & ~reg_be))) | - (addr_hit[ 43] & (|(SCMI_PERMIT[ 43] & ~reg_be))) | - (addr_hit[ 44] & (|(SCMI_PERMIT[ 44] & ~reg_be))) | - (addr_hit[ 45] & (|(SCMI_PERMIT[ 45] & ~reg_be))) | - (addr_hit[ 46] & (|(SCMI_PERMIT[ 46] & ~reg_be))) | - (addr_hit[ 47] & (|(SCMI_PERMIT[ 47] & ~reg_be))) | - (addr_hit[ 48] & (|(SCMI_PERMIT[ 48] & ~reg_be))) | - (addr_hit[ 49] & (|(SCMI_PERMIT[ 49] & ~reg_be))) | - (addr_hit[ 50] & (|(SCMI_PERMIT[ 50] & ~reg_be))) | - (addr_hit[ 51] & (|(SCMI_PERMIT[ 51] & ~reg_be))) | - (addr_hit[ 52] & (|(SCMI_PERMIT[ 52] & ~reg_be))) | - (addr_hit[ 53] & (|(SCMI_PERMIT[ 53] & ~reg_be))) | - (addr_hit[ 54] & (|(SCMI_PERMIT[ 54] & ~reg_be))) | - (addr_hit[ 55] & (|(SCMI_PERMIT[ 55] & ~reg_be))) | - (addr_hit[ 56] & (|(SCMI_PERMIT[ 56] & ~reg_be))) | - (addr_hit[ 57] & (|(SCMI_PERMIT[ 57] & ~reg_be))) | - (addr_hit[ 58] & (|(SCMI_PERMIT[ 58] & ~reg_be))) | - (addr_hit[ 59] & (|(SCMI_PERMIT[ 59] & ~reg_be))) | - (addr_hit[ 60] & (|(SCMI_PERMIT[ 60] & ~reg_be))) | - (addr_hit[ 61] & (|(SCMI_PERMIT[ 61] & ~reg_be))) | - (addr_hit[ 62] & (|(SCMI_PERMIT[ 62] & ~reg_be))) | - (addr_hit[ 63] & (|(SCMI_PERMIT[ 63] & ~reg_be))) | - (addr_hit[ 64] & (|(SCMI_PERMIT[ 64] & ~reg_be))) | - (addr_hit[ 65] & (|(SCMI_PERMIT[ 65] & ~reg_be))) | - (addr_hit[ 66] & (|(SCMI_PERMIT[ 66] & ~reg_be))) | - (addr_hit[ 67] & (|(SCMI_PERMIT[ 67] & ~reg_be))) | - (addr_hit[ 68] & (|(SCMI_PERMIT[ 68] & ~reg_be))) | - (addr_hit[ 69] & (|(SCMI_PERMIT[ 69] & ~reg_be))) | - (addr_hit[ 70] & (|(SCMI_PERMIT[ 70] & ~reg_be))) | - (addr_hit[ 71] & (|(SCMI_PERMIT[ 71] & ~reg_be))) | - (addr_hit[ 72] & (|(SCMI_PERMIT[ 72] & ~reg_be))) | - (addr_hit[ 73] & (|(SCMI_PERMIT[ 73] & ~reg_be))) | - (addr_hit[ 74] & (|(SCMI_PERMIT[ 74] & ~reg_be))) | - (addr_hit[ 75] & (|(SCMI_PERMIT[ 75] & ~reg_be))) | - (addr_hit[ 76] & (|(SCMI_PERMIT[ 76] & ~reg_be))) | - (addr_hit[ 77] & (|(SCMI_PERMIT[ 77] & ~reg_be))) | - (addr_hit[ 78] & (|(SCMI_PERMIT[ 78] & ~reg_be))) | - (addr_hit[ 79] & (|(SCMI_PERMIT[ 79] & ~reg_be))) | - (addr_hit[ 80] & (|(SCMI_PERMIT[ 80] & ~reg_be))) | - (addr_hit[ 81] & (|(SCMI_PERMIT[ 81] & ~reg_be))) | - (addr_hit[ 82] & (|(SCMI_PERMIT[ 82] & ~reg_be))) | - (addr_hit[ 83] & (|(SCMI_PERMIT[ 83] & ~reg_be))) | - (addr_hit[ 84] & (|(SCMI_PERMIT[ 84] & ~reg_be))) | - (addr_hit[ 85] & (|(SCMI_PERMIT[ 85] & ~reg_be))) | - (addr_hit[ 86] & (|(SCMI_PERMIT[ 86] & ~reg_be))) | - (addr_hit[ 87] & (|(SCMI_PERMIT[ 87] & ~reg_be))) | - (addr_hit[ 88] & (|(SCMI_PERMIT[ 88] & ~reg_be))) | - (addr_hit[ 89] & (|(SCMI_PERMIT[ 89] & ~reg_be))) | - (addr_hit[ 90] & (|(SCMI_PERMIT[ 90] & ~reg_be))) | - (addr_hit[ 91] & (|(SCMI_PERMIT[ 91] & ~reg_be))) | - (addr_hit[ 92] & (|(SCMI_PERMIT[ 92] & ~reg_be))) | - (addr_hit[ 93] & (|(SCMI_PERMIT[ 93] & ~reg_be))) | - (addr_hit[ 94] & (|(SCMI_PERMIT[ 94] & ~reg_be))) | - (addr_hit[ 95] & (|(SCMI_PERMIT[ 95] & ~reg_be))) | - (addr_hit[ 96] & (|(SCMI_PERMIT[ 96] & ~reg_be))) | - (addr_hit[ 97] & (|(SCMI_PERMIT[ 97] & ~reg_be))) | - (addr_hit[ 98] & (|(SCMI_PERMIT[ 98] & ~reg_be))) | - (addr_hit[ 99] & (|(SCMI_PERMIT[ 99] & ~reg_be))) | - (addr_hit[ 100] & (|(SCMI_PERMIT[ 100] & ~reg_be))) | - (addr_hit[ 101] & (|(SCMI_PERMIT[ 101] & ~reg_be))) | - (addr_hit[ 102] & (|(SCMI_PERMIT[ 102] & ~reg_be))) | - (addr_hit[ 103] & (|(SCMI_PERMIT[ 103] & ~reg_be))) | - (addr_hit[ 104] & (|(SCMI_PERMIT[ 104] & ~reg_be))) | - (addr_hit[ 105] & (|(SCMI_PERMIT[ 105] & ~reg_be))) | - (addr_hit[ 106] & (|(SCMI_PERMIT[ 106] & ~reg_be))) | - (addr_hit[ 107] & (|(SCMI_PERMIT[ 107] & ~reg_be))) | - (addr_hit[ 108] & (|(SCMI_PERMIT[ 108] & ~reg_be))) | - (addr_hit[ 109] & (|(SCMI_PERMIT[ 109] & ~reg_be))) | - (addr_hit[ 110] & (|(SCMI_PERMIT[ 110] & ~reg_be))) | - (addr_hit[ 111] & (|(SCMI_PERMIT[ 111] & ~reg_be))) | - (addr_hit[ 112] & (|(SCMI_PERMIT[ 112] & ~reg_be))) | - (addr_hit[ 113] & (|(SCMI_PERMIT[ 113] & ~reg_be))) | - (addr_hit[ 114] & (|(SCMI_PERMIT[ 114] & ~reg_be))) | - (addr_hit[ 115] & (|(SCMI_PERMIT[ 115] & ~reg_be))) | - (addr_hit[ 116] & (|(SCMI_PERMIT[ 116] & ~reg_be))) | - (addr_hit[ 117] & (|(SCMI_PERMIT[ 117] & ~reg_be))) | - (addr_hit[ 118] & (|(SCMI_PERMIT[ 118] & ~reg_be))) | - (addr_hit[ 119] & (|(SCMI_PERMIT[ 119] & ~reg_be))) | - (addr_hit[ 120] & (|(SCMI_PERMIT[ 120] & ~reg_be))) | - (addr_hit[ 121] & (|(SCMI_PERMIT[ 121] & ~reg_be))) | - (addr_hit[ 122] & (|(SCMI_PERMIT[ 122] & ~reg_be))) | - (addr_hit[ 123] & (|(SCMI_PERMIT[ 123] & ~reg_be))) | - (addr_hit[ 124] & (|(SCMI_PERMIT[ 124] & ~reg_be))) | - (addr_hit[ 125] & (|(SCMI_PERMIT[ 125] & ~reg_be))) | - (addr_hit[ 126] & (|(SCMI_PERMIT[ 126] & ~reg_be))) | - (addr_hit[ 127] & (|(SCMI_PERMIT[ 127] & ~reg_be))) | - (addr_hit[ 128] & (|(SCMI_PERMIT[ 128] & ~reg_be))) | - (addr_hit[ 129] & (|(SCMI_PERMIT[ 129] & ~reg_be))) | - (addr_hit[ 130] & (|(SCMI_PERMIT[ 130] & ~reg_be))) | - (addr_hit[ 131] & (|(SCMI_PERMIT[ 131] & ~reg_be))) | - (addr_hit[ 132] & (|(SCMI_PERMIT[ 132] & ~reg_be))) | - (addr_hit[ 133] & (|(SCMI_PERMIT[ 133] & ~reg_be))) | - (addr_hit[ 134] & (|(SCMI_PERMIT[ 134] & ~reg_be))) | - (addr_hit[ 135] & (|(SCMI_PERMIT[ 135] & ~reg_be))) | - (addr_hit[ 136] & (|(SCMI_PERMIT[ 136] & ~reg_be))) | - (addr_hit[ 137] & (|(SCMI_PERMIT[ 137] & ~reg_be))) | - (addr_hit[ 138] & (|(SCMI_PERMIT[ 138] & ~reg_be))) | - (addr_hit[ 139] & (|(SCMI_PERMIT[ 139] & ~reg_be))) | - (addr_hit[ 140] & (|(SCMI_PERMIT[ 140] & ~reg_be))) | - (addr_hit[ 141] & (|(SCMI_PERMIT[ 141] & ~reg_be))) | - (addr_hit[ 142] & (|(SCMI_PERMIT[ 142] & ~reg_be))) | - (addr_hit[ 143] & (|(SCMI_PERMIT[ 143] & ~reg_be))) | - (addr_hit[ 144] & (|(SCMI_PERMIT[ 144] & ~reg_be))) | - (addr_hit[ 145] & (|(SCMI_PERMIT[ 145] & ~reg_be))) | - (addr_hit[ 146] & (|(SCMI_PERMIT[ 146] & ~reg_be))) | - (addr_hit[ 147] & (|(SCMI_PERMIT[ 147] & ~reg_be))) | - (addr_hit[ 148] & (|(SCMI_PERMIT[ 148] & ~reg_be))) | - (addr_hit[ 149] & (|(SCMI_PERMIT[ 149] & ~reg_be))) | - (addr_hit[ 150] & (|(SCMI_PERMIT[ 150] & ~reg_be))) | - (addr_hit[ 151] & (|(SCMI_PERMIT[ 151] & ~reg_be))) | - (addr_hit[ 152] & (|(SCMI_PERMIT[ 152] & ~reg_be))) | - (addr_hit[ 153] & (|(SCMI_PERMIT[ 153] & ~reg_be))) | - (addr_hit[ 154] & (|(SCMI_PERMIT[ 154] & ~reg_be))) | - (addr_hit[ 155] & (|(SCMI_PERMIT[ 155] & ~reg_be))) | - (addr_hit[ 156] & (|(SCMI_PERMIT[ 156] & ~reg_be))) | - (addr_hit[ 157] & (|(SCMI_PERMIT[ 157] & ~reg_be))) | - (addr_hit[ 158] & (|(SCMI_PERMIT[ 158] & ~reg_be))) | - (addr_hit[ 159] & (|(SCMI_PERMIT[ 159] & ~reg_be))) | - (addr_hit[ 160] & (|(SCMI_PERMIT[ 160] & ~reg_be))) | - (addr_hit[ 161] & (|(SCMI_PERMIT[ 161] & ~reg_be))) | - (addr_hit[ 162] & (|(SCMI_PERMIT[ 162] & ~reg_be))) | - (addr_hit[ 163] & (|(SCMI_PERMIT[ 163] & ~reg_be))) | - (addr_hit[ 164] & (|(SCMI_PERMIT[ 164] & ~reg_be))) | - (addr_hit[ 165] & (|(SCMI_PERMIT[ 165] & ~reg_be))) | - (addr_hit[ 166] & (|(SCMI_PERMIT[ 166] & ~reg_be))) | - (addr_hit[ 167] & (|(SCMI_PERMIT[ 167] & ~reg_be))) | - (addr_hit[ 168] & (|(SCMI_PERMIT[ 168] & ~reg_be))) | - (addr_hit[ 169] & (|(SCMI_PERMIT[ 169] & ~reg_be))) | - (addr_hit[ 170] & (|(SCMI_PERMIT[ 170] & ~reg_be))) | - (addr_hit[ 171] & (|(SCMI_PERMIT[ 171] & ~reg_be))) | - (addr_hit[ 172] & (|(SCMI_PERMIT[ 172] & ~reg_be))) | - (addr_hit[ 173] & (|(SCMI_PERMIT[ 173] & ~reg_be))) | - (addr_hit[ 174] & (|(SCMI_PERMIT[ 174] & ~reg_be))) | - (addr_hit[ 175] & (|(SCMI_PERMIT[ 175] & ~reg_be))) | - (addr_hit[ 176] & (|(SCMI_PERMIT[ 176] & ~reg_be))) | - (addr_hit[ 177] & (|(SCMI_PERMIT[ 177] & ~reg_be))) | - (addr_hit[ 178] & (|(SCMI_PERMIT[ 178] & ~reg_be))) | - (addr_hit[ 179] & (|(SCMI_PERMIT[ 179] & ~reg_be))) | - (addr_hit[ 180] & (|(SCMI_PERMIT[ 180] & ~reg_be))) | - (addr_hit[ 181] & (|(SCMI_PERMIT[ 181] & ~reg_be))) | - (addr_hit[ 182] & (|(SCMI_PERMIT[ 182] & ~reg_be))) | - (addr_hit[ 183] & (|(SCMI_PERMIT[ 183] & ~reg_be))) | - (addr_hit[ 184] & (|(SCMI_PERMIT[ 184] & ~reg_be))) | - (addr_hit[ 185] & (|(SCMI_PERMIT[ 185] & ~reg_be))) | - (addr_hit[ 186] & (|(SCMI_PERMIT[ 186] & ~reg_be))) | - (addr_hit[ 187] & (|(SCMI_PERMIT[ 187] & ~reg_be))) | - (addr_hit[ 188] & (|(SCMI_PERMIT[ 188] & ~reg_be))) | - (addr_hit[ 189] & (|(SCMI_PERMIT[ 189] & ~reg_be))) | - (addr_hit[ 190] & (|(SCMI_PERMIT[ 190] & ~reg_be))) | - (addr_hit[ 191] & (|(SCMI_PERMIT[ 191] & ~reg_be))) | - (addr_hit[ 192] & (|(SCMI_PERMIT[ 192] & ~reg_be))) | - (addr_hit[ 193] & (|(SCMI_PERMIT[ 193] & ~reg_be))) | - (addr_hit[ 194] & (|(SCMI_PERMIT[ 194] & ~reg_be))) | - (addr_hit[ 195] & (|(SCMI_PERMIT[ 195] & ~reg_be))) | - (addr_hit[ 196] & (|(SCMI_PERMIT[ 196] & ~reg_be))) | - (addr_hit[ 197] & (|(SCMI_PERMIT[ 197] & ~reg_be))) | - (addr_hit[ 198] & (|(SCMI_PERMIT[ 198] & ~reg_be))) | - (addr_hit[ 199] & (|(SCMI_PERMIT[ 199] & ~reg_be))) | - (addr_hit[ 200] & (|(SCMI_PERMIT[ 200] & ~reg_be))) | - (addr_hit[ 201] & (|(SCMI_PERMIT[ 201] & ~reg_be))) | - (addr_hit[ 202] & (|(SCMI_PERMIT[ 202] & ~reg_be))) | - (addr_hit[ 203] & (|(SCMI_PERMIT[ 203] & ~reg_be))) | - (addr_hit[ 204] & (|(SCMI_PERMIT[ 204] & ~reg_be))) | - (addr_hit[ 205] & (|(SCMI_PERMIT[ 205] & ~reg_be))) | - (addr_hit[ 206] & (|(SCMI_PERMIT[ 206] & ~reg_be))) | - (addr_hit[ 207] & (|(SCMI_PERMIT[ 207] & ~reg_be))) | - (addr_hit[ 208] & (|(SCMI_PERMIT[ 208] & ~reg_be))) | - (addr_hit[ 209] & (|(SCMI_PERMIT[ 209] & ~reg_be))) | - (addr_hit[ 210] & (|(SCMI_PERMIT[ 210] & ~reg_be))) | - (addr_hit[ 211] & (|(SCMI_PERMIT[ 211] & ~reg_be))) | - (addr_hit[ 212] & (|(SCMI_PERMIT[ 212] & ~reg_be))) | - (addr_hit[ 213] & (|(SCMI_PERMIT[ 213] & ~reg_be))) | - (addr_hit[ 214] & (|(SCMI_PERMIT[ 214] & ~reg_be))) | - (addr_hit[ 215] & (|(SCMI_PERMIT[ 215] & ~reg_be))) | - (addr_hit[ 216] & (|(SCMI_PERMIT[ 216] & ~reg_be))) | - (addr_hit[ 217] & (|(SCMI_PERMIT[ 217] & ~reg_be))) | - (addr_hit[ 218] & (|(SCMI_PERMIT[ 218] & ~reg_be))) | - (addr_hit[ 219] & (|(SCMI_PERMIT[ 219] & ~reg_be))) | - (addr_hit[ 220] & (|(SCMI_PERMIT[ 220] & ~reg_be))) | - (addr_hit[ 221] & (|(SCMI_PERMIT[ 221] & ~reg_be))) | - (addr_hit[ 222] & (|(SCMI_PERMIT[ 222] & ~reg_be))) | - (addr_hit[ 223] & (|(SCMI_PERMIT[ 223] & ~reg_be))) | - (addr_hit[ 224] & (|(SCMI_PERMIT[ 224] & ~reg_be))) | - (addr_hit[ 225] & (|(SCMI_PERMIT[ 225] & ~reg_be))) | - (addr_hit[ 226] & (|(SCMI_PERMIT[ 226] & ~reg_be))) | - (addr_hit[ 227] & (|(SCMI_PERMIT[ 227] & ~reg_be))) | - (addr_hit[ 228] & (|(SCMI_PERMIT[ 228] & ~reg_be))) | - (addr_hit[ 229] & (|(SCMI_PERMIT[ 229] & ~reg_be))) | - (addr_hit[ 230] & (|(SCMI_PERMIT[ 230] & ~reg_be))) | - (addr_hit[ 231] & (|(SCMI_PERMIT[ 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676] & ~reg_be))) | - (addr_hit[ 677] & (|(SCMI_PERMIT[ 677] & ~reg_be))) | - (addr_hit[ 678] & (|(SCMI_PERMIT[ 678] & ~reg_be))) | - (addr_hit[ 679] & (|(SCMI_PERMIT[ 679] & ~reg_be))) | - (addr_hit[ 680] & (|(SCMI_PERMIT[ 680] & ~reg_be))) | - (addr_hit[ 681] & (|(SCMI_PERMIT[ 681] & ~reg_be))) | - (addr_hit[ 682] & (|(SCMI_PERMIT[ 682] & ~reg_be))) | - (addr_hit[ 683] & (|(SCMI_PERMIT[ 683] & ~reg_be))) | - (addr_hit[ 684] & (|(SCMI_PERMIT[ 684] & ~reg_be))) | - (addr_hit[ 685] & (|(SCMI_PERMIT[ 685] & ~reg_be))) | - (addr_hit[ 686] & (|(SCMI_PERMIT[ 686] & ~reg_be))) | - (addr_hit[ 687] & (|(SCMI_PERMIT[ 687] & ~reg_be))) | - (addr_hit[ 688] & (|(SCMI_PERMIT[ 688] & ~reg_be))) | - (addr_hit[ 689] & (|(SCMI_PERMIT[ 689] & ~reg_be))) | - (addr_hit[ 690] & (|(SCMI_PERMIT[ 690] & ~reg_be))) | - (addr_hit[ 691] & (|(SCMI_PERMIT[ 691] & ~reg_be))) | - (addr_hit[ 692] & (|(SCMI_PERMIT[ 692] & ~reg_be))) | - (addr_hit[ 693] & (|(SCMI_PERMIT[ 693] & ~reg_be))) | - (addr_hit[ 694] & (|(SCMI_PERMIT[ 694] & ~reg_be))) | - (addr_hit[ 695] & (|(SCMI_PERMIT[ 695] & ~reg_be))) | - (addr_hit[ 696] & (|(SCMI_PERMIT[ 696] & ~reg_be))) | - (addr_hit[ 697] & (|(SCMI_PERMIT[ 697] & ~reg_be))) | - (addr_hit[ 698] & (|(SCMI_PERMIT[ 698] & ~reg_be))) | - (addr_hit[ 699] & (|(SCMI_PERMIT[ 699] & ~reg_be))) | - (addr_hit[ 700] & (|(SCMI_PERMIT[ 700] & ~reg_be))) | - (addr_hit[ 701] & (|(SCMI_PERMIT[ 701] & ~reg_be))) | - (addr_hit[ 702] & (|(SCMI_PERMIT[ 702] & ~reg_be))) | - (addr_hit[ 703] & (|(SCMI_PERMIT[ 703] & ~reg_be))) | - (addr_hit[ 704] & (|(SCMI_PERMIT[ 704] & ~reg_be))) | - (addr_hit[ 705] & (|(SCMI_PERMIT[ 705] & ~reg_be))) | - (addr_hit[ 706] & (|(SCMI_PERMIT[ 706] & ~reg_be))) | - (addr_hit[ 707] & (|(SCMI_PERMIT[ 707] & ~reg_be))) | - (addr_hit[ 708] & (|(SCMI_PERMIT[ 708] & ~reg_be))) | - (addr_hit[ 709] & (|(SCMI_PERMIT[ 709] & ~reg_be))) | - (addr_hit[ 710] & (|(SCMI_PERMIT[ 710] & ~reg_be))) | - (addr_hit[ 711] & (|(SCMI_PERMIT[ 711] & ~reg_be))) | - (addr_hit[ 712] & (|(SCMI_PERMIT[ 712] & ~reg_be))) | - (addr_hit[ 713] & (|(SCMI_PERMIT[ 713] & ~reg_be))) | - (addr_hit[ 714] & (|(SCMI_PERMIT[ 714] & ~reg_be))) | - (addr_hit[ 715] & (|(SCMI_PERMIT[ 715] & ~reg_be))) | - (addr_hit[ 716] & (|(SCMI_PERMIT[ 716] & ~reg_be))) | - (addr_hit[ 717] & (|(SCMI_PERMIT[ 717] & ~reg_be))) | - (addr_hit[ 718] & (|(SCMI_PERMIT[ 718] & ~reg_be))) | - (addr_hit[ 719] & (|(SCMI_PERMIT[ 719] & ~reg_be))) | - (addr_hit[ 720] & (|(SCMI_PERMIT[ 720] & ~reg_be))) | - (addr_hit[ 721] & (|(SCMI_PERMIT[ 721] & ~reg_be))) | - (addr_hit[ 722] & (|(SCMI_PERMIT[ 722] & ~reg_be))) | - (addr_hit[ 723] & (|(SCMI_PERMIT[ 723] & ~reg_be))) | - (addr_hit[ 724] & (|(SCMI_PERMIT[ 724] & ~reg_be))) | - (addr_hit[ 725] & (|(SCMI_PERMIT[ 725] & ~reg_be))) | - (addr_hit[ 726] & (|(SCMI_PERMIT[ 726] & ~reg_be))) | - (addr_hit[ 727] & (|(SCMI_PERMIT[ 727] & ~reg_be))) | - (addr_hit[ 728] & (|(SCMI_PERMIT[ 728] & ~reg_be))) | - (addr_hit[ 729] & (|(SCMI_PERMIT[ 729] & ~reg_be))) | - (addr_hit[ 730] & (|(SCMI_PERMIT[ 730] & ~reg_be))) | - (addr_hit[ 731] & (|(SCMI_PERMIT[ 731] & ~reg_be))) | - (addr_hit[ 732] & (|(SCMI_PERMIT[ 732] & ~reg_be))) | - (addr_hit[ 733] & (|(SCMI_PERMIT[ 733] & ~reg_be))) | - (addr_hit[ 734] & (|(SCMI_PERMIT[ 734] & ~reg_be))) | - (addr_hit[ 735] & (|(SCMI_PERMIT[ 735] & ~reg_be))) | - (addr_hit[ 736] & (|(SCMI_PERMIT[ 736] & ~reg_be))) | - (addr_hit[ 737] & (|(SCMI_PERMIT[ 737] & ~reg_be))) | - (addr_hit[ 738] & (|(SCMI_PERMIT[ 738] & ~reg_be))) | - (addr_hit[ 739] & (|(SCMI_PERMIT[ 739] & ~reg_be))) | - (addr_hit[ 740] & (|(SCMI_PERMIT[ 740] & ~reg_be))) | - (addr_hit[ 741] & (|(SCMI_PERMIT[ 741] & ~reg_be))) | - (addr_hit[ 742] & (|(SCMI_PERMIT[ 742] & ~reg_be))) | - (addr_hit[ 743] & (|(SCMI_PERMIT[ 743] & ~reg_be))) | - (addr_hit[ 744] & (|(SCMI_PERMIT[ 744] & ~reg_be))) | - (addr_hit[ 745] & (|(SCMI_PERMIT[ 745] & ~reg_be))) | - (addr_hit[ 746] & (|(SCMI_PERMIT[ 746] & ~reg_be))) | - (addr_hit[ 747] & (|(SCMI_PERMIT[ 747] & ~reg_be))) | - (addr_hit[ 748] & (|(SCMI_PERMIT[ 748] & ~reg_be))) | - (addr_hit[ 749] & (|(SCMI_PERMIT[ 749] & ~reg_be))) | - (addr_hit[ 750] & (|(SCMI_PERMIT[ 750] & ~reg_be))) | - (addr_hit[ 751] & (|(SCMI_PERMIT[ 751] & ~reg_be))) | - (addr_hit[ 752] & (|(SCMI_PERMIT[ 752] & ~reg_be))) | - (addr_hit[ 753] & (|(SCMI_PERMIT[ 753] & ~reg_be))) | - (addr_hit[ 754] & (|(SCMI_PERMIT[ 754] & ~reg_be))) | - (addr_hit[ 755] & (|(SCMI_PERMIT[ 755] & ~reg_be))) | - (addr_hit[ 756] & (|(SCMI_PERMIT[ 756] & ~reg_be))) | - (addr_hit[ 757] & (|(SCMI_PERMIT[ 757] & ~reg_be))) | - (addr_hit[ 758] & (|(SCMI_PERMIT[ 758] & ~reg_be))) | - (addr_hit[ 759] & (|(SCMI_PERMIT[ 759] & ~reg_be))) | - (addr_hit[ 760] & (|(SCMI_PERMIT[ 760] & ~reg_be))) | - (addr_hit[ 761] & (|(SCMI_PERMIT[ 761] & ~reg_be))) | - (addr_hit[ 762] & (|(SCMI_PERMIT[ 762] & ~reg_be))) | - (addr_hit[ 763] & (|(SCMI_PERMIT[ 763] & ~reg_be))) | - (addr_hit[ 764] & (|(SCMI_PERMIT[ 764] & ~reg_be))) | - (addr_hit[ 765] & (|(SCMI_PERMIT[ 765] & ~reg_be))) | - (addr_hit[ 766] & (|(SCMI_PERMIT[ 766] & ~reg_be))) | - (addr_hit[ 767] & (|(SCMI_PERMIT[ 767] & ~reg_be))) | - (addr_hit[ 768] & (|(SCMI_PERMIT[ 768] & ~reg_be))) | - (addr_hit[ 769] & (|(SCMI_PERMIT[ 769] & ~reg_be))) | - (addr_hit[ 770] & (|(SCMI_PERMIT[ 770] & ~reg_be))) | - (addr_hit[ 771] & (|(SCMI_PERMIT[ 771] & ~reg_be))) | - (addr_hit[ 772] & (|(SCMI_PERMIT[ 772] & ~reg_be))) | - (addr_hit[ 773] & (|(SCMI_PERMIT[ 773] & ~reg_be))) | - (addr_hit[ 774] & (|(SCMI_PERMIT[ 774] & ~reg_be))) | - (addr_hit[ 775] & (|(SCMI_PERMIT[ 775] & ~reg_be))) | - (addr_hit[ 776] & (|(SCMI_PERMIT[ 776] & ~reg_be))) | - (addr_hit[ 777] & (|(SCMI_PERMIT[ 777] & ~reg_be))) | - (addr_hit[ 778] & (|(SCMI_PERMIT[ 778] & ~reg_be))) | - (addr_hit[ 779] & (|(SCMI_PERMIT[ 779] & ~reg_be))) | - (addr_hit[ 780] & (|(SCMI_PERMIT[ 780] & ~reg_be))) | - (addr_hit[ 781] & (|(SCMI_PERMIT[ 781] & ~reg_be))) | - (addr_hit[ 782] & (|(SCMI_PERMIT[ 782] & ~reg_be))) | - (addr_hit[ 783] & (|(SCMI_PERMIT[ 783] & ~reg_be))) | - (addr_hit[ 784] & (|(SCMI_PERMIT[ 784] & ~reg_be))) | - (addr_hit[ 785] & (|(SCMI_PERMIT[ 785] & ~reg_be))) | - (addr_hit[ 786] & (|(SCMI_PERMIT[ 786] & ~reg_be))) | - (addr_hit[ 787] & (|(SCMI_PERMIT[ 787] & ~reg_be))) | - (addr_hit[ 788] & (|(SCMI_PERMIT[ 788] & ~reg_be))) | - (addr_hit[ 789] & (|(SCMI_PERMIT[ 789] & ~reg_be))) | - (addr_hit[ 790] & (|(SCMI_PERMIT[ 790] & ~reg_be))) | - (addr_hit[ 791] & (|(SCMI_PERMIT[ 791] & ~reg_be))) | - (addr_hit[ 792] & (|(SCMI_PERMIT[ 792] & ~reg_be))) | - (addr_hit[ 793] & (|(SCMI_PERMIT[ 793] & ~reg_be))) | - (addr_hit[ 794] & (|(SCMI_PERMIT[ 794] & ~reg_be))) | - (addr_hit[ 795] & (|(SCMI_PERMIT[ 795] & ~reg_be))) | - (addr_hit[ 796] & (|(SCMI_PERMIT[ 796] & ~reg_be))) | - (addr_hit[ 797] & (|(SCMI_PERMIT[ 797] & ~reg_be))) | - (addr_hit[ 798] & (|(SCMI_PERMIT[ 798] & ~reg_be))) | - (addr_hit[ 799] & (|(SCMI_PERMIT[ 799] & ~reg_be))) | - (addr_hit[ 800] & (|(SCMI_PERMIT[ 800] & ~reg_be))) | - (addr_hit[ 801] & (|(SCMI_PERMIT[ 801] & ~reg_be))) | - (addr_hit[ 802] & (|(SCMI_PERMIT[ 802] & ~reg_be))) | - (addr_hit[ 803] & (|(SCMI_PERMIT[ 803] & ~reg_be))) | - (addr_hit[ 804] & (|(SCMI_PERMIT[ 804] & ~reg_be))) | - (addr_hit[ 805] & (|(SCMI_PERMIT[ 805] & ~reg_be))) | - (addr_hit[ 806] & (|(SCMI_PERMIT[ 806] & ~reg_be))) | - (addr_hit[ 807] & (|(SCMI_PERMIT[ 807] & ~reg_be))) | - (addr_hit[ 808] & (|(SCMI_PERMIT[ 808] & ~reg_be))) | - (addr_hit[ 809] & (|(SCMI_PERMIT[ 809] & ~reg_be))) | - (addr_hit[ 810] & (|(SCMI_PERMIT[ 810] & ~reg_be))) | - (addr_hit[ 811] & (|(SCMI_PERMIT[ 811] & ~reg_be))) | - (addr_hit[ 812] & (|(SCMI_PERMIT[ 812] & ~reg_be))) | - (addr_hit[ 813] & (|(SCMI_PERMIT[ 813] & ~reg_be))) | - (addr_hit[ 814] & (|(SCMI_PERMIT[ 814] & ~reg_be))) | - (addr_hit[ 815] & (|(SCMI_PERMIT[ 815] & ~reg_be))) | - (addr_hit[ 816] & (|(SCMI_PERMIT[ 816] & ~reg_be))) | - (addr_hit[ 817] & (|(SCMI_PERMIT[ 817] & ~reg_be))) | - (addr_hit[ 818] & (|(SCMI_PERMIT[ 818] & ~reg_be))) | - (addr_hit[ 819] & (|(SCMI_PERMIT[ 819] & ~reg_be))) | - (addr_hit[ 820] & (|(SCMI_PERMIT[ 820] & ~reg_be))) | - (addr_hit[ 821] & (|(SCMI_PERMIT[ 821] & ~reg_be))) | - (addr_hit[ 822] & (|(SCMI_PERMIT[ 822] & ~reg_be))) | - (addr_hit[ 823] & (|(SCMI_PERMIT[ 823] & ~reg_be))) | - (addr_hit[ 824] & (|(SCMI_PERMIT[ 824] & ~reg_be))) | - (addr_hit[ 825] & (|(SCMI_PERMIT[ 825] & ~reg_be))) | - (addr_hit[ 826] & (|(SCMI_PERMIT[ 826] & ~reg_be))) | - (addr_hit[ 827] & (|(SCMI_PERMIT[ 827] & ~reg_be))) | - (addr_hit[ 828] & (|(SCMI_PERMIT[ 828] & ~reg_be))) | - (addr_hit[ 829] & (|(SCMI_PERMIT[ 829] & ~reg_be))) | - (addr_hit[ 830] & (|(SCMI_PERMIT[ 830] & ~reg_be))) | - (addr_hit[ 831] & (|(SCMI_PERMIT[ 831] & ~reg_be))) | - (addr_hit[ 832] & (|(SCMI_PERMIT[ 832] & ~reg_be))) | - (addr_hit[ 833] & (|(SCMI_PERMIT[ 833] & ~reg_be))) | - (addr_hit[ 834] & (|(SCMI_PERMIT[ 834] & ~reg_be))) | - (addr_hit[ 835] & (|(SCMI_PERMIT[ 835] & ~reg_be))) | - (addr_hit[ 836] & (|(SCMI_PERMIT[ 836] & ~reg_be))) | - (addr_hit[ 837] & (|(SCMI_PERMIT[ 837] & ~reg_be))) | - (addr_hit[ 838] & (|(SCMI_PERMIT[ 838] & ~reg_be))) | - (addr_hit[ 839] & (|(SCMI_PERMIT[ 839] & ~reg_be))) | - (addr_hit[ 840] & (|(SCMI_PERMIT[ 840] & ~reg_be))) | - (addr_hit[ 841] & (|(SCMI_PERMIT[ 841] & ~reg_be))) | - (addr_hit[ 842] & (|(SCMI_PERMIT[ 842] & ~reg_be))) | - (addr_hit[ 843] & (|(SCMI_PERMIT[ 843] & ~reg_be))) | - (addr_hit[ 844] & (|(SCMI_PERMIT[ 844] & ~reg_be))) | - (addr_hit[ 845] & (|(SCMI_PERMIT[ 845] & ~reg_be))) | - (addr_hit[ 846] & (|(SCMI_PERMIT[ 846] & ~reg_be))) | - (addr_hit[ 847] & (|(SCMI_PERMIT[ 847] & ~reg_be))) | - (addr_hit[ 848] & (|(SCMI_PERMIT[ 848] & ~reg_be))) | - (addr_hit[ 849] & (|(SCMI_PERMIT[ 849] & ~reg_be))) | - (addr_hit[ 850] & (|(SCMI_PERMIT[ 850] & ~reg_be))) | - (addr_hit[ 851] & (|(SCMI_PERMIT[ 851] & ~reg_be))) | - (addr_hit[ 852] & (|(SCMI_PERMIT[ 852] & ~reg_be))) | - (addr_hit[ 853] & (|(SCMI_PERMIT[ 853] & ~reg_be))) | - (addr_hit[ 854] & (|(SCMI_PERMIT[ 854] & ~reg_be))) | - (addr_hit[ 855] & (|(SCMI_PERMIT[ 855] & ~reg_be))) | - (addr_hit[ 856] & (|(SCMI_PERMIT[ 856] & ~reg_be))) | - (addr_hit[ 857] & (|(SCMI_PERMIT[ 857] & ~reg_be))) | - (addr_hit[ 858] & (|(SCMI_PERMIT[ 858] & ~reg_be))) | - (addr_hit[ 859] & (|(SCMI_PERMIT[ 859] & ~reg_be))) | - (addr_hit[ 860] & (|(SCMI_PERMIT[ 860] & ~reg_be))) | - (addr_hit[ 861] & (|(SCMI_PERMIT[ 861] & ~reg_be))) | - (addr_hit[ 862] & (|(SCMI_PERMIT[ 862] & ~reg_be))) | - (addr_hit[ 863] & (|(SCMI_PERMIT[ 863] & ~reg_be))) | - (addr_hit[ 864] & (|(SCMI_PERMIT[ 864] & ~reg_be))) | - (addr_hit[ 865] & (|(SCMI_PERMIT[ 865] & ~reg_be))) | - (addr_hit[ 866] & (|(SCMI_PERMIT[ 866] & ~reg_be))) | - (addr_hit[ 867] & (|(SCMI_PERMIT[ 867] & ~reg_be))) | - (addr_hit[ 868] & (|(SCMI_PERMIT[ 868] & ~reg_be))) | - (addr_hit[ 869] & (|(SCMI_PERMIT[ 869] & ~reg_be))) | - (addr_hit[ 870] & (|(SCMI_PERMIT[ 870] & ~reg_be))) | - (addr_hit[ 871] & (|(SCMI_PERMIT[ 871] & ~reg_be))) | - (addr_hit[ 872] & (|(SCMI_PERMIT[ 872] & ~reg_be))) | - (addr_hit[ 873] & (|(SCMI_PERMIT[ 873] & ~reg_be))) | - (addr_hit[ 874] & (|(SCMI_PERMIT[ 874] & ~reg_be))) | - (addr_hit[ 875] & (|(SCMI_PERMIT[ 875] & ~reg_be))) | - (addr_hit[ 876] & (|(SCMI_PERMIT[ 876] & ~reg_be))) | - (addr_hit[ 877] & (|(SCMI_PERMIT[ 877] & ~reg_be))) | - (addr_hit[ 878] & (|(SCMI_PERMIT[ 878] & ~reg_be))) | - (addr_hit[ 879] & (|(SCMI_PERMIT[ 879] & ~reg_be))) | - (addr_hit[ 880] & (|(SCMI_PERMIT[ 880] & ~reg_be))) | - (addr_hit[ 881] & (|(SCMI_PERMIT[ 881] & ~reg_be))) | - (addr_hit[ 882] & (|(SCMI_PERMIT[ 882] & ~reg_be))) | - (addr_hit[ 883] & (|(SCMI_PERMIT[ 883] & ~reg_be))) | - (addr_hit[ 884] & (|(SCMI_PERMIT[ 884] & ~reg_be))) | - (addr_hit[ 885] & (|(SCMI_PERMIT[ 885] & ~reg_be))) | - (addr_hit[ 886] & (|(SCMI_PERMIT[ 886] & ~reg_be))) | - (addr_hit[ 887] & (|(SCMI_PERMIT[ 887] & ~reg_be))) | - (addr_hit[ 888] & (|(SCMI_PERMIT[ 888] & ~reg_be))) | - (addr_hit[ 889] & (|(SCMI_PERMIT[ 889] & ~reg_be))) | - (addr_hit[ 890] & (|(SCMI_PERMIT[ 890] & ~reg_be))) | - (addr_hit[ 891] & (|(SCMI_PERMIT[ 891] & ~reg_be))) | - (addr_hit[ 892] & (|(SCMI_PERMIT[ 892] & ~reg_be))) | - (addr_hit[ 893] & (|(SCMI_PERMIT[ 893] & ~reg_be))) | - (addr_hit[ 894] & (|(SCMI_PERMIT[ 894] & ~reg_be))) | - (addr_hit[ 895] & (|(SCMI_PERMIT[ 895] & ~reg_be))) | - (addr_hit[ 896] & (|(SCMI_PERMIT[ 896] & ~reg_be))) | - (addr_hit[ 897] & (|(SCMI_PERMIT[ 897] & ~reg_be))) | - (addr_hit[ 898] & (|(SCMI_PERMIT[ 898] & ~reg_be))) | - (addr_hit[ 899] & (|(SCMI_PERMIT[ 899] & ~reg_be))) | - (addr_hit[ 900] & (|(SCMI_PERMIT[ 900] & ~reg_be))) | - (addr_hit[ 901] & (|(SCMI_PERMIT[ 901] & ~reg_be))) | - (addr_hit[ 902] & (|(SCMI_PERMIT[ 902] & ~reg_be))) | - (addr_hit[ 903] & (|(SCMI_PERMIT[ 903] & ~reg_be))) | - (addr_hit[ 904] & (|(SCMI_PERMIT[ 904] & ~reg_be))) | - (addr_hit[ 905] & (|(SCMI_PERMIT[ 905] & ~reg_be))) | - (addr_hit[ 906] & (|(SCMI_PERMIT[ 906] & ~reg_be))) | - (addr_hit[ 907] & (|(SCMI_PERMIT[ 907] & ~reg_be))) | - (addr_hit[ 908] & (|(SCMI_PERMIT[ 908] & ~reg_be))) | - (addr_hit[ 909] & (|(SCMI_PERMIT[ 909] & ~reg_be))) | - (addr_hit[ 910] & (|(SCMI_PERMIT[ 910] & ~reg_be))) | - (addr_hit[ 911] & (|(SCMI_PERMIT[ 911] & ~reg_be))) | - (addr_hit[ 912] & (|(SCMI_PERMIT[ 912] & ~reg_be))) | - (addr_hit[ 913] & (|(SCMI_PERMIT[ 913] & ~reg_be))) | - (addr_hit[ 914] & (|(SCMI_PERMIT[ 914] & ~reg_be))) | - (addr_hit[ 915] & (|(SCMI_PERMIT[ 915] & ~reg_be))) | - (addr_hit[ 916] & (|(SCMI_PERMIT[ 916] & ~reg_be))) | - (addr_hit[ 917] & (|(SCMI_PERMIT[ 917] & ~reg_be))) | - (addr_hit[ 918] & (|(SCMI_PERMIT[ 918] & ~reg_be))) | - (addr_hit[ 919] & (|(SCMI_PERMIT[ 919] & ~reg_be))) | - (addr_hit[ 920] & (|(SCMI_PERMIT[ 920] & ~reg_be))) | - (addr_hit[ 921] & (|(SCMI_PERMIT[ 921] & ~reg_be))) | - (addr_hit[ 922] & (|(SCMI_PERMIT[ 922] & ~reg_be))) | - (addr_hit[ 923] & (|(SCMI_PERMIT[ 923] & ~reg_be))) | - (addr_hit[ 924] & (|(SCMI_PERMIT[ 924] & ~reg_be))) | - (addr_hit[ 925] & (|(SCMI_PERMIT[ 925] & ~reg_be))) | - (addr_hit[ 926] & (|(SCMI_PERMIT[ 926] & ~reg_be))) | - (addr_hit[ 927] & (|(SCMI_PERMIT[ 927] & ~reg_be))) | - (addr_hit[ 928] & (|(SCMI_PERMIT[ 928] & ~reg_be))) | - (addr_hit[ 929] & (|(SCMI_PERMIT[ 929] & ~reg_be))) | - (addr_hit[ 930] & (|(SCMI_PERMIT[ 930] & ~reg_be))) | - (addr_hit[ 931] & (|(SCMI_PERMIT[ 931] & ~reg_be))) | - (addr_hit[ 932] & (|(SCMI_PERMIT[ 932] & ~reg_be))) | - (addr_hit[ 933] & (|(SCMI_PERMIT[ 933] & ~reg_be))) | - (addr_hit[ 934] & (|(SCMI_PERMIT[ 934] & ~reg_be))) | - (addr_hit[ 935] & (|(SCMI_PERMIT[ 935] & ~reg_be))) | - (addr_hit[ 936] & (|(SCMI_PERMIT[ 936] & ~reg_be))) | - (addr_hit[ 937] & (|(SCMI_PERMIT[ 937] & ~reg_be))) | - (addr_hit[ 938] & (|(SCMI_PERMIT[ 938] & ~reg_be))) | - (addr_hit[ 939] & (|(SCMI_PERMIT[ 939] & ~reg_be))) | - (addr_hit[ 940] & (|(SCMI_PERMIT[ 940] & ~reg_be))) | - (addr_hit[ 941] & (|(SCMI_PERMIT[ 941] & ~reg_be))) | - (addr_hit[ 942] & (|(SCMI_PERMIT[ 942] & ~reg_be))) | - (addr_hit[ 943] & (|(SCMI_PERMIT[ 943] & ~reg_be))) | - (addr_hit[ 944] & (|(SCMI_PERMIT[ 944] & ~reg_be))) | - (addr_hit[ 945] & (|(SCMI_PERMIT[ 945] & ~reg_be))) | - (addr_hit[ 946] & (|(SCMI_PERMIT[ 946] & ~reg_be))) | - (addr_hit[ 947] & (|(SCMI_PERMIT[ 947] & ~reg_be))) | - (addr_hit[ 948] & (|(SCMI_PERMIT[ 948] & ~reg_be))) | - (addr_hit[ 949] & (|(SCMI_PERMIT[ 949] & ~reg_be))) | - (addr_hit[ 950] & (|(SCMI_PERMIT[ 950] & ~reg_be))) | - (addr_hit[ 951] & (|(SCMI_PERMIT[ 951] & ~reg_be))) | - (addr_hit[ 952] & (|(SCMI_PERMIT[ 952] & ~reg_be))) | - (addr_hit[ 953] & (|(SCMI_PERMIT[ 953] & ~reg_be))) | - (addr_hit[ 954] & (|(SCMI_PERMIT[ 954] & ~reg_be))) | - (addr_hit[ 955] & (|(SCMI_PERMIT[ 955] & ~reg_be))) | - (addr_hit[ 956] & (|(SCMI_PERMIT[ 956] & ~reg_be))) | - (addr_hit[ 957] & (|(SCMI_PERMIT[ 957] & ~reg_be))) | - (addr_hit[ 958] & (|(SCMI_PERMIT[ 958] & ~reg_be))) | - (addr_hit[ 959] & (|(SCMI_PERMIT[ 959] & ~reg_be))) | - (addr_hit[ 960] & (|(SCMI_PERMIT[ 960] & ~reg_be))) | - (addr_hit[ 961] & (|(SCMI_PERMIT[ 961] & ~reg_be))) | - (addr_hit[ 962] & (|(SCMI_PERMIT[ 962] & ~reg_be))) | - (addr_hit[ 963] & (|(SCMI_PERMIT[ 963] & ~reg_be))) | - (addr_hit[ 964] & (|(SCMI_PERMIT[ 964] & ~reg_be))) | - (addr_hit[ 965] & (|(SCMI_PERMIT[ 965] & ~reg_be))) | - (addr_hit[ 966] & (|(SCMI_PERMIT[ 966] & ~reg_be))) | - (addr_hit[ 967] & (|(SCMI_PERMIT[ 967] & ~reg_be))) | - (addr_hit[ 968] & (|(SCMI_PERMIT[ 968] & ~reg_be))) | - (addr_hit[ 969] & (|(SCMI_PERMIT[ 969] & ~reg_be))) | - (addr_hit[ 970] & (|(SCMI_PERMIT[ 970] & ~reg_be))) | - (addr_hit[ 971] & (|(SCMI_PERMIT[ 971] & ~reg_be))) | - (addr_hit[ 972] & (|(SCMI_PERMIT[ 972] & ~reg_be))) | - (addr_hit[ 973] & (|(SCMI_PERMIT[ 973] & ~reg_be))) | - (addr_hit[ 974] & (|(SCMI_PERMIT[ 974] & ~reg_be))) | - (addr_hit[ 975] & (|(SCMI_PERMIT[ 975] & ~reg_be))) | - (addr_hit[ 976] & (|(SCMI_PERMIT[ 976] & ~reg_be))) | - (addr_hit[ 977] & (|(SCMI_PERMIT[ 977] & ~reg_be))) | - (addr_hit[ 978] & (|(SCMI_PERMIT[ 978] & ~reg_be))) | - (addr_hit[ 979] & (|(SCMI_PERMIT[ 979] & ~reg_be))) | - (addr_hit[ 980] & (|(SCMI_PERMIT[ 980] & ~reg_be))) | - (addr_hit[ 981] & (|(SCMI_PERMIT[ 981] & ~reg_be))) | - (addr_hit[ 982] & (|(SCMI_PERMIT[ 982] & ~reg_be))) | - (addr_hit[ 983] & (|(SCMI_PERMIT[ 983] & ~reg_be))) | - (addr_hit[ 984] & (|(SCMI_PERMIT[ 984] & ~reg_be))) | - (addr_hit[ 985] & (|(SCMI_PERMIT[ 985] & ~reg_be))) | - (addr_hit[ 986] & (|(SCMI_PERMIT[ 986] & ~reg_be))) | - (addr_hit[ 987] & (|(SCMI_PERMIT[ 987] & ~reg_be))) | - (addr_hit[ 988] & (|(SCMI_PERMIT[ 988] & ~reg_be))) | - (addr_hit[ 989] & (|(SCMI_PERMIT[ 989] & ~reg_be))) | - (addr_hit[ 990] & (|(SCMI_PERMIT[ 990] & ~reg_be))) | - (addr_hit[ 991] & (|(SCMI_PERMIT[ 991] & ~reg_be))) | - (addr_hit[ 992] & (|(SCMI_PERMIT[ 992] & ~reg_be))) | - (addr_hit[ 993] & (|(SCMI_PERMIT[ 993] & ~reg_be))) | - (addr_hit[ 994] & (|(SCMI_PERMIT[ 994] & ~reg_be))) | - (addr_hit[ 995] & (|(SCMI_PERMIT[ 995] & ~reg_be))) | - (addr_hit[ 996] & (|(SCMI_PERMIT[ 996] & ~reg_be))) | - (addr_hit[ 997] & (|(SCMI_PERMIT[ 997] & ~reg_be))) | - (addr_hit[ 998] & (|(SCMI_PERMIT[ 998] & ~reg_be))) | - (addr_hit[ 999] & (|(SCMI_PERMIT[ 999] & ~reg_be))) | - (addr_hit[1000] & (|(SCMI_PERMIT[1000] & ~reg_be))) | - (addr_hit[1001] & (|(SCMI_PERMIT[1001] & ~reg_be))) | - (addr_hit[1002] & (|(SCMI_PERMIT[1002] & ~reg_be))) | - (addr_hit[1003] & (|(SCMI_PERMIT[1003] & ~reg_be))) | - (addr_hit[1004] & (|(SCMI_PERMIT[1004] & ~reg_be))) | - (addr_hit[1005] & (|(SCMI_PERMIT[1005] & ~reg_be))) | - (addr_hit[1006] & (|(SCMI_PERMIT[1006] & ~reg_be))) | - (addr_hit[1007] & (|(SCMI_PERMIT[1007] & ~reg_be))) | - (addr_hit[1008] & (|(SCMI_PERMIT[1008] & ~reg_be))) | - (addr_hit[1009] & (|(SCMI_PERMIT[1009] & ~reg_be))) | - (addr_hit[1010] & (|(SCMI_PERMIT[1010] & ~reg_be))) | - (addr_hit[1011] & (|(SCMI_PERMIT[1011] & ~reg_be))) | - (addr_hit[1012] & (|(SCMI_PERMIT[1012] & ~reg_be))) | - (addr_hit[1013] & (|(SCMI_PERMIT[1013] & ~reg_be))) | - (addr_hit[1014] & (|(SCMI_PERMIT[1014] & ~reg_be))) | - (addr_hit[1015] & (|(SCMI_PERMIT[1015] & ~reg_be))) | - (addr_hit[1016] & (|(SCMI_PERMIT[1016] & ~reg_be))) | - (addr_hit[1017] & (|(SCMI_PERMIT[1017] & ~reg_be))) | - (addr_hit[1018] & (|(SCMI_PERMIT[1018] & ~reg_be))) | - (addr_hit[1019] & (|(SCMI_PERMIT[1019] & ~reg_be))) | - (addr_hit[1020] & (|(SCMI_PERMIT[1020] & ~reg_be))) | - (addr_hit[1021] & (|(SCMI_PERMIT[1021] & ~reg_be))) | - (addr_hit[1022] & (|(SCMI_PERMIT[1022] & ~reg_be))) | - (addr_hit[1023] & (|(SCMI_PERMIT[1023] & ~reg_be))) | - (addr_hit[1024] & (|(SCMI_PERMIT[1024] & ~reg_be))) | - (addr_hit[1025] & (|(SCMI_PERMIT[1025] & ~reg_be))) | - (addr_hit[1026] & (|(SCMI_PERMIT[1026] & ~reg_be))) | - (addr_hit[1027] & (|(SCMI_PERMIT[1027] & ~reg_be))) | - (addr_hit[1028] & (|(SCMI_PERMIT[1028] & ~reg_be))) | - (addr_hit[1029] & (|(SCMI_PERMIT[1029] & ~reg_be))) | - (addr_hit[1030] & (|(SCMI_PERMIT[1030] & ~reg_be))) | - (addr_hit[1031] & (|(SCMI_PERMIT[1031] & ~reg_be))) | - (addr_hit[1032] & (|(SCMI_PERMIT[1032] & ~reg_be))) | - (addr_hit[1033] & (|(SCMI_PERMIT[1033] & ~reg_be))) | - (addr_hit[1034] & (|(SCMI_PERMIT[1034] & ~reg_be))) | - (addr_hit[1035] & (|(SCMI_PERMIT[1035] & ~reg_be))) | - (addr_hit[1036] & (|(SCMI_PERMIT[1036] & ~reg_be))) | - (addr_hit[1037] & (|(SCMI_PERMIT[1037] & ~reg_be))) | - (addr_hit[1038] & (|(SCMI_PERMIT[1038] & ~reg_be))) | - (addr_hit[1039] & (|(SCMI_PERMIT[1039] & ~reg_be))) | - (addr_hit[1040] & (|(SCMI_PERMIT[1040] & ~reg_be))) | - (addr_hit[1041] & (|(SCMI_PERMIT[1041] & ~reg_be))) | - (addr_hit[1042] & (|(SCMI_PERMIT[1042] & ~reg_be))) | - (addr_hit[1043] & (|(SCMI_PERMIT[1043] & ~reg_be))) | - (addr_hit[1044] & (|(SCMI_PERMIT[1044] & ~reg_be))) | - (addr_hit[1045] & (|(SCMI_PERMIT[1045] & ~reg_be))) | - (addr_hit[1046] & (|(SCMI_PERMIT[1046] & ~reg_be))) | - (addr_hit[1047] & (|(SCMI_PERMIT[1047] & ~reg_be))) | - (addr_hit[1048] & (|(SCMI_PERMIT[1048] & ~reg_be))) | - (addr_hit[1049] & (|(SCMI_PERMIT[1049] & ~reg_be))) | - (addr_hit[1050] & (|(SCMI_PERMIT[1050] & ~reg_be))) | - (addr_hit[1051] & (|(SCMI_PERMIT[1051] & ~reg_be))) | - (addr_hit[1052] & (|(SCMI_PERMIT[1052] & ~reg_be))) | - (addr_hit[1053] & (|(SCMI_PERMIT[1053] & ~reg_be))) | - (addr_hit[1054] & (|(SCMI_PERMIT[1054] & ~reg_be))) | - (addr_hit[1055] & (|(SCMI_PERMIT[1055] & ~reg_be))) | - (addr_hit[1056] & (|(SCMI_PERMIT[1056] & ~reg_be))) | - (addr_hit[1057] & (|(SCMI_PERMIT[1057] & ~reg_be))) | - (addr_hit[1058] & (|(SCMI_PERMIT[1058] & ~reg_be))) | - (addr_hit[1059] & (|(SCMI_PERMIT[1059] & ~reg_be))) | - (addr_hit[1060] & (|(SCMI_PERMIT[1060] & ~reg_be))) | - (addr_hit[1061] & (|(SCMI_PERMIT[1061] & ~reg_be))) | - (addr_hit[1062] & (|(SCMI_PERMIT[1062] & ~reg_be))) | - (addr_hit[1063] & (|(SCMI_PERMIT[1063] & ~reg_be))) | - (addr_hit[1064] & (|(SCMI_PERMIT[1064] & ~reg_be))) | - (addr_hit[1065] & (|(SCMI_PERMIT[1065] & ~reg_be))) | - (addr_hit[1066] & (|(SCMI_PERMIT[1066] & ~reg_be))) | - (addr_hit[1067] & (|(SCMI_PERMIT[1067] & ~reg_be))) | - (addr_hit[1068] & (|(SCMI_PERMIT[1068] & ~reg_be))) | - (addr_hit[1069] & (|(SCMI_PERMIT[1069] & ~reg_be))) | - (addr_hit[1070] & (|(SCMI_PERMIT[1070] & ~reg_be))) | - (addr_hit[1071] & (|(SCMI_PERMIT[1071] & ~reg_be))) | - (addr_hit[1072] & (|(SCMI_PERMIT[1072] & ~reg_be))) | - (addr_hit[1073] & (|(SCMI_PERMIT[1073] & ~reg_be))) | - (addr_hit[1074] & (|(SCMI_PERMIT[1074] & ~reg_be))) | - (addr_hit[1075] & (|(SCMI_PERMIT[1075] & ~reg_be))) | - (addr_hit[1076] & (|(SCMI_PERMIT[1076] & ~reg_be))) | - (addr_hit[1077] & (|(SCMI_PERMIT[1077] & ~reg_be))) | - (addr_hit[1078] & (|(SCMI_PERMIT[1078] & ~reg_be))) | - (addr_hit[1079] & (|(SCMI_PERMIT[1079] & ~reg_be))) | - (addr_hit[1080] & (|(SCMI_PERMIT[1080] & ~reg_be))) | - (addr_hit[1081] & (|(SCMI_PERMIT[1081] & ~reg_be))) | - (addr_hit[1082] & (|(SCMI_PERMIT[1082] & ~reg_be))) | - (addr_hit[1083] & (|(SCMI_PERMIT[1083] & ~reg_be))) | - (addr_hit[1084] & (|(SCMI_PERMIT[1084] & ~reg_be))) | - (addr_hit[1085] & (|(SCMI_PERMIT[1085] & ~reg_be))) | - (addr_hit[1086] & (|(SCMI_PERMIT[1086] & ~reg_be))) | - (addr_hit[1087] & (|(SCMI_PERMIT[1087] & ~reg_be))) | - (addr_hit[1088] & (|(SCMI_PERMIT[1088] & ~reg_be))) | - (addr_hit[1089] & (|(SCMI_PERMIT[1089] & ~reg_be))) | - (addr_hit[1090] & (|(SCMI_PERMIT[1090] & ~reg_be))) | - (addr_hit[1091] & (|(SCMI_PERMIT[1091] & ~reg_be))) | - (addr_hit[1092] & (|(SCMI_PERMIT[1092] & ~reg_be))) | - (addr_hit[1093] & (|(SCMI_PERMIT[1093] & ~reg_be))) | - (addr_hit[1094] & (|(SCMI_PERMIT[1094] & ~reg_be))) | - (addr_hit[1095] & (|(SCMI_PERMIT[1095] & ~reg_be))) | - (addr_hit[1096] & (|(SCMI_PERMIT[1096] & ~reg_be))) | - (addr_hit[1097] & (|(SCMI_PERMIT[1097] & ~reg_be))) | - (addr_hit[1098] & (|(SCMI_PERMIT[1098] & ~reg_be))) | - (addr_hit[1099] & (|(SCMI_PERMIT[1099] & ~reg_be))) | - (addr_hit[1100] & (|(SCMI_PERMIT[1100] & ~reg_be))) | - (addr_hit[1101] & (|(SCMI_PERMIT[1101] & ~reg_be))) | - (addr_hit[1102] & (|(SCMI_PERMIT[1102] & ~reg_be))) | - (addr_hit[1103] & (|(SCMI_PERMIT[1103] & ~reg_be))) | - (addr_hit[1104] & (|(SCMI_PERMIT[1104] & ~reg_be))) | - (addr_hit[1105] & (|(SCMI_PERMIT[1105] & ~reg_be))) | - (addr_hit[1106] & (|(SCMI_PERMIT[1106] & ~reg_be))) | - (addr_hit[1107] & (|(SCMI_PERMIT[1107] & ~reg_be))) | - (addr_hit[1108] & (|(SCMI_PERMIT[1108] & ~reg_be))) | - (addr_hit[1109] & (|(SCMI_PERMIT[1109] & ~reg_be))) | - (addr_hit[1110] & (|(SCMI_PERMIT[1110] & ~reg_be))) | - (addr_hit[1111] & (|(SCMI_PERMIT[1111] & ~reg_be))) | - (addr_hit[1112] & (|(SCMI_PERMIT[1112] & ~reg_be))) | - (addr_hit[1113] & (|(SCMI_PERMIT[1113] & ~reg_be))) | - (addr_hit[1114] & (|(SCMI_PERMIT[1114] & ~reg_be))) | - (addr_hit[1115] & (|(SCMI_PERMIT[1115] & ~reg_be))) | - (addr_hit[1116] & (|(SCMI_PERMIT[1116] & ~reg_be))) | - (addr_hit[1117] & (|(SCMI_PERMIT[1117] & ~reg_be))) | - (addr_hit[1118] & (|(SCMI_PERMIT[1118] & ~reg_be))) | - (addr_hit[1119] & (|(SCMI_PERMIT[1119] & ~reg_be))) | - (addr_hit[1120] & (|(SCMI_PERMIT[1120] & ~reg_be))) | - (addr_hit[1121] & (|(SCMI_PERMIT[1121] & ~reg_be))) | - (addr_hit[1122] & (|(SCMI_PERMIT[1122] & ~reg_be))) | - (addr_hit[1123] & (|(SCMI_PERMIT[1123] & ~reg_be))) | - (addr_hit[1124] & (|(SCMI_PERMIT[1124] & ~reg_be))) | - (addr_hit[1125] & (|(SCMI_PERMIT[1125] & ~reg_be))) | - (addr_hit[1126] & (|(SCMI_PERMIT[1126] & ~reg_be))) | - (addr_hit[1127] & (|(SCMI_PERMIT[1127] & ~reg_be))) | - (addr_hit[1128] & (|(SCMI_PERMIT[1128] & ~reg_be))) | - (addr_hit[1129] & (|(SCMI_PERMIT[1129] & ~reg_be))) | - (addr_hit[1130] & (|(SCMI_PERMIT[1130] & ~reg_be))) | - (addr_hit[1131] & (|(SCMI_PERMIT[1131] & ~reg_be))) | - (addr_hit[1132] & (|(SCMI_PERMIT[1132] & ~reg_be))) | - (addr_hit[1133] & (|(SCMI_PERMIT[1133] & ~reg_be))) | - (addr_hit[1134] & (|(SCMI_PERMIT[1134] & ~reg_be))) | - (addr_hit[1135] & (|(SCMI_PERMIT[1135] & ~reg_be))) | - (addr_hit[1136] & (|(SCMI_PERMIT[1136] & ~reg_be))) | - (addr_hit[1137] & (|(SCMI_PERMIT[1137] & ~reg_be))) | - (addr_hit[1138] & (|(SCMI_PERMIT[1138] & ~reg_be))) | - (addr_hit[1139] & (|(SCMI_PERMIT[1139] & ~reg_be))) | - (addr_hit[1140] & (|(SCMI_PERMIT[1140] & ~reg_be))) | - (addr_hit[1141] & (|(SCMI_PERMIT[1141] & ~reg_be))) | - (addr_hit[1142] & (|(SCMI_PERMIT[1142] & ~reg_be))) | - (addr_hit[1143] & (|(SCMI_PERMIT[1143] & ~reg_be))) | - (addr_hit[1144] & (|(SCMI_PERMIT[1144] & ~reg_be))) | - (addr_hit[1145] & (|(SCMI_PERMIT[1145] & ~reg_be))) | - (addr_hit[1146] & (|(SCMI_PERMIT[1146] & ~reg_be))) | - (addr_hit[1147] & (|(SCMI_PERMIT[1147] & ~reg_be))) | - (addr_hit[1148] & (|(SCMI_PERMIT[1148] & ~reg_be))) | - (addr_hit[1149] & (|(SCMI_PERMIT[1149] & ~reg_be))) | - (addr_hit[1150] & (|(SCMI_PERMIT[1150] & ~reg_be))) | - (addr_hit[1151] & (|(SCMI_PERMIT[1151] & ~reg_be))) | - (addr_hit[1152] & (|(SCMI_PERMIT[1152] & ~reg_be))) | - (addr_hit[1153] & (|(SCMI_PERMIT[1153] & ~reg_be))) | - (addr_hit[1154] & (|(SCMI_PERMIT[1154] & ~reg_be))) | - (addr_hit[1155] & (|(SCMI_PERMIT[1155] & ~reg_be))) | - (addr_hit[1156] & (|(SCMI_PERMIT[1156] & ~reg_be))) | - (addr_hit[1157] & (|(SCMI_PERMIT[1157] & ~reg_be))) | - (addr_hit[1158] & (|(SCMI_PERMIT[1158] & ~reg_be))) | - (addr_hit[1159] & (|(SCMI_PERMIT[1159] & ~reg_be))) | - (addr_hit[1160] & (|(SCMI_PERMIT[1160] & ~reg_be))) | - (addr_hit[1161] & (|(SCMI_PERMIT[1161] & ~reg_be))) | - (addr_hit[1162] & (|(SCMI_PERMIT[1162] & ~reg_be))) | - (addr_hit[1163] & (|(SCMI_PERMIT[1163] & ~reg_be))) | - (addr_hit[1164] & (|(SCMI_PERMIT[1164] & ~reg_be))) | - (addr_hit[1165] & (|(SCMI_PERMIT[1165] & ~reg_be))) | - (addr_hit[1166] & (|(SCMI_PERMIT[1166] & ~reg_be))) | - (addr_hit[1167] & (|(SCMI_PERMIT[1167] & ~reg_be))) | - (addr_hit[1168] & (|(SCMI_PERMIT[1168] & ~reg_be))) | - (addr_hit[1169] & (|(SCMI_PERMIT[1169] & ~reg_be))) | - (addr_hit[1170] & (|(SCMI_PERMIT[1170] & ~reg_be))) | - (addr_hit[1171] & (|(SCMI_PERMIT[1171] & ~reg_be))) | - (addr_hit[1172] & (|(SCMI_PERMIT[1172] & ~reg_be))) | - (addr_hit[1173] & (|(SCMI_PERMIT[1173] & ~reg_be))) | - (addr_hit[1174] & (|(SCMI_PERMIT[1174] & ~reg_be))) | - (addr_hit[1175] & (|(SCMI_PERMIT[1175] & ~reg_be))) | - (addr_hit[1176] & (|(SCMI_PERMIT[1176] & ~reg_be))) | - (addr_hit[1177] & (|(SCMI_PERMIT[1177] & ~reg_be))) | - (addr_hit[1178] & (|(SCMI_PERMIT[1178] & ~reg_be))) | - (addr_hit[1179] & (|(SCMI_PERMIT[1179] & ~reg_be))) | - (addr_hit[1180] & (|(SCMI_PERMIT[1180] & ~reg_be))) | - (addr_hit[1181] & (|(SCMI_PERMIT[1181] & ~reg_be))) | - (addr_hit[1182] & (|(SCMI_PERMIT[1182] & ~reg_be))) | - (addr_hit[1183] & (|(SCMI_PERMIT[1183] & ~reg_be))) | - (addr_hit[1184] & (|(SCMI_PERMIT[1184] & ~reg_be))) | - (addr_hit[1185] & (|(SCMI_PERMIT[1185] & ~reg_be))) | - (addr_hit[1186] & (|(SCMI_PERMIT[1186] & ~reg_be))) | - (addr_hit[1187] & (|(SCMI_PERMIT[1187] & ~reg_be))) | - (addr_hit[1188] & (|(SCMI_PERMIT[1188] & ~reg_be))) | - (addr_hit[1189] & (|(SCMI_PERMIT[1189] & ~reg_be))) | - (addr_hit[1190] & (|(SCMI_PERMIT[1190] & ~reg_be))) | - (addr_hit[1191] & (|(SCMI_PERMIT[1191] & ~reg_be))) | - (addr_hit[1192] & (|(SCMI_PERMIT[1192] & ~reg_be))) | - (addr_hit[1193] & (|(SCMI_PERMIT[1193] & ~reg_be))) | - (addr_hit[1194] & (|(SCMI_PERMIT[1194] & ~reg_be))) | - (addr_hit[1195] & (|(SCMI_PERMIT[1195] & ~reg_be))) | - (addr_hit[1196] & (|(SCMI_PERMIT[1196] & ~reg_be))) | - (addr_hit[1197] & (|(SCMI_PERMIT[1197] & ~reg_be))) | - (addr_hit[1198] & (|(SCMI_PERMIT[1198] & ~reg_be))) | - (addr_hit[1199] & (|(SCMI_PERMIT[1199] & ~reg_be))) | - (addr_hit[1200] & (|(SCMI_PERMIT[1200] & ~reg_be))) | - (addr_hit[1201] & (|(SCMI_PERMIT[1201] & ~reg_be))) | - (addr_hit[1202] & (|(SCMI_PERMIT[1202] & ~reg_be))) | - (addr_hit[1203] & (|(SCMI_PERMIT[1203] & ~reg_be))) | - (addr_hit[1204] & (|(SCMI_PERMIT[1204] & ~reg_be))) | - (addr_hit[1205] & (|(SCMI_PERMIT[1205] & ~reg_be))) | - (addr_hit[1206] & (|(SCMI_PERMIT[1206] & ~reg_be))) | - (addr_hit[1207] & (|(SCMI_PERMIT[1207] & ~reg_be))) | - (addr_hit[1208] & (|(SCMI_PERMIT[1208] & ~reg_be))) | - (addr_hit[1209] & (|(SCMI_PERMIT[1209] & ~reg_be))) | - (addr_hit[1210] & (|(SCMI_PERMIT[1210] & ~reg_be))) | - (addr_hit[1211] & (|(SCMI_PERMIT[1211] & ~reg_be))) | - (addr_hit[1212] & (|(SCMI_PERMIT[1212] & ~reg_be))) | - (addr_hit[1213] & (|(SCMI_PERMIT[1213] & ~reg_be))) | - (addr_hit[1214] & (|(SCMI_PERMIT[1214] & ~reg_be))) | - (addr_hit[1215] & (|(SCMI_PERMIT[1215] & ~reg_be))) | - (addr_hit[1216] & (|(SCMI_PERMIT[1216] & ~reg_be))) | - (addr_hit[1217] & (|(SCMI_PERMIT[1217] & ~reg_be))) | - (addr_hit[1218] & (|(SCMI_PERMIT[1218] & ~reg_be))) | - (addr_hit[1219] & (|(SCMI_PERMIT[1219] & ~reg_be))) | - (addr_hit[1220] & (|(SCMI_PERMIT[1220] & ~reg_be))) | - (addr_hit[1221] & (|(SCMI_PERMIT[1221] & ~reg_be))) | - (addr_hit[1222] & (|(SCMI_PERMIT[1222] & ~reg_be))) | - (addr_hit[1223] & (|(SCMI_PERMIT[1223] & ~reg_be))) | - (addr_hit[1224] & (|(SCMI_PERMIT[1224] & ~reg_be))) | - (addr_hit[1225] & (|(SCMI_PERMIT[1225] & ~reg_be))) | - (addr_hit[1226] & (|(SCMI_PERMIT[1226] & ~reg_be))) | - (addr_hit[1227] & (|(SCMI_PERMIT[1227] & ~reg_be))) | - (addr_hit[1228] & (|(SCMI_PERMIT[1228] & ~reg_be))) | - (addr_hit[1229] & (|(SCMI_PERMIT[1229] & ~reg_be))) | - (addr_hit[1230] & (|(SCMI_PERMIT[1230] & ~reg_be))) | - (addr_hit[1231] & (|(SCMI_PERMIT[1231] & ~reg_be))) | - (addr_hit[1232] & (|(SCMI_PERMIT[1232] & ~reg_be))) | - (addr_hit[1233] & (|(SCMI_PERMIT[1233] & ~reg_be))) | - (addr_hit[1234] & (|(SCMI_PERMIT[1234] & ~reg_be))) | - (addr_hit[1235] & (|(SCMI_PERMIT[1235] & ~reg_be))) | - (addr_hit[1236] & (|(SCMI_PERMIT[1236] & ~reg_be))) | - (addr_hit[1237] & (|(SCMI_PERMIT[1237] & ~reg_be))) | - (addr_hit[1238] & (|(SCMI_PERMIT[1238] & ~reg_be))) | - (addr_hit[1239] & (|(SCMI_PERMIT[1239] & ~reg_be))) | - (addr_hit[1240] & (|(SCMI_PERMIT[1240] & ~reg_be))) | - (addr_hit[1241] & (|(SCMI_PERMIT[1241] & ~reg_be))) | - (addr_hit[1242] & (|(SCMI_PERMIT[1242] & ~reg_be))) | - (addr_hit[1243] & (|(SCMI_PERMIT[1243] & ~reg_be))) | - (addr_hit[1244] & (|(SCMI_PERMIT[1244] & ~reg_be))) | - (addr_hit[1245] & (|(SCMI_PERMIT[1245] & ~reg_be))) | - (addr_hit[1246] & (|(SCMI_PERMIT[1246] & ~reg_be))) | - (addr_hit[1247] & (|(SCMI_PERMIT[1247] & ~reg_be))) | - (addr_hit[1248] & (|(SCMI_PERMIT[1248] & ~reg_be))) | - (addr_hit[1249] & (|(SCMI_PERMIT[1249] & ~reg_be))) | - (addr_hit[1250] & (|(SCMI_PERMIT[1250] & ~reg_be))) | - (addr_hit[1251] & (|(SCMI_PERMIT[1251] & ~reg_be))) | - (addr_hit[1252] & (|(SCMI_PERMIT[1252] & ~reg_be))) | - (addr_hit[1253] & (|(SCMI_PERMIT[1253] & ~reg_be))) | - (addr_hit[1254] & (|(SCMI_PERMIT[1254] & ~reg_be))) | - (addr_hit[1255] & (|(SCMI_PERMIT[1255] & ~reg_be))) | - (addr_hit[1256] & (|(SCMI_PERMIT[1256] & ~reg_be))) | - (addr_hit[1257] & (|(SCMI_PERMIT[1257] & ~reg_be))) | - (addr_hit[1258] & (|(SCMI_PERMIT[1258] & ~reg_be))) | - (addr_hit[1259] & (|(SCMI_PERMIT[1259] & ~reg_be))) | - (addr_hit[1260] & (|(SCMI_PERMIT[1260] & ~reg_be))) | - (addr_hit[1261] & (|(SCMI_PERMIT[1261] & ~reg_be))) | - (addr_hit[1262] & (|(SCMI_PERMIT[1262] & ~reg_be))) | - (addr_hit[1263] & (|(SCMI_PERMIT[1263] & ~reg_be))) | - (addr_hit[1264] & (|(SCMI_PERMIT[1264] & ~reg_be))) | - (addr_hit[1265] & (|(SCMI_PERMIT[1265] & ~reg_be))) | - (addr_hit[1266] & (|(SCMI_PERMIT[1266] & ~reg_be))) | - (addr_hit[1267] & (|(SCMI_PERMIT[1267] & ~reg_be))) | - (addr_hit[1268] & (|(SCMI_PERMIT[1268] & ~reg_be))) | - (addr_hit[1269] & (|(SCMI_PERMIT[1269] & ~reg_be))) | - (addr_hit[1270] & (|(SCMI_PERMIT[1270] & ~reg_be))) | - (addr_hit[1271] & (|(SCMI_PERMIT[1271] & ~reg_be))) | - (addr_hit[1272] & (|(SCMI_PERMIT[1272] & ~reg_be))) | - (addr_hit[1273] & (|(SCMI_PERMIT[1273] & ~reg_be))) | - (addr_hit[1274] & (|(SCMI_PERMIT[1274] & ~reg_be))) | - (addr_hit[1275] & (|(SCMI_PERMIT[1275] & ~reg_be))) | - (addr_hit[1276] & (|(SCMI_PERMIT[1276] & ~reg_be))) | - (addr_hit[1277] & (|(SCMI_PERMIT[1277] & ~reg_be))) | - (addr_hit[1278] & (|(SCMI_PERMIT[1278] & ~reg_be))) | - (addr_hit[1279] & (|(SCMI_PERMIT[1279] & ~reg_be))) | - (addr_hit[1280] & (|(SCMI_PERMIT[1280] & ~reg_be))) | - (addr_hit[1281] & (|(SCMI_PERMIT[1281] & ~reg_be))) | - (addr_hit[1282] & (|(SCMI_PERMIT[1282] & ~reg_be))) | - (addr_hit[1283] & (|(SCMI_PERMIT[1283] & ~reg_be))) | - (addr_hit[1284] & (|(SCMI_PERMIT[1284] & ~reg_be))) | - (addr_hit[1285] & (|(SCMI_PERMIT[1285] & ~reg_be))) | - (addr_hit[1286] & (|(SCMI_PERMIT[1286] & ~reg_be))) | - (addr_hit[1287] & (|(SCMI_PERMIT[1287] & ~reg_be))) | - (addr_hit[1288] & (|(SCMI_PERMIT[1288] & ~reg_be))) | - (addr_hit[1289] & (|(SCMI_PERMIT[1289] & ~reg_be))) | - (addr_hit[1290] & (|(SCMI_PERMIT[1290] & ~reg_be))) | - (addr_hit[1291] & (|(SCMI_PERMIT[1291] & ~reg_be))) | - (addr_hit[1292] & (|(SCMI_PERMIT[1292] & ~reg_be))) | - (addr_hit[1293] & (|(SCMI_PERMIT[1293] & ~reg_be))) | - (addr_hit[1294] & (|(SCMI_PERMIT[1294] & ~reg_be))) | - (addr_hit[1295] & (|(SCMI_PERMIT[1295] & ~reg_be))) | - (addr_hit[1296] & (|(SCMI_PERMIT[1296] & ~reg_be))) | - (addr_hit[1297] & (|(SCMI_PERMIT[1297] & ~reg_be))) | - (addr_hit[1298] & (|(SCMI_PERMIT[1298] & ~reg_be))) | - (addr_hit[1299] & (|(SCMI_PERMIT[1299] & ~reg_be))) | - (addr_hit[1300] & (|(SCMI_PERMIT[1300] & ~reg_be))) | - (addr_hit[1301] & (|(SCMI_PERMIT[1301] & ~reg_be))) | - (addr_hit[1302] & (|(SCMI_PERMIT[1302] & ~reg_be))) | - (addr_hit[1303] & (|(SCMI_PERMIT[1303] & ~reg_be))) | - (addr_hit[1304] & (|(SCMI_PERMIT[1304] & ~reg_be))) | - (addr_hit[1305] & (|(SCMI_PERMIT[1305] & ~reg_be))) | - (addr_hit[1306] & (|(SCMI_PERMIT[1306] & ~reg_be))) | - (addr_hit[1307] & (|(SCMI_PERMIT[1307] & ~reg_be))) | - (addr_hit[1308] & (|(SCMI_PERMIT[1308] & ~reg_be))) | - (addr_hit[1309] & (|(SCMI_PERMIT[1309] & ~reg_be))) | - (addr_hit[1310] & (|(SCMI_PERMIT[1310] & ~reg_be))) | - (addr_hit[1311] & (|(SCMI_PERMIT[1311] & ~reg_be))) | - (addr_hit[1312] & (|(SCMI_PERMIT[1312] & ~reg_be))) | - (addr_hit[1313] & (|(SCMI_PERMIT[1313] & ~reg_be))) | - (addr_hit[1314] & (|(SCMI_PERMIT[1314] & ~reg_be))) | - (addr_hit[1315] & (|(SCMI_PERMIT[1315] & ~reg_be))) | - (addr_hit[1316] & (|(SCMI_PERMIT[1316] & ~reg_be))) | - (addr_hit[1317] & (|(SCMI_PERMIT[1317] & ~reg_be))) | - (addr_hit[1318] & (|(SCMI_PERMIT[1318] & ~reg_be))) | - (addr_hit[1319] & (|(SCMI_PERMIT[1319] & ~reg_be))) | - (addr_hit[1320] & (|(SCMI_PERMIT[1320] & ~reg_be))) | - (addr_hit[1321] & (|(SCMI_PERMIT[1321] & ~reg_be))) | - (addr_hit[1322] & (|(SCMI_PERMIT[1322] & ~reg_be))) | - (addr_hit[1323] & (|(SCMI_PERMIT[1323] & ~reg_be))) | - (addr_hit[1324] & (|(SCMI_PERMIT[1324] & ~reg_be))) | - (addr_hit[1325] & (|(SCMI_PERMIT[1325] & ~reg_be))) | - (addr_hit[1326] & (|(SCMI_PERMIT[1326] & ~reg_be))) | - (addr_hit[1327] & (|(SCMI_PERMIT[1327] & ~reg_be))) | - (addr_hit[1328] & (|(SCMI_PERMIT[1328] & ~reg_be))) | - (addr_hit[1329] & (|(SCMI_PERMIT[1329] & ~reg_be))) | - (addr_hit[1330] & (|(SCMI_PERMIT[1330] & ~reg_be))) | - (addr_hit[1331] & (|(SCMI_PERMIT[1331] & ~reg_be))) | - (addr_hit[1332] & (|(SCMI_PERMIT[1332] & ~reg_be))) | - (addr_hit[1333] & (|(SCMI_PERMIT[1333] & ~reg_be))) | - (addr_hit[1334] & (|(SCMI_PERMIT[1334] & ~reg_be))) | - (addr_hit[1335] & (|(SCMI_PERMIT[1335] & ~reg_be))) | - (addr_hit[1336] & (|(SCMI_PERMIT[1336] & ~reg_be))) | - (addr_hit[1337] & (|(SCMI_PERMIT[1337] & ~reg_be))) | - (addr_hit[1338] & (|(SCMI_PERMIT[1338] & ~reg_be))) | - (addr_hit[1339] & (|(SCMI_PERMIT[1339] & ~reg_be))) | - (addr_hit[1340] & (|(SCMI_PERMIT[1340] & ~reg_be))) | - (addr_hit[1341] & (|(SCMI_PERMIT[1341] & ~reg_be))) | - (addr_hit[1342] & (|(SCMI_PERMIT[1342] & ~reg_be))) | - (addr_hit[1343] & (|(SCMI_PERMIT[1343] & ~reg_be))) | - (addr_hit[1344] & (|(SCMI_PERMIT[1344] & ~reg_be))) | - (addr_hit[1345] & (|(SCMI_PERMIT[1345] & ~reg_be))) | - (addr_hit[1346] & (|(SCMI_PERMIT[1346] & ~reg_be))) | - (addr_hit[1347] & (|(SCMI_PERMIT[1347] & ~reg_be))) | - (addr_hit[1348] & (|(SCMI_PERMIT[1348] & ~reg_be))) | - (addr_hit[1349] & (|(SCMI_PERMIT[1349] & ~reg_be))) | - (addr_hit[1350] & (|(SCMI_PERMIT[1350] & ~reg_be))) | - (addr_hit[1351] & (|(SCMI_PERMIT[1351] & ~reg_be))) | - (addr_hit[1352] & (|(SCMI_PERMIT[1352] & ~reg_be))) | - (addr_hit[1353] & (|(SCMI_PERMIT[1353] & ~reg_be))) | - (addr_hit[1354] & (|(SCMI_PERMIT[1354] & ~reg_be))) | - (addr_hit[1355] & (|(SCMI_PERMIT[1355] & ~reg_be))) | - (addr_hit[1356] & (|(SCMI_PERMIT[1356] & ~reg_be))) | - (addr_hit[1357] & (|(SCMI_PERMIT[1357] & ~reg_be))) | - (addr_hit[1358] & (|(SCMI_PERMIT[1358] & ~reg_be))) | - (addr_hit[1359] & (|(SCMI_PERMIT[1359] & ~reg_be))) | - (addr_hit[1360] & (|(SCMI_PERMIT[1360] & ~reg_be))) | - (addr_hit[1361] & (|(SCMI_PERMIT[1361] & ~reg_be))) | - (addr_hit[1362] & (|(SCMI_PERMIT[1362] & ~reg_be))) | - (addr_hit[1363] & (|(SCMI_PERMIT[1363] & ~reg_be))) | - (addr_hit[1364] & (|(SCMI_PERMIT[1364] & ~reg_be))) | - (addr_hit[1365] & (|(SCMI_PERMIT[1365] & ~reg_be))) | - (addr_hit[1366] & (|(SCMI_PERMIT[1366] & ~reg_be))) | - (addr_hit[1367] & (|(SCMI_PERMIT[1367] & ~reg_be))) | - (addr_hit[1368] & (|(SCMI_PERMIT[1368] & ~reg_be))) | - (addr_hit[1369] & (|(SCMI_PERMIT[1369] & ~reg_be))) | - (addr_hit[1370] & (|(SCMI_PERMIT[1370] & ~reg_be))) | - (addr_hit[1371] & (|(SCMI_PERMIT[1371] & ~reg_be))) | - (addr_hit[1372] & (|(SCMI_PERMIT[1372] & ~reg_be))) | - (addr_hit[1373] & (|(SCMI_PERMIT[1373] & ~reg_be))) | - (addr_hit[1374] & (|(SCMI_PERMIT[1374] & ~reg_be))) | - (addr_hit[1375] & (|(SCMI_PERMIT[1375] & ~reg_be))) | - (addr_hit[1376] & (|(SCMI_PERMIT[1376] & ~reg_be))) | - (addr_hit[1377] & (|(SCMI_PERMIT[1377] & ~reg_be))) | - (addr_hit[1378] & (|(SCMI_PERMIT[1378] & ~reg_be))) | - (addr_hit[1379] & (|(SCMI_PERMIT[1379] & ~reg_be))) | - (addr_hit[1380] & (|(SCMI_PERMIT[1380] & ~reg_be))) | - (addr_hit[1381] & (|(SCMI_PERMIT[1381] & ~reg_be))) | - (addr_hit[1382] & (|(SCMI_PERMIT[1382] & ~reg_be))) | - (addr_hit[1383] & (|(SCMI_PERMIT[1383] & ~reg_be))) | - (addr_hit[1384] & (|(SCMI_PERMIT[1384] & ~reg_be))) | - (addr_hit[1385] & (|(SCMI_PERMIT[1385] & ~reg_be))) | - (addr_hit[1386] & (|(SCMI_PERMIT[1386] & ~reg_be))) | - (addr_hit[1387] & (|(SCMI_PERMIT[1387] & ~reg_be))) | - (addr_hit[1388] & (|(SCMI_PERMIT[1388] & ~reg_be))) | - (addr_hit[1389] & (|(SCMI_PERMIT[1389] & ~reg_be))) | - (addr_hit[1390] & (|(SCMI_PERMIT[1390] & ~reg_be))) | - (addr_hit[1391] & (|(SCMI_PERMIT[1391] & ~reg_be))) | - (addr_hit[1392] & (|(SCMI_PERMIT[1392] & ~reg_be))) | - (addr_hit[1393] & (|(SCMI_PERMIT[1393] & ~reg_be))) | - (addr_hit[1394] & (|(SCMI_PERMIT[1394] & ~reg_be))) | - (addr_hit[1395] & (|(SCMI_PERMIT[1395] & ~reg_be))) | - (addr_hit[1396] & (|(SCMI_PERMIT[1396] & ~reg_be))) | - (addr_hit[1397] & (|(SCMI_PERMIT[1397] & ~reg_be))) | - (addr_hit[1398] & (|(SCMI_PERMIT[1398] & ~reg_be))) | - (addr_hit[1399] & (|(SCMI_PERMIT[1399] & ~reg_be))) | - (addr_hit[1400] & (|(SCMI_PERMIT[1400] & ~reg_be))) | - (addr_hit[1401] & (|(SCMI_PERMIT[1401] & ~reg_be))) | - (addr_hit[1402] & (|(SCMI_PERMIT[1402] & ~reg_be))) | - (addr_hit[1403] & (|(SCMI_PERMIT[1403] & ~reg_be))) | - (addr_hit[1404] & (|(SCMI_PERMIT[1404] & ~reg_be))) | - (addr_hit[1405] & (|(SCMI_PERMIT[1405] & ~reg_be))) | - (addr_hit[1406] & (|(SCMI_PERMIT[1406] & ~reg_be))) | - (addr_hit[1407] & (|(SCMI_PERMIT[1407] & ~reg_be))) | - (addr_hit[1408] & (|(SCMI_PERMIT[1408] & ~reg_be))) | - (addr_hit[1409] & (|(SCMI_PERMIT[1409] & ~reg_be))) | - (addr_hit[1410] & (|(SCMI_PERMIT[1410] & ~reg_be))) | - (addr_hit[1411] & (|(SCMI_PERMIT[1411] & ~reg_be))) | - (addr_hit[1412] & (|(SCMI_PERMIT[1412] & ~reg_be))) | - (addr_hit[1413] & (|(SCMI_PERMIT[1413] & ~reg_be))) | - (addr_hit[1414] & (|(SCMI_PERMIT[1414] & ~reg_be))) | - (addr_hit[1415] & (|(SCMI_PERMIT[1415] & ~reg_be))) | - (addr_hit[1416] & (|(SCMI_PERMIT[1416] & ~reg_be))) | - (addr_hit[1417] & (|(SCMI_PERMIT[1417] & ~reg_be))) | - (addr_hit[1418] & (|(SCMI_PERMIT[1418] & ~reg_be))) | - (addr_hit[1419] & (|(SCMI_PERMIT[1419] & ~reg_be))) | - (addr_hit[1420] & (|(SCMI_PERMIT[1420] & ~reg_be))) | - (addr_hit[1421] & (|(SCMI_PERMIT[1421] & ~reg_be))) | - (addr_hit[1422] & (|(SCMI_PERMIT[1422] & ~reg_be))) | - (addr_hit[1423] & (|(SCMI_PERMIT[1423] & ~reg_be))) | - (addr_hit[1424] & (|(SCMI_PERMIT[1424] & ~reg_be))) | - (addr_hit[1425] & (|(SCMI_PERMIT[1425] & ~reg_be))) | - (addr_hit[1426] & (|(SCMI_PERMIT[1426] & ~reg_be))) | - (addr_hit[1427] & (|(SCMI_PERMIT[1427] & ~reg_be))) | - (addr_hit[1428] & (|(SCMI_PERMIT[1428] & ~reg_be))) | - (addr_hit[1429] & (|(SCMI_PERMIT[1429] & ~reg_be))) | - (addr_hit[1430] & (|(SCMI_PERMIT[1430] & ~reg_be))) | - (addr_hit[1431] & (|(SCMI_PERMIT[1431] & ~reg_be))) | - (addr_hit[1432] & (|(SCMI_PERMIT[1432] & ~reg_be))) | - (addr_hit[1433] & (|(SCMI_PERMIT[1433] & ~reg_be))) | - (addr_hit[1434] & (|(SCMI_PERMIT[1434] & ~reg_be))) | - (addr_hit[1435] & (|(SCMI_PERMIT[1435] & ~reg_be))) | - (addr_hit[1436] & (|(SCMI_PERMIT[1436] & ~reg_be))) | - (addr_hit[1437] & (|(SCMI_PERMIT[1437] & ~reg_be))) | - (addr_hit[1438] & (|(SCMI_PERMIT[1438] & ~reg_be))) | - (addr_hit[1439] & (|(SCMI_PERMIT[1439] & ~reg_be))) | - (addr_hit[1440] & (|(SCMI_PERMIT[1440] & ~reg_be))) | - (addr_hit[1441] & (|(SCMI_PERMIT[1441] & ~reg_be))) | - (addr_hit[1442] & (|(SCMI_PERMIT[1442] & ~reg_be))) | - (addr_hit[1443] & (|(SCMI_PERMIT[1443] & ~reg_be))) | - (addr_hit[1444] & (|(SCMI_PERMIT[1444] & ~reg_be))) | - (addr_hit[1445] & (|(SCMI_PERMIT[1445] & ~reg_be))) | - (addr_hit[1446] & (|(SCMI_PERMIT[1446] & ~reg_be))) | - (addr_hit[1447] & (|(SCMI_PERMIT[1447] & ~reg_be))) | - (addr_hit[1448] & (|(SCMI_PERMIT[1448] & ~reg_be))) | - (addr_hit[1449] & (|(SCMI_PERMIT[1449] & ~reg_be))) | - (addr_hit[1450] & (|(SCMI_PERMIT[1450] & ~reg_be))) | - (addr_hit[1451] & (|(SCMI_PERMIT[1451] & ~reg_be))) | - (addr_hit[1452] & (|(SCMI_PERMIT[1452] & ~reg_be))) | - (addr_hit[1453] & (|(SCMI_PERMIT[1453] & ~reg_be))) | - (addr_hit[1454] & (|(SCMI_PERMIT[1454] & ~reg_be))) | - (addr_hit[1455] & (|(SCMI_PERMIT[1455] & ~reg_be))) | - (addr_hit[1456] & (|(SCMI_PERMIT[1456] & ~reg_be))) | - (addr_hit[1457] & (|(SCMI_PERMIT[1457] & ~reg_be))) | - (addr_hit[1458] & (|(SCMI_PERMIT[1458] & ~reg_be))) | - (addr_hit[1459] & (|(SCMI_PERMIT[1459] & ~reg_be))) | - (addr_hit[1460] & (|(SCMI_PERMIT[1460] & ~reg_be))) | - (addr_hit[1461] & (|(SCMI_PERMIT[1461] & ~reg_be))) | - (addr_hit[1462] & (|(SCMI_PERMIT[1462] & ~reg_be))) | - (addr_hit[1463] & (|(SCMI_PERMIT[1463] & ~reg_be))) | - (addr_hit[1464] & (|(SCMI_PERMIT[1464] & ~reg_be))) | - (addr_hit[1465] & (|(SCMI_PERMIT[1465] & ~reg_be))) | - (addr_hit[1466] & (|(SCMI_PERMIT[1466] & ~reg_be))) | - (addr_hit[1467] & (|(SCMI_PERMIT[1467] & ~reg_be))) | - (addr_hit[1468] & (|(SCMI_PERMIT[1468] & ~reg_be))) | - (addr_hit[1469] & (|(SCMI_PERMIT[1469] & ~reg_be))))); - end - - assign reserved_1_c0_we = addr_hit[0] & reg_we & !reg_error; - assign reserved_1_c0_wd = reg_wdata[31:0]; - - assign channel_status_c0_channel_free_we = addr_hit[1] & reg_we & !reg_error; - assign channel_status_c0_channel_free_wd = reg_wdata[0]; - - assign channel_status_c0_channel_error_we = addr_hit[1] & reg_we & !reg_error; - assign channel_status_c0_channel_error_wd = reg_wdata[1]; - - assign channel_status_c0_field1_we = addr_hit[1] & reg_we & !reg_error; - assign channel_status_c0_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c0_we = addr_hit[2] & reg_we & !reg_error; - assign reserved_2_c0_wd = reg_wdata[31:0]; - - assign channel_flags_c0_intr_enable_we = addr_hit[4] & reg_we & !reg_error; - assign channel_flags_c0_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c0_field1_we = addr_hit[4] & reg_we & !reg_error; - assign channel_flags_c0_field1_wd = reg_wdata[31:1]; - - assign length_c0_we = addr_hit[5] & reg_we & !reg_error; - assign length_c0_wd = reg_wdata[31:0]; - - assign message_header_c0_message_id_we = addr_hit[6] & reg_we & !reg_error; - assign message_header_c0_message_id_wd = reg_wdata[7:0]; - - assign message_header_c0_message_type_we = addr_hit[6] & reg_we & !reg_error; - assign message_header_c0_message_type_wd = reg_wdata[9:8]; - - assign message_header_c0_protocol_id_we = addr_hit[6] & reg_we & !reg_error; - assign message_header_c0_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c0_token_we = addr_hit[6] & reg_we & !reg_error; - assign message_header_c0_token_wd = reg_wdata[27:18]; - - assign message_header_c0_field1_we = addr_hit[6] & reg_we & !reg_error; - assign message_header_c0_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c0_we = addr_hit[7] & reg_we & !reg_error; - assign message_payload_1_c0_wd = reg_wdata[31:0]; - - assign doorbell_c0_intr_we = addr_hit[8] & reg_we & !reg_error; - assign doorbell_c0_intr_wd = reg_wdata[0]; - - assign doorbell_c0_preserve_mask_we = addr_hit[8] & reg_we & !reg_error; - assign doorbell_c0_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c0_intr_we = addr_hit[9] & reg_we & !reg_error; - assign completion_interrupt_c0_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c0_preserve_mask_we = addr_hit[9] & reg_we & !reg_error; - assign completion_interrupt_c0_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c1_we = addr_hit[10] & reg_we & !reg_error; - assign reserved_1_c1_wd = reg_wdata[31:0]; - - assign channel_status_c1_channel_free_we = addr_hit[11] & reg_we & !reg_error; - assign channel_status_c1_channel_free_wd = reg_wdata[0]; - - assign channel_status_c1_channel_error_we = addr_hit[11] & reg_we & !reg_error; - assign channel_status_c1_channel_error_wd = reg_wdata[1]; - - assign channel_status_c1_field1_we = addr_hit[11] & reg_we & !reg_error; - assign channel_status_c1_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c1_we = addr_hit[12] & reg_we & !reg_error; - assign reserved_2_c1_wd = reg_wdata[31:0]; - - assign channel_flags_c1_intr_enable_we = addr_hit[14] & reg_we & !reg_error; - assign channel_flags_c1_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c1_field1_we = addr_hit[14] & reg_we & !reg_error; - assign channel_flags_c1_field1_wd = reg_wdata[31:1]; - - assign length_c1_we = addr_hit[15] & reg_we & !reg_error; - assign length_c1_wd = reg_wdata[31:0]; - - assign message_header_c1_message_id_we = addr_hit[16] & reg_we & !reg_error; - assign message_header_c1_message_id_wd = reg_wdata[7:0]; - - assign message_header_c1_message_type_we = addr_hit[16] & reg_we & !reg_error; - assign message_header_c1_message_type_wd = reg_wdata[9:8]; - - assign message_header_c1_protocol_id_we = addr_hit[16] & reg_we & !reg_error; - assign message_header_c1_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c1_token_we = addr_hit[16] & reg_we & !reg_error; - assign message_header_c1_token_wd = reg_wdata[27:18]; - - assign message_header_c1_field1_we = addr_hit[16] & reg_we & !reg_error; - assign message_header_c1_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c1_we = addr_hit[17] & reg_we & !reg_error; - assign message_payload_1_c1_wd = reg_wdata[31:0]; - - assign doorbell_c1_intr_we = addr_hit[18] & reg_we & !reg_error; - assign doorbell_c1_intr_wd = reg_wdata[0]; - - assign doorbell_c1_preserve_mask_we = addr_hit[18] & reg_we & !reg_error; - assign doorbell_c1_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c1_intr_we = addr_hit[19] & reg_we & !reg_error; - assign completion_interrupt_c1_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c1_preserve_mask_we = addr_hit[19] & reg_we & !reg_error; - assign completion_interrupt_c1_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c2_we = addr_hit[20] & reg_we & !reg_error; - assign reserved_1_c2_wd = reg_wdata[31:0]; - - assign channel_status_c2_channel_free_we = addr_hit[21] & reg_we & !reg_error; - assign channel_status_c2_channel_free_wd = reg_wdata[0]; - - assign channel_status_c2_channel_error_we = addr_hit[21] & reg_we & !reg_error; - assign channel_status_c2_channel_error_wd = reg_wdata[1]; - - assign channel_status_c2_field1_we = addr_hit[21] & reg_we & !reg_error; - assign channel_status_c2_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c2_we = addr_hit[22] & reg_we & !reg_error; - assign reserved_2_c2_wd = reg_wdata[31:0]; - - assign channel_flags_c2_intr_enable_we = addr_hit[24] & reg_we & !reg_error; - assign channel_flags_c2_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c2_field1_we = addr_hit[24] & reg_we & !reg_error; - assign channel_flags_c2_field1_wd = reg_wdata[31:1]; - - assign length_c2_we = addr_hit[25] & reg_we & !reg_error; - assign length_c2_wd = reg_wdata[31:0]; - - assign message_header_c2_message_id_we = addr_hit[26] & reg_we & !reg_error; - assign message_header_c2_message_id_wd = reg_wdata[7:0]; - - assign message_header_c2_message_type_we = addr_hit[26] & reg_we & !reg_error; - assign message_header_c2_message_type_wd = reg_wdata[9:8]; - - assign message_header_c2_protocol_id_we = addr_hit[26] & reg_we & !reg_error; - assign message_header_c2_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c2_token_we = addr_hit[26] & reg_we & !reg_error; - assign message_header_c2_token_wd = reg_wdata[27:18]; - - assign message_header_c2_field1_we = addr_hit[26] & reg_we & !reg_error; - assign message_header_c2_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c2_we = addr_hit[27] & reg_we & !reg_error; - assign message_payload_1_c2_wd = reg_wdata[31:0]; - - assign doorbell_c2_intr_we = addr_hit[28] & reg_we & !reg_error; - assign doorbell_c2_intr_wd = reg_wdata[0]; - - assign doorbell_c2_preserve_mask_we = addr_hit[28] & reg_we & !reg_error; - assign doorbell_c2_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c2_intr_we = addr_hit[29] & reg_we & !reg_error; - assign completion_interrupt_c2_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c2_preserve_mask_we = addr_hit[29] & reg_we & !reg_error; - assign completion_interrupt_c2_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c3_we = addr_hit[30] & reg_we & !reg_error; - assign reserved_1_c3_wd = reg_wdata[31:0]; - - assign channel_status_c3_channel_free_we = addr_hit[31] & reg_we & !reg_error; - assign channel_status_c3_channel_free_wd = reg_wdata[0]; - - assign channel_status_c3_channel_error_we = addr_hit[31] & reg_we & !reg_error; - assign channel_status_c3_channel_error_wd = reg_wdata[1]; - - assign channel_status_c3_field1_we = addr_hit[31] & reg_we & !reg_error; - assign channel_status_c3_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c3_we = addr_hit[32] & reg_we & !reg_error; - assign reserved_2_c3_wd = reg_wdata[31:0]; - - assign channel_flags_c3_intr_enable_we = addr_hit[34] & reg_we & !reg_error; - assign channel_flags_c3_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c3_field1_we = addr_hit[34] & reg_we & !reg_error; - assign channel_flags_c3_field1_wd = reg_wdata[31:1]; - - assign length_c3_we = addr_hit[35] & reg_we & !reg_error; - assign length_c3_wd = reg_wdata[31:0]; - - assign message_header_c3_message_id_we = addr_hit[36] & reg_we & !reg_error; - assign message_header_c3_message_id_wd = reg_wdata[7:0]; - - assign message_header_c3_message_type_we = addr_hit[36] & reg_we & !reg_error; - assign message_header_c3_message_type_wd = reg_wdata[9:8]; - - assign message_header_c3_protocol_id_we = addr_hit[36] & reg_we & !reg_error; - assign message_header_c3_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c3_token_we = addr_hit[36] & reg_we & !reg_error; - assign message_header_c3_token_wd = reg_wdata[27:18]; - - assign message_header_c3_field1_we = addr_hit[36] & reg_we & !reg_error; - assign message_header_c3_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c3_we = addr_hit[37] & reg_we & !reg_error; - assign message_payload_1_c3_wd = reg_wdata[31:0]; - - assign doorbell_c3_intr_we = addr_hit[38] & reg_we & !reg_error; - assign doorbell_c3_intr_wd = reg_wdata[0]; - - assign doorbell_c3_preserve_mask_we = addr_hit[38] & reg_we & !reg_error; - assign doorbell_c3_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c3_intr_we = addr_hit[39] & reg_we & !reg_error; - assign completion_interrupt_c3_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c3_preserve_mask_we = addr_hit[39] & reg_we & !reg_error; - assign completion_interrupt_c3_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c4_we = addr_hit[40] & reg_we & !reg_error; - assign reserved_1_c4_wd = reg_wdata[31:0]; - - assign channel_status_c4_channel_free_we = addr_hit[41] & reg_we & !reg_error; - assign channel_status_c4_channel_free_wd = reg_wdata[0]; - - assign channel_status_c4_channel_error_we = addr_hit[41] & reg_we & !reg_error; - assign channel_status_c4_channel_error_wd = reg_wdata[1]; - - assign channel_status_c4_field1_we = addr_hit[41] & reg_we & !reg_error; - assign channel_status_c4_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c4_we = addr_hit[42] & reg_we & !reg_error; - assign reserved_2_c4_wd = reg_wdata[31:0]; - - assign channel_flags_c4_intr_enable_we = addr_hit[44] & reg_we & !reg_error; - assign channel_flags_c4_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c4_field1_we = addr_hit[44] & reg_we & !reg_error; - assign channel_flags_c4_field1_wd = reg_wdata[31:1]; - - assign length_c4_we = addr_hit[45] & reg_we & !reg_error; - assign length_c4_wd = reg_wdata[31:0]; - - assign message_header_c4_message_id_we = addr_hit[46] & reg_we & !reg_error; - assign message_header_c4_message_id_wd = reg_wdata[7:0]; - - assign message_header_c4_message_type_we = addr_hit[46] & reg_we & !reg_error; - assign message_header_c4_message_type_wd = reg_wdata[9:8]; - - assign message_header_c4_protocol_id_we = addr_hit[46] & reg_we & !reg_error; - assign message_header_c4_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c4_token_we = addr_hit[46] & reg_we & !reg_error; - assign message_header_c4_token_wd = reg_wdata[27:18]; - - assign message_header_c4_field1_we = addr_hit[46] & reg_we & !reg_error; - assign message_header_c4_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c4_we = addr_hit[47] & reg_we & !reg_error; - assign message_payload_1_c4_wd = reg_wdata[31:0]; - - assign doorbell_c4_intr_we = addr_hit[48] & reg_we & !reg_error; - assign doorbell_c4_intr_wd = reg_wdata[0]; - - assign doorbell_c4_preserve_mask_we = addr_hit[48] & reg_we & !reg_error; - assign doorbell_c4_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c4_intr_we = addr_hit[49] & reg_we & !reg_error; - assign completion_interrupt_c4_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c4_preserve_mask_we = addr_hit[49] & reg_we & !reg_error; - assign completion_interrupt_c4_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c5_we = addr_hit[50] & reg_we & !reg_error; - assign reserved_1_c5_wd = reg_wdata[31:0]; - - assign channel_status_c5_channel_free_we = addr_hit[51] & reg_we & !reg_error; - assign channel_status_c5_channel_free_wd = reg_wdata[0]; - - assign channel_status_c5_channel_error_we = addr_hit[51] & reg_we & !reg_error; - assign channel_status_c5_channel_error_wd = reg_wdata[1]; - - assign channel_status_c5_field1_we = addr_hit[51] & reg_we & !reg_error; - assign channel_status_c5_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c5_we = addr_hit[52] & reg_we & !reg_error; - assign reserved_2_c5_wd = reg_wdata[31:0]; - - assign channel_flags_c5_intr_enable_we = addr_hit[54] & reg_we & !reg_error; - assign channel_flags_c5_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c5_field1_we = addr_hit[54] & reg_we & !reg_error; - assign channel_flags_c5_field1_wd = reg_wdata[31:1]; - - assign length_c5_we = addr_hit[55] & reg_we & !reg_error; - assign length_c5_wd = reg_wdata[31:0]; - - assign message_header_c5_message_id_we = addr_hit[56] & reg_we & !reg_error; - assign message_header_c5_message_id_wd = reg_wdata[7:0]; - - assign message_header_c5_message_type_we = addr_hit[56] & reg_we & !reg_error; - assign message_header_c5_message_type_wd = reg_wdata[9:8]; - - assign message_header_c5_protocol_id_we = addr_hit[56] & reg_we & !reg_error; - assign message_header_c5_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c5_token_we = addr_hit[56] & reg_we & !reg_error; - assign message_header_c5_token_wd = reg_wdata[27:18]; - - assign message_header_c5_field1_we = addr_hit[56] & reg_we & !reg_error; - assign message_header_c5_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c5_we = addr_hit[57] & reg_we & !reg_error; - assign message_payload_1_c5_wd = reg_wdata[31:0]; - - assign doorbell_c5_intr_we = addr_hit[58] & reg_we & !reg_error; - assign doorbell_c5_intr_wd = reg_wdata[0]; - - assign doorbell_c5_preserve_mask_we = addr_hit[58] & reg_we & !reg_error; - assign doorbell_c5_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c5_intr_we = addr_hit[59] & reg_we & !reg_error; - assign completion_interrupt_c5_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c5_preserve_mask_we = addr_hit[59] & reg_we & !reg_error; - assign completion_interrupt_c5_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c6_we = addr_hit[60] & reg_we & !reg_error; - assign reserved_1_c6_wd = reg_wdata[31:0]; - - assign channel_status_c6_channel_free_we = addr_hit[61] & reg_we & !reg_error; - assign channel_status_c6_channel_free_wd = reg_wdata[0]; - - assign channel_status_c6_channel_error_we = addr_hit[61] & reg_we & !reg_error; - assign channel_status_c6_channel_error_wd = reg_wdata[1]; - - assign channel_status_c6_field1_we = addr_hit[61] & reg_we & !reg_error; - assign channel_status_c6_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c6_we = addr_hit[62] & reg_we & !reg_error; - assign reserved_2_c6_wd = reg_wdata[31:0]; - - assign channel_flags_c6_intr_enable_we = addr_hit[64] & reg_we & !reg_error; - assign channel_flags_c6_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c6_field1_we = addr_hit[64] & reg_we & !reg_error; - assign channel_flags_c6_field1_wd = reg_wdata[31:1]; - - assign length_c6_we = addr_hit[65] & reg_we & !reg_error; - assign length_c6_wd = reg_wdata[31:0]; - - assign message_header_c6_message_id_we = addr_hit[66] & reg_we & !reg_error; - assign message_header_c6_message_id_wd = reg_wdata[7:0]; - - assign message_header_c6_message_type_we = addr_hit[66] & reg_we & !reg_error; - assign message_header_c6_message_type_wd = reg_wdata[9:8]; - - assign message_header_c6_protocol_id_we = addr_hit[66] & reg_we & !reg_error; - assign message_header_c6_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c6_token_we = addr_hit[66] & reg_we & !reg_error; - assign message_header_c6_token_wd = reg_wdata[27:18]; - - assign message_header_c6_field1_we = addr_hit[66] & reg_we & !reg_error; - assign message_header_c6_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c6_we = addr_hit[67] & reg_we & !reg_error; - assign message_payload_1_c6_wd = reg_wdata[31:0]; - - assign doorbell_c6_intr_we = addr_hit[68] & reg_we & !reg_error; - assign doorbell_c6_intr_wd = reg_wdata[0]; - - assign doorbell_c6_preserve_mask_we = addr_hit[68] & reg_we & !reg_error; - assign doorbell_c6_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c6_intr_we = addr_hit[69] & reg_we & !reg_error; - assign completion_interrupt_c6_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c6_preserve_mask_we = addr_hit[69] & reg_we & !reg_error; - assign completion_interrupt_c6_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c7_we = addr_hit[70] & reg_we & !reg_error; - assign reserved_1_c7_wd = reg_wdata[31:0]; - - assign channel_status_c7_channel_free_we = addr_hit[71] & reg_we & !reg_error; - assign channel_status_c7_channel_free_wd = reg_wdata[0]; - - assign channel_status_c7_channel_error_we = addr_hit[71] & reg_we & !reg_error; - assign channel_status_c7_channel_error_wd = reg_wdata[1]; - - assign channel_status_c7_field1_we = addr_hit[71] & reg_we & !reg_error; - assign channel_status_c7_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c7_we = addr_hit[72] & reg_we & !reg_error; - assign reserved_2_c7_wd = reg_wdata[31:0]; - - assign channel_flags_c7_intr_enable_we = addr_hit[74] & reg_we & !reg_error; - assign channel_flags_c7_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c7_field1_we = addr_hit[74] & reg_we & !reg_error; - assign channel_flags_c7_field1_wd = reg_wdata[31:1]; - - assign length_c7_we = addr_hit[75] & reg_we & !reg_error; - assign length_c7_wd = reg_wdata[31:0]; - - assign message_header_c7_message_id_we = addr_hit[76] & reg_we & !reg_error; - assign message_header_c7_message_id_wd = reg_wdata[7:0]; - - assign message_header_c7_message_type_we = addr_hit[76] & reg_we & !reg_error; - assign message_header_c7_message_type_wd = reg_wdata[9:8]; - - assign message_header_c7_protocol_id_we = addr_hit[76] & reg_we & !reg_error; - assign message_header_c7_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c7_token_we = addr_hit[76] & reg_we & !reg_error; - assign message_header_c7_token_wd = reg_wdata[27:18]; - - assign message_header_c7_field1_we = addr_hit[76] & reg_we & !reg_error; - assign message_header_c7_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c7_we = addr_hit[77] & reg_we & !reg_error; - assign message_payload_1_c7_wd = reg_wdata[31:0]; - - assign doorbell_c7_intr_we = addr_hit[78] & reg_we & !reg_error; - assign doorbell_c7_intr_wd = reg_wdata[0]; - - assign doorbell_c7_preserve_mask_we = addr_hit[78] & reg_we & !reg_error; - assign doorbell_c7_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c7_intr_we = addr_hit[79] & reg_we & !reg_error; - assign completion_interrupt_c7_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c7_preserve_mask_we = addr_hit[79] & reg_we & !reg_error; - assign completion_interrupt_c7_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c8_we = addr_hit[80] & reg_we & !reg_error; - assign reserved_1_c8_wd = reg_wdata[31:0]; - - assign channel_status_c8_channel_free_we = addr_hit[81] & reg_we & !reg_error; - assign channel_status_c8_channel_free_wd = reg_wdata[0]; - - assign channel_status_c8_channel_error_we = addr_hit[81] & reg_we & !reg_error; - assign channel_status_c8_channel_error_wd = reg_wdata[1]; - - assign channel_status_c8_field1_we = addr_hit[81] & reg_we & !reg_error; - assign channel_status_c8_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c8_we = addr_hit[82] & reg_we & !reg_error; - assign reserved_2_c8_wd = reg_wdata[31:0]; - - assign channel_flags_c8_intr_enable_we = addr_hit[84] & reg_we & !reg_error; - assign channel_flags_c8_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c8_field1_we = addr_hit[84] & reg_we & !reg_error; - assign channel_flags_c8_field1_wd = reg_wdata[31:1]; - - assign length_c8_we = addr_hit[85] & reg_we & !reg_error; - assign length_c8_wd = reg_wdata[31:0]; - - assign message_header_c8_message_id_we = addr_hit[86] & reg_we & !reg_error; - assign message_header_c8_message_id_wd = reg_wdata[7:0]; - - assign message_header_c8_message_type_we = addr_hit[86] & reg_we & !reg_error; - assign message_header_c8_message_type_wd = reg_wdata[9:8]; - - assign message_header_c8_protocol_id_we = addr_hit[86] & reg_we & !reg_error; - assign message_header_c8_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c8_token_we = addr_hit[86] & reg_we & !reg_error; - assign message_header_c8_token_wd = reg_wdata[27:18]; - - assign message_header_c8_field1_we = addr_hit[86] & reg_we & !reg_error; - assign message_header_c8_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c8_we = addr_hit[87] & reg_we & !reg_error; - assign message_payload_1_c8_wd = reg_wdata[31:0]; - - assign doorbell_c8_intr_we = addr_hit[88] & reg_we & !reg_error; - assign doorbell_c8_intr_wd = reg_wdata[0]; - - assign doorbell_c8_preserve_mask_we = addr_hit[88] & reg_we & !reg_error; - assign doorbell_c8_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c8_intr_we = addr_hit[89] & reg_we & !reg_error; - assign completion_interrupt_c8_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c8_preserve_mask_we = addr_hit[89] & reg_we & !reg_error; - assign completion_interrupt_c8_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c9_we = addr_hit[90] & reg_we & !reg_error; - assign reserved_1_c9_wd = reg_wdata[31:0]; - - assign channel_status_c9_channel_free_we = addr_hit[91] & reg_we & !reg_error; - assign channel_status_c9_channel_free_wd = reg_wdata[0]; - - assign channel_status_c9_channel_error_we = addr_hit[91] & reg_we & !reg_error; - assign channel_status_c9_channel_error_wd = reg_wdata[1]; - - assign channel_status_c9_field1_we = addr_hit[91] & reg_we & !reg_error; - assign channel_status_c9_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c9_we = addr_hit[92] & reg_we & !reg_error; - assign reserved_2_c9_wd = reg_wdata[31:0]; - - assign channel_flags_c9_intr_enable_we = addr_hit[94] & reg_we & !reg_error; - assign channel_flags_c9_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c9_field1_we = addr_hit[94] & reg_we & !reg_error; - assign channel_flags_c9_field1_wd = reg_wdata[31:1]; - - assign length_c9_we = addr_hit[95] & reg_we & !reg_error; - assign length_c9_wd = reg_wdata[31:0]; - - assign message_header_c9_message_id_we = addr_hit[96] & reg_we & !reg_error; - assign message_header_c9_message_id_wd = reg_wdata[7:0]; - - assign message_header_c9_message_type_we = addr_hit[96] & reg_we & !reg_error; - assign message_header_c9_message_type_wd = reg_wdata[9:8]; - - assign message_header_c9_protocol_id_we = addr_hit[96] & reg_we & !reg_error; - assign message_header_c9_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c9_token_we = addr_hit[96] & reg_we & !reg_error; - assign message_header_c9_token_wd = reg_wdata[27:18]; - - assign message_header_c9_field1_we = addr_hit[96] & reg_we & !reg_error; - assign message_header_c9_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c9_we = addr_hit[97] & reg_we & !reg_error; - assign message_payload_1_c9_wd = reg_wdata[31:0]; - - assign doorbell_c9_intr_we = addr_hit[98] & reg_we & !reg_error; - assign doorbell_c9_intr_wd = reg_wdata[0]; - - assign doorbell_c9_preserve_mask_we = addr_hit[98] & reg_we & !reg_error; - assign doorbell_c9_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c9_intr_we = addr_hit[99] & reg_we & !reg_error; - assign completion_interrupt_c9_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c9_preserve_mask_we = addr_hit[99] & reg_we & !reg_error; - assign completion_interrupt_c9_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c10_we = addr_hit[100] & reg_we & !reg_error; - assign reserved_1_c10_wd = reg_wdata[31:0]; - - assign channel_status_c10_channel_free_we = addr_hit[101] & reg_we & !reg_error; - assign channel_status_c10_channel_free_wd = reg_wdata[0]; - - assign channel_status_c10_channel_error_we = addr_hit[101] & reg_we & !reg_error; - assign channel_status_c10_channel_error_wd = reg_wdata[1]; - - assign channel_status_c10_field1_we = addr_hit[101] & reg_we & !reg_error; - assign channel_status_c10_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c10_we = addr_hit[102] & reg_we & !reg_error; - assign reserved_2_c10_wd = reg_wdata[31:0]; - - assign channel_flags_c10_intr_enable_we = addr_hit[104] & reg_we & !reg_error; - assign channel_flags_c10_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c10_field1_we = addr_hit[104] & reg_we & !reg_error; - assign channel_flags_c10_field1_wd = reg_wdata[31:1]; - - assign length_c10_we = addr_hit[105] & reg_we & !reg_error; - assign length_c10_wd = reg_wdata[31:0]; - - assign message_header_c10_message_id_we = addr_hit[106] & reg_we & !reg_error; - assign message_header_c10_message_id_wd = reg_wdata[7:0]; - - assign message_header_c10_message_type_we = addr_hit[106] & reg_we & !reg_error; - assign message_header_c10_message_type_wd = reg_wdata[9:8]; - - assign message_header_c10_protocol_id_we = addr_hit[106] & reg_we & !reg_error; - assign message_header_c10_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c10_token_we = addr_hit[106] & reg_we & !reg_error; - assign message_header_c10_token_wd = reg_wdata[27:18]; - - assign message_header_c10_field1_we = addr_hit[106] & reg_we & !reg_error; - assign message_header_c10_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c10_we = addr_hit[107] & reg_we & !reg_error; - assign message_payload_1_c10_wd = reg_wdata[31:0]; - - assign doorbell_c10_intr_we = addr_hit[108] & reg_we & !reg_error; - assign doorbell_c10_intr_wd = reg_wdata[0]; - - assign doorbell_c10_preserve_mask_we = addr_hit[108] & reg_we & !reg_error; - assign doorbell_c10_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c10_intr_we = addr_hit[109] & reg_we & !reg_error; - assign completion_interrupt_c10_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c10_preserve_mask_we = addr_hit[109] & reg_we & !reg_error; - assign completion_interrupt_c10_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c11_we = addr_hit[110] & reg_we & !reg_error; - assign reserved_1_c11_wd = reg_wdata[31:0]; - - assign channel_status_c11_channel_free_we = addr_hit[111] & reg_we & !reg_error; - assign channel_status_c11_channel_free_wd = reg_wdata[0]; - - assign channel_status_c11_channel_error_we = addr_hit[111] & reg_we & !reg_error; - assign channel_status_c11_channel_error_wd = reg_wdata[1]; - - assign channel_status_c11_field1_we = addr_hit[111] & reg_we & !reg_error; - assign channel_status_c11_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c11_we = addr_hit[112] & reg_we & !reg_error; - assign reserved_2_c11_wd = reg_wdata[31:0]; - - assign channel_flags_c11_intr_enable_we = addr_hit[114] & reg_we & !reg_error; - assign channel_flags_c11_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c11_field1_we = addr_hit[114] & reg_we & !reg_error; - assign channel_flags_c11_field1_wd = reg_wdata[31:1]; - - assign length_c11_we = addr_hit[115] & reg_we & !reg_error; - assign length_c11_wd = reg_wdata[31:0]; - - assign message_header_c11_message_id_we = addr_hit[116] & reg_we & !reg_error; - assign message_header_c11_message_id_wd = reg_wdata[7:0]; - - assign message_header_c11_message_type_we = addr_hit[116] & reg_we & !reg_error; - assign message_header_c11_message_type_wd = reg_wdata[9:8]; - - assign message_header_c11_protocol_id_we = addr_hit[116] & reg_we & !reg_error; - assign message_header_c11_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c11_token_we = addr_hit[116] & reg_we & !reg_error; - assign message_header_c11_token_wd = reg_wdata[27:18]; - - assign message_header_c11_field1_we = addr_hit[116] & reg_we & !reg_error; - assign message_header_c11_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c11_we = addr_hit[117] & reg_we & !reg_error; - assign message_payload_1_c11_wd = reg_wdata[31:0]; - - assign doorbell_c11_intr_we = addr_hit[118] & reg_we & !reg_error; - assign doorbell_c11_intr_wd = reg_wdata[0]; - - assign doorbell_c11_preserve_mask_we = addr_hit[118] & reg_we & !reg_error; - assign doorbell_c11_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c11_intr_we = addr_hit[119] & reg_we & !reg_error; - assign completion_interrupt_c11_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c11_preserve_mask_we = addr_hit[119] & reg_we & !reg_error; - assign completion_interrupt_c11_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c12_we = addr_hit[120] & reg_we & !reg_error; - assign reserved_1_c12_wd = reg_wdata[31:0]; - - assign channel_status_c12_channel_free_we = addr_hit[121] & reg_we & !reg_error; - assign channel_status_c12_channel_free_wd = reg_wdata[0]; - - assign channel_status_c12_channel_error_we = addr_hit[121] & reg_we & !reg_error; - assign channel_status_c12_channel_error_wd = reg_wdata[1]; - - assign channel_status_c12_field1_we = addr_hit[121] & reg_we & !reg_error; - assign channel_status_c12_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c12_we = addr_hit[122] & reg_we & !reg_error; - assign reserved_2_c12_wd = reg_wdata[31:0]; - - assign channel_flags_c12_intr_enable_we = addr_hit[124] & reg_we & !reg_error; - assign channel_flags_c12_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c12_field1_we = addr_hit[124] & reg_we & !reg_error; - assign channel_flags_c12_field1_wd = reg_wdata[31:1]; - - assign length_c12_we = addr_hit[125] & reg_we & !reg_error; - assign length_c12_wd = reg_wdata[31:0]; - - assign message_header_c12_message_id_we = addr_hit[126] & reg_we & !reg_error; - assign message_header_c12_message_id_wd = reg_wdata[7:0]; - - assign message_header_c12_message_type_we = addr_hit[126] & reg_we & !reg_error; - assign message_header_c12_message_type_wd = reg_wdata[9:8]; - - assign message_header_c12_protocol_id_we = addr_hit[126] & reg_we & !reg_error; - assign message_header_c12_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c12_token_we = addr_hit[126] & reg_we & !reg_error; - assign message_header_c12_token_wd = reg_wdata[27:18]; - - assign message_header_c12_field1_we = addr_hit[126] & reg_we & !reg_error; - assign message_header_c12_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c12_we = addr_hit[127] & reg_we & !reg_error; - assign message_payload_1_c12_wd = reg_wdata[31:0]; - - assign doorbell_c12_intr_we = addr_hit[128] & reg_we & !reg_error; - assign doorbell_c12_intr_wd = reg_wdata[0]; - - assign doorbell_c12_preserve_mask_we = addr_hit[128] & reg_we & !reg_error; - assign doorbell_c12_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c12_intr_we = addr_hit[129] & reg_we & !reg_error; - assign completion_interrupt_c12_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c12_preserve_mask_we = addr_hit[129] & reg_we & !reg_error; - assign completion_interrupt_c12_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c13_we = addr_hit[130] & reg_we & !reg_error; - assign reserved_1_c13_wd = reg_wdata[31:0]; - - assign channel_status_c13_channel_free_we = addr_hit[131] & reg_we & !reg_error; - assign channel_status_c13_channel_free_wd = reg_wdata[0]; - - assign channel_status_c13_channel_error_we = addr_hit[131] & reg_we & !reg_error; - assign channel_status_c13_channel_error_wd = reg_wdata[1]; - - assign channel_status_c13_field1_we = addr_hit[131] & reg_we & !reg_error; - assign channel_status_c13_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c13_we = addr_hit[132] & reg_we & !reg_error; - assign reserved_2_c13_wd = reg_wdata[31:0]; - - assign channel_flags_c13_intr_enable_we = addr_hit[134] & reg_we & !reg_error; - assign channel_flags_c13_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c13_field1_we = addr_hit[134] & reg_we & !reg_error; - assign channel_flags_c13_field1_wd = reg_wdata[31:1]; - - assign length_c13_we = addr_hit[135] & reg_we & !reg_error; - assign length_c13_wd = reg_wdata[31:0]; - - assign message_header_c13_message_id_we = addr_hit[136] & reg_we & !reg_error; - assign message_header_c13_message_id_wd = reg_wdata[7:0]; - - assign message_header_c13_message_type_we = addr_hit[136] & reg_we & !reg_error; - assign message_header_c13_message_type_wd = reg_wdata[9:8]; - - assign message_header_c13_protocol_id_we = addr_hit[136] & reg_we & !reg_error; - assign message_header_c13_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c13_token_we = addr_hit[136] & reg_we & !reg_error; - assign message_header_c13_token_wd = reg_wdata[27:18]; - - assign message_header_c13_field1_we = addr_hit[136] & reg_we & !reg_error; - assign message_header_c13_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c13_we = addr_hit[137] & reg_we & !reg_error; - assign message_payload_1_c13_wd = reg_wdata[31:0]; - - assign doorbell_c13_intr_we = addr_hit[138] & reg_we & !reg_error; - assign doorbell_c13_intr_wd = reg_wdata[0]; - - assign doorbell_c13_preserve_mask_we = addr_hit[138] & reg_we & !reg_error; - assign doorbell_c13_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c13_intr_we = addr_hit[139] & reg_we & !reg_error; - assign completion_interrupt_c13_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c13_preserve_mask_we = addr_hit[139] & reg_we & !reg_error; - assign completion_interrupt_c13_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c14_we = addr_hit[140] & reg_we & !reg_error; - assign reserved_1_c14_wd = reg_wdata[31:0]; - - assign channel_status_c14_channel_free_we = addr_hit[141] & reg_we & !reg_error; - assign channel_status_c14_channel_free_wd = reg_wdata[0]; - - assign channel_status_c14_channel_error_we = addr_hit[141] & reg_we & !reg_error; - assign channel_status_c14_channel_error_wd = reg_wdata[1]; - - assign channel_status_c14_field1_we = addr_hit[141] & reg_we & !reg_error; - assign channel_status_c14_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c14_we = addr_hit[142] & reg_we & !reg_error; - assign reserved_2_c14_wd = reg_wdata[31:0]; - - assign channel_flags_c14_intr_enable_we = addr_hit[144] & reg_we & !reg_error; - assign channel_flags_c14_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c14_field1_we = addr_hit[144] & reg_we & !reg_error; - assign channel_flags_c14_field1_wd = reg_wdata[31:1]; - - assign length_c14_we = addr_hit[145] & reg_we & !reg_error; - assign length_c14_wd = reg_wdata[31:0]; - - assign message_header_c14_message_id_we = addr_hit[146] & reg_we & !reg_error; - assign message_header_c14_message_id_wd = reg_wdata[7:0]; - - assign message_header_c14_message_type_we = addr_hit[146] & reg_we & !reg_error; - assign message_header_c14_message_type_wd = reg_wdata[9:8]; - - assign message_header_c14_protocol_id_we = addr_hit[146] & reg_we & !reg_error; - assign message_header_c14_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c14_token_we = addr_hit[146] & reg_we & !reg_error; - assign message_header_c14_token_wd = reg_wdata[27:18]; - - assign message_header_c14_field1_we = addr_hit[146] & reg_we & !reg_error; - assign message_header_c14_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c14_we = addr_hit[147] & reg_we & !reg_error; - assign message_payload_1_c14_wd = reg_wdata[31:0]; - - assign doorbell_c14_intr_we = addr_hit[148] & reg_we & !reg_error; - assign doorbell_c14_intr_wd = reg_wdata[0]; - - assign doorbell_c14_preserve_mask_we = addr_hit[148] & reg_we & !reg_error; - assign doorbell_c14_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c14_intr_we = addr_hit[149] & reg_we & !reg_error; - assign completion_interrupt_c14_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c14_preserve_mask_we = addr_hit[149] & reg_we & !reg_error; - assign completion_interrupt_c14_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c15_we = addr_hit[150] & reg_we & !reg_error; - assign reserved_1_c15_wd = reg_wdata[31:0]; - - assign channel_status_c15_channel_free_we = addr_hit[151] & reg_we & !reg_error; - assign channel_status_c15_channel_free_wd = reg_wdata[0]; - - assign channel_status_c15_channel_error_we = addr_hit[151] & reg_we & !reg_error; - assign channel_status_c15_channel_error_wd = reg_wdata[1]; - - assign channel_status_c15_field1_we = addr_hit[151] & reg_we & !reg_error; - assign channel_status_c15_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c15_we = addr_hit[152] & reg_we & !reg_error; - assign reserved_2_c15_wd = reg_wdata[31:0]; - - assign channel_flags_c15_intr_enable_we = addr_hit[154] & reg_we & !reg_error; - assign channel_flags_c15_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c15_field1_we = addr_hit[154] & reg_we & !reg_error; - assign channel_flags_c15_field1_wd = reg_wdata[31:1]; - - assign length_c15_we = addr_hit[155] & reg_we & !reg_error; - assign length_c15_wd = reg_wdata[31:0]; - - assign message_header_c15_message_id_we = addr_hit[156] & reg_we & !reg_error; - assign message_header_c15_message_id_wd = reg_wdata[7:0]; - - assign message_header_c15_message_type_we = addr_hit[156] & reg_we & !reg_error; - assign message_header_c15_message_type_wd = reg_wdata[9:8]; - - assign message_header_c15_protocol_id_we = addr_hit[156] & reg_we & !reg_error; - assign message_header_c15_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c15_token_we = addr_hit[156] & reg_we & !reg_error; - assign message_header_c15_token_wd = reg_wdata[27:18]; - - assign message_header_c15_field1_we = addr_hit[156] & reg_we & !reg_error; - assign message_header_c15_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c15_we = addr_hit[157] & reg_we & !reg_error; - assign message_payload_1_c15_wd = reg_wdata[31:0]; - - assign doorbell_c15_intr_we = addr_hit[158] & reg_we & !reg_error; - assign doorbell_c15_intr_wd = reg_wdata[0]; - - assign doorbell_c15_preserve_mask_we = addr_hit[158] & reg_we & !reg_error; - assign doorbell_c15_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c15_intr_we = addr_hit[159] & reg_we & !reg_error; - assign completion_interrupt_c15_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c15_preserve_mask_we = addr_hit[159] & reg_we & !reg_error; - assign completion_interrupt_c15_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c16_we = addr_hit[160] & reg_we & !reg_error; - assign reserved_1_c16_wd = reg_wdata[31:0]; - - assign channel_status_c16_channel_free_we = addr_hit[161] & reg_we & !reg_error; - assign channel_status_c16_channel_free_wd = reg_wdata[0]; - - assign channel_status_c16_channel_error_we = addr_hit[161] & reg_we & !reg_error; - assign channel_status_c16_channel_error_wd = reg_wdata[1]; - - assign channel_status_c16_field1_we = addr_hit[161] & reg_we & !reg_error; - assign channel_status_c16_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c16_we = addr_hit[162] & reg_we & !reg_error; - assign reserved_2_c16_wd = reg_wdata[31:0]; - - assign channel_flags_c16_intr_enable_we = addr_hit[164] & reg_we & !reg_error; - assign channel_flags_c16_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c16_field1_we = addr_hit[164] & reg_we & !reg_error; - assign channel_flags_c16_field1_wd = reg_wdata[31:1]; - - assign length_c16_we = addr_hit[165] & reg_we & !reg_error; - assign length_c16_wd = reg_wdata[31:0]; - - assign message_header_c16_message_id_we = addr_hit[166] & reg_we & !reg_error; - assign message_header_c16_message_id_wd = reg_wdata[7:0]; - - assign message_header_c16_message_type_we = addr_hit[166] & reg_we & !reg_error; - assign message_header_c16_message_type_wd = reg_wdata[9:8]; - - assign message_header_c16_protocol_id_we = addr_hit[166] & reg_we & !reg_error; - assign message_header_c16_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c16_token_we = addr_hit[166] & reg_we & !reg_error; - assign message_header_c16_token_wd = reg_wdata[27:18]; - - assign message_header_c16_field1_we = addr_hit[166] & reg_we & !reg_error; - assign message_header_c16_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c16_we = addr_hit[167] & reg_we & !reg_error; - assign message_payload_1_c16_wd = reg_wdata[31:0]; - - assign doorbell_c16_intr_we = addr_hit[168] & reg_we & !reg_error; - assign doorbell_c16_intr_wd = reg_wdata[0]; - - assign doorbell_c16_preserve_mask_we = addr_hit[168] & reg_we & !reg_error; - assign doorbell_c16_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c16_intr_we = addr_hit[169] & reg_we & !reg_error; - assign completion_interrupt_c16_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c16_preserve_mask_we = addr_hit[169] & reg_we & !reg_error; - assign completion_interrupt_c16_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c17_we = addr_hit[170] & reg_we & !reg_error; - assign reserved_1_c17_wd = reg_wdata[31:0]; - - assign channel_status_c17_channel_free_we = addr_hit[171] & reg_we & !reg_error; - assign channel_status_c17_channel_free_wd = reg_wdata[0]; - - assign channel_status_c17_channel_error_we = addr_hit[171] & reg_we & !reg_error; - assign channel_status_c17_channel_error_wd = reg_wdata[1]; - - assign channel_status_c17_field1_we = addr_hit[171] & reg_we & !reg_error; - assign channel_status_c17_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c17_we = addr_hit[172] & reg_we & !reg_error; - assign reserved_2_c17_wd = reg_wdata[31:0]; - - assign channel_flags_c17_intr_enable_we = addr_hit[174] & reg_we & !reg_error; - assign channel_flags_c17_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c17_field1_we = addr_hit[174] & reg_we & !reg_error; - assign channel_flags_c17_field1_wd = reg_wdata[31:1]; - - assign length_c17_we = addr_hit[175] & reg_we & !reg_error; - assign length_c17_wd = reg_wdata[31:0]; - - assign message_header_c17_message_id_we = addr_hit[176] & reg_we & !reg_error; - assign message_header_c17_message_id_wd = reg_wdata[7:0]; - - assign message_header_c17_message_type_we = addr_hit[176] & reg_we & !reg_error; - assign message_header_c17_message_type_wd = reg_wdata[9:8]; - - assign message_header_c17_protocol_id_we = addr_hit[176] & reg_we & !reg_error; - assign message_header_c17_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c17_token_we = addr_hit[176] & reg_we & !reg_error; - assign message_header_c17_token_wd = reg_wdata[27:18]; - - assign message_header_c17_field1_we = addr_hit[176] & reg_we & !reg_error; - assign message_header_c17_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c17_we = addr_hit[177] & reg_we & !reg_error; - assign message_payload_1_c17_wd = reg_wdata[31:0]; - - assign doorbell_c17_intr_we = addr_hit[178] & reg_we & !reg_error; - assign doorbell_c17_intr_wd = reg_wdata[0]; - - assign doorbell_c17_preserve_mask_we = addr_hit[178] & reg_we & !reg_error; - assign doorbell_c17_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c17_intr_we = addr_hit[179] & reg_we & !reg_error; - assign completion_interrupt_c17_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c17_preserve_mask_we = addr_hit[179] & reg_we & !reg_error; - assign completion_interrupt_c17_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c18_we = addr_hit[180] & reg_we & !reg_error; - assign reserved_1_c18_wd = reg_wdata[31:0]; - - assign channel_status_c18_channel_free_we = addr_hit[181] & reg_we & !reg_error; - assign channel_status_c18_channel_free_wd = reg_wdata[0]; - - assign channel_status_c18_channel_error_we = addr_hit[181] & reg_we & !reg_error; - assign channel_status_c18_channel_error_wd = reg_wdata[1]; - - assign channel_status_c18_field1_we = addr_hit[181] & reg_we & !reg_error; - assign channel_status_c18_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c18_we = addr_hit[182] & reg_we & !reg_error; - assign reserved_2_c18_wd = reg_wdata[31:0]; - - assign channel_flags_c18_intr_enable_we = addr_hit[184] & reg_we & !reg_error; - assign channel_flags_c18_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c18_field1_we = addr_hit[184] & reg_we & !reg_error; - assign channel_flags_c18_field1_wd = reg_wdata[31:1]; - - assign length_c18_we = addr_hit[185] & reg_we & !reg_error; - assign length_c18_wd = reg_wdata[31:0]; - - assign message_header_c18_message_id_we = addr_hit[186] & reg_we & !reg_error; - assign message_header_c18_message_id_wd = reg_wdata[7:0]; - - assign message_header_c18_message_type_we = addr_hit[186] & reg_we & !reg_error; - assign message_header_c18_message_type_wd = reg_wdata[9:8]; - - assign message_header_c18_protocol_id_we = addr_hit[186] & reg_we & !reg_error; - assign message_header_c18_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c18_token_we = addr_hit[186] & reg_we & !reg_error; - assign message_header_c18_token_wd = reg_wdata[27:18]; - - assign message_header_c18_field1_we = addr_hit[186] & reg_we & !reg_error; - assign message_header_c18_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c18_we = addr_hit[187] & reg_we & !reg_error; - assign message_payload_1_c18_wd = reg_wdata[31:0]; - - assign doorbell_c18_intr_we = addr_hit[188] & reg_we & !reg_error; - assign doorbell_c18_intr_wd = reg_wdata[0]; - - assign doorbell_c18_preserve_mask_we = addr_hit[188] & reg_we & !reg_error; - assign doorbell_c18_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c18_intr_we = addr_hit[189] & reg_we & !reg_error; - assign completion_interrupt_c18_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c18_preserve_mask_we = addr_hit[189] & reg_we & !reg_error; - assign completion_interrupt_c18_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c19_we = addr_hit[190] & reg_we & !reg_error; - assign reserved_1_c19_wd = reg_wdata[31:0]; - - assign channel_status_c19_channel_free_we = addr_hit[191] & reg_we & !reg_error; - assign channel_status_c19_channel_free_wd = reg_wdata[0]; - - assign channel_status_c19_channel_error_we = addr_hit[191] & reg_we & !reg_error; - assign channel_status_c19_channel_error_wd = reg_wdata[1]; - - assign channel_status_c19_field1_we = addr_hit[191] & reg_we & !reg_error; - assign channel_status_c19_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c19_we = addr_hit[192] & reg_we & !reg_error; - assign reserved_2_c19_wd = reg_wdata[31:0]; - - assign channel_flags_c19_intr_enable_we = addr_hit[194] & reg_we & !reg_error; - assign channel_flags_c19_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c19_field1_we = addr_hit[194] & reg_we & !reg_error; - assign channel_flags_c19_field1_wd = reg_wdata[31:1]; - - assign length_c19_we = addr_hit[195] & reg_we & !reg_error; - assign length_c19_wd = reg_wdata[31:0]; - - assign message_header_c19_message_id_we = addr_hit[196] & reg_we & !reg_error; - assign message_header_c19_message_id_wd = reg_wdata[7:0]; - - assign message_header_c19_message_type_we = addr_hit[196] & reg_we & !reg_error; - assign message_header_c19_message_type_wd = reg_wdata[9:8]; - - assign message_header_c19_protocol_id_we = addr_hit[196] & reg_we & !reg_error; - assign message_header_c19_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c19_token_we = addr_hit[196] & reg_we & !reg_error; - assign message_header_c19_token_wd = reg_wdata[27:18]; - - assign message_header_c19_field1_we = addr_hit[196] & reg_we & !reg_error; - assign message_header_c19_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c19_we = addr_hit[197] & reg_we & !reg_error; - assign message_payload_1_c19_wd = reg_wdata[31:0]; - - assign doorbell_c19_intr_we = addr_hit[198] & reg_we & !reg_error; - assign doorbell_c19_intr_wd = reg_wdata[0]; - - assign doorbell_c19_preserve_mask_we = addr_hit[198] & reg_we & !reg_error; - assign doorbell_c19_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c19_intr_we = addr_hit[199] & reg_we & !reg_error; - assign completion_interrupt_c19_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c19_preserve_mask_we = addr_hit[199] & reg_we & !reg_error; - assign completion_interrupt_c19_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c20_we = addr_hit[200] & reg_we & !reg_error; - assign reserved_1_c20_wd = reg_wdata[31:0]; - - assign channel_status_c20_channel_free_we = addr_hit[201] & reg_we & !reg_error; - assign channel_status_c20_channel_free_wd = reg_wdata[0]; - - assign channel_status_c20_channel_error_we = addr_hit[201] & reg_we & !reg_error; - assign channel_status_c20_channel_error_wd = reg_wdata[1]; - - assign channel_status_c20_field1_we = addr_hit[201] & reg_we & !reg_error; - assign channel_status_c20_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c20_we = addr_hit[202] & reg_we & !reg_error; - assign reserved_2_c20_wd = reg_wdata[31:0]; - - assign channel_flags_c20_intr_enable_we = addr_hit[204] & reg_we & !reg_error; - assign channel_flags_c20_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c20_field1_we = addr_hit[204] & reg_we & !reg_error; - assign channel_flags_c20_field1_wd = reg_wdata[31:1]; - - assign length_c20_we = addr_hit[205] & reg_we & !reg_error; - assign length_c20_wd = reg_wdata[31:0]; - - assign message_header_c20_message_id_we = addr_hit[206] & reg_we & !reg_error; - assign message_header_c20_message_id_wd = reg_wdata[7:0]; - - assign message_header_c20_message_type_we = addr_hit[206] & reg_we & !reg_error; - assign message_header_c20_message_type_wd = reg_wdata[9:8]; - - assign message_header_c20_protocol_id_we = addr_hit[206] & reg_we & !reg_error; - assign message_header_c20_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c20_token_we = addr_hit[206] & reg_we & !reg_error; - assign message_header_c20_token_wd = reg_wdata[27:18]; - - assign message_header_c20_field1_we = addr_hit[206] & reg_we & !reg_error; - assign message_header_c20_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c20_we = addr_hit[207] & reg_we & !reg_error; - assign message_payload_1_c20_wd = reg_wdata[31:0]; - - assign doorbell_c20_intr_we = addr_hit[208] & reg_we & !reg_error; - assign doorbell_c20_intr_wd = reg_wdata[0]; - - assign doorbell_c20_preserve_mask_we = addr_hit[208] & reg_we & !reg_error; - assign doorbell_c20_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c20_intr_we = addr_hit[209] & reg_we & !reg_error; - assign completion_interrupt_c20_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c20_preserve_mask_we = addr_hit[209] & reg_we & !reg_error; - assign completion_interrupt_c20_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c21_we = addr_hit[210] & reg_we & !reg_error; - assign reserved_1_c21_wd = reg_wdata[31:0]; - - assign channel_status_c21_channel_free_we = addr_hit[211] & reg_we & !reg_error; - assign channel_status_c21_channel_free_wd = reg_wdata[0]; - - assign channel_status_c21_channel_error_we = addr_hit[211] & reg_we & !reg_error; - assign channel_status_c21_channel_error_wd = reg_wdata[1]; - - assign channel_status_c21_field1_we = addr_hit[211] & reg_we & !reg_error; - assign channel_status_c21_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c21_we = addr_hit[212] & reg_we & !reg_error; - assign reserved_2_c21_wd = reg_wdata[31:0]; - - assign channel_flags_c21_intr_enable_we = addr_hit[214] & reg_we & !reg_error; - assign channel_flags_c21_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c21_field1_we = addr_hit[214] & reg_we & !reg_error; - assign channel_flags_c21_field1_wd = reg_wdata[31:1]; - - assign length_c21_we = addr_hit[215] & reg_we & !reg_error; - assign length_c21_wd = reg_wdata[31:0]; - - assign message_header_c21_message_id_we = addr_hit[216] & reg_we & !reg_error; - assign message_header_c21_message_id_wd = reg_wdata[7:0]; - - assign message_header_c21_message_type_we = addr_hit[216] & reg_we & !reg_error; - assign message_header_c21_message_type_wd = reg_wdata[9:8]; - - assign message_header_c21_protocol_id_we = addr_hit[216] & reg_we & !reg_error; - assign message_header_c21_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c21_token_we = addr_hit[216] & reg_we & !reg_error; - assign message_header_c21_token_wd = reg_wdata[27:18]; - - assign message_header_c21_field1_we = addr_hit[216] & reg_we & !reg_error; - assign message_header_c21_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c21_we = addr_hit[217] & reg_we & !reg_error; - assign message_payload_1_c21_wd = reg_wdata[31:0]; - - assign doorbell_c21_intr_we = addr_hit[218] & reg_we & !reg_error; - assign doorbell_c21_intr_wd = reg_wdata[0]; - - assign doorbell_c21_preserve_mask_we = addr_hit[218] & reg_we & !reg_error; - assign doorbell_c21_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c21_intr_we = addr_hit[219] & reg_we & !reg_error; - assign completion_interrupt_c21_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c21_preserve_mask_we = addr_hit[219] & reg_we & !reg_error; - assign completion_interrupt_c21_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c22_we = addr_hit[220] & reg_we & !reg_error; - assign reserved_1_c22_wd = reg_wdata[31:0]; - - assign channel_status_c22_channel_free_we = addr_hit[221] & reg_we & !reg_error; - assign channel_status_c22_channel_free_wd = reg_wdata[0]; - - assign channel_status_c22_channel_error_we = addr_hit[221] & reg_we & !reg_error; - assign channel_status_c22_channel_error_wd = reg_wdata[1]; - - assign channel_status_c22_field1_we = addr_hit[221] & reg_we & !reg_error; - assign channel_status_c22_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c22_we = addr_hit[222] & reg_we & !reg_error; - assign reserved_2_c22_wd = reg_wdata[31:0]; - - assign channel_flags_c22_intr_enable_we = addr_hit[224] & reg_we & !reg_error; - assign channel_flags_c22_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c22_field1_we = addr_hit[224] & reg_we & !reg_error; - assign channel_flags_c22_field1_wd = reg_wdata[31:1]; - - assign length_c22_we = addr_hit[225] & reg_we & !reg_error; - assign length_c22_wd = reg_wdata[31:0]; - - assign message_header_c22_message_id_we = addr_hit[226] & reg_we & !reg_error; - assign message_header_c22_message_id_wd = reg_wdata[7:0]; - - assign message_header_c22_message_type_we = addr_hit[226] & reg_we & !reg_error; - assign message_header_c22_message_type_wd = reg_wdata[9:8]; - - assign message_header_c22_protocol_id_we = addr_hit[226] & reg_we & !reg_error; - assign message_header_c22_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c22_token_we = addr_hit[226] & reg_we & !reg_error; - assign message_header_c22_token_wd = reg_wdata[27:18]; - - assign message_header_c22_field1_we = addr_hit[226] & reg_we & !reg_error; - assign message_header_c22_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c22_we = addr_hit[227] & reg_we & !reg_error; - assign message_payload_1_c22_wd = reg_wdata[31:0]; - - assign doorbell_c22_intr_we = addr_hit[228] & reg_we & !reg_error; - assign doorbell_c22_intr_wd = reg_wdata[0]; - - assign doorbell_c22_preserve_mask_we = addr_hit[228] & reg_we & !reg_error; - assign doorbell_c22_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c22_intr_we = addr_hit[229] & reg_we & !reg_error; - assign completion_interrupt_c22_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c22_preserve_mask_we = addr_hit[229] & reg_we & !reg_error; - assign completion_interrupt_c22_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c23_we = addr_hit[230] & reg_we & !reg_error; - assign reserved_1_c23_wd = reg_wdata[31:0]; - - assign channel_status_c23_channel_free_we = addr_hit[231] & reg_we & !reg_error; - assign channel_status_c23_channel_free_wd = reg_wdata[0]; - - assign channel_status_c23_channel_error_we = addr_hit[231] & reg_we & !reg_error; - assign channel_status_c23_channel_error_wd = reg_wdata[1]; - - assign channel_status_c23_field1_we = addr_hit[231] & reg_we & !reg_error; - assign channel_status_c23_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c23_we = addr_hit[232] & reg_we & !reg_error; - assign reserved_2_c23_wd = reg_wdata[31:0]; - - assign channel_flags_c23_intr_enable_we = addr_hit[234] & reg_we & !reg_error; - assign channel_flags_c23_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c23_field1_we = addr_hit[234] & reg_we & !reg_error; - assign channel_flags_c23_field1_wd = reg_wdata[31:1]; - - assign length_c23_we = addr_hit[235] & reg_we & !reg_error; - assign length_c23_wd = reg_wdata[31:0]; - - assign message_header_c23_message_id_we = addr_hit[236] & reg_we & !reg_error; - assign message_header_c23_message_id_wd = reg_wdata[7:0]; - - assign message_header_c23_message_type_we = addr_hit[236] & reg_we & !reg_error; - assign message_header_c23_message_type_wd = reg_wdata[9:8]; - - assign message_header_c23_protocol_id_we = addr_hit[236] & reg_we & !reg_error; - assign message_header_c23_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c23_token_we = addr_hit[236] & reg_we & !reg_error; - assign message_header_c23_token_wd = reg_wdata[27:18]; - - assign message_header_c23_field1_we = addr_hit[236] & reg_we & !reg_error; - assign message_header_c23_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c23_we = addr_hit[237] & reg_we & !reg_error; - assign message_payload_1_c23_wd = reg_wdata[31:0]; - - assign doorbell_c23_intr_we = addr_hit[238] & reg_we & !reg_error; - assign doorbell_c23_intr_wd = reg_wdata[0]; - - assign doorbell_c23_preserve_mask_we = addr_hit[238] & reg_we & !reg_error; - assign doorbell_c23_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c23_intr_we = addr_hit[239] & reg_we & !reg_error; - assign completion_interrupt_c23_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c23_preserve_mask_we = addr_hit[239] & reg_we & !reg_error; - assign completion_interrupt_c23_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c24_we = addr_hit[240] & reg_we & !reg_error; - assign reserved_1_c24_wd = reg_wdata[31:0]; - - assign channel_status_c24_channel_free_we = addr_hit[241] & reg_we & !reg_error; - assign channel_status_c24_channel_free_wd = reg_wdata[0]; - - assign channel_status_c24_channel_error_we = addr_hit[241] & reg_we & !reg_error; - assign channel_status_c24_channel_error_wd = reg_wdata[1]; - - assign channel_status_c24_field1_we = addr_hit[241] & reg_we & !reg_error; - assign channel_status_c24_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c24_we = addr_hit[242] & reg_we & !reg_error; - assign reserved_2_c24_wd = reg_wdata[31:0]; - - assign channel_flags_c24_intr_enable_we = addr_hit[244] & reg_we & !reg_error; - assign channel_flags_c24_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c24_field1_we = addr_hit[244] & reg_we & !reg_error; - assign channel_flags_c24_field1_wd = reg_wdata[31:1]; - - assign length_c24_we = addr_hit[245] & reg_we & !reg_error; - assign length_c24_wd = reg_wdata[31:0]; - - assign message_header_c24_message_id_we = addr_hit[246] & reg_we & !reg_error; - assign message_header_c24_message_id_wd = reg_wdata[7:0]; - - assign message_header_c24_message_type_we = addr_hit[246] & reg_we & !reg_error; - assign message_header_c24_message_type_wd = reg_wdata[9:8]; - - assign message_header_c24_protocol_id_we = addr_hit[246] & reg_we & !reg_error; - assign message_header_c24_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c24_token_we = addr_hit[246] & reg_we & !reg_error; - assign message_header_c24_token_wd = reg_wdata[27:18]; - - assign message_header_c24_field1_we = addr_hit[246] & reg_we & !reg_error; - assign message_header_c24_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c24_we = addr_hit[247] & reg_we & !reg_error; - assign message_payload_1_c24_wd = reg_wdata[31:0]; - - assign doorbell_c24_intr_we = addr_hit[248] & reg_we & !reg_error; - assign doorbell_c24_intr_wd = reg_wdata[0]; - - assign doorbell_c24_preserve_mask_we = addr_hit[248] & reg_we & !reg_error; - assign doorbell_c24_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c24_intr_we = addr_hit[249] & reg_we & !reg_error; - assign completion_interrupt_c24_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c24_preserve_mask_we = addr_hit[249] & reg_we & !reg_error; - assign completion_interrupt_c24_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c25_we = addr_hit[250] & reg_we & !reg_error; - assign reserved_1_c25_wd = reg_wdata[31:0]; - - assign channel_status_c25_channel_free_we = addr_hit[251] & reg_we & !reg_error; - assign channel_status_c25_channel_free_wd = reg_wdata[0]; - - assign channel_status_c25_channel_error_we = addr_hit[251] & reg_we & !reg_error; - assign channel_status_c25_channel_error_wd = reg_wdata[1]; - - assign channel_status_c25_field1_we = addr_hit[251] & reg_we & !reg_error; - assign channel_status_c25_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c25_we = addr_hit[252] & reg_we & !reg_error; - assign reserved_2_c25_wd = reg_wdata[31:0]; - - assign channel_flags_c25_intr_enable_we = addr_hit[254] & reg_we & !reg_error; - assign channel_flags_c25_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c25_field1_we = addr_hit[254] & reg_we & !reg_error; - assign channel_flags_c25_field1_wd = reg_wdata[31:1]; - - assign length_c25_we = addr_hit[255] & reg_we & !reg_error; - assign length_c25_wd = reg_wdata[31:0]; - - assign message_header_c25_message_id_we = addr_hit[256] & reg_we & !reg_error; - assign message_header_c25_message_id_wd = reg_wdata[7:0]; - - assign message_header_c25_message_type_we = addr_hit[256] & reg_we & !reg_error; - assign message_header_c25_message_type_wd = reg_wdata[9:8]; - - assign message_header_c25_protocol_id_we = addr_hit[256] & reg_we & !reg_error; - assign message_header_c25_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c25_token_we = addr_hit[256] & reg_we & !reg_error; - assign message_header_c25_token_wd = reg_wdata[27:18]; - - assign message_header_c25_field1_we = addr_hit[256] & reg_we & !reg_error; - assign message_header_c25_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c25_we = addr_hit[257] & reg_we & !reg_error; - assign message_payload_1_c25_wd = reg_wdata[31:0]; - - assign doorbell_c25_intr_we = addr_hit[258] & reg_we & !reg_error; - assign doorbell_c25_intr_wd = reg_wdata[0]; - - assign doorbell_c25_preserve_mask_we = addr_hit[258] & reg_we & !reg_error; - assign doorbell_c25_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c25_intr_we = addr_hit[259] & reg_we & !reg_error; - assign completion_interrupt_c25_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c25_preserve_mask_we = addr_hit[259] & reg_we & !reg_error; - assign completion_interrupt_c25_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c26_we = addr_hit[260] & reg_we & !reg_error; - assign reserved_1_c26_wd = reg_wdata[31:0]; - - assign channel_status_c26_channel_free_we = addr_hit[261] & reg_we & !reg_error; - assign channel_status_c26_channel_free_wd = reg_wdata[0]; - - assign channel_status_c26_channel_error_we = addr_hit[261] & reg_we & !reg_error; - assign channel_status_c26_channel_error_wd = reg_wdata[1]; - - assign channel_status_c26_field1_we = addr_hit[261] & reg_we & !reg_error; - assign channel_status_c26_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c26_we = addr_hit[262] & reg_we & !reg_error; - assign reserved_2_c26_wd = reg_wdata[31:0]; - - assign channel_flags_c26_intr_enable_we = addr_hit[264] & reg_we & !reg_error; - assign channel_flags_c26_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c26_field1_we = addr_hit[264] & reg_we & !reg_error; - assign channel_flags_c26_field1_wd = reg_wdata[31:1]; - - assign length_c26_we = addr_hit[265] & reg_we & !reg_error; - assign length_c26_wd = reg_wdata[31:0]; - - assign message_header_c26_message_id_we = addr_hit[266] & reg_we & !reg_error; - assign message_header_c26_message_id_wd = reg_wdata[7:0]; - - assign message_header_c26_message_type_we = addr_hit[266] & reg_we & !reg_error; - assign message_header_c26_message_type_wd = reg_wdata[9:8]; - - assign message_header_c26_protocol_id_we = addr_hit[266] & reg_we & !reg_error; - assign message_header_c26_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c26_token_we = addr_hit[266] & reg_we & !reg_error; - assign message_header_c26_token_wd = reg_wdata[27:18]; - - assign message_header_c26_field1_we = addr_hit[266] & reg_we & !reg_error; - assign message_header_c26_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c26_we = addr_hit[267] & reg_we & !reg_error; - assign message_payload_1_c26_wd = reg_wdata[31:0]; - - assign doorbell_c26_intr_we = addr_hit[268] & reg_we & !reg_error; - assign doorbell_c26_intr_wd = reg_wdata[0]; - - assign doorbell_c26_preserve_mask_we = addr_hit[268] & reg_we & !reg_error; - assign doorbell_c26_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c26_intr_we = addr_hit[269] & reg_we & !reg_error; - assign completion_interrupt_c26_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c26_preserve_mask_we = addr_hit[269] & reg_we & !reg_error; - assign completion_interrupt_c26_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c27_we = addr_hit[270] & reg_we & !reg_error; - assign reserved_1_c27_wd = reg_wdata[31:0]; - - assign channel_status_c27_channel_free_we = addr_hit[271] & reg_we & !reg_error; - assign channel_status_c27_channel_free_wd = reg_wdata[0]; - - assign channel_status_c27_channel_error_we = addr_hit[271] & reg_we & !reg_error; - assign channel_status_c27_channel_error_wd = reg_wdata[1]; - - assign channel_status_c27_field1_we = addr_hit[271] & reg_we & !reg_error; - assign channel_status_c27_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c27_we = addr_hit[272] & reg_we & !reg_error; - assign reserved_2_c27_wd = reg_wdata[31:0]; - - assign channel_flags_c27_intr_enable_we = addr_hit[274] & reg_we & !reg_error; - assign channel_flags_c27_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c27_field1_we = addr_hit[274] & reg_we & !reg_error; - assign channel_flags_c27_field1_wd = reg_wdata[31:1]; - - assign length_c27_we = addr_hit[275] & reg_we & !reg_error; - assign length_c27_wd = reg_wdata[31:0]; - - assign message_header_c27_message_id_we = addr_hit[276] & reg_we & !reg_error; - assign message_header_c27_message_id_wd = reg_wdata[7:0]; - - assign message_header_c27_message_type_we = addr_hit[276] & reg_we & !reg_error; - assign message_header_c27_message_type_wd = reg_wdata[9:8]; - - assign message_header_c27_protocol_id_we = addr_hit[276] & reg_we & !reg_error; - assign message_header_c27_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c27_token_we = addr_hit[276] & reg_we & !reg_error; - assign message_header_c27_token_wd = reg_wdata[27:18]; - - assign message_header_c27_field1_we = addr_hit[276] & reg_we & !reg_error; - assign message_header_c27_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c27_we = addr_hit[277] & reg_we & !reg_error; - assign message_payload_1_c27_wd = reg_wdata[31:0]; - - assign doorbell_c27_intr_we = addr_hit[278] & reg_we & !reg_error; - assign doorbell_c27_intr_wd = reg_wdata[0]; - - assign doorbell_c27_preserve_mask_we = addr_hit[278] & reg_we & !reg_error; - assign doorbell_c27_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c27_intr_we = addr_hit[279] & reg_we & !reg_error; - assign completion_interrupt_c27_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c27_preserve_mask_we = addr_hit[279] & reg_we & !reg_error; - assign completion_interrupt_c27_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c28_we = addr_hit[280] & reg_we & !reg_error; - assign reserved_1_c28_wd = reg_wdata[31:0]; - - assign channel_status_c28_channel_free_we = addr_hit[281] & reg_we & !reg_error; - assign channel_status_c28_channel_free_wd = reg_wdata[0]; - - assign channel_status_c28_channel_error_we = addr_hit[281] & reg_we & !reg_error; - assign channel_status_c28_channel_error_wd = reg_wdata[1]; - - assign channel_status_c28_field1_we = addr_hit[281] & reg_we & !reg_error; - assign channel_status_c28_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c28_we = addr_hit[282] & reg_we & !reg_error; - assign reserved_2_c28_wd = reg_wdata[31:0]; - - assign channel_flags_c28_intr_enable_we = addr_hit[284] & reg_we & !reg_error; - assign channel_flags_c28_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c28_field1_we = addr_hit[284] & reg_we & !reg_error; - assign channel_flags_c28_field1_wd = reg_wdata[31:1]; - - assign length_c28_we = addr_hit[285] & reg_we & !reg_error; - assign length_c28_wd = reg_wdata[31:0]; - - assign message_header_c28_message_id_we = addr_hit[286] & reg_we & !reg_error; - assign message_header_c28_message_id_wd = reg_wdata[7:0]; - - assign message_header_c28_message_type_we = addr_hit[286] & reg_we & !reg_error; - assign message_header_c28_message_type_wd = reg_wdata[9:8]; - - assign message_header_c28_protocol_id_we = addr_hit[286] & reg_we & !reg_error; - assign message_header_c28_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c28_token_we = addr_hit[286] & reg_we & !reg_error; - assign message_header_c28_token_wd = reg_wdata[27:18]; - - assign message_header_c28_field1_we = addr_hit[286] & reg_we & !reg_error; - assign message_header_c28_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c28_we = addr_hit[287] & reg_we & !reg_error; - assign message_payload_1_c28_wd = reg_wdata[31:0]; - - assign doorbell_c28_intr_we = addr_hit[288] & reg_we & !reg_error; - assign doorbell_c28_intr_wd = reg_wdata[0]; - - assign doorbell_c28_preserve_mask_we = addr_hit[288] & reg_we & !reg_error; - assign doorbell_c28_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c28_intr_we = addr_hit[289] & reg_we & !reg_error; - assign completion_interrupt_c28_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c28_preserve_mask_we = addr_hit[289] & reg_we & !reg_error; - assign completion_interrupt_c28_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c29_we = addr_hit[290] & reg_we & !reg_error; - assign reserved_1_c29_wd = reg_wdata[31:0]; - - assign channel_status_c29_channel_free_we = addr_hit[291] & reg_we & !reg_error; - assign channel_status_c29_channel_free_wd = reg_wdata[0]; - - assign channel_status_c29_channel_error_we = addr_hit[291] & reg_we & !reg_error; - assign channel_status_c29_channel_error_wd = reg_wdata[1]; - - assign channel_status_c29_field1_we = addr_hit[291] & reg_we & !reg_error; - assign channel_status_c29_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c29_we = addr_hit[292] & reg_we & !reg_error; - assign reserved_2_c29_wd = reg_wdata[31:0]; - - assign channel_flags_c29_intr_enable_we = addr_hit[294] & reg_we & !reg_error; - assign channel_flags_c29_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c29_field1_we = addr_hit[294] & reg_we & !reg_error; - assign channel_flags_c29_field1_wd = reg_wdata[31:1]; - - assign length_c29_we = addr_hit[295] & reg_we & !reg_error; - assign length_c29_wd = reg_wdata[31:0]; - - assign message_header_c29_message_id_we = addr_hit[296] & reg_we & !reg_error; - assign message_header_c29_message_id_wd = reg_wdata[7:0]; - - assign message_header_c29_message_type_we = addr_hit[296] & reg_we & !reg_error; - assign message_header_c29_message_type_wd = reg_wdata[9:8]; - - assign message_header_c29_protocol_id_we = addr_hit[296] & reg_we & !reg_error; - assign message_header_c29_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c29_token_we = addr_hit[296] & reg_we & !reg_error; - assign message_header_c29_token_wd = reg_wdata[27:18]; - - assign message_header_c29_field1_we = addr_hit[296] & reg_we & !reg_error; - assign message_header_c29_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c29_we = addr_hit[297] & reg_we & !reg_error; - assign message_payload_1_c29_wd = reg_wdata[31:0]; - - assign doorbell_c29_intr_we = addr_hit[298] & reg_we & !reg_error; - assign doorbell_c29_intr_wd = reg_wdata[0]; - - assign doorbell_c29_preserve_mask_we = addr_hit[298] & reg_we & !reg_error; - assign doorbell_c29_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c29_intr_we = addr_hit[299] & reg_we & !reg_error; - assign completion_interrupt_c29_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c29_preserve_mask_we = addr_hit[299] & reg_we & !reg_error; - assign completion_interrupt_c29_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c30_we = addr_hit[300] & reg_we & !reg_error; - assign reserved_1_c30_wd = reg_wdata[31:0]; - - assign channel_status_c30_channel_free_we = addr_hit[301] & reg_we & !reg_error; - assign channel_status_c30_channel_free_wd = reg_wdata[0]; - - assign channel_status_c30_channel_error_we = addr_hit[301] & reg_we & !reg_error; - assign channel_status_c30_channel_error_wd = reg_wdata[1]; - - assign channel_status_c30_field1_we = addr_hit[301] & reg_we & !reg_error; - assign channel_status_c30_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c30_we = addr_hit[302] & reg_we & !reg_error; - assign reserved_2_c30_wd = reg_wdata[31:0]; - - assign channel_flags_c30_intr_enable_we = addr_hit[304] & reg_we & !reg_error; - assign channel_flags_c30_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c30_field1_we = addr_hit[304] & reg_we & !reg_error; - assign channel_flags_c30_field1_wd = reg_wdata[31:1]; - - assign length_c30_we = addr_hit[305] & reg_we & !reg_error; - assign length_c30_wd = reg_wdata[31:0]; - - assign message_header_c30_message_id_we = addr_hit[306] & reg_we & !reg_error; - assign message_header_c30_message_id_wd = reg_wdata[7:0]; - - assign message_header_c30_message_type_we = addr_hit[306] & reg_we & !reg_error; - assign message_header_c30_message_type_wd = reg_wdata[9:8]; - - assign message_header_c30_protocol_id_we = addr_hit[306] & reg_we & !reg_error; - assign message_header_c30_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c30_token_we = addr_hit[306] & reg_we & !reg_error; - assign message_header_c30_token_wd = reg_wdata[27:18]; - - assign message_header_c30_field1_we = addr_hit[306] & reg_we & !reg_error; - assign message_header_c30_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c30_we = addr_hit[307] & reg_we & !reg_error; - assign message_payload_1_c30_wd = reg_wdata[31:0]; - - assign doorbell_c30_intr_we = addr_hit[308] & reg_we & !reg_error; - assign doorbell_c30_intr_wd = reg_wdata[0]; - - assign doorbell_c30_preserve_mask_we = addr_hit[308] & reg_we & !reg_error; - assign doorbell_c30_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c30_intr_we = addr_hit[309] & reg_we & !reg_error; - assign completion_interrupt_c30_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c30_preserve_mask_we = addr_hit[309] & reg_we & !reg_error; - assign completion_interrupt_c30_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c31_we = addr_hit[310] & reg_we & !reg_error; - assign reserved_1_c31_wd = reg_wdata[31:0]; - - assign channel_status_c31_channel_free_we = addr_hit[311] & reg_we & !reg_error; - assign channel_status_c31_channel_free_wd = reg_wdata[0]; - - assign channel_status_c31_channel_error_we = addr_hit[311] & reg_we & !reg_error; - assign channel_status_c31_channel_error_wd = reg_wdata[1]; - - assign channel_status_c31_field1_we = addr_hit[311] & reg_we & !reg_error; - assign channel_status_c31_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c31_we = addr_hit[312] & reg_we & !reg_error; - assign reserved_2_c31_wd = reg_wdata[31:0]; - - assign channel_flags_c31_intr_enable_we = addr_hit[314] & reg_we & !reg_error; - assign channel_flags_c31_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c31_field1_we = addr_hit[314] & reg_we & !reg_error; - assign channel_flags_c31_field1_wd = reg_wdata[31:1]; - - assign length_c31_we = addr_hit[315] & reg_we & !reg_error; - assign length_c31_wd = reg_wdata[31:0]; - - assign message_header_c31_message_id_we = addr_hit[316] & reg_we & !reg_error; - assign message_header_c31_message_id_wd = reg_wdata[7:0]; - - assign message_header_c31_message_type_we = addr_hit[316] & reg_we & !reg_error; - assign message_header_c31_message_type_wd = reg_wdata[9:8]; - - assign message_header_c31_protocol_id_we = addr_hit[316] & reg_we & !reg_error; - assign message_header_c31_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c31_token_we = addr_hit[316] & reg_we & !reg_error; - assign message_header_c31_token_wd = reg_wdata[27:18]; - - assign message_header_c31_field1_we = addr_hit[316] & reg_we & !reg_error; - assign message_header_c31_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c31_we = addr_hit[317] & reg_we & !reg_error; - assign message_payload_1_c31_wd = reg_wdata[31:0]; - - assign doorbell_c31_intr_we = addr_hit[318] & reg_we & !reg_error; - assign doorbell_c31_intr_wd = reg_wdata[0]; - - assign doorbell_c31_preserve_mask_we = addr_hit[318] & reg_we & !reg_error; - assign doorbell_c31_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c31_intr_we = addr_hit[319] & reg_we & !reg_error; - assign completion_interrupt_c31_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c31_preserve_mask_we = addr_hit[319] & reg_we & !reg_error; - assign completion_interrupt_c31_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c32_we = addr_hit[320] & reg_we & !reg_error; - assign reserved_1_c32_wd = reg_wdata[31:0]; - - assign channel_status_c32_channel_free_we = addr_hit[321] & reg_we & !reg_error; - assign channel_status_c32_channel_free_wd = reg_wdata[0]; - - assign channel_status_c32_channel_error_we = addr_hit[321] & reg_we & !reg_error; - assign channel_status_c32_channel_error_wd = reg_wdata[1]; - - assign channel_status_c32_field1_we = addr_hit[321] & reg_we & !reg_error; - assign channel_status_c32_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c32_we = addr_hit[322] & reg_we & !reg_error; - assign reserved_2_c32_wd = reg_wdata[31:0]; - - assign channel_flags_c32_intr_enable_we = addr_hit[324] & reg_we & !reg_error; - assign channel_flags_c32_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c32_field1_we = addr_hit[324] & reg_we & !reg_error; - assign channel_flags_c32_field1_wd = reg_wdata[31:1]; - - assign length_c32_we = addr_hit[325] & reg_we & !reg_error; - assign length_c32_wd = reg_wdata[31:0]; - - assign message_header_c32_message_id_we = addr_hit[326] & reg_we & !reg_error; - assign message_header_c32_message_id_wd = reg_wdata[7:0]; - - assign message_header_c32_message_type_we = addr_hit[326] & reg_we & !reg_error; - assign message_header_c32_message_type_wd = reg_wdata[9:8]; - - assign message_header_c32_protocol_id_we = addr_hit[326] & reg_we & !reg_error; - assign message_header_c32_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c32_token_we = addr_hit[326] & reg_we & !reg_error; - assign message_header_c32_token_wd = reg_wdata[27:18]; - - assign message_header_c32_field1_we = addr_hit[326] & reg_we & !reg_error; - assign message_header_c32_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c32_we = addr_hit[327] & reg_we & !reg_error; - assign message_payload_1_c32_wd = reg_wdata[31:0]; - - assign doorbell_c32_intr_we = addr_hit[328] & reg_we & !reg_error; - assign doorbell_c32_intr_wd = reg_wdata[0]; - - assign doorbell_c32_preserve_mask_we = addr_hit[328] & reg_we & !reg_error; - assign doorbell_c32_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c32_intr_we = addr_hit[329] & reg_we & !reg_error; - assign completion_interrupt_c32_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c32_preserve_mask_we = addr_hit[329] & reg_we & !reg_error; - assign completion_interrupt_c32_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c33_we = addr_hit[330] & reg_we & !reg_error; - assign reserved_1_c33_wd = reg_wdata[31:0]; - - assign channel_status_c33_channel_free_we = addr_hit[331] & reg_we & !reg_error; - assign channel_status_c33_channel_free_wd = reg_wdata[0]; - - assign channel_status_c33_channel_error_we = addr_hit[331] & reg_we & !reg_error; - assign channel_status_c33_channel_error_wd = reg_wdata[1]; - - assign channel_status_c33_field1_we = addr_hit[331] & reg_we & !reg_error; - assign channel_status_c33_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c33_we = addr_hit[332] & reg_we & !reg_error; - assign reserved_2_c33_wd = reg_wdata[31:0]; - - assign channel_flags_c33_intr_enable_we = addr_hit[334] & reg_we & !reg_error; - assign channel_flags_c33_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c33_field1_we = addr_hit[334] & reg_we & !reg_error; - assign channel_flags_c33_field1_wd = reg_wdata[31:1]; - - assign length_c33_we = addr_hit[335] & reg_we & !reg_error; - assign length_c33_wd = reg_wdata[31:0]; - - assign message_header_c33_message_id_we = addr_hit[336] & reg_we & !reg_error; - assign message_header_c33_message_id_wd = reg_wdata[7:0]; - - assign message_header_c33_message_type_we = addr_hit[336] & reg_we & !reg_error; - assign message_header_c33_message_type_wd = reg_wdata[9:8]; - - assign message_header_c33_protocol_id_we = addr_hit[336] & reg_we & !reg_error; - assign message_header_c33_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c33_token_we = addr_hit[336] & reg_we & !reg_error; - assign message_header_c33_token_wd = reg_wdata[27:18]; - - assign message_header_c33_field1_we = addr_hit[336] & reg_we & !reg_error; - assign message_header_c33_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c33_we = addr_hit[337] & reg_we & !reg_error; - assign message_payload_1_c33_wd = reg_wdata[31:0]; - - assign doorbell_c33_intr_we = addr_hit[338] & reg_we & !reg_error; - assign doorbell_c33_intr_wd = reg_wdata[0]; - - assign doorbell_c33_preserve_mask_we = addr_hit[338] & reg_we & !reg_error; - assign doorbell_c33_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c33_intr_we = addr_hit[339] & reg_we & !reg_error; - assign completion_interrupt_c33_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c33_preserve_mask_we = addr_hit[339] & reg_we & !reg_error; - assign completion_interrupt_c33_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c34_we = addr_hit[340] & reg_we & !reg_error; - assign reserved_1_c34_wd = reg_wdata[31:0]; - - assign channel_status_c34_channel_free_we = addr_hit[341] & reg_we & !reg_error; - assign channel_status_c34_channel_free_wd = reg_wdata[0]; - - assign channel_status_c34_channel_error_we = addr_hit[341] & reg_we & !reg_error; - assign channel_status_c34_channel_error_wd = reg_wdata[1]; - - assign channel_status_c34_field1_we = addr_hit[341] & reg_we & !reg_error; - assign channel_status_c34_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c34_we = addr_hit[342] & reg_we & !reg_error; - assign reserved_2_c34_wd = reg_wdata[31:0]; - - assign channel_flags_c34_intr_enable_we = addr_hit[344] & reg_we & !reg_error; - assign channel_flags_c34_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c34_field1_we = addr_hit[344] & reg_we & !reg_error; - assign channel_flags_c34_field1_wd = reg_wdata[31:1]; - - assign length_c34_we = addr_hit[345] & reg_we & !reg_error; - assign length_c34_wd = reg_wdata[31:0]; - - assign message_header_c34_message_id_we = addr_hit[346] & reg_we & !reg_error; - assign message_header_c34_message_id_wd = reg_wdata[7:0]; - - assign message_header_c34_message_type_we = addr_hit[346] & reg_we & !reg_error; - assign message_header_c34_message_type_wd = reg_wdata[9:8]; - - assign message_header_c34_protocol_id_we = addr_hit[346] & reg_we & !reg_error; - assign message_header_c34_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c34_token_we = addr_hit[346] & reg_we & !reg_error; - assign message_header_c34_token_wd = reg_wdata[27:18]; - - assign message_header_c34_field1_we = addr_hit[346] & reg_we & !reg_error; - assign message_header_c34_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c34_we = addr_hit[347] & reg_we & !reg_error; - assign message_payload_1_c34_wd = reg_wdata[31:0]; - - assign doorbell_c34_intr_we = addr_hit[348] & reg_we & !reg_error; - assign doorbell_c34_intr_wd = reg_wdata[0]; - - assign doorbell_c34_preserve_mask_we = addr_hit[348] & reg_we & !reg_error; - assign doorbell_c34_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c34_intr_we = addr_hit[349] & reg_we & !reg_error; - assign completion_interrupt_c34_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c34_preserve_mask_we = addr_hit[349] & reg_we & !reg_error; - assign completion_interrupt_c34_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c35_we = addr_hit[350] & reg_we & !reg_error; - assign reserved_1_c35_wd = reg_wdata[31:0]; - - assign channel_status_c35_channel_free_we = addr_hit[351] & reg_we & !reg_error; - assign channel_status_c35_channel_free_wd = reg_wdata[0]; - - assign channel_status_c35_channel_error_we = addr_hit[351] & reg_we & !reg_error; - assign channel_status_c35_channel_error_wd = reg_wdata[1]; - - assign channel_status_c35_field1_we = addr_hit[351] & reg_we & !reg_error; - assign channel_status_c35_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c35_we = addr_hit[352] & reg_we & !reg_error; - assign reserved_2_c35_wd = reg_wdata[31:0]; - - assign channel_flags_c35_intr_enable_we = addr_hit[354] & reg_we & !reg_error; - assign channel_flags_c35_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c35_field1_we = addr_hit[354] & reg_we & !reg_error; - assign channel_flags_c35_field1_wd = reg_wdata[31:1]; - - assign length_c35_we = addr_hit[355] & reg_we & !reg_error; - assign length_c35_wd = reg_wdata[31:0]; - - assign message_header_c35_message_id_we = addr_hit[356] & reg_we & !reg_error; - assign message_header_c35_message_id_wd = reg_wdata[7:0]; - - assign message_header_c35_message_type_we = addr_hit[356] & reg_we & !reg_error; - assign message_header_c35_message_type_wd = reg_wdata[9:8]; - - assign message_header_c35_protocol_id_we = addr_hit[356] & reg_we & !reg_error; - assign message_header_c35_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c35_token_we = addr_hit[356] & reg_we & !reg_error; - assign message_header_c35_token_wd = reg_wdata[27:18]; - - assign message_header_c35_field1_we = addr_hit[356] & reg_we & !reg_error; - assign message_header_c35_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c35_we = addr_hit[357] & reg_we & !reg_error; - assign message_payload_1_c35_wd = reg_wdata[31:0]; - - assign doorbell_c35_intr_we = addr_hit[358] & reg_we & !reg_error; - assign doorbell_c35_intr_wd = reg_wdata[0]; - - assign doorbell_c35_preserve_mask_we = addr_hit[358] & reg_we & !reg_error; - assign doorbell_c35_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c35_intr_we = addr_hit[359] & reg_we & !reg_error; - assign completion_interrupt_c35_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c35_preserve_mask_we = addr_hit[359] & reg_we & !reg_error; - assign completion_interrupt_c35_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c36_we = addr_hit[360] & reg_we & !reg_error; - assign reserved_1_c36_wd = reg_wdata[31:0]; - - assign channel_status_c36_channel_free_we = addr_hit[361] & reg_we & !reg_error; - assign channel_status_c36_channel_free_wd = reg_wdata[0]; - - assign channel_status_c36_channel_error_we = addr_hit[361] & reg_we & !reg_error; - assign channel_status_c36_channel_error_wd = reg_wdata[1]; - - assign channel_status_c36_field1_we = addr_hit[361] & reg_we & !reg_error; - assign channel_status_c36_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c36_we = addr_hit[362] & reg_we & !reg_error; - assign reserved_2_c36_wd = reg_wdata[31:0]; - - assign channel_flags_c36_intr_enable_we = addr_hit[364] & reg_we & !reg_error; - assign channel_flags_c36_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c36_field1_we = addr_hit[364] & reg_we & !reg_error; - assign channel_flags_c36_field1_wd = reg_wdata[31:1]; - - assign length_c36_we = addr_hit[365] & reg_we & !reg_error; - assign length_c36_wd = reg_wdata[31:0]; - - assign message_header_c36_message_id_we = addr_hit[366] & reg_we & !reg_error; - assign message_header_c36_message_id_wd = reg_wdata[7:0]; - - assign message_header_c36_message_type_we = addr_hit[366] & reg_we & !reg_error; - assign message_header_c36_message_type_wd = reg_wdata[9:8]; - - assign message_header_c36_protocol_id_we = addr_hit[366] & reg_we & !reg_error; - assign message_header_c36_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c36_token_we = addr_hit[366] & reg_we & !reg_error; - assign message_header_c36_token_wd = reg_wdata[27:18]; - - assign message_header_c36_field1_we = addr_hit[366] & reg_we & !reg_error; - assign message_header_c36_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c36_we = addr_hit[367] & reg_we & !reg_error; - assign message_payload_1_c36_wd = reg_wdata[31:0]; - - assign doorbell_c36_intr_we = addr_hit[368] & reg_we & !reg_error; - assign doorbell_c36_intr_wd = reg_wdata[0]; - - assign doorbell_c36_preserve_mask_we = addr_hit[368] & reg_we & !reg_error; - assign doorbell_c36_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c36_intr_we = addr_hit[369] & reg_we & !reg_error; - assign completion_interrupt_c36_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c36_preserve_mask_we = addr_hit[369] & reg_we & !reg_error; - assign completion_interrupt_c36_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c37_we = addr_hit[370] & reg_we & !reg_error; - assign reserved_1_c37_wd = reg_wdata[31:0]; - - assign channel_status_c37_channel_free_we = addr_hit[371] & reg_we & !reg_error; - assign channel_status_c37_channel_free_wd = reg_wdata[0]; - - assign channel_status_c37_channel_error_we = addr_hit[371] & reg_we & !reg_error; - assign channel_status_c37_channel_error_wd = reg_wdata[1]; - - assign channel_status_c37_field1_we = addr_hit[371] & reg_we & !reg_error; - assign channel_status_c37_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c37_we = addr_hit[372] & reg_we & !reg_error; - assign reserved_2_c37_wd = reg_wdata[31:0]; - - assign channel_flags_c37_intr_enable_we = addr_hit[374] & reg_we & !reg_error; - assign channel_flags_c37_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c37_field1_we = addr_hit[374] & reg_we & !reg_error; - assign channel_flags_c37_field1_wd = reg_wdata[31:1]; - - assign length_c37_we = addr_hit[375] & reg_we & !reg_error; - assign length_c37_wd = reg_wdata[31:0]; - - assign message_header_c37_message_id_we = addr_hit[376] & reg_we & !reg_error; - assign message_header_c37_message_id_wd = reg_wdata[7:0]; - - assign message_header_c37_message_type_we = addr_hit[376] & reg_we & !reg_error; - assign message_header_c37_message_type_wd = reg_wdata[9:8]; - - assign message_header_c37_protocol_id_we = addr_hit[376] & reg_we & !reg_error; - assign message_header_c37_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c37_token_we = addr_hit[376] & reg_we & !reg_error; - assign message_header_c37_token_wd = reg_wdata[27:18]; - - assign message_header_c37_field1_we = addr_hit[376] & reg_we & !reg_error; - assign message_header_c37_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c37_we = addr_hit[377] & reg_we & !reg_error; - assign message_payload_1_c37_wd = reg_wdata[31:0]; - - assign doorbell_c37_intr_we = addr_hit[378] & reg_we & !reg_error; - assign doorbell_c37_intr_wd = reg_wdata[0]; - - assign doorbell_c37_preserve_mask_we = addr_hit[378] & reg_we & !reg_error; - assign doorbell_c37_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c37_intr_we = addr_hit[379] & reg_we & !reg_error; - assign completion_interrupt_c37_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c37_preserve_mask_we = addr_hit[379] & reg_we & !reg_error; - assign completion_interrupt_c37_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c38_we = addr_hit[380] & reg_we & !reg_error; - assign reserved_1_c38_wd = reg_wdata[31:0]; - - assign channel_status_c38_channel_free_we = addr_hit[381] & reg_we & !reg_error; - assign channel_status_c38_channel_free_wd = reg_wdata[0]; - - assign channel_status_c38_channel_error_we = addr_hit[381] & reg_we & !reg_error; - assign channel_status_c38_channel_error_wd = reg_wdata[1]; - - assign channel_status_c38_field1_we = addr_hit[381] & reg_we & !reg_error; - assign channel_status_c38_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c38_we = addr_hit[382] & reg_we & !reg_error; - assign reserved_2_c38_wd = reg_wdata[31:0]; - - assign channel_flags_c38_intr_enable_we = addr_hit[384] & reg_we & !reg_error; - assign channel_flags_c38_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c38_field1_we = addr_hit[384] & reg_we & !reg_error; - assign channel_flags_c38_field1_wd = reg_wdata[31:1]; - - assign length_c38_we = addr_hit[385] & reg_we & !reg_error; - assign length_c38_wd = reg_wdata[31:0]; - - assign message_header_c38_message_id_we = addr_hit[386] & reg_we & !reg_error; - assign message_header_c38_message_id_wd = reg_wdata[7:0]; - - assign message_header_c38_message_type_we = addr_hit[386] & reg_we & !reg_error; - assign message_header_c38_message_type_wd = reg_wdata[9:8]; - - assign message_header_c38_protocol_id_we = addr_hit[386] & reg_we & !reg_error; - assign message_header_c38_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c38_token_we = addr_hit[386] & reg_we & !reg_error; - assign message_header_c38_token_wd = reg_wdata[27:18]; - - assign message_header_c38_field1_we = addr_hit[386] & reg_we & !reg_error; - assign message_header_c38_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c38_we = addr_hit[387] & reg_we & !reg_error; - assign message_payload_1_c38_wd = reg_wdata[31:0]; - - assign doorbell_c38_intr_we = addr_hit[388] & reg_we & !reg_error; - assign doorbell_c38_intr_wd = reg_wdata[0]; - - assign doorbell_c38_preserve_mask_we = addr_hit[388] & reg_we & !reg_error; - assign doorbell_c38_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c38_intr_we = addr_hit[389] & reg_we & !reg_error; - assign completion_interrupt_c38_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c38_preserve_mask_we = addr_hit[389] & reg_we & !reg_error; - assign completion_interrupt_c38_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c39_we = addr_hit[390] & reg_we & !reg_error; - assign reserved_1_c39_wd = reg_wdata[31:0]; - - assign channel_status_c39_channel_free_we = addr_hit[391] & reg_we & !reg_error; - assign channel_status_c39_channel_free_wd = reg_wdata[0]; - - assign channel_status_c39_channel_error_we = addr_hit[391] & reg_we & !reg_error; - assign channel_status_c39_channel_error_wd = reg_wdata[1]; - - assign channel_status_c39_field1_we = addr_hit[391] & reg_we & !reg_error; - assign channel_status_c39_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c39_we = addr_hit[392] & reg_we & !reg_error; - assign reserved_2_c39_wd = reg_wdata[31:0]; - - assign channel_flags_c39_intr_enable_we = addr_hit[394] & reg_we & !reg_error; - assign channel_flags_c39_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c39_field1_we = addr_hit[394] & reg_we & !reg_error; - assign channel_flags_c39_field1_wd = reg_wdata[31:1]; - - assign length_c39_we = addr_hit[395] & reg_we & !reg_error; - assign length_c39_wd = reg_wdata[31:0]; - - assign message_header_c39_message_id_we = addr_hit[396] & reg_we & !reg_error; - assign message_header_c39_message_id_wd = reg_wdata[7:0]; - - assign message_header_c39_message_type_we = addr_hit[396] & reg_we & !reg_error; - assign message_header_c39_message_type_wd = reg_wdata[9:8]; - - assign message_header_c39_protocol_id_we = addr_hit[396] & reg_we & !reg_error; - assign message_header_c39_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c39_token_we = addr_hit[396] & reg_we & !reg_error; - assign message_header_c39_token_wd = reg_wdata[27:18]; - - assign message_header_c39_field1_we = addr_hit[396] & reg_we & !reg_error; - assign message_header_c39_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c39_we = addr_hit[397] & reg_we & !reg_error; - assign message_payload_1_c39_wd = reg_wdata[31:0]; - - assign doorbell_c39_intr_we = addr_hit[398] & reg_we & !reg_error; - assign doorbell_c39_intr_wd = reg_wdata[0]; - - assign doorbell_c39_preserve_mask_we = addr_hit[398] & reg_we & !reg_error; - assign doorbell_c39_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c39_intr_we = addr_hit[399] & reg_we & !reg_error; - assign completion_interrupt_c39_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c39_preserve_mask_we = addr_hit[399] & reg_we & !reg_error; - assign completion_interrupt_c39_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c40_we = addr_hit[400] & reg_we & !reg_error; - assign reserved_1_c40_wd = reg_wdata[31:0]; - - assign channel_status_c40_channel_free_we = addr_hit[401] & reg_we & !reg_error; - assign channel_status_c40_channel_free_wd = reg_wdata[0]; - - assign channel_status_c40_channel_error_we = addr_hit[401] & reg_we & !reg_error; - assign channel_status_c40_channel_error_wd = reg_wdata[1]; - - assign channel_status_c40_field1_we = addr_hit[401] & reg_we & !reg_error; - assign channel_status_c40_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c40_we = addr_hit[402] & reg_we & !reg_error; - assign reserved_2_c40_wd = reg_wdata[31:0]; - - assign channel_flags_c40_intr_enable_we = addr_hit[404] & reg_we & !reg_error; - assign channel_flags_c40_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c40_field1_we = addr_hit[404] & reg_we & !reg_error; - assign channel_flags_c40_field1_wd = reg_wdata[31:1]; - - assign length_c40_we = addr_hit[405] & reg_we & !reg_error; - assign length_c40_wd = reg_wdata[31:0]; - - assign message_header_c40_message_id_we = addr_hit[406] & reg_we & !reg_error; - assign message_header_c40_message_id_wd = reg_wdata[7:0]; - - assign message_header_c40_message_type_we = addr_hit[406] & reg_we & !reg_error; - assign message_header_c40_message_type_wd = reg_wdata[9:8]; - - assign message_header_c40_protocol_id_we = addr_hit[406] & reg_we & !reg_error; - assign message_header_c40_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c40_token_we = addr_hit[406] & reg_we & !reg_error; - assign message_header_c40_token_wd = reg_wdata[27:18]; - - assign message_header_c40_field1_we = addr_hit[406] & reg_we & !reg_error; - assign message_header_c40_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c40_we = addr_hit[407] & reg_we & !reg_error; - assign message_payload_1_c40_wd = reg_wdata[31:0]; - - assign doorbell_c40_intr_we = addr_hit[408] & reg_we & !reg_error; - assign doorbell_c40_intr_wd = reg_wdata[0]; - - assign doorbell_c40_preserve_mask_we = addr_hit[408] & reg_we & !reg_error; - assign doorbell_c40_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c40_intr_we = addr_hit[409] & reg_we & !reg_error; - assign completion_interrupt_c40_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c40_preserve_mask_we = addr_hit[409] & reg_we & !reg_error; - assign completion_interrupt_c40_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c41_we = addr_hit[410] & reg_we & !reg_error; - assign reserved_1_c41_wd = reg_wdata[31:0]; - - assign channel_status_c41_channel_free_we = addr_hit[411] & reg_we & !reg_error; - assign channel_status_c41_channel_free_wd = reg_wdata[0]; - - assign channel_status_c41_channel_error_we = addr_hit[411] & reg_we & !reg_error; - assign channel_status_c41_channel_error_wd = reg_wdata[1]; - - assign channel_status_c41_field1_we = addr_hit[411] & reg_we & !reg_error; - assign channel_status_c41_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c41_we = addr_hit[412] & reg_we & !reg_error; - assign reserved_2_c41_wd = reg_wdata[31:0]; - - assign channel_flags_c41_intr_enable_we = addr_hit[414] & reg_we & !reg_error; - assign channel_flags_c41_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c41_field1_we = addr_hit[414] & reg_we & !reg_error; - assign channel_flags_c41_field1_wd = reg_wdata[31:1]; - - assign length_c41_we = addr_hit[415] & reg_we & !reg_error; - assign length_c41_wd = reg_wdata[31:0]; - - assign message_header_c41_message_id_we = addr_hit[416] & reg_we & !reg_error; - assign message_header_c41_message_id_wd = reg_wdata[7:0]; - - assign message_header_c41_message_type_we = addr_hit[416] & reg_we & !reg_error; - assign message_header_c41_message_type_wd = reg_wdata[9:8]; - - assign message_header_c41_protocol_id_we = addr_hit[416] & reg_we & !reg_error; - assign message_header_c41_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c41_token_we = addr_hit[416] & reg_we & !reg_error; - assign message_header_c41_token_wd = reg_wdata[27:18]; - - assign message_header_c41_field1_we = addr_hit[416] & reg_we & !reg_error; - assign message_header_c41_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c41_we = addr_hit[417] & reg_we & !reg_error; - assign message_payload_1_c41_wd = reg_wdata[31:0]; - - assign doorbell_c41_intr_we = addr_hit[418] & reg_we & !reg_error; - assign doorbell_c41_intr_wd = reg_wdata[0]; - - assign doorbell_c41_preserve_mask_we = addr_hit[418] & reg_we & !reg_error; - assign doorbell_c41_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c41_intr_we = addr_hit[419] & reg_we & !reg_error; - assign completion_interrupt_c41_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c41_preserve_mask_we = addr_hit[419] & reg_we & !reg_error; - assign completion_interrupt_c41_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c42_we = addr_hit[420] & reg_we & !reg_error; - assign reserved_1_c42_wd = reg_wdata[31:0]; - - assign channel_status_c42_channel_free_we = addr_hit[421] & reg_we & !reg_error; - assign channel_status_c42_channel_free_wd = reg_wdata[0]; - - assign channel_status_c42_channel_error_we = addr_hit[421] & reg_we & !reg_error; - assign channel_status_c42_channel_error_wd = reg_wdata[1]; - - assign channel_status_c42_field1_we = addr_hit[421] & reg_we & !reg_error; - assign channel_status_c42_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c42_we = addr_hit[422] & reg_we & !reg_error; - assign reserved_2_c42_wd = reg_wdata[31:0]; - - assign channel_flags_c42_intr_enable_we = addr_hit[424] & reg_we & !reg_error; - assign channel_flags_c42_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c42_field1_we = addr_hit[424] & reg_we & !reg_error; - assign channel_flags_c42_field1_wd = reg_wdata[31:1]; - - assign length_c42_we = addr_hit[425] & reg_we & !reg_error; - assign length_c42_wd = reg_wdata[31:0]; - - assign message_header_c42_message_id_we = addr_hit[426] & reg_we & !reg_error; - assign message_header_c42_message_id_wd = reg_wdata[7:0]; - - assign message_header_c42_message_type_we = addr_hit[426] & reg_we & !reg_error; - assign message_header_c42_message_type_wd = reg_wdata[9:8]; - - assign message_header_c42_protocol_id_we = addr_hit[426] & reg_we & !reg_error; - assign message_header_c42_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c42_token_we = addr_hit[426] & reg_we & !reg_error; - assign message_header_c42_token_wd = reg_wdata[27:18]; - - assign message_header_c42_field1_we = addr_hit[426] & reg_we & !reg_error; - assign message_header_c42_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c42_we = addr_hit[427] & reg_we & !reg_error; - assign message_payload_1_c42_wd = reg_wdata[31:0]; - - assign doorbell_c42_intr_we = addr_hit[428] & reg_we & !reg_error; - assign doorbell_c42_intr_wd = reg_wdata[0]; - - assign doorbell_c42_preserve_mask_we = addr_hit[428] & reg_we & !reg_error; - assign doorbell_c42_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c42_intr_we = addr_hit[429] & reg_we & !reg_error; - assign completion_interrupt_c42_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c42_preserve_mask_we = addr_hit[429] & reg_we & !reg_error; - assign completion_interrupt_c42_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c43_we = addr_hit[430] & reg_we & !reg_error; - assign reserved_1_c43_wd = reg_wdata[31:0]; - - assign channel_status_c43_channel_free_we = addr_hit[431] & reg_we & !reg_error; - assign channel_status_c43_channel_free_wd = reg_wdata[0]; - - assign channel_status_c43_channel_error_we = addr_hit[431] & reg_we & !reg_error; - assign channel_status_c43_channel_error_wd = reg_wdata[1]; - - assign channel_status_c43_field1_we = addr_hit[431] & reg_we & !reg_error; - assign channel_status_c43_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c43_we = addr_hit[432] & reg_we & !reg_error; - assign reserved_2_c43_wd = reg_wdata[31:0]; - - assign channel_flags_c43_intr_enable_we = addr_hit[434] & reg_we & !reg_error; - assign channel_flags_c43_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c43_field1_we = addr_hit[434] & reg_we & !reg_error; - assign channel_flags_c43_field1_wd = reg_wdata[31:1]; - - assign length_c43_we = addr_hit[435] & reg_we & !reg_error; - assign length_c43_wd = reg_wdata[31:0]; - - assign message_header_c43_message_id_we = addr_hit[436] & reg_we & !reg_error; - assign message_header_c43_message_id_wd = reg_wdata[7:0]; - - assign message_header_c43_message_type_we = addr_hit[436] & reg_we & !reg_error; - assign message_header_c43_message_type_wd = reg_wdata[9:8]; - - assign message_header_c43_protocol_id_we = addr_hit[436] & reg_we & !reg_error; - assign message_header_c43_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c43_token_we = addr_hit[436] & reg_we & !reg_error; - assign message_header_c43_token_wd = reg_wdata[27:18]; - - assign message_header_c43_field1_we = addr_hit[436] & reg_we & !reg_error; - assign message_header_c43_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c43_we = addr_hit[437] & reg_we & !reg_error; - assign message_payload_1_c43_wd = reg_wdata[31:0]; - - assign doorbell_c43_intr_we = addr_hit[438] & reg_we & !reg_error; - assign doorbell_c43_intr_wd = reg_wdata[0]; - - assign doorbell_c43_preserve_mask_we = addr_hit[438] & reg_we & !reg_error; - assign doorbell_c43_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c43_intr_we = addr_hit[439] & reg_we & !reg_error; - assign completion_interrupt_c43_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c43_preserve_mask_we = addr_hit[439] & reg_we & !reg_error; - assign completion_interrupt_c43_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c44_we = addr_hit[440] & reg_we & !reg_error; - assign reserved_1_c44_wd = reg_wdata[31:0]; - - assign channel_status_c44_channel_free_we = addr_hit[441] & reg_we & !reg_error; - assign channel_status_c44_channel_free_wd = reg_wdata[0]; - - assign channel_status_c44_channel_error_we = addr_hit[441] & reg_we & !reg_error; - assign channel_status_c44_channel_error_wd = reg_wdata[1]; - - assign channel_status_c44_field1_we = addr_hit[441] & reg_we & !reg_error; - assign channel_status_c44_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c44_we = addr_hit[442] & reg_we & !reg_error; - assign reserved_2_c44_wd = reg_wdata[31:0]; - - assign channel_flags_c44_intr_enable_we = addr_hit[444] & reg_we & !reg_error; - assign channel_flags_c44_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c44_field1_we = addr_hit[444] & reg_we & !reg_error; - assign channel_flags_c44_field1_wd = reg_wdata[31:1]; - - assign length_c44_we = addr_hit[445] & reg_we & !reg_error; - assign length_c44_wd = reg_wdata[31:0]; - - assign message_header_c44_message_id_we = addr_hit[446] & reg_we & !reg_error; - assign message_header_c44_message_id_wd = reg_wdata[7:0]; - - assign message_header_c44_message_type_we = addr_hit[446] & reg_we & !reg_error; - assign message_header_c44_message_type_wd = reg_wdata[9:8]; - - assign message_header_c44_protocol_id_we = addr_hit[446] & reg_we & !reg_error; - assign message_header_c44_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c44_token_we = addr_hit[446] & reg_we & !reg_error; - assign message_header_c44_token_wd = reg_wdata[27:18]; - - assign message_header_c44_field1_we = addr_hit[446] & reg_we & !reg_error; - assign message_header_c44_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c44_we = addr_hit[447] & reg_we & !reg_error; - assign message_payload_1_c44_wd = reg_wdata[31:0]; - - assign doorbell_c44_intr_we = addr_hit[448] & reg_we & !reg_error; - assign doorbell_c44_intr_wd = reg_wdata[0]; - - assign doorbell_c44_preserve_mask_we = addr_hit[448] & reg_we & !reg_error; - assign doorbell_c44_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c44_intr_we = addr_hit[449] & reg_we & !reg_error; - assign completion_interrupt_c44_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c44_preserve_mask_we = addr_hit[449] & reg_we & !reg_error; - assign completion_interrupt_c44_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c45_we = addr_hit[450] & reg_we & !reg_error; - assign reserved_1_c45_wd = reg_wdata[31:0]; - - assign channel_status_c45_channel_free_we = addr_hit[451] & reg_we & !reg_error; - assign channel_status_c45_channel_free_wd = reg_wdata[0]; - - assign channel_status_c45_channel_error_we = addr_hit[451] & reg_we & !reg_error; - assign channel_status_c45_channel_error_wd = reg_wdata[1]; - - assign channel_status_c45_field1_we = addr_hit[451] & reg_we & !reg_error; - assign channel_status_c45_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c45_we = addr_hit[452] & reg_we & !reg_error; - assign reserved_2_c45_wd = reg_wdata[31:0]; - - assign channel_flags_c45_intr_enable_we = addr_hit[454] & reg_we & !reg_error; - assign channel_flags_c45_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c45_field1_we = addr_hit[454] & reg_we & !reg_error; - assign channel_flags_c45_field1_wd = reg_wdata[31:1]; - - assign length_c45_we = addr_hit[455] & reg_we & !reg_error; - assign length_c45_wd = reg_wdata[31:0]; - - assign message_header_c45_message_id_we = addr_hit[456] & reg_we & !reg_error; - assign message_header_c45_message_id_wd = reg_wdata[7:0]; - - assign message_header_c45_message_type_we = addr_hit[456] & reg_we & !reg_error; - assign message_header_c45_message_type_wd = reg_wdata[9:8]; - - assign message_header_c45_protocol_id_we = addr_hit[456] & reg_we & !reg_error; - assign message_header_c45_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c45_token_we = addr_hit[456] & reg_we & !reg_error; - assign message_header_c45_token_wd = reg_wdata[27:18]; - - assign message_header_c45_field1_we = addr_hit[456] & reg_we & !reg_error; - assign message_header_c45_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c45_we = addr_hit[457] & reg_we & !reg_error; - assign message_payload_1_c45_wd = reg_wdata[31:0]; - - assign doorbell_c45_intr_we = addr_hit[458] & reg_we & !reg_error; - assign doorbell_c45_intr_wd = reg_wdata[0]; - - assign doorbell_c45_preserve_mask_we = addr_hit[458] & reg_we & !reg_error; - assign doorbell_c45_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c45_intr_we = addr_hit[459] & reg_we & !reg_error; - assign completion_interrupt_c45_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c45_preserve_mask_we = addr_hit[459] & reg_we & !reg_error; - assign completion_interrupt_c45_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c46_we = addr_hit[460] & reg_we & !reg_error; - assign reserved_1_c46_wd = reg_wdata[31:0]; - - assign channel_status_c46_channel_free_we = addr_hit[461] & reg_we & !reg_error; - assign channel_status_c46_channel_free_wd = reg_wdata[0]; - - assign channel_status_c46_channel_error_we = addr_hit[461] & reg_we & !reg_error; - assign channel_status_c46_channel_error_wd = reg_wdata[1]; - - assign channel_status_c46_field1_we = addr_hit[461] & reg_we & !reg_error; - assign channel_status_c46_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c46_we = addr_hit[462] & reg_we & !reg_error; - assign reserved_2_c46_wd = reg_wdata[31:0]; - - assign channel_flags_c46_intr_enable_we = addr_hit[464] & reg_we & !reg_error; - assign channel_flags_c46_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c46_field1_we = addr_hit[464] & reg_we & !reg_error; - assign channel_flags_c46_field1_wd = reg_wdata[31:1]; - - assign length_c46_we = addr_hit[465] & reg_we & !reg_error; - assign length_c46_wd = reg_wdata[31:0]; - - assign message_header_c46_message_id_we = addr_hit[466] & reg_we & !reg_error; - assign message_header_c46_message_id_wd = reg_wdata[7:0]; - - assign message_header_c46_message_type_we = addr_hit[466] & reg_we & !reg_error; - assign message_header_c46_message_type_wd = reg_wdata[9:8]; - - assign message_header_c46_protocol_id_we = addr_hit[466] & reg_we & !reg_error; - assign message_header_c46_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c46_token_we = addr_hit[466] & reg_we & !reg_error; - assign message_header_c46_token_wd = reg_wdata[27:18]; - - assign message_header_c46_field1_we = addr_hit[466] & reg_we & !reg_error; - assign message_header_c46_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c46_we = addr_hit[467] & reg_we & !reg_error; - assign message_payload_1_c46_wd = reg_wdata[31:0]; - - assign doorbell_c46_intr_we = addr_hit[468] & reg_we & !reg_error; - assign doorbell_c46_intr_wd = reg_wdata[0]; - - assign doorbell_c46_preserve_mask_we = addr_hit[468] & reg_we & !reg_error; - assign doorbell_c46_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c46_intr_we = addr_hit[469] & reg_we & !reg_error; - assign completion_interrupt_c46_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c46_preserve_mask_we = addr_hit[469] & reg_we & !reg_error; - assign completion_interrupt_c46_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c47_we = addr_hit[470] & reg_we & !reg_error; - assign reserved_1_c47_wd = reg_wdata[31:0]; - - assign channel_status_c47_channel_free_we = addr_hit[471] & reg_we & !reg_error; - assign channel_status_c47_channel_free_wd = reg_wdata[0]; - - assign channel_status_c47_channel_error_we = addr_hit[471] & reg_we & !reg_error; - assign channel_status_c47_channel_error_wd = reg_wdata[1]; - - assign channel_status_c47_field1_we = addr_hit[471] & reg_we & !reg_error; - assign channel_status_c47_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c47_we = addr_hit[472] & reg_we & !reg_error; - assign reserved_2_c47_wd = reg_wdata[31:0]; - - assign channel_flags_c47_intr_enable_we = addr_hit[474] & reg_we & !reg_error; - assign channel_flags_c47_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c47_field1_we = addr_hit[474] & reg_we & !reg_error; - assign channel_flags_c47_field1_wd = reg_wdata[31:1]; - - assign length_c47_we = addr_hit[475] & reg_we & !reg_error; - assign length_c47_wd = reg_wdata[31:0]; - - assign message_header_c47_message_id_we = addr_hit[476] & reg_we & !reg_error; - assign message_header_c47_message_id_wd = reg_wdata[7:0]; - - assign message_header_c47_message_type_we = addr_hit[476] & reg_we & !reg_error; - assign message_header_c47_message_type_wd = reg_wdata[9:8]; - - assign message_header_c47_protocol_id_we = addr_hit[476] & reg_we & !reg_error; - assign message_header_c47_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c47_token_we = addr_hit[476] & reg_we & !reg_error; - assign message_header_c47_token_wd = reg_wdata[27:18]; - - assign message_header_c47_field1_we = addr_hit[476] & reg_we & !reg_error; - assign message_header_c47_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c47_we = addr_hit[477] & reg_we & !reg_error; - assign message_payload_1_c47_wd = reg_wdata[31:0]; - - assign doorbell_c47_intr_we = addr_hit[478] & reg_we & !reg_error; - assign doorbell_c47_intr_wd = reg_wdata[0]; - - assign doorbell_c47_preserve_mask_we = addr_hit[478] & reg_we & !reg_error; - assign doorbell_c47_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c47_intr_we = addr_hit[479] & reg_we & !reg_error; - assign completion_interrupt_c47_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c47_preserve_mask_we = addr_hit[479] & reg_we & !reg_error; - assign completion_interrupt_c47_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c48_we = addr_hit[480] & reg_we & !reg_error; - assign reserved_1_c48_wd = reg_wdata[31:0]; - - assign channel_status_c48_channel_free_we = addr_hit[481] & reg_we & !reg_error; - assign channel_status_c48_channel_free_wd = reg_wdata[0]; - - assign channel_status_c48_channel_error_we = addr_hit[481] & reg_we & !reg_error; - assign channel_status_c48_channel_error_wd = reg_wdata[1]; - - assign channel_status_c48_field1_we = addr_hit[481] & reg_we & !reg_error; - assign channel_status_c48_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c48_we = addr_hit[482] & reg_we & !reg_error; - assign reserved_2_c48_wd = reg_wdata[31:0]; - - assign channel_flags_c48_intr_enable_we = addr_hit[484] & reg_we & !reg_error; - assign channel_flags_c48_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c48_field1_we = addr_hit[484] & reg_we & !reg_error; - assign channel_flags_c48_field1_wd = reg_wdata[31:1]; - - assign length_c48_we = addr_hit[485] & reg_we & !reg_error; - assign length_c48_wd = reg_wdata[31:0]; - - assign message_header_c48_message_id_we = addr_hit[486] & reg_we & !reg_error; - assign message_header_c48_message_id_wd = reg_wdata[7:0]; - - assign message_header_c48_message_type_we = addr_hit[486] & reg_we & !reg_error; - assign message_header_c48_message_type_wd = reg_wdata[9:8]; - - assign message_header_c48_protocol_id_we = addr_hit[486] & reg_we & !reg_error; - assign message_header_c48_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c48_token_we = addr_hit[486] & reg_we & !reg_error; - assign message_header_c48_token_wd = reg_wdata[27:18]; - - assign message_header_c48_field1_we = addr_hit[486] & reg_we & !reg_error; - assign message_header_c48_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c48_we = addr_hit[487] & reg_we & !reg_error; - assign message_payload_1_c48_wd = reg_wdata[31:0]; - - assign doorbell_c48_intr_we = addr_hit[488] & reg_we & !reg_error; - assign doorbell_c48_intr_wd = reg_wdata[0]; - - assign doorbell_c48_preserve_mask_we = addr_hit[488] & reg_we & !reg_error; - assign doorbell_c48_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c48_intr_we = addr_hit[489] & reg_we & !reg_error; - assign completion_interrupt_c48_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c48_preserve_mask_we = addr_hit[489] & reg_we & !reg_error; - assign completion_interrupt_c48_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c49_we = addr_hit[490] & reg_we & !reg_error; - assign reserved_1_c49_wd = reg_wdata[31:0]; - - assign channel_status_c49_channel_free_we = addr_hit[491] & reg_we & !reg_error; - assign channel_status_c49_channel_free_wd = reg_wdata[0]; - - assign channel_status_c49_channel_error_we = addr_hit[491] & reg_we & !reg_error; - assign channel_status_c49_channel_error_wd = reg_wdata[1]; - - assign channel_status_c49_field1_we = addr_hit[491] & reg_we & !reg_error; - assign channel_status_c49_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c49_we = addr_hit[492] & reg_we & !reg_error; - assign reserved_2_c49_wd = reg_wdata[31:0]; - - assign channel_flags_c49_intr_enable_we = addr_hit[494] & reg_we & !reg_error; - assign channel_flags_c49_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c49_field1_we = addr_hit[494] & reg_we & !reg_error; - assign channel_flags_c49_field1_wd = reg_wdata[31:1]; - - assign length_c49_we = addr_hit[495] & reg_we & !reg_error; - assign length_c49_wd = reg_wdata[31:0]; - - assign message_header_c49_message_id_we = addr_hit[496] & reg_we & !reg_error; - assign message_header_c49_message_id_wd = reg_wdata[7:0]; - - assign message_header_c49_message_type_we = addr_hit[496] & reg_we & !reg_error; - assign message_header_c49_message_type_wd = reg_wdata[9:8]; - - assign message_header_c49_protocol_id_we = addr_hit[496] & reg_we & !reg_error; - assign message_header_c49_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c49_token_we = addr_hit[496] & reg_we & !reg_error; - assign message_header_c49_token_wd = reg_wdata[27:18]; - - assign message_header_c49_field1_we = addr_hit[496] & reg_we & !reg_error; - assign message_header_c49_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c49_we = addr_hit[497] & reg_we & !reg_error; - assign message_payload_1_c49_wd = reg_wdata[31:0]; - - assign doorbell_c49_intr_we = addr_hit[498] & reg_we & !reg_error; - assign doorbell_c49_intr_wd = reg_wdata[0]; - - assign doorbell_c49_preserve_mask_we = addr_hit[498] & reg_we & !reg_error; - assign doorbell_c49_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c49_intr_we = addr_hit[499] & reg_we & !reg_error; - assign completion_interrupt_c49_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c49_preserve_mask_we = addr_hit[499] & reg_we & !reg_error; - assign completion_interrupt_c49_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c50_we = addr_hit[500] & reg_we & !reg_error; - assign reserved_1_c50_wd = reg_wdata[31:0]; - - assign channel_status_c50_channel_free_we = addr_hit[501] & reg_we & !reg_error; - assign channel_status_c50_channel_free_wd = reg_wdata[0]; - - assign channel_status_c50_channel_error_we = addr_hit[501] & reg_we & !reg_error; - assign channel_status_c50_channel_error_wd = reg_wdata[1]; - - assign channel_status_c50_field1_we = addr_hit[501] & reg_we & !reg_error; - assign channel_status_c50_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c50_we = addr_hit[502] & reg_we & !reg_error; - assign reserved_2_c50_wd = reg_wdata[31:0]; - - assign channel_flags_c50_intr_enable_we = addr_hit[504] & reg_we & !reg_error; - assign channel_flags_c50_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c50_field1_we = addr_hit[504] & reg_we & !reg_error; - assign channel_flags_c50_field1_wd = reg_wdata[31:1]; - - assign length_c50_we = addr_hit[505] & reg_we & !reg_error; - assign length_c50_wd = reg_wdata[31:0]; - - assign message_header_c50_message_id_we = addr_hit[506] & reg_we & !reg_error; - assign message_header_c50_message_id_wd = reg_wdata[7:0]; - - assign message_header_c50_message_type_we = addr_hit[506] & reg_we & !reg_error; - assign message_header_c50_message_type_wd = reg_wdata[9:8]; - - assign message_header_c50_protocol_id_we = addr_hit[506] & reg_we & !reg_error; - assign message_header_c50_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c50_token_we = addr_hit[506] & reg_we & !reg_error; - assign message_header_c50_token_wd = reg_wdata[27:18]; - - assign message_header_c50_field1_we = addr_hit[506] & reg_we & !reg_error; - assign message_header_c50_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c50_we = addr_hit[507] & reg_we & !reg_error; - assign message_payload_1_c50_wd = reg_wdata[31:0]; - - assign doorbell_c50_intr_we = addr_hit[508] & reg_we & !reg_error; - assign doorbell_c50_intr_wd = reg_wdata[0]; - - assign doorbell_c50_preserve_mask_we = addr_hit[508] & reg_we & !reg_error; - assign doorbell_c50_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c50_intr_we = addr_hit[509] & reg_we & !reg_error; - assign completion_interrupt_c50_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c50_preserve_mask_we = addr_hit[509] & reg_we & !reg_error; - assign completion_interrupt_c50_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c51_we = addr_hit[510] & reg_we & !reg_error; - assign reserved_1_c51_wd = reg_wdata[31:0]; - - assign channel_status_c51_channel_free_we = addr_hit[511] & reg_we & !reg_error; - assign channel_status_c51_channel_free_wd = reg_wdata[0]; - - assign channel_status_c51_channel_error_we = addr_hit[511] & reg_we & !reg_error; - assign channel_status_c51_channel_error_wd = reg_wdata[1]; - - assign channel_status_c51_field1_we = addr_hit[511] & reg_we & !reg_error; - assign channel_status_c51_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c51_we = addr_hit[512] & reg_we & !reg_error; - assign reserved_2_c51_wd = reg_wdata[31:0]; - - assign channel_flags_c51_intr_enable_we = addr_hit[514] & reg_we & !reg_error; - assign channel_flags_c51_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c51_field1_we = addr_hit[514] & reg_we & !reg_error; - assign channel_flags_c51_field1_wd = reg_wdata[31:1]; - - assign length_c51_we = addr_hit[515] & reg_we & !reg_error; - assign length_c51_wd = reg_wdata[31:0]; - - assign message_header_c51_message_id_we = addr_hit[516] & reg_we & !reg_error; - assign message_header_c51_message_id_wd = reg_wdata[7:0]; - - assign message_header_c51_message_type_we = addr_hit[516] & reg_we & !reg_error; - assign message_header_c51_message_type_wd = reg_wdata[9:8]; - - assign message_header_c51_protocol_id_we = addr_hit[516] & reg_we & !reg_error; - assign message_header_c51_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c51_token_we = addr_hit[516] & reg_we & !reg_error; - assign message_header_c51_token_wd = reg_wdata[27:18]; - - assign message_header_c51_field1_we = addr_hit[516] & reg_we & !reg_error; - assign message_header_c51_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c51_we = addr_hit[517] & reg_we & !reg_error; - assign message_payload_1_c51_wd = reg_wdata[31:0]; - - assign doorbell_c51_intr_we = addr_hit[518] & reg_we & !reg_error; - assign doorbell_c51_intr_wd = reg_wdata[0]; - - assign doorbell_c51_preserve_mask_we = addr_hit[518] & reg_we & !reg_error; - assign doorbell_c51_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c51_intr_we = addr_hit[519] & reg_we & !reg_error; - assign completion_interrupt_c51_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c51_preserve_mask_we = addr_hit[519] & reg_we & !reg_error; - assign completion_interrupt_c51_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c52_we = addr_hit[520] & reg_we & !reg_error; - assign reserved_1_c52_wd = reg_wdata[31:0]; - - assign channel_status_c52_channel_free_we = addr_hit[521] & reg_we & !reg_error; - assign channel_status_c52_channel_free_wd = reg_wdata[0]; - - assign channel_status_c52_channel_error_we = addr_hit[521] & reg_we & !reg_error; - assign channel_status_c52_channel_error_wd = reg_wdata[1]; - - assign channel_status_c52_field1_we = addr_hit[521] & reg_we & !reg_error; - assign channel_status_c52_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c52_we = addr_hit[522] & reg_we & !reg_error; - assign reserved_2_c52_wd = reg_wdata[31:0]; - - assign channel_flags_c52_intr_enable_we = addr_hit[524] & reg_we & !reg_error; - assign channel_flags_c52_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c52_field1_we = addr_hit[524] & reg_we & !reg_error; - assign channel_flags_c52_field1_wd = reg_wdata[31:1]; - - assign length_c52_we = addr_hit[525] & reg_we & !reg_error; - assign length_c52_wd = reg_wdata[31:0]; - - assign message_header_c52_message_id_we = addr_hit[526] & reg_we & !reg_error; - assign message_header_c52_message_id_wd = reg_wdata[7:0]; - - assign message_header_c52_message_type_we = addr_hit[526] & reg_we & !reg_error; - assign message_header_c52_message_type_wd = reg_wdata[9:8]; - - assign message_header_c52_protocol_id_we = addr_hit[526] & reg_we & !reg_error; - assign message_header_c52_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c52_token_we = addr_hit[526] & reg_we & !reg_error; - assign message_header_c52_token_wd = reg_wdata[27:18]; - - assign message_header_c52_field1_we = addr_hit[526] & reg_we & !reg_error; - assign message_header_c52_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c52_we = addr_hit[527] & reg_we & !reg_error; - assign message_payload_1_c52_wd = reg_wdata[31:0]; - - assign doorbell_c52_intr_we = addr_hit[528] & reg_we & !reg_error; - assign doorbell_c52_intr_wd = reg_wdata[0]; - - assign doorbell_c52_preserve_mask_we = addr_hit[528] & reg_we & !reg_error; - assign doorbell_c52_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c52_intr_we = addr_hit[529] & reg_we & !reg_error; - assign completion_interrupt_c52_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c52_preserve_mask_we = addr_hit[529] & reg_we & !reg_error; - assign completion_interrupt_c52_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c53_we = addr_hit[530] & reg_we & !reg_error; - assign reserved_1_c53_wd = reg_wdata[31:0]; - - assign channel_status_c53_channel_free_we = addr_hit[531] & reg_we & !reg_error; - assign channel_status_c53_channel_free_wd = reg_wdata[0]; - - assign channel_status_c53_channel_error_we = addr_hit[531] & reg_we & !reg_error; - assign channel_status_c53_channel_error_wd = reg_wdata[1]; - - assign channel_status_c53_field1_we = addr_hit[531] & reg_we & !reg_error; - assign channel_status_c53_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c53_we = addr_hit[532] & reg_we & !reg_error; - assign reserved_2_c53_wd = reg_wdata[31:0]; - - assign channel_flags_c53_intr_enable_we = addr_hit[534] & reg_we & !reg_error; - assign channel_flags_c53_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c53_field1_we = addr_hit[534] & reg_we & !reg_error; - assign channel_flags_c53_field1_wd = reg_wdata[31:1]; - - assign length_c53_we = addr_hit[535] & reg_we & !reg_error; - assign length_c53_wd = reg_wdata[31:0]; - - assign message_header_c53_message_id_we = addr_hit[536] & reg_we & !reg_error; - assign message_header_c53_message_id_wd = reg_wdata[7:0]; - - assign message_header_c53_message_type_we = addr_hit[536] & reg_we & !reg_error; - assign message_header_c53_message_type_wd = reg_wdata[9:8]; - - assign message_header_c53_protocol_id_we = addr_hit[536] & reg_we & !reg_error; - assign message_header_c53_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c53_token_we = addr_hit[536] & reg_we & !reg_error; - assign message_header_c53_token_wd = reg_wdata[27:18]; - - assign message_header_c53_field1_we = addr_hit[536] & reg_we & !reg_error; - assign message_header_c53_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c53_we = addr_hit[537] & reg_we & !reg_error; - assign message_payload_1_c53_wd = reg_wdata[31:0]; - - assign doorbell_c53_intr_we = addr_hit[538] & reg_we & !reg_error; - assign doorbell_c53_intr_wd = reg_wdata[0]; - - assign doorbell_c53_preserve_mask_we = addr_hit[538] & reg_we & !reg_error; - assign doorbell_c53_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c53_intr_we = addr_hit[539] & reg_we & !reg_error; - assign completion_interrupt_c53_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c53_preserve_mask_we = addr_hit[539] & reg_we & !reg_error; - assign completion_interrupt_c53_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c54_we = addr_hit[540] & reg_we & !reg_error; - assign reserved_1_c54_wd = reg_wdata[31:0]; - - assign channel_status_c54_channel_free_we = addr_hit[541] & reg_we & !reg_error; - assign channel_status_c54_channel_free_wd = reg_wdata[0]; - - assign channel_status_c54_channel_error_we = addr_hit[541] & reg_we & !reg_error; - assign channel_status_c54_channel_error_wd = reg_wdata[1]; - - assign channel_status_c54_field1_we = addr_hit[541] & reg_we & !reg_error; - assign channel_status_c54_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c54_we = addr_hit[542] & reg_we & !reg_error; - assign reserved_2_c54_wd = reg_wdata[31:0]; - - assign channel_flags_c54_intr_enable_we = addr_hit[544] & reg_we & !reg_error; - assign channel_flags_c54_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c54_field1_we = addr_hit[544] & reg_we & !reg_error; - assign channel_flags_c54_field1_wd = reg_wdata[31:1]; - - assign length_c54_we = addr_hit[545] & reg_we & !reg_error; - assign length_c54_wd = reg_wdata[31:0]; - - assign message_header_c54_message_id_we = addr_hit[546] & reg_we & !reg_error; - assign message_header_c54_message_id_wd = reg_wdata[7:0]; - - assign message_header_c54_message_type_we = addr_hit[546] & reg_we & !reg_error; - assign message_header_c54_message_type_wd = reg_wdata[9:8]; - - assign message_header_c54_protocol_id_we = addr_hit[546] & reg_we & !reg_error; - assign message_header_c54_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c54_token_we = addr_hit[546] & reg_we & !reg_error; - assign message_header_c54_token_wd = reg_wdata[27:18]; - - assign message_header_c54_field1_we = addr_hit[546] & reg_we & !reg_error; - assign message_header_c54_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c54_we = addr_hit[547] & reg_we & !reg_error; - assign message_payload_1_c54_wd = reg_wdata[31:0]; - - assign doorbell_c54_intr_we = addr_hit[548] & reg_we & !reg_error; - assign doorbell_c54_intr_wd = reg_wdata[0]; - - assign doorbell_c54_preserve_mask_we = addr_hit[548] & reg_we & !reg_error; - assign doorbell_c54_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c54_intr_we = addr_hit[549] & reg_we & !reg_error; - assign completion_interrupt_c54_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c54_preserve_mask_we = addr_hit[549] & reg_we & !reg_error; - assign completion_interrupt_c54_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c55_we = addr_hit[550] & reg_we & !reg_error; - assign reserved_1_c55_wd = reg_wdata[31:0]; - - assign channel_status_c55_channel_free_we = addr_hit[551] & reg_we & !reg_error; - assign channel_status_c55_channel_free_wd = reg_wdata[0]; - - assign channel_status_c55_channel_error_we = addr_hit[551] & reg_we & !reg_error; - assign channel_status_c55_channel_error_wd = reg_wdata[1]; - - assign channel_status_c55_field1_we = addr_hit[551] & reg_we & !reg_error; - assign channel_status_c55_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c55_we = addr_hit[552] & reg_we & !reg_error; - assign reserved_2_c55_wd = reg_wdata[31:0]; - - assign channel_flags_c55_intr_enable_we = addr_hit[554] & reg_we & !reg_error; - assign channel_flags_c55_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c55_field1_we = addr_hit[554] & reg_we & !reg_error; - assign channel_flags_c55_field1_wd = reg_wdata[31:1]; - - assign length_c55_we = addr_hit[555] & reg_we & !reg_error; - assign length_c55_wd = reg_wdata[31:0]; - - assign message_header_c55_message_id_we = addr_hit[556] & reg_we & !reg_error; - assign message_header_c55_message_id_wd = reg_wdata[7:0]; - - assign message_header_c55_message_type_we = addr_hit[556] & reg_we & !reg_error; - assign message_header_c55_message_type_wd = reg_wdata[9:8]; - - assign message_header_c55_protocol_id_we = addr_hit[556] & reg_we & !reg_error; - assign message_header_c55_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c55_token_we = addr_hit[556] & reg_we & !reg_error; - assign message_header_c55_token_wd = reg_wdata[27:18]; - - assign message_header_c55_field1_we = addr_hit[556] & reg_we & !reg_error; - assign message_header_c55_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c55_we = addr_hit[557] & reg_we & !reg_error; - assign message_payload_1_c55_wd = reg_wdata[31:0]; - - assign doorbell_c55_intr_we = addr_hit[558] & reg_we & !reg_error; - assign doorbell_c55_intr_wd = reg_wdata[0]; - - assign doorbell_c55_preserve_mask_we = addr_hit[558] & reg_we & !reg_error; - assign doorbell_c55_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c55_intr_we = addr_hit[559] & reg_we & !reg_error; - assign completion_interrupt_c55_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c55_preserve_mask_we = addr_hit[559] & reg_we & !reg_error; - assign completion_interrupt_c55_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c56_we = addr_hit[560] & reg_we & !reg_error; - assign reserved_1_c56_wd = reg_wdata[31:0]; - - assign channel_status_c56_channel_free_we = addr_hit[561] & reg_we & !reg_error; - assign channel_status_c56_channel_free_wd = reg_wdata[0]; - - assign channel_status_c56_channel_error_we = addr_hit[561] & reg_we & !reg_error; - assign channel_status_c56_channel_error_wd = reg_wdata[1]; - - assign channel_status_c56_field1_we = addr_hit[561] & reg_we & !reg_error; - assign channel_status_c56_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c56_we = addr_hit[562] & reg_we & !reg_error; - assign reserved_2_c56_wd = reg_wdata[31:0]; - - assign channel_flags_c56_intr_enable_we = addr_hit[564] & reg_we & !reg_error; - assign channel_flags_c56_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c56_field1_we = addr_hit[564] & reg_we & !reg_error; - assign channel_flags_c56_field1_wd = reg_wdata[31:1]; - - assign length_c56_we = addr_hit[565] & reg_we & !reg_error; - assign length_c56_wd = reg_wdata[31:0]; - - assign message_header_c56_message_id_we = addr_hit[566] & reg_we & !reg_error; - assign message_header_c56_message_id_wd = reg_wdata[7:0]; - - assign message_header_c56_message_type_we = addr_hit[566] & reg_we & !reg_error; - assign message_header_c56_message_type_wd = reg_wdata[9:8]; - - assign message_header_c56_protocol_id_we = addr_hit[566] & reg_we & !reg_error; - assign message_header_c56_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c56_token_we = addr_hit[566] & reg_we & !reg_error; - assign message_header_c56_token_wd = reg_wdata[27:18]; - - assign message_header_c56_field1_we = addr_hit[566] & reg_we & !reg_error; - assign message_header_c56_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c56_we = addr_hit[567] & reg_we & !reg_error; - assign message_payload_1_c56_wd = reg_wdata[31:0]; - - assign doorbell_c56_intr_we = addr_hit[568] & reg_we & !reg_error; - assign doorbell_c56_intr_wd = reg_wdata[0]; - - assign doorbell_c56_preserve_mask_we = addr_hit[568] & reg_we & !reg_error; - assign doorbell_c56_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c56_intr_we = addr_hit[569] & reg_we & !reg_error; - assign completion_interrupt_c56_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c56_preserve_mask_we = addr_hit[569] & reg_we & !reg_error; - assign completion_interrupt_c56_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c57_we = addr_hit[570] & reg_we & !reg_error; - assign reserved_1_c57_wd = reg_wdata[31:0]; - - assign channel_status_c57_channel_free_we = addr_hit[571] & reg_we & !reg_error; - assign channel_status_c57_channel_free_wd = reg_wdata[0]; - - assign channel_status_c57_channel_error_we = addr_hit[571] & reg_we & !reg_error; - assign channel_status_c57_channel_error_wd = reg_wdata[1]; - - assign channel_status_c57_field1_we = addr_hit[571] & reg_we & !reg_error; - assign channel_status_c57_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c57_we = addr_hit[572] & reg_we & !reg_error; - assign reserved_2_c57_wd = reg_wdata[31:0]; - - assign channel_flags_c57_intr_enable_we = addr_hit[574] & reg_we & !reg_error; - assign channel_flags_c57_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c57_field1_we = addr_hit[574] & reg_we & !reg_error; - assign channel_flags_c57_field1_wd = reg_wdata[31:1]; - - assign length_c57_we = addr_hit[575] & reg_we & !reg_error; - assign length_c57_wd = reg_wdata[31:0]; - - assign message_header_c57_message_id_we = addr_hit[576] & reg_we & !reg_error; - assign message_header_c57_message_id_wd = reg_wdata[7:0]; - - assign message_header_c57_message_type_we = addr_hit[576] & reg_we & !reg_error; - assign message_header_c57_message_type_wd = reg_wdata[9:8]; - - assign message_header_c57_protocol_id_we = addr_hit[576] & reg_we & !reg_error; - assign message_header_c57_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c57_token_we = addr_hit[576] & reg_we & !reg_error; - assign message_header_c57_token_wd = reg_wdata[27:18]; - - assign message_header_c57_field1_we = addr_hit[576] & reg_we & !reg_error; - assign message_header_c57_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c57_we = addr_hit[577] & reg_we & !reg_error; - assign message_payload_1_c57_wd = reg_wdata[31:0]; - - assign doorbell_c57_intr_we = addr_hit[578] & reg_we & !reg_error; - assign doorbell_c57_intr_wd = reg_wdata[0]; - - assign doorbell_c57_preserve_mask_we = addr_hit[578] & reg_we & !reg_error; - assign doorbell_c57_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c57_intr_we = addr_hit[579] & reg_we & !reg_error; - assign completion_interrupt_c57_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c57_preserve_mask_we = addr_hit[579] & reg_we & !reg_error; - assign completion_interrupt_c57_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c58_we = addr_hit[580] & reg_we & !reg_error; - assign reserved_1_c58_wd = reg_wdata[31:0]; - - assign channel_status_c58_channel_free_we = addr_hit[581] & reg_we & !reg_error; - assign channel_status_c58_channel_free_wd = reg_wdata[0]; - - assign channel_status_c58_channel_error_we = addr_hit[581] & reg_we & !reg_error; - assign channel_status_c58_channel_error_wd = reg_wdata[1]; - - assign channel_status_c58_field1_we = addr_hit[581] & reg_we & !reg_error; - assign channel_status_c58_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c58_we = addr_hit[582] & reg_we & !reg_error; - assign reserved_2_c58_wd = reg_wdata[31:0]; - - assign channel_flags_c58_intr_enable_we = addr_hit[584] & reg_we & !reg_error; - assign channel_flags_c58_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c58_field1_we = addr_hit[584] & reg_we & !reg_error; - assign channel_flags_c58_field1_wd = reg_wdata[31:1]; - - assign length_c58_we = addr_hit[585] & reg_we & !reg_error; - assign length_c58_wd = reg_wdata[31:0]; - - assign message_header_c58_message_id_we = addr_hit[586] & reg_we & !reg_error; - assign message_header_c58_message_id_wd = reg_wdata[7:0]; - - assign message_header_c58_message_type_we = addr_hit[586] & reg_we & !reg_error; - assign message_header_c58_message_type_wd = reg_wdata[9:8]; - - assign message_header_c58_protocol_id_we = addr_hit[586] & reg_we & !reg_error; - assign message_header_c58_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c58_token_we = addr_hit[586] & reg_we & !reg_error; - assign message_header_c58_token_wd = reg_wdata[27:18]; - - assign message_header_c58_field1_we = addr_hit[586] & reg_we & !reg_error; - assign message_header_c58_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c58_we = addr_hit[587] & reg_we & !reg_error; - assign message_payload_1_c58_wd = reg_wdata[31:0]; - - assign doorbell_c58_intr_we = addr_hit[588] & reg_we & !reg_error; - assign doorbell_c58_intr_wd = reg_wdata[0]; - - assign doorbell_c58_preserve_mask_we = addr_hit[588] & reg_we & !reg_error; - assign doorbell_c58_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c58_intr_we = addr_hit[589] & reg_we & !reg_error; - assign completion_interrupt_c58_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c58_preserve_mask_we = addr_hit[589] & reg_we & !reg_error; - assign completion_interrupt_c58_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c59_we = addr_hit[590] & reg_we & !reg_error; - assign reserved_1_c59_wd = reg_wdata[31:0]; - - assign channel_status_c59_channel_free_we = addr_hit[591] & reg_we & !reg_error; - assign channel_status_c59_channel_free_wd = reg_wdata[0]; - - assign channel_status_c59_channel_error_we = addr_hit[591] & reg_we & !reg_error; - assign channel_status_c59_channel_error_wd = reg_wdata[1]; - - assign channel_status_c59_field1_we = addr_hit[591] & reg_we & !reg_error; - assign channel_status_c59_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c59_we = addr_hit[592] & reg_we & !reg_error; - assign reserved_2_c59_wd = reg_wdata[31:0]; - - assign channel_flags_c59_intr_enable_we = addr_hit[594] & reg_we & !reg_error; - assign channel_flags_c59_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c59_field1_we = addr_hit[594] & reg_we & !reg_error; - assign channel_flags_c59_field1_wd = reg_wdata[31:1]; - - assign length_c59_we = addr_hit[595] & reg_we & !reg_error; - assign length_c59_wd = reg_wdata[31:0]; - - assign message_header_c59_message_id_we = addr_hit[596] & reg_we & !reg_error; - assign message_header_c59_message_id_wd = reg_wdata[7:0]; - - assign message_header_c59_message_type_we = addr_hit[596] & reg_we & !reg_error; - assign message_header_c59_message_type_wd = reg_wdata[9:8]; - - assign message_header_c59_protocol_id_we = addr_hit[596] & reg_we & !reg_error; - assign message_header_c59_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c59_token_we = addr_hit[596] & reg_we & !reg_error; - assign message_header_c59_token_wd = reg_wdata[27:18]; - - assign message_header_c59_field1_we = addr_hit[596] & reg_we & !reg_error; - assign message_header_c59_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c59_we = addr_hit[597] & reg_we & !reg_error; - assign message_payload_1_c59_wd = reg_wdata[31:0]; - - assign doorbell_c59_intr_we = addr_hit[598] & reg_we & !reg_error; - assign doorbell_c59_intr_wd = reg_wdata[0]; - - assign doorbell_c59_preserve_mask_we = addr_hit[598] & reg_we & !reg_error; - assign doorbell_c59_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c59_intr_we = addr_hit[599] & reg_we & !reg_error; - assign completion_interrupt_c59_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c59_preserve_mask_we = addr_hit[599] & reg_we & !reg_error; - assign completion_interrupt_c59_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c60_we = addr_hit[600] & reg_we & !reg_error; - assign reserved_1_c60_wd = reg_wdata[31:0]; - - assign channel_status_c60_channel_free_we = addr_hit[601] & reg_we & !reg_error; - assign channel_status_c60_channel_free_wd = reg_wdata[0]; - - assign channel_status_c60_channel_error_we = addr_hit[601] & reg_we & !reg_error; - assign channel_status_c60_channel_error_wd = reg_wdata[1]; - - assign channel_status_c60_field1_we = addr_hit[601] & reg_we & !reg_error; - assign channel_status_c60_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c60_we = addr_hit[602] & reg_we & !reg_error; - assign reserved_2_c60_wd = reg_wdata[31:0]; - - assign channel_flags_c60_intr_enable_we = addr_hit[604] & reg_we & !reg_error; - assign channel_flags_c60_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c60_field1_we = addr_hit[604] & reg_we & !reg_error; - assign channel_flags_c60_field1_wd = reg_wdata[31:1]; - - assign length_c60_we = addr_hit[605] & reg_we & !reg_error; - assign length_c60_wd = reg_wdata[31:0]; - - assign message_header_c60_message_id_we = addr_hit[606] & reg_we & !reg_error; - assign message_header_c60_message_id_wd = reg_wdata[7:0]; - - assign message_header_c60_message_type_we = addr_hit[606] & reg_we & !reg_error; - assign message_header_c60_message_type_wd = reg_wdata[9:8]; - - assign message_header_c60_protocol_id_we = addr_hit[606] & reg_we & !reg_error; - assign message_header_c60_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c60_token_we = addr_hit[606] & reg_we & !reg_error; - assign message_header_c60_token_wd = reg_wdata[27:18]; - - assign message_header_c60_field1_we = addr_hit[606] & reg_we & !reg_error; - assign message_header_c60_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c60_we = addr_hit[607] & reg_we & !reg_error; - assign message_payload_1_c60_wd = reg_wdata[31:0]; - - assign doorbell_c60_intr_we = addr_hit[608] & reg_we & !reg_error; - assign doorbell_c60_intr_wd = reg_wdata[0]; - - assign doorbell_c60_preserve_mask_we = addr_hit[608] & reg_we & !reg_error; - assign doorbell_c60_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c60_intr_we = addr_hit[609] & reg_we & !reg_error; - assign completion_interrupt_c60_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c60_preserve_mask_we = addr_hit[609] & reg_we & !reg_error; - assign completion_interrupt_c60_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c61_we = addr_hit[610] & reg_we & !reg_error; - assign reserved_1_c61_wd = reg_wdata[31:0]; - - assign channel_status_c61_channel_free_we = addr_hit[611] & reg_we & !reg_error; - assign channel_status_c61_channel_free_wd = reg_wdata[0]; - - assign channel_status_c61_channel_error_we = addr_hit[611] & reg_we & !reg_error; - assign channel_status_c61_channel_error_wd = reg_wdata[1]; - - assign channel_status_c61_field1_we = addr_hit[611] & reg_we & !reg_error; - assign channel_status_c61_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c61_we = addr_hit[612] & reg_we & !reg_error; - assign reserved_2_c61_wd = reg_wdata[31:0]; - - assign channel_flags_c61_intr_enable_we = addr_hit[614] & reg_we & !reg_error; - assign channel_flags_c61_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c61_field1_we = addr_hit[614] & reg_we & !reg_error; - assign channel_flags_c61_field1_wd = reg_wdata[31:1]; - - assign length_c61_we = addr_hit[615] & reg_we & !reg_error; - assign length_c61_wd = reg_wdata[31:0]; - - assign message_header_c61_message_id_we = addr_hit[616] & reg_we & !reg_error; - assign message_header_c61_message_id_wd = reg_wdata[7:0]; - - assign message_header_c61_message_type_we = addr_hit[616] & reg_we & !reg_error; - assign message_header_c61_message_type_wd = reg_wdata[9:8]; - - assign message_header_c61_protocol_id_we = addr_hit[616] & reg_we & !reg_error; - assign message_header_c61_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c61_token_we = addr_hit[616] & reg_we & !reg_error; - assign message_header_c61_token_wd = reg_wdata[27:18]; - - assign message_header_c61_field1_we = addr_hit[616] & reg_we & !reg_error; - assign message_header_c61_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c61_we = addr_hit[617] & reg_we & !reg_error; - assign message_payload_1_c61_wd = reg_wdata[31:0]; - - assign doorbell_c61_intr_we = addr_hit[618] & reg_we & !reg_error; - assign doorbell_c61_intr_wd = reg_wdata[0]; - - assign doorbell_c61_preserve_mask_we = addr_hit[618] & reg_we & !reg_error; - assign doorbell_c61_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c61_intr_we = addr_hit[619] & reg_we & !reg_error; - assign completion_interrupt_c61_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c61_preserve_mask_we = addr_hit[619] & reg_we & !reg_error; - assign completion_interrupt_c61_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c62_we = addr_hit[620] & reg_we & !reg_error; - assign reserved_1_c62_wd = reg_wdata[31:0]; - - assign channel_status_c62_channel_free_we = addr_hit[621] & reg_we & !reg_error; - assign channel_status_c62_channel_free_wd = reg_wdata[0]; - - assign channel_status_c62_channel_error_we = addr_hit[621] & reg_we & !reg_error; - assign channel_status_c62_channel_error_wd = reg_wdata[1]; - - assign channel_status_c62_field1_we = addr_hit[621] & reg_we & !reg_error; - assign channel_status_c62_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c62_we = addr_hit[622] & reg_we & !reg_error; - assign reserved_2_c62_wd = reg_wdata[31:0]; - - assign channel_flags_c62_intr_enable_we = addr_hit[624] & reg_we & !reg_error; - assign channel_flags_c62_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c62_field1_we = addr_hit[624] & reg_we & !reg_error; - assign channel_flags_c62_field1_wd = reg_wdata[31:1]; - - assign length_c62_we = addr_hit[625] & reg_we & !reg_error; - assign length_c62_wd = reg_wdata[31:0]; - - assign message_header_c62_message_id_we = addr_hit[626] & reg_we & !reg_error; - assign message_header_c62_message_id_wd = reg_wdata[7:0]; - - assign message_header_c62_message_type_we = addr_hit[626] & reg_we & !reg_error; - assign message_header_c62_message_type_wd = reg_wdata[9:8]; - - assign message_header_c62_protocol_id_we = addr_hit[626] & reg_we & !reg_error; - assign message_header_c62_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c62_token_we = addr_hit[626] & reg_we & !reg_error; - assign message_header_c62_token_wd = reg_wdata[27:18]; - - assign message_header_c62_field1_we = addr_hit[626] & reg_we & !reg_error; - assign message_header_c62_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c62_we = addr_hit[627] & reg_we & !reg_error; - assign message_payload_1_c62_wd = reg_wdata[31:0]; - - assign doorbell_c62_intr_we = addr_hit[628] & reg_we & !reg_error; - assign doorbell_c62_intr_wd = reg_wdata[0]; - - assign doorbell_c62_preserve_mask_we = addr_hit[628] & reg_we & !reg_error; - assign doorbell_c62_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c62_intr_we = addr_hit[629] & reg_we & !reg_error; - assign completion_interrupt_c62_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c62_preserve_mask_we = addr_hit[629] & reg_we & !reg_error; - assign completion_interrupt_c62_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c63_we = addr_hit[630] & reg_we & !reg_error; - assign reserved_1_c63_wd = reg_wdata[31:0]; - - assign channel_status_c63_channel_free_we = addr_hit[631] & reg_we & !reg_error; - assign channel_status_c63_channel_free_wd = reg_wdata[0]; - - assign channel_status_c63_channel_error_we = addr_hit[631] & reg_we & !reg_error; - assign channel_status_c63_channel_error_wd = reg_wdata[1]; - - assign channel_status_c63_field1_we = addr_hit[631] & reg_we & !reg_error; - assign channel_status_c63_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c63_we = addr_hit[632] & reg_we & !reg_error; - assign reserved_2_c63_wd = reg_wdata[31:0]; - - assign channel_flags_c63_intr_enable_we = addr_hit[634] & reg_we & !reg_error; - assign channel_flags_c63_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c63_field1_we = addr_hit[634] & reg_we & !reg_error; - assign channel_flags_c63_field1_wd = reg_wdata[31:1]; - - assign length_c63_we = addr_hit[635] & reg_we & !reg_error; - assign length_c63_wd = reg_wdata[31:0]; - - assign message_header_c63_message_id_we = addr_hit[636] & reg_we & !reg_error; - assign message_header_c63_message_id_wd = reg_wdata[7:0]; - - assign message_header_c63_message_type_we = addr_hit[636] & reg_we & !reg_error; - assign message_header_c63_message_type_wd = reg_wdata[9:8]; - - assign message_header_c63_protocol_id_we = addr_hit[636] & reg_we & !reg_error; - assign message_header_c63_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c63_token_we = addr_hit[636] & reg_we & !reg_error; - assign message_header_c63_token_wd = reg_wdata[27:18]; - - assign message_header_c63_field1_we = addr_hit[636] & reg_we & !reg_error; - assign message_header_c63_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c63_we = addr_hit[637] & reg_we & !reg_error; - assign message_payload_1_c63_wd = reg_wdata[31:0]; - - assign doorbell_c63_intr_we = addr_hit[638] & reg_we & !reg_error; - assign doorbell_c63_intr_wd = reg_wdata[0]; - - assign doorbell_c63_preserve_mask_we = addr_hit[638] & reg_we & !reg_error; - assign doorbell_c63_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c63_intr_we = addr_hit[639] & reg_we & !reg_error; - assign completion_interrupt_c63_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c63_preserve_mask_we = addr_hit[639] & reg_we & !reg_error; - assign completion_interrupt_c63_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c64_we = addr_hit[640] & reg_we & !reg_error; - assign reserved_1_c64_wd = reg_wdata[31:0]; - - assign channel_status_c64_channel_free_we = addr_hit[641] & reg_we & !reg_error; - assign channel_status_c64_channel_free_wd = reg_wdata[0]; - - assign channel_status_c64_channel_error_we = addr_hit[641] & reg_we & !reg_error; - assign channel_status_c64_channel_error_wd = reg_wdata[1]; - - assign channel_status_c64_field1_we = addr_hit[641] & reg_we & !reg_error; - assign channel_status_c64_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c64_we = addr_hit[642] & reg_we & !reg_error; - assign reserved_2_c64_wd = reg_wdata[31:0]; - - assign channel_flags_c64_intr_enable_we = addr_hit[644] & reg_we & !reg_error; - assign channel_flags_c64_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c64_field1_we = addr_hit[644] & reg_we & !reg_error; - assign channel_flags_c64_field1_wd = reg_wdata[31:1]; - - assign length_c64_we = addr_hit[645] & reg_we & !reg_error; - assign length_c64_wd = reg_wdata[31:0]; - - assign message_header_c64_message_id_we = addr_hit[646] & reg_we & !reg_error; - assign message_header_c64_message_id_wd = reg_wdata[7:0]; - - assign message_header_c64_message_type_we = addr_hit[646] & reg_we & !reg_error; - assign message_header_c64_message_type_wd = reg_wdata[9:8]; - - assign message_header_c64_protocol_id_we = addr_hit[646] & reg_we & !reg_error; - assign message_header_c64_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c64_token_we = addr_hit[646] & reg_we & !reg_error; - assign message_header_c64_token_wd = reg_wdata[27:18]; - - assign message_header_c64_field1_we = addr_hit[646] & reg_we & !reg_error; - assign message_header_c64_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c64_we = addr_hit[647] & reg_we & !reg_error; - assign message_payload_1_c64_wd = reg_wdata[31:0]; - - assign doorbell_c64_intr_we = addr_hit[648] & reg_we & !reg_error; - assign doorbell_c64_intr_wd = reg_wdata[0]; - - assign doorbell_c64_preserve_mask_we = addr_hit[648] & reg_we & !reg_error; - assign doorbell_c64_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c64_intr_we = addr_hit[649] & reg_we & !reg_error; - assign completion_interrupt_c64_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c64_preserve_mask_we = addr_hit[649] & reg_we & !reg_error; - assign completion_interrupt_c64_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c65_we = addr_hit[650] & reg_we & !reg_error; - assign reserved_1_c65_wd = reg_wdata[31:0]; - - assign channel_status_c65_channel_free_we = addr_hit[651] & reg_we & !reg_error; - assign channel_status_c65_channel_free_wd = reg_wdata[0]; - - assign channel_status_c65_channel_error_we = addr_hit[651] & reg_we & !reg_error; - assign channel_status_c65_channel_error_wd = reg_wdata[1]; - - assign channel_status_c65_field1_we = addr_hit[651] & reg_we & !reg_error; - assign channel_status_c65_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c65_we = addr_hit[652] & reg_we & !reg_error; - assign reserved_2_c65_wd = reg_wdata[31:0]; - - assign channel_flags_c65_intr_enable_we = addr_hit[654] & reg_we & !reg_error; - assign channel_flags_c65_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c65_field1_we = addr_hit[654] & reg_we & !reg_error; - assign channel_flags_c65_field1_wd = reg_wdata[31:1]; - - assign length_c65_we = addr_hit[655] & reg_we & !reg_error; - assign length_c65_wd = reg_wdata[31:0]; - - assign message_header_c65_message_id_we = addr_hit[656] & reg_we & !reg_error; - assign message_header_c65_message_id_wd = reg_wdata[7:0]; - - assign message_header_c65_message_type_we = addr_hit[656] & reg_we & !reg_error; - assign message_header_c65_message_type_wd = reg_wdata[9:8]; - - assign message_header_c65_protocol_id_we = addr_hit[656] & reg_we & !reg_error; - assign message_header_c65_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c65_token_we = addr_hit[656] & reg_we & !reg_error; - assign message_header_c65_token_wd = reg_wdata[27:18]; - - assign message_header_c65_field1_we = addr_hit[656] & reg_we & !reg_error; - assign message_header_c65_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c65_we = addr_hit[657] & reg_we & !reg_error; - assign message_payload_1_c65_wd = reg_wdata[31:0]; - - assign doorbell_c65_intr_we = addr_hit[658] & reg_we & !reg_error; - assign doorbell_c65_intr_wd = reg_wdata[0]; - - assign doorbell_c65_preserve_mask_we = addr_hit[658] & reg_we & !reg_error; - assign doorbell_c65_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c65_intr_we = addr_hit[659] & reg_we & !reg_error; - assign completion_interrupt_c65_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c65_preserve_mask_we = addr_hit[659] & reg_we & !reg_error; - assign completion_interrupt_c65_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c66_we = addr_hit[660] & reg_we & !reg_error; - assign reserved_1_c66_wd = reg_wdata[31:0]; - - assign channel_status_c66_channel_free_we = addr_hit[661] & reg_we & !reg_error; - assign channel_status_c66_channel_free_wd = reg_wdata[0]; - - assign channel_status_c66_channel_error_we = addr_hit[661] & reg_we & !reg_error; - assign channel_status_c66_channel_error_wd = reg_wdata[1]; - - assign channel_status_c66_field1_we = addr_hit[661] & reg_we & !reg_error; - assign channel_status_c66_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c66_we = addr_hit[662] & reg_we & !reg_error; - assign reserved_2_c66_wd = reg_wdata[31:0]; - - assign channel_flags_c66_intr_enable_we = addr_hit[664] & reg_we & !reg_error; - assign channel_flags_c66_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c66_field1_we = addr_hit[664] & reg_we & !reg_error; - assign channel_flags_c66_field1_wd = reg_wdata[31:1]; - - assign length_c66_we = addr_hit[665] & reg_we & !reg_error; - assign length_c66_wd = reg_wdata[31:0]; - - assign message_header_c66_message_id_we = addr_hit[666] & reg_we & !reg_error; - assign message_header_c66_message_id_wd = reg_wdata[7:0]; - - assign message_header_c66_message_type_we = addr_hit[666] & reg_we & !reg_error; - assign message_header_c66_message_type_wd = reg_wdata[9:8]; - - assign message_header_c66_protocol_id_we = addr_hit[666] & reg_we & !reg_error; - assign message_header_c66_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c66_token_we = addr_hit[666] & reg_we & !reg_error; - assign message_header_c66_token_wd = reg_wdata[27:18]; - - assign message_header_c66_field1_we = addr_hit[666] & reg_we & !reg_error; - assign message_header_c66_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c66_we = addr_hit[667] & reg_we & !reg_error; - assign message_payload_1_c66_wd = reg_wdata[31:0]; - - assign doorbell_c66_intr_we = addr_hit[668] & reg_we & !reg_error; - assign doorbell_c66_intr_wd = reg_wdata[0]; - - assign doorbell_c66_preserve_mask_we = addr_hit[668] & reg_we & !reg_error; - assign doorbell_c66_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c66_intr_we = addr_hit[669] & reg_we & !reg_error; - assign completion_interrupt_c66_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c66_preserve_mask_we = addr_hit[669] & reg_we & !reg_error; - assign completion_interrupt_c66_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c67_we = addr_hit[670] & reg_we & !reg_error; - assign reserved_1_c67_wd = reg_wdata[31:0]; - - assign channel_status_c67_channel_free_we = addr_hit[671] & reg_we & !reg_error; - assign channel_status_c67_channel_free_wd = reg_wdata[0]; - - assign channel_status_c67_channel_error_we = addr_hit[671] & reg_we & !reg_error; - assign channel_status_c67_channel_error_wd = reg_wdata[1]; - - assign channel_status_c67_field1_we = addr_hit[671] & reg_we & !reg_error; - assign channel_status_c67_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c67_we = addr_hit[672] & reg_we & !reg_error; - assign reserved_2_c67_wd = reg_wdata[31:0]; - - assign channel_flags_c67_intr_enable_we = addr_hit[674] & reg_we & !reg_error; - assign channel_flags_c67_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c67_field1_we = addr_hit[674] & reg_we & !reg_error; - assign channel_flags_c67_field1_wd = reg_wdata[31:1]; - - assign length_c67_we = addr_hit[675] & reg_we & !reg_error; - assign length_c67_wd = reg_wdata[31:0]; - - assign message_header_c67_message_id_we = addr_hit[676] & reg_we & !reg_error; - assign message_header_c67_message_id_wd = reg_wdata[7:0]; - - assign message_header_c67_message_type_we = addr_hit[676] & reg_we & !reg_error; - assign message_header_c67_message_type_wd = reg_wdata[9:8]; - - assign message_header_c67_protocol_id_we = addr_hit[676] & reg_we & !reg_error; - assign message_header_c67_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c67_token_we = addr_hit[676] & reg_we & !reg_error; - assign message_header_c67_token_wd = reg_wdata[27:18]; - - assign message_header_c67_field1_we = addr_hit[676] & reg_we & !reg_error; - assign message_header_c67_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c67_we = addr_hit[677] & reg_we & !reg_error; - assign message_payload_1_c67_wd = reg_wdata[31:0]; - - assign doorbell_c67_intr_we = addr_hit[678] & reg_we & !reg_error; - assign doorbell_c67_intr_wd = reg_wdata[0]; - - assign doorbell_c67_preserve_mask_we = addr_hit[678] & reg_we & !reg_error; - assign doorbell_c67_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c67_intr_we = addr_hit[679] & reg_we & !reg_error; - assign completion_interrupt_c67_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c67_preserve_mask_we = addr_hit[679] & reg_we & !reg_error; - assign completion_interrupt_c67_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c68_we = addr_hit[680] & reg_we & !reg_error; - assign reserved_1_c68_wd = reg_wdata[31:0]; - - assign channel_status_c68_channel_free_we = addr_hit[681] & reg_we & !reg_error; - assign channel_status_c68_channel_free_wd = reg_wdata[0]; - - assign channel_status_c68_channel_error_we = addr_hit[681] & reg_we & !reg_error; - assign channel_status_c68_channel_error_wd = reg_wdata[1]; - - assign channel_status_c68_field1_we = addr_hit[681] & reg_we & !reg_error; - assign channel_status_c68_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c68_we = addr_hit[682] & reg_we & !reg_error; - assign reserved_2_c68_wd = reg_wdata[31:0]; - - assign channel_flags_c68_intr_enable_we = addr_hit[684] & reg_we & !reg_error; - assign channel_flags_c68_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c68_field1_we = addr_hit[684] & reg_we & !reg_error; - assign channel_flags_c68_field1_wd = reg_wdata[31:1]; - - assign length_c68_we = addr_hit[685] & reg_we & !reg_error; - assign length_c68_wd = reg_wdata[31:0]; - - assign message_header_c68_message_id_we = addr_hit[686] & reg_we & !reg_error; - assign message_header_c68_message_id_wd = reg_wdata[7:0]; - - assign message_header_c68_message_type_we = addr_hit[686] & reg_we & !reg_error; - assign message_header_c68_message_type_wd = reg_wdata[9:8]; - - assign message_header_c68_protocol_id_we = addr_hit[686] & reg_we & !reg_error; - assign message_header_c68_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c68_token_we = addr_hit[686] & reg_we & !reg_error; - assign message_header_c68_token_wd = reg_wdata[27:18]; - - assign message_header_c68_field1_we = addr_hit[686] & reg_we & !reg_error; - assign message_header_c68_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c68_we = addr_hit[687] & reg_we & !reg_error; - assign message_payload_1_c68_wd = reg_wdata[31:0]; - - assign doorbell_c68_intr_we = addr_hit[688] & reg_we & !reg_error; - assign doorbell_c68_intr_wd = reg_wdata[0]; - - assign doorbell_c68_preserve_mask_we = addr_hit[688] & reg_we & !reg_error; - assign doorbell_c68_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c68_intr_we = addr_hit[689] & reg_we & !reg_error; - assign completion_interrupt_c68_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c68_preserve_mask_we = addr_hit[689] & reg_we & !reg_error; - assign completion_interrupt_c68_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c69_we = addr_hit[690] & reg_we & !reg_error; - assign reserved_1_c69_wd = reg_wdata[31:0]; - - assign channel_status_c69_channel_free_we = addr_hit[691] & reg_we & !reg_error; - assign channel_status_c69_channel_free_wd = reg_wdata[0]; - - assign channel_status_c69_channel_error_we = addr_hit[691] & reg_we & !reg_error; - assign channel_status_c69_channel_error_wd = reg_wdata[1]; - - assign channel_status_c69_field1_we = addr_hit[691] & reg_we & !reg_error; - assign channel_status_c69_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c69_we = addr_hit[692] & reg_we & !reg_error; - assign reserved_2_c69_wd = reg_wdata[31:0]; - - assign channel_flags_c69_intr_enable_we = addr_hit[694] & reg_we & !reg_error; - assign channel_flags_c69_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c69_field1_we = addr_hit[694] & reg_we & !reg_error; - assign channel_flags_c69_field1_wd = reg_wdata[31:1]; - - assign length_c69_we = addr_hit[695] & reg_we & !reg_error; - assign length_c69_wd = reg_wdata[31:0]; - - assign message_header_c69_message_id_we = addr_hit[696] & reg_we & !reg_error; - assign message_header_c69_message_id_wd = reg_wdata[7:0]; - - assign message_header_c69_message_type_we = addr_hit[696] & reg_we & !reg_error; - assign message_header_c69_message_type_wd = reg_wdata[9:8]; - - assign message_header_c69_protocol_id_we = addr_hit[696] & reg_we & !reg_error; - assign message_header_c69_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c69_token_we = addr_hit[696] & reg_we & !reg_error; - assign message_header_c69_token_wd = reg_wdata[27:18]; - - assign message_header_c69_field1_we = addr_hit[696] & reg_we & !reg_error; - assign message_header_c69_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c69_we = addr_hit[697] & reg_we & !reg_error; - assign message_payload_1_c69_wd = reg_wdata[31:0]; - - assign doorbell_c69_intr_we = addr_hit[698] & reg_we & !reg_error; - assign doorbell_c69_intr_wd = reg_wdata[0]; - - assign doorbell_c69_preserve_mask_we = addr_hit[698] & reg_we & !reg_error; - assign doorbell_c69_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c69_intr_we = addr_hit[699] & reg_we & !reg_error; - assign completion_interrupt_c69_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c69_preserve_mask_we = addr_hit[699] & reg_we & !reg_error; - assign completion_interrupt_c69_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c70_we = addr_hit[700] & reg_we & !reg_error; - assign reserved_1_c70_wd = reg_wdata[31:0]; - - assign channel_status_c70_channel_free_we = addr_hit[701] & reg_we & !reg_error; - assign channel_status_c70_channel_free_wd = reg_wdata[0]; - - assign channel_status_c70_channel_error_we = addr_hit[701] & reg_we & !reg_error; - assign channel_status_c70_channel_error_wd = reg_wdata[1]; - - assign channel_status_c70_field1_we = addr_hit[701] & reg_we & !reg_error; - assign channel_status_c70_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c70_we = addr_hit[702] & reg_we & !reg_error; - assign reserved_2_c70_wd = reg_wdata[31:0]; - - assign channel_flags_c70_intr_enable_we = addr_hit[704] & reg_we & !reg_error; - assign channel_flags_c70_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c70_field1_we = addr_hit[704] & reg_we & !reg_error; - assign channel_flags_c70_field1_wd = reg_wdata[31:1]; - - assign length_c70_we = addr_hit[705] & reg_we & !reg_error; - assign length_c70_wd = reg_wdata[31:0]; - - assign message_header_c70_message_id_we = addr_hit[706] & reg_we & !reg_error; - assign message_header_c70_message_id_wd = reg_wdata[7:0]; - - assign message_header_c70_message_type_we = addr_hit[706] & reg_we & !reg_error; - assign message_header_c70_message_type_wd = reg_wdata[9:8]; - - assign message_header_c70_protocol_id_we = addr_hit[706] & reg_we & !reg_error; - assign message_header_c70_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c70_token_we = addr_hit[706] & reg_we & !reg_error; - assign message_header_c70_token_wd = reg_wdata[27:18]; - - assign message_header_c70_field1_we = addr_hit[706] & reg_we & !reg_error; - assign message_header_c70_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c70_we = addr_hit[707] & reg_we & !reg_error; - assign message_payload_1_c70_wd = reg_wdata[31:0]; - - assign doorbell_c70_intr_we = addr_hit[708] & reg_we & !reg_error; - assign doorbell_c70_intr_wd = reg_wdata[0]; - - assign doorbell_c70_preserve_mask_we = addr_hit[708] & reg_we & !reg_error; - assign doorbell_c70_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c70_intr_we = addr_hit[709] & reg_we & !reg_error; - assign completion_interrupt_c70_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c70_preserve_mask_we = addr_hit[709] & reg_we & !reg_error; - assign completion_interrupt_c70_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c71_we = addr_hit[710] & reg_we & !reg_error; - assign reserved_1_c71_wd = reg_wdata[31:0]; - - assign channel_status_c71_channel_free_we = addr_hit[711] & reg_we & !reg_error; - assign channel_status_c71_channel_free_wd = reg_wdata[0]; - - assign channel_status_c71_channel_error_we = addr_hit[711] & reg_we & !reg_error; - assign channel_status_c71_channel_error_wd = reg_wdata[1]; - - assign channel_status_c71_field1_we = addr_hit[711] & reg_we & !reg_error; - assign channel_status_c71_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c71_we = addr_hit[712] & reg_we & !reg_error; - assign reserved_2_c71_wd = reg_wdata[31:0]; - - assign channel_flags_c71_intr_enable_we = addr_hit[714] & reg_we & !reg_error; - assign channel_flags_c71_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c71_field1_we = addr_hit[714] & reg_we & !reg_error; - assign channel_flags_c71_field1_wd = reg_wdata[31:1]; - - assign length_c71_we = addr_hit[715] & reg_we & !reg_error; - assign length_c71_wd = reg_wdata[31:0]; - - assign message_header_c71_message_id_we = addr_hit[716] & reg_we & !reg_error; - assign message_header_c71_message_id_wd = reg_wdata[7:0]; - - assign message_header_c71_message_type_we = addr_hit[716] & reg_we & !reg_error; - assign message_header_c71_message_type_wd = reg_wdata[9:8]; - - assign message_header_c71_protocol_id_we = addr_hit[716] & reg_we & !reg_error; - assign message_header_c71_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c71_token_we = addr_hit[716] & reg_we & !reg_error; - assign message_header_c71_token_wd = reg_wdata[27:18]; - - assign message_header_c71_field1_we = addr_hit[716] & reg_we & !reg_error; - assign message_header_c71_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c71_we = addr_hit[717] & reg_we & !reg_error; - assign message_payload_1_c71_wd = reg_wdata[31:0]; - - assign doorbell_c71_intr_we = addr_hit[718] & reg_we & !reg_error; - assign doorbell_c71_intr_wd = reg_wdata[0]; - - assign doorbell_c71_preserve_mask_we = addr_hit[718] & reg_we & !reg_error; - assign doorbell_c71_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c71_intr_we = addr_hit[719] & reg_we & !reg_error; - assign completion_interrupt_c71_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c71_preserve_mask_we = addr_hit[719] & reg_we & !reg_error; - assign completion_interrupt_c71_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c72_we = addr_hit[720] & reg_we & !reg_error; - assign reserved_1_c72_wd = reg_wdata[31:0]; - - assign channel_status_c72_channel_free_we = addr_hit[721] & reg_we & !reg_error; - assign channel_status_c72_channel_free_wd = reg_wdata[0]; - - assign channel_status_c72_channel_error_we = addr_hit[721] & reg_we & !reg_error; - assign channel_status_c72_channel_error_wd = reg_wdata[1]; - - assign channel_status_c72_field1_we = addr_hit[721] & reg_we & !reg_error; - assign channel_status_c72_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c72_we = addr_hit[722] & reg_we & !reg_error; - assign reserved_2_c72_wd = reg_wdata[31:0]; - - assign channel_flags_c72_intr_enable_we = addr_hit[724] & reg_we & !reg_error; - assign channel_flags_c72_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c72_field1_we = addr_hit[724] & reg_we & !reg_error; - assign channel_flags_c72_field1_wd = reg_wdata[31:1]; - - assign length_c72_we = addr_hit[725] & reg_we & !reg_error; - assign length_c72_wd = reg_wdata[31:0]; - - assign message_header_c72_message_id_we = addr_hit[726] & reg_we & !reg_error; - assign message_header_c72_message_id_wd = reg_wdata[7:0]; - - assign message_header_c72_message_type_we = addr_hit[726] & reg_we & !reg_error; - assign message_header_c72_message_type_wd = reg_wdata[9:8]; - - assign message_header_c72_protocol_id_we = addr_hit[726] & reg_we & !reg_error; - assign message_header_c72_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c72_token_we = addr_hit[726] & reg_we & !reg_error; - assign message_header_c72_token_wd = reg_wdata[27:18]; - - assign message_header_c72_field1_we = addr_hit[726] & reg_we & !reg_error; - assign message_header_c72_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c72_we = addr_hit[727] & reg_we & !reg_error; - assign message_payload_1_c72_wd = reg_wdata[31:0]; - - assign doorbell_c72_intr_we = addr_hit[728] & reg_we & !reg_error; - assign doorbell_c72_intr_wd = reg_wdata[0]; - - assign doorbell_c72_preserve_mask_we = addr_hit[728] & reg_we & !reg_error; - assign doorbell_c72_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c72_intr_we = addr_hit[729] & reg_we & !reg_error; - assign completion_interrupt_c72_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c72_preserve_mask_we = addr_hit[729] & reg_we & !reg_error; - assign completion_interrupt_c72_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c73_we = addr_hit[730] & reg_we & !reg_error; - assign reserved_1_c73_wd = reg_wdata[31:0]; - - assign channel_status_c73_channel_free_we = addr_hit[731] & reg_we & !reg_error; - assign channel_status_c73_channel_free_wd = reg_wdata[0]; - - assign channel_status_c73_channel_error_we = addr_hit[731] & reg_we & !reg_error; - assign channel_status_c73_channel_error_wd = reg_wdata[1]; - - assign channel_status_c73_field1_we = addr_hit[731] & reg_we & !reg_error; - assign channel_status_c73_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c73_we = addr_hit[732] & reg_we & !reg_error; - assign reserved_2_c73_wd = reg_wdata[31:0]; - - assign channel_flags_c73_intr_enable_we = addr_hit[734] & reg_we & !reg_error; - assign channel_flags_c73_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c73_field1_we = addr_hit[734] & reg_we & !reg_error; - assign channel_flags_c73_field1_wd = reg_wdata[31:1]; - - assign length_c73_we = addr_hit[735] & reg_we & !reg_error; - assign length_c73_wd = reg_wdata[31:0]; - - assign message_header_c73_message_id_we = addr_hit[736] & reg_we & !reg_error; - assign message_header_c73_message_id_wd = reg_wdata[7:0]; - - assign message_header_c73_message_type_we = addr_hit[736] & reg_we & !reg_error; - assign message_header_c73_message_type_wd = reg_wdata[9:8]; - - assign message_header_c73_protocol_id_we = addr_hit[736] & reg_we & !reg_error; - assign message_header_c73_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c73_token_we = addr_hit[736] & reg_we & !reg_error; - assign message_header_c73_token_wd = reg_wdata[27:18]; - - assign message_header_c73_field1_we = addr_hit[736] & reg_we & !reg_error; - assign message_header_c73_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c73_we = addr_hit[737] & reg_we & !reg_error; - assign message_payload_1_c73_wd = reg_wdata[31:0]; - - assign doorbell_c73_intr_we = addr_hit[738] & reg_we & !reg_error; - assign doorbell_c73_intr_wd = reg_wdata[0]; - - assign doorbell_c73_preserve_mask_we = addr_hit[738] & reg_we & !reg_error; - assign doorbell_c73_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c73_intr_we = addr_hit[739] & reg_we & !reg_error; - assign completion_interrupt_c73_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c73_preserve_mask_we = addr_hit[739] & reg_we & !reg_error; - assign completion_interrupt_c73_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c74_we = addr_hit[740] & reg_we & !reg_error; - assign reserved_1_c74_wd = reg_wdata[31:0]; - - assign channel_status_c74_channel_free_we = addr_hit[741] & reg_we & !reg_error; - assign channel_status_c74_channel_free_wd = reg_wdata[0]; - - assign channel_status_c74_channel_error_we = addr_hit[741] & reg_we & !reg_error; - assign channel_status_c74_channel_error_wd = reg_wdata[1]; - - assign channel_status_c74_field1_we = addr_hit[741] & reg_we & !reg_error; - assign channel_status_c74_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c74_we = addr_hit[742] & reg_we & !reg_error; - assign reserved_2_c74_wd = reg_wdata[31:0]; - - assign channel_flags_c74_intr_enable_we = addr_hit[744] & reg_we & !reg_error; - assign channel_flags_c74_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c74_field1_we = addr_hit[744] & reg_we & !reg_error; - assign channel_flags_c74_field1_wd = reg_wdata[31:1]; - - assign length_c74_we = addr_hit[745] & reg_we & !reg_error; - assign length_c74_wd = reg_wdata[31:0]; - - assign message_header_c74_message_id_we = addr_hit[746] & reg_we & !reg_error; - assign message_header_c74_message_id_wd = reg_wdata[7:0]; - - assign message_header_c74_message_type_we = addr_hit[746] & reg_we & !reg_error; - assign message_header_c74_message_type_wd = reg_wdata[9:8]; - - assign message_header_c74_protocol_id_we = addr_hit[746] & reg_we & !reg_error; - assign message_header_c74_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c74_token_we = addr_hit[746] & reg_we & !reg_error; - assign message_header_c74_token_wd = reg_wdata[27:18]; - - assign message_header_c74_field1_we = addr_hit[746] & reg_we & !reg_error; - assign message_header_c74_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c74_we = addr_hit[747] & reg_we & !reg_error; - assign message_payload_1_c74_wd = reg_wdata[31:0]; - - assign doorbell_c74_intr_we = addr_hit[748] & reg_we & !reg_error; - assign doorbell_c74_intr_wd = reg_wdata[0]; - - assign doorbell_c74_preserve_mask_we = addr_hit[748] & reg_we & !reg_error; - assign doorbell_c74_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c74_intr_we = addr_hit[749] & reg_we & !reg_error; - assign completion_interrupt_c74_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c74_preserve_mask_we = addr_hit[749] & reg_we & !reg_error; - assign completion_interrupt_c74_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c75_we = addr_hit[750] & reg_we & !reg_error; - assign reserved_1_c75_wd = reg_wdata[31:0]; - - assign channel_status_c75_channel_free_we = addr_hit[751] & reg_we & !reg_error; - assign channel_status_c75_channel_free_wd = reg_wdata[0]; - - assign channel_status_c75_channel_error_we = addr_hit[751] & reg_we & !reg_error; - assign channel_status_c75_channel_error_wd = reg_wdata[1]; - - assign channel_status_c75_field1_we = addr_hit[751] & reg_we & !reg_error; - assign channel_status_c75_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c75_we = addr_hit[752] & reg_we & !reg_error; - assign reserved_2_c75_wd = reg_wdata[31:0]; - - assign channel_flags_c75_intr_enable_we = addr_hit[754] & reg_we & !reg_error; - assign channel_flags_c75_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c75_field1_we = addr_hit[754] & reg_we & !reg_error; - assign channel_flags_c75_field1_wd = reg_wdata[31:1]; - - assign length_c75_we = addr_hit[755] & reg_we & !reg_error; - assign length_c75_wd = reg_wdata[31:0]; - - assign message_header_c75_message_id_we = addr_hit[756] & reg_we & !reg_error; - assign message_header_c75_message_id_wd = reg_wdata[7:0]; - - assign message_header_c75_message_type_we = addr_hit[756] & reg_we & !reg_error; - assign message_header_c75_message_type_wd = reg_wdata[9:8]; - - assign message_header_c75_protocol_id_we = addr_hit[756] & reg_we & !reg_error; - assign message_header_c75_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c75_token_we = addr_hit[756] & reg_we & !reg_error; - assign message_header_c75_token_wd = reg_wdata[27:18]; - - assign message_header_c75_field1_we = addr_hit[756] & reg_we & !reg_error; - assign message_header_c75_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c75_we = addr_hit[757] & reg_we & !reg_error; - assign message_payload_1_c75_wd = reg_wdata[31:0]; - - assign doorbell_c75_intr_we = addr_hit[758] & reg_we & !reg_error; - assign doorbell_c75_intr_wd = reg_wdata[0]; - - assign doorbell_c75_preserve_mask_we = addr_hit[758] & reg_we & !reg_error; - assign doorbell_c75_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c75_intr_we = addr_hit[759] & reg_we & !reg_error; - assign completion_interrupt_c75_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c75_preserve_mask_we = addr_hit[759] & reg_we & !reg_error; - assign completion_interrupt_c75_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c76_we = addr_hit[760] & reg_we & !reg_error; - assign reserved_1_c76_wd = reg_wdata[31:0]; - - assign channel_status_c76_channel_free_we = addr_hit[761] & reg_we & !reg_error; - assign channel_status_c76_channel_free_wd = reg_wdata[0]; - - assign channel_status_c76_channel_error_we = addr_hit[761] & reg_we & !reg_error; - assign channel_status_c76_channel_error_wd = reg_wdata[1]; - - assign channel_status_c76_field1_we = addr_hit[761] & reg_we & !reg_error; - assign channel_status_c76_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c76_we = addr_hit[762] & reg_we & !reg_error; - assign reserved_2_c76_wd = reg_wdata[31:0]; - - assign channel_flags_c76_intr_enable_we = addr_hit[764] & reg_we & !reg_error; - assign channel_flags_c76_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c76_field1_we = addr_hit[764] & reg_we & !reg_error; - assign channel_flags_c76_field1_wd = reg_wdata[31:1]; - - assign length_c76_we = addr_hit[765] & reg_we & !reg_error; - assign length_c76_wd = reg_wdata[31:0]; - - assign message_header_c76_message_id_we = addr_hit[766] & reg_we & !reg_error; - assign message_header_c76_message_id_wd = reg_wdata[7:0]; - - assign message_header_c76_message_type_we = addr_hit[766] & reg_we & !reg_error; - assign message_header_c76_message_type_wd = reg_wdata[9:8]; - - assign message_header_c76_protocol_id_we = addr_hit[766] & reg_we & !reg_error; - assign message_header_c76_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c76_token_we = addr_hit[766] & reg_we & !reg_error; - assign message_header_c76_token_wd = reg_wdata[27:18]; - - assign message_header_c76_field1_we = addr_hit[766] & reg_we & !reg_error; - assign message_header_c76_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c76_we = addr_hit[767] & reg_we & !reg_error; - assign message_payload_1_c76_wd = reg_wdata[31:0]; - - assign doorbell_c76_intr_we = addr_hit[768] & reg_we & !reg_error; - assign doorbell_c76_intr_wd = reg_wdata[0]; - - assign doorbell_c76_preserve_mask_we = addr_hit[768] & reg_we & !reg_error; - assign doorbell_c76_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c76_intr_we = addr_hit[769] & reg_we & !reg_error; - assign completion_interrupt_c76_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c76_preserve_mask_we = addr_hit[769] & reg_we & !reg_error; - assign completion_interrupt_c76_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c77_we = addr_hit[770] & reg_we & !reg_error; - assign reserved_1_c77_wd = reg_wdata[31:0]; - - assign channel_status_c77_channel_free_we = addr_hit[771] & reg_we & !reg_error; - assign channel_status_c77_channel_free_wd = reg_wdata[0]; - - assign channel_status_c77_channel_error_we = addr_hit[771] & reg_we & !reg_error; - assign channel_status_c77_channel_error_wd = reg_wdata[1]; - - assign channel_status_c77_field1_we = addr_hit[771] & reg_we & !reg_error; - assign channel_status_c77_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c77_we = addr_hit[772] & reg_we & !reg_error; - assign reserved_2_c77_wd = reg_wdata[31:0]; - - assign channel_flags_c77_intr_enable_we = addr_hit[774] & reg_we & !reg_error; - assign channel_flags_c77_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c77_field1_we = addr_hit[774] & reg_we & !reg_error; - assign channel_flags_c77_field1_wd = reg_wdata[31:1]; - - assign length_c77_we = addr_hit[775] & reg_we & !reg_error; - assign length_c77_wd = reg_wdata[31:0]; - - assign message_header_c77_message_id_we = addr_hit[776] & reg_we & !reg_error; - assign message_header_c77_message_id_wd = reg_wdata[7:0]; - - assign message_header_c77_message_type_we = addr_hit[776] & reg_we & !reg_error; - assign message_header_c77_message_type_wd = reg_wdata[9:8]; - - assign message_header_c77_protocol_id_we = addr_hit[776] & reg_we & !reg_error; - assign message_header_c77_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c77_token_we = addr_hit[776] & reg_we & !reg_error; - assign message_header_c77_token_wd = reg_wdata[27:18]; - - assign message_header_c77_field1_we = addr_hit[776] & reg_we & !reg_error; - assign message_header_c77_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c77_we = addr_hit[777] & reg_we & !reg_error; - assign message_payload_1_c77_wd = reg_wdata[31:0]; - - assign doorbell_c77_intr_we = addr_hit[778] & reg_we & !reg_error; - assign doorbell_c77_intr_wd = reg_wdata[0]; - - assign doorbell_c77_preserve_mask_we = addr_hit[778] & reg_we & !reg_error; - assign doorbell_c77_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c77_intr_we = addr_hit[779] & reg_we & !reg_error; - assign completion_interrupt_c77_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c77_preserve_mask_we = addr_hit[779] & reg_we & !reg_error; - assign completion_interrupt_c77_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c78_we = addr_hit[780] & reg_we & !reg_error; - assign reserved_1_c78_wd = reg_wdata[31:0]; - - assign channel_status_c78_channel_free_we = addr_hit[781] & reg_we & !reg_error; - assign channel_status_c78_channel_free_wd = reg_wdata[0]; - - assign channel_status_c78_channel_error_we = addr_hit[781] & reg_we & !reg_error; - assign channel_status_c78_channel_error_wd = reg_wdata[1]; - - assign channel_status_c78_field1_we = addr_hit[781] & reg_we & !reg_error; - assign channel_status_c78_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c78_we = addr_hit[782] & reg_we & !reg_error; - assign reserved_2_c78_wd = reg_wdata[31:0]; - - assign channel_flags_c78_intr_enable_we = addr_hit[784] & reg_we & !reg_error; - assign channel_flags_c78_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c78_field1_we = addr_hit[784] & reg_we & !reg_error; - assign channel_flags_c78_field1_wd = reg_wdata[31:1]; - - assign length_c78_we = addr_hit[785] & reg_we & !reg_error; - assign length_c78_wd = reg_wdata[31:0]; - - assign message_header_c78_message_id_we = addr_hit[786] & reg_we & !reg_error; - assign message_header_c78_message_id_wd = reg_wdata[7:0]; - - assign message_header_c78_message_type_we = addr_hit[786] & reg_we & !reg_error; - assign message_header_c78_message_type_wd = reg_wdata[9:8]; - - assign message_header_c78_protocol_id_we = addr_hit[786] & reg_we & !reg_error; - assign message_header_c78_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c78_token_we = addr_hit[786] & reg_we & !reg_error; - assign message_header_c78_token_wd = reg_wdata[27:18]; - - assign message_header_c78_field1_we = addr_hit[786] & reg_we & !reg_error; - assign message_header_c78_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c78_we = addr_hit[787] & reg_we & !reg_error; - assign message_payload_1_c78_wd = reg_wdata[31:0]; - - assign doorbell_c78_intr_we = addr_hit[788] & reg_we & !reg_error; - assign doorbell_c78_intr_wd = reg_wdata[0]; - - assign doorbell_c78_preserve_mask_we = addr_hit[788] & reg_we & !reg_error; - assign doorbell_c78_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c78_intr_we = addr_hit[789] & reg_we & !reg_error; - assign completion_interrupt_c78_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c78_preserve_mask_we = addr_hit[789] & reg_we & !reg_error; - assign completion_interrupt_c78_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c79_we = addr_hit[790] & reg_we & !reg_error; - assign reserved_1_c79_wd = reg_wdata[31:0]; - - assign channel_status_c79_channel_free_we = addr_hit[791] & reg_we & !reg_error; - assign channel_status_c79_channel_free_wd = reg_wdata[0]; - - assign channel_status_c79_channel_error_we = addr_hit[791] & reg_we & !reg_error; - assign channel_status_c79_channel_error_wd = reg_wdata[1]; - - assign channel_status_c79_field1_we = addr_hit[791] & reg_we & !reg_error; - assign channel_status_c79_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c79_we = addr_hit[792] & reg_we & !reg_error; - assign reserved_2_c79_wd = reg_wdata[31:0]; - - assign channel_flags_c79_intr_enable_we = addr_hit[794] & reg_we & !reg_error; - assign channel_flags_c79_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c79_field1_we = addr_hit[794] & reg_we & !reg_error; - assign channel_flags_c79_field1_wd = reg_wdata[31:1]; - - assign length_c79_we = addr_hit[795] & reg_we & !reg_error; - assign length_c79_wd = reg_wdata[31:0]; - - assign message_header_c79_message_id_we = addr_hit[796] & reg_we & !reg_error; - assign message_header_c79_message_id_wd = reg_wdata[7:0]; - - assign message_header_c79_message_type_we = addr_hit[796] & reg_we & !reg_error; - assign message_header_c79_message_type_wd = reg_wdata[9:8]; - - assign message_header_c79_protocol_id_we = addr_hit[796] & reg_we & !reg_error; - assign message_header_c79_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c79_token_we = addr_hit[796] & reg_we & !reg_error; - assign message_header_c79_token_wd = reg_wdata[27:18]; - - assign message_header_c79_field1_we = addr_hit[796] & reg_we & !reg_error; - assign message_header_c79_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c79_we = addr_hit[797] & reg_we & !reg_error; - assign message_payload_1_c79_wd = reg_wdata[31:0]; - - assign doorbell_c79_intr_we = addr_hit[798] & reg_we & !reg_error; - assign doorbell_c79_intr_wd = reg_wdata[0]; - - assign doorbell_c79_preserve_mask_we = addr_hit[798] & reg_we & !reg_error; - assign doorbell_c79_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c79_intr_we = addr_hit[799] & reg_we & !reg_error; - assign completion_interrupt_c79_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c79_preserve_mask_we = addr_hit[799] & reg_we & !reg_error; - assign completion_interrupt_c79_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c80_we = addr_hit[800] & reg_we & !reg_error; - assign reserved_1_c80_wd = reg_wdata[31:0]; - - assign channel_status_c80_channel_free_we = addr_hit[801] & reg_we & !reg_error; - assign channel_status_c80_channel_free_wd = reg_wdata[0]; - - assign channel_status_c80_channel_error_we = addr_hit[801] & reg_we & !reg_error; - assign channel_status_c80_channel_error_wd = reg_wdata[1]; - - assign channel_status_c80_field1_we = addr_hit[801] & reg_we & !reg_error; - assign channel_status_c80_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c80_we = addr_hit[802] & reg_we & !reg_error; - assign reserved_2_c80_wd = reg_wdata[31:0]; - - assign channel_flags_c80_intr_enable_we = addr_hit[804] & reg_we & !reg_error; - assign channel_flags_c80_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c80_field1_we = addr_hit[804] & reg_we & !reg_error; - assign channel_flags_c80_field1_wd = reg_wdata[31:1]; - - assign length_c80_we = addr_hit[805] & reg_we & !reg_error; - assign length_c80_wd = reg_wdata[31:0]; - - assign message_header_c80_message_id_we = addr_hit[806] & reg_we & !reg_error; - assign message_header_c80_message_id_wd = reg_wdata[7:0]; - - assign message_header_c80_message_type_we = addr_hit[806] & reg_we & !reg_error; - assign message_header_c80_message_type_wd = reg_wdata[9:8]; - - assign message_header_c80_protocol_id_we = addr_hit[806] & reg_we & !reg_error; - assign message_header_c80_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c80_token_we = addr_hit[806] & reg_we & !reg_error; - assign message_header_c80_token_wd = reg_wdata[27:18]; - - assign message_header_c80_field1_we = addr_hit[806] & reg_we & !reg_error; - assign message_header_c80_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c80_we = addr_hit[807] & reg_we & !reg_error; - assign message_payload_1_c80_wd = reg_wdata[31:0]; - - assign doorbell_c80_intr_we = addr_hit[808] & reg_we & !reg_error; - assign doorbell_c80_intr_wd = reg_wdata[0]; - - assign doorbell_c80_preserve_mask_we = addr_hit[808] & reg_we & !reg_error; - assign doorbell_c80_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c80_intr_we = addr_hit[809] & reg_we & !reg_error; - assign completion_interrupt_c80_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c80_preserve_mask_we = addr_hit[809] & reg_we & !reg_error; - assign completion_interrupt_c80_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c81_we = addr_hit[810] & reg_we & !reg_error; - assign reserved_1_c81_wd = reg_wdata[31:0]; - - assign channel_status_c81_channel_free_we = addr_hit[811] & reg_we & !reg_error; - assign channel_status_c81_channel_free_wd = reg_wdata[0]; - - assign channel_status_c81_channel_error_we = addr_hit[811] & reg_we & !reg_error; - assign channel_status_c81_channel_error_wd = reg_wdata[1]; - - assign channel_status_c81_field1_we = addr_hit[811] & reg_we & !reg_error; - assign channel_status_c81_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c81_we = addr_hit[812] & reg_we & !reg_error; - assign reserved_2_c81_wd = reg_wdata[31:0]; - - assign channel_flags_c81_intr_enable_we = addr_hit[814] & reg_we & !reg_error; - assign channel_flags_c81_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c81_field1_we = addr_hit[814] & reg_we & !reg_error; - assign channel_flags_c81_field1_wd = reg_wdata[31:1]; - - assign length_c81_we = addr_hit[815] & reg_we & !reg_error; - assign length_c81_wd = reg_wdata[31:0]; - - assign message_header_c81_message_id_we = addr_hit[816] & reg_we & !reg_error; - assign message_header_c81_message_id_wd = reg_wdata[7:0]; - - assign message_header_c81_message_type_we = addr_hit[816] & reg_we & !reg_error; - assign message_header_c81_message_type_wd = reg_wdata[9:8]; - - assign message_header_c81_protocol_id_we = addr_hit[816] & reg_we & !reg_error; - assign message_header_c81_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c81_token_we = addr_hit[816] & reg_we & !reg_error; - assign message_header_c81_token_wd = reg_wdata[27:18]; - - assign message_header_c81_field1_we = addr_hit[816] & reg_we & !reg_error; - assign message_header_c81_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c81_we = addr_hit[817] & reg_we & !reg_error; - assign message_payload_1_c81_wd = reg_wdata[31:0]; - - assign doorbell_c81_intr_we = addr_hit[818] & reg_we & !reg_error; - assign doorbell_c81_intr_wd = reg_wdata[0]; - - assign doorbell_c81_preserve_mask_we = addr_hit[818] & reg_we & !reg_error; - assign doorbell_c81_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c81_intr_we = addr_hit[819] & reg_we & !reg_error; - assign completion_interrupt_c81_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c81_preserve_mask_we = addr_hit[819] & reg_we & !reg_error; - assign completion_interrupt_c81_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c82_we = addr_hit[820] & reg_we & !reg_error; - assign reserved_1_c82_wd = reg_wdata[31:0]; - - assign channel_status_c82_channel_free_we = addr_hit[821] & reg_we & !reg_error; - assign channel_status_c82_channel_free_wd = reg_wdata[0]; - - assign channel_status_c82_channel_error_we = addr_hit[821] & reg_we & !reg_error; - assign channel_status_c82_channel_error_wd = reg_wdata[1]; - - assign channel_status_c82_field1_we = addr_hit[821] & reg_we & !reg_error; - assign channel_status_c82_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c82_we = addr_hit[822] & reg_we & !reg_error; - assign reserved_2_c82_wd = reg_wdata[31:0]; - - assign channel_flags_c82_intr_enable_we = addr_hit[824] & reg_we & !reg_error; - assign channel_flags_c82_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c82_field1_we = addr_hit[824] & reg_we & !reg_error; - assign channel_flags_c82_field1_wd = reg_wdata[31:1]; - - assign length_c82_we = addr_hit[825] & reg_we & !reg_error; - assign length_c82_wd = reg_wdata[31:0]; - - assign message_header_c82_message_id_we = addr_hit[826] & reg_we & !reg_error; - assign message_header_c82_message_id_wd = reg_wdata[7:0]; - - assign message_header_c82_message_type_we = addr_hit[826] & reg_we & !reg_error; - assign message_header_c82_message_type_wd = reg_wdata[9:8]; - - assign message_header_c82_protocol_id_we = addr_hit[826] & reg_we & !reg_error; - assign message_header_c82_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c82_token_we = addr_hit[826] & reg_we & !reg_error; - assign message_header_c82_token_wd = reg_wdata[27:18]; - - assign message_header_c82_field1_we = addr_hit[826] & reg_we & !reg_error; - assign message_header_c82_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c82_we = addr_hit[827] & reg_we & !reg_error; - assign message_payload_1_c82_wd = reg_wdata[31:0]; - - assign doorbell_c82_intr_we = addr_hit[828] & reg_we & !reg_error; - assign doorbell_c82_intr_wd = reg_wdata[0]; - - assign doorbell_c82_preserve_mask_we = addr_hit[828] & reg_we & !reg_error; - assign doorbell_c82_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c82_intr_we = addr_hit[829] & reg_we & !reg_error; - assign completion_interrupt_c82_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c82_preserve_mask_we = addr_hit[829] & reg_we & !reg_error; - assign completion_interrupt_c82_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c83_we = addr_hit[830] & reg_we & !reg_error; - assign reserved_1_c83_wd = reg_wdata[31:0]; - - assign channel_status_c83_channel_free_we = addr_hit[831] & reg_we & !reg_error; - assign channel_status_c83_channel_free_wd = reg_wdata[0]; - - assign channel_status_c83_channel_error_we = addr_hit[831] & reg_we & !reg_error; - assign channel_status_c83_channel_error_wd = reg_wdata[1]; - - assign channel_status_c83_field1_we = addr_hit[831] & reg_we & !reg_error; - assign channel_status_c83_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c83_we = addr_hit[832] & reg_we & !reg_error; - assign reserved_2_c83_wd = reg_wdata[31:0]; - - assign channel_flags_c83_intr_enable_we = addr_hit[834] & reg_we & !reg_error; - assign channel_flags_c83_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c83_field1_we = addr_hit[834] & reg_we & !reg_error; - assign channel_flags_c83_field1_wd = reg_wdata[31:1]; - - assign length_c83_we = addr_hit[835] & reg_we & !reg_error; - assign length_c83_wd = reg_wdata[31:0]; - - assign message_header_c83_message_id_we = addr_hit[836] & reg_we & !reg_error; - assign message_header_c83_message_id_wd = reg_wdata[7:0]; - - assign message_header_c83_message_type_we = addr_hit[836] & reg_we & !reg_error; - assign message_header_c83_message_type_wd = reg_wdata[9:8]; - - assign message_header_c83_protocol_id_we = addr_hit[836] & reg_we & !reg_error; - assign message_header_c83_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c83_token_we = addr_hit[836] & reg_we & !reg_error; - assign message_header_c83_token_wd = reg_wdata[27:18]; - - assign message_header_c83_field1_we = addr_hit[836] & reg_we & !reg_error; - assign message_header_c83_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c83_we = addr_hit[837] & reg_we & !reg_error; - assign message_payload_1_c83_wd = reg_wdata[31:0]; - - assign doorbell_c83_intr_we = addr_hit[838] & reg_we & !reg_error; - assign doorbell_c83_intr_wd = reg_wdata[0]; - - assign doorbell_c83_preserve_mask_we = addr_hit[838] & reg_we & !reg_error; - assign doorbell_c83_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c83_intr_we = addr_hit[839] & reg_we & !reg_error; - assign completion_interrupt_c83_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c83_preserve_mask_we = addr_hit[839] & reg_we & !reg_error; - assign completion_interrupt_c83_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c84_we = addr_hit[840] & reg_we & !reg_error; - assign reserved_1_c84_wd = reg_wdata[31:0]; - - assign channel_status_c84_channel_free_we = addr_hit[841] & reg_we & !reg_error; - assign channel_status_c84_channel_free_wd = reg_wdata[0]; - - assign channel_status_c84_channel_error_we = addr_hit[841] & reg_we & !reg_error; - assign channel_status_c84_channel_error_wd = reg_wdata[1]; - - assign channel_status_c84_field1_we = addr_hit[841] & reg_we & !reg_error; - assign channel_status_c84_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c84_we = addr_hit[842] & reg_we & !reg_error; - assign reserved_2_c84_wd = reg_wdata[31:0]; - - assign channel_flags_c84_intr_enable_we = addr_hit[844] & reg_we & !reg_error; - assign channel_flags_c84_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c84_field1_we = addr_hit[844] & reg_we & !reg_error; - assign channel_flags_c84_field1_wd = reg_wdata[31:1]; - - assign length_c84_we = addr_hit[845] & reg_we & !reg_error; - assign length_c84_wd = reg_wdata[31:0]; - - assign message_header_c84_message_id_we = addr_hit[846] & reg_we & !reg_error; - assign message_header_c84_message_id_wd = reg_wdata[7:0]; - - assign message_header_c84_message_type_we = addr_hit[846] & reg_we & !reg_error; - assign message_header_c84_message_type_wd = reg_wdata[9:8]; - - assign message_header_c84_protocol_id_we = addr_hit[846] & reg_we & !reg_error; - assign message_header_c84_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c84_token_we = addr_hit[846] & reg_we & !reg_error; - assign message_header_c84_token_wd = reg_wdata[27:18]; - - assign message_header_c84_field1_we = addr_hit[846] & reg_we & !reg_error; - assign message_header_c84_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c84_we = addr_hit[847] & reg_we & !reg_error; - assign message_payload_1_c84_wd = reg_wdata[31:0]; - - assign doorbell_c84_intr_we = addr_hit[848] & reg_we & !reg_error; - assign doorbell_c84_intr_wd = reg_wdata[0]; - - assign doorbell_c84_preserve_mask_we = addr_hit[848] & reg_we & !reg_error; - assign doorbell_c84_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c84_intr_we = addr_hit[849] & reg_we & !reg_error; - assign completion_interrupt_c84_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c84_preserve_mask_we = addr_hit[849] & reg_we & !reg_error; - assign completion_interrupt_c84_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c85_we = addr_hit[850] & reg_we & !reg_error; - assign reserved_1_c85_wd = reg_wdata[31:0]; - - assign channel_status_c85_channel_free_we = addr_hit[851] & reg_we & !reg_error; - assign channel_status_c85_channel_free_wd = reg_wdata[0]; - - assign channel_status_c85_channel_error_we = addr_hit[851] & reg_we & !reg_error; - assign channel_status_c85_channel_error_wd = reg_wdata[1]; - - assign channel_status_c85_field1_we = addr_hit[851] & reg_we & !reg_error; - assign channel_status_c85_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c85_we = addr_hit[852] & reg_we & !reg_error; - assign reserved_2_c85_wd = reg_wdata[31:0]; - - assign channel_flags_c85_intr_enable_we = addr_hit[854] & reg_we & !reg_error; - assign channel_flags_c85_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c85_field1_we = addr_hit[854] & reg_we & !reg_error; - assign channel_flags_c85_field1_wd = reg_wdata[31:1]; - - assign length_c85_we = addr_hit[855] & reg_we & !reg_error; - assign length_c85_wd = reg_wdata[31:0]; - - assign message_header_c85_message_id_we = addr_hit[856] & reg_we & !reg_error; - assign message_header_c85_message_id_wd = reg_wdata[7:0]; - - assign message_header_c85_message_type_we = addr_hit[856] & reg_we & !reg_error; - assign message_header_c85_message_type_wd = reg_wdata[9:8]; - - assign message_header_c85_protocol_id_we = addr_hit[856] & reg_we & !reg_error; - assign message_header_c85_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c85_token_we = addr_hit[856] & reg_we & !reg_error; - assign message_header_c85_token_wd = reg_wdata[27:18]; - - assign message_header_c85_field1_we = addr_hit[856] & reg_we & !reg_error; - assign message_header_c85_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c85_we = addr_hit[857] & reg_we & !reg_error; - assign message_payload_1_c85_wd = reg_wdata[31:0]; - - assign doorbell_c85_intr_we = addr_hit[858] & reg_we & !reg_error; - assign doorbell_c85_intr_wd = reg_wdata[0]; - - assign doorbell_c85_preserve_mask_we = addr_hit[858] & reg_we & !reg_error; - assign doorbell_c85_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c85_intr_we = addr_hit[859] & reg_we & !reg_error; - assign completion_interrupt_c85_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c85_preserve_mask_we = addr_hit[859] & reg_we & !reg_error; - assign completion_interrupt_c85_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c86_we = addr_hit[860] & reg_we & !reg_error; - assign reserved_1_c86_wd = reg_wdata[31:0]; - - assign channel_status_c86_channel_free_we = addr_hit[861] & reg_we & !reg_error; - assign channel_status_c86_channel_free_wd = reg_wdata[0]; - - assign channel_status_c86_channel_error_we = addr_hit[861] & reg_we & !reg_error; - assign channel_status_c86_channel_error_wd = reg_wdata[1]; - - assign channel_status_c86_field1_we = addr_hit[861] & reg_we & !reg_error; - assign channel_status_c86_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c86_we = addr_hit[862] & reg_we & !reg_error; - assign reserved_2_c86_wd = reg_wdata[31:0]; - - assign channel_flags_c86_intr_enable_we = addr_hit[864] & reg_we & !reg_error; - assign channel_flags_c86_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c86_field1_we = addr_hit[864] & reg_we & !reg_error; - assign channel_flags_c86_field1_wd = reg_wdata[31:1]; - - assign length_c86_we = addr_hit[865] & reg_we & !reg_error; - assign length_c86_wd = reg_wdata[31:0]; - - assign message_header_c86_message_id_we = addr_hit[866] & reg_we & !reg_error; - assign message_header_c86_message_id_wd = reg_wdata[7:0]; - - assign message_header_c86_message_type_we = addr_hit[866] & reg_we & !reg_error; - assign message_header_c86_message_type_wd = reg_wdata[9:8]; - - assign message_header_c86_protocol_id_we = addr_hit[866] & reg_we & !reg_error; - assign message_header_c86_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c86_token_we = addr_hit[866] & reg_we & !reg_error; - assign message_header_c86_token_wd = reg_wdata[27:18]; - - assign message_header_c86_field1_we = addr_hit[866] & reg_we & !reg_error; - assign message_header_c86_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c86_we = addr_hit[867] & reg_we & !reg_error; - assign message_payload_1_c86_wd = reg_wdata[31:0]; - - assign doorbell_c86_intr_we = addr_hit[868] & reg_we & !reg_error; - assign doorbell_c86_intr_wd = reg_wdata[0]; - - assign doorbell_c86_preserve_mask_we = addr_hit[868] & reg_we & !reg_error; - assign doorbell_c86_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c86_intr_we = addr_hit[869] & reg_we & !reg_error; - assign completion_interrupt_c86_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c86_preserve_mask_we = addr_hit[869] & reg_we & !reg_error; - assign completion_interrupt_c86_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c87_we = addr_hit[870] & reg_we & !reg_error; - assign reserved_1_c87_wd = reg_wdata[31:0]; - - assign channel_status_c87_channel_free_we = addr_hit[871] & reg_we & !reg_error; - assign channel_status_c87_channel_free_wd = reg_wdata[0]; - - assign channel_status_c87_channel_error_we = addr_hit[871] & reg_we & !reg_error; - assign channel_status_c87_channel_error_wd = reg_wdata[1]; - - assign channel_status_c87_field1_we = addr_hit[871] & reg_we & !reg_error; - assign channel_status_c87_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c87_we = addr_hit[872] & reg_we & !reg_error; - assign reserved_2_c87_wd = reg_wdata[31:0]; - - assign channel_flags_c87_intr_enable_we = addr_hit[874] & reg_we & !reg_error; - assign channel_flags_c87_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c87_field1_we = addr_hit[874] & reg_we & !reg_error; - assign channel_flags_c87_field1_wd = reg_wdata[31:1]; - - assign length_c87_we = addr_hit[875] & reg_we & !reg_error; - assign length_c87_wd = reg_wdata[31:0]; - - assign message_header_c87_message_id_we = addr_hit[876] & reg_we & !reg_error; - assign message_header_c87_message_id_wd = reg_wdata[7:0]; - - assign message_header_c87_message_type_we = addr_hit[876] & reg_we & !reg_error; - assign message_header_c87_message_type_wd = reg_wdata[9:8]; - - assign message_header_c87_protocol_id_we = addr_hit[876] & reg_we & !reg_error; - assign message_header_c87_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c87_token_we = addr_hit[876] & reg_we & !reg_error; - assign message_header_c87_token_wd = reg_wdata[27:18]; - - assign message_header_c87_field1_we = addr_hit[876] & reg_we & !reg_error; - assign message_header_c87_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c87_we = addr_hit[877] & reg_we & !reg_error; - assign message_payload_1_c87_wd = reg_wdata[31:0]; - - assign doorbell_c87_intr_we = addr_hit[878] & reg_we & !reg_error; - assign doorbell_c87_intr_wd = reg_wdata[0]; - - assign doorbell_c87_preserve_mask_we = addr_hit[878] & reg_we & !reg_error; - assign doorbell_c87_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c87_intr_we = addr_hit[879] & reg_we & !reg_error; - assign completion_interrupt_c87_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c87_preserve_mask_we = addr_hit[879] & reg_we & !reg_error; - assign completion_interrupt_c87_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c88_we = addr_hit[880] & reg_we & !reg_error; - assign reserved_1_c88_wd = reg_wdata[31:0]; - - assign channel_status_c88_channel_free_we = addr_hit[881] & reg_we & !reg_error; - assign channel_status_c88_channel_free_wd = reg_wdata[0]; - - assign channel_status_c88_channel_error_we = addr_hit[881] & reg_we & !reg_error; - assign channel_status_c88_channel_error_wd = reg_wdata[1]; - - assign channel_status_c88_field1_we = addr_hit[881] & reg_we & !reg_error; - assign channel_status_c88_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c88_we = addr_hit[882] & reg_we & !reg_error; - assign reserved_2_c88_wd = reg_wdata[31:0]; - - assign channel_flags_c88_intr_enable_we = addr_hit[884] & reg_we & !reg_error; - assign channel_flags_c88_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c88_field1_we = addr_hit[884] & reg_we & !reg_error; - assign channel_flags_c88_field1_wd = reg_wdata[31:1]; - - assign length_c88_we = addr_hit[885] & reg_we & !reg_error; - assign length_c88_wd = reg_wdata[31:0]; - - assign message_header_c88_message_id_we = addr_hit[886] & reg_we & !reg_error; - assign message_header_c88_message_id_wd = reg_wdata[7:0]; - - assign message_header_c88_message_type_we = addr_hit[886] & reg_we & !reg_error; - assign message_header_c88_message_type_wd = reg_wdata[9:8]; - - assign message_header_c88_protocol_id_we = addr_hit[886] & reg_we & !reg_error; - assign message_header_c88_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c88_token_we = addr_hit[886] & reg_we & !reg_error; - assign message_header_c88_token_wd = reg_wdata[27:18]; - - assign message_header_c88_field1_we = addr_hit[886] & reg_we & !reg_error; - assign message_header_c88_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c88_we = addr_hit[887] & reg_we & !reg_error; - assign message_payload_1_c88_wd = reg_wdata[31:0]; - - assign doorbell_c88_intr_we = addr_hit[888] & reg_we & !reg_error; - assign doorbell_c88_intr_wd = reg_wdata[0]; - - assign doorbell_c88_preserve_mask_we = addr_hit[888] & reg_we & !reg_error; - assign doorbell_c88_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c88_intr_we = addr_hit[889] & reg_we & !reg_error; - assign completion_interrupt_c88_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c88_preserve_mask_we = addr_hit[889] & reg_we & !reg_error; - assign completion_interrupt_c88_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c89_we = addr_hit[890] & reg_we & !reg_error; - assign reserved_1_c89_wd = reg_wdata[31:0]; - - assign channel_status_c89_channel_free_we = addr_hit[891] & reg_we & !reg_error; - assign channel_status_c89_channel_free_wd = reg_wdata[0]; - - assign channel_status_c89_channel_error_we = addr_hit[891] & reg_we & !reg_error; - assign channel_status_c89_channel_error_wd = reg_wdata[1]; - - assign channel_status_c89_field1_we = addr_hit[891] & reg_we & !reg_error; - assign channel_status_c89_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c89_we = addr_hit[892] & reg_we & !reg_error; - assign reserved_2_c89_wd = reg_wdata[31:0]; - - assign channel_flags_c89_intr_enable_we = addr_hit[894] & reg_we & !reg_error; - assign channel_flags_c89_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c89_field1_we = addr_hit[894] & reg_we & !reg_error; - assign channel_flags_c89_field1_wd = reg_wdata[31:1]; - - assign length_c89_we = addr_hit[895] & reg_we & !reg_error; - assign length_c89_wd = reg_wdata[31:0]; - - assign message_header_c89_message_id_we = addr_hit[896] & reg_we & !reg_error; - assign message_header_c89_message_id_wd = reg_wdata[7:0]; - - assign message_header_c89_message_type_we = addr_hit[896] & reg_we & !reg_error; - assign message_header_c89_message_type_wd = reg_wdata[9:8]; - - assign message_header_c89_protocol_id_we = addr_hit[896] & reg_we & !reg_error; - assign message_header_c89_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c89_token_we = addr_hit[896] & reg_we & !reg_error; - assign message_header_c89_token_wd = reg_wdata[27:18]; - - assign message_header_c89_field1_we = addr_hit[896] & reg_we & !reg_error; - assign message_header_c89_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c89_we = addr_hit[897] & reg_we & !reg_error; - assign message_payload_1_c89_wd = reg_wdata[31:0]; - - assign doorbell_c89_intr_we = addr_hit[898] & reg_we & !reg_error; - assign doorbell_c89_intr_wd = reg_wdata[0]; - - assign doorbell_c89_preserve_mask_we = addr_hit[898] & reg_we & !reg_error; - assign doorbell_c89_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c89_intr_we = addr_hit[899] & reg_we & !reg_error; - assign completion_interrupt_c89_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c89_preserve_mask_we = addr_hit[899] & reg_we & !reg_error; - assign completion_interrupt_c89_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c90_we = addr_hit[900] & reg_we & !reg_error; - assign reserved_1_c90_wd = reg_wdata[31:0]; - - assign channel_status_c90_channel_free_we = addr_hit[901] & reg_we & !reg_error; - assign channel_status_c90_channel_free_wd = reg_wdata[0]; - - assign channel_status_c90_channel_error_we = addr_hit[901] & reg_we & !reg_error; - assign channel_status_c90_channel_error_wd = reg_wdata[1]; - - assign channel_status_c90_field1_we = addr_hit[901] & reg_we & !reg_error; - assign channel_status_c90_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c90_we = addr_hit[902] & reg_we & !reg_error; - assign reserved_2_c90_wd = reg_wdata[31:0]; - - assign channel_flags_c90_intr_enable_we = addr_hit[904] & reg_we & !reg_error; - assign channel_flags_c90_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c90_field1_we = addr_hit[904] & reg_we & !reg_error; - assign channel_flags_c90_field1_wd = reg_wdata[31:1]; - - assign length_c90_we = addr_hit[905] & reg_we & !reg_error; - assign length_c90_wd = reg_wdata[31:0]; - - assign message_header_c90_message_id_we = addr_hit[906] & reg_we & !reg_error; - assign message_header_c90_message_id_wd = reg_wdata[7:0]; - - assign message_header_c90_message_type_we = addr_hit[906] & reg_we & !reg_error; - assign message_header_c90_message_type_wd = reg_wdata[9:8]; - - assign message_header_c90_protocol_id_we = addr_hit[906] & reg_we & !reg_error; - assign message_header_c90_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c90_token_we = addr_hit[906] & reg_we & !reg_error; - assign message_header_c90_token_wd = reg_wdata[27:18]; - - assign message_header_c90_field1_we = addr_hit[906] & reg_we & !reg_error; - assign message_header_c90_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c90_we = addr_hit[907] & reg_we & !reg_error; - assign message_payload_1_c90_wd = reg_wdata[31:0]; - - assign doorbell_c90_intr_we = addr_hit[908] & reg_we & !reg_error; - assign doorbell_c90_intr_wd = reg_wdata[0]; - - assign doorbell_c90_preserve_mask_we = addr_hit[908] & reg_we & !reg_error; - assign doorbell_c90_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c90_intr_we = addr_hit[909] & reg_we & !reg_error; - assign completion_interrupt_c90_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c90_preserve_mask_we = addr_hit[909] & reg_we & !reg_error; - assign completion_interrupt_c90_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c91_we = addr_hit[910] & reg_we & !reg_error; - assign reserved_1_c91_wd = reg_wdata[31:0]; - - assign channel_status_c91_channel_free_we = addr_hit[911] & reg_we & !reg_error; - assign channel_status_c91_channel_free_wd = reg_wdata[0]; - - assign channel_status_c91_channel_error_we = addr_hit[911] & reg_we & !reg_error; - assign channel_status_c91_channel_error_wd = reg_wdata[1]; - - assign channel_status_c91_field1_we = addr_hit[911] & reg_we & !reg_error; - assign channel_status_c91_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c91_we = addr_hit[912] & reg_we & !reg_error; - assign reserved_2_c91_wd = reg_wdata[31:0]; - - assign channel_flags_c91_intr_enable_we = addr_hit[914] & reg_we & !reg_error; - assign channel_flags_c91_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c91_field1_we = addr_hit[914] & reg_we & !reg_error; - assign channel_flags_c91_field1_wd = reg_wdata[31:1]; - - assign length_c91_we = addr_hit[915] & reg_we & !reg_error; - assign length_c91_wd = reg_wdata[31:0]; - - assign message_header_c91_message_id_we = addr_hit[916] & reg_we & !reg_error; - assign message_header_c91_message_id_wd = reg_wdata[7:0]; - - assign message_header_c91_message_type_we = addr_hit[916] & reg_we & !reg_error; - assign message_header_c91_message_type_wd = reg_wdata[9:8]; - - assign message_header_c91_protocol_id_we = addr_hit[916] & reg_we & !reg_error; - assign message_header_c91_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c91_token_we = addr_hit[916] & reg_we & !reg_error; - assign message_header_c91_token_wd = reg_wdata[27:18]; - - assign message_header_c91_field1_we = addr_hit[916] & reg_we & !reg_error; - assign message_header_c91_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c91_we = addr_hit[917] & reg_we & !reg_error; - assign message_payload_1_c91_wd = reg_wdata[31:0]; - - assign doorbell_c91_intr_we = addr_hit[918] & reg_we & !reg_error; - assign doorbell_c91_intr_wd = reg_wdata[0]; - - assign doorbell_c91_preserve_mask_we = addr_hit[918] & reg_we & !reg_error; - assign doorbell_c91_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c91_intr_we = addr_hit[919] & reg_we & !reg_error; - assign completion_interrupt_c91_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c91_preserve_mask_we = addr_hit[919] & reg_we & !reg_error; - assign completion_interrupt_c91_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c92_we = addr_hit[920] & reg_we & !reg_error; - assign reserved_1_c92_wd = reg_wdata[31:0]; - - assign channel_status_c92_channel_free_we = addr_hit[921] & reg_we & !reg_error; - assign channel_status_c92_channel_free_wd = reg_wdata[0]; - - assign channel_status_c92_channel_error_we = addr_hit[921] & reg_we & !reg_error; - assign channel_status_c92_channel_error_wd = reg_wdata[1]; - - assign channel_status_c92_field1_we = addr_hit[921] & reg_we & !reg_error; - assign channel_status_c92_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c92_we = addr_hit[922] & reg_we & !reg_error; - assign reserved_2_c92_wd = reg_wdata[31:0]; - - assign channel_flags_c92_intr_enable_we = addr_hit[924] & reg_we & !reg_error; - assign channel_flags_c92_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c92_field1_we = addr_hit[924] & reg_we & !reg_error; - assign channel_flags_c92_field1_wd = reg_wdata[31:1]; - - assign length_c92_we = addr_hit[925] & reg_we & !reg_error; - assign length_c92_wd = reg_wdata[31:0]; - - assign message_header_c92_message_id_we = addr_hit[926] & reg_we & !reg_error; - assign message_header_c92_message_id_wd = reg_wdata[7:0]; - - assign message_header_c92_message_type_we = addr_hit[926] & reg_we & !reg_error; - assign message_header_c92_message_type_wd = reg_wdata[9:8]; - - assign message_header_c92_protocol_id_we = addr_hit[926] & reg_we & !reg_error; - assign message_header_c92_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c92_token_we = addr_hit[926] & reg_we & !reg_error; - assign message_header_c92_token_wd = reg_wdata[27:18]; - - assign message_header_c92_field1_we = addr_hit[926] & reg_we & !reg_error; - assign message_header_c92_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c92_we = addr_hit[927] & reg_we & !reg_error; - assign message_payload_1_c92_wd = reg_wdata[31:0]; - - assign doorbell_c92_intr_we = addr_hit[928] & reg_we & !reg_error; - assign doorbell_c92_intr_wd = reg_wdata[0]; - - assign doorbell_c92_preserve_mask_we = addr_hit[928] & reg_we & !reg_error; - assign doorbell_c92_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c92_intr_we = addr_hit[929] & reg_we & !reg_error; - assign completion_interrupt_c92_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c92_preserve_mask_we = addr_hit[929] & reg_we & !reg_error; - assign completion_interrupt_c92_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c93_we = addr_hit[930] & reg_we & !reg_error; - assign reserved_1_c93_wd = reg_wdata[31:0]; - - assign channel_status_c93_channel_free_we = addr_hit[931] & reg_we & !reg_error; - assign channel_status_c93_channel_free_wd = reg_wdata[0]; - - assign channel_status_c93_channel_error_we = addr_hit[931] & reg_we & !reg_error; - assign channel_status_c93_channel_error_wd = reg_wdata[1]; - - assign channel_status_c93_field1_we = addr_hit[931] & reg_we & !reg_error; - assign channel_status_c93_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c93_we = addr_hit[932] & reg_we & !reg_error; - assign reserved_2_c93_wd = reg_wdata[31:0]; - - assign channel_flags_c93_intr_enable_we = addr_hit[934] & reg_we & !reg_error; - assign channel_flags_c93_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c93_field1_we = addr_hit[934] & reg_we & !reg_error; - assign channel_flags_c93_field1_wd = reg_wdata[31:1]; - - assign length_c93_we = addr_hit[935] & reg_we & !reg_error; - assign length_c93_wd = reg_wdata[31:0]; - - assign message_header_c93_message_id_we = addr_hit[936] & reg_we & !reg_error; - assign message_header_c93_message_id_wd = reg_wdata[7:0]; - - assign message_header_c93_message_type_we = addr_hit[936] & reg_we & !reg_error; - assign message_header_c93_message_type_wd = reg_wdata[9:8]; - - assign message_header_c93_protocol_id_we = addr_hit[936] & reg_we & !reg_error; - assign message_header_c93_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c93_token_we = addr_hit[936] & reg_we & !reg_error; - assign message_header_c93_token_wd = reg_wdata[27:18]; - - assign message_header_c93_field1_we = addr_hit[936] & reg_we & !reg_error; - assign message_header_c93_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c93_we = addr_hit[937] & reg_we & !reg_error; - assign message_payload_1_c93_wd = reg_wdata[31:0]; - - assign doorbell_c93_intr_we = addr_hit[938] & reg_we & !reg_error; - assign doorbell_c93_intr_wd = reg_wdata[0]; - - assign doorbell_c93_preserve_mask_we = addr_hit[938] & reg_we & !reg_error; - assign doorbell_c93_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c93_intr_we = addr_hit[939] & reg_we & !reg_error; - assign completion_interrupt_c93_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c93_preserve_mask_we = addr_hit[939] & reg_we & !reg_error; - assign completion_interrupt_c93_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c94_we = addr_hit[940] & reg_we & !reg_error; - assign reserved_1_c94_wd = reg_wdata[31:0]; - - assign channel_status_c94_channel_free_we = addr_hit[941] & reg_we & !reg_error; - assign channel_status_c94_channel_free_wd = reg_wdata[0]; - - assign channel_status_c94_channel_error_we = addr_hit[941] & reg_we & !reg_error; - assign channel_status_c94_channel_error_wd = reg_wdata[1]; - - assign channel_status_c94_field1_we = addr_hit[941] & reg_we & !reg_error; - assign channel_status_c94_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c94_we = addr_hit[942] & reg_we & !reg_error; - assign reserved_2_c94_wd = reg_wdata[31:0]; - - assign channel_flags_c94_intr_enable_we = addr_hit[944] & reg_we & !reg_error; - assign channel_flags_c94_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c94_field1_we = addr_hit[944] & reg_we & !reg_error; - assign channel_flags_c94_field1_wd = reg_wdata[31:1]; - - assign length_c94_we = addr_hit[945] & reg_we & !reg_error; - assign length_c94_wd = reg_wdata[31:0]; - - assign message_header_c94_message_id_we = addr_hit[946] & reg_we & !reg_error; - assign message_header_c94_message_id_wd = reg_wdata[7:0]; - - assign message_header_c94_message_type_we = addr_hit[946] & reg_we & !reg_error; - assign message_header_c94_message_type_wd = reg_wdata[9:8]; - - assign message_header_c94_protocol_id_we = addr_hit[946] & reg_we & !reg_error; - assign message_header_c94_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c94_token_we = addr_hit[946] & reg_we & !reg_error; - assign message_header_c94_token_wd = reg_wdata[27:18]; - - assign message_header_c94_field1_we = addr_hit[946] & reg_we & !reg_error; - assign message_header_c94_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c94_we = addr_hit[947] & reg_we & !reg_error; - assign message_payload_1_c94_wd = reg_wdata[31:0]; - - assign doorbell_c94_intr_we = addr_hit[948] & reg_we & !reg_error; - assign doorbell_c94_intr_wd = reg_wdata[0]; - - assign doorbell_c94_preserve_mask_we = addr_hit[948] & reg_we & !reg_error; - assign doorbell_c94_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c94_intr_we = addr_hit[949] & reg_we & !reg_error; - assign completion_interrupt_c94_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c94_preserve_mask_we = addr_hit[949] & reg_we & !reg_error; - assign completion_interrupt_c94_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c95_we = addr_hit[950] & reg_we & !reg_error; - assign reserved_1_c95_wd = reg_wdata[31:0]; - - assign channel_status_c95_channel_free_we = addr_hit[951] & reg_we & !reg_error; - assign channel_status_c95_channel_free_wd = reg_wdata[0]; - - assign channel_status_c95_channel_error_we = addr_hit[951] & reg_we & !reg_error; - assign channel_status_c95_channel_error_wd = reg_wdata[1]; - - assign channel_status_c95_field1_we = addr_hit[951] & reg_we & !reg_error; - assign channel_status_c95_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c95_we = addr_hit[952] & reg_we & !reg_error; - assign reserved_2_c95_wd = reg_wdata[31:0]; - - assign channel_flags_c95_intr_enable_we = addr_hit[954] & reg_we & !reg_error; - assign channel_flags_c95_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c95_field1_we = addr_hit[954] & reg_we & !reg_error; - assign channel_flags_c95_field1_wd = reg_wdata[31:1]; - - assign length_c95_we = addr_hit[955] & reg_we & !reg_error; - assign length_c95_wd = reg_wdata[31:0]; - - assign message_header_c95_message_id_we = addr_hit[956] & reg_we & !reg_error; - assign message_header_c95_message_id_wd = reg_wdata[7:0]; - - assign message_header_c95_message_type_we = addr_hit[956] & reg_we & !reg_error; - assign message_header_c95_message_type_wd = reg_wdata[9:8]; - - assign message_header_c95_protocol_id_we = addr_hit[956] & reg_we & !reg_error; - assign message_header_c95_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c95_token_we = addr_hit[956] & reg_we & !reg_error; - assign message_header_c95_token_wd = reg_wdata[27:18]; - - assign message_header_c95_field1_we = addr_hit[956] & reg_we & !reg_error; - assign message_header_c95_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c95_we = addr_hit[957] & reg_we & !reg_error; - assign message_payload_1_c95_wd = reg_wdata[31:0]; - - assign doorbell_c95_intr_we = addr_hit[958] & reg_we & !reg_error; - assign doorbell_c95_intr_wd = reg_wdata[0]; - - assign doorbell_c95_preserve_mask_we = addr_hit[958] & reg_we & !reg_error; - assign doorbell_c95_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c95_intr_we = addr_hit[959] & reg_we & !reg_error; - assign completion_interrupt_c95_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c95_preserve_mask_we = addr_hit[959] & reg_we & !reg_error; - assign completion_interrupt_c95_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c96_we = addr_hit[960] & reg_we & !reg_error; - assign reserved_1_c96_wd = reg_wdata[31:0]; - - assign channel_status_c96_channel_free_we = addr_hit[961] & reg_we & !reg_error; - assign channel_status_c96_channel_free_wd = reg_wdata[0]; - - assign channel_status_c96_channel_error_we = addr_hit[961] & reg_we & !reg_error; - assign channel_status_c96_channel_error_wd = reg_wdata[1]; - - assign channel_status_c96_field1_we = addr_hit[961] & reg_we & !reg_error; - assign channel_status_c96_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c96_we = addr_hit[962] & reg_we & !reg_error; - assign reserved_2_c96_wd = reg_wdata[31:0]; - - assign channel_flags_c96_intr_enable_we = addr_hit[964] & reg_we & !reg_error; - assign channel_flags_c96_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c96_field1_we = addr_hit[964] & reg_we & !reg_error; - assign channel_flags_c96_field1_wd = reg_wdata[31:1]; - - assign length_c96_we = addr_hit[965] & reg_we & !reg_error; - assign length_c96_wd = reg_wdata[31:0]; - - assign message_header_c96_message_id_we = addr_hit[966] & reg_we & !reg_error; - assign message_header_c96_message_id_wd = reg_wdata[7:0]; - - assign message_header_c96_message_type_we = addr_hit[966] & reg_we & !reg_error; - assign message_header_c96_message_type_wd = reg_wdata[9:8]; - - assign message_header_c96_protocol_id_we = addr_hit[966] & reg_we & !reg_error; - assign message_header_c96_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c96_token_we = addr_hit[966] & reg_we & !reg_error; - assign message_header_c96_token_wd = reg_wdata[27:18]; - - assign message_header_c96_field1_we = addr_hit[966] & reg_we & !reg_error; - assign message_header_c96_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c96_we = addr_hit[967] & reg_we & !reg_error; - assign message_payload_1_c96_wd = reg_wdata[31:0]; - - assign doorbell_c96_intr_we = addr_hit[968] & reg_we & !reg_error; - assign doorbell_c96_intr_wd = reg_wdata[0]; - - assign doorbell_c96_preserve_mask_we = addr_hit[968] & reg_we & !reg_error; - assign doorbell_c96_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c96_intr_we = addr_hit[969] & reg_we & !reg_error; - assign completion_interrupt_c96_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c96_preserve_mask_we = addr_hit[969] & reg_we & !reg_error; - assign completion_interrupt_c96_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c97_we = addr_hit[970] & reg_we & !reg_error; - assign reserved_1_c97_wd = reg_wdata[31:0]; - - assign channel_status_c97_channel_free_we = addr_hit[971] & reg_we & !reg_error; - assign channel_status_c97_channel_free_wd = reg_wdata[0]; - - assign channel_status_c97_channel_error_we = addr_hit[971] & reg_we & !reg_error; - assign channel_status_c97_channel_error_wd = reg_wdata[1]; - - assign channel_status_c97_field1_we = addr_hit[971] & reg_we & !reg_error; - assign channel_status_c97_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c97_we = addr_hit[972] & reg_we & !reg_error; - assign reserved_2_c97_wd = reg_wdata[31:0]; - - assign channel_flags_c97_intr_enable_we = addr_hit[974] & reg_we & !reg_error; - assign channel_flags_c97_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c97_field1_we = addr_hit[974] & reg_we & !reg_error; - assign channel_flags_c97_field1_wd = reg_wdata[31:1]; - - assign length_c97_we = addr_hit[975] & reg_we & !reg_error; - assign length_c97_wd = reg_wdata[31:0]; - - assign message_header_c97_message_id_we = addr_hit[976] & reg_we & !reg_error; - assign message_header_c97_message_id_wd = reg_wdata[7:0]; - - assign message_header_c97_message_type_we = addr_hit[976] & reg_we & !reg_error; - assign message_header_c97_message_type_wd = reg_wdata[9:8]; - - assign message_header_c97_protocol_id_we = addr_hit[976] & reg_we & !reg_error; - assign message_header_c97_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c97_token_we = addr_hit[976] & reg_we & !reg_error; - assign message_header_c97_token_wd = reg_wdata[27:18]; - - assign message_header_c97_field1_we = addr_hit[976] & reg_we & !reg_error; - assign message_header_c97_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c97_we = addr_hit[977] & reg_we & !reg_error; - assign message_payload_1_c97_wd = reg_wdata[31:0]; - - assign doorbell_c97_intr_we = addr_hit[978] & reg_we & !reg_error; - assign doorbell_c97_intr_wd = reg_wdata[0]; - - assign doorbell_c97_preserve_mask_we = addr_hit[978] & reg_we & !reg_error; - assign doorbell_c97_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c97_intr_we = addr_hit[979] & reg_we & !reg_error; - assign completion_interrupt_c97_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c97_preserve_mask_we = addr_hit[979] & reg_we & !reg_error; - assign completion_interrupt_c97_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c98_we = addr_hit[980] & reg_we & !reg_error; - assign reserved_1_c98_wd = reg_wdata[31:0]; - - assign channel_status_c98_channel_free_we = addr_hit[981] & reg_we & !reg_error; - assign channel_status_c98_channel_free_wd = reg_wdata[0]; - - assign channel_status_c98_channel_error_we = addr_hit[981] & reg_we & !reg_error; - assign channel_status_c98_channel_error_wd = reg_wdata[1]; - - assign channel_status_c98_field1_we = addr_hit[981] & reg_we & !reg_error; - assign channel_status_c98_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c98_we = addr_hit[982] & reg_we & !reg_error; - assign reserved_2_c98_wd = reg_wdata[31:0]; - - assign channel_flags_c98_intr_enable_we = addr_hit[984] & reg_we & !reg_error; - assign channel_flags_c98_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c98_field1_we = addr_hit[984] & reg_we & !reg_error; - assign channel_flags_c98_field1_wd = reg_wdata[31:1]; - - assign length_c98_we = addr_hit[985] & reg_we & !reg_error; - assign length_c98_wd = reg_wdata[31:0]; - - assign message_header_c98_message_id_we = addr_hit[986] & reg_we & !reg_error; - assign message_header_c98_message_id_wd = reg_wdata[7:0]; - - assign message_header_c98_message_type_we = addr_hit[986] & reg_we & !reg_error; - assign message_header_c98_message_type_wd = reg_wdata[9:8]; - - assign message_header_c98_protocol_id_we = addr_hit[986] & reg_we & !reg_error; - assign message_header_c98_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c98_token_we = addr_hit[986] & reg_we & !reg_error; - assign message_header_c98_token_wd = reg_wdata[27:18]; - - assign message_header_c98_field1_we = addr_hit[986] & reg_we & !reg_error; - assign message_header_c98_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c98_we = addr_hit[987] & reg_we & !reg_error; - assign message_payload_1_c98_wd = reg_wdata[31:0]; - - assign doorbell_c98_intr_we = addr_hit[988] & reg_we & !reg_error; - assign doorbell_c98_intr_wd = reg_wdata[0]; - - assign doorbell_c98_preserve_mask_we = addr_hit[988] & reg_we & !reg_error; - assign doorbell_c98_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c98_intr_we = addr_hit[989] & reg_we & !reg_error; - assign completion_interrupt_c98_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c98_preserve_mask_we = addr_hit[989] & reg_we & !reg_error; - assign completion_interrupt_c98_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c99_we = addr_hit[990] & reg_we & !reg_error; - assign reserved_1_c99_wd = reg_wdata[31:0]; - - assign channel_status_c99_channel_free_we = addr_hit[991] & reg_we & !reg_error; - assign channel_status_c99_channel_free_wd = reg_wdata[0]; - - assign channel_status_c99_channel_error_we = addr_hit[991] & reg_we & !reg_error; - assign channel_status_c99_channel_error_wd = reg_wdata[1]; - - assign channel_status_c99_field1_we = addr_hit[991] & reg_we & !reg_error; - assign channel_status_c99_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c99_we = addr_hit[992] & reg_we & !reg_error; - assign reserved_2_c99_wd = reg_wdata[31:0]; - - assign channel_flags_c99_intr_enable_we = addr_hit[994] & reg_we & !reg_error; - assign channel_flags_c99_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c99_field1_we = addr_hit[994] & reg_we & !reg_error; - assign channel_flags_c99_field1_wd = reg_wdata[31:1]; - - assign length_c99_we = addr_hit[995] & reg_we & !reg_error; - assign length_c99_wd = reg_wdata[31:0]; - - assign message_header_c99_message_id_we = addr_hit[996] & reg_we & !reg_error; - assign message_header_c99_message_id_wd = reg_wdata[7:0]; - - assign message_header_c99_message_type_we = addr_hit[996] & reg_we & !reg_error; - assign message_header_c99_message_type_wd = reg_wdata[9:8]; - - assign message_header_c99_protocol_id_we = addr_hit[996] & reg_we & !reg_error; - assign message_header_c99_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c99_token_we = addr_hit[996] & reg_we & !reg_error; - assign message_header_c99_token_wd = reg_wdata[27:18]; - - assign message_header_c99_field1_we = addr_hit[996] & reg_we & !reg_error; - assign message_header_c99_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c99_we = addr_hit[997] & reg_we & !reg_error; - assign message_payload_1_c99_wd = reg_wdata[31:0]; - - assign doorbell_c99_intr_we = addr_hit[998] & reg_we & !reg_error; - assign doorbell_c99_intr_wd = reg_wdata[0]; - - assign doorbell_c99_preserve_mask_we = addr_hit[998] & reg_we & !reg_error; - assign doorbell_c99_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c99_intr_we = addr_hit[999] & reg_we & !reg_error; - assign completion_interrupt_c99_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c99_preserve_mask_we = addr_hit[999] & reg_we & !reg_error; - assign completion_interrupt_c99_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c100_we = addr_hit[1000] & reg_we & !reg_error; - assign reserved_1_c100_wd = reg_wdata[31:0]; - - assign channel_status_c100_channel_free_we = addr_hit[1001] & reg_we & !reg_error; - assign channel_status_c100_channel_free_wd = reg_wdata[0]; - - assign channel_status_c100_channel_error_we = addr_hit[1001] & reg_we & !reg_error; - assign channel_status_c100_channel_error_wd = reg_wdata[1]; - - assign channel_status_c100_field1_we = addr_hit[1001] & reg_we & !reg_error; - assign channel_status_c100_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c100_we = addr_hit[1002] & reg_we & !reg_error; - assign reserved_2_c100_wd = reg_wdata[31:0]; - - assign channel_flags_c100_intr_enable_we = addr_hit[1004] & reg_we & !reg_error; - assign channel_flags_c100_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c100_field1_we = addr_hit[1004] & reg_we & !reg_error; - assign channel_flags_c100_field1_wd = reg_wdata[31:1]; - - assign length_c100_we = addr_hit[1005] & reg_we & !reg_error; - assign length_c100_wd = reg_wdata[31:0]; - - assign message_header_c100_message_id_we = addr_hit[1006] & reg_we & !reg_error; - assign message_header_c100_message_id_wd = reg_wdata[7:0]; - - assign message_header_c100_message_type_we = addr_hit[1006] & reg_we & !reg_error; - assign message_header_c100_message_type_wd = reg_wdata[9:8]; - - assign message_header_c100_protocol_id_we = addr_hit[1006] & reg_we & !reg_error; - assign message_header_c100_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c100_token_we = addr_hit[1006] & reg_we & !reg_error; - assign message_header_c100_token_wd = reg_wdata[27:18]; - - assign message_header_c100_field1_we = addr_hit[1006] & reg_we & !reg_error; - assign message_header_c100_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c100_we = addr_hit[1007] & reg_we & !reg_error; - assign message_payload_1_c100_wd = reg_wdata[31:0]; - - assign doorbell_c100_intr_we = addr_hit[1008] & reg_we & !reg_error; - assign doorbell_c100_intr_wd = reg_wdata[0]; - - assign doorbell_c100_preserve_mask_we = addr_hit[1008] & reg_we & !reg_error; - assign doorbell_c100_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c100_intr_we = addr_hit[1009] & reg_we & !reg_error; - assign completion_interrupt_c100_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c100_preserve_mask_we = addr_hit[1009] & reg_we & !reg_error; - assign completion_interrupt_c100_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c101_we = addr_hit[1010] & reg_we & !reg_error; - assign reserved_1_c101_wd = reg_wdata[31:0]; - - assign channel_status_c101_channel_free_we = addr_hit[1011] & reg_we & !reg_error; - assign channel_status_c101_channel_free_wd = reg_wdata[0]; - - assign channel_status_c101_channel_error_we = addr_hit[1011] & reg_we & !reg_error; - assign channel_status_c101_channel_error_wd = reg_wdata[1]; - - assign channel_status_c101_field1_we = addr_hit[1011] & reg_we & !reg_error; - assign channel_status_c101_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c101_we = addr_hit[1012] & reg_we & !reg_error; - assign reserved_2_c101_wd = reg_wdata[31:0]; - - assign channel_flags_c101_intr_enable_we = addr_hit[1014] & reg_we & !reg_error; - assign channel_flags_c101_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c101_field1_we = addr_hit[1014] & reg_we & !reg_error; - assign channel_flags_c101_field1_wd = reg_wdata[31:1]; - - assign length_c101_we = addr_hit[1015] & reg_we & !reg_error; - assign length_c101_wd = reg_wdata[31:0]; - - assign message_header_c101_message_id_we = addr_hit[1016] & reg_we & !reg_error; - assign message_header_c101_message_id_wd = reg_wdata[7:0]; - - assign message_header_c101_message_type_we = addr_hit[1016] & reg_we & !reg_error; - assign message_header_c101_message_type_wd = reg_wdata[9:8]; - - assign message_header_c101_protocol_id_we = addr_hit[1016] & reg_we & !reg_error; - assign message_header_c101_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c101_token_we = addr_hit[1016] & reg_we & !reg_error; - assign message_header_c101_token_wd = reg_wdata[27:18]; - - assign message_header_c101_field1_we = addr_hit[1016] & reg_we & !reg_error; - assign message_header_c101_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c101_we = addr_hit[1017] & reg_we & !reg_error; - assign message_payload_1_c101_wd = reg_wdata[31:0]; - - assign doorbell_c101_intr_we = addr_hit[1018] & reg_we & !reg_error; - assign doorbell_c101_intr_wd = reg_wdata[0]; - - assign doorbell_c101_preserve_mask_we = addr_hit[1018] & reg_we & !reg_error; - assign doorbell_c101_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c101_intr_we = addr_hit[1019] & reg_we & !reg_error; - assign completion_interrupt_c101_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c101_preserve_mask_we = addr_hit[1019] & reg_we & !reg_error; - assign completion_interrupt_c101_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c102_we = addr_hit[1020] & reg_we & !reg_error; - assign reserved_1_c102_wd = reg_wdata[31:0]; - - assign channel_status_c102_channel_free_we = addr_hit[1021] & reg_we & !reg_error; - assign channel_status_c102_channel_free_wd = reg_wdata[0]; - - assign channel_status_c102_channel_error_we = addr_hit[1021] & reg_we & !reg_error; - assign channel_status_c102_channel_error_wd = reg_wdata[1]; - - assign channel_status_c102_field1_we = addr_hit[1021] & reg_we & !reg_error; - assign channel_status_c102_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c102_we = addr_hit[1022] & reg_we & !reg_error; - assign reserved_2_c102_wd = reg_wdata[31:0]; - - assign channel_flags_c102_intr_enable_we = addr_hit[1024] & reg_we & !reg_error; - assign channel_flags_c102_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c102_field1_we = addr_hit[1024] & reg_we & !reg_error; - assign channel_flags_c102_field1_wd = reg_wdata[31:1]; - - assign length_c102_we = addr_hit[1025] & reg_we & !reg_error; - assign length_c102_wd = reg_wdata[31:0]; - - assign message_header_c102_message_id_we = addr_hit[1026] & reg_we & !reg_error; - assign message_header_c102_message_id_wd = reg_wdata[7:0]; - - assign message_header_c102_message_type_we = addr_hit[1026] & reg_we & !reg_error; - assign message_header_c102_message_type_wd = reg_wdata[9:8]; - - assign message_header_c102_protocol_id_we = addr_hit[1026] & reg_we & !reg_error; - assign message_header_c102_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c102_token_we = addr_hit[1026] & reg_we & !reg_error; - assign message_header_c102_token_wd = reg_wdata[27:18]; - - assign message_header_c102_field1_we = addr_hit[1026] & reg_we & !reg_error; - assign message_header_c102_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c102_we = addr_hit[1027] & reg_we & !reg_error; - assign message_payload_1_c102_wd = reg_wdata[31:0]; - - assign doorbell_c102_intr_we = addr_hit[1028] & reg_we & !reg_error; - assign doorbell_c102_intr_wd = reg_wdata[0]; - - assign doorbell_c102_preserve_mask_we = addr_hit[1028] & reg_we & !reg_error; - assign doorbell_c102_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c102_intr_we = addr_hit[1029] & reg_we & !reg_error; - assign completion_interrupt_c102_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c102_preserve_mask_we = addr_hit[1029] & reg_we & !reg_error; - assign completion_interrupt_c102_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c103_we = addr_hit[1030] & reg_we & !reg_error; - assign reserved_1_c103_wd = reg_wdata[31:0]; - - assign channel_status_c103_channel_free_we = addr_hit[1031] & reg_we & !reg_error; - assign channel_status_c103_channel_free_wd = reg_wdata[0]; - - assign channel_status_c103_channel_error_we = addr_hit[1031] & reg_we & !reg_error; - assign channel_status_c103_channel_error_wd = reg_wdata[1]; - - assign channel_status_c103_field1_we = addr_hit[1031] & reg_we & !reg_error; - assign channel_status_c103_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c103_we = addr_hit[1032] & reg_we & !reg_error; - assign reserved_2_c103_wd = reg_wdata[31:0]; - - assign channel_flags_c103_intr_enable_we = addr_hit[1034] & reg_we & !reg_error; - assign channel_flags_c103_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c103_field1_we = addr_hit[1034] & reg_we & !reg_error; - assign channel_flags_c103_field1_wd = reg_wdata[31:1]; - - assign length_c103_we = addr_hit[1035] & reg_we & !reg_error; - assign length_c103_wd = reg_wdata[31:0]; - - assign message_header_c103_message_id_we = addr_hit[1036] & reg_we & !reg_error; - assign message_header_c103_message_id_wd = reg_wdata[7:0]; - - assign message_header_c103_message_type_we = addr_hit[1036] & reg_we & !reg_error; - assign message_header_c103_message_type_wd = reg_wdata[9:8]; - - assign message_header_c103_protocol_id_we = addr_hit[1036] & reg_we & !reg_error; - assign message_header_c103_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c103_token_we = addr_hit[1036] & reg_we & !reg_error; - assign message_header_c103_token_wd = reg_wdata[27:18]; - - assign message_header_c103_field1_we = addr_hit[1036] & reg_we & !reg_error; - assign message_header_c103_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c103_we = addr_hit[1037] & reg_we & !reg_error; - assign message_payload_1_c103_wd = reg_wdata[31:0]; - - assign doorbell_c103_intr_we = addr_hit[1038] & reg_we & !reg_error; - assign doorbell_c103_intr_wd = reg_wdata[0]; - - assign doorbell_c103_preserve_mask_we = addr_hit[1038] & reg_we & !reg_error; - assign doorbell_c103_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c103_intr_we = addr_hit[1039] & reg_we & !reg_error; - assign completion_interrupt_c103_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c103_preserve_mask_we = addr_hit[1039] & reg_we & !reg_error; - assign completion_interrupt_c103_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c104_we = addr_hit[1040] & reg_we & !reg_error; - assign reserved_1_c104_wd = reg_wdata[31:0]; - - assign channel_status_c104_channel_free_we = addr_hit[1041] & reg_we & !reg_error; - assign channel_status_c104_channel_free_wd = reg_wdata[0]; - - assign channel_status_c104_channel_error_we = addr_hit[1041] & reg_we & !reg_error; - assign channel_status_c104_channel_error_wd = reg_wdata[1]; - - assign channel_status_c104_field1_we = addr_hit[1041] & reg_we & !reg_error; - assign channel_status_c104_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c104_we = addr_hit[1042] & reg_we & !reg_error; - assign reserved_2_c104_wd = reg_wdata[31:0]; - - assign channel_flags_c104_intr_enable_we = addr_hit[1044] & reg_we & !reg_error; - assign channel_flags_c104_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c104_field1_we = addr_hit[1044] & reg_we & !reg_error; - assign channel_flags_c104_field1_wd = reg_wdata[31:1]; - - assign length_c104_we = addr_hit[1045] & reg_we & !reg_error; - assign length_c104_wd = reg_wdata[31:0]; - - assign message_header_c104_message_id_we = addr_hit[1046] & reg_we & !reg_error; - assign message_header_c104_message_id_wd = reg_wdata[7:0]; - - assign message_header_c104_message_type_we = addr_hit[1046] & reg_we & !reg_error; - assign message_header_c104_message_type_wd = reg_wdata[9:8]; - - assign message_header_c104_protocol_id_we = addr_hit[1046] & reg_we & !reg_error; - assign message_header_c104_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c104_token_we = addr_hit[1046] & reg_we & !reg_error; - assign message_header_c104_token_wd = reg_wdata[27:18]; - - assign message_header_c104_field1_we = addr_hit[1046] & reg_we & !reg_error; - assign message_header_c104_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c104_we = addr_hit[1047] & reg_we & !reg_error; - assign message_payload_1_c104_wd = reg_wdata[31:0]; - - assign doorbell_c104_intr_we = addr_hit[1048] & reg_we & !reg_error; - assign doorbell_c104_intr_wd = reg_wdata[0]; - - assign doorbell_c104_preserve_mask_we = addr_hit[1048] & reg_we & !reg_error; - assign doorbell_c104_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c104_intr_we = addr_hit[1049] & reg_we & !reg_error; - assign completion_interrupt_c104_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c104_preserve_mask_we = addr_hit[1049] & reg_we & !reg_error; - assign completion_interrupt_c104_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c105_we = addr_hit[1050] & reg_we & !reg_error; - assign reserved_1_c105_wd = reg_wdata[31:0]; - - assign channel_status_c105_channel_free_we = addr_hit[1051] & reg_we & !reg_error; - assign channel_status_c105_channel_free_wd = reg_wdata[0]; - - assign channel_status_c105_channel_error_we = addr_hit[1051] & reg_we & !reg_error; - assign channel_status_c105_channel_error_wd = reg_wdata[1]; - - assign channel_status_c105_field1_we = addr_hit[1051] & reg_we & !reg_error; - assign channel_status_c105_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c105_we = addr_hit[1052] & reg_we & !reg_error; - assign reserved_2_c105_wd = reg_wdata[31:0]; - - assign channel_flags_c105_intr_enable_we = addr_hit[1054] & reg_we & !reg_error; - assign channel_flags_c105_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c105_field1_we = addr_hit[1054] & reg_we & !reg_error; - assign channel_flags_c105_field1_wd = reg_wdata[31:1]; - - assign length_c105_we = addr_hit[1055] & reg_we & !reg_error; - assign length_c105_wd = reg_wdata[31:0]; - - assign message_header_c105_message_id_we = addr_hit[1056] & reg_we & !reg_error; - assign message_header_c105_message_id_wd = reg_wdata[7:0]; - - assign message_header_c105_message_type_we = addr_hit[1056] & reg_we & !reg_error; - assign message_header_c105_message_type_wd = reg_wdata[9:8]; - - assign message_header_c105_protocol_id_we = addr_hit[1056] & reg_we & !reg_error; - assign message_header_c105_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c105_token_we = addr_hit[1056] & reg_we & !reg_error; - assign message_header_c105_token_wd = reg_wdata[27:18]; - - assign message_header_c105_field1_we = addr_hit[1056] & reg_we & !reg_error; - assign message_header_c105_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c105_we = addr_hit[1057] & reg_we & !reg_error; - assign message_payload_1_c105_wd = reg_wdata[31:0]; - - assign doorbell_c105_intr_we = addr_hit[1058] & reg_we & !reg_error; - assign doorbell_c105_intr_wd = reg_wdata[0]; - - assign doorbell_c105_preserve_mask_we = addr_hit[1058] & reg_we & !reg_error; - assign doorbell_c105_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c105_intr_we = addr_hit[1059] & reg_we & !reg_error; - assign completion_interrupt_c105_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c105_preserve_mask_we = addr_hit[1059] & reg_we & !reg_error; - assign completion_interrupt_c105_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c106_we = addr_hit[1060] & reg_we & !reg_error; - assign reserved_1_c106_wd = reg_wdata[31:0]; - - assign channel_status_c106_channel_free_we = addr_hit[1061] & reg_we & !reg_error; - assign channel_status_c106_channel_free_wd = reg_wdata[0]; - - assign channel_status_c106_channel_error_we = addr_hit[1061] & reg_we & !reg_error; - assign channel_status_c106_channel_error_wd = reg_wdata[1]; - - assign channel_status_c106_field1_we = addr_hit[1061] & reg_we & !reg_error; - assign channel_status_c106_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c106_we = addr_hit[1062] & reg_we & !reg_error; - assign reserved_2_c106_wd = reg_wdata[31:0]; - - assign channel_flags_c106_intr_enable_we = addr_hit[1064] & reg_we & !reg_error; - assign channel_flags_c106_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c106_field1_we = addr_hit[1064] & reg_we & !reg_error; - assign channel_flags_c106_field1_wd = reg_wdata[31:1]; - - assign length_c106_we = addr_hit[1065] & reg_we & !reg_error; - assign length_c106_wd = reg_wdata[31:0]; - - assign message_header_c106_message_id_we = addr_hit[1066] & reg_we & !reg_error; - assign message_header_c106_message_id_wd = reg_wdata[7:0]; - - assign message_header_c106_message_type_we = addr_hit[1066] & reg_we & !reg_error; - assign message_header_c106_message_type_wd = reg_wdata[9:8]; - - assign message_header_c106_protocol_id_we = addr_hit[1066] & reg_we & !reg_error; - assign message_header_c106_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c106_token_we = addr_hit[1066] & reg_we & !reg_error; - assign message_header_c106_token_wd = reg_wdata[27:18]; - - assign message_header_c106_field1_we = addr_hit[1066] & reg_we & !reg_error; - assign message_header_c106_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c106_we = addr_hit[1067] & reg_we & !reg_error; - assign message_payload_1_c106_wd = reg_wdata[31:0]; - - assign doorbell_c106_intr_we = addr_hit[1068] & reg_we & !reg_error; - assign doorbell_c106_intr_wd = reg_wdata[0]; - - assign doorbell_c106_preserve_mask_we = addr_hit[1068] & reg_we & !reg_error; - assign doorbell_c106_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c106_intr_we = addr_hit[1069] & reg_we & !reg_error; - assign completion_interrupt_c106_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c106_preserve_mask_we = addr_hit[1069] & reg_we & !reg_error; - assign completion_interrupt_c106_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c107_we = addr_hit[1070] & reg_we & !reg_error; - assign reserved_1_c107_wd = reg_wdata[31:0]; - - assign channel_status_c107_channel_free_we = addr_hit[1071] & reg_we & !reg_error; - assign channel_status_c107_channel_free_wd = reg_wdata[0]; - - assign channel_status_c107_channel_error_we = addr_hit[1071] & reg_we & !reg_error; - assign channel_status_c107_channel_error_wd = reg_wdata[1]; - - assign channel_status_c107_field1_we = addr_hit[1071] & reg_we & !reg_error; - assign channel_status_c107_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c107_we = addr_hit[1072] & reg_we & !reg_error; - assign reserved_2_c107_wd = reg_wdata[31:0]; - - assign channel_flags_c107_intr_enable_we = addr_hit[1074] & reg_we & !reg_error; - assign channel_flags_c107_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c107_field1_we = addr_hit[1074] & reg_we & !reg_error; - assign channel_flags_c107_field1_wd = reg_wdata[31:1]; - - assign length_c107_we = addr_hit[1075] & reg_we & !reg_error; - assign length_c107_wd = reg_wdata[31:0]; - - assign message_header_c107_message_id_we = addr_hit[1076] & reg_we & !reg_error; - assign message_header_c107_message_id_wd = reg_wdata[7:0]; - - assign message_header_c107_message_type_we = addr_hit[1076] & reg_we & !reg_error; - assign message_header_c107_message_type_wd = reg_wdata[9:8]; - - assign message_header_c107_protocol_id_we = addr_hit[1076] & reg_we & !reg_error; - assign message_header_c107_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c107_token_we = addr_hit[1076] & reg_we & !reg_error; - assign message_header_c107_token_wd = reg_wdata[27:18]; - - assign message_header_c107_field1_we = addr_hit[1076] & reg_we & !reg_error; - assign message_header_c107_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c107_we = addr_hit[1077] & reg_we & !reg_error; - assign message_payload_1_c107_wd = reg_wdata[31:0]; - - assign doorbell_c107_intr_we = addr_hit[1078] & reg_we & !reg_error; - assign doorbell_c107_intr_wd = reg_wdata[0]; - - assign doorbell_c107_preserve_mask_we = addr_hit[1078] & reg_we & !reg_error; - assign doorbell_c107_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c107_intr_we = addr_hit[1079] & reg_we & !reg_error; - assign completion_interrupt_c107_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c107_preserve_mask_we = addr_hit[1079] & reg_we & !reg_error; - assign completion_interrupt_c107_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c108_we = addr_hit[1080] & reg_we & !reg_error; - assign reserved_1_c108_wd = reg_wdata[31:0]; - - assign channel_status_c108_channel_free_we = addr_hit[1081] & reg_we & !reg_error; - assign channel_status_c108_channel_free_wd = reg_wdata[0]; - - assign channel_status_c108_channel_error_we = addr_hit[1081] & reg_we & !reg_error; - assign channel_status_c108_channel_error_wd = reg_wdata[1]; - - assign channel_status_c108_field1_we = addr_hit[1081] & reg_we & !reg_error; - assign channel_status_c108_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c108_we = addr_hit[1082] & reg_we & !reg_error; - assign reserved_2_c108_wd = reg_wdata[31:0]; - - assign channel_flags_c108_intr_enable_we = addr_hit[1084] & reg_we & !reg_error; - assign channel_flags_c108_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c108_field1_we = addr_hit[1084] & reg_we & !reg_error; - assign channel_flags_c108_field1_wd = reg_wdata[31:1]; - - assign length_c108_we = addr_hit[1085] & reg_we & !reg_error; - assign length_c108_wd = reg_wdata[31:0]; - - assign message_header_c108_message_id_we = addr_hit[1086] & reg_we & !reg_error; - assign message_header_c108_message_id_wd = reg_wdata[7:0]; - - assign message_header_c108_message_type_we = addr_hit[1086] & reg_we & !reg_error; - assign message_header_c108_message_type_wd = reg_wdata[9:8]; - - assign message_header_c108_protocol_id_we = addr_hit[1086] & reg_we & !reg_error; - assign message_header_c108_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c108_token_we = addr_hit[1086] & reg_we & !reg_error; - assign message_header_c108_token_wd = reg_wdata[27:18]; - - assign message_header_c108_field1_we = addr_hit[1086] & reg_we & !reg_error; - assign message_header_c108_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c108_we = addr_hit[1087] & reg_we & !reg_error; - assign message_payload_1_c108_wd = reg_wdata[31:0]; - - assign doorbell_c108_intr_we = addr_hit[1088] & reg_we & !reg_error; - assign doorbell_c108_intr_wd = reg_wdata[0]; - - assign doorbell_c108_preserve_mask_we = addr_hit[1088] & reg_we & !reg_error; - assign doorbell_c108_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c108_intr_we = addr_hit[1089] & reg_we & !reg_error; - assign completion_interrupt_c108_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c108_preserve_mask_we = addr_hit[1089] & reg_we & !reg_error; - assign completion_interrupt_c108_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c109_we = addr_hit[1090] & reg_we & !reg_error; - assign reserved_1_c109_wd = reg_wdata[31:0]; - - assign channel_status_c109_channel_free_we = addr_hit[1091] & reg_we & !reg_error; - assign channel_status_c109_channel_free_wd = reg_wdata[0]; - - assign channel_status_c109_channel_error_we = addr_hit[1091] & reg_we & !reg_error; - assign channel_status_c109_channel_error_wd = reg_wdata[1]; - - assign channel_status_c109_field1_we = addr_hit[1091] & reg_we & !reg_error; - assign channel_status_c109_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c109_we = addr_hit[1092] & reg_we & !reg_error; - assign reserved_2_c109_wd = reg_wdata[31:0]; - - assign channel_flags_c109_intr_enable_we = addr_hit[1094] & reg_we & !reg_error; - assign channel_flags_c109_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c109_field1_we = addr_hit[1094] & reg_we & !reg_error; - assign channel_flags_c109_field1_wd = reg_wdata[31:1]; - - assign length_c109_we = addr_hit[1095] & reg_we & !reg_error; - assign length_c109_wd = reg_wdata[31:0]; - - assign message_header_c109_message_id_we = addr_hit[1096] & reg_we & !reg_error; - assign message_header_c109_message_id_wd = reg_wdata[7:0]; - - assign message_header_c109_message_type_we = addr_hit[1096] & reg_we & !reg_error; - assign message_header_c109_message_type_wd = reg_wdata[9:8]; - - assign message_header_c109_protocol_id_we = addr_hit[1096] & reg_we & !reg_error; - assign message_header_c109_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c109_token_we = addr_hit[1096] & reg_we & !reg_error; - assign message_header_c109_token_wd = reg_wdata[27:18]; - - assign message_header_c109_field1_we = addr_hit[1096] & reg_we & !reg_error; - assign message_header_c109_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c109_we = addr_hit[1097] & reg_we & !reg_error; - assign message_payload_1_c109_wd = reg_wdata[31:0]; - - assign doorbell_c109_intr_we = addr_hit[1098] & reg_we & !reg_error; - assign doorbell_c109_intr_wd = reg_wdata[0]; - - assign doorbell_c109_preserve_mask_we = addr_hit[1098] & reg_we & !reg_error; - assign doorbell_c109_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c109_intr_we = addr_hit[1099] & reg_we & !reg_error; - assign completion_interrupt_c109_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c109_preserve_mask_we = addr_hit[1099] & reg_we & !reg_error; - assign completion_interrupt_c109_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c110_we = addr_hit[1100] & reg_we & !reg_error; - assign reserved_1_c110_wd = reg_wdata[31:0]; - - assign channel_status_c110_channel_free_we = addr_hit[1101] & reg_we & !reg_error; - assign channel_status_c110_channel_free_wd = reg_wdata[0]; - - assign channel_status_c110_channel_error_we = addr_hit[1101] & reg_we & !reg_error; - assign channel_status_c110_channel_error_wd = reg_wdata[1]; - - assign channel_status_c110_field1_we = addr_hit[1101] & reg_we & !reg_error; - assign channel_status_c110_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c110_we = addr_hit[1102] & reg_we & !reg_error; - assign reserved_2_c110_wd = reg_wdata[31:0]; - - assign channel_flags_c110_intr_enable_we = addr_hit[1104] & reg_we & !reg_error; - assign channel_flags_c110_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c110_field1_we = addr_hit[1104] & reg_we & !reg_error; - assign channel_flags_c110_field1_wd = reg_wdata[31:1]; - - assign length_c110_we = addr_hit[1105] & reg_we & !reg_error; - assign length_c110_wd = reg_wdata[31:0]; - - assign message_header_c110_message_id_we = addr_hit[1106] & reg_we & !reg_error; - assign message_header_c110_message_id_wd = reg_wdata[7:0]; - - assign message_header_c110_message_type_we = addr_hit[1106] & reg_we & !reg_error; - assign message_header_c110_message_type_wd = reg_wdata[9:8]; - - assign message_header_c110_protocol_id_we = addr_hit[1106] & reg_we & !reg_error; - assign message_header_c110_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c110_token_we = addr_hit[1106] & reg_we & !reg_error; - assign message_header_c110_token_wd = reg_wdata[27:18]; - - assign message_header_c110_field1_we = addr_hit[1106] & reg_we & !reg_error; - assign message_header_c110_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c110_we = addr_hit[1107] & reg_we & !reg_error; - assign message_payload_1_c110_wd = reg_wdata[31:0]; - - assign doorbell_c110_intr_we = addr_hit[1108] & reg_we & !reg_error; - assign doorbell_c110_intr_wd = reg_wdata[0]; - - assign doorbell_c110_preserve_mask_we = addr_hit[1108] & reg_we & !reg_error; - assign doorbell_c110_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c110_intr_we = addr_hit[1109] & reg_we & !reg_error; - assign completion_interrupt_c110_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c110_preserve_mask_we = addr_hit[1109] & reg_we & !reg_error; - assign completion_interrupt_c110_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c111_we = addr_hit[1110] & reg_we & !reg_error; - assign reserved_1_c111_wd = reg_wdata[31:0]; - - assign channel_status_c111_channel_free_we = addr_hit[1111] & reg_we & !reg_error; - assign channel_status_c111_channel_free_wd = reg_wdata[0]; - - assign channel_status_c111_channel_error_we = addr_hit[1111] & reg_we & !reg_error; - assign channel_status_c111_channel_error_wd = reg_wdata[1]; - - assign channel_status_c111_field1_we = addr_hit[1111] & reg_we & !reg_error; - assign channel_status_c111_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c111_we = addr_hit[1112] & reg_we & !reg_error; - assign reserved_2_c111_wd = reg_wdata[31:0]; - - assign channel_flags_c111_intr_enable_we = addr_hit[1114] & reg_we & !reg_error; - assign channel_flags_c111_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c111_field1_we = addr_hit[1114] & reg_we & !reg_error; - assign channel_flags_c111_field1_wd = reg_wdata[31:1]; - - assign length_c111_we = addr_hit[1115] & reg_we & !reg_error; - assign length_c111_wd = reg_wdata[31:0]; - - assign message_header_c111_message_id_we = addr_hit[1116] & reg_we & !reg_error; - assign message_header_c111_message_id_wd = reg_wdata[7:0]; - - assign message_header_c111_message_type_we = addr_hit[1116] & reg_we & !reg_error; - assign message_header_c111_message_type_wd = reg_wdata[9:8]; - - assign message_header_c111_protocol_id_we = addr_hit[1116] & reg_we & !reg_error; - assign message_header_c111_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c111_token_we = addr_hit[1116] & reg_we & !reg_error; - assign message_header_c111_token_wd = reg_wdata[27:18]; - - assign message_header_c111_field1_we = addr_hit[1116] & reg_we & !reg_error; - assign message_header_c111_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c111_we = addr_hit[1117] & reg_we & !reg_error; - assign message_payload_1_c111_wd = reg_wdata[31:0]; - - assign doorbell_c111_intr_we = addr_hit[1118] & reg_we & !reg_error; - assign doorbell_c111_intr_wd = reg_wdata[0]; - - assign doorbell_c111_preserve_mask_we = addr_hit[1118] & reg_we & !reg_error; - assign doorbell_c111_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c111_intr_we = addr_hit[1119] & reg_we & !reg_error; - assign completion_interrupt_c111_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c111_preserve_mask_we = addr_hit[1119] & reg_we & !reg_error; - assign completion_interrupt_c111_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c112_we = addr_hit[1120] & reg_we & !reg_error; - assign reserved_1_c112_wd = reg_wdata[31:0]; - - assign channel_status_c112_channel_free_we = addr_hit[1121] & reg_we & !reg_error; - assign channel_status_c112_channel_free_wd = reg_wdata[0]; - - assign channel_status_c112_channel_error_we = addr_hit[1121] & reg_we & !reg_error; - assign channel_status_c112_channel_error_wd = reg_wdata[1]; - - assign channel_status_c112_field1_we = addr_hit[1121] & reg_we & !reg_error; - assign channel_status_c112_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c112_we = addr_hit[1122] & reg_we & !reg_error; - assign reserved_2_c112_wd = reg_wdata[31:0]; - - assign channel_flags_c112_intr_enable_we = addr_hit[1124] & reg_we & !reg_error; - assign channel_flags_c112_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c112_field1_we = addr_hit[1124] & reg_we & !reg_error; - assign channel_flags_c112_field1_wd = reg_wdata[31:1]; - - assign length_c112_we = addr_hit[1125] & reg_we & !reg_error; - assign length_c112_wd = reg_wdata[31:0]; - - assign message_header_c112_message_id_we = addr_hit[1126] & reg_we & !reg_error; - assign message_header_c112_message_id_wd = reg_wdata[7:0]; - - assign message_header_c112_message_type_we = addr_hit[1126] & reg_we & !reg_error; - assign message_header_c112_message_type_wd = reg_wdata[9:8]; - - assign message_header_c112_protocol_id_we = addr_hit[1126] & reg_we & !reg_error; - assign message_header_c112_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c112_token_we = addr_hit[1126] & reg_we & !reg_error; - assign message_header_c112_token_wd = reg_wdata[27:18]; - - assign message_header_c112_field1_we = addr_hit[1126] & reg_we & !reg_error; - assign message_header_c112_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c112_we = addr_hit[1127] & reg_we & !reg_error; - assign message_payload_1_c112_wd = reg_wdata[31:0]; - - assign doorbell_c112_intr_we = addr_hit[1128] & reg_we & !reg_error; - assign doorbell_c112_intr_wd = reg_wdata[0]; - - assign doorbell_c112_preserve_mask_we = addr_hit[1128] & reg_we & !reg_error; - assign doorbell_c112_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c112_intr_we = addr_hit[1129] & reg_we & !reg_error; - assign completion_interrupt_c112_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c112_preserve_mask_we = addr_hit[1129] & reg_we & !reg_error; - assign completion_interrupt_c112_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c113_we = addr_hit[1130] & reg_we & !reg_error; - assign reserved_1_c113_wd = reg_wdata[31:0]; - - assign channel_status_c113_channel_free_we = addr_hit[1131] & reg_we & !reg_error; - assign channel_status_c113_channel_free_wd = reg_wdata[0]; - - assign channel_status_c113_channel_error_we = addr_hit[1131] & reg_we & !reg_error; - assign channel_status_c113_channel_error_wd = reg_wdata[1]; - - assign channel_status_c113_field1_we = addr_hit[1131] & reg_we & !reg_error; - assign channel_status_c113_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c113_we = addr_hit[1132] & reg_we & !reg_error; - assign reserved_2_c113_wd = reg_wdata[31:0]; - - assign channel_flags_c113_intr_enable_we = addr_hit[1134] & reg_we & !reg_error; - assign channel_flags_c113_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c113_field1_we = addr_hit[1134] & reg_we & !reg_error; - assign channel_flags_c113_field1_wd = reg_wdata[31:1]; - - assign length_c113_we = addr_hit[1135] & reg_we & !reg_error; - assign length_c113_wd = reg_wdata[31:0]; - - assign message_header_c113_message_id_we = addr_hit[1136] & reg_we & !reg_error; - assign message_header_c113_message_id_wd = reg_wdata[7:0]; - - assign message_header_c113_message_type_we = addr_hit[1136] & reg_we & !reg_error; - assign message_header_c113_message_type_wd = reg_wdata[9:8]; - - assign message_header_c113_protocol_id_we = addr_hit[1136] & reg_we & !reg_error; - assign message_header_c113_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c113_token_we = addr_hit[1136] & reg_we & !reg_error; - assign message_header_c113_token_wd = reg_wdata[27:18]; - - assign message_header_c113_field1_we = addr_hit[1136] & reg_we & !reg_error; - assign message_header_c113_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c113_we = addr_hit[1137] & reg_we & !reg_error; - assign message_payload_1_c113_wd = reg_wdata[31:0]; - - assign doorbell_c113_intr_we = addr_hit[1138] & reg_we & !reg_error; - assign doorbell_c113_intr_wd = reg_wdata[0]; - - assign doorbell_c113_preserve_mask_we = addr_hit[1138] & reg_we & !reg_error; - assign doorbell_c113_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c113_intr_we = addr_hit[1139] & reg_we & !reg_error; - assign completion_interrupt_c113_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c113_preserve_mask_we = addr_hit[1139] & reg_we & !reg_error; - assign completion_interrupt_c113_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c114_we = addr_hit[1140] & reg_we & !reg_error; - assign reserved_1_c114_wd = reg_wdata[31:0]; - - assign channel_status_c114_channel_free_we = addr_hit[1141] & reg_we & !reg_error; - assign channel_status_c114_channel_free_wd = reg_wdata[0]; - - assign channel_status_c114_channel_error_we = addr_hit[1141] & reg_we & !reg_error; - assign channel_status_c114_channel_error_wd = reg_wdata[1]; - - assign channel_status_c114_field1_we = addr_hit[1141] & reg_we & !reg_error; - assign channel_status_c114_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c114_we = addr_hit[1142] & reg_we & !reg_error; - assign reserved_2_c114_wd = reg_wdata[31:0]; - - assign channel_flags_c114_intr_enable_we = addr_hit[1144] & reg_we & !reg_error; - assign channel_flags_c114_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c114_field1_we = addr_hit[1144] & reg_we & !reg_error; - assign channel_flags_c114_field1_wd = reg_wdata[31:1]; - - assign length_c114_we = addr_hit[1145] & reg_we & !reg_error; - assign length_c114_wd = reg_wdata[31:0]; - - assign message_header_c114_message_id_we = addr_hit[1146] & reg_we & !reg_error; - assign message_header_c114_message_id_wd = reg_wdata[7:0]; - - assign message_header_c114_message_type_we = addr_hit[1146] & reg_we & !reg_error; - assign message_header_c114_message_type_wd = reg_wdata[9:8]; - - assign message_header_c114_protocol_id_we = addr_hit[1146] & reg_we & !reg_error; - assign message_header_c114_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c114_token_we = addr_hit[1146] & reg_we & !reg_error; - assign message_header_c114_token_wd = reg_wdata[27:18]; - - assign message_header_c114_field1_we = addr_hit[1146] & reg_we & !reg_error; - assign message_header_c114_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c114_we = addr_hit[1147] & reg_we & !reg_error; - assign message_payload_1_c114_wd = reg_wdata[31:0]; - - assign doorbell_c114_intr_we = addr_hit[1148] & reg_we & !reg_error; - assign doorbell_c114_intr_wd = reg_wdata[0]; - - assign doorbell_c114_preserve_mask_we = addr_hit[1148] & reg_we & !reg_error; - assign doorbell_c114_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c114_intr_we = addr_hit[1149] & reg_we & !reg_error; - assign completion_interrupt_c114_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c114_preserve_mask_we = addr_hit[1149] & reg_we & !reg_error; - assign completion_interrupt_c114_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c115_we = addr_hit[1150] & reg_we & !reg_error; - assign reserved_1_c115_wd = reg_wdata[31:0]; - - assign channel_status_c115_channel_free_we = addr_hit[1151] & reg_we & !reg_error; - assign channel_status_c115_channel_free_wd = reg_wdata[0]; - - assign channel_status_c115_channel_error_we = addr_hit[1151] & reg_we & !reg_error; - assign channel_status_c115_channel_error_wd = reg_wdata[1]; - - assign channel_status_c115_field1_we = addr_hit[1151] & reg_we & !reg_error; - assign channel_status_c115_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c115_we = addr_hit[1152] & reg_we & !reg_error; - assign reserved_2_c115_wd = reg_wdata[31:0]; - - assign channel_flags_c115_intr_enable_we = addr_hit[1154] & reg_we & !reg_error; - assign channel_flags_c115_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c115_field1_we = addr_hit[1154] & reg_we & !reg_error; - assign channel_flags_c115_field1_wd = reg_wdata[31:1]; - - assign length_c115_we = addr_hit[1155] & reg_we & !reg_error; - assign length_c115_wd = reg_wdata[31:0]; - - assign message_header_c115_message_id_we = addr_hit[1156] & reg_we & !reg_error; - assign message_header_c115_message_id_wd = reg_wdata[7:0]; - - assign message_header_c115_message_type_we = addr_hit[1156] & reg_we & !reg_error; - assign message_header_c115_message_type_wd = reg_wdata[9:8]; - - assign message_header_c115_protocol_id_we = addr_hit[1156] & reg_we & !reg_error; - assign message_header_c115_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c115_token_we = addr_hit[1156] & reg_we & !reg_error; - assign message_header_c115_token_wd = reg_wdata[27:18]; - - assign message_header_c115_field1_we = addr_hit[1156] & reg_we & !reg_error; - assign message_header_c115_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c115_we = addr_hit[1157] & reg_we & !reg_error; - assign message_payload_1_c115_wd = reg_wdata[31:0]; - - assign doorbell_c115_intr_we = addr_hit[1158] & reg_we & !reg_error; - assign doorbell_c115_intr_wd = reg_wdata[0]; - - assign doorbell_c115_preserve_mask_we = addr_hit[1158] & reg_we & !reg_error; - assign doorbell_c115_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c115_intr_we = addr_hit[1159] & reg_we & !reg_error; - assign completion_interrupt_c115_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c115_preserve_mask_we = addr_hit[1159] & reg_we & !reg_error; - assign completion_interrupt_c115_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c116_we = addr_hit[1160] & reg_we & !reg_error; - assign reserved_1_c116_wd = reg_wdata[31:0]; - - assign channel_status_c116_channel_free_we = addr_hit[1161] & reg_we & !reg_error; - assign channel_status_c116_channel_free_wd = reg_wdata[0]; - - assign channel_status_c116_channel_error_we = addr_hit[1161] & reg_we & !reg_error; - assign channel_status_c116_channel_error_wd = reg_wdata[1]; - - assign channel_status_c116_field1_we = addr_hit[1161] & reg_we & !reg_error; - assign channel_status_c116_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c116_we = addr_hit[1162] & reg_we & !reg_error; - assign reserved_2_c116_wd = reg_wdata[31:0]; - - assign channel_flags_c116_intr_enable_we = addr_hit[1164] & reg_we & !reg_error; - assign channel_flags_c116_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c116_field1_we = addr_hit[1164] & reg_we & !reg_error; - assign channel_flags_c116_field1_wd = reg_wdata[31:1]; - - assign length_c116_we = addr_hit[1165] & reg_we & !reg_error; - assign length_c116_wd = reg_wdata[31:0]; - - assign message_header_c116_message_id_we = addr_hit[1166] & reg_we & !reg_error; - assign message_header_c116_message_id_wd = reg_wdata[7:0]; - - assign message_header_c116_message_type_we = addr_hit[1166] & reg_we & !reg_error; - assign message_header_c116_message_type_wd = reg_wdata[9:8]; - - assign message_header_c116_protocol_id_we = addr_hit[1166] & reg_we & !reg_error; - assign message_header_c116_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c116_token_we = addr_hit[1166] & reg_we & !reg_error; - assign message_header_c116_token_wd = reg_wdata[27:18]; - - assign message_header_c116_field1_we = addr_hit[1166] & reg_we & !reg_error; - assign message_header_c116_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c116_we = addr_hit[1167] & reg_we & !reg_error; - assign message_payload_1_c116_wd = reg_wdata[31:0]; - - assign doorbell_c116_intr_we = addr_hit[1168] & reg_we & !reg_error; - assign doorbell_c116_intr_wd = reg_wdata[0]; - - assign doorbell_c116_preserve_mask_we = addr_hit[1168] & reg_we & !reg_error; - assign doorbell_c116_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c116_intr_we = addr_hit[1169] & reg_we & !reg_error; - assign completion_interrupt_c116_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c116_preserve_mask_we = addr_hit[1169] & reg_we & !reg_error; - assign completion_interrupt_c116_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c117_we = addr_hit[1170] & reg_we & !reg_error; - assign reserved_1_c117_wd = reg_wdata[31:0]; - - assign channel_status_c117_channel_free_we = addr_hit[1171] & reg_we & !reg_error; - assign channel_status_c117_channel_free_wd = reg_wdata[0]; - - assign channel_status_c117_channel_error_we = addr_hit[1171] & reg_we & !reg_error; - assign channel_status_c117_channel_error_wd = reg_wdata[1]; - - assign channel_status_c117_field1_we = addr_hit[1171] & reg_we & !reg_error; - assign channel_status_c117_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c117_we = addr_hit[1172] & reg_we & !reg_error; - assign reserved_2_c117_wd = reg_wdata[31:0]; - - assign channel_flags_c117_intr_enable_we = addr_hit[1174] & reg_we & !reg_error; - assign channel_flags_c117_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c117_field1_we = addr_hit[1174] & reg_we & !reg_error; - assign channel_flags_c117_field1_wd = reg_wdata[31:1]; - - assign length_c117_we = addr_hit[1175] & reg_we & !reg_error; - assign length_c117_wd = reg_wdata[31:0]; - - assign message_header_c117_message_id_we = addr_hit[1176] & reg_we & !reg_error; - assign message_header_c117_message_id_wd = reg_wdata[7:0]; - - assign message_header_c117_message_type_we = addr_hit[1176] & reg_we & !reg_error; - assign message_header_c117_message_type_wd = reg_wdata[9:8]; - - assign message_header_c117_protocol_id_we = addr_hit[1176] & reg_we & !reg_error; - assign message_header_c117_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c117_token_we = addr_hit[1176] & reg_we & !reg_error; - assign message_header_c117_token_wd = reg_wdata[27:18]; - - assign message_header_c117_field1_we = addr_hit[1176] & reg_we & !reg_error; - assign message_header_c117_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c117_we = addr_hit[1177] & reg_we & !reg_error; - assign message_payload_1_c117_wd = reg_wdata[31:0]; - - assign doorbell_c117_intr_we = addr_hit[1178] & reg_we & !reg_error; - assign doorbell_c117_intr_wd = reg_wdata[0]; - - assign doorbell_c117_preserve_mask_we = addr_hit[1178] & reg_we & !reg_error; - assign doorbell_c117_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c117_intr_we = addr_hit[1179] & reg_we & !reg_error; - assign completion_interrupt_c117_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c117_preserve_mask_we = addr_hit[1179] & reg_we & !reg_error; - assign completion_interrupt_c117_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c118_we = addr_hit[1180] & reg_we & !reg_error; - assign reserved_1_c118_wd = reg_wdata[31:0]; - - assign channel_status_c118_channel_free_we = addr_hit[1181] & reg_we & !reg_error; - assign channel_status_c118_channel_free_wd = reg_wdata[0]; - - assign channel_status_c118_channel_error_we = addr_hit[1181] & reg_we & !reg_error; - assign channel_status_c118_channel_error_wd = reg_wdata[1]; - - assign channel_status_c118_field1_we = addr_hit[1181] & reg_we & !reg_error; - assign channel_status_c118_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c118_we = addr_hit[1182] & reg_we & !reg_error; - assign reserved_2_c118_wd = reg_wdata[31:0]; - - assign channel_flags_c118_intr_enable_we = addr_hit[1184] & reg_we & !reg_error; - assign channel_flags_c118_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c118_field1_we = addr_hit[1184] & reg_we & !reg_error; - assign channel_flags_c118_field1_wd = reg_wdata[31:1]; - - assign length_c118_we = addr_hit[1185] & reg_we & !reg_error; - assign length_c118_wd = reg_wdata[31:0]; - - assign message_header_c118_message_id_we = addr_hit[1186] & reg_we & !reg_error; - assign message_header_c118_message_id_wd = reg_wdata[7:0]; - - assign message_header_c118_message_type_we = addr_hit[1186] & reg_we & !reg_error; - assign message_header_c118_message_type_wd = reg_wdata[9:8]; - - assign message_header_c118_protocol_id_we = addr_hit[1186] & reg_we & !reg_error; - assign message_header_c118_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c118_token_we = addr_hit[1186] & reg_we & !reg_error; - assign message_header_c118_token_wd = reg_wdata[27:18]; - - assign message_header_c118_field1_we = addr_hit[1186] & reg_we & !reg_error; - assign message_header_c118_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c118_we = addr_hit[1187] & reg_we & !reg_error; - assign message_payload_1_c118_wd = reg_wdata[31:0]; - - assign doorbell_c118_intr_we = addr_hit[1188] & reg_we & !reg_error; - assign doorbell_c118_intr_wd = reg_wdata[0]; - - assign doorbell_c118_preserve_mask_we = addr_hit[1188] & reg_we & !reg_error; - assign doorbell_c118_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c118_intr_we = addr_hit[1189] & reg_we & !reg_error; - assign completion_interrupt_c118_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c118_preserve_mask_we = addr_hit[1189] & reg_we & !reg_error; - assign completion_interrupt_c118_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c119_we = addr_hit[1190] & reg_we & !reg_error; - assign reserved_1_c119_wd = reg_wdata[31:0]; - - assign channel_status_c119_channel_free_we = addr_hit[1191] & reg_we & !reg_error; - assign channel_status_c119_channel_free_wd = reg_wdata[0]; - - assign channel_status_c119_channel_error_we = addr_hit[1191] & reg_we & !reg_error; - assign channel_status_c119_channel_error_wd = reg_wdata[1]; - - assign channel_status_c119_field1_we = addr_hit[1191] & reg_we & !reg_error; - assign channel_status_c119_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c119_we = addr_hit[1192] & reg_we & !reg_error; - assign reserved_2_c119_wd = reg_wdata[31:0]; - - assign channel_flags_c119_intr_enable_we = addr_hit[1194] & reg_we & !reg_error; - assign channel_flags_c119_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c119_field1_we = addr_hit[1194] & reg_we & !reg_error; - assign channel_flags_c119_field1_wd = reg_wdata[31:1]; - - assign length_c119_we = addr_hit[1195] & reg_we & !reg_error; - assign length_c119_wd = reg_wdata[31:0]; - - assign message_header_c119_message_id_we = addr_hit[1196] & reg_we & !reg_error; - assign message_header_c119_message_id_wd = reg_wdata[7:0]; - - assign message_header_c119_message_type_we = addr_hit[1196] & reg_we & !reg_error; - assign message_header_c119_message_type_wd = reg_wdata[9:8]; - - assign message_header_c119_protocol_id_we = addr_hit[1196] & reg_we & !reg_error; - assign message_header_c119_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c119_token_we = addr_hit[1196] & reg_we & !reg_error; - assign message_header_c119_token_wd = reg_wdata[27:18]; - - assign message_header_c119_field1_we = addr_hit[1196] & reg_we & !reg_error; - assign message_header_c119_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c119_we = addr_hit[1197] & reg_we & !reg_error; - assign message_payload_1_c119_wd = reg_wdata[31:0]; - - assign doorbell_c119_intr_we = addr_hit[1198] & reg_we & !reg_error; - assign doorbell_c119_intr_wd = reg_wdata[0]; - - assign doorbell_c119_preserve_mask_we = addr_hit[1198] & reg_we & !reg_error; - assign doorbell_c119_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c119_intr_we = addr_hit[1199] & reg_we & !reg_error; - assign completion_interrupt_c119_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c119_preserve_mask_we = addr_hit[1199] & reg_we & !reg_error; - assign completion_interrupt_c119_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c120_we = addr_hit[1200] & reg_we & !reg_error; - assign reserved_1_c120_wd = reg_wdata[31:0]; - - assign channel_status_c120_channel_free_we = addr_hit[1201] & reg_we & !reg_error; - assign channel_status_c120_channel_free_wd = reg_wdata[0]; - - assign channel_status_c120_channel_error_we = addr_hit[1201] & reg_we & !reg_error; - assign channel_status_c120_channel_error_wd = reg_wdata[1]; - - assign channel_status_c120_field1_we = addr_hit[1201] & reg_we & !reg_error; - assign channel_status_c120_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c120_we = addr_hit[1202] & reg_we & !reg_error; - assign reserved_2_c120_wd = reg_wdata[31:0]; - - assign channel_flags_c120_intr_enable_we = addr_hit[1204] & reg_we & !reg_error; - assign channel_flags_c120_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c120_field1_we = addr_hit[1204] & reg_we & !reg_error; - assign channel_flags_c120_field1_wd = reg_wdata[31:1]; - - assign length_c120_we = addr_hit[1205] & reg_we & !reg_error; - assign length_c120_wd = reg_wdata[31:0]; - - assign message_header_c120_message_id_we = addr_hit[1206] & reg_we & !reg_error; - assign message_header_c120_message_id_wd = reg_wdata[7:0]; - - assign message_header_c120_message_type_we = addr_hit[1206] & reg_we & !reg_error; - assign message_header_c120_message_type_wd = reg_wdata[9:8]; - - assign message_header_c120_protocol_id_we = addr_hit[1206] & reg_we & !reg_error; - assign message_header_c120_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c120_token_we = addr_hit[1206] & reg_we & !reg_error; - assign message_header_c120_token_wd = reg_wdata[27:18]; - - assign message_header_c120_field1_we = addr_hit[1206] & reg_we & !reg_error; - assign message_header_c120_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c120_we = addr_hit[1207] & reg_we & !reg_error; - assign message_payload_1_c120_wd = reg_wdata[31:0]; - - assign doorbell_c120_intr_we = addr_hit[1208] & reg_we & !reg_error; - assign doorbell_c120_intr_wd = reg_wdata[0]; - - assign doorbell_c120_preserve_mask_we = addr_hit[1208] & reg_we & !reg_error; - assign doorbell_c120_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c120_intr_we = addr_hit[1209] & reg_we & !reg_error; - assign completion_interrupt_c120_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c120_preserve_mask_we = addr_hit[1209] & reg_we & !reg_error; - assign completion_interrupt_c120_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c121_we = addr_hit[1210] & reg_we & !reg_error; - assign reserved_1_c121_wd = reg_wdata[31:0]; - - assign channel_status_c121_channel_free_we = addr_hit[1211] & reg_we & !reg_error; - assign channel_status_c121_channel_free_wd = reg_wdata[0]; - - assign channel_status_c121_channel_error_we = addr_hit[1211] & reg_we & !reg_error; - assign channel_status_c121_channel_error_wd = reg_wdata[1]; - - assign channel_status_c121_field1_we = addr_hit[1211] & reg_we & !reg_error; - assign channel_status_c121_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c121_we = addr_hit[1212] & reg_we & !reg_error; - assign reserved_2_c121_wd = reg_wdata[31:0]; - - assign channel_flags_c121_intr_enable_we = addr_hit[1214] & reg_we & !reg_error; - assign channel_flags_c121_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c121_field1_we = addr_hit[1214] & reg_we & !reg_error; - assign channel_flags_c121_field1_wd = reg_wdata[31:1]; - - assign length_c121_we = addr_hit[1215] & reg_we & !reg_error; - assign length_c121_wd = reg_wdata[31:0]; - - assign message_header_c121_message_id_we = addr_hit[1216] & reg_we & !reg_error; - assign message_header_c121_message_id_wd = reg_wdata[7:0]; - - assign message_header_c121_message_type_we = addr_hit[1216] & reg_we & !reg_error; - assign message_header_c121_message_type_wd = reg_wdata[9:8]; - - assign message_header_c121_protocol_id_we = addr_hit[1216] & reg_we & !reg_error; - assign message_header_c121_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c121_token_we = addr_hit[1216] & reg_we & !reg_error; - assign message_header_c121_token_wd = reg_wdata[27:18]; - - assign message_header_c121_field1_we = addr_hit[1216] & reg_we & !reg_error; - assign message_header_c121_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c121_we = addr_hit[1217] & reg_we & !reg_error; - assign message_payload_1_c121_wd = reg_wdata[31:0]; - - assign doorbell_c121_intr_we = addr_hit[1218] & reg_we & !reg_error; - assign doorbell_c121_intr_wd = reg_wdata[0]; - - assign doorbell_c121_preserve_mask_we = addr_hit[1218] & reg_we & !reg_error; - assign doorbell_c121_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c121_intr_we = addr_hit[1219] & reg_we & !reg_error; - assign completion_interrupt_c121_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c121_preserve_mask_we = addr_hit[1219] & reg_we & !reg_error; - assign completion_interrupt_c121_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c122_we = addr_hit[1220] & reg_we & !reg_error; - assign reserved_1_c122_wd = reg_wdata[31:0]; - - assign channel_status_c122_channel_free_we = addr_hit[1221] & reg_we & !reg_error; - assign channel_status_c122_channel_free_wd = reg_wdata[0]; - - assign channel_status_c122_channel_error_we = addr_hit[1221] & reg_we & !reg_error; - assign channel_status_c122_channel_error_wd = reg_wdata[1]; - - assign channel_status_c122_field1_we = addr_hit[1221] & reg_we & !reg_error; - assign channel_status_c122_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c122_we = addr_hit[1222] & reg_we & !reg_error; - assign reserved_2_c122_wd = reg_wdata[31:0]; - - assign channel_flags_c122_intr_enable_we = addr_hit[1224] & reg_we & !reg_error; - assign channel_flags_c122_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c122_field1_we = addr_hit[1224] & reg_we & !reg_error; - assign channel_flags_c122_field1_wd = reg_wdata[31:1]; - - assign length_c122_we = addr_hit[1225] & reg_we & !reg_error; - assign length_c122_wd = reg_wdata[31:0]; - - assign message_header_c122_message_id_we = addr_hit[1226] & reg_we & !reg_error; - assign message_header_c122_message_id_wd = reg_wdata[7:0]; - - assign message_header_c122_message_type_we = addr_hit[1226] & reg_we & !reg_error; - assign message_header_c122_message_type_wd = reg_wdata[9:8]; - - assign message_header_c122_protocol_id_we = addr_hit[1226] & reg_we & !reg_error; - assign message_header_c122_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c122_token_we = addr_hit[1226] & reg_we & !reg_error; - assign message_header_c122_token_wd = reg_wdata[27:18]; - - assign message_header_c122_field1_we = addr_hit[1226] & reg_we & !reg_error; - assign message_header_c122_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c122_we = addr_hit[1227] & reg_we & !reg_error; - assign message_payload_1_c122_wd = reg_wdata[31:0]; - - assign doorbell_c122_intr_we = addr_hit[1228] & reg_we & !reg_error; - assign doorbell_c122_intr_wd = reg_wdata[0]; - - assign doorbell_c122_preserve_mask_we = addr_hit[1228] & reg_we & !reg_error; - assign doorbell_c122_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c122_intr_we = addr_hit[1229] & reg_we & !reg_error; - assign completion_interrupt_c122_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c122_preserve_mask_we = addr_hit[1229] & reg_we & !reg_error; - assign completion_interrupt_c122_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c123_we = addr_hit[1230] & reg_we & !reg_error; - assign reserved_1_c123_wd = reg_wdata[31:0]; - - assign channel_status_c123_channel_free_we = addr_hit[1231] & reg_we & !reg_error; - assign channel_status_c123_channel_free_wd = reg_wdata[0]; - - assign channel_status_c123_channel_error_we = addr_hit[1231] & reg_we & !reg_error; - assign channel_status_c123_channel_error_wd = reg_wdata[1]; - - assign channel_status_c123_field1_we = addr_hit[1231] & reg_we & !reg_error; - assign channel_status_c123_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c123_we = addr_hit[1232] & reg_we & !reg_error; - assign reserved_2_c123_wd = reg_wdata[31:0]; - - assign channel_flags_c123_intr_enable_we = addr_hit[1234] & reg_we & !reg_error; - assign channel_flags_c123_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c123_field1_we = addr_hit[1234] & reg_we & !reg_error; - assign channel_flags_c123_field1_wd = reg_wdata[31:1]; - - assign length_c123_we = addr_hit[1235] & reg_we & !reg_error; - assign length_c123_wd = reg_wdata[31:0]; - - assign message_header_c123_message_id_we = addr_hit[1236] & reg_we & !reg_error; - assign message_header_c123_message_id_wd = reg_wdata[7:0]; - - assign message_header_c123_message_type_we = addr_hit[1236] & reg_we & !reg_error; - assign message_header_c123_message_type_wd = reg_wdata[9:8]; - - assign message_header_c123_protocol_id_we = addr_hit[1236] & reg_we & !reg_error; - assign message_header_c123_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c123_token_we = addr_hit[1236] & reg_we & !reg_error; - assign message_header_c123_token_wd = reg_wdata[27:18]; - - assign message_header_c123_field1_we = addr_hit[1236] & reg_we & !reg_error; - assign message_header_c123_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c123_we = addr_hit[1237] & reg_we & !reg_error; - assign message_payload_1_c123_wd = reg_wdata[31:0]; - - assign doorbell_c123_intr_we = addr_hit[1238] & reg_we & !reg_error; - assign doorbell_c123_intr_wd = reg_wdata[0]; - - assign doorbell_c123_preserve_mask_we = addr_hit[1238] & reg_we & !reg_error; - assign doorbell_c123_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c123_intr_we = addr_hit[1239] & reg_we & !reg_error; - assign completion_interrupt_c123_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c123_preserve_mask_we = addr_hit[1239] & reg_we & !reg_error; - assign completion_interrupt_c123_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c124_we = addr_hit[1240] & reg_we & !reg_error; - assign reserved_1_c124_wd = reg_wdata[31:0]; - - assign channel_status_c124_channel_free_we = addr_hit[1241] & reg_we & !reg_error; - assign channel_status_c124_channel_free_wd = reg_wdata[0]; - - assign channel_status_c124_channel_error_we = addr_hit[1241] & reg_we & !reg_error; - assign channel_status_c124_channel_error_wd = reg_wdata[1]; - - assign channel_status_c124_field1_we = addr_hit[1241] & reg_we & !reg_error; - assign channel_status_c124_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c124_we = addr_hit[1242] & reg_we & !reg_error; - assign reserved_2_c124_wd = reg_wdata[31:0]; - - assign channel_flags_c124_intr_enable_we = addr_hit[1244] & reg_we & !reg_error; - assign channel_flags_c124_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c124_field1_we = addr_hit[1244] & reg_we & !reg_error; - assign channel_flags_c124_field1_wd = reg_wdata[31:1]; - - assign length_c124_we = addr_hit[1245] & reg_we & !reg_error; - assign length_c124_wd = reg_wdata[31:0]; - - assign message_header_c124_message_id_we = addr_hit[1246] & reg_we & !reg_error; - assign message_header_c124_message_id_wd = reg_wdata[7:0]; - - assign message_header_c124_message_type_we = addr_hit[1246] & reg_we & !reg_error; - assign message_header_c124_message_type_wd = reg_wdata[9:8]; - - assign message_header_c124_protocol_id_we = addr_hit[1246] & reg_we & !reg_error; - assign message_header_c124_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c124_token_we = addr_hit[1246] & reg_we & !reg_error; - assign message_header_c124_token_wd = reg_wdata[27:18]; - - assign message_header_c124_field1_we = addr_hit[1246] & reg_we & !reg_error; - assign message_header_c124_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c124_we = addr_hit[1247] & reg_we & !reg_error; - assign message_payload_1_c124_wd = reg_wdata[31:0]; - - assign doorbell_c124_intr_we = addr_hit[1248] & reg_we & !reg_error; - assign doorbell_c124_intr_wd = reg_wdata[0]; - - assign doorbell_c124_preserve_mask_we = addr_hit[1248] & reg_we & !reg_error; - assign doorbell_c124_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c124_intr_we = addr_hit[1249] & reg_we & !reg_error; - assign completion_interrupt_c124_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c124_preserve_mask_we = addr_hit[1249] & reg_we & !reg_error; - assign completion_interrupt_c124_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c125_we = addr_hit[1250] & reg_we & !reg_error; - assign reserved_1_c125_wd = reg_wdata[31:0]; - - assign channel_status_c125_channel_free_we = addr_hit[1251] & reg_we & !reg_error; - assign channel_status_c125_channel_free_wd = reg_wdata[0]; - - assign channel_status_c125_channel_error_we = addr_hit[1251] & reg_we & !reg_error; - assign channel_status_c125_channel_error_wd = reg_wdata[1]; - - assign channel_status_c125_field1_we = addr_hit[1251] & reg_we & !reg_error; - assign channel_status_c125_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c125_we = addr_hit[1252] & reg_we & !reg_error; - assign reserved_2_c125_wd = reg_wdata[31:0]; - - assign channel_flags_c125_intr_enable_we = addr_hit[1254] & reg_we & !reg_error; - assign channel_flags_c125_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c125_field1_we = addr_hit[1254] & reg_we & !reg_error; - assign channel_flags_c125_field1_wd = reg_wdata[31:1]; - - assign length_c125_we = addr_hit[1255] & reg_we & !reg_error; - assign length_c125_wd = reg_wdata[31:0]; - - assign message_header_c125_message_id_we = addr_hit[1256] & reg_we & !reg_error; - assign message_header_c125_message_id_wd = reg_wdata[7:0]; - - assign message_header_c125_message_type_we = addr_hit[1256] & reg_we & !reg_error; - assign message_header_c125_message_type_wd = reg_wdata[9:8]; - - assign message_header_c125_protocol_id_we = addr_hit[1256] & reg_we & !reg_error; - assign message_header_c125_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c125_token_we = addr_hit[1256] & reg_we & !reg_error; - assign message_header_c125_token_wd = reg_wdata[27:18]; - - assign message_header_c125_field1_we = addr_hit[1256] & reg_we & !reg_error; - assign message_header_c125_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c125_we = addr_hit[1257] & reg_we & !reg_error; - assign message_payload_1_c125_wd = reg_wdata[31:0]; - - assign doorbell_c125_intr_we = addr_hit[1258] & reg_we & !reg_error; - assign doorbell_c125_intr_wd = reg_wdata[0]; - - assign doorbell_c125_preserve_mask_we = addr_hit[1258] & reg_we & !reg_error; - assign doorbell_c125_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c125_intr_we = addr_hit[1259] & reg_we & !reg_error; - assign completion_interrupt_c125_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c125_preserve_mask_we = addr_hit[1259] & reg_we & !reg_error; - assign completion_interrupt_c125_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c126_we = addr_hit[1260] & reg_we & !reg_error; - assign reserved_1_c126_wd = reg_wdata[31:0]; - - assign channel_status_c126_channel_free_we = addr_hit[1261] & reg_we & !reg_error; - assign channel_status_c126_channel_free_wd = reg_wdata[0]; - - assign channel_status_c126_channel_error_we = addr_hit[1261] & reg_we & !reg_error; - assign channel_status_c126_channel_error_wd = reg_wdata[1]; - - assign channel_status_c126_field1_we = addr_hit[1261] & reg_we & !reg_error; - assign channel_status_c126_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c126_we = addr_hit[1262] & reg_we & !reg_error; - assign reserved_2_c126_wd = reg_wdata[31:0]; - - assign channel_flags_c126_intr_enable_we = addr_hit[1264] & reg_we & !reg_error; - assign channel_flags_c126_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c126_field1_we = addr_hit[1264] & reg_we & !reg_error; - assign channel_flags_c126_field1_wd = reg_wdata[31:1]; - - assign length_c126_we = addr_hit[1265] & reg_we & !reg_error; - assign length_c126_wd = reg_wdata[31:0]; - - assign message_header_c126_message_id_we = addr_hit[1266] & reg_we & !reg_error; - assign message_header_c126_message_id_wd = reg_wdata[7:0]; - - assign message_header_c126_message_type_we = addr_hit[1266] & reg_we & !reg_error; - assign message_header_c126_message_type_wd = reg_wdata[9:8]; - - assign message_header_c126_protocol_id_we = addr_hit[1266] & reg_we & !reg_error; - assign message_header_c126_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c126_token_we = addr_hit[1266] & reg_we & !reg_error; - assign message_header_c126_token_wd = reg_wdata[27:18]; - - assign message_header_c126_field1_we = addr_hit[1266] & reg_we & !reg_error; - assign message_header_c126_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c126_we = addr_hit[1267] & reg_we & !reg_error; - assign message_payload_1_c126_wd = reg_wdata[31:0]; - - assign doorbell_c126_intr_we = addr_hit[1268] & reg_we & !reg_error; - assign doorbell_c126_intr_wd = reg_wdata[0]; - - assign doorbell_c126_preserve_mask_we = addr_hit[1268] & reg_we & !reg_error; - assign doorbell_c126_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c126_intr_we = addr_hit[1269] & reg_we & !reg_error; - assign completion_interrupt_c126_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c126_preserve_mask_we = addr_hit[1269] & reg_we & !reg_error; - assign completion_interrupt_c126_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c127_we = addr_hit[1270] & reg_we & !reg_error; - assign reserved_1_c127_wd = reg_wdata[31:0]; - - assign channel_status_c127_channel_free_we = addr_hit[1271] & reg_we & !reg_error; - assign channel_status_c127_channel_free_wd = reg_wdata[0]; - - assign channel_status_c127_channel_error_we = addr_hit[1271] & reg_we & !reg_error; - assign channel_status_c127_channel_error_wd = reg_wdata[1]; - - assign channel_status_c127_field1_we = addr_hit[1271] & reg_we & !reg_error; - assign channel_status_c127_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c127_we = addr_hit[1272] & reg_we & !reg_error; - assign reserved_2_c127_wd = reg_wdata[31:0]; - - assign channel_flags_c127_intr_enable_we = addr_hit[1274] & reg_we & !reg_error; - assign channel_flags_c127_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c127_field1_we = addr_hit[1274] & reg_we & !reg_error; - assign channel_flags_c127_field1_wd = reg_wdata[31:1]; - - assign length_c127_we = addr_hit[1275] & reg_we & !reg_error; - assign length_c127_wd = reg_wdata[31:0]; - - assign message_header_c127_message_id_we = addr_hit[1276] & reg_we & !reg_error; - assign message_header_c127_message_id_wd = reg_wdata[7:0]; - - assign message_header_c127_message_type_we = addr_hit[1276] & reg_we & !reg_error; - assign message_header_c127_message_type_wd = reg_wdata[9:8]; - - assign message_header_c127_protocol_id_we = addr_hit[1276] & reg_we & !reg_error; - assign message_header_c127_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c127_token_we = addr_hit[1276] & reg_we & !reg_error; - assign message_header_c127_token_wd = reg_wdata[27:18]; - - assign message_header_c127_field1_we = addr_hit[1276] & reg_we & !reg_error; - assign message_header_c127_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c127_we = addr_hit[1277] & reg_we & !reg_error; - assign message_payload_1_c127_wd = reg_wdata[31:0]; - - assign doorbell_c127_intr_we = addr_hit[1278] & reg_we & !reg_error; - assign doorbell_c127_intr_wd = reg_wdata[0]; - - assign doorbell_c127_preserve_mask_we = addr_hit[1278] & reg_we & !reg_error; - assign doorbell_c127_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c127_intr_we = addr_hit[1279] & reg_we & !reg_error; - assign completion_interrupt_c127_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c127_preserve_mask_we = addr_hit[1279] & reg_we & !reg_error; - assign completion_interrupt_c127_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c128_we = addr_hit[1280] & reg_we & !reg_error; - assign reserved_1_c128_wd = reg_wdata[31:0]; - - assign channel_status_c128_channel_free_we = addr_hit[1281] & reg_we & !reg_error; - assign channel_status_c128_channel_free_wd = reg_wdata[0]; - - assign channel_status_c128_channel_error_we = addr_hit[1281] & reg_we & !reg_error; - assign channel_status_c128_channel_error_wd = reg_wdata[1]; - - assign channel_status_c128_field1_we = addr_hit[1281] & reg_we & !reg_error; - assign channel_status_c128_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c128_we = addr_hit[1282] & reg_we & !reg_error; - assign reserved_2_c128_wd = reg_wdata[31:0]; - - assign channel_flags_c128_intr_enable_we = addr_hit[1284] & reg_we & !reg_error; - assign channel_flags_c128_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c128_field1_we = addr_hit[1284] & reg_we & !reg_error; - assign channel_flags_c128_field1_wd = reg_wdata[31:1]; - - assign length_c128_we = addr_hit[1285] & reg_we & !reg_error; - assign length_c128_wd = reg_wdata[31:0]; - - assign message_header_c128_message_id_we = addr_hit[1286] & reg_we & !reg_error; - assign message_header_c128_message_id_wd = reg_wdata[7:0]; - - assign message_header_c128_message_type_we = addr_hit[1286] & reg_we & !reg_error; - assign message_header_c128_message_type_wd = reg_wdata[9:8]; - - assign message_header_c128_protocol_id_we = addr_hit[1286] & reg_we & !reg_error; - assign message_header_c128_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c128_token_we = addr_hit[1286] & reg_we & !reg_error; - assign message_header_c128_token_wd = reg_wdata[27:18]; - - assign message_header_c128_field1_we = addr_hit[1286] & reg_we & !reg_error; - assign message_header_c128_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c128_we = addr_hit[1287] & reg_we & !reg_error; - assign message_payload_1_c128_wd = reg_wdata[31:0]; - - assign doorbell_c128_intr_we = addr_hit[1288] & reg_we & !reg_error; - assign doorbell_c128_intr_wd = reg_wdata[0]; - - assign doorbell_c128_preserve_mask_we = addr_hit[1288] & reg_we & !reg_error; - assign doorbell_c128_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c128_intr_we = addr_hit[1289] & reg_we & !reg_error; - assign completion_interrupt_c128_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c128_preserve_mask_we = addr_hit[1289] & reg_we & !reg_error; - assign completion_interrupt_c128_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c129_we = addr_hit[1290] & reg_we & !reg_error; - assign reserved_1_c129_wd = reg_wdata[31:0]; - - assign channel_status_c129_channel_free_we = addr_hit[1291] & reg_we & !reg_error; - assign channel_status_c129_channel_free_wd = reg_wdata[0]; - - assign channel_status_c129_channel_error_we = addr_hit[1291] & reg_we & !reg_error; - assign channel_status_c129_channel_error_wd = reg_wdata[1]; - - assign channel_status_c129_field1_we = addr_hit[1291] & reg_we & !reg_error; - assign channel_status_c129_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c129_we = addr_hit[1292] & reg_we & !reg_error; - assign reserved_2_c129_wd = reg_wdata[31:0]; - - assign channel_flags_c129_intr_enable_we = addr_hit[1294] & reg_we & !reg_error; - assign channel_flags_c129_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c129_field1_we = addr_hit[1294] & reg_we & !reg_error; - assign channel_flags_c129_field1_wd = reg_wdata[31:1]; - - assign length_c129_we = addr_hit[1295] & reg_we & !reg_error; - assign length_c129_wd = reg_wdata[31:0]; - - assign message_header_c129_message_id_we = addr_hit[1296] & reg_we & !reg_error; - assign message_header_c129_message_id_wd = reg_wdata[7:0]; - - assign message_header_c129_message_type_we = addr_hit[1296] & reg_we & !reg_error; - assign message_header_c129_message_type_wd = reg_wdata[9:8]; - - assign message_header_c129_protocol_id_we = addr_hit[1296] & reg_we & !reg_error; - assign message_header_c129_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c129_token_we = addr_hit[1296] & reg_we & !reg_error; - assign message_header_c129_token_wd = reg_wdata[27:18]; - - assign message_header_c129_field1_we = addr_hit[1296] & reg_we & !reg_error; - assign message_header_c129_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c129_we = addr_hit[1297] & reg_we & !reg_error; - assign message_payload_1_c129_wd = reg_wdata[31:0]; - - assign doorbell_c129_intr_we = addr_hit[1298] & reg_we & !reg_error; - assign doorbell_c129_intr_wd = reg_wdata[0]; - - assign doorbell_c129_preserve_mask_we = addr_hit[1298] & reg_we & !reg_error; - assign doorbell_c129_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c129_intr_we = addr_hit[1299] & reg_we & !reg_error; - assign completion_interrupt_c129_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c129_preserve_mask_we = addr_hit[1299] & reg_we & !reg_error; - assign completion_interrupt_c129_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c130_we = addr_hit[1300] & reg_we & !reg_error; - assign reserved_1_c130_wd = reg_wdata[31:0]; - - assign channel_status_c130_channel_free_we = addr_hit[1301] & reg_we & !reg_error; - assign channel_status_c130_channel_free_wd = reg_wdata[0]; - - assign channel_status_c130_channel_error_we = addr_hit[1301] & reg_we & !reg_error; - assign channel_status_c130_channel_error_wd = reg_wdata[1]; - - assign channel_status_c130_field1_we = addr_hit[1301] & reg_we & !reg_error; - assign channel_status_c130_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c130_we = addr_hit[1302] & reg_we & !reg_error; - assign reserved_2_c130_wd = reg_wdata[31:0]; - - assign channel_flags_c130_intr_enable_we = addr_hit[1304] & reg_we & !reg_error; - assign channel_flags_c130_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c130_field1_we = addr_hit[1304] & reg_we & !reg_error; - assign channel_flags_c130_field1_wd = reg_wdata[31:1]; - - assign length_c130_we = addr_hit[1305] & reg_we & !reg_error; - assign length_c130_wd = reg_wdata[31:0]; - - assign message_header_c130_message_id_we = addr_hit[1306] & reg_we & !reg_error; - assign message_header_c130_message_id_wd = reg_wdata[7:0]; - - assign message_header_c130_message_type_we = addr_hit[1306] & reg_we & !reg_error; - assign message_header_c130_message_type_wd = reg_wdata[9:8]; - - assign message_header_c130_protocol_id_we = addr_hit[1306] & reg_we & !reg_error; - assign message_header_c130_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c130_token_we = addr_hit[1306] & reg_we & !reg_error; - assign message_header_c130_token_wd = reg_wdata[27:18]; - - assign message_header_c130_field1_we = addr_hit[1306] & reg_we & !reg_error; - assign message_header_c130_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c130_we = addr_hit[1307] & reg_we & !reg_error; - assign message_payload_1_c130_wd = reg_wdata[31:0]; - - assign doorbell_c130_intr_we = addr_hit[1308] & reg_we & !reg_error; - assign doorbell_c130_intr_wd = reg_wdata[0]; - - assign doorbell_c130_preserve_mask_we = addr_hit[1308] & reg_we & !reg_error; - assign doorbell_c130_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c130_intr_we = addr_hit[1309] & reg_we & !reg_error; - assign completion_interrupt_c130_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c130_preserve_mask_we = addr_hit[1309] & reg_we & !reg_error; - assign completion_interrupt_c130_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c131_we = addr_hit[1310] & reg_we & !reg_error; - assign reserved_1_c131_wd = reg_wdata[31:0]; - - assign channel_status_c131_channel_free_we = addr_hit[1311] & reg_we & !reg_error; - assign channel_status_c131_channel_free_wd = reg_wdata[0]; - - assign channel_status_c131_channel_error_we = addr_hit[1311] & reg_we & !reg_error; - assign channel_status_c131_channel_error_wd = reg_wdata[1]; - - assign channel_status_c131_field1_we = addr_hit[1311] & reg_we & !reg_error; - assign channel_status_c131_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c131_we = addr_hit[1312] & reg_we & !reg_error; - assign reserved_2_c131_wd = reg_wdata[31:0]; - - assign channel_flags_c131_intr_enable_we = addr_hit[1314] & reg_we & !reg_error; - assign channel_flags_c131_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c131_field1_we = addr_hit[1314] & reg_we & !reg_error; - assign channel_flags_c131_field1_wd = reg_wdata[31:1]; - - assign length_c131_we = addr_hit[1315] & reg_we & !reg_error; - assign length_c131_wd = reg_wdata[31:0]; - - assign message_header_c131_message_id_we = addr_hit[1316] & reg_we & !reg_error; - assign message_header_c131_message_id_wd = reg_wdata[7:0]; - - assign message_header_c131_message_type_we = addr_hit[1316] & reg_we & !reg_error; - assign message_header_c131_message_type_wd = reg_wdata[9:8]; - - assign message_header_c131_protocol_id_we = addr_hit[1316] & reg_we & !reg_error; - assign message_header_c131_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c131_token_we = addr_hit[1316] & reg_we & !reg_error; - assign message_header_c131_token_wd = reg_wdata[27:18]; - - assign message_header_c131_field1_we = addr_hit[1316] & reg_we & !reg_error; - assign message_header_c131_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c131_we = addr_hit[1317] & reg_we & !reg_error; - assign message_payload_1_c131_wd = reg_wdata[31:0]; - - assign doorbell_c131_intr_we = addr_hit[1318] & reg_we & !reg_error; - assign doorbell_c131_intr_wd = reg_wdata[0]; - - assign doorbell_c131_preserve_mask_we = addr_hit[1318] & reg_we & !reg_error; - assign doorbell_c131_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c131_intr_we = addr_hit[1319] & reg_we & !reg_error; - assign completion_interrupt_c131_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c131_preserve_mask_we = addr_hit[1319] & reg_we & !reg_error; - assign completion_interrupt_c131_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c132_we = addr_hit[1320] & reg_we & !reg_error; - assign reserved_1_c132_wd = reg_wdata[31:0]; - - assign channel_status_c132_channel_free_we = addr_hit[1321] & reg_we & !reg_error; - assign channel_status_c132_channel_free_wd = reg_wdata[0]; - - assign channel_status_c132_channel_error_we = addr_hit[1321] & reg_we & !reg_error; - assign channel_status_c132_channel_error_wd = reg_wdata[1]; - - assign channel_status_c132_field1_we = addr_hit[1321] & reg_we & !reg_error; - assign channel_status_c132_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c132_we = addr_hit[1322] & reg_we & !reg_error; - assign reserved_2_c132_wd = reg_wdata[31:0]; - - assign channel_flags_c132_intr_enable_we = addr_hit[1324] & reg_we & !reg_error; - assign channel_flags_c132_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c132_field1_we = addr_hit[1324] & reg_we & !reg_error; - assign channel_flags_c132_field1_wd = reg_wdata[31:1]; - - assign length_c132_we = addr_hit[1325] & reg_we & !reg_error; - assign length_c132_wd = reg_wdata[31:0]; - - assign message_header_c132_message_id_we = addr_hit[1326] & reg_we & !reg_error; - assign message_header_c132_message_id_wd = reg_wdata[7:0]; - - assign message_header_c132_message_type_we = addr_hit[1326] & reg_we & !reg_error; - assign message_header_c132_message_type_wd = reg_wdata[9:8]; - - assign message_header_c132_protocol_id_we = addr_hit[1326] & reg_we & !reg_error; - assign message_header_c132_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c132_token_we = addr_hit[1326] & reg_we & !reg_error; - assign message_header_c132_token_wd = reg_wdata[27:18]; - - assign message_header_c132_field1_we = addr_hit[1326] & reg_we & !reg_error; - assign message_header_c132_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c132_we = addr_hit[1327] & reg_we & !reg_error; - assign message_payload_1_c132_wd = reg_wdata[31:0]; - - assign doorbell_c132_intr_we = addr_hit[1328] & reg_we & !reg_error; - assign doorbell_c132_intr_wd = reg_wdata[0]; - - assign doorbell_c132_preserve_mask_we = addr_hit[1328] & reg_we & !reg_error; - assign doorbell_c132_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c132_intr_we = addr_hit[1329] & reg_we & !reg_error; - assign completion_interrupt_c132_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c132_preserve_mask_we = addr_hit[1329] & reg_we & !reg_error; - assign completion_interrupt_c132_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c133_we = addr_hit[1330] & reg_we & !reg_error; - assign reserved_1_c133_wd = reg_wdata[31:0]; - - assign channel_status_c133_channel_free_we = addr_hit[1331] & reg_we & !reg_error; - assign channel_status_c133_channel_free_wd = reg_wdata[0]; - - assign channel_status_c133_channel_error_we = addr_hit[1331] & reg_we & !reg_error; - assign channel_status_c133_channel_error_wd = reg_wdata[1]; - - assign channel_status_c133_field1_we = addr_hit[1331] & reg_we & !reg_error; - assign channel_status_c133_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c133_we = addr_hit[1332] & reg_we & !reg_error; - assign reserved_2_c133_wd = reg_wdata[31:0]; - - assign channel_flags_c133_intr_enable_we = addr_hit[1334] & reg_we & !reg_error; - assign channel_flags_c133_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c133_field1_we = addr_hit[1334] & reg_we & !reg_error; - assign channel_flags_c133_field1_wd = reg_wdata[31:1]; - - assign length_c133_we = addr_hit[1335] & reg_we & !reg_error; - assign length_c133_wd = reg_wdata[31:0]; - - assign message_header_c133_message_id_we = addr_hit[1336] & reg_we & !reg_error; - assign message_header_c133_message_id_wd = reg_wdata[7:0]; - - assign message_header_c133_message_type_we = addr_hit[1336] & reg_we & !reg_error; - assign message_header_c133_message_type_wd = reg_wdata[9:8]; - - assign message_header_c133_protocol_id_we = addr_hit[1336] & reg_we & !reg_error; - assign message_header_c133_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c133_token_we = addr_hit[1336] & reg_we & !reg_error; - assign message_header_c133_token_wd = reg_wdata[27:18]; - - assign message_header_c133_field1_we = addr_hit[1336] & reg_we & !reg_error; - assign message_header_c133_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c133_we = addr_hit[1337] & reg_we & !reg_error; - assign message_payload_1_c133_wd = reg_wdata[31:0]; - - assign doorbell_c133_intr_we = addr_hit[1338] & reg_we & !reg_error; - assign doorbell_c133_intr_wd = reg_wdata[0]; - - assign doorbell_c133_preserve_mask_we = addr_hit[1338] & reg_we & !reg_error; - assign doorbell_c133_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c133_intr_we = addr_hit[1339] & reg_we & !reg_error; - assign completion_interrupt_c133_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c133_preserve_mask_we = addr_hit[1339] & reg_we & !reg_error; - assign completion_interrupt_c133_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c134_we = addr_hit[1340] & reg_we & !reg_error; - assign reserved_1_c134_wd = reg_wdata[31:0]; - - assign channel_status_c134_channel_free_we = addr_hit[1341] & reg_we & !reg_error; - assign channel_status_c134_channel_free_wd = reg_wdata[0]; - - assign channel_status_c134_channel_error_we = addr_hit[1341] & reg_we & !reg_error; - assign channel_status_c134_channel_error_wd = reg_wdata[1]; - - assign channel_status_c134_field1_we = addr_hit[1341] & reg_we & !reg_error; - assign channel_status_c134_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c134_we = addr_hit[1342] & reg_we & !reg_error; - assign reserved_2_c134_wd = reg_wdata[31:0]; - - assign channel_flags_c134_intr_enable_we = addr_hit[1344] & reg_we & !reg_error; - assign channel_flags_c134_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c134_field1_we = addr_hit[1344] & reg_we & !reg_error; - assign channel_flags_c134_field1_wd = reg_wdata[31:1]; - - assign length_c134_we = addr_hit[1345] & reg_we & !reg_error; - assign length_c134_wd = reg_wdata[31:0]; - - assign message_header_c134_message_id_we = addr_hit[1346] & reg_we & !reg_error; - assign message_header_c134_message_id_wd = reg_wdata[7:0]; - - assign message_header_c134_message_type_we = addr_hit[1346] & reg_we & !reg_error; - assign message_header_c134_message_type_wd = reg_wdata[9:8]; - - assign message_header_c134_protocol_id_we = addr_hit[1346] & reg_we & !reg_error; - assign message_header_c134_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c134_token_we = addr_hit[1346] & reg_we & !reg_error; - assign message_header_c134_token_wd = reg_wdata[27:18]; - - assign message_header_c134_field1_we = addr_hit[1346] & reg_we & !reg_error; - assign message_header_c134_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c134_we = addr_hit[1347] & reg_we & !reg_error; - assign message_payload_1_c134_wd = reg_wdata[31:0]; - - assign doorbell_c134_intr_we = addr_hit[1348] & reg_we & !reg_error; - assign doorbell_c134_intr_wd = reg_wdata[0]; - - assign doorbell_c134_preserve_mask_we = addr_hit[1348] & reg_we & !reg_error; - assign doorbell_c134_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c134_intr_we = addr_hit[1349] & reg_we & !reg_error; - assign completion_interrupt_c134_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c134_preserve_mask_we = addr_hit[1349] & reg_we & !reg_error; - assign completion_interrupt_c134_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c135_we = addr_hit[1350] & reg_we & !reg_error; - assign reserved_1_c135_wd = reg_wdata[31:0]; - - assign channel_status_c135_channel_free_we = addr_hit[1351] & reg_we & !reg_error; - assign channel_status_c135_channel_free_wd = reg_wdata[0]; - - assign channel_status_c135_channel_error_we = addr_hit[1351] & reg_we & !reg_error; - assign channel_status_c135_channel_error_wd = reg_wdata[1]; - - assign channel_status_c135_field1_we = addr_hit[1351] & reg_we & !reg_error; - assign channel_status_c135_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c135_we = addr_hit[1352] & reg_we & !reg_error; - assign reserved_2_c135_wd = reg_wdata[31:0]; - - assign channel_flags_c135_intr_enable_we = addr_hit[1354] & reg_we & !reg_error; - assign channel_flags_c135_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c135_field1_we = addr_hit[1354] & reg_we & !reg_error; - assign channel_flags_c135_field1_wd = reg_wdata[31:1]; - - assign length_c135_we = addr_hit[1355] & reg_we & !reg_error; - assign length_c135_wd = reg_wdata[31:0]; - - assign message_header_c135_message_id_we = addr_hit[1356] & reg_we & !reg_error; - assign message_header_c135_message_id_wd = reg_wdata[7:0]; - - assign message_header_c135_message_type_we = addr_hit[1356] & reg_we & !reg_error; - assign message_header_c135_message_type_wd = reg_wdata[9:8]; - - assign message_header_c135_protocol_id_we = addr_hit[1356] & reg_we & !reg_error; - assign message_header_c135_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c135_token_we = addr_hit[1356] & reg_we & !reg_error; - assign message_header_c135_token_wd = reg_wdata[27:18]; - - assign message_header_c135_field1_we = addr_hit[1356] & reg_we & !reg_error; - assign message_header_c135_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c135_we = addr_hit[1357] & reg_we & !reg_error; - assign message_payload_1_c135_wd = reg_wdata[31:0]; - - assign doorbell_c135_intr_we = addr_hit[1358] & reg_we & !reg_error; - assign doorbell_c135_intr_wd = reg_wdata[0]; - - assign doorbell_c135_preserve_mask_we = addr_hit[1358] & reg_we & !reg_error; - assign doorbell_c135_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c135_intr_we = addr_hit[1359] & reg_we & !reg_error; - assign completion_interrupt_c135_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c135_preserve_mask_we = addr_hit[1359] & reg_we & !reg_error; - assign completion_interrupt_c135_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c136_we = addr_hit[1360] & reg_we & !reg_error; - assign reserved_1_c136_wd = reg_wdata[31:0]; - - assign channel_status_c136_channel_free_we = addr_hit[1361] & reg_we & !reg_error; - assign channel_status_c136_channel_free_wd = reg_wdata[0]; - - assign channel_status_c136_channel_error_we = addr_hit[1361] & reg_we & !reg_error; - assign channel_status_c136_channel_error_wd = reg_wdata[1]; - - assign channel_status_c136_field1_we = addr_hit[1361] & reg_we & !reg_error; - assign channel_status_c136_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c136_we = addr_hit[1362] & reg_we & !reg_error; - assign reserved_2_c136_wd = reg_wdata[31:0]; - - assign channel_flags_c136_intr_enable_we = addr_hit[1364] & reg_we & !reg_error; - assign channel_flags_c136_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c136_field1_we = addr_hit[1364] & reg_we & !reg_error; - assign channel_flags_c136_field1_wd = reg_wdata[31:1]; - - assign length_c136_we = addr_hit[1365] & reg_we & !reg_error; - assign length_c136_wd = reg_wdata[31:0]; - - assign message_header_c136_message_id_we = addr_hit[1366] & reg_we & !reg_error; - assign message_header_c136_message_id_wd = reg_wdata[7:0]; - - assign message_header_c136_message_type_we = addr_hit[1366] & reg_we & !reg_error; - assign message_header_c136_message_type_wd = reg_wdata[9:8]; - - assign message_header_c136_protocol_id_we = addr_hit[1366] & reg_we & !reg_error; - assign message_header_c136_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c136_token_we = addr_hit[1366] & reg_we & !reg_error; - assign message_header_c136_token_wd = reg_wdata[27:18]; - - assign message_header_c136_field1_we = addr_hit[1366] & reg_we & !reg_error; - assign message_header_c136_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c136_we = addr_hit[1367] & reg_we & !reg_error; - assign message_payload_1_c136_wd = reg_wdata[31:0]; - - assign doorbell_c136_intr_we = addr_hit[1368] & reg_we & !reg_error; - assign doorbell_c136_intr_wd = reg_wdata[0]; - - assign doorbell_c136_preserve_mask_we = addr_hit[1368] & reg_we & !reg_error; - assign doorbell_c136_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c136_intr_we = addr_hit[1369] & reg_we & !reg_error; - assign completion_interrupt_c136_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c136_preserve_mask_we = addr_hit[1369] & reg_we & !reg_error; - assign completion_interrupt_c136_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c137_we = addr_hit[1370] & reg_we & !reg_error; - assign reserved_1_c137_wd = reg_wdata[31:0]; - - assign channel_status_c137_channel_free_we = addr_hit[1371] & reg_we & !reg_error; - assign channel_status_c137_channel_free_wd = reg_wdata[0]; - - assign channel_status_c137_channel_error_we = addr_hit[1371] & reg_we & !reg_error; - assign channel_status_c137_channel_error_wd = reg_wdata[1]; - - assign channel_status_c137_field1_we = addr_hit[1371] & reg_we & !reg_error; - assign channel_status_c137_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c137_we = addr_hit[1372] & reg_we & !reg_error; - assign reserved_2_c137_wd = reg_wdata[31:0]; - - assign channel_flags_c137_intr_enable_we = addr_hit[1374] & reg_we & !reg_error; - assign channel_flags_c137_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c137_field1_we = addr_hit[1374] & reg_we & !reg_error; - assign channel_flags_c137_field1_wd = reg_wdata[31:1]; - - assign length_c137_we = addr_hit[1375] & reg_we & !reg_error; - assign length_c137_wd = reg_wdata[31:0]; - - assign message_header_c137_message_id_we = addr_hit[1376] & reg_we & !reg_error; - assign message_header_c137_message_id_wd = reg_wdata[7:0]; - - assign message_header_c137_message_type_we = addr_hit[1376] & reg_we & !reg_error; - assign message_header_c137_message_type_wd = reg_wdata[9:8]; - - assign message_header_c137_protocol_id_we = addr_hit[1376] & reg_we & !reg_error; - assign message_header_c137_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c137_token_we = addr_hit[1376] & reg_we & !reg_error; - assign message_header_c137_token_wd = reg_wdata[27:18]; - - assign message_header_c137_field1_we = addr_hit[1376] & reg_we & !reg_error; - assign message_header_c137_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c137_we = addr_hit[1377] & reg_we & !reg_error; - assign message_payload_1_c137_wd = reg_wdata[31:0]; - - assign doorbell_c137_intr_we = addr_hit[1378] & reg_we & !reg_error; - assign doorbell_c137_intr_wd = reg_wdata[0]; - - assign doorbell_c137_preserve_mask_we = addr_hit[1378] & reg_we & !reg_error; - assign doorbell_c137_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c137_intr_we = addr_hit[1379] & reg_we & !reg_error; - assign completion_interrupt_c137_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c137_preserve_mask_we = addr_hit[1379] & reg_we & !reg_error; - assign completion_interrupt_c137_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c138_we = addr_hit[1380] & reg_we & !reg_error; - assign reserved_1_c138_wd = reg_wdata[31:0]; - - assign channel_status_c138_channel_free_we = addr_hit[1381] & reg_we & !reg_error; - assign channel_status_c138_channel_free_wd = reg_wdata[0]; - - assign channel_status_c138_channel_error_we = addr_hit[1381] & reg_we & !reg_error; - assign channel_status_c138_channel_error_wd = reg_wdata[1]; - - assign channel_status_c138_field1_we = addr_hit[1381] & reg_we & !reg_error; - assign channel_status_c138_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c138_we = addr_hit[1382] & reg_we & !reg_error; - assign reserved_2_c138_wd = reg_wdata[31:0]; - - assign channel_flags_c138_intr_enable_we = addr_hit[1384] & reg_we & !reg_error; - assign channel_flags_c138_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c138_field1_we = addr_hit[1384] & reg_we & !reg_error; - assign channel_flags_c138_field1_wd = reg_wdata[31:1]; - - assign length_c138_we = addr_hit[1385] & reg_we & !reg_error; - assign length_c138_wd = reg_wdata[31:0]; - - assign message_header_c138_message_id_we = addr_hit[1386] & reg_we & !reg_error; - assign message_header_c138_message_id_wd = reg_wdata[7:0]; - - assign message_header_c138_message_type_we = addr_hit[1386] & reg_we & !reg_error; - assign message_header_c138_message_type_wd = reg_wdata[9:8]; - - assign message_header_c138_protocol_id_we = addr_hit[1386] & reg_we & !reg_error; - assign message_header_c138_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c138_token_we = addr_hit[1386] & reg_we & !reg_error; - assign message_header_c138_token_wd = reg_wdata[27:18]; - - assign message_header_c138_field1_we = addr_hit[1386] & reg_we & !reg_error; - assign message_header_c138_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c138_we = addr_hit[1387] & reg_we & !reg_error; - assign message_payload_1_c138_wd = reg_wdata[31:0]; - - assign doorbell_c138_intr_we = addr_hit[1388] & reg_we & !reg_error; - assign doorbell_c138_intr_wd = reg_wdata[0]; - - assign doorbell_c138_preserve_mask_we = addr_hit[1388] & reg_we & !reg_error; - assign doorbell_c138_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c138_intr_we = addr_hit[1389] & reg_we & !reg_error; - assign completion_interrupt_c138_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c138_preserve_mask_we = addr_hit[1389] & reg_we & !reg_error; - assign completion_interrupt_c138_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c139_we = addr_hit[1390] & reg_we & !reg_error; - assign reserved_1_c139_wd = reg_wdata[31:0]; - - assign channel_status_c139_channel_free_we = addr_hit[1391] & reg_we & !reg_error; - assign channel_status_c139_channel_free_wd = reg_wdata[0]; - - assign channel_status_c139_channel_error_we = addr_hit[1391] & reg_we & !reg_error; - assign channel_status_c139_channel_error_wd = reg_wdata[1]; - - assign channel_status_c139_field1_we = addr_hit[1391] & reg_we & !reg_error; - assign channel_status_c139_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c139_we = addr_hit[1392] & reg_we & !reg_error; - assign reserved_2_c139_wd = reg_wdata[31:0]; - - assign channel_flags_c139_intr_enable_we = addr_hit[1394] & reg_we & !reg_error; - assign channel_flags_c139_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c139_field1_we = addr_hit[1394] & reg_we & !reg_error; - assign channel_flags_c139_field1_wd = reg_wdata[31:1]; - - assign length_c139_we = addr_hit[1395] & reg_we & !reg_error; - assign length_c139_wd = reg_wdata[31:0]; - - assign message_header_c139_message_id_we = addr_hit[1396] & reg_we & !reg_error; - assign message_header_c139_message_id_wd = reg_wdata[7:0]; - - assign message_header_c139_message_type_we = addr_hit[1396] & reg_we & !reg_error; - assign message_header_c139_message_type_wd = reg_wdata[9:8]; - - assign message_header_c139_protocol_id_we = addr_hit[1396] & reg_we & !reg_error; - assign message_header_c139_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c139_token_we = addr_hit[1396] & reg_we & !reg_error; - assign message_header_c139_token_wd = reg_wdata[27:18]; - - assign message_header_c139_field1_we = addr_hit[1396] & reg_we & !reg_error; - assign message_header_c139_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c139_we = addr_hit[1397] & reg_we & !reg_error; - assign message_payload_1_c139_wd = reg_wdata[31:0]; - - assign doorbell_c139_intr_we = addr_hit[1398] & reg_we & !reg_error; - assign doorbell_c139_intr_wd = reg_wdata[0]; - - assign doorbell_c139_preserve_mask_we = addr_hit[1398] & reg_we & !reg_error; - assign doorbell_c139_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c139_intr_we = addr_hit[1399] & reg_we & !reg_error; - assign completion_interrupt_c139_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c139_preserve_mask_we = addr_hit[1399] & reg_we & !reg_error; - assign completion_interrupt_c139_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c140_we = addr_hit[1400] & reg_we & !reg_error; - assign reserved_1_c140_wd = reg_wdata[31:0]; - - assign channel_status_c140_channel_free_we = addr_hit[1401] & reg_we & !reg_error; - assign channel_status_c140_channel_free_wd = reg_wdata[0]; - - assign channel_status_c140_channel_error_we = addr_hit[1401] & reg_we & !reg_error; - assign channel_status_c140_channel_error_wd = reg_wdata[1]; - - assign channel_status_c140_field1_we = addr_hit[1401] & reg_we & !reg_error; - assign channel_status_c140_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c140_we = addr_hit[1402] & reg_we & !reg_error; - assign reserved_2_c140_wd = reg_wdata[31:0]; - - assign channel_flags_c140_intr_enable_we = addr_hit[1404] & reg_we & !reg_error; - assign channel_flags_c140_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c140_field1_we = addr_hit[1404] & reg_we & !reg_error; - assign channel_flags_c140_field1_wd = reg_wdata[31:1]; - - assign length_c140_we = addr_hit[1405] & reg_we & !reg_error; - assign length_c140_wd = reg_wdata[31:0]; - - assign message_header_c140_message_id_we = addr_hit[1406] & reg_we & !reg_error; - assign message_header_c140_message_id_wd = reg_wdata[7:0]; - - assign message_header_c140_message_type_we = addr_hit[1406] & reg_we & !reg_error; - assign message_header_c140_message_type_wd = reg_wdata[9:8]; - - assign message_header_c140_protocol_id_we = addr_hit[1406] & reg_we & !reg_error; - assign message_header_c140_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c140_token_we = addr_hit[1406] & reg_we & !reg_error; - assign message_header_c140_token_wd = reg_wdata[27:18]; - - assign message_header_c140_field1_we = addr_hit[1406] & reg_we & !reg_error; - assign message_header_c140_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c140_we = addr_hit[1407] & reg_we & !reg_error; - assign message_payload_1_c140_wd = reg_wdata[31:0]; - - assign doorbell_c140_intr_we = addr_hit[1408] & reg_we & !reg_error; - assign doorbell_c140_intr_wd = reg_wdata[0]; - - assign doorbell_c140_preserve_mask_we = addr_hit[1408] & reg_we & !reg_error; - assign doorbell_c140_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c140_intr_we = addr_hit[1409] & reg_we & !reg_error; - assign completion_interrupt_c140_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c140_preserve_mask_we = addr_hit[1409] & reg_we & !reg_error; - assign completion_interrupt_c140_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c141_we = addr_hit[1410] & reg_we & !reg_error; - assign reserved_1_c141_wd = reg_wdata[31:0]; - - assign channel_status_c141_channel_free_we = addr_hit[1411] & reg_we & !reg_error; - assign channel_status_c141_channel_free_wd = reg_wdata[0]; - - assign channel_status_c141_channel_error_we = addr_hit[1411] & reg_we & !reg_error; - assign channel_status_c141_channel_error_wd = reg_wdata[1]; - - assign channel_status_c141_field1_we = addr_hit[1411] & reg_we & !reg_error; - assign channel_status_c141_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c141_we = addr_hit[1412] & reg_we & !reg_error; - assign reserved_2_c141_wd = reg_wdata[31:0]; - - assign channel_flags_c141_intr_enable_we = addr_hit[1414] & reg_we & !reg_error; - assign channel_flags_c141_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c141_field1_we = addr_hit[1414] & reg_we & !reg_error; - assign channel_flags_c141_field1_wd = reg_wdata[31:1]; - - assign length_c141_we = addr_hit[1415] & reg_we & !reg_error; - assign length_c141_wd = reg_wdata[31:0]; - - assign message_header_c141_message_id_we = addr_hit[1416] & reg_we & !reg_error; - assign message_header_c141_message_id_wd = reg_wdata[7:0]; - - assign message_header_c141_message_type_we = addr_hit[1416] & reg_we & !reg_error; - assign message_header_c141_message_type_wd = reg_wdata[9:8]; - - assign message_header_c141_protocol_id_we = addr_hit[1416] & reg_we & !reg_error; - assign message_header_c141_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c141_token_we = addr_hit[1416] & reg_we & !reg_error; - assign message_header_c141_token_wd = reg_wdata[27:18]; - - assign message_header_c141_field1_we = addr_hit[1416] & reg_we & !reg_error; - assign message_header_c141_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c141_we = addr_hit[1417] & reg_we & !reg_error; - assign message_payload_1_c141_wd = reg_wdata[31:0]; - - assign doorbell_c141_intr_we = addr_hit[1418] & reg_we & !reg_error; - assign doorbell_c141_intr_wd = reg_wdata[0]; - - assign doorbell_c141_preserve_mask_we = addr_hit[1418] & reg_we & !reg_error; - assign doorbell_c141_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c141_intr_we = addr_hit[1419] & reg_we & !reg_error; - assign completion_interrupt_c141_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c141_preserve_mask_we = addr_hit[1419] & reg_we & !reg_error; - assign completion_interrupt_c141_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c142_we = addr_hit[1420] & reg_we & !reg_error; - assign reserved_1_c142_wd = reg_wdata[31:0]; - - assign channel_status_c142_channel_free_we = addr_hit[1421] & reg_we & !reg_error; - assign channel_status_c142_channel_free_wd = reg_wdata[0]; - - assign channel_status_c142_channel_error_we = addr_hit[1421] & reg_we & !reg_error; - assign channel_status_c142_channel_error_wd = reg_wdata[1]; - - assign channel_status_c142_field1_we = addr_hit[1421] & reg_we & !reg_error; - assign channel_status_c142_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c142_we = addr_hit[1422] & reg_we & !reg_error; - assign reserved_2_c142_wd = reg_wdata[31:0]; - - assign channel_flags_c142_intr_enable_we = addr_hit[1424] & reg_we & !reg_error; - assign channel_flags_c142_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c142_field1_we = addr_hit[1424] & reg_we & !reg_error; - assign channel_flags_c142_field1_wd = reg_wdata[31:1]; - - assign length_c142_we = addr_hit[1425] & reg_we & !reg_error; - assign length_c142_wd = reg_wdata[31:0]; - - assign message_header_c142_message_id_we = addr_hit[1426] & reg_we & !reg_error; - assign message_header_c142_message_id_wd = reg_wdata[7:0]; - - assign message_header_c142_message_type_we = addr_hit[1426] & reg_we & !reg_error; - assign message_header_c142_message_type_wd = reg_wdata[9:8]; - - assign message_header_c142_protocol_id_we = addr_hit[1426] & reg_we & !reg_error; - assign message_header_c142_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c142_token_we = addr_hit[1426] & reg_we & !reg_error; - assign message_header_c142_token_wd = reg_wdata[27:18]; - - assign message_header_c142_field1_we = addr_hit[1426] & reg_we & !reg_error; - assign message_header_c142_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c142_we = addr_hit[1427] & reg_we & !reg_error; - assign message_payload_1_c142_wd = reg_wdata[31:0]; - - assign doorbell_c142_intr_we = addr_hit[1428] & reg_we & !reg_error; - assign doorbell_c142_intr_wd = reg_wdata[0]; - - assign doorbell_c142_preserve_mask_we = addr_hit[1428] & reg_we & !reg_error; - assign doorbell_c142_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c142_intr_we = addr_hit[1429] & reg_we & !reg_error; - assign completion_interrupt_c142_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c142_preserve_mask_we = addr_hit[1429] & reg_we & !reg_error; - assign completion_interrupt_c142_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c143_we = addr_hit[1430] & reg_we & !reg_error; - assign reserved_1_c143_wd = reg_wdata[31:0]; - - assign channel_status_c143_channel_free_we = addr_hit[1431] & reg_we & !reg_error; - assign channel_status_c143_channel_free_wd = reg_wdata[0]; - - assign channel_status_c143_channel_error_we = addr_hit[1431] & reg_we & !reg_error; - assign channel_status_c143_channel_error_wd = reg_wdata[1]; - - assign channel_status_c143_field1_we = addr_hit[1431] & reg_we & !reg_error; - assign channel_status_c143_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c143_we = addr_hit[1432] & reg_we & !reg_error; - assign reserved_2_c143_wd = reg_wdata[31:0]; - - assign channel_flags_c143_intr_enable_we = addr_hit[1434] & reg_we & !reg_error; - assign channel_flags_c143_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c143_field1_we = addr_hit[1434] & reg_we & !reg_error; - assign channel_flags_c143_field1_wd = reg_wdata[31:1]; - - assign length_c143_we = addr_hit[1435] & reg_we & !reg_error; - assign length_c143_wd = reg_wdata[31:0]; - - assign message_header_c143_message_id_we = addr_hit[1436] & reg_we & !reg_error; - assign message_header_c143_message_id_wd = reg_wdata[7:0]; - - assign message_header_c143_message_type_we = addr_hit[1436] & reg_we & !reg_error; - assign message_header_c143_message_type_wd = reg_wdata[9:8]; - - assign message_header_c143_protocol_id_we = addr_hit[1436] & reg_we & !reg_error; - assign message_header_c143_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c143_token_we = addr_hit[1436] & reg_we & !reg_error; - assign message_header_c143_token_wd = reg_wdata[27:18]; - - assign message_header_c143_field1_we = addr_hit[1436] & reg_we & !reg_error; - assign message_header_c143_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c143_we = addr_hit[1437] & reg_we & !reg_error; - assign message_payload_1_c143_wd = reg_wdata[31:0]; - - assign doorbell_c143_intr_we = addr_hit[1438] & reg_we & !reg_error; - assign doorbell_c143_intr_wd = reg_wdata[0]; - - assign doorbell_c143_preserve_mask_we = addr_hit[1438] & reg_we & !reg_error; - assign doorbell_c143_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c143_intr_we = addr_hit[1439] & reg_we & !reg_error; - assign completion_interrupt_c143_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c143_preserve_mask_we = addr_hit[1439] & reg_we & !reg_error; - assign completion_interrupt_c143_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c144_we = addr_hit[1440] & reg_we & !reg_error; - assign reserved_1_c144_wd = reg_wdata[31:0]; - - assign channel_status_c144_channel_free_we = addr_hit[1441] & reg_we & !reg_error; - assign channel_status_c144_channel_free_wd = reg_wdata[0]; - - assign channel_status_c144_channel_error_we = addr_hit[1441] & reg_we & !reg_error; - assign channel_status_c144_channel_error_wd = reg_wdata[1]; - - assign channel_status_c144_field1_we = addr_hit[1441] & reg_we & !reg_error; - assign channel_status_c144_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c144_we = addr_hit[1442] & reg_we & !reg_error; - assign reserved_2_c144_wd = reg_wdata[31:0]; - - assign channel_flags_c144_intr_enable_we = addr_hit[1444] & reg_we & !reg_error; - assign channel_flags_c144_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c144_field1_we = addr_hit[1444] & reg_we & !reg_error; - assign channel_flags_c144_field1_wd = reg_wdata[31:1]; - - assign length_c144_we = addr_hit[1445] & reg_we & !reg_error; - assign length_c144_wd = reg_wdata[31:0]; - - assign message_header_c144_message_id_we = addr_hit[1446] & reg_we & !reg_error; - assign message_header_c144_message_id_wd = reg_wdata[7:0]; - - assign message_header_c144_message_type_we = addr_hit[1446] & reg_we & !reg_error; - assign message_header_c144_message_type_wd = reg_wdata[9:8]; - - assign message_header_c144_protocol_id_we = addr_hit[1446] & reg_we & !reg_error; - assign message_header_c144_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c144_token_we = addr_hit[1446] & reg_we & !reg_error; - assign message_header_c144_token_wd = reg_wdata[27:18]; - - assign message_header_c144_field1_we = addr_hit[1446] & reg_we & !reg_error; - assign message_header_c144_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c144_we = addr_hit[1447] & reg_we & !reg_error; - assign message_payload_1_c144_wd = reg_wdata[31:0]; - - assign doorbell_c144_intr_we = addr_hit[1448] & reg_we & !reg_error; - assign doorbell_c144_intr_wd = reg_wdata[0]; - - assign doorbell_c144_preserve_mask_we = addr_hit[1448] & reg_we & !reg_error; - assign doorbell_c144_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c144_intr_we = addr_hit[1449] & reg_we & !reg_error; - assign completion_interrupt_c144_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c144_preserve_mask_we = addr_hit[1449] & reg_we & !reg_error; - assign completion_interrupt_c144_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c145_we = addr_hit[1450] & reg_we & !reg_error; - assign reserved_1_c145_wd = reg_wdata[31:0]; - - assign channel_status_c145_channel_free_we = addr_hit[1451] & reg_we & !reg_error; - assign channel_status_c145_channel_free_wd = reg_wdata[0]; - - assign channel_status_c145_channel_error_we = addr_hit[1451] & reg_we & !reg_error; - assign channel_status_c145_channel_error_wd = reg_wdata[1]; - - assign channel_status_c145_field1_we = addr_hit[1451] & reg_we & !reg_error; - assign channel_status_c145_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c145_we = addr_hit[1452] & reg_we & !reg_error; - assign reserved_2_c145_wd = reg_wdata[31:0]; - - assign channel_flags_c145_intr_enable_we = addr_hit[1454] & reg_we & !reg_error; - assign channel_flags_c145_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c145_field1_we = addr_hit[1454] & reg_we & !reg_error; - assign channel_flags_c145_field1_wd = reg_wdata[31:1]; - - assign length_c145_we = addr_hit[1455] & reg_we & !reg_error; - assign length_c145_wd = reg_wdata[31:0]; - - assign message_header_c145_message_id_we = addr_hit[1456] & reg_we & !reg_error; - assign message_header_c145_message_id_wd = reg_wdata[7:0]; - - assign message_header_c145_message_type_we = addr_hit[1456] & reg_we & !reg_error; - assign message_header_c145_message_type_wd = reg_wdata[9:8]; - - assign message_header_c145_protocol_id_we = addr_hit[1456] & reg_we & !reg_error; - assign message_header_c145_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c145_token_we = addr_hit[1456] & reg_we & !reg_error; - assign message_header_c145_token_wd = reg_wdata[27:18]; - - assign message_header_c145_field1_we = addr_hit[1456] & reg_we & !reg_error; - assign message_header_c145_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c145_we = addr_hit[1457] & reg_we & !reg_error; - assign message_payload_1_c145_wd = reg_wdata[31:0]; - - assign doorbell_c145_intr_we = addr_hit[1458] & reg_we & !reg_error; - assign doorbell_c145_intr_wd = reg_wdata[0]; - - assign doorbell_c145_preserve_mask_we = addr_hit[1458] & reg_we & !reg_error; - assign doorbell_c145_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c145_intr_we = addr_hit[1459] & reg_we & !reg_error; - assign completion_interrupt_c145_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c145_preserve_mask_we = addr_hit[1459] & reg_we & !reg_error; - assign completion_interrupt_c145_preserve_mask_wd = reg_wdata[31:1]; - - assign reserved_1_c146_we = addr_hit[1460] & reg_we & !reg_error; - assign reserved_1_c146_wd = reg_wdata[31:0]; - - assign channel_status_c146_channel_free_we = addr_hit[1461] & reg_we & !reg_error; - assign channel_status_c146_channel_free_wd = reg_wdata[0]; - - assign channel_status_c146_channel_error_we = addr_hit[1461] & reg_we & !reg_error; - assign channel_status_c146_channel_error_wd = reg_wdata[1]; - - assign channel_status_c146_field1_we = addr_hit[1461] & reg_we & !reg_error; - assign channel_status_c146_field1_wd = reg_wdata[31:2]; - - assign reserved_2_c146_we = addr_hit[1462] & reg_we & !reg_error; - assign reserved_2_c146_wd = reg_wdata[31:0]; - - assign channel_flags_c146_intr_enable_we = addr_hit[1464] & reg_we & !reg_error; - assign channel_flags_c146_intr_enable_wd = reg_wdata[0]; - - assign channel_flags_c146_field1_we = addr_hit[1464] & reg_we & !reg_error; - assign channel_flags_c146_field1_wd = reg_wdata[31:1]; - - assign length_c146_we = addr_hit[1465] & reg_we & !reg_error; - assign length_c146_wd = reg_wdata[31:0]; - - assign message_header_c146_message_id_we = addr_hit[1466] & reg_we & !reg_error; - assign message_header_c146_message_id_wd = reg_wdata[7:0]; - - assign message_header_c146_message_type_we = addr_hit[1466] & reg_we & !reg_error; - assign message_header_c146_message_type_wd = reg_wdata[9:8]; - - assign message_header_c146_protocol_id_we = addr_hit[1466] & reg_we & !reg_error; - assign message_header_c146_protocol_id_wd = reg_wdata[17:10]; - - assign message_header_c146_token_we = addr_hit[1466] & reg_we & !reg_error; - assign message_header_c146_token_wd = reg_wdata[27:18]; - - assign message_header_c146_field1_we = addr_hit[1466] & reg_we & !reg_error; - assign message_header_c146_field1_wd = reg_wdata[31:28]; - - assign message_payload_1_c146_we = addr_hit[1467] & reg_we & !reg_error; - assign message_payload_1_c146_wd = reg_wdata[31:0]; - - assign doorbell_c146_intr_we = addr_hit[1468] & reg_we & !reg_error; - assign doorbell_c146_intr_wd = reg_wdata[0]; - - assign doorbell_c146_preserve_mask_we = addr_hit[1468] & reg_we & !reg_error; - assign doorbell_c146_preserve_mask_wd = reg_wdata[31:1]; - - assign completion_interrupt_c146_intr_we = addr_hit[1469] & reg_we & !reg_error; - assign completion_interrupt_c146_intr_wd = reg_wdata[0]; - - assign completion_interrupt_c146_preserve_mask_we = addr_hit[1469] & reg_we & !reg_error; - assign completion_interrupt_c146_preserve_mask_wd = reg_wdata[31:1]; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[31:0] = reserved_1_c0_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = channel_status_c0_channel_free_qs; - reg_rdata_next[1] = channel_status_c0_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c0_field1_qs; - end - - addr_hit[2]: begin - reg_rdata_next[31:0] = reserved_2_c0_qs; - end - - addr_hit[3]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[4]: begin - reg_rdata_next[0] = channel_flags_c0_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c0_field1_qs; - end - - addr_hit[5]: begin - reg_rdata_next[31:0] = length_c0_qs; - end - - addr_hit[6]: begin - reg_rdata_next[7:0] = message_header_c0_message_id_qs; - reg_rdata_next[9:8] = message_header_c0_message_type_qs; - reg_rdata_next[17:10] = message_header_c0_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c0_token_qs; - reg_rdata_next[31:28] = message_header_c0_field1_qs; - end - - addr_hit[7]: begin - reg_rdata_next[31:0] = message_payload_1_c0_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = doorbell_c0_intr_qs; - reg_rdata_next[31:1] = doorbell_c0_preserve_mask_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = completion_interrupt_c0_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c0_preserve_mask_qs; - end - - addr_hit[10]: begin - reg_rdata_next[31:0] = reserved_1_c1_qs; - end - - addr_hit[11]: begin - reg_rdata_next[0] = channel_status_c1_channel_free_qs; - reg_rdata_next[1] = channel_status_c1_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c1_field1_qs; - end - - addr_hit[12]: begin - reg_rdata_next[31:0] = reserved_2_c1_qs; - end - - addr_hit[13]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[14]: begin - reg_rdata_next[0] = channel_flags_c1_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c1_field1_qs; - end - - addr_hit[15]: begin - reg_rdata_next[31:0] = length_c1_qs; - end - - addr_hit[16]: begin - reg_rdata_next[7:0] = message_header_c1_message_id_qs; - reg_rdata_next[9:8] = message_header_c1_message_type_qs; - reg_rdata_next[17:10] = message_header_c1_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c1_token_qs; - reg_rdata_next[31:28] = message_header_c1_field1_qs; - end - - addr_hit[17]: begin - reg_rdata_next[31:0] = message_payload_1_c1_qs; - end - - addr_hit[18]: begin - reg_rdata_next[0] = doorbell_c1_intr_qs; - reg_rdata_next[31:1] = doorbell_c1_preserve_mask_qs; - end - - addr_hit[19]: begin - reg_rdata_next[0] = completion_interrupt_c1_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c1_preserve_mask_qs; - end - - addr_hit[20]: begin - reg_rdata_next[31:0] = reserved_1_c2_qs; - end - - addr_hit[21]: begin - reg_rdata_next[0] = channel_status_c2_channel_free_qs; - reg_rdata_next[1] = channel_status_c2_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c2_field1_qs; - end - - addr_hit[22]: begin - reg_rdata_next[31:0] = reserved_2_c2_qs; - end - - addr_hit[23]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[24]: begin - reg_rdata_next[0] = channel_flags_c2_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c2_field1_qs; - end - - addr_hit[25]: begin - reg_rdata_next[31:0] = length_c2_qs; - end - - addr_hit[26]: begin - reg_rdata_next[7:0] = message_header_c2_message_id_qs; - reg_rdata_next[9:8] = message_header_c2_message_type_qs; - reg_rdata_next[17:10] = message_header_c2_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c2_token_qs; - reg_rdata_next[31:28] = message_header_c2_field1_qs; - end - - addr_hit[27]: begin - reg_rdata_next[31:0] = message_payload_1_c2_qs; - end - - addr_hit[28]: begin - reg_rdata_next[0] = doorbell_c2_intr_qs; - reg_rdata_next[31:1] = doorbell_c2_preserve_mask_qs; - end - - addr_hit[29]: begin - reg_rdata_next[0] = completion_interrupt_c2_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c2_preserve_mask_qs; - end - - addr_hit[30]: begin - reg_rdata_next[31:0] = reserved_1_c3_qs; - end - - addr_hit[31]: begin - reg_rdata_next[0] = channel_status_c3_channel_free_qs; - reg_rdata_next[1] = channel_status_c3_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c3_field1_qs; - end - - addr_hit[32]: begin - reg_rdata_next[31:0] = reserved_2_c3_qs; - end - - addr_hit[33]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[34]: begin - reg_rdata_next[0] = channel_flags_c3_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c3_field1_qs; - end - - addr_hit[35]: begin - reg_rdata_next[31:0] = length_c3_qs; - end - - addr_hit[36]: begin - reg_rdata_next[7:0] = message_header_c3_message_id_qs; - reg_rdata_next[9:8] = message_header_c3_message_type_qs; - reg_rdata_next[17:10] = message_header_c3_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c3_token_qs; - reg_rdata_next[31:28] = message_header_c3_field1_qs; - end - - addr_hit[37]: begin - reg_rdata_next[31:0] = message_payload_1_c3_qs; - end - - addr_hit[38]: begin - reg_rdata_next[0] = doorbell_c3_intr_qs; - reg_rdata_next[31:1] = doorbell_c3_preserve_mask_qs; - end - - addr_hit[39]: begin - reg_rdata_next[0] = completion_interrupt_c3_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c3_preserve_mask_qs; - end - - addr_hit[40]: begin - reg_rdata_next[31:0] = reserved_1_c4_qs; - end - - addr_hit[41]: begin - reg_rdata_next[0] = channel_status_c4_channel_free_qs; - reg_rdata_next[1] = channel_status_c4_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c4_field1_qs; - end - - addr_hit[42]: begin - reg_rdata_next[31:0] = reserved_2_c4_qs; - end - - addr_hit[43]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[44]: begin - reg_rdata_next[0] = channel_flags_c4_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c4_field1_qs; - end - - addr_hit[45]: begin - reg_rdata_next[31:0] = length_c4_qs; - end - - addr_hit[46]: begin - reg_rdata_next[7:0] = message_header_c4_message_id_qs; - reg_rdata_next[9:8] = message_header_c4_message_type_qs; - reg_rdata_next[17:10] = message_header_c4_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c4_token_qs; - reg_rdata_next[31:28] = message_header_c4_field1_qs; - end - - addr_hit[47]: begin - reg_rdata_next[31:0] = message_payload_1_c4_qs; - end - - addr_hit[48]: begin - reg_rdata_next[0] = doorbell_c4_intr_qs; - reg_rdata_next[31:1] = doorbell_c4_preserve_mask_qs; - end - - addr_hit[49]: begin - reg_rdata_next[0] = completion_interrupt_c4_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c4_preserve_mask_qs; - end - - addr_hit[50]: begin - reg_rdata_next[31:0] = reserved_1_c5_qs; - end - - addr_hit[51]: begin - reg_rdata_next[0] = channel_status_c5_channel_free_qs; - reg_rdata_next[1] = channel_status_c5_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c5_field1_qs; - end - - addr_hit[52]: begin - reg_rdata_next[31:0] = reserved_2_c5_qs; - end - - addr_hit[53]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[54]: begin - reg_rdata_next[0] = channel_flags_c5_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c5_field1_qs; - end - - addr_hit[55]: begin - reg_rdata_next[31:0] = length_c5_qs; - end - - addr_hit[56]: begin - reg_rdata_next[7:0] = message_header_c5_message_id_qs; - reg_rdata_next[9:8] = message_header_c5_message_type_qs; - reg_rdata_next[17:10] = message_header_c5_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c5_token_qs; - reg_rdata_next[31:28] = message_header_c5_field1_qs; - end - - addr_hit[57]: begin - reg_rdata_next[31:0] = message_payload_1_c5_qs; - end - - addr_hit[58]: begin - reg_rdata_next[0] = doorbell_c5_intr_qs; - reg_rdata_next[31:1] = doorbell_c5_preserve_mask_qs; - end - - addr_hit[59]: begin - reg_rdata_next[0] = completion_interrupt_c5_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c5_preserve_mask_qs; - end - - addr_hit[60]: begin - reg_rdata_next[31:0] = reserved_1_c6_qs; - end - - addr_hit[61]: begin - reg_rdata_next[0] = channel_status_c6_channel_free_qs; - reg_rdata_next[1] = channel_status_c6_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c6_field1_qs; - end - - addr_hit[62]: begin - reg_rdata_next[31:0] = reserved_2_c6_qs; - end - - addr_hit[63]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[64]: begin - reg_rdata_next[0] = channel_flags_c6_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c6_field1_qs; - end - - addr_hit[65]: begin - reg_rdata_next[31:0] = length_c6_qs; - end - - addr_hit[66]: begin - reg_rdata_next[7:0] = message_header_c6_message_id_qs; - reg_rdata_next[9:8] = message_header_c6_message_type_qs; - reg_rdata_next[17:10] = message_header_c6_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c6_token_qs; - reg_rdata_next[31:28] = message_header_c6_field1_qs; - end - - addr_hit[67]: begin - reg_rdata_next[31:0] = message_payload_1_c6_qs; - end - - addr_hit[68]: begin - reg_rdata_next[0] = doorbell_c6_intr_qs; - reg_rdata_next[31:1] = doorbell_c6_preserve_mask_qs; - end - - addr_hit[69]: begin - reg_rdata_next[0] = completion_interrupt_c6_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c6_preserve_mask_qs; - end - - addr_hit[70]: begin - reg_rdata_next[31:0] = reserved_1_c7_qs; - end - - addr_hit[71]: begin - reg_rdata_next[0] = channel_status_c7_channel_free_qs; - reg_rdata_next[1] = channel_status_c7_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c7_field1_qs; - end - - addr_hit[72]: begin - reg_rdata_next[31:0] = reserved_2_c7_qs; - end - - addr_hit[73]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[74]: begin - reg_rdata_next[0] = channel_flags_c7_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c7_field1_qs; - end - - addr_hit[75]: begin - reg_rdata_next[31:0] = length_c7_qs; - end - - addr_hit[76]: begin - reg_rdata_next[7:0] = message_header_c7_message_id_qs; - reg_rdata_next[9:8] = message_header_c7_message_type_qs; - reg_rdata_next[17:10] = message_header_c7_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c7_token_qs; - reg_rdata_next[31:28] = message_header_c7_field1_qs; - end - - addr_hit[77]: begin - reg_rdata_next[31:0] = message_payload_1_c7_qs; - end - - addr_hit[78]: begin - reg_rdata_next[0] = doorbell_c7_intr_qs; - reg_rdata_next[31:1] = doorbell_c7_preserve_mask_qs; - end - - addr_hit[79]: begin - reg_rdata_next[0] = completion_interrupt_c7_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c7_preserve_mask_qs; - end - - addr_hit[80]: begin - reg_rdata_next[31:0] = reserved_1_c8_qs; - end - - addr_hit[81]: begin - reg_rdata_next[0] = channel_status_c8_channel_free_qs; - reg_rdata_next[1] = channel_status_c8_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c8_field1_qs; - end - - addr_hit[82]: begin - reg_rdata_next[31:0] = reserved_2_c8_qs; - end - - addr_hit[83]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[84]: begin - reg_rdata_next[0] = channel_flags_c8_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c8_field1_qs; - end - - addr_hit[85]: begin - reg_rdata_next[31:0] = length_c8_qs; - end - - addr_hit[86]: begin - reg_rdata_next[7:0] = message_header_c8_message_id_qs; - reg_rdata_next[9:8] = message_header_c8_message_type_qs; - reg_rdata_next[17:10] = message_header_c8_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c8_token_qs; - reg_rdata_next[31:28] = message_header_c8_field1_qs; - end - - addr_hit[87]: begin - reg_rdata_next[31:0] = message_payload_1_c8_qs; - end - - addr_hit[88]: begin - reg_rdata_next[0] = doorbell_c8_intr_qs; - reg_rdata_next[31:1] = doorbell_c8_preserve_mask_qs; - end - - addr_hit[89]: begin - reg_rdata_next[0] = completion_interrupt_c8_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c8_preserve_mask_qs; - end - - addr_hit[90]: begin - reg_rdata_next[31:0] = reserved_1_c9_qs; - end - - addr_hit[91]: begin - reg_rdata_next[0] = channel_status_c9_channel_free_qs; - reg_rdata_next[1] = channel_status_c9_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c9_field1_qs; - end - - addr_hit[92]: begin - reg_rdata_next[31:0] = reserved_2_c9_qs; - end - - addr_hit[93]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[94]: begin - reg_rdata_next[0] = channel_flags_c9_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c9_field1_qs; - end - - addr_hit[95]: begin - reg_rdata_next[31:0] = length_c9_qs; - end - - addr_hit[96]: begin - reg_rdata_next[7:0] = message_header_c9_message_id_qs; - reg_rdata_next[9:8] = message_header_c9_message_type_qs; - reg_rdata_next[17:10] = message_header_c9_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c9_token_qs; - reg_rdata_next[31:28] = message_header_c9_field1_qs; - end - - addr_hit[97]: begin - reg_rdata_next[31:0] = message_payload_1_c9_qs; - end - - addr_hit[98]: begin - reg_rdata_next[0] = doorbell_c9_intr_qs; - reg_rdata_next[31:1] = doorbell_c9_preserve_mask_qs; - end - - addr_hit[99]: begin - reg_rdata_next[0] = completion_interrupt_c9_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c9_preserve_mask_qs; - end - - addr_hit[100]: begin - reg_rdata_next[31:0] = reserved_1_c10_qs; - end - - addr_hit[101]: begin - reg_rdata_next[0] = channel_status_c10_channel_free_qs; - reg_rdata_next[1] = channel_status_c10_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c10_field1_qs; - end - - addr_hit[102]: begin - reg_rdata_next[31:0] = reserved_2_c10_qs; - end - - addr_hit[103]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[104]: begin - reg_rdata_next[0] = channel_flags_c10_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c10_field1_qs; - end - - addr_hit[105]: begin - reg_rdata_next[31:0] = length_c10_qs; - end - - addr_hit[106]: begin - reg_rdata_next[7:0] = message_header_c10_message_id_qs; - reg_rdata_next[9:8] = message_header_c10_message_type_qs; - reg_rdata_next[17:10] = message_header_c10_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c10_token_qs; - reg_rdata_next[31:28] = message_header_c10_field1_qs; - end - - addr_hit[107]: begin - reg_rdata_next[31:0] = message_payload_1_c10_qs; - end - - addr_hit[108]: begin - reg_rdata_next[0] = doorbell_c10_intr_qs; - reg_rdata_next[31:1] = doorbell_c10_preserve_mask_qs; - end - - addr_hit[109]: begin - reg_rdata_next[0] = completion_interrupt_c10_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c10_preserve_mask_qs; - end - - addr_hit[110]: begin - reg_rdata_next[31:0] = reserved_1_c11_qs; - end - - addr_hit[111]: begin - reg_rdata_next[0] = channel_status_c11_channel_free_qs; - reg_rdata_next[1] = channel_status_c11_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c11_field1_qs; - end - - addr_hit[112]: begin - reg_rdata_next[31:0] = reserved_2_c11_qs; - end - - addr_hit[113]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[114]: begin - reg_rdata_next[0] = channel_flags_c11_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c11_field1_qs; - end - - addr_hit[115]: begin - reg_rdata_next[31:0] = length_c11_qs; - end - - addr_hit[116]: begin - reg_rdata_next[7:0] = message_header_c11_message_id_qs; - reg_rdata_next[9:8] = message_header_c11_message_type_qs; - reg_rdata_next[17:10] = message_header_c11_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c11_token_qs; - reg_rdata_next[31:28] = message_header_c11_field1_qs; - end - - addr_hit[117]: begin - reg_rdata_next[31:0] = message_payload_1_c11_qs; - end - - addr_hit[118]: begin - reg_rdata_next[0] = doorbell_c11_intr_qs; - reg_rdata_next[31:1] = doorbell_c11_preserve_mask_qs; - end - - addr_hit[119]: begin - reg_rdata_next[0] = completion_interrupt_c11_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c11_preserve_mask_qs; - end - - addr_hit[120]: begin - reg_rdata_next[31:0] = reserved_1_c12_qs; - end - - addr_hit[121]: begin - reg_rdata_next[0] = channel_status_c12_channel_free_qs; - reg_rdata_next[1] = channel_status_c12_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c12_field1_qs; - end - - addr_hit[122]: begin - reg_rdata_next[31:0] = reserved_2_c12_qs; - end - - addr_hit[123]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[124]: begin - reg_rdata_next[0] = channel_flags_c12_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c12_field1_qs; - end - - addr_hit[125]: begin - reg_rdata_next[31:0] = length_c12_qs; - end - - addr_hit[126]: begin - reg_rdata_next[7:0] = message_header_c12_message_id_qs; - reg_rdata_next[9:8] = message_header_c12_message_type_qs; - reg_rdata_next[17:10] = message_header_c12_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c12_token_qs; - reg_rdata_next[31:28] = message_header_c12_field1_qs; - end - - addr_hit[127]: begin - reg_rdata_next[31:0] = message_payload_1_c12_qs; - end - - addr_hit[128]: begin - reg_rdata_next[0] = doorbell_c12_intr_qs; - reg_rdata_next[31:1] = doorbell_c12_preserve_mask_qs; - end - - addr_hit[129]: begin - reg_rdata_next[0] = completion_interrupt_c12_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c12_preserve_mask_qs; - end - - addr_hit[130]: begin - reg_rdata_next[31:0] = reserved_1_c13_qs; - end - - addr_hit[131]: begin - reg_rdata_next[0] = channel_status_c13_channel_free_qs; - reg_rdata_next[1] = channel_status_c13_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c13_field1_qs; - end - - addr_hit[132]: begin - reg_rdata_next[31:0] = reserved_2_c13_qs; - end - - addr_hit[133]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[134]: begin - reg_rdata_next[0] = channel_flags_c13_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c13_field1_qs; - end - - addr_hit[135]: begin - reg_rdata_next[31:0] = length_c13_qs; - end - - addr_hit[136]: begin - reg_rdata_next[7:0] = message_header_c13_message_id_qs; - reg_rdata_next[9:8] = message_header_c13_message_type_qs; - reg_rdata_next[17:10] = message_header_c13_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c13_token_qs; - reg_rdata_next[31:28] = message_header_c13_field1_qs; - end - - addr_hit[137]: begin - reg_rdata_next[31:0] = message_payload_1_c13_qs; - end - - addr_hit[138]: begin - reg_rdata_next[0] = doorbell_c13_intr_qs; - reg_rdata_next[31:1] = doorbell_c13_preserve_mask_qs; - end - - addr_hit[139]: begin - reg_rdata_next[0] = completion_interrupt_c13_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c13_preserve_mask_qs; - end - - addr_hit[140]: begin - reg_rdata_next[31:0] = reserved_1_c14_qs; - end - - addr_hit[141]: begin - reg_rdata_next[0] = channel_status_c14_channel_free_qs; - reg_rdata_next[1] = channel_status_c14_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c14_field1_qs; - end - - addr_hit[142]: begin - reg_rdata_next[31:0] = reserved_2_c14_qs; - end - - addr_hit[143]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[144]: begin - reg_rdata_next[0] = channel_flags_c14_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c14_field1_qs; - end - - addr_hit[145]: begin - reg_rdata_next[31:0] = length_c14_qs; - end - - addr_hit[146]: begin - reg_rdata_next[7:0] = message_header_c14_message_id_qs; - reg_rdata_next[9:8] = message_header_c14_message_type_qs; - reg_rdata_next[17:10] = message_header_c14_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c14_token_qs; - reg_rdata_next[31:28] = message_header_c14_field1_qs; - end - - addr_hit[147]: begin - reg_rdata_next[31:0] = message_payload_1_c14_qs; - end - - addr_hit[148]: begin - reg_rdata_next[0] = doorbell_c14_intr_qs; - reg_rdata_next[31:1] = doorbell_c14_preserve_mask_qs; - end - - addr_hit[149]: begin - reg_rdata_next[0] = completion_interrupt_c14_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c14_preserve_mask_qs; - end - - addr_hit[150]: begin - reg_rdata_next[31:0] = reserved_1_c15_qs; - end - - addr_hit[151]: begin - reg_rdata_next[0] = channel_status_c15_channel_free_qs; - reg_rdata_next[1] = channel_status_c15_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c15_field1_qs; - end - - addr_hit[152]: begin - reg_rdata_next[31:0] = reserved_2_c15_qs; - end - - addr_hit[153]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[154]: begin - reg_rdata_next[0] = channel_flags_c15_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c15_field1_qs; - end - - addr_hit[155]: begin - reg_rdata_next[31:0] = length_c15_qs; - end - - addr_hit[156]: begin - reg_rdata_next[7:0] = message_header_c15_message_id_qs; - reg_rdata_next[9:8] = message_header_c15_message_type_qs; - reg_rdata_next[17:10] = message_header_c15_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c15_token_qs; - reg_rdata_next[31:28] = message_header_c15_field1_qs; - end - - addr_hit[157]: begin - reg_rdata_next[31:0] = message_payload_1_c15_qs; - end - - addr_hit[158]: begin - reg_rdata_next[0] = doorbell_c15_intr_qs; - reg_rdata_next[31:1] = doorbell_c15_preserve_mask_qs; - end - - addr_hit[159]: begin - reg_rdata_next[0] = completion_interrupt_c15_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c15_preserve_mask_qs; - end - - addr_hit[160]: begin - reg_rdata_next[31:0] = reserved_1_c16_qs; - end - - addr_hit[161]: begin - reg_rdata_next[0] = channel_status_c16_channel_free_qs; - reg_rdata_next[1] = channel_status_c16_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c16_field1_qs; - end - - addr_hit[162]: begin - reg_rdata_next[31:0] = reserved_2_c16_qs; - end - - addr_hit[163]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[164]: begin - reg_rdata_next[0] = channel_flags_c16_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c16_field1_qs; - end - - addr_hit[165]: begin - reg_rdata_next[31:0] = length_c16_qs; - end - - addr_hit[166]: begin - reg_rdata_next[7:0] = message_header_c16_message_id_qs; - reg_rdata_next[9:8] = message_header_c16_message_type_qs; - reg_rdata_next[17:10] = message_header_c16_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c16_token_qs; - reg_rdata_next[31:28] = message_header_c16_field1_qs; - end - - addr_hit[167]: begin - reg_rdata_next[31:0] = message_payload_1_c16_qs; - end - - addr_hit[168]: begin - reg_rdata_next[0] = doorbell_c16_intr_qs; - reg_rdata_next[31:1] = doorbell_c16_preserve_mask_qs; - end - - addr_hit[169]: begin - reg_rdata_next[0] = completion_interrupt_c16_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c16_preserve_mask_qs; - end - - addr_hit[170]: begin - reg_rdata_next[31:0] = reserved_1_c17_qs; - end - - addr_hit[171]: begin - reg_rdata_next[0] = channel_status_c17_channel_free_qs; - reg_rdata_next[1] = channel_status_c17_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c17_field1_qs; - end - - addr_hit[172]: begin - reg_rdata_next[31:0] = reserved_2_c17_qs; - end - - addr_hit[173]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[174]: begin - reg_rdata_next[0] = channel_flags_c17_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c17_field1_qs; - end - - addr_hit[175]: begin - reg_rdata_next[31:0] = length_c17_qs; - end - - addr_hit[176]: begin - reg_rdata_next[7:0] = message_header_c17_message_id_qs; - reg_rdata_next[9:8] = message_header_c17_message_type_qs; - reg_rdata_next[17:10] = message_header_c17_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c17_token_qs; - reg_rdata_next[31:28] = message_header_c17_field1_qs; - end - - addr_hit[177]: begin - reg_rdata_next[31:0] = message_payload_1_c17_qs; - end - - addr_hit[178]: begin - reg_rdata_next[0] = doorbell_c17_intr_qs; - reg_rdata_next[31:1] = doorbell_c17_preserve_mask_qs; - end - - addr_hit[179]: begin - reg_rdata_next[0] = completion_interrupt_c17_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c17_preserve_mask_qs; - end - - addr_hit[180]: begin - reg_rdata_next[31:0] = reserved_1_c18_qs; - end - - addr_hit[181]: begin - reg_rdata_next[0] = channel_status_c18_channel_free_qs; - reg_rdata_next[1] = channel_status_c18_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c18_field1_qs; - end - - addr_hit[182]: begin - reg_rdata_next[31:0] = reserved_2_c18_qs; - end - - addr_hit[183]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[184]: begin - reg_rdata_next[0] = channel_flags_c18_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c18_field1_qs; - end - - addr_hit[185]: begin - reg_rdata_next[31:0] = length_c18_qs; - end - - addr_hit[186]: begin - reg_rdata_next[7:0] = message_header_c18_message_id_qs; - reg_rdata_next[9:8] = message_header_c18_message_type_qs; - reg_rdata_next[17:10] = message_header_c18_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c18_token_qs; - reg_rdata_next[31:28] = message_header_c18_field1_qs; - end - - addr_hit[187]: begin - reg_rdata_next[31:0] = message_payload_1_c18_qs; - end - - addr_hit[188]: begin - reg_rdata_next[0] = doorbell_c18_intr_qs; - reg_rdata_next[31:1] = doorbell_c18_preserve_mask_qs; - end - - addr_hit[189]: begin - reg_rdata_next[0] = completion_interrupt_c18_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c18_preserve_mask_qs; - end - - addr_hit[190]: begin - reg_rdata_next[31:0] = reserved_1_c19_qs; - end - - addr_hit[191]: begin - reg_rdata_next[0] = channel_status_c19_channel_free_qs; - reg_rdata_next[1] = channel_status_c19_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c19_field1_qs; - end - - addr_hit[192]: begin - reg_rdata_next[31:0] = reserved_2_c19_qs; - end - - addr_hit[193]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[194]: begin - reg_rdata_next[0] = channel_flags_c19_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c19_field1_qs; - end - - addr_hit[195]: begin - reg_rdata_next[31:0] = length_c19_qs; - end - - addr_hit[196]: begin - reg_rdata_next[7:0] = message_header_c19_message_id_qs; - reg_rdata_next[9:8] = message_header_c19_message_type_qs; - reg_rdata_next[17:10] = message_header_c19_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c19_token_qs; - reg_rdata_next[31:28] = message_header_c19_field1_qs; - end - - addr_hit[197]: begin - reg_rdata_next[31:0] = message_payload_1_c19_qs; - end - - addr_hit[198]: begin - reg_rdata_next[0] = doorbell_c19_intr_qs; - reg_rdata_next[31:1] = doorbell_c19_preserve_mask_qs; - end - - addr_hit[199]: begin - reg_rdata_next[0] = completion_interrupt_c19_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c19_preserve_mask_qs; - end - - addr_hit[200]: begin - reg_rdata_next[31:0] = reserved_1_c20_qs; - end - - addr_hit[201]: begin - reg_rdata_next[0] = channel_status_c20_channel_free_qs; - reg_rdata_next[1] = channel_status_c20_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c20_field1_qs; - end - - addr_hit[202]: begin - reg_rdata_next[31:0] = reserved_2_c20_qs; - end - - addr_hit[203]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[204]: begin - reg_rdata_next[0] = channel_flags_c20_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c20_field1_qs; - end - - addr_hit[205]: begin - reg_rdata_next[31:0] = length_c20_qs; - end - - addr_hit[206]: begin - reg_rdata_next[7:0] = message_header_c20_message_id_qs; - reg_rdata_next[9:8] = message_header_c20_message_type_qs; - reg_rdata_next[17:10] = message_header_c20_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c20_token_qs; - reg_rdata_next[31:28] = message_header_c20_field1_qs; - end - - addr_hit[207]: begin - reg_rdata_next[31:0] = message_payload_1_c20_qs; - end - - addr_hit[208]: begin - reg_rdata_next[0] = doorbell_c20_intr_qs; - reg_rdata_next[31:1] = doorbell_c20_preserve_mask_qs; - end - - addr_hit[209]: begin - reg_rdata_next[0] = completion_interrupt_c20_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c20_preserve_mask_qs; - end - - addr_hit[210]: begin - reg_rdata_next[31:0] = reserved_1_c21_qs; - end - - addr_hit[211]: begin - reg_rdata_next[0] = channel_status_c21_channel_free_qs; - reg_rdata_next[1] = channel_status_c21_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c21_field1_qs; - end - - addr_hit[212]: begin - reg_rdata_next[31:0] = reserved_2_c21_qs; - end - - addr_hit[213]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[214]: begin - reg_rdata_next[0] = channel_flags_c21_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c21_field1_qs; - end - - addr_hit[215]: begin - reg_rdata_next[31:0] = length_c21_qs; - end - - addr_hit[216]: begin - reg_rdata_next[7:0] = message_header_c21_message_id_qs; - reg_rdata_next[9:8] = message_header_c21_message_type_qs; - reg_rdata_next[17:10] = message_header_c21_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c21_token_qs; - reg_rdata_next[31:28] = message_header_c21_field1_qs; - end - - addr_hit[217]: begin - reg_rdata_next[31:0] = message_payload_1_c21_qs; - end - - addr_hit[218]: begin - reg_rdata_next[0] = doorbell_c21_intr_qs; - reg_rdata_next[31:1] = doorbell_c21_preserve_mask_qs; - end - - addr_hit[219]: begin - reg_rdata_next[0] = completion_interrupt_c21_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c21_preserve_mask_qs; - end - - addr_hit[220]: begin - reg_rdata_next[31:0] = reserved_1_c22_qs; - end - - addr_hit[221]: begin - reg_rdata_next[0] = channel_status_c22_channel_free_qs; - reg_rdata_next[1] = channel_status_c22_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c22_field1_qs; - end - - addr_hit[222]: begin - reg_rdata_next[31:0] = reserved_2_c22_qs; - end - - addr_hit[223]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[224]: begin - reg_rdata_next[0] = channel_flags_c22_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c22_field1_qs; - end - - addr_hit[225]: begin - reg_rdata_next[31:0] = length_c22_qs; - end - - addr_hit[226]: begin - reg_rdata_next[7:0] = message_header_c22_message_id_qs; - reg_rdata_next[9:8] = message_header_c22_message_type_qs; - reg_rdata_next[17:10] = message_header_c22_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c22_token_qs; - reg_rdata_next[31:28] = message_header_c22_field1_qs; - end - - addr_hit[227]: begin - reg_rdata_next[31:0] = message_payload_1_c22_qs; - end - - addr_hit[228]: begin - reg_rdata_next[0] = doorbell_c22_intr_qs; - reg_rdata_next[31:1] = doorbell_c22_preserve_mask_qs; - end - - addr_hit[229]: begin - reg_rdata_next[0] = completion_interrupt_c22_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c22_preserve_mask_qs; - end - - addr_hit[230]: begin - reg_rdata_next[31:0] = reserved_1_c23_qs; - end - - addr_hit[231]: begin - reg_rdata_next[0] = channel_status_c23_channel_free_qs; - reg_rdata_next[1] = channel_status_c23_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c23_field1_qs; - end - - addr_hit[232]: begin - reg_rdata_next[31:0] = reserved_2_c23_qs; - end - - addr_hit[233]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[234]: begin - reg_rdata_next[0] = channel_flags_c23_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c23_field1_qs; - end - - addr_hit[235]: begin - reg_rdata_next[31:0] = length_c23_qs; - end - - addr_hit[236]: begin - reg_rdata_next[7:0] = message_header_c23_message_id_qs; - reg_rdata_next[9:8] = message_header_c23_message_type_qs; - reg_rdata_next[17:10] = message_header_c23_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c23_token_qs; - reg_rdata_next[31:28] = message_header_c23_field1_qs; - end - - addr_hit[237]: begin - reg_rdata_next[31:0] = message_payload_1_c23_qs; - end - - addr_hit[238]: begin - reg_rdata_next[0] = doorbell_c23_intr_qs; - reg_rdata_next[31:1] = doorbell_c23_preserve_mask_qs; - end - - addr_hit[239]: begin - reg_rdata_next[0] = completion_interrupt_c23_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c23_preserve_mask_qs; - end - - addr_hit[240]: begin - reg_rdata_next[31:0] = reserved_1_c24_qs; - end - - addr_hit[241]: begin - reg_rdata_next[0] = channel_status_c24_channel_free_qs; - reg_rdata_next[1] = channel_status_c24_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c24_field1_qs; - end - - addr_hit[242]: begin - reg_rdata_next[31:0] = reserved_2_c24_qs; - end - - addr_hit[243]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[244]: begin - reg_rdata_next[0] = channel_flags_c24_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c24_field1_qs; - end - - addr_hit[245]: begin - reg_rdata_next[31:0] = length_c24_qs; - end - - addr_hit[246]: begin - reg_rdata_next[7:0] = message_header_c24_message_id_qs; - reg_rdata_next[9:8] = message_header_c24_message_type_qs; - reg_rdata_next[17:10] = message_header_c24_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c24_token_qs; - reg_rdata_next[31:28] = message_header_c24_field1_qs; - end - - addr_hit[247]: begin - reg_rdata_next[31:0] = message_payload_1_c24_qs; - end - - addr_hit[248]: begin - reg_rdata_next[0] = doorbell_c24_intr_qs; - reg_rdata_next[31:1] = doorbell_c24_preserve_mask_qs; - end - - addr_hit[249]: begin - reg_rdata_next[0] = completion_interrupt_c24_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c24_preserve_mask_qs; - end - - addr_hit[250]: begin - reg_rdata_next[31:0] = reserved_1_c25_qs; - end - - addr_hit[251]: begin - reg_rdata_next[0] = channel_status_c25_channel_free_qs; - reg_rdata_next[1] = channel_status_c25_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c25_field1_qs; - end - - addr_hit[252]: begin - reg_rdata_next[31:0] = reserved_2_c25_qs; - end - - addr_hit[253]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[254]: begin - reg_rdata_next[0] = channel_flags_c25_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c25_field1_qs; - end - - addr_hit[255]: begin - reg_rdata_next[31:0] = length_c25_qs; - end - - addr_hit[256]: begin - reg_rdata_next[7:0] = message_header_c25_message_id_qs; - reg_rdata_next[9:8] = message_header_c25_message_type_qs; - reg_rdata_next[17:10] = message_header_c25_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c25_token_qs; - reg_rdata_next[31:28] = message_header_c25_field1_qs; - end - - addr_hit[257]: begin - reg_rdata_next[31:0] = message_payload_1_c25_qs; - end - - addr_hit[258]: begin - reg_rdata_next[0] = doorbell_c25_intr_qs; - reg_rdata_next[31:1] = doorbell_c25_preserve_mask_qs; - end - - addr_hit[259]: begin - reg_rdata_next[0] = completion_interrupt_c25_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c25_preserve_mask_qs; - end - - addr_hit[260]: begin - reg_rdata_next[31:0] = reserved_1_c26_qs; - end - - addr_hit[261]: begin - reg_rdata_next[0] = channel_status_c26_channel_free_qs; - reg_rdata_next[1] = channel_status_c26_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c26_field1_qs; - end - - addr_hit[262]: begin - reg_rdata_next[31:0] = reserved_2_c26_qs; - end - - addr_hit[263]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[264]: begin - reg_rdata_next[0] = channel_flags_c26_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c26_field1_qs; - end - - addr_hit[265]: begin - reg_rdata_next[31:0] = length_c26_qs; - end - - addr_hit[266]: begin - reg_rdata_next[7:0] = message_header_c26_message_id_qs; - reg_rdata_next[9:8] = message_header_c26_message_type_qs; - reg_rdata_next[17:10] = message_header_c26_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c26_token_qs; - reg_rdata_next[31:28] = message_header_c26_field1_qs; - end - - addr_hit[267]: begin - reg_rdata_next[31:0] = message_payload_1_c26_qs; - end - - addr_hit[268]: begin - reg_rdata_next[0] = doorbell_c26_intr_qs; - reg_rdata_next[31:1] = doorbell_c26_preserve_mask_qs; - end - - addr_hit[269]: begin - reg_rdata_next[0] = completion_interrupt_c26_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c26_preserve_mask_qs; - end - - addr_hit[270]: begin - reg_rdata_next[31:0] = reserved_1_c27_qs; - end - - addr_hit[271]: begin - reg_rdata_next[0] = channel_status_c27_channel_free_qs; - reg_rdata_next[1] = channel_status_c27_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c27_field1_qs; - end - - addr_hit[272]: begin - reg_rdata_next[31:0] = reserved_2_c27_qs; - end - - addr_hit[273]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[274]: begin - reg_rdata_next[0] = channel_flags_c27_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c27_field1_qs; - end - - addr_hit[275]: begin - reg_rdata_next[31:0] = length_c27_qs; - end - - addr_hit[276]: begin - reg_rdata_next[7:0] = message_header_c27_message_id_qs; - reg_rdata_next[9:8] = message_header_c27_message_type_qs; - reg_rdata_next[17:10] = message_header_c27_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c27_token_qs; - reg_rdata_next[31:28] = message_header_c27_field1_qs; - end - - addr_hit[277]: begin - reg_rdata_next[31:0] = message_payload_1_c27_qs; - end - - addr_hit[278]: begin - reg_rdata_next[0] = doorbell_c27_intr_qs; - reg_rdata_next[31:1] = doorbell_c27_preserve_mask_qs; - end - - addr_hit[279]: begin - reg_rdata_next[0] = completion_interrupt_c27_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c27_preserve_mask_qs; - end - - addr_hit[280]: begin - reg_rdata_next[31:0] = reserved_1_c28_qs; - end - - addr_hit[281]: begin - reg_rdata_next[0] = channel_status_c28_channel_free_qs; - reg_rdata_next[1] = channel_status_c28_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c28_field1_qs; - end - - addr_hit[282]: begin - reg_rdata_next[31:0] = reserved_2_c28_qs; - end - - addr_hit[283]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[284]: begin - reg_rdata_next[0] = channel_flags_c28_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c28_field1_qs; - end - - addr_hit[285]: begin - reg_rdata_next[31:0] = length_c28_qs; - end - - addr_hit[286]: begin - reg_rdata_next[7:0] = message_header_c28_message_id_qs; - reg_rdata_next[9:8] = message_header_c28_message_type_qs; - reg_rdata_next[17:10] = message_header_c28_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c28_token_qs; - reg_rdata_next[31:28] = message_header_c28_field1_qs; - end - - addr_hit[287]: begin - reg_rdata_next[31:0] = message_payload_1_c28_qs; - end - - addr_hit[288]: begin - reg_rdata_next[0] = doorbell_c28_intr_qs; - reg_rdata_next[31:1] = doorbell_c28_preserve_mask_qs; - end - - addr_hit[289]: begin - reg_rdata_next[0] = completion_interrupt_c28_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c28_preserve_mask_qs; - end - - addr_hit[290]: begin - reg_rdata_next[31:0] = reserved_1_c29_qs; - end - - addr_hit[291]: begin - reg_rdata_next[0] = channel_status_c29_channel_free_qs; - reg_rdata_next[1] = channel_status_c29_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c29_field1_qs; - end - - addr_hit[292]: begin - reg_rdata_next[31:0] = reserved_2_c29_qs; - end - - addr_hit[293]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[294]: begin - reg_rdata_next[0] = channel_flags_c29_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c29_field1_qs; - end - - addr_hit[295]: begin - reg_rdata_next[31:0] = length_c29_qs; - end - - addr_hit[296]: begin - reg_rdata_next[7:0] = message_header_c29_message_id_qs; - reg_rdata_next[9:8] = message_header_c29_message_type_qs; - reg_rdata_next[17:10] = message_header_c29_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c29_token_qs; - reg_rdata_next[31:28] = message_header_c29_field1_qs; - end - - addr_hit[297]: begin - reg_rdata_next[31:0] = message_payload_1_c29_qs; - end - - addr_hit[298]: begin - reg_rdata_next[0] = doorbell_c29_intr_qs; - reg_rdata_next[31:1] = doorbell_c29_preserve_mask_qs; - end - - addr_hit[299]: begin - reg_rdata_next[0] = completion_interrupt_c29_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c29_preserve_mask_qs; - end - - addr_hit[300]: begin - reg_rdata_next[31:0] = reserved_1_c30_qs; - end - - addr_hit[301]: begin - reg_rdata_next[0] = channel_status_c30_channel_free_qs; - reg_rdata_next[1] = channel_status_c30_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c30_field1_qs; - end - - addr_hit[302]: begin - reg_rdata_next[31:0] = reserved_2_c30_qs; - end - - addr_hit[303]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[304]: begin - reg_rdata_next[0] = channel_flags_c30_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c30_field1_qs; - end - - addr_hit[305]: begin - reg_rdata_next[31:0] = length_c30_qs; - end - - addr_hit[306]: begin - reg_rdata_next[7:0] = message_header_c30_message_id_qs; - reg_rdata_next[9:8] = message_header_c30_message_type_qs; - reg_rdata_next[17:10] = message_header_c30_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c30_token_qs; - reg_rdata_next[31:28] = message_header_c30_field1_qs; - end - - addr_hit[307]: begin - reg_rdata_next[31:0] = message_payload_1_c30_qs; - end - - addr_hit[308]: begin - reg_rdata_next[0] = doorbell_c30_intr_qs; - reg_rdata_next[31:1] = doorbell_c30_preserve_mask_qs; - end - - addr_hit[309]: begin - reg_rdata_next[0] = completion_interrupt_c30_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c30_preserve_mask_qs; - end - - addr_hit[310]: begin - reg_rdata_next[31:0] = reserved_1_c31_qs; - end - - addr_hit[311]: begin - reg_rdata_next[0] = channel_status_c31_channel_free_qs; - reg_rdata_next[1] = channel_status_c31_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c31_field1_qs; - end - - addr_hit[312]: begin - reg_rdata_next[31:0] = reserved_2_c31_qs; - end - - addr_hit[313]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[314]: begin - reg_rdata_next[0] = channel_flags_c31_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c31_field1_qs; - end - - addr_hit[315]: begin - reg_rdata_next[31:0] = length_c31_qs; - end - - addr_hit[316]: begin - reg_rdata_next[7:0] = message_header_c31_message_id_qs; - reg_rdata_next[9:8] = message_header_c31_message_type_qs; - reg_rdata_next[17:10] = message_header_c31_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c31_token_qs; - reg_rdata_next[31:28] = message_header_c31_field1_qs; - end - - addr_hit[317]: begin - reg_rdata_next[31:0] = message_payload_1_c31_qs; - end - - addr_hit[318]: begin - reg_rdata_next[0] = doorbell_c31_intr_qs; - reg_rdata_next[31:1] = doorbell_c31_preserve_mask_qs; - end - - addr_hit[319]: begin - reg_rdata_next[0] = completion_interrupt_c31_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c31_preserve_mask_qs; - end - - addr_hit[320]: begin - reg_rdata_next[31:0] = reserved_1_c32_qs; - end - - addr_hit[321]: begin - reg_rdata_next[0] = channel_status_c32_channel_free_qs; - reg_rdata_next[1] = channel_status_c32_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c32_field1_qs; - end - - addr_hit[322]: begin - reg_rdata_next[31:0] = reserved_2_c32_qs; - end - - addr_hit[323]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[324]: begin - reg_rdata_next[0] = channel_flags_c32_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c32_field1_qs; - end - - addr_hit[325]: begin - reg_rdata_next[31:0] = length_c32_qs; - end - - addr_hit[326]: begin - reg_rdata_next[7:0] = message_header_c32_message_id_qs; - reg_rdata_next[9:8] = message_header_c32_message_type_qs; - reg_rdata_next[17:10] = message_header_c32_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c32_token_qs; - reg_rdata_next[31:28] = message_header_c32_field1_qs; - end - - addr_hit[327]: begin - reg_rdata_next[31:0] = message_payload_1_c32_qs; - end - - addr_hit[328]: begin - reg_rdata_next[0] = doorbell_c32_intr_qs; - reg_rdata_next[31:1] = doorbell_c32_preserve_mask_qs; - end - - addr_hit[329]: begin - reg_rdata_next[0] = completion_interrupt_c32_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c32_preserve_mask_qs; - end - - addr_hit[330]: begin - reg_rdata_next[31:0] = reserved_1_c33_qs; - end - - addr_hit[331]: begin - reg_rdata_next[0] = channel_status_c33_channel_free_qs; - reg_rdata_next[1] = channel_status_c33_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c33_field1_qs; - end - - addr_hit[332]: begin - reg_rdata_next[31:0] = reserved_2_c33_qs; - end - - addr_hit[333]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[334]: begin - reg_rdata_next[0] = channel_flags_c33_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c33_field1_qs; - end - - addr_hit[335]: begin - reg_rdata_next[31:0] = length_c33_qs; - end - - addr_hit[336]: begin - reg_rdata_next[7:0] = message_header_c33_message_id_qs; - reg_rdata_next[9:8] = message_header_c33_message_type_qs; - reg_rdata_next[17:10] = message_header_c33_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c33_token_qs; - reg_rdata_next[31:28] = message_header_c33_field1_qs; - end - - addr_hit[337]: begin - reg_rdata_next[31:0] = message_payload_1_c33_qs; - end - - addr_hit[338]: begin - reg_rdata_next[0] = doorbell_c33_intr_qs; - reg_rdata_next[31:1] = doorbell_c33_preserve_mask_qs; - end - - addr_hit[339]: begin - reg_rdata_next[0] = completion_interrupt_c33_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c33_preserve_mask_qs; - end - - addr_hit[340]: begin - reg_rdata_next[31:0] = reserved_1_c34_qs; - end - - addr_hit[341]: begin - reg_rdata_next[0] = channel_status_c34_channel_free_qs; - reg_rdata_next[1] = channel_status_c34_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c34_field1_qs; - end - - addr_hit[342]: begin - reg_rdata_next[31:0] = reserved_2_c34_qs; - end - - addr_hit[343]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[344]: begin - reg_rdata_next[0] = channel_flags_c34_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c34_field1_qs; - end - - addr_hit[345]: begin - reg_rdata_next[31:0] = length_c34_qs; - end - - addr_hit[346]: begin - reg_rdata_next[7:0] = message_header_c34_message_id_qs; - reg_rdata_next[9:8] = message_header_c34_message_type_qs; - reg_rdata_next[17:10] = message_header_c34_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c34_token_qs; - reg_rdata_next[31:28] = message_header_c34_field1_qs; - end - - addr_hit[347]: begin - reg_rdata_next[31:0] = message_payload_1_c34_qs; - end - - addr_hit[348]: begin - reg_rdata_next[0] = doorbell_c34_intr_qs; - reg_rdata_next[31:1] = doorbell_c34_preserve_mask_qs; - end - - addr_hit[349]: begin - reg_rdata_next[0] = completion_interrupt_c34_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c34_preserve_mask_qs; - end - - addr_hit[350]: begin - reg_rdata_next[31:0] = reserved_1_c35_qs; - end - - addr_hit[351]: begin - reg_rdata_next[0] = channel_status_c35_channel_free_qs; - reg_rdata_next[1] = channel_status_c35_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c35_field1_qs; - end - - addr_hit[352]: begin - reg_rdata_next[31:0] = reserved_2_c35_qs; - end - - addr_hit[353]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[354]: begin - reg_rdata_next[0] = channel_flags_c35_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c35_field1_qs; - end - - addr_hit[355]: begin - reg_rdata_next[31:0] = length_c35_qs; - end - - addr_hit[356]: begin - reg_rdata_next[7:0] = message_header_c35_message_id_qs; - reg_rdata_next[9:8] = message_header_c35_message_type_qs; - reg_rdata_next[17:10] = message_header_c35_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c35_token_qs; - reg_rdata_next[31:28] = message_header_c35_field1_qs; - end - - addr_hit[357]: begin - reg_rdata_next[31:0] = message_payload_1_c35_qs; - end - - addr_hit[358]: begin - reg_rdata_next[0] = doorbell_c35_intr_qs; - reg_rdata_next[31:1] = doorbell_c35_preserve_mask_qs; - end - - addr_hit[359]: begin - reg_rdata_next[0] = completion_interrupt_c35_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c35_preserve_mask_qs; - end - - addr_hit[360]: begin - reg_rdata_next[31:0] = reserved_1_c36_qs; - end - - addr_hit[361]: begin - reg_rdata_next[0] = channel_status_c36_channel_free_qs; - reg_rdata_next[1] = channel_status_c36_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c36_field1_qs; - end - - addr_hit[362]: begin - reg_rdata_next[31:0] = reserved_2_c36_qs; - end - - addr_hit[363]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[364]: begin - reg_rdata_next[0] = channel_flags_c36_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c36_field1_qs; - end - - addr_hit[365]: begin - reg_rdata_next[31:0] = length_c36_qs; - end - - addr_hit[366]: begin - reg_rdata_next[7:0] = message_header_c36_message_id_qs; - reg_rdata_next[9:8] = message_header_c36_message_type_qs; - reg_rdata_next[17:10] = message_header_c36_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c36_token_qs; - reg_rdata_next[31:28] = message_header_c36_field1_qs; - end - - addr_hit[367]: begin - reg_rdata_next[31:0] = message_payload_1_c36_qs; - end - - addr_hit[368]: begin - reg_rdata_next[0] = doorbell_c36_intr_qs; - reg_rdata_next[31:1] = doorbell_c36_preserve_mask_qs; - end - - addr_hit[369]: begin - reg_rdata_next[0] = completion_interrupt_c36_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c36_preserve_mask_qs; - end - - addr_hit[370]: begin - reg_rdata_next[31:0] = reserved_1_c37_qs; - end - - addr_hit[371]: begin - reg_rdata_next[0] = channel_status_c37_channel_free_qs; - reg_rdata_next[1] = channel_status_c37_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c37_field1_qs; - end - - addr_hit[372]: begin - reg_rdata_next[31:0] = reserved_2_c37_qs; - end - - addr_hit[373]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[374]: begin - reg_rdata_next[0] = channel_flags_c37_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c37_field1_qs; - end - - addr_hit[375]: begin - reg_rdata_next[31:0] = length_c37_qs; - end - - addr_hit[376]: begin - reg_rdata_next[7:0] = message_header_c37_message_id_qs; - reg_rdata_next[9:8] = message_header_c37_message_type_qs; - reg_rdata_next[17:10] = message_header_c37_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c37_token_qs; - reg_rdata_next[31:28] = message_header_c37_field1_qs; - end - - addr_hit[377]: begin - reg_rdata_next[31:0] = message_payload_1_c37_qs; - end - - addr_hit[378]: begin - reg_rdata_next[0] = doorbell_c37_intr_qs; - reg_rdata_next[31:1] = doorbell_c37_preserve_mask_qs; - end - - addr_hit[379]: begin - reg_rdata_next[0] = completion_interrupt_c37_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c37_preserve_mask_qs; - end - - addr_hit[380]: begin - reg_rdata_next[31:0] = reserved_1_c38_qs; - end - - addr_hit[381]: begin - reg_rdata_next[0] = channel_status_c38_channel_free_qs; - reg_rdata_next[1] = channel_status_c38_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c38_field1_qs; - end - - addr_hit[382]: begin - reg_rdata_next[31:0] = reserved_2_c38_qs; - end - - addr_hit[383]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[384]: begin - reg_rdata_next[0] = channel_flags_c38_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c38_field1_qs; - end - - addr_hit[385]: begin - reg_rdata_next[31:0] = length_c38_qs; - end - - addr_hit[386]: begin - reg_rdata_next[7:0] = message_header_c38_message_id_qs; - reg_rdata_next[9:8] = message_header_c38_message_type_qs; - reg_rdata_next[17:10] = message_header_c38_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c38_token_qs; - reg_rdata_next[31:28] = message_header_c38_field1_qs; - end - - addr_hit[387]: begin - reg_rdata_next[31:0] = message_payload_1_c38_qs; - end - - addr_hit[388]: begin - reg_rdata_next[0] = doorbell_c38_intr_qs; - reg_rdata_next[31:1] = doorbell_c38_preserve_mask_qs; - end - - addr_hit[389]: begin - reg_rdata_next[0] = completion_interrupt_c38_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c38_preserve_mask_qs; - end - - addr_hit[390]: begin - reg_rdata_next[31:0] = reserved_1_c39_qs; - end - - addr_hit[391]: begin - reg_rdata_next[0] = channel_status_c39_channel_free_qs; - reg_rdata_next[1] = channel_status_c39_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c39_field1_qs; - end - - addr_hit[392]: begin - reg_rdata_next[31:0] = reserved_2_c39_qs; - end - - addr_hit[393]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[394]: begin - reg_rdata_next[0] = channel_flags_c39_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c39_field1_qs; - end - - addr_hit[395]: begin - reg_rdata_next[31:0] = length_c39_qs; - end - - addr_hit[396]: begin - reg_rdata_next[7:0] = message_header_c39_message_id_qs; - reg_rdata_next[9:8] = message_header_c39_message_type_qs; - reg_rdata_next[17:10] = message_header_c39_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c39_token_qs; - reg_rdata_next[31:28] = message_header_c39_field1_qs; - end - - addr_hit[397]: begin - reg_rdata_next[31:0] = message_payload_1_c39_qs; - end - - addr_hit[398]: begin - reg_rdata_next[0] = doorbell_c39_intr_qs; - reg_rdata_next[31:1] = doorbell_c39_preserve_mask_qs; - end - - addr_hit[399]: begin - reg_rdata_next[0] = completion_interrupt_c39_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c39_preserve_mask_qs; - end - - addr_hit[400]: begin - reg_rdata_next[31:0] = reserved_1_c40_qs; - end - - addr_hit[401]: begin - reg_rdata_next[0] = channel_status_c40_channel_free_qs; - reg_rdata_next[1] = channel_status_c40_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c40_field1_qs; - end - - addr_hit[402]: begin - reg_rdata_next[31:0] = reserved_2_c40_qs; - end - - addr_hit[403]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[404]: begin - reg_rdata_next[0] = channel_flags_c40_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c40_field1_qs; - end - - addr_hit[405]: begin - reg_rdata_next[31:0] = length_c40_qs; - end - - addr_hit[406]: begin - reg_rdata_next[7:0] = message_header_c40_message_id_qs; - reg_rdata_next[9:8] = message_header_c40_message_type_qs; - reg_rdata_next[17:10] = message_header_c40_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c40_token_qs; - reg_rdata_next[31:28] = message_header_c40_field1_qs; - end - - addr_hit[407]: begin - reg_rdata_next[31:0] = message_payload_1_c40_qs; - end - - addr_hit[408]: begin - reg_rdata_next[0] = doorbell_c40_intr_qs; - reg_rdata_next[31:1] = doorbell_c40_preserve_mask_qs; - end - - addr_hit[409]: begin - reg_rdata_next[0] = completion_interrupt_c40_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c40_preserve_mask_qs; - end - - addr_hit[410]: begin - reg_rdata_next[31:0] = reserved_1_c41_qs; - end - - addr_hit[411]: begin - reg_rdata_next[0] = channel_status_c41_channel_free_qs; - reg_rdata_next[1] = channel_status_c41_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c41_field1_qs; - end - - addr_hit[412]: begin - reg_rdata_next[31:0] = reserved_2_c41_qs; - end - - addr_hit[413]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[414]: begin - reg_rdata_next[0] = channel_flags_c41_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c41_field1_qs; - end - - addr_hit[415]: begin - reg_rdata_next[31:0] = length_c41_qs; - end - - addr_hit[416]: begin - reg_rdata_next[7:0] = message_header_c41_message_id_qs; - reg_rdata_next[9:8] = message_header_c41_message_type_qs; - reg_rdata_next[17:10] = message_header_c41_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c41_token_qs; - reg_rdata_next[31:28] = message_header_c41_field1_qs; - end - - addr_hit[417]: begin - reg_rdata_next[31:0] = message_payload_1_c41_qs; - end - - addr_hit[418]: begin - reg_rdata_next[0] = doorbell_c41_intr_qs; - reg_rdata_next[31:1] = doorbell_c41_preserve_mask_qs; - end - - addr_hit[419]: begin - reg_rdata_next[0] = completion_interrupt_c41_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c41_preserve_mask_qs; - end - - addr_hit[420]: begin - reg_rdata_next[31:0] = reserved_1_c42_qs; - end - - addr_hit[421]: begin - reg_rdata_next[0] = channel_status_c42_channel_free_qs; - reg_rdata_next[1] = channel_status_c42_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c42_field1_qs; - end - - addr_hit[422]: begin - reg_rdata_next[31:0] = reserved_2_c42_qs; - end - - addr_hit[423]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[424]: begin - reg_rdata_next[0] = channel_flags_c42_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c42_field1_qs; - end - - addr_hit[425]: begin - reg_rdata_next[31:0] = length_c42_qs; - end - - addr_hit[426]: begin - reg_rdata_next[7:0] = message_header_c42_message_id_qs; - reg_rdata_next[9:8] = message_header_c42_message_type_qs; - reg_rdata_next[17:10] = message_header_c42_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c42_token_qs; - reg_rdata_next[31:28] = message_header_c42_field1_qs; - end - - addr_hit[427]: begin - reg_rdata_next[31:0] = message_payload_1_c42_qs; - end - - addr_hit[428]: begin - reg_rdata_next[0] = doorbell_c42_intr_qs; - reg_rdata_next[31:1] = doorbell_c42_preserve_mask_qs; - end - - addr_hit[429]: begin - reg_rdata_next[0] = completion_interrupt_c42_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c42_preserve_mask_qs; - end - - addr_hit[430]: begin - reg_rdata_next[31:0] = reserved_1_c43_qs; - end - - addr_hit[431]: begin - reg_rdata_next[0] = channel_status_c43_channel_free_qs; - reg_rdata_next[1] = channel_status_c43_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c43_field1_qs; - end - - addr_hit[432]: begin - reg_rdata_next[31:0] = reserved_2_c43_qs; - end - - addr_hit[433]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[434]: begin - reg_rdata_next[0] = channel_flags_c43_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c43_field1_qs; - end - - addr_hit[435]: begin - reg_rdata_next[31:0] = length_c43_qs; - end - - addr_hit[436]: begin - reg_rdata_next[7:0] = message_header_c43_message_id_qs; - reg_rdata_next[9:8] = message_header_c43_message_type_qs; - reg_rdata_next[17:10] = message_header_c43_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c43_token_qs; - reg_rdata_next[31:28] = message_header_c43_field1_qs; - end - - addr_hit[437]: begin - reg_rdata_next[31:0] = message_payload_1_c43_qs; - end - - addr_hit[438]: begin - reg_rdata_next[0] = doorbell_c43_intr_qs; - reg_rdata_next[31:1] = doorbell_c43_preserve_mask_qs; - end - - addr_hit[439]: begin - reg_rdata_next[0] = completion_interrupt_c43_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c43_preserve_mask_qs; - end - - addr_hit[440]: begin - reg_rdata_next[31:0] = reserved_1_c44_qs; - end - - addr_hit[441]: begin - reg_rdata_next[0] = channel_status_c44_channel_free_qs; - reg_rdata_next[1] = channel_status_c44_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c44_field1_qs; - end - - addr_hit[442]: begin - reg_rdata_next[31:0] = reserved_2_c44_qs; - end - - addr_hit[443]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[444]: begin - reg_rdata_next[0] = channel_flags_c44_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c44_field1_qs; - end - - addr_hit[445]: begin - reg_rdata_next[31:0] = length_c44_qs; - end - - addr_hit[446]: begin - reg_rdata_next[7:0] = message_header_c44_message_id_qs; - reg_rdata_next[9:8] = message_header_c44_message_type_qs; - reg_rdata_next[17:10] = message_header_c44_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c44_token_qs; - reg_rdata_next[31:28] = message_header_c44_field1_qs; - end - - addr_hit[447]: begin - reg_rdata_next[31:0] = message_payload_1_c44_qs; - end - - addr_hit[448]: begin - reg_rdata_next[0] = doorbell_c44_intr_qs; - reg_rdata_next[31:1] = doorbell_c44_preserve_mask_qs; - end - - addr_hit[449]: begin - reg_rdata_next[0] = completion_interrupt_c44_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c44_preserve_mask_qs; - end - - addr_hit[450]: begin - reg_rdata_next[31:0] = reserved_1_c45_qs; - end - - addr_hit[451]: begin - reg_rdata_next[0] = channel_status_c45_channel_free_qs; - reg_rdata_next[1] = channel_status_c45_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c45_field1_qs; - end - - addr_hit[452]: begin - reg_rdata_next[31:0] = reserved_2_c45_qs; - end - - addr_hit[453]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[454]: begin - reg_rdata_next[0] = channel_flags_c45_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c45_field1_qs; - end - - addr_hit[455]: begin - reg_rdata_next[31:0] = length_c45_qs; - end - - addr_hit[456]: begin - reg_rdata_next[7:0] = message_header_c45_message_id_qs; - reg_rdata_next[9:8] = message_header_c45_message_type_qs; - reg_rdata_next[17:10] = message_header_c45_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c45_token_qs; - reg_rdata_next[31:28] = message_header_c45_field1_qs; - end - - addr_hit[457]: begin - reg_rdata_next[31:0] = message_payload_1_c45_qs; - end - - addr_hit[458]: begin - reg_rdata_next[0] = doorbell_c45_intr_qs; - reg_rdata_next[31:1] = doorbell_c45_preserve_mask_qs; - end - - addr_hit[459]: begin - reg_rdata_next[0] = completion_interrupt_c45_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c45_preserve_mask_qs; - end - - addr_hit[460]: begin - reg_rdata_next[31:0] = reserved_1_c46_qs; - end - - addr_hit[461]: begin - reg_rdata_next[0] = channel_status_c46_channel_free_qs; - reg_rdata_next[1] = channel_status_c46_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c46_field1_qs; - end - - addr_hit[462]: begin - reg_rdata_next[31:0] = reserved_2_c46_qs; - end - - addr_hit[463]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[464]: begin - reg_rdata_next[0] = channel_flags_c46_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c46_field1_qs; - end - - addr_hit[465]: begin - reg_rdata_next[31:0] = length_c46_qs; - end - - addr_hit[466]: begin - reg_rdata_next[7:0] = message_header_c46_message_id_qs; - reg_rdata_next[9:8] = message_header_c46_message_type_qs; - reg_rdata_next[17:10] = message_header_c46_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c46_token_qs; - reg_rdata_next[31:28] = message_header_c46_field1_qs; - end - - addr_hit[467]: begin - reg_rdata_next[31:0] = message_payload_1_c46_qs; - end - - addr_hit[468]: begin - reg_rdata_next[0] = doorbell_c46_intr_qs; - reg_rdata_next[31:1] = doorbell_c46_preserve_mask_qs; - end - - addr_hit[469]: begin - reg_rdata_next[0] = completion_interrupt_c46_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c46_preserve_mask_qs; - end - - addr_hit[470]: begin - reg_rdata_next[31:0] = reserved_1_c47_qs; - end - - addr_hit[471]: begin - reg_rdata_next[0] = channel_status_c47_channel_free_qs; - reg_rdata_next[1] = channel_status_c47_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c47_field1_qs; - end - - addr_hit[472]: begin - reg_rdata_next[31:0] = reserved_2_c47_qs; - end - - addr_hit[473]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[474]: begin - reg_rdata_next[0] = channel_flags_c47_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c47_field1_qs; - end - - addr_hit[475]: begin - reg_rdata_next[31:0] = length_c47_qs; - end - - addr_hit[476]: begin - reg_rdata_next[7:0] = message_header_c47_message_id_qs; - reg_rdata_next[9:8] = message_header_c47_message_type_qs; - reg_rdata_next[17:10] = message_header_c47_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c47_token_qs; - reg_rdata_next[31:28] = message_header_c47_field1_qs; - end - - addr_hit[477]: begin - reg_rdata_next[31:0] = message_payload_1_c47_qs; - end - - addr_hit[478]: begin - reg_rdata_next[0] = doorbell_c47_intr_qs; - reg_rdata_next[31:1] = doorbell_c47_preserve_mask_qs; - end - - addr_hit[479]: begin - reg_rdata_next[0] = completion_interrupt_c47_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c47_preserve_mask_qs; - end - - addr_hit[480]: begin - reg_rdata_next[31:0] = reserved_1_c48_qs; - end - - addr_hit[481]: begin - reg_rdata_next[0] = channel_status_c48_channel_free_qs; - reg_rdata_next[1] = channel_status_c48_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c48_field1_qs; - end - - addr_hit[482]: begin - reg_rdata_next[31:0] = reserved_2_c48_qs; - end - - addr_hit[483]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[484]: begin - reg_rdata_next[0] = channel_flags_c48_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c48_field1_qs; - end - - addr_hit[485]: begin - reg_rdata_next[31:0] = length_c48_qs; - end - - addr_hit[486]: begin - reg_rdata_next[7:0] = message_header_c48_message_id_qs; - reg_rdata_next[9:8] = message_header_c48_message_type_qs; - reg_rdata_next[17:10] = message_header_c48_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c48_token_qs; - reg_rdata_next[31:28] = message_header_c48_field1_qs; - end - - addr_hit[487]: begin - reg_rdata_next[31:0] = message_payload_1_c48_qs; - end - - addr_hit[488]: begin - reg_rdata_next[0] = doorbell_c48_intr_qs; - reg_rdata_next[31:1] = doorbell_c48_preserve_mask_qs; - end - - addr_hit[489]: begin - reg_rdata_next[0] = completion_interrupt_c48_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c48_preserve_mask_qs; - end - - addr_hit[490]: begin - reg_rdata_next[31:0] = reserved_1_c49_qs; - end - - addr_hit[491]: begin - reg_rdata_next[0] = channel_status_c49_channel_free_qs; - reg_rdata_next[1] = channel_status_c49_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c49_field1_qs; - end - - addr_hit[492]: begin - reg_rdata_next[31:0] = reserved_2_c49_qs; - end - - addr_hit[493]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[494]: begin - reg_rdata_next[0] = channel_flags_c49_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c49_field1_qs; - end - - addr_hit[495]: begin - reg_rdata_next[31:0] = length_c49_qs; - end - - addr_hit[496]: begin - reg_rdata_next[7:0] = message_header_c49_message_id_qs; - reg_rdata_next[9:8] = message_header_c49_message_type_qs; - reg_rdata_next[17:10] = message_header_c49_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c49_token_qs; - reg_rdata_next[31:28] = message_header_c49_field1_qs; - end - - addr_hit[497]: begin - reg_rdata_next[31:0] = message_payload_1_c49_qs; - end - - addr_hit[498]: begin - reg_rdata_next[0] = doorbell_c49_intr_qs; - reg_rdata_next[31:1] = doorbell_c49_preserve_mask_qs; - end - - addr_hit[499]: begin - reg_rdata_next[0] = completion_interrupt_c49_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c49_preserve_mask_qs; - end - - addr_hit[500]: begin - reg_rdata_next[31:0] = reserved_1_c50_qs; - end - - addr_hit[501]: begin - reg_rdata_next[0] = channel_status_c50_channel_free_qs; - reg_rdata_next[1] = channel_status_c50_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c50_field1_qs; - end - - addr_hit[502]: begin - reg_rdata_next[31:0] = reserved_2_c50_qs; - end - - addr_hit[503]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[504]: begin - reg_rdata_next[0] = channel_flags_c50_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c50_field1_qs; - end - - addr_hit[505]: begin - reg_rdata_next[31:0] = length_c50_qs; - end - - addr_hit[506]: begin - reg_rdata_next[7:0] = message_header_c50_message_id_qs; - reg_rdata_next[9:8] = message_header_c50_message_type_qs; - reg_rdata_next[17:10] = message_header_c50_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c50_token_qs; - reg_rdata_next[31:28] = message_header_c50_field1_qs; - end - - addr_hit[507]: begin - reg_rdata_next[31:0] = message_payload_1_c50_qs; - end - - addr_hit[508]: begin - reg_rdata_next[0] = doorbell_c50_intr_qs; - reg_rdata_next[31:1] = doorbell_c50_preserve_mask_qs; - end - - addr_hit[509]: begin - reg_rdata_next[0] = completion_interrupt_c50_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c50_preserve_mask_qs; - end - - addr_hit[510]: begin - reg_rdata_next[31:0] = reserved_1_c51_qs; - end - - addr_hit[511]: begin - reg_rdata_next[0] = channel_status_c51_channel_free_qs; - reg_rdata_next[1] = channel_status_c51_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c51_field1_qs; - end - - addr_hit[512]: begin - reg_rdata_next[31:0] = reserved_2_c51_qs; - end - - addr_hit[513]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[514]: begin - reg_rdata_next[0] = channel_flags_c51_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c51_field1_qs; - end - - addr_hit[515]: begin - reg_rdata_next[31:0] = length_c51_qs; - end - - addr_hit[516]: begin - reg_rdata_next[7:0] = message_header_c51_message_id_qs; - reg_rdata_next[9:8] = message_header_c51_message_type_qs; - reg_rdata_next[17:10] = message_header_c51_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c51_token_qs; - reg_rdata_next[31:28] = message_header_c51_field1_qs; - end - - addr_hit[517]: begin - reg_rdata_next[31:0] = message_payload_1_c51_qs; - end - - addr_hit[518]: begin - reg_rdata_next[0] = doorbell_c51_intr_qs; - reg_rdata_next[31:1] = doorbell_c51_preserve_mask_qs; - end - - addr_hit[519]: begin - reg_rdata_next[0] = completion_interrupt_c51_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c51_preserve_mask_qs; - end - - addr_hit[520]: begin - reg_rdata_next[31:0] = reserved_1_c52_qs; - end - - addr_hit[521]: begin - reg_rdata_next[0] = channel_status_c52_channel_free_qs; - reg_rdata_next[1] = channel_status_c52_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c52_field1_qs; - end - - addr_hit[522]: begin - reg_rdata_next[31:0] = reserved_2_c52_qs; - end - - addr_hit[523]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[524]: begin - reg_rdata_next[0] = channel_flags_c52_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c52_field1_qs; - end - - addr_hit[525]: begin - reg_rdata_next[31:0] = length_c52_qs; - end - - addr_hit[526]: begin - reg_rdata_next[7:0] = message_header_c52_message_id_qs; - reg_rdata_next[9:8] = message_header_c52_message_type_qs; - reg_rdata_next[17:10] = message_header_c52_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c52_token_qs; - reg_rdata_next[31:28] = message_header_c52_field1_qs; - end - - addr_hit[527]: begin - reg_rdata_next[31:0] = message_payload_1_c52_qs; - end - - addr_hit[528]: begin - reg_rdata_next[0] = doorbell_c52_intr_qs; - reg_rdata_next[31:1] = doorbell_c52_preserve_mask_qs; - end - - addr_hit[529]: begin - reg_rdata_next[0] = completion_interrupt_c52_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c52_preserve_mask_qs; - end - - addr_hit[530]: begin - reg_rdata_next[31:0] = reserved_1_c53_qs; - end - - addr_hit[531]: begin - reg_rdata_next[0] = channel_status_c53_channel_free_qs; - reg_rdata_next[1] = channel_status_c53_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c53_field1_qs; - end - - addr_hit[532]: begin - reg_rdata_next[31:0] = reserved_2_c53_qs; - end - - addr_hit[533]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[534]: begin - reg_rdata_next[0] = channel_flags_c53_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c53_field1_qs; - end - - addr_hit[535]: begin - reg_rdata_next[31:0] = length_c53_qs; - end - - addr_hit[536]: begin - reg_rdata_next[7:0] = message_header_c53_message_id_qs; - reg_rdata_next[9:8] = message_header_c53_message_type_qs; - reg_rdata_next[17:10] = message_header_c53_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c53_token_qs; - reg_rdata_next[31:28] = message_header_c53_field1_qs; - end - - addr_hit[537]: begin - reg_rdata_next[31:0] = message_payload_1_c53_qs; - end - - addr_hit[538]: begin - reg_rdata_next[0] = doorbell_c53_intr_qs; - reg_rdata_next[31:1] = doorbell_c53_preserve_mask_qs; - end - - addr_hit[539]: begin - reg_rdata_next[0] = completion_interrupt_c53_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c53_preserve_mask_qs; - end - - addr_hit[540]: begin - reg_rdata_next[31:0] = reserved_1_c54_qs; - end - - addr_hit[541]: begin - reg_rdata_next[0] = channel_status_c54_channel_free_qs; - reg_rdata_next[1] = channel_status_c54_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c54_field1_qs; - end - - addr_hit[542]: begin - reg_rdata_next[31:0] = reserved_2_c54_qs; - end - - addr_hit[543]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[544]: begin - reg_rdata_next[0] = channel_flags_c54_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c54_field1_qs; - end - - addr_hit[545]: begin - reg_rdata_next[31:0] = length_c54_qs; - end - - addr_hit[546]: begin - reg_rdata_next[7:0] = message_header_c54_message_id_qs; - reg_rdata_next[9:8] = message_header_c54_message_type_qs; - reg_rdata_next[17:10] = message_header_c54_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c54_token_qs; - reg_rdata_next[31:28] = message_header_c54_field1_qs; - end - - addr_hit[547]: begin - reg_rdata_next[31:0] = message_payload_1_c54_qs; - end - - addr_hit[548]: begin - reg_rdata_next[0] = doorbell_c54_intr_qs; - reg_rdata_next[31:1] = doorbell_c54_preserve_mask_qs; - end - - addr_hit[549]: begin - reg_rdata_next[0] = completion_interrupt_c54_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c54_preserve_mask_qs; - end - - addr_hit[550]: begin - reg_rdata_next[31:0] = reserved_1_c55_qs; - end - - addr_hit[551]: begin - reg_rdata_next[0] = channel_status_c55_channel_free_qs; - reg_rdata_next[1] = channel_status_c55_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c55_field1_qs; - end - - addr_hit[552]: begin - reg_rdata_next[31:0] = reserved_2_c55_qs; - end - - addr_hit[553]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[554]: begin - reg_rdata_next[0] = channel_flags_c55_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c55_field1_qs; - end - - addr_hit[555]: begin - reg_rdata_next[31:0] = length_c55_qs; - end - - addr_hit[556]: begin - reg_rdata_next[7:0] = message_header_c55_message_id_qs; - reg_rdata_next[9:8] = message_header_c55_message_type_qs; - reg_rdata_next[17:10] = message_header_c55_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c55_token_qs; - reg_rdata_next[31:28] = message_header_c55_field1_qs; - end - - addr_hit[557]: begin - reg_rdata_next[31:0] = message_payload_1_c55_qs; - end - - addr_hit[558]: begin - reg_rdata_next[0] = doorbell_c55_intr_qs; - reg_rdata_next[31:1] = doorbell_c55_preserve_mask_qs; - end - - addr_hit[559]: begin - reg_rdata_next[0] = completion_interrupt_c55_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c55_preserve_mask_qs; - end - - addr_hit[560]: begin - reg_rdata_next[31:0] = reserved_1_c56_qs; - end - - addr_hit[561]: begin - reg_rdata_next[0] = channel_status_c56_channel_free_qs; - reg_rdata_next[1] = channel_status_c56_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c56_field1_qs; - end - - addr_hit[562]: begin - reg_rdata_next[31:0] = reserved_2_c56_qs; - end - - addr_hit[563]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[564]: begin - reg_rdata_next[0] = channel_flags_c56_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c56_field1_qs; - end - - addr_hit[565]: begin - reg_rdata_next[31:0] = length_c56_qs; - end - - addr_hit[566]: begin - reg_rdata_next[7:0] = message_header_c56_message_id_qs; - reg_rdata_next[9:8] = message_header_c56_message_type_qs; - reg_rdata_next[17:10] = message_header_c56_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c56_token_qs; - reg_rdata_next[31:28] = message_header_c56_field1_qs; - end - - addr_hit[567]: begin - reg_rdata_next[31:0] = message_payload_1_c56_qs; - end - - addr_hit[568]: begin - reg_rdata_next[0] = doorbell_c56_intr_qs; - reg_rdata_next[31:1] = doorbell_c56_preserve_mask_qs; - end - - addr_hit[569]: begin - reg_rdata_next[0] = completion_interrupt_c56_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c56_preserve_mask_qs; - end - - addr_hit[570]: begin - reg_rdata_next[31:0] = reserved_1_c57_qs; - end - - addr_hit[571]: begin - reg_rdata_next[0] = channel_status_c57_channel_free_qs; - reg_rdata_next[1] = channel_status_c57_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c57_field1_qs; - end - - addr_hit[572]: begin - reg_rdata_next[31:0] = reserved_2_c57_qs; - end - - addr_hit[573]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[574]: begin - reg_rdata_next[0] = channel_flags_c57_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c57_field1_qs; - end - - addr_hit[575]: begin - reg_rdata_next[31:0] = length_c57_qs; - end - - addr_hit[576]: begin - reg_rdata_next[7:0] = message_header_c57_message_id_qs; - reg_rdata_next[9:8] = message_header_c57_message_type_qs; - reg_rdata_next[17:10] = message_header_c57_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c57_token_qs; - reg_rdata_next[31:28] = message_header_c57_field1_qs; - end - - addr_hit[577]: begin - reg_rdata_next[31:0] = message_payload_1_c57_qs; - end - - addr_hit[578]: begin - reg_rdata_next[0] = doorbell_c57_intr_qs; - reg_rdata_next[31:1] = doorbell_c57_preserve_mask_qs; - end - - addr_hit[579]: begin - reg_rdata_next[0] = completion_interrupt_c57_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c57_preserve_mask_qs; - end - - addr_hit[580]: begin - reg_rdata_next[31:0] = reserved_1_c58_qs; - end - - addr_hit[581]: begin - reg_rdata_next[0] = channel_status_c58_channel_free_qs; - reg_rdata_next[1] = channel_status_c58_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c58_field1_qs; - end - - addr_hit[582]: begin - reg_rdata_next[31:0] = reserved_2_c58_qs; - end - - addr_hit[583]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[584]: begin - reg_rdata_next[0] = channel_flags_c58_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c58_field1_qs; - end - - addr_hit[585]: begin - reg_rdata_next[31:0] = length_c58_qs; - end - - addr_hit[586]: begin - reg_rdata_next[7:0] = message_header_c58_message_id_qs; - reg_rdata_next[9:8] = message_header_c58_message_type_qs; - reg_rdata_next[17:10] = message_header_c58_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c58_token_qs; - reg_rdata_next[31:28] = message_header_c58_field1_qs; - end - - addr_hit[587]: begin - reg_rdata_next[31:0] = message_payload_1_c58_qs; - end - - addr_hit[588]: begin - reg_rdata_next[0] = doorbell_c58_intr_qs; - reg_rdata_next[31:1] = doorbell_c58_preserve_mask_qs; - end - - addr_hit[589]: begin - reg_rdata_next[0] = completion_interrupt_c58_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c58_preserve_mask_qs; - end - - addr_hit[590]: begin - reg_rdata_next[31:0] = reserved_1_c59_qs; - end - - addr_hit[591]: begin - reg_rdata_next[0] = channel_status_c59_channel_free_qs; - reg_rdata_next[1] = channel_status_c59_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c59_field1_qs; - end - - addr_hit[592]: begin - reg_rdata_next[31:0] = reserved_2_c59_qs; - end - - addr_hit[593]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[594]: begin - reg_rdata_next[0] = channel_flags_c59_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c59_field1_qs; - end - - addr_hit[595]: begin - reg_rdata_next[31:0] = length_c59_qs; - end - - addr_hit[596]: begin - reg_rdata_next[7:0] = message_header_c59_message_id_qs; - reg_rdata_next[9:8] = message_header_c59_message_type_qs; - reg_rdata_next[17:10] = message_header_c59_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c59_token_qs; - reg_rdata_next[31:28] = message_header_c59_field1_qs; - end - - addr_hit[597]: begin - reg_rdata_next[31:0] = message_payload_1_c59_qs; - end - - addr_hit[598]: begin - reg_rdata_next[0] = doorbell_c59_intr_qs; - reg_rdata_next[31:1] = doorbell_c59_preserve_mask_qs; - end - - addr_hit[599]: begin - reg_rdata_next[0] = completion_interrupt_c59_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c59_preserve_mask_qs; - end - - addr_hit[600]: begin - reg_rdata_next[31:0] = reserved_1_c60_qs; - end - - addr_hit[601]: begin - reg_rdata_next[0] = channel_status_c60_channel_free_qs; - reg_rdata_next[1] = channel_status_c60_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c60_field1_qs; - end - - addr_hit[602]: begin - reg_rdata_next[31:0] = reserved_2_c60_qs; - end - - addr_hit[603]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[604]: begin - reg_rdata_next[0] = channel_flags_c60_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c60_field1_qs; - end - - addr_hit[605]: begin - reg_rdata_next[31:0] = length_c60_qs; - end - - addr_hit[606]: begin - reg_rdata_next[7:0] = message_header_c60_message_id_qs; - reg_rdata_next[9:8] = message_header_c60_message_type_qs; - reg_rdata_next[17:10] = message_header_c60_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c60_token_qs; - reg_rdata_next[31:28] = message_header_c60_field1_qs; - end - - addr_hit[607]: begin - reg_rdata_next[31:0] = message_payload_1_c60_qs; - end - - addr_hit[608]: begin - reg_rdata_next[0] = doorbell_c60_intr_qs; - reg_rdata_next[31:1] = doorbell_c60_preserve_mask_qs; - end - - addr_hit[609]: begin - reg_rdata_next[0] = completion_interrupt_c60_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c60_preserve_mask_qs; - end - - addr_hit[610]: begin - reg_rdata_next[31:0] = reserved_1_c61_qs; - end - - addr_hit[611]: begin - reg_rdata_next[0] = channel_status_c61_channel_free_qs; - reg_rdata_next[1] = channel_status_c61_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c61_field1_qs; - end - - addr_hit[612]: begin - reg_rdata_next[31:0] = reserved_2_c61_qs; - end - - addr_hit[613]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[614]: begin - reg_rdata_next[0] = channel_flags_c61_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c61_field1_qs; - end - - addr_hit[615]: begin - reg_rdata_next[31:0] = length_c61_qs; - end - - addr_hit[616]: begin - reg_rdata_next[7:0] = message_header_c61_message_id_qs; - reg_rdata_next[9:8] = message_header_c61_message_type_qs; - reg_rdata_next[17:10] = message_header_c61_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c61_token_qs; - reg_rdata_next[31:28] = message_header_c61_field1_qs; - end - - addr_hit[617]: begin - reg_rdata_next[31:0] = message_payload_1_c61_qs; - end - - addr_hit[618]: begin - reg_rdata_next[0] = doorbell_c61_intr_qs; - reg_rdata_next[31:1] = doorbell_c61_preserve_mask_qs; - end - - addr_hit[619]: begin - reg_rdata_next[0] = completion_interrupt_c61_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c61_preserve_mask_qs; - end - - addr_hit[620]: begin - reg_rdata_next[31:0] = reserved_1_c62_qs; - end - - addr_hit[621]: begin - reg_rdata_next[0] = channel_status_c62_channel_free_qs; - reg_rdata_next[1] = channel_status_c62_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c62_field1_qs; - end - - addr_hit[622]: begin - reg_rdata_next[31:0] = reserved_2_c62_qs; - end - - addr_hit[623]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[624]: begin - reg_rdata_next[0] = channel_flags_c62_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c62_field1_qs; - end - - addr_hit[625]: begin - reg_rdata_next[31:0] = length_c62_qs; - end - - addr_hit[626]: begin - reg_rdata_next[7:0] = message_header_c62_message_id_qs; - reg_rdata_next[9:8] = message_header_c62_message_type_qs; - reg_rdata_next[17:10] = message_header_c62_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c62_token_qs; - reg_rdata_next[31:28] = message_header_c62_field1_qs; - end - - addr_hit[627]: begin - reg_rdata_next[31:0] = message_payload_1_c62_qs; - end - - addr_hit[628]: begin - reg_rdata_next[0] = doorbell_c62_intr_qs; - reg_rdata_next[31:1] = doorbell_c62_preserve_mask_qs; - end - - addr_hit[629]: begin - reg_rdata_next[0] = completion_interrupt_c62_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c62_preserve_mask_qs; - end - - addr_hit[630]: begin - reg_rdata_next[31:0] = reserved_1_c63_qs; - end - - addr_hit[631]: begin - reg_rdata_next[0] = channel_status_c63_channel_free_qs; - reg_rdata_next[1] = channel_status_c63_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c63_field1_qs; - end - - addr_hit[632]: begin - reg_rdata_next[31:0] = reserved_2_c63_qs; - end - - addr_hit[633]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[634]: begin - reg_rdata_next[0] = channel_flags_c63_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c63_field1_qs; - end - - addr_hit[635]: begin - reg_rdata_next[31:0] = length_c63_qs; - end - - addr_hit[636]: begin - reg_rdata_next[7:0] = message_header_c63_message_id_qs; - reg_rdata_next[9:8] = message_header_c63_message_type_qs; - reg_rdata_next[17:10] = message_header_c63_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c63_token_qs; - reg_rdata_next[31:28] = message_header_c63_field1_qs; - end - - addr_hit[637]: begin - reg_rdata_next[31:0] = message_payload_1_c63_qs; - end - - addr_hit[638]: begin - reg_rdata_next[0] = doorbell_c63_intr_qs; - reg_rdata_next[31:1] = doorbell_c63_preserve_mask_qs; - end - - addr_hit[639]: begin - reg_rdata_next[0] = completion_interrupt_c63_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c63_preserve_mask_qs; - end - - addr_hit[640]: begin - reg_rdata_next[31:0] = reserved_1_c64_qs; - end - - addr_hit[641]: begin - reg_rdata_next[0] = channel_status_c64_channel_free_qs; - reg_rdata_next[1] = channel_status_c64_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c64_field1_qs; - end - - addr_hit[642]: begin - reg_rdata_next[31:0] = reserved_2_c64_qs; - end - - addr_hit[643]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[644]: begin - reg_rdata_next[0] = channel_flags_c64_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c64_field1_qs; - end - - addr_hit[645]: begin - reg_rdata_next[31:0] = length_c64_qs; - end - - addr_hit[646]: begin - reg_rdata_next[7:0] = message_header_c64_message_id_qs; - reg_rdata_next[9:8] = message_header_c64_message_type_qs; - reg_rdata_next[17:10] = message_header_c64_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c64_token_qs; - reg_rdata_next[31:28] = message_header_c64_field1_qs; - end - - addr_hit[647]: begin - reg_rdata_next[31:0] = message_payload_1_c64_qs; - end - - addr_hit[648]: begin - reg_rdata_next[0] = doorbell_c64_intr_qs; - reg_rdata_next[31:1] = doorbell_c64_preserve_mask_qs; - end - - addr_hit[649]: begin - reg_rdata_next[0] = completion_interrupt_c64_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c64_preserve_mask_qs; - end - - addr_hit[650]: begin - reg_rdata_next[31:0] = reserved_1_c65_qs; - end - - addr_hit[651]: begin - reg_rdata_next[0] = channel_status_c65_channel_free_qs; - reg_rdata_next[1] = channel_status_c65_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c65_field1_qs; - end - - addr_hit[652]: begin - reg_rdata_next[31:0] = reserved_2_c65_qs; - end - - addr_hit[653]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[654]: begin - reg_rdata_next[0] = channel_flags_c65_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c65_field1_qs; - end - - addr_hit[655]: begin - reg_rdata_next[31:0] = length_c65_qs; - end - - addr_hit[656]: begin - reg_rdata_next[7:0] = message_header_c65_message_id_qs; - reg_rdata_next[9:8] = message_header_c65_message_type_qs; - reg_rdata_next[17:10] = message_header_c65_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c65_token_qs; - reg_rdata_next[31:28] = message_header_c65_field1_qs; - end - - addr_hit[657]: begin - reg_rdata_next[31:0] = message_payload_1_c65_qs; - end - - addr_hit[658]: begin - reg_rdata_next[0] = doorbell_c65_intr_qs; - reg_rdata_next[31:1] = doorbell_c65_preserve_mask_qs; - end - - addr_hit[659]: begin - reg_rdata_next[0] = completion_interrupt_c65_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c65_preserve_mask_qs; - end - - addr_hit[660]: begin - reg_rdata_next[31:0] = reserved_1_c66_qs; - end - - addr_hit[661]: begin - reg_rdata_next[0] = channel_status_c66_channel_free_qs; - reg_rdata_next[1] = channel_status_c66_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c66_field1_qs; - end - - addr_hit[662]: begin - reg_rdata_next[31:0] = reserved_2_c66_qs; - end - - addr_hit[663]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[664]: begin - reg_rdata_next[0] = channel_flags_c66_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c66_field1_qs; - end - - addr_hit[665]: begin - reg_rdata_next[31:0] = length_c66_qs; - end - - addr_hit[666]: begin - reg_rdata_next[7:0] = message_header_c66_message_id_qs; - reg_rdata_next[9:8] = message_header_c66_message_type_qs; - reg_rdata_next[17:10] = message_header_c66_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c66_token_qs; - reg_rdata_next[31:28] = message_header_c66_field1_qs; - end - - addr_hit[667]: begin - reg_rdata_next[31:0] = message_payload_1_c66_qs; - end - - addr_hit[668]: begin - reg_rdata_next[0] = doorbell_c66_intr_qs; - reg_rdata_next[31:1] = doorbell_c66_preserve_mask_qs; - end - - addr_hit[669]: begin - reg_rdata_next[0] = completion_interrupt_c66_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c66_preserve_mask_qs; - end - - addr_hit[670]: begin - reg_rdata_next[31:0] = reserved_1_c67_qs; - end - - addr_hit[671]: begin - reg_rdata_next[0] = channel_status_c67_channel_free_qs; - reg_rdata_next[1] = channel_status_c67_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c67_field1_qs; - end - - addr_hit[672]: begin - reg_rdata_next[31:0] = reserved_2_c67_qs; - end - - addr_hit[673]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[674]: begin - reg_rdata_next[0] = channel_flags_c67_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c67_field1_qs; - end - - addr_hit[675]: begin - reg_rdata_next[31:0] = length_c67_qs; - end - - addr_hit[676]: begin - reg_rdata_next[7:0] = message_header_c67_message_id_qs; - reg_rdata_next[9:8] = message_header_c67_message_type_qs; - reg_rdata_next[17:10] = message_header_c67_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c67_token_qs; - reg_rdata_next[31:28] = message_header_c67_field1_qs; - end - - addr_hit[677]: begin - reg_rdata_next[31:0] = message_payload_1_c67_qs; - end - - addr_hit[678]: begin - reg_rdata_next[0] = doorbell_c67_intr_qs; - reg_rdata_next[31:1] = doorbell_c67_preserve_mask_qs; - end - - addr_hit[679]: begin - reg_rdata_next[0] = completion_interrupt_c67_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c67_preserve_mask_qs; - end - - addr_hit[680]: begin - reg_rdata_next[31:0] = reserved_1_c68_qs; - end - - addr_hit[681]: begin - reg_rdata_next[0] = channel_status_c68_channel_free_qs; - reg_rdata_next[1] = channel_status_c68_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c68_field1_qs; - end - - addr_hit[682]: begin - reg_rdata_next[31:0] = reserved_2_c68_qs; - end - - addr_hit[683]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[684]: begin - reg_rdata_next[0] = channel_flags_c68_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c68_field1_qs; - end - - addr_hit[685]: begin - reg_rdata_next[31:0] = length_c68_qs; - end - - addr_hit[686]: begin - reg_rdata_next[7:0] = message_header_c68_message_id_qs; - reg_rdata_next[9:8] = message_header_c68_message_type_qs; - reg_rdata_next[17:10] = message_header_c68_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c68_token_qs; - reg_rdata_next[31:28] = message_header_c68_field1_qs; - end - - addr_hit[687]: begin - reg_rdata_next[31:0] = message_payload_1_c68_qs; - end - - addr_hit[688]: begin - reg_rdata_next[0] = doorbell_c68_intr_qs; - reg_rdata_next[31:1] = doorbell_c68_preserve_mask_qs; - end - - addr_hit[689]: begin - reg_rdata_next[0] = completion_interrupt_c68_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c68_preserve_mask_qs; - end - - addr_hit[690]: begin - reg_rdata_next[31:0] = reserved_1_c69_qs; - end - - addr_hit[691]: begin - reg_rdata_next[0] = channel_status_c69_channel_free_qs; - reg_rdata_next[1] = channel_status_c69_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c69_field1_qs; - end - - addr_hit[692]: begin - reg_rdata_next[31:0] = reserved_2_c69_qs; - end - - addr_hit[693]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[694]: begin - reg_rdata_next[0] = channel_flags_c69_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c69_field1_qs; - end - - addr_hit[695]: begin - reg_rdata_next[31:0] = length_c69_qs; - end - - addr_hit[696]: begin - reg_rdata_next[7:0] = message_header_c69_message_id_qs; - reg_rdata_next[9:8] = message_header_c69_message_type_qs; - reg_rdata_next[17:10] = message_header_c69_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c69_token_qs; - reg_rdata_next[31:28] = message_header_c69_field1_qs; - end - - addr_hit[697]: begin - reg_rdata_next[31:0] = message_payload_1_c69_qs; - end - - addr_hit[698]: begin - reg_rdata_next[0] = doorbell_c69_intr_qs; - reg_rdata_next[31:1] = doorbell_c69_preserve_mask_qs; - end - - addr_hit[699]: begin - reg_rdata_next[0] = completion_interrupt_c69_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c69_preserve_mask_qs; - end - - addr_hit[700]: begin - reg_rdata_next[31:0] = reserved_1_c70_qs; - end - - addr_hit[701]: begin - reg_rdata_next[0] = channel_status_c70_channel_free_qs; - reg_rdata_next[1] = channel_status_c70_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c70_field1_qs; - end - - addr_hit[702]: begin - reg_rdata_next[31:0] = reserved_2_c70_qs; - end - - addr_hit[703]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[704]: begin - reg_rdata_next[0] = channel_flags_c70_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c70_field1_qs; - end - - addr_hit[705]: begin - reg_rdata_next[31:0] = length_c70_qs; - end - - addr_hit[706]: begin - reg_rdata_next[7:0] = message_header_c70_message_id_qs; - reg_rdata_next[9:8] = message_header_c70_message_type_qs; - reg_rdata_next[17:10] = message_header_c70_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c70_token_qs; - reg_rdata_next[31:28] = message_header_c70_field1_qs; - end - - addr_hit[707]: begin - reg_rdata_next[31:0] = message_payload_1_c70_qs; - end - - addr_hit[708]: begin - reg_rdata_next[0] = doorbell_c70_intr_qs; - reg_rdata_next[31:1] = doorbell_c70_preserve_mask_qs; - end - - addr_hit[709]: begin - reg_rdata_next[0] = completion_interrupt_c70_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c70_preserve_mask_qs; - end - - addr_hit[710]: begin - reg_rdata_next[31:0] = reserved_1_c71_qs; - end - - addr_hit[711]: begin - reg_rdata_next[0] = channel_status_c71_channel_free_qs; - reg_rdata_next[1] = channel_status_c71_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c71_field1_qs; - end - - addr_hit[712]: begin - reg_rdata_next[31:0] = reserved_2_c71_qs; - end - - addr_hit[713]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[714]: begin - reg_rdata_next[0] = channel_flags_c71_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c71_field1_qs; - end - - addr_hit[715]: begin - reg_rdata_next[31:0] = length_c71_qs; - end - - addr_hit[716]: begin - reg_rdata_next[7:0] = message_header_c71_message_id_qs; - reg_rdata_next[9:8] = message_header_c71_message_type_qs; - reg_rdata_next[17:10] = message_header_c71_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c71_token_qs; - reg_rdata_next[31:28] = message_header_c71_field1_qs; - end - - addr_hit[717]: begin - reg_rdata_next[31:0] = message_payload_1_c71_qs; - end - - addr_hit[718]: begin - reg_rdata_next[0] = doorbell_c71_intr_qs; - reg_rdata_next[31:1] = doorbell_c71_preserve_mask_qs; - end - - addr_hit[719]: begin - reg_rdata_next[0] = completion_interrupt_c71_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c71_preserve_mask_qs; - end - - addr_hit[720]: begin - reg_rdata_next[31:0] = reserved_1_c72_qs; - end - - addr_hit[721]: begin - reg_rdata_next[0] = channel_status_c72_channel_free_qs; - reg_rdata_next[1] = channel_status_c72_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c72_field1_qs; - end - - addr_hit[722]: begin - reg_rdata_next[31:0] = reserved_2_c72_qs; - end - - addr_hit[723]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[724]: begin - reg_rdata_next[0] = channel_flags_c72_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c72_field1_qs; - end - - addr_hit[725]: begin - reg_rdata_next[31:0] = length_c72_qs; - end - - addr_hit[726]: begin - reg_rdata_next[7:0] = message_header_c72_message_id_qs; - reg_rdata_next[9:8] = message_header_c72_message_type_qs; - reg_rdata_next[17:10] = message_header_c72_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c72_token_qs; - reg_rdata_next[31:28] = message_header_c72_field1_qs; - end - - addr_hit[727]: begin - reg_rdata_next[31:0] = message_payload_1_c72_qs; - end - - addr_hit[728]: begin - reg_rdata_next[0] = doorbell_c72_intr_qs; - reg_rdata_next[31:1] = doorbell_c72_preserve_mask_qs; - end - - addr_hit[729]: begin - reg_rdata_next[0] = completion_interrupt_c72_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c72_preserve_mask_qs; - end - - addr_hit[730]: begin - reg_rdata_next[31:0] = reserved_1_c73_qs; - end - - addr_hit[731]: begin - reg_rdata_next[0] = channel_status_c73_channel_free_qs; - reg_rdata_next[1] = channel_status_c73_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c73_field1_qs; - end - - addr_hit[732]: begin - reg_rdata_next[31:0] = reserved_2_c73_qs; - end - - addr_hit[733]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[734]: begin - reg_rdata_next[0] = channel_flags_c73_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c73_field1_qs; - end - - addr_hit[735]: begin - reg_rdata_next[31:0] = length_c73_qs; - end - - addr_hit[736]: begin - reg_rdata_next[7:0] = message_header_c73_message_id_qs; - reg_rdata_next[9:8] = message_header_c73_message_type_qs; - reg_rdata_next[17:10] = message_header_c73_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c73_token_qs; - reg_rdata_next[31:28] = message_header_c73_field1_qs; - end - - addr_hit[737]: begin - reg_rdata_next[31:0] = message_payload_1_c73_qs; - end - - addr_hit[738]: begin - reg_rdata_next[0] = doorbell_c73_intr_qs; - reg_rdata_next[31:1] = doorbell_c73_preserve_mask_qs; - end - - addr_hit[739]: begin - reg_rdata_next[0] = completion_interrupt_c73_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c73_preserve_mask_qs; - end - - addr_hit[740]: begin - reg_rdata_next[31:0] = reserved_1_c74_qs; - end - - addr_hit[741]: begin - reg_rdata_next[0] = channel_status_c74_channel_free_qs; - reg_rdata_next[1] = channel_status_c74_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c74_field1_qs; - end - - addr_hit[742]: begin - reg_rdata_next[31:0] = reserved_2_c74_qs; - end - - addr_hit[743]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[744]: begin - reg_rdata_next[0] = channel_flags_c74_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c74_field1_qs; - end - - addr_hit[745]: begin - reg_rdata_next[31:0] = length_c74_qs; - end - - addr_hit[746]: begin - reg_rdata_next[7:0] = message_header_c74_message_id_qs; - reg_rdata_next[9:8] = message_header_c74_message_type_qs; - reg_rdata_next[17:10] = message_header_c74_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c74_token_qs; - reg_rdata_next[31:28] = message_header_c74_field1_qs; - end - - addr_hit[747]: begin - reg_rdata_next[31:0] = message_payload_1_c74_qs; - end - - addr_hit[748]: begin - reg_rdata_next[0] = doorbell_c74_intr_qs; - reg_rdata_next[31:1] = doorbell_c74_preserve_mask_qs; - end - - addr_hit[749]: begin - reg_rdata_next[0] = completion_interrupt_c74_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c74_preserve_mask_qs; - end - - addr_hit[750]: begin - reg_rdata_next[31:0] = reserved_1_c75_qs; - end - - addr_hit[751]: begin - reg_rdata_next[0] = channel_status_c75_channel_free_qs; - reg_rdata_next[1] = channel_status_c75_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c75_field1_qs; - end - - addr_hit[752]: begin - reg_rdata_next[31:0] = reserved_2_c75_qs; - end - - addr_hit[753]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[754]: begin - reg_rdata_next[0] = channel_flags_c75_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c75_field1_qs; - end - - addr_hit[755]: begin - reg_rdata_next[31:0] = length_c75_qs; - end - - addr_hit[756]: begin - reg_rdata_next[7:0] = message_header_c75_message_id_qs; - reg_rdata_next[9:8] = message_header_c75_message_type_qs; - reg_rdata_next[17:10] = message_header_c75_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c75_token_qs; - reg_rdata_next[31:28] = message_header_c75_field1_qs; - end - - addr_hit[757]: begin - reg_rdata_next[31:0] = message_payload_1_c75_qs; - end - - addr_hit[758]: begin - reg_rdata_next[0] = doorbell_c75_intr_qs; - reg_rdata_next[31:1] = doorbell_c75_preserve_mask_qs; - end - - addr_hit[759]: begin - reg_rdata_next[0] = completion_interrupt_c75_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c75_preserve_mask_qs; - end - - addr_hit[760]: begin - reg_rdata_next[31:0] = reserved_1_c76_qs; - end - - addr_hit[761]: begin - reg_rdata_next[0] = channel_status_c76_channel_free_qs; - reg_rdata_next[1] = channel_status_c76_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c76_field1_qs; - end - - addr_hit[762]: begin - reg_rdata_next[31:0] = reserved_2_c76_qs; - end - - addr_hit[763]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[764]: begin - reg_rdata_next[0] = channel_flags_c76_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c76_field1_qs; - end - - addr_hit[765]: begin - reg_rdata_next[31:0] = length_c76_qs; - end - - addr_hit[766]: begin - reg_rdata_next[7:0] = message_header_c76_message_id_qs; - reg_rdata_next[9:8] = message_header_c76_message_type_qs; - reg_rdata_next[17:10] = message_header_c76_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c76_token_qs; - reg_rdata_next[31:28] = message_header_c76_field1_qs; - end - - addr_hit[767]: begin - reg_rdata_next[31:0] = message_payload_1_c76_qs; - end - - addr_hit[768]: begin - reg_rdata_next[0] = doorbell_c76_intr_qs; - reg_rdata_next[31:1] = doorbell_c76_preserve_mask_qs; - end - - addr_hit[769]: begin - reg_rdata_next[0] = completion_interrupt_c76_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c76_preserve_mask_qs; - end - - addr_hit[770]: begin - reg_rdata_next[31:0] = reserved_1_c77_qs; - end - - addr_hit[771]: begin - reg_rdata_next[0] = channel_status_c77_channel_free_qs; - reg_rdata_next[1] = channel_status_c77_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c77_field1_qs; - end - - addr_hit[772]: begin - reg_rdata_next[31:0] = reserved_2_c77_qs; - end - - addr_hit[773]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[774]: begin - reg_rdata_next[0] = channel_flags_c77_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c77_field1_qs; - end - - addr_hit[775]: begin - reg_rdata_next[31:0] = length_c77_qs; - end - - addr_hit[776]: begin - reg_rdata_next[7:0] = message_header_c77_message_id_qs; - reg_rdata_next[9:8] = message_header_c77_message_type_qs; - reg_rdata_next[17:10] = message_header_c77_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c77_token_qs; - reg_rdata_next[31:28] = message_header_c77_field1_qs; - end - - addr_hit[777]: begin - reg_rdata_next[31:0] = message_payload_1_c77_qs; - end - - addr_hit[778]: begin - reg_rdata_next[0] = doorbell_c77_intr_qs; - reg_rdata_next[31:1] = doorbell_c77_preserve_mask_qs; - end - - addr_hit[779]: begin - reg_rdata_next[0] = completion_interrupt_c77_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c77_preserve_mask_qs; - end - - addr_hit[780]: begin - reg_rdata_next[31:0] = reserved_1_c78_qs; - end - - addr_hit[781]: begin - reg_rdata_next[0] = channel_status_c78_channel_free_qs; - reg_rdata_next[1] = channel_status_c78_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c78_field1_qs; - end - - addr_hit[782]: begin - reg_rdata_next[31:0] = reserved_2_c78_qs; - end - - addr_hit[783]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[784]: begin - reg_rdata_next[0] = channel_flags_c78_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c78_field1_qs; - end - - addr_hit[785]: begin - reg_rdata_next[31:0] = length_c78_qs; - end - - addr_hit[786]: begin - reg_rdata_next[7:0] = message_header_c78_message_id_qs; - reg_rdata_next[9:8] = message_header_c78_message_type_qs; - reg_rdata_next[17:10] = message_header_c78_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c78_token_qs; - reg_rdata_next[31:28] = message_header_c78_field1_qs; - end - - addr_hit[787]: begin - reg_rdata_next[31:0] = message_payload_1_c78_qs; - end - - addr_hit[788]: begin - reg_rdata_next[0] = doorbell_c78_intr_qs; - reg_rdata_next[31:1] = doorbell_c78_preserve_mask_qs; - end - - addr_hit[789]: begin - reg_rdata_next[0] = completion_interrupt_c78_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c78_preserve_mask_qs; - end - - addr_hit[790]: begin - reg_rdata_next[31:0] = reserved_1_c79_qs; - end - - addr_hit[791]: begin - reg_rdata_next[0] = channel_status_c79_channel_free_qs; - reg_rdata_next[1] = channel_status_c79_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c79_field1_qs; - end - - addr_hit[792]: begin - reg_rdata_next[31:0] = reserved_2_c79_qs; - end - - addr_hit[793]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[794]: begin - reg_rdata_next[0] = channel_flags_c79_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c79_field1_qs; - end - - addr_hit[795]: begin - reg_rdata_next[31:0] = length_c79_qs; - end - - addr_hit[796]: begin - reg_rdata_next[7:0] = message_header_c79_message_id_qs; - reg_rdata_next[9:8] = message_header_c79_message_type_qs; - reg_rdata_next[17:10] = message_header_c79_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c79_token_qs; - reg_rdata_next[31:28] = message_header_c79_field1_qs; - end - - addr_hit[797]: begin - reg_rdata_next[31:0] = message_payload_1_c79_qs; - end - - addr_hit[798]: begin - reg_rdata_next[0] = doorbell_c79_intr_qs; - reg_rdata_next[31:1] = doorbell_c79_preserve_mask_qs; - end - - addr_hit[799]: begin - reg_rdata_next[0] = completion_interrupt_c79_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c79_preserve_mask_qs; - end - - addr_hit[800]: begin - reg_rdata_next[31:0] = reserved_1_c80_qs; - end - - addr_hit[801]: begin - reg_rdata_next[0] = channel_status_c80_channel_free_qs; - reg_rdata_next[1] = channel_status_c80_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c80_field1_qs; - end - - addr_hit[802]: begin - reg_rdata_next[31:0] = reserved_2_c80_qs; - end - - addr_hit[803]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[804]: begin - reg_rdata_next[0] = channel_flags_c80_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c80_field1_qs; - end - - addr_hit[805]: begin - reg_rdata_next[31:0] = length_c80_qs; - end - - addr_hit[806]: begin - reg_rdata_next[7:0] = message_header_c80_message_id_qs; - reg_rdata_next[9:8] = message_header_c80_message_type_qs; - reg_rdata_next[17:10] = message_header_c80_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c80_token_qs; - reg_rdata_next[31:28] = message_header_c80_field1_qs; - end - - addr_hit[807]: begin - reg_rdata_next[31:0] = message_payload_1_c80_qs; - end - - addr_hit[808]: begin - reg_rdata_next[0] = doorbell_c80_intr_qs; - reg_rdata_next[31:1] = doorbell_c80_preserve_mask_qs; - end - - addr_hit[809]: begin - reg_rdata_next[0] = completion_interrupt_c80_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c80_preserve_mask_qs; - end - - addr_hit[810]: begin - reg_rdata_next[31:0] = reserved_1_c81_qs; - end - - addr_hit[811]: begin - reg_rdata_next[0] = channel_status_c81_channel_free_qs; - reg_rdata_next[1] = channel_status_c81_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c81_field1_qs; - end - - addr_hit[812]: begin - reg_rdata_next[31:0] = reserved_2_c81_qs; - end - - addr_hit[813]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[814]: begin - reg_rdata_next[0] = channel_flags_c81_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c81_field1_qs; - end - - addr_hit[815]: begin - reg_rdata_next[31:0] = length_c81_qs; - end - - addr_hit[816]: begin - reg_rdata_next[7:0] = message_header_c81_message_id_qs; - reg_rdata_next[9:8] = message_header_c81_message_type_qs; - reg_rdata_next[17:10] = message_header_c81_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c81_token_qs; - reg_rdata_next[31:28] = message_header_c81_field1_qs; - end - - addr_hit[817]: begin - reg_rdata_next[31:0] = message_payload_1_c81_qs; - end - - addr_hit[818]: begin - reg_rdata_next[0] = doorbell_c81_intr_qs; - reg_rdata_next[31:1] = doorbell_c81_preserve_mask_qs; - end - - addr_hit[819]: begin - reg_rdata_next[0] = completion_interrupt_c81_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c81_preserve_mask_qs; - end - - addr_hit[820]: begin - reg_rdata_next[31:0] = reserved_1_c82_qs; - end - - addr_hit[821]: begin - reg_rdata_next[0] = channel_status_c82_channel_free_qs; - reg_rdata_next[1] = channel_status_c82_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c82_field1_qs; - end - - addr_hit[822]: begin - reg_rdata_next[31:0] = reserved_2_c82_qs; - end - - addr_hit[823]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[824]: begin - reg_rdata_next[0] = channel_flags_c82_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c82_field1_qs; - end - - addr_hit[825]: begin - reg_rdata_next[31:0] = length_c82_qs; - end - - addr_hit[826]: begin - reg_rdata_next[7:0] = message_header_c82_message_id_qs; - reg_rdata_next[9:8] = message_header_c82_message_type_qs; - reg_rdata_next[17:10] = message_header_c82_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c82_token_qs; - reg_rdata_next[31:28] = message_header_c82_field1_qs; - end - - addr_hit[827]: begin - reg_rdata_next[31:0] = message_payload_1_c82_qs; - end - - addr_hit[828]: begin - reg_rdata_next[0] = doorbell_c82_intr_qs; - reg_rdata_next[31:1] = doorbell_c82_preserve_mask_qs; - end - - addr_hit[829]: begin - reg_rdata_next[0] = completion_interrupt_c82_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c82_preserve_mask_qs; - end - - addr_hit[830]: begin - reg_rdata_next[31:0] = reserved_1_c83_qs; - end - - addr_hit[831]: begin - reg_rdata_next[0] = channel_status_c83_channel_free_qs; - reg_rdata_next[1] = channel_status_c83_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c83_field1_qs; - end - - addr_hit[832]: begin - reg_rdata_next[31:0] = reserved_2_c83_qs; - end - - addr_hit[833]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[834]: begin - reg_rdata_next[0] = channel_flags_c83_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c83_field1_qs; - end - - addr_hit[835]: begin - reg_rdata_next[31:0] = length_c83_qs; - end - - addr_hit[836]: begin - reg_rdata_next[7:0] = message_header_c83_message_id_qs; - reg_rdata_next[9:8] = message_header_c83_message_type_qs; - reg_rdata_next[17:10] = message_header_c83_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c83_token_qs; - reg_rdata_next[31:28] = message_header_c83_field1_qs; - end - - addr_hit[837]: begin - reg_rdata_next[31:0] = message_payload_1_c83_qs; - end - - addr_hit[838]: begin - reg_rdata_next[0] = doorbell_c83_intr_qs; - reg_rdata_next[31:1] = doorbell_c83_preserve_mask_qs; - end - - addr_hit[839]: begin - reg_rdata_next[0] = completion_interrupt_c83_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c83_preserve_mask_qs; - end - - addr_hit[840]: begin - reg_rdata_next[31:0] = reserved_1_c84_qs; - end - - addr_hit[841]: begin - reg_rdata_next[0] = channel_status_c84_channel_free_qs; - reg_rdata_next[1] = channel_status_c84_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c84_field1_qs; - end - - addr_hit[842]: begin - reg_rdata_next[31:0] = reserved_2_c84_qs; - end - - addr_hit[843]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[844]: begin - reg_rdata_next[0] = channel_flags_c84_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c84_field1_qs; - end - - addr_hit[845]: begin - reg_rdata_next[31:0] = length_c84_qs; - end - - addr_hit[846]: begin - reg_rdata_next[7:0] = message_header_c84_message_id_qs; - reg_rdata_next[9:8] = message_header_c84_message_type_qs; - reg_rdata_next[17:10] = message_header_c84_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c84_token_qs; - reg_rdata_next[31:28] = message_header_c84_field1_qs; - end - - addr_hit[847]: begin - reg_rdata_next[31:0] = message_payload_1_c84_qs; - end - - addr_hit[848]: begin - reg_rdata_next[0] = doorbell_c84_intr_qs; - reg_rdata_next[31:1] = doorbell_c84_preserve_mask_qs; - end - - addr_hit[849]: begin - reg_rdata_next[0] = completion_interrupt_c84_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c84_preserve_mask_qs; - end - - addr_hit[850]: begin - reg_rdata_next[31:0] = reserved_1_c85_qs; - end - - addr_hit[851]: begin - reg_rdata_next[0] = channel_status_c85_channel_free_qs; - reg_rdata_next[1] = channel_status_c85_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c85_field1_qs; - end - - addr_hit[852]: begin - reg_rdata_next[31:0] = reserved_2_c85_qs; - end - - addr_hit[853]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[854]: begin - reg_rdata_next[0] = channel_flags_c85_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c85_field1_qs; - end - - addr_hit[855]: begin - reg_rdata_next[31:0] = length_c85_qs; - end - - addr_hit[856]: begin - reg_rdata_next[7:0] = message_header_c85_message_id_qs; - reg_rdata_next[9:8] = message_header_c85_message_type_qs; - reg_rdata_next[17:10] = message_header_c85_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c85_token_qs; - reg_rdata_next[31:28] = message_header_c85_field1_qs; - end - - addr_hit[857]: begin - reg_rdata_next[31:0] = message_payload_1_c85_qs; - end - - addr_hit[858]: begin - reg_rdata_next[0] = doorbell_c85_intr_qs; - reg_rdata_next[31:1] = doorbell_c85_preserve_mask_qs; - end - - addr_hit[859]: begin - reg_rdata_next[0] = completion_interrupt_c85_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c85_preserve_mask_qs; - end - - addr_hit[860]: begin - reg_rdata_next[31:0] = reserved_1_c86_qs; - end - - addr_hit[861]: begin - reg_rdata_next[0] = channel_status_c86_channel_free_qs; - reg_rdata_next[1] = channel_status_c86_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c86_field1_qs; - end - - addr_hit[862]: begin - reg_rdata_next[31:0] = reserved_2_c86_qs; - end - - addr_hit[863]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[864]: begin - reg_rdata_next[0] = channel_flags_c86_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c86_field1_qs; - end - - addr_hit[865]: begin - reg_rdata_next[31:0] = length_c86_qs; - end - - addr_hit[866]: begin - reg_rdata_next[7:0] = message_header_c86_message_id_qs; - reg_rdata_next[9:8] = message_header_c86_message_type_qs; - reg_rdata_next[17:10] = message_header_c86_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c86_token_qs; - reg_rdata_next[31:28] = message_header_c86_field1_qs; - end - - addr_hit[867]: begin - reg_rdata_next[31:0] = message_payload_1_c86_qs; - end - - addr_hit[868]: begin - reg_rdata_next[0] = doorbell_c86_intr_qs; - reg_rdata_next[31:1] = doorbell_c86_preserve_mask_qs; - end - - addr_hit[869]: begin - reg_rdata_next[0] = completion_interrupt_c86_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c86_preserve_mask_qs; - end - - addr_hit[870]: begin - reg_rdata_next[31:0] = reserved_1_c87_qs; - end - - addr_hit[871]: begin - reg_rdata_next[0] = channel_status_c87_channel_free_qs; - reg_rdata_next[1] = channel_status_c87_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c87_field1_qs; - end - - addr_hit[872]: begin - reg_rdata_next[31:0] = reserved_2_c87_qs; - end - - addr_hit[873]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[874]: begin - reg_rdata_next[0] = channel_flags_c87_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c87_field1_qs; - end - - addr_hit[875]: begin - reg_rdata_next[31:0] = length_c87_qs; - end - - addr_hit[876]: begin - reg_rdata_next[7:0] = message_header_c87_message_id_qs; - reg_rdata_next[9:8] = message_header_c87_message_type_qs; - reg_rdata_next[17:10] = message_header_c87_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c87_token_qs; - reg_rdata_next[31:28] = message_header_c87_field1_qs; - end - - addr_hit[877]: begin - reg_rdata_next[31:0] = message_payload_1_c87_qs; - end - - addr_hit[878]: begin - reg_rdata_next[0] = doorbell_c87_intr_qs; - reg_rdata_next[31:1] = doorbell_c87_preserve_mask_qs; - end - - addr_hit[879]: begin - reg_rdata_next[0] = completion_interrupt_c87_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c87_preserve_mask_qs; - end - - addr_hit[880]: begin - reg_rdata_next[31:0] = reserved_1_c88_qs; - end - - addr_hit[881]: begin - reg_rdata_next[0] = channel_status_c88_channel_free_qs; - reg_rdata_next[1] = channel_status_c88_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c88_field1_qs; - end - - addr_hit[882]: begin - reg_rdata_next[31:0] = reserved_2_c88_qs; - end - - addr_hit[883]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[884]: begin - reg_rdata_next[0] = channel_flags_c88_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c88_field1_qs; - end - - addr_hit[885]: begin - reg_rdata_next[31:0] = length_c88_qs; - end - - addr_hit[886]: begin - reg_rdata_next[7:0] = message_header_c88_message_id_qs; - reg_rdata_next[9:8] = message_header_c88_message_type_qs; - reg_rdata_next[17:10] = message_header_c88_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c88_token_qs; - reg_rdata_next[31:28] = message_header_c88_field1_qs; - end - - addr_hit[887]: begin - reg_rdata_next[31:0] = message_payload_1_c88_qs; - end - - addr_hit[888]: begin - reg_rdata_next[0] = doorbell_c88_intr_qs; - reg_rdata_next[31:1] = doorbell_c88_preserve_mask_qs; - end - - addr_hit[889]: begin - reg_rdata_next[0] = completion_interrupt_c88_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c88_preserve_mask_qs; - end - - addr_hit[890]: begin - reg_rdata_next[31:0] = reserved_1_c89_qs; - end - - addr_hit[891]: begin - reg_rdata_next[0] = channel_status_c89_channel_free_qs; - reg_rdata_next[1] = channel_status_c89_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c89_field1_qs; - end - - addr_hit[892]: begin - reg_rdata_next[31:0] = reserved_2_c89_qs; - end - - addr_hit[893]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[894]: begin - reg_rdata_next[0] = channel_flags_c89_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c89_field1_qs; - end - - addr_hit[895]: begin - reg_rdata_next[31:0] = length_c89_qs; - end - - addr_hit[896]: begin - reg_rdata_next[7:0] = message_header_c89_message_id_qs; - reg_rdata_next[9:8] = message_header_c89_message_type_qs; - reg_rdata_next[17:10] = message_header_c89_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c89_token_qs; - reg_rdata_next[31:28] = message_header_c89_field1_qs; - end - - addr_hit[897]: begin - reg_rdata_next[31:0] = message_payload_1_c89_qs; - end - - addr_hit[898]: begin - reg_rdata_next[0] = doorbell_c89_intr_qs; - reg_rdata_next[31:1] = doorbell_c89_preserve_mask_qs; - end - - addr_hit[899]: begin - reg_rdata_next[0] = completion_interrupt_c89_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c89_preserve_mask_qs; - end - - addr_hit[900]: begin - reg_rdata_next[31:0] = reserved_1_c90_qs; - end - - addr_hit[901]: begin - reg_rdata_next[0] = channel_status_c90_channel_free_qs; - reg_rdata_next[1] = channel_status_c90_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c90_field1_qs; - end - - addr_hit[902]: begin - reg_rdata_next[31:0] = reserved_2_c90_qs; - end - - addr_hit[903]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[904]: begin - reg_rdata_next[0] = channel_flags_c90_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c90_field1_qs; - end - - addr_hit[905]: begin - reg_rdata_next[31:0] = length_c90_qs; - end - - addr_hit[906]: begin - reg_rdata_next[7:0] = message_header_c90_message_id_qs; - reg_rdata_next[9:8] = message_header_c90_message_type_qs; - reg_rdata_next[17:10] = message_header_c90_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c90_token_qs; - reg_rdata_next[31:28] = message_header_c90_field1_qs; - end - - addr_hit[907]: begin - reg_rdata_next[31:0] = message_payload_1_c90_qs; - end - - addr_hit[908]: begin - reg_rdata_next[0] = doorbell_c90_intr_qs; - reg_rdata_next[31:1] = doorbell_c90_preserve_mask_qs; - end - - addr_hit[909]: begin - reg_rdata_next[0] = completion_interrupt_c90_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c90_preserve_mask_qs; - end - - addr_hit[910]: begin - reg_rdata_next[31:0] = reserved_1_c91_qs; - end - - addr_hit[911]: begin - reg_rdata_next[0] = channel_status_c91_channel_free_qs; - reg_rdata_next[1] = channel_status_c91_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c91_field1_qs; - end - - addr_hit[912]: begin - reg_rdata_next[31:0] = reserved_2_c91_qs; - end - - addr_hit[913]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[914]: begin - reg_rdata_next[0] = channel_flags_c91_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c91_field1_qs; - end - - addr_hit[915]: begin - reg_rdata_next[31:0] = length_c91_qs; - end - - addr_hit[916]: begin - reg_rdata_next[7:0] = message_header_c91_message_id_qs; - reg_rdata_next[9:8] = message_header_c91_message_type_qs; - reg_rdata_next[17:10] = message_header_c91_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c91_token_qs; - reg_rdata_next[31:28] = message_header_c91_field1_qs; - end - - addr_hit[917]: begin - reg_rdata_next[31:0] = message_payload_1_c91_qs; - end - - addr_hit[918]: begin - reg_rdata_next[0] = doorbell_c91_intr_qs; - reg_rdata_next[31:1] = doorbell_c91_preserve_mask_qs; - end - - addr_hit[919]: begin - reg_rdata_next[0] = completion_interrupt_c91_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c91_preserve_mask_qs; - end - - addr_hit[920]: begin - reg_rdata_next[31:0] = reserved_1_c92_qs; - end - - addr_hit[921]: begin - reg_rdata_next[0] = channel_status_c92_channel_free_qs; - reg_rdata_next[1] = channel_status_c92_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c92_field1_qs; - end - - addr_hit[922]: begin - reg_rdata_next[31:0] = reserved_2_c92_qs; - end - - addr_hit[923]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[924]: begin - reg_rdata_next[0] = channel_flags_c92_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c92_field1_qs; - end - - addr_hit[925]: begin - reg_rdata_next[31:0] = length_c92_qs; - end - - addr_hit[926]: begin - reg_rdata_next[7:0] = message_header_c92_message_id_qs; - reg_rdata_next[9:8] = message_header_c92_message_type_qs; - reg_rdata_next[17:10] = message_header_c92_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c92_token_qs; - reg_rdata_next[31:28] = message_header_c92_field1_qs; - end - - addr_hit[927]: begin - reg_rdata_next[31:0] = message_payload_1_c92_qs; - end - - addr_hit[928]: begin - reg_rdata_next[0] = doorbell_c92_intr_qs; - reg_rdata_next[31:1] = doorbell_c92_preserve_mask_qs; - end - - addr_hit[929]: begin - reg_rdata_next[0] = completion_interrupt_c92_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c92_preserve_mask_qs; - end - - addr_hit[930]: begin - reg_rdata_next[31:0] = reserved_1_c93_qs; - end - - addr_hit[931]: begin - reg_rdata_next[0] = channel_status_c93_channel_free_qs; - reg_rdata_next[1] = channel_status_c93_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c93_field1_qs; - end - - addr_hit[932]: begin - reg_rdata_next[31:0] = reserved_2_c93_qs; - end - - addr_hit[933]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[934]: begin - reg_rdata_next[0] = channel_flags_c93_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c93_field1_qs; - end - - addr_hit[935]: begin - reg_rdata_next[31:0] = length_c93_qs; - end - - addr_hit[936]: begin - reg_rdata_next[7:0] = message_header_c93_message_id_qs; - reg_rdata_next[9:8] = message_header_c93_message_type_qs; - reg_rdata_next[17:10] = message_header_c93_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c93_token_qs; - reg_rdata_next[31:28] = message_header_c93_field1_qs; - end - - addr_hit[937]: begin - reg_rdata_next[31:0] = message_payload_1_c93_qs; - end - - addr_hit[938]: begin - reg_rdata_next[0] = doorbell_c93_intr_qs; - reg_rdata_next[31:1] = doorbell_c93_preserve_mask_qs; - end - - addr_hit[939]: begin - reg_rdata_next[0] = completion_interrupt_c93_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c93_preserve_mask_qs; - end - - addr_hit[940]: begin - reg_rdata_next[31:0] = reserved_1_c94_qs; - end - - addr_hit[941]: begin - reg_rdata_next[0] = channel_status_c94_channel_free_qs; - reg_rdata_next[1] = channel_status_c94_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c94_field1_qs; - end - - addr_hit[942]: begin - reg_rdata_next[31:0] = reserved_2_c94_qs; - end - - addr_hit[943]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[944]: begin - reg_rdata_next[0] = channel_flags_c94_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c94_field1_qs; - end - - addr_hit[945]: begin - reg_rdata_next[31:0] = length_c94_qs; - end - - addr_hit[946]: begin - reg_rdata_next[7:0] = message_header_c94_message_id_qs; - reg_rdata_next[9:8] = message_header_c94_message_type_qs; - reg_rdata_next[17:10] = message_header_c94_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c94_token_qs; - reg_rdata_next[31:28] = message_header_c94_field1_qs; - end - - addr_hit[947]: begin - reg_rdata_next[31:0] = message_payload_1_c94_qs; - end - - addr_hit[948]: begin - reg_rdata_next[0] = doorbell_c94_intr_qs; - reg_rdata_next[31:1] = doorbell_c94_preserve_mask_qs; - end - - addr_hit[949]: begin - reg_rdata_next[0] = completion_interrupt_c94_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c94_preserve_mask_qs; - end - - addr_hit[950]: begin - reg_rdata_next[31:0] = reserved_1_c95_qs; - end - - addr_hit[951]: begin - reg_rdata_next[0] = channel_status_c95_channel_free_qs; - reg_rdata_next[1] = channel_status_c95_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c95_field1_qs; - end - - addr_hit[952]: begin - reg_rdata_next[31:0] = reserved_2_c95_qs; - end - - addr_hit[953]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[954]: begin - reg_rdata_next[0] = channel_flags_c95_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c95_field1_qs; - end - - addr_hit[955]: begin - reg_rdata_next[31:0] = length_c95_qs; - end - - addr_hit[956]: begin - reg_rdata_next[7:0] = message_header_c95_message_id_qs; - reg_rdata_next[9:8] = message_header_c95_message_type_qs; - reg_rdata_next[17:10] = message_header_c95_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c95_token_qs; - reg_rdata_next[31:28] = message_header_c95_field1_qs; - end - - addr_hit[957]: begin - reg_rdata_next[31:0] = message_payload_1_c95_qs; - end - - addr_hit[958]: begin - reg_rdata_next[0] = doorbell_c95_intr_qs; - reg_rdata_next[31:1] = doorbell_c95_preserve_mask_qs; - end - - addr_hit[959]: begin - reg_rdata_next[0] = completion_interrupt_c95_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c95_preserve_mask_qs; - end - - addr_hit[960]: begin - reg_rdata_next[31:0] = reserved_1_c96_qs; - end - - addr_hit[961]: begin - reg_rdata_next[0] = channel_status_c96_channel_free_qs; - reg_rdata_next[1] = channel_status_c96_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c96_field1_qs; - end - - addr_hit[962]: begin - reg_rdata_next[31:0] = reserved_2_c96_qs; - end - - addr_hit[963]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[964]: begin - reg_rdata_next[0] = channel_flags_c96_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c96_field1_qs; - end - - addr_hit[965]: begin - reg_rdata_next[31:0] = length_c96_qs; - end - - addr_hit[966]: begin - reg_rdata_next[7:0] = message_header_c96_message_id_qs; - reg_rdata_next[9:8] = message_header_c96_message_type_qs; - reg_rdata_next[17:10] = message_header_c96_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c96_token_qs; - reg_rdata_next[31:28] = message_header_c96_field1_qs; - end - - addr_hit[967]: begin - reg_rdata_next[31:0] = message_payload_1_c96_qs; - end - - addr_hit[968]: begin - reg_rdata_next[0] = doorbell_c96_intr_qs; - reg_rdata_next[31:1] = doorbell_c96_preserve_mask_qs; - end - - addr_hit[969]: begin - reg_rdata_next[0] = completion_interrupt_c96_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c96_preserve_mask_qs; - end - - addr_hit[970]: begin - reg_rdata_next[31:0] = reserved_1_c97_qs; - end - - addr_hit[971]: begin - reg_rdata_next[0] = channel_status_c97_channel_free_qs; - reg_rdata_next[1] = channel_status_c97_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c97_field1_qs; - end - - addr_hit[972]: begin - reg_rdata_next[31:0] = reserved_2_c97_qs; - end - - addr_hit[973]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[974]: begin - reg_rdata_next[0] = channel_flags_c97_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c97_field1_qs; - end - - addr_hit[975]: begin - reg_rdata_next[31:0] = length_c97_qs; - end - - addr_hit[976]: begin - reg_rdata_next[7:0] = message_header_c97_message_id_qs; - reg_rdata_next[9:8] = message_header_c97_message_type_qs; - reg_rdata_next[17:10] = message_header_c97_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c97_token_qs; - reg_rdata_next[31:28] = message_header_c97_field1_qs; - end - - addr_hit[977]: begin - reg_rdata_next[31:0] = message_payload_1_c97_qs; - end - - addr_hit[978]: begin - reg_rdata_next[0] = doorbell_c97_intr_qs; - reg_rdata_next[31:1] = doorbell_c97_preserve_mask_qs; - end - - addr_hit[979]: begin - reg_rdata_next[0] = completion_interrupt_c97_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c97_preserve_mask_qs; - end - - addr_hit[980]: begin - reg_rdata_next[31:0] = reserved_1_c98_qs; - end - - addr_hit[981]: begin - reg_rdata_next[0] = channel_status_c98_channel_free_qs; - reg_rdata_next[1] = channel_status_c98_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c98_field1_qs; - end - - addr_hit[982]: begin - reg_rdata_next[31:0] = reserved_2_c98_qs; - end - - addr_hit[983]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[984]: begin - reg_rdata_next[0] = channel_flags_c98_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c98_field1_qs; - end - - addr_hit[985]: begin - reg_rdata_next[31:0] = length_c98_qs; - end - - addr_hit[986]: begin - reg_rdata_next[7:0] = message_header_c98_message_id_qs; - reg_rdata_next[9:8] = message_header_c98_message_type_qs; - reg_rdata_next[17:10] = message_header_c98_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c98_token_qs; - reg_rdata_next[31:28] = message_header_c98_field1_qs; - end - - addr_hit[987]: begin - reg_rdata_next[31:0] = message_payload_1_c98_qs; - end - - addr_hit[988]: begin - reg_rdata_next[0] = doorbell_c98_intr_qs; - reg_rdata_next[31:1] = doorbell_c98_preserve_mask_qs; - end - - addr_hit[989]: begin - reg_rdata_next[0] = completion_interrupt_c98_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c98_preserve_mask_qs; - end - - addr_hit[990]: begin - reg_rdata_next[31:0] = reserved_1_c99_qs; - end - - addr_hit[991]: begin - reg_rdata_next[0] = channel_status_c99_channel_free_qs; - reg_rdata_next[1] = channel_status_c99_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c99_field1_qs; - end - - addr_hit[992]: begin - reg_rdata_next[31:0] = reserved_2_c99_qs; - end - - addr_hit[993]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[994]: begin - reg_rdata_next[0] = channel_flags_c99_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c99_field1_qs; - end - - addr_hit[995]: begin - reg_rdata_next[31:0] = length_c99_qs; - end - - addr_hit[996]: begin - reg_rdata_next[7:0] = message_header_c99_message_id_qs; - reg_rdata_next[9:8] = message_header_c99_message_type_qs; - reg_rdata_next[17:10] = message_header_c99_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c99_token_qs; - reg_rdata_next[31:28] = message_header_c99_field1_qs; - end - - addr_hit[997]: begin - reg_rdata_next[31:0] = message_payload_1_c99_qs; - end - - addr_hit[998]: begin - reg_rdata_next[0] = doorbell_c99_intr_qs; - reg_rdata_next[31:1] = doorbell_c99_preserve_mask_qs; - end - - addr_hit[999]: begin - reg_rdata_next[0] = completion_interrupt_c99_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c99_preserve_mask_qs; - end - - addr_hit[1000]: begin - reg_rdata_next[31:0] = reserved_1_c100_qs; - end - - addr_hit[1001]: begin - reg_rdata_next[0] = channel_status_c100_channel_free_qs; - reg_rdata_next[1] = channel_status_c100_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c100_field1_qs; - end - - addr_hit[1002]: begin - reg_rdata_next[31:0] = reserved_2_c100_qs; - end - - addr_hit[1003]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1004]: begin - reg_rdata_next[0] = channel_flags_c100_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c100_field1_qs; - end - - addr_hit[1005]: begin - reg_rdata_next[31:0] = length_c100_qs; - end - - addr_hit[1006]: begin - reg_rdata_next[7:0] = message_header_c100_message_id_qs; - reg_rdata_next[9:8] = message_header_c100_message_type_qs; - reg_rdata_next[17:10] = message_header_c100_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c100_token_qs; - reg_rdata_next[31:28] = message_header_c100_field1_qs; - end - - addr_hit[1007]: begin - reg_rdata_next[31:0] = message_payload_1_c100_qs; - end - - addr_hit[1008]: begin - reg_rdata_next[0] = doorbell_c100_intr_qs; - reg_rdata_next[31:1] = doorbell_c100_preserve_mask_qs; - end - - addr_hit[1009]: begin - reg_rdata_next[0] = completion_interrupt_c100_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c100_preserve_mask_qs; - end - - addr_hit[1010]: begin - reg_rdata_next[31:0] = reserved_1_c101_qs; - end - - addr_hit[1011]: begin - reg_rdata_next[0] = channel_status_c101_channel_free_qs; - reg_rdata_next[1] = channel_status_c101_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c101_field1_qs; - end - - addr_hit[1012]: begin - reg_rdata_next[31:0] = reserved_2_c101_qs; - end - - addr_hit[1013]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1014]: begin - reg_rdata_next[0] = channel_flags_c101_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c101_field1_qs; - end - - addr_hit[1015]: begin - reg_rdata_next[31:0] = length_c101_qs; - end - - addr_hit[1016]: begin - reg_rdata_next[7:0] = message_header_c101_message_id_qs; - reg_rdata_next[9:8] = message_header_c101_message_type_qs; - reg_rdata_next[17:10] = message_header_c101_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c101_token_qs; - reg_rdata_next[31:28] = message_header_c101_field1_qs; - end - - addr_hit[1017]: begin - reg_rdata_next[31:0] = message_payload_1_c101_qs; - end - - addr_hit[1018]: begin - reg_rdata_next[0] = doorbell_c101_intr_qs; - reg_rdata_next[31:1] = doorbell_c101_preserve_mask_qs; - end - - addr_hit[1019]: begin - reg_rdata_next[0] = completion_interrupt_c101_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c101_preserve_mask_qs; - end - - addr_hit[1020]: begin - reg_rdata_next[31:0] = reserved_1_c102_qs; - end - - addr_hit[1021]: begin - reg_rdata_next[0] = channel_status_c102_channel_free_qs; - reg_rdata_next[1] = channel_status_c102_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c102_field1_qs; - end - - addr_hit[1022]: begin - reg_rdata_next[31:0] = reserved_2_c102_qs; - end - - addr_hit[1023]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1024]: begin - reg_rdata_next[0] = channel_flags_c102_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c102_field1_qs; - end - - addr_hit[1025]: begin - reg_rdata_next[31:0] = length_c102_qs; - end - - addr_hit[1026]: begin - reg_rdata_next[7:0] = message_header_c102_message_id_qs; - reg_rdata_next[9:8] = message_header_c102_message_type_qs; - reg_rdata_next[17:10] = message_header_c102_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c102_token_qs; - reg_rdata_next[31:28] = message_header_c102_field1_qs; - end - - addr_hit[1027]: begin - reg_rdata_next[31:0] = message_payload_1_c102_qs; - end - - addr_hit[1028]: begin - reg_rdata_next[0] = doorbell_c102_intr_qs; - reg_rdata_next[31:1] = doorbell_c102_preserve_mask_qs; - end - - addr_hit[1029]: begin - reg_rdata_next[0] = completion_interrupt_c102_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c102_preserve_mask_qs; - end - - addr_hit[1030]: begin - reg_rdata_next[31:0] = reserved_1_c103_qs; - end - - addr_hit[1031]: begin - reg_rdata_next[0] = channel_status_c103_channel_free_qs; - reg_rdata_next[1] = channel_status_c103_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c103_field1_qs; - end - - addr_hit[1032]: begin - reg_rdata_next[31:0] = reserved_2_c103_qs; - end - - addr_hit[1033]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1034]: begin - reg_rdata_next[0] = channel_flags_c103_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c103_field1_qs; - end - - addr_hit[1035]: begin - reg_rdata_next[31:0] = length_c103_qs; - end - - addr_hit[1036]: begin - reg_rdata_next[7:0] = message_header_c103_message_id_qs; - reg_rdata_next[9:8] = message_header_c103_message_type_qs; - reg_rdata_next[17:10] = message_header_c103_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c103_token_qs; - reg_rdata_next[31:28] = message_header_c103_field1_qs; - end - - addr_hit[1037]: begin - reg_rdata_next[31:0] = message_payload_1_c103_qs; - end - - addr_hit[1038]: begin - reg_rdata_next[0] = doorbell_c103_intr_qs; - reg_rdata_next[31:1] = doorbell_c103_preserve_mask_qs; - end - - addr_hit[1039]: begin - reg_rdata_next[0] = completion_interrupt_c103_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c103_preserve_mask_qs; - end - - addr_hit[1040]: begin - reg_rdata_next[31:0] = reserved_1_c104_qs; - end - - addr_hit[1041]: begin - reg_rdata_next[0] = channel_status_c104_channel_free_qs; - reg_rdata_next[1] = channel_status_c104_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c104_field1_qs; - end - - addr_hit[1042]: begin - reg_rdata_next[31:0] = reserved_2_c104_qs; - end - - addr_hit[1043]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1044]: begin - reg_rdata_next[0] = channel_flags_c104_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c104_field1_qs; - end - - addr_hit[1045]: begin - reg_rdata_next[31:0] = length_c104_qs; - end - - addr_hit[1046]: begin - reg_rdata_next[7:0] = message_header_c104_message_id_qs; - reg_rdata_next[9:8] = message_header_c104_message_type_qs; - reg_rdata_next[17:10] = message_header_c104_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c104_token_qs; - reg_rdata_next[31:28] = message_header_c104_field1_qs; - end - - addr_hit[1047]: begin - reg_rdata_next[31:0] = message_payload_1_c104_qs; - end - - addr_hit[1048]: begin - reg_rdata_next[0] = doorbell_c104_intr_qs; - reg_rdata_next[31:1] = doorbell_c104_preserve_mask_qs; - end - - addr_hit[1049]: begin - reg_rdata_next[0] = completion_interrupt_c104_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c104_preserve_mask_qs; - end - - addr_hit[1050]: begin - reg_rdata_next[31:0] = reserved_1_c105_qs; - end - - addr_hit[1051]: begin - reg_rdata_next[0] = channel_status_c105_channel_free_qs; - reg_rdata_next[1] = channel_status_c105_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c105_field1_qs; - end - - addr_hit[1052]: begin - reg_rdata_next[31:0] = reserved_2_c105_qs; - end - - addr_hit[1053]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1054]: begin - reg_rdata_next[0] = channel_flags_c105_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c105_field1_qs; - end - - addr_hit[1055]: begin - reg_rdata_next[31:0] = length_c105_qs; - end - - addr_hit[1056]: begin - reg_rdata_next[7:0] = message_header_c105_message_id_qs; - reg_rdata_next[9:8] = message_header_c105_message_type_qs; - reg_rdata_next[17:10] = message_header_c105_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c105_token_qs; - reg_rdata_next[31:28] = message_header_c105_field1_qs; - end - - addr_hit[1057]: begin - reg_rdata_next[31:0] = message_payload_1_c105_qs; - end - - addr_hit[1058]: begin - reg_rdata_next[0] = doorbell_c105_intr_qs; - reg_rdata_next[31:1] = doorbell_c105_preserve_mask_qs; - end - - addr_hit[1059]: begin - reg_rdata_next[0] = completion_interrupt_c105_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c105_preserve_mask_qs; - end - - addr_hit[1060]: begin - reg_rdata_next[31:0] = reserved_1_c106_qs; - end - - addr_hit[1061]: begin - reg_rdata_next[0] = channel_status_c106_channel_free_qs; - reg_rdata_next[1] = channel_status_c106_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c106_field1_qs; - end - - addr_hit[1062]: begin - reg_rdata_next[31:0] = reserved_2_c106_qs; - end - - addr_hit[1063]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1064]: begin - reg_rdata_next[0] = channel_flags_c106_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c106_field1_qs; - end - - addr_hit[1065]: begin - reg_rdata_next[31:0] = length_c106_qs; - end - - addr_hit[1066]: begin - reg_rdata_next[7:0] = message_header_c106_message_id_qs; - reg_rdata_next[9:8] = message_header_c106_message_type_qs; - reg_rdata_next[17:10] = message_header_c106_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c106_token_qs; - reg_rdata_next[31:28] = message_header_c106_field1_qs; - end - - addr_hit[1067]: begin - reg_rdata_next[31:0] = message_payload_1_c106_qs; - end - - addr_hit[1068]: begin - reg_rdata_next[0] = doorbell_c106_intr_qs; - reg_rdata_next[31:1] = doorbell_c106_preserve_mask_qs; - end - - addr_hit[1069]: begin - reg_rdata_next[0] = completion_interrupt_c106_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c106_preserve_mask_qs; - end - - addr_hit[1070]: begin - reg_rdata_next[31:0] = reserved_1_c107_qs; - end - - addr_hit[1071]: begin - reg_rdata_next[0] = channel_status_c107_channel_free_qs; - reg_rdata_next[1] = channel_status_c107_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c107_field1_qs; - end - - addr_hit[1072]: begin - reg_rdata_next[31:0] = reserved_2_c107_qs; - end - - addr_hit[1073]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1074]: begin - reg_rdata_next[0] = channel_flags_c107_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c107_field1_qs; - end - - addr_hit[1075]: begin - reg_rdata_next[31:0] = length_c107_qs; - end - - addr_hit[1076]: begin - reg_rdata_next[7:0] = message_header_c107_message_id_qs; - reg_rdata_next[9:8] = message_header_c107_message_type_qs; - reg_rdata_next[17:10] = message_header_c107_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c107_token_qs; - reg_rdata_next[31:28] = message_header_c107_field1_qs; - end - - addr_hit[1077]: begin - reg_rdata_next[31:0] = message_payload_1_c107_qs; - end - - addr_hit[1078]: begin - reg_rdata_next[0] = doorbell_c107_intr_qs; - reg_rdata_next[31:1] = doorbell_c107_preserve_mask_qs; - end - - addr_hit[1079]: begin - reg_rdata_next[0] = completion_interrupt_c107_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c107_preserve_mask_qs; - end - - addr_hit[1080]: begin - reg_rdata_next[31:0] = reserved_1_c108_qs; - end - - addr_hit[1081]: begin - reg_rdata_next[0] = channel_status_c108_channel_free_qs; - reg_rdata_next[1] = channel_status_c108_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c108_field1_qs; - end - - addr_hit[1082]: begin - reg_rdata_next[31:0] = reserved_2_c108_qs; - end - - addr_hit[1083]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1084]: begin - reg_rdata_next[0] = channel_flags_c108_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c108_field1_qs; - end - - addr_hit[1085]: begin - reg_rdata_next[31:0] = length_c108_qs; - end - - addr_hit[1086]: begin - reg_rdata_next[7:0] = message_header_c108_message_id_qs; - reg_rdata_next[9:8] = message_header_c108_message_type_qs; - reg_rdata_next[17:10] = message_header_c108_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c108_token_qs; - reg_rdata_next[31:28] = message_header_c108_field1_qs; - end - - addr_hit[1087]: begin - reg_rdata_next[31:0] = message_payload_1_c108_qs; - end - - addr_hit[1088]: begin - reg_rdata_next[0] = doorbell_c108_intr_qs; - reg_rdata_next[31:1] = doorbell_c108_preserve_mask_qs; - end - - addr_hit[1089]: begin - reg_rdata_next[0] = completion_interrupt_c108_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c108_preserve_mask_qs; - end - - addr_hit[1090]: begin - reg_rdata_next[31:0] = reserved_1_c109_qs; - end - - addr_hit[1091]: begin - reg_rdata_next[0] = channel_status_c109_channel_free_qs; - reg_rdata_next[1] = channel_status_c109_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c109_field1_qs; - end - - addr_hit[1092]: begin - reg_rdata_next[31:0] = reserved_2_c109_qs; - end - - addr_hit[1093]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1094]: begin - reg_rdata_next[0] = channel_flags_c109_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c109_field1_qs; - end - - addr_hit[1095]: begin - reg_rdata_next[31:0] = length_c109_qs; - end - - addr_hit[1096]: begin - reg_rdata_next[7:0] = message_header_c109_message_id_qs; - reg_rdata_next[9:8] = message_header_c109_message_type_qs; - reg_rdata_next[17:10] = message_header_c109_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c109_token_qs; - reg_rdata_next[31:28] = message_header_c109_field1_qs; - end - - addr_hit[1097]: begin - reg_rdata_next[31:0] = message_payload_1_c109_qs; - end - - addr_hit[1098]: begin - reg_rdata_next[0] = doorbell_c109_intr_qs; - reg_rdata_next[31:1] = doorbell_c109_preserve_mask_qs; - end - - addr_hit[1099]: begin - reg_rdata_next[0] = completion_interrupt_c109_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c109_preserve_mask_qs; - end - - addr_hit[1100]: begin - reg_rdata_next[31:0] = reserved_1_c110_qs; - end - - addr_hit[1101]: begin - reg_rdata_next[0] = channel_status_c110_channel_free_qs; - reg_rdata_next[1] = channel_status_c110_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c110_field1_qs; - end - - addr_hit[1102]: begin - reg_rdata_next[31:0] = reserved_2_c110_qs; - end - - addr_hit[1103]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1104]: begin - reg_rdata_next[0] = channel_flags_c110_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c110_field1_qs; - end - - addr_hit[1105]: begin - reg_rdata_next[31:0] = length_c110_qs; - end - - addr_hit[1106]: begin - reg_rdata_next[7:0] = message_header_c110_message_id_qs; - reg_rdata_next[9:8] = message_header_c110_message_type_qs; - reg_rdata_next[17:10] = message_header_c110_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c110_token_qs; - reg_rdata_next[31:28] = message_header_c110_field1_qs; - end - - addr_hit[1107]: begin - reg_rdata_next[31:0] = message_payload_1_c110_qs; - end - - addr_hit[1108]: begin - reg_rdata_next[0] = doorbell_c110_intr_qs; - reg_rdata_next[31:1] = doorbell_c110_preserve_mask_qs; - end - - addr_hit[1109]: begin - reg_rdata_next[0] = completion_interrupt_c110_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c110_preserve_mask_qs; - end - - addr_hit[1110]: begin - reg_rdata_next[31:0] = reserved_1_c111_qs; - end - - addr_hit[1111]: begin - reg_rdata_next[0] = channel_status_c111_channel_free_qs; - reg_rdata_next[1] = channel_status_c111_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c111_field1_qs; - end - - addr_hit[1112]: begin - reg_rdata_next[31:0] = reserved_2_c111_qs; - end - - addr_hit[1113]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1114]: begin - reg_rdata_next[0] = channel_flags_c111_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c111_field1_qs; - end - - addr_hit[1115]: begin - reg_rdata_next[31:0] = length_c111_qs; - end - - addr_hit[1116]: begin - reg_rdata_next[7:0] = message_header_c111_message_id_qs; - reg_rdata_next[9:8] = message_header_c111_message_type_qs; - reg_rdata_next[17:10] = message_header_c111_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c111_token_qs; - reg_rdata_next[31:28] = message_header_c111_field1_qs; - end - - addr_hit[1117]: begin - reg_rdata_next[31:0] = message_payload_1_c111_qs; - end - - addr_hit[1118]: begin - reg_rdata_next[0] = doorbell_c111_intr_qs; - reg_rdata_next[31:1] = doorbell_c111_preserve_mask_qs; - end - - addr_hit[1119]: begin - reg_rdata_next[0] = completion_interrupt_c111_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c111_preserve_mask_qs; - end - - addr_hit[1120]: begin - reg_rdata_next[31:0] = reserved_1_c112_qs; - end - - addr_hit[1121]: begin - reg_rdata_next[0] = channel_status_c112_channel_free_qs; - reg_rdata_next[1] = channel_status_c112_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c112_field1_qs; - end - - addr_hit[1122]: begin - reg_rdata_next[31:0] = reserved_2_c112_qs; - end - - addr_hit[1123]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1124]: begin - reg_rdata_next[0] = channel_flags_c112_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c112_field1_qs; - end - - addr_hit[1125]: begin - reg_rdata_next[31:0] = length_c112_qs; - end - - addr_hit[1126]: begin - reg_rdata_next[7:0] = message_header_c112_message_id_qs; - reg_rdata_next[9:8] = message_header_c112_message_type_qs; - reg_rdata_next[17:10] = message_header_c112_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c112_token_qs; - reg_rdata_next[31:28] = message_header_c112_field1_qs; - end - - addr_hit[1127]: begin - reg_rdata_next[31:0] = message_payload_1_c112_qs; - end - - addr_hit[1128]: begin - reg_rdata_next[0] = doorbell_c112_intr_qs; - reg_rdata_next[31:1] = doorbell_c112_preserve_mask_qs; - end - - addr_hit[1129]: begin - reg_rdata_next[0] = completion_interrupt_c112_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c112_preserve_mask_qs; - end - - addr_hit[1130]: begin - reg_rdata_next[31:0] = reserved_1_c113_qs; - end - - addr_hit[1131]: begin - reg_rdata_next[0] = channel_status_c113_channel_free_qs; - reg_rdata_next[1] = channel_status_c113_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c113_field1_qs; - end - - addr_hit[1132]: begin - reg_rdata_next[31:0] = reserved_2_c113_qs; - end - - addr_hit[1133]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1134]: begin - reg_rdata_next[0] = channel_flags_c113_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c113_field1_qs; - end - - addr_hit[1135]: begin - reg_rdata_next[31:0] = length_c113_qs; - end - - addr_hit[1136]: begin - reg_rdata_next[7:0] = message_header_c113_message_id_qs; - reg_rdata_next[9:8] = message_header_c113_message_type_qs; - reg_rdata_next[17:10] = message_header_c113_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c113_token_qs; - reg_rdata_next[31:28] = message_header_c113_field1_qs; - end - - addr_hit[1137]: begin - reg_rdata_next[31:0] = message_payload_1_c113_qs; - end - - addr_hit[1138]: begin - reg_rdata_next[0] = doorbell_c113_intr_qs; - reg_rdata_next[31:1] = doorbell_c113_preserve_mask_qs; - end - - addr_hit[1139]: begin - reg_rdata_next[0] = completion_interrupt_c113_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c113_preserve_mask_qs; - end - - addr_hit[1140]: begin - reg_rdata_next[31:0] = reserved_1_c114_qs; - end - - addr_hit[1141]: begin - reg_rdata_next[0] = channel_status_c114_channel_free_qs; - reg_rdata_next[1] = channel_status_c114_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c114_field1_qs; - end - - addr_hit[1142]: begin - reg_rdata_next[31:0] = reserved_2_c114_qs; - end - - addr_hit[1143]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1144]: begin - reg_rdata_next[0] = channel_flags_c114_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c114_field1_qs; - end - - addr_hit[1145]: begin - reg_rdata_next[31:0] = length_c114_qs; - end - - addr_hit[1146]: begin - reg_rdata_next[7:0] = message_header_c114_message_id_qs; - reg_rdata_next[9:8] = message_header_c114_message_type_qs; - reg_rdata_next[17:10] = message_header_c114_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c114_token_qs; - reg_rdata_next[31:28] = message_header_c114_field1_qs; - end - - addr_hit[1147]: begin - reg_rdata_next[31:0] = message_payload_1_c114_qs; - end - - addr_hit[1148]: begin - reg_rdata_next[0] = doorbell_c114_intr_qs; - reg_rdata_next[31:1] = doorbell_c114_preserve_mask_qs; - end - - addr_hit[1149]: begin - reg_rdata_next[0] = completion_interrupt_c114_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c114_preserve_mask_qs; - end - - addr_hit[1150]: begin - reg_rdata_next[31:0] = reserved_1_c115_qs; - end - - addr_hit[1151]: begin - reg_rdata_next[0] = channel_status_c115_channel_free_qs; - reg_rdata_next[1] = channel_status_c115_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c115_field1_qs; - end - - addr_hit[1152]: begin - reg_rdata_next[31:0] = reserved_2_c115_qs; - end - - addr_hit[1153]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1154]: begin - reg_rdata_next[0] = channel_flags_c115_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c115_field1_qs; - end - - addr_hit[1155]: begin - reg_rdata_next[31:0] = length_c115_qs; - end - - addr_hit[1156]: begin - reg_rdata_next[7:0] = message_header_c115_message_id_qs; - reg_rdata_next[9:8] = message_header_c115_message_type_qs; - reg_rdata_next[17:10] = message_header_c115_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c115_token_qs; - reg_rdata_next[31:28] = message_header_c115_field1_qs; - end - - addr_hit[1157]: begin - reg_rdata_next[31:0] = message_payload_1_c115_qs; - end - - addr_hit[1158]: begin - reg_rdata_next[0] = doorbell_c115_intr_qs; - reg_rdata_next[31:1] = doorbell_c115_preserve_mask_qs; - end - - addr_hit[1159]: begin - reg_rdata_next[0] = completion_interrupt_c115_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c115_preserve_mask_qs; - end - - addr_hit[1160]: begin - reg_rdata_next[31:0] = reserved_1_c116_qs; - end - - addr_hit[1161]: begin - reg_rdata_next[0] = channel_status_c116_channel_free_qs; - reg_rdata_next[1] = channel_status_c116_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c116_field1_qs; - end - - addr_hit[1162]: begin - reg_rdata_next[31:0] = reserved_2_c116_qs; - end - - addr_hit[1163]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1164]: begin - reg_rdata_next[0] = channel_flags_c116_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c116_field1_qs; - end - - addr_hit[1165]: begin - reg_rdata_next[31:0] = length_c116_qs; - end - - addr_hit[1166]: begin - reg_rdata_next[7:0] = message_header_c116_message_id_qs; - reg_rdata_next[9:8] = message_header_c116_message_type_qs; - reg_rdata_next[17:10] = message_header_c116_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c116_token_qs; - reg_rdata_next[31:28] = message_header_c116_field1_qs; - end - - addr_hit[1167]: begin - reg_rdata_next[31:0] = message_payload_1_c116_qs; - end - - addr_hit[1168]: begin - reg_rdata_next[0] = doorbell_c116_intr_qs; - reg_rdata_next[31:1] = doorbell_c116_preserve_mask_qs; - end - - addr_hit[1169]: begin - reg_rdata_next[0] = completion_interrupt_c116_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c116_preserve_mask_qs; - end - - addr_hit[1170]: begin - reg_rdata_next[31:0] = reserved_1_c117_qs; - end - - addr_hit[1171]: begin - reg_rdata_next[0] = channel_status_c117_channel_free_qs; - reg_rdata_next[1] = channel_status_c117_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c117_field1_qs; - end - - addr_hit[1172]: begin - reg_rdata_next[31:0] = reserved_2_c117_qs; - end - - addr_hit[1173]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1174]: begin - reg_rdata_next[0] = channel_flags_c117_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c117_field1_qs; - end - - addr_hit[1175]: begin - reg_rdata_next[31:0] = length_c117_qs; - end - - addr_hit[1176]: begin - reg_rdata_next[7:0] = message_header_c117_message_id_qs; - reg_rdata_next[9:8] = message_header_c117_message_type_qs; - reg_rdata_next[17:10] = message_header_c117_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c117_token_qs; - reg_rdata_next[31:28] = message_header_c117_field1_qs; - end - - addr_hit[1177]: begin - reg_rdata_next[31:0] = message_payload_1_c117_qs; - end - - addr_hit[1178]: begin - reg_rdata_next[0] = doorbell_c117_intr_qs; - reg_rdata_next[31:1] = doorbell_c117_preserve_mask_qs; - end - - addr_hit[1179]: begin - reg_rdata_next[0] = completion_interrupt_c117_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c117_preserve_mask_qs; - end - - addr_hit[1180]: begin - reg_rdata_next[31:0] = reserved_1_c118_qs; - end - - addr_hit[1181]: begin - reg_rdata_next[0] = channel_status_c118_channel_free_qs; - reg_rdata_next[1] = channel_status_c118_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c118_field1_qs; - end - - addr_hit[1182]: begin - reg_rdata_next[31:0] = reserved_2_c118_qs; - end - - addr_hit[1183]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1184]: begin - reg_rdata_next[0] = channel_flags_c118_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c118_field1_qs; - end - - addr_hit[1185]: begin - reg_rdata_next[31:0] = length_c118_qs; - end - - addr_hit[1186]: begin - reg_rdata_next[7:0] = message_header_c118_message_id_qs; - reg_rdata_next[9:8] = message_header_c118_message_type_qs; - reg_rdata_next[17:10] = message_header_c118_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c118_token_qs; - reg_rdata_next[31:28] = message_header_c118_field1_qs; - end - - addr_hit[1187]: begin - reg_rdata_next[31:0] = message_payload_1_c118_qs; - end - - addr_hit[1188]: begin - reg_rdata_next[0] = doorbell_c118_intr_qs; - reg_rdata_next[31:1] = doorbell_c118_preserve_mask_qs; - end - - addr_hit[1189]: begin - reg_rdata_next[0] = completion_interrupt_c118_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c118_preserve_mask_qs; - end - - addr_hit[1190]: begin - reg_rdata_next[31:0] = reserved_1_c119_qs; - end - - addr_hit[1191]: begin - reg_rdata_next[0] = channel_status_c119_channel_free_qs; - reg_rdata_next[1] = channel_status_c119_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c119_field1_qs; - end - - addr_hit[1192]: begin - reg_rdata_next[31:0] = reserved_2_c119_qs; - end - - addr_hit[1193]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1194]: begin - reg_rdata_next[0] = channel_flags_c119_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c119_field1_qs; - end - - addr_hit[1195]: begin - reg_rdata_next[31:0] = length_c119_qs; - end - - addr_hit[1196]: begin - reg_rdata_next[7:0] = message_header_c119_message_id_qs; - reg_rdata_next[9:8] = message_header_c119_message_type_qs; - reg_rdata_next[17:10] = message_header_c119_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c119_token_qs; - reg_rdata_next[31:28] = message_header_c119_field1_qs; - end - - addr_hit[1197]: begin - reg_rdata_next[31:0] = message_payload_1_c119_qs; - end - - addr_hit[1198]: begin - reg_rdata_next[0] = doorbell_c119_intr_qs; - reg_rdata_next[31:1] = doorbell_c119_preserve_mask_qs; - end - - addr_hit[1199]: begin - reg_rdata_next[0] = completion_interrupt_c119_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c119_preserve_mask_qs; - end - - addr_hit[1200]: begin - reg_rdata_next[31:0] = reserved_1_c120_qs; - end - - addr_hit[1201]: begin - reg_rdata_next[0] = channel_status_c120_channel_free_qs; - reg_rdata_next[1] = channel_status_c120_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c120_field1_qs; - end - - addr_hit[1202]: begin - reg_rdata_next[31:0] = reserved_2_c120_qs; - end - - addr_hit[1203]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1204]: begin - reg_rdata_next[0] = channel_flags_c120_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c120_field1_qs; - end - - addr_hit[1205]: begin - reg_rdata_next[31:0] = length_c120_qs; - end - - addr_hit[1206]: begin - reg_rdata_next[7:0] = message_header_c120_message_id_qs; - reg_rdata_next[9:8] = message_header_c120_message_type_qs; - reg_rdata_next[17:10] = message_header_c120_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c120_token_qs; - reg_rdata_next[31:28] = message_header_c120_field1_qs; - end - - addr_hit[1207]: begin - reg_rdata_next[31:0] = message_payload_1_c120_qs; - end - - addr_hit[1208]: begin - reg_rdata_next[0] = doorbell_c120_intr_qs; - reg_rdata_next[31:1] = doorbell_c120_preserve_mask_qs; - end - - addr_hit[1209]: begin - reg_rdata_next[0] = completion_interrupt_c120_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c120_preserve_mask_qs; - end - - addr_hit[1210]: begin - reg_rdata_next[31:0] = reserved_1_c121_qs; - end - - addr_hit[1211]: begin - reg_rdata_next[0] = channel_status_c121_channel_free_qs; - reg_rdata_next[1] = channel_status_c121_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c121_field1_qs; - end - - addr_hit[1212]: begin - reg_rdata_next[31:0] = reserved_2_c121_qs; - end - - addr_hit[1213]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1214]: begin - reg_rdata_next[0] = channel_flags_c121_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c121_field1_qs; - end - - addr_hit[1215]: begin - reg_rdata_next[31:0] = length_c121_qs; - end - - addr_hit[1216]: begin - reg_rdata_next[7:0] = message_header_c121_message_id_qs; - reg_rdata_next[9:8] = message_header_c121_message_type_qs; - reg_rdata_next[17:10] = message_header_c121_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c121_token_qs; - reg_rdata_next[31:28] = message_header_c121_field1_qs; - end - - addr_hit[1217]: begin - reg_rdata_next[31:0] = message_payload_1_c121_qs; - end - - addr_hit[1218]: begin - reg_rdata_next[0] = doorbell_c121_intr_qs; - reg_rdata_next[31:1] = doorbell_c121_preserve_mask_qs; - end - - addr_hit[1219]: begin - reg_rdata_next[0] = completion_interrupt_c121_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c121_preserve_mask_qs; - end - - addr_hit[1220]: begin - reg_rdata_next[31:0] = reserved_1_c122_qs; - end - - addr_hit[1221]: begin - reg_rdata_next[0] = channel_status_c122_channel_free_qs; - reg_rdata_next[1] = channel_status_c122_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c122_field1_qs; - end - - addr_hit[1222]: begin - reg_rdata_next[31:0] = reserved_2_c122_qs; - end - - addr_hit[1223]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1224]: begin - reg_rdata_next[0] = channel_flags_c122_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c122_field1_qs; - end - - addr_hit[1225]: begin - reg_rdata_next[31:0] = length_c122_qs; - end - - addr_hit[1226]: begin - reg_rdata_next[7:0] = message_header_c122_message_id_qs; - reg_rdata_next[9:8] = message_header_c122_message_type_qs; - reg_rdata_next[17:10] = message_header_c122_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c122_token_qs; - reg_rdata_next[31:28] = message_header_c122_field1_qs; - end - - addr_hit[1227]: begin - reg_rdata_next[31:0] = message_payload_1_c122_qs; - end - - addr_hit[1228]: begin - reg_rdata_next[0] = doorbell_c122_intr_qs; - reg_rdata_next[31:1] = doorbell_c122_preserve_mask_qs; - end - - addr_hit[1229]: begin - reg_rdata_next[0] = completion_interrupt_c122_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c122_preserve_mask_qs; - end - - addr_hit[1230]: begin - reg_rdata_next[31:0] = reserved_1_c123_qs; - end - - addr_hit[1231]: begin - reg_rdata_next[0] = channel_status_c123_channel_free_qs; - reg_rdata_next[1] = channel_status_c123_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c123_field1_qs; - end - - addr_hit[1232]: begin - reg_rdata_next[31:0] = reserved_2_c123_qs; - end - - addr_hit[1233]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1234]: begin - reg_rdata_next[0] = channel_flags_c123_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c123_field1_qs; - end - - addr_hit[1235]: begin - reg_rdata_next[31:0] = length_c123_qs; - end - - addr_hit[1236]: begin - reg_rdata_next[7:0] = message_header_c123_message_id_qs; - reg_rdata_next[9:8] = message_header_c123_message_type_qs; - reg_rdata_next[17:10] = message_header_c123_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c123_token_qs; - reg_rdata_next[31:28] = message_header_c123_field1_qs; - end - - addr_hit[1237]: begin - reg_rdata_next[31:0] = message_payload_1_c123_qs; - end - - addr_hit[1238]: begin - reg_rdata_next[0] = doorbell_c123_intr_qs; - reg_rdata_next[31:1] = doorbell_c123_preserve_mask_qs; - end - - addr_hit[1239]: begin - reg_rdata_next[0] = completion_interrupt_c123_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c123_preserve_mask_qs; - end - - addr_hit[1240]: begin - reg_rdata_next[31:0] = reserved_1_c124_qs; - end - - addr_hit[1241]: begin - reg_rdata_next[0] = channel_status_c124_channel_free_qs; - reg_rdata_next[1] = channel_status_c124_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c124_field1_qs; - end - - addr_hit[1242]: begin - reg_rdata_next[31:0] = reserved_2_c124_qs; - end - - addr_hit[1243]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1244]: begin - reg_rdata_next[0] = channel_flags_c124_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c124_field1_qs; - end - - addr_hit[1245]: begin - reg_rdata_next[31:0] = length_c124_qs; - end - - addr_hit[1246]: begin - reg_rdata_next[7:0] = message_header_c124_message_id_qs; - reg_rdata_next[9:8] = message_header_c124_message_type_qs; - reg_rdata_next[17:10] = message_header_c124_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c124_token_qs; - reg_rdata_next[31:28] = message_header_c124_field1_qs; - end - - addr_hit[1247]: begin - reg_rdata_next[31:0] = message_payload_1_c124_qs; - end - - addr_hit[1248]: begin - reg_rdata_next[0] = doorbell_c124_intr_qs; - reg_rdata_next[31:1] = doorbell_c124_preserve_mask_qs; - end - - addr_hit[1249]: begin - reg_rdata_next[0] = completion_interrupt_c124_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c124_preserve_mask_qs; - end - - addr_hit[1250]: begin - reg_rdata_next[31:0] = reserved_1_c125_qs; - end - - addr_hit[1251]: begin - reg_rdata_next[0] = channel_status_c125_channel_free_qs; - reg_rdata_next[1] = channel_status_c125_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c125_field1_qs; - end - - addr_hit[1252]: begin - reg_rdata_next[31:0] = reserved_2_c125_qs; - end - - addr_hit[1253]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1254]: begin - reg_rdata_next[0] = channel_flags_c125_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c125_field1_qs; - end - - addr_hit[1255]: begin - reg_rdata_next[31:0] = length_c125_qs; - end - - addr_hit[1256]: begin - reg_rdata_next[7:0] = message_header_c125_message_id_qs; - reg_rdata_next[9:8] = message_header_c125_message_type_qs; - reg_rdata_next[17:10] = message_header_c125_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c125_token_qs; - reg_rdata_next[31:28] = message_header_c125_field1_qs; - end - - addr_hit[1257]: begin - reg_rdata_next[31:0] = message_payload_1_c125_qs; - end - - addr_hit[1258]: begin - reg_rdata_next[0] = doorbell_c125_intr_qs; - reg_rdata_next[31:1] = doorbell_c125_preserve_mask_qs; - end - - addr_hit[1259]: begin - reg_rdata_next[0] = completion_interrupt_c125_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c125_preserve_mask_qs; - end - - addr_hit[1260]: begin - reg_rdata_next[31:0] = reserved_1_c126_qs; - end - - addr_hit[1261]: begin - reg_rdata_next[0] = channel_status_c126_channel_free_qs; - reg_rdata_next[1] = channel_status_c126_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c126_field1_qs; - end - - addr_hit[1262]: begin - reg_rdata_next[31:0] = reserved_2_c126_qs; - end - - addr_hit[1263]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1264]: begin - reg_rdata_next[0] = channel_flags_c126_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c126_field1_qs; - end - - addr_hit[1265]: begin - reg_rdata_next[31:0] = length_c126_qs; - end - - addr_hit[1266]: begin - reg_rdata_next[7:0] = message_header_c126_message_id_qs; - reg_rdata_next[9:8] = message_header_c126_message_type_qs; - reg_rdata_next[17:10] = message_header_c126_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c126_token_qs; - reg_rdata_next[31:28] = message_header_c126_field1_qs; - end - - addr_hit[1267]: begin - reg_rdata_next[31:0] = message_payload_1_c126_qs; - end - - addr_hit[1268]: begin - reg_rdata_next[0] = doorbell_c126_intr_qs; - reg_rdata_next[31:1] = doorbell_c126_preserve_mask_qs; - end - - addr_hit[1269]: begin - reg_rdata_next[0] = completion_interrupt_c126_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c126_preserve_mask_qs; - end - - addr_hit[1270]: begin - reg_rdata_next[31:0] = reserved_1_c127_qs; - end - - addr_hit[1271]: begin - reg_rdata_next[0] = channel_status_c127_channel_free_qs; - reg_rdata_next[1] = channel_status_c127_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c127_field1_qs; - end - - addr_hit[1272]: begin - reg_rdata_next[31:0] = reserved_2_c127_qs; - end - - addr_hit[1273]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1274]: begin - reg_rdata_next[0] = channel_flags_c127_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c127_field1_qs; - end - - addr_hit[1275]: begin - reg_rdata_next[31:0] = length_c127_qs; - end - - addr_hit[1276]: begin - reg_rdata_next[7:0] = message_header_c127_message_id_qs; - reg_rdata_next[9:8] = message_header_c127_message_type_qs; - reg_rdata_next[17:10] = message_header_c127_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c127_token_qs; - reg_rdata_next[31:28] = message_header_c127_field1_qs; - end - - addr_hit[1277]: begin - reg_rdata_next[31:0] = message_payload_1_c127_qs; - end - - addr_hit[1278]: begin - reg_rdata_next[0] = doorbell_c127_intr_qs; - reg_rdata_next[31:1] = doorbell_c127_preserve_mask_qs; - end - - addr_hit[1279]: begin - reg_rdata_next[0] = completion_interrupt_c127_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c127_preserve_mask_qs; - end - - addr_hit[1280]: begin - reg_rdata_next[31:0] = reserved_1_c128_qs; - end - - addr_hit[1281]: begin - reg_rdata_next[0] = channel_status_c128_channel_free_qs; - reg_rdata_next[1] = channel_status_c128_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c128_field1_qs; - end - - addr_hit[1282]: begin - reg_rdata_next[31:0] = reserved_2_c128_qs; - end - - addr_hit[1283]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1284]: begin - reg_rdata_next[0] = channel_flags_c128_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c128_field1_qs; - end - - addr_hit[1285]: begin - reg_rdata_next[31:0] = length_c128_qs; - end - - addr_hit[1286]: begin - reg_rdata_next[7:0] = message_header_c128_message_id_qs; - reg_rdata_next[9:8] = message_header_c128_message_type_qs; - reg_rdata_next[17:10] = message_header_c128_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c128_token_qs; - reg_rdata_next[31:28] = message_header_c128_field1_qs; - end - - addr_hit[1287]: begin - reg_rdata_next[31:0] = message_payload_1_c128_qs; - end - - addr_hit[1288]: begin - reg_rdata_next[0] = doorbell_c128_intr_qs; - reg_rdata_next[31:1] = doorbell_c128_preserve_mask_qs; - end - - addr_hit[1289]: begin - reg_rdata_next[0] = completion_interrupt_c128_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c128_preserve_mask_qs; - end - - addr_hit[1290]: begin - reg_rdata_next[31:0] = reserved_1_c129_qs; - end - - addr_hit[1291]: begin - reg_rdata_next[0] = channel_status_c129_channel_free_qs; - reg_rdata_next[1] = channel_status_c129_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c129_field1_qs; - end - - addr_hit[1292]: begin - reg_rdata_next[31:0] = reserved_2_c129_qs; - end - - addr_hit[1293]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1294]: begin - reg_rdata_next[0] = channel_flags_c129_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c129_field1_qs; - end - - addr_hit[1295]: begin - reg_rdata_next[31:0] = length_c129_qs; - end - - addr_hit[1296]: begin - reg_rdata_next[7:0] = message_header_c129_message_id_qs; - reg_rdata_next[9:8] = message_header_c129_message_type_qs; - reg_rdata_next[17:10] = message_header_c129_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c129_token_qs; - reg_rdata_next[31:28] = message_header_c129_field1_qs; - end - - addr_hit[1297]: begin - reg_rdata_next[31:0] = message_payload_1_c129_qs; - end - - addr_hit[1298]: begin - reg_rdata_next[0] = doorbell_c129_intr_qs; - reg_rdata_next[31:1] = doorbell_c129_preserve_mask_qs; - end - - addr_hit[1299]: begin - reg_rdata_next[0] = completion_interrupt_c129_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c129_preserve_mask_qs; - end - - addr_hit[1300]: begin - reg_rdata_next[31:0] = reserved_1_c130_qs; - end - - addr_hit[1301]: begin - reg_rdata_next[0] = channel_status_c130_channel_free_qs; - reg_rdata_next[1] = channel_status_c130_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c130_field1_qs; - end - - addr_hit[1302]: begin - reg_rdata_next[31:0] = reserved_2_c130_qs; - end - - addr_hit[1303]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1304]: begin - reg_rdata_next[0] = channel_flags_c130_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c130_field1_qs; - end - - addr_hit[1305]: begin - reg_rdata_next[31:0] = length_c130_qs; - end - - addr_hit[1306]: begin - reg_rdata_next[7:0] = message_header_c130_message_id_qs; - reg_rdata_next[9:8] = message_header_c130_message_type_qs; - reg_rdata_next[17:10] = message_header_c130_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c130_token_qs; - reg_rdata_next[31:28] = message_header_c130_field1_qs; - end - - addr_hit[1307]: begin - reg_rdata_next[31:0] = message_payload_1_c130_qs; - end - - addr_hit[1308]: begin - reg_rdata_next[0] = doorbell_c130_intr_qs; - reg_rdata_next[31:1] = doorbell_c130_preserve_mask_qs; - end - - addr_hit[1309]: begin - reg_rdata_next[0] = completion_interrupt_c130_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c130_preserve_mask_qs; - end - - addr_hit[1310]: begin - reg_rdata_next[31:0] = reserved_1_c131_qs; - end - - addr_hit[1311]: begin - reg_rdata_next[0] = channel_status_c131_channel_free_qs; - reg_rdata_next[1] = channel_status_c131_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c131_field1_qs; - end - - addr_hit[1312]: begin - reg_rdata_next[31:0] = reserved_2_c131_qs; - end - - addr_hit[1313]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1314]: begin - reg_rdata_next[0] = channel_flags_c131_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c131_field1_qs; - end - - addr_hit[1315]: begin - reg_rdata_next[31:0] = length_c131_qs; - end - - addr_hit[1316]: begin - reg_rdata_next[7:0] = message_header_c131_message_id_qs; - reg_rdata_next[9:8] = message_header_c131_message_type_qs; - reg_rdata_next[17:10] = message_header_c131_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c131_token_qs; - reg_rdata_next[31:28] = message_header_c131_field1_qs; - end - - addr_hit[1317]: begin - reg_rdata_next[31:0] = message_payload_1_c131_qs; - end - - addr_hit[1318]: begin - reg_rdata_next[0] = doorbell_c131_intr_qs; - reg_rdata_next[31:1] = doorbell_c131_preserve_mask_qs; - end - - addr_hit[1319]: begin - reg_rdata_next[0] = completion_interrupt_c131_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c131_preserve_mask_qs; - end - - addr_hit[1320]: begin - reg_rdata_next[31:0] = reserved_1_c132_qs; - end - - addr_hit[1321]: begin - reg_rdata_next[0] = channel_status_c132_channel_free_qs; - reg_rdata_next[1] = channel_status_c132_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c132_field1_qs; - end - - addr_hit[1322]: begin - reg_rdata_next[31:0] = reserved_2_c132_qs; - end - - addr_hit[1323]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1324]: begin - reg_rdata_next[0] = channel_flags_c132_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c132_field1_qs; - end - - addr_hit[1325]: begin - reg_rdata_next[31:0] = length_c132_qs; - end - - addr_hit[1326]: begin - reg_rdata_next[7:0] = message_header_c132_message_id_qs; - reg_rdata_next[9:8] = message_header_c132_message_type_qs; - reg_rdata_next[17:10] = message_header_c132_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c132_token_qs; - reg_rdata_next[31:28] = message_header_c132_field1_qs; - end - - addr_hit[1327]: begin - reg_rdata_next[31:0] = message_payload_1_c132_qs; - end - - addr_hit[1328]: begin - reg_rdata_next[0] = doorbell_c132_intr_qs; - reg_rdata_next[31:1] = doorbell_c132_preserve_mask_qs; - end - - addr_hit[1329]: begin - reg_rdata_next[0] = completion_interrupt_c132_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c132_preserve_mask_qs; - end - - addr_hit[1330]: begin - reg_rdata_next[31:0] = reserved_1_c133_qs; - end - - addr_hit[1331]: begin - reg_rdata_next[0] = channel_status_c133_channel_free_qs; - reg_rdata_next[1] = channel_status_c133_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c133_field1_qs; - end - - addr_hit[1332]: begin - reg_rdata_next[31:0] = reserved_2_c133_qs; - end - - addr_hit[1333]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1334]: begin - reg_rdata_next[0] = channel_flags_c133_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c133_field1_qs; - end - - addr_hit[1335]: begin - reg_rdata_next[31:0] = length_c133_qs; - end - - addr_hit[1336]: begin - reg_rdata_next[7:0] = message_header_c133_message_id_qs; - reg_rdata_next[9:8] = message_header_c133_message_type_qs; - reg_rdata_next[17:10] = message_header_c133_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c133_token_qs; - reg_rdata_next[31:28] = message_header_c133_field1_qs; - end - - addr_hit[1337]: begin - reg_rdata_next[31:0] = message_payload_1_c133_qs; - end - - addr_hit[1338]: begin - reg_rdata_next[0] = doorbell_c133_intr_qs; - reg_rdata_next[31:1] = doorbell_c133_preserve_mask_qs; - end - - addr_hit[1339]: begin - reg_rdata_next[0] = completion_interrupt_c133_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c133_preserve_mask_qs; - end - - addr_hit[1340]: begin - reg_rdata_next[31:0] = reserved_1_c134_qs; - end - - addr_hit[1341]: begin - reg_rdata_next[0] = channel_status_c134_channel_free_qs; - reg_rdata_next[1] = channel_status_c134_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c134_field1_qs; - end - - addr_hit[1342]: begin - reg_rdata_next[31:0] = reserved_2_c134_qs; - end - - addr_hit[1343]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1344]: begin - reg_rdata_next[0] = channel_flags_c134_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c134_field1_qs; - end - - addr_hit[1345]: begin - reg_rdata_next[31:0] = length_c134_qs; - end - - addr_hit[1346]: begin - reg_rdata_next[7:0] = message_header_c134_message_id_qs; - reg_rdata_next[9:8] = message_header_c134_message_type_qs; - reg_rdata_next[17:10] = message_header_c134_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c134_token_qs; - reg_rdata_next[31:28] = message_header_c134_field1_qs; - end - - addr_hit[1347]: begin - reg_rdata_next[31:0] = message_payload_1_c134_qs; - end - - addr_hit[1348]: begin - reg_rdata_next[0] = doorbell_c134_intr_qs; - reg_rdata_next[31:1] = doorbell_c134_preserve_mask_qs; - end - - addr_hit[1349]: begin - reg_rdata_next[0] = completion_interrupt_c134_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c134_preserve_mask_qs; - end - - addr_hit[1350]: begin - reg_rdata_next[31:0] = reserved_1_c135_qs; - end - - addr_hit[1351]: begin - reg_rdata_next[0] = channel_status_c135_channel_free_qs; - reg_rdata_next[1] = channel_status_c135_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c135_field1_qs; - end - - addr_hit[1352]: begin - reg_rdata_next[31:0] = reserved_2_c135_qs; - end - - addr_hit[1353]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1354]: begin - reg_rdata_next[0] = channel_flags_c135_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c135_field1_qs; - end - - addr_hit[1355]: begin - reg_rdata_next[31:0] = length_c135_qs; - end - - addr_hit[1356]: begin - reg_rdata_next[7:0] = message_header_c135_message_id_qs; - reg_rdata_next[9:8] = message_header_c135_message_type_qs; - reg_rdata_next[17:10] = message_header_c135_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c135_token_qs; - reg_rdata_next[31:28] = message_header_c135_field1_qs; - end - - addr_hit[1357]: begin - reg_rdata_next[31:0] = message_payload_1_c135_qs; - end - - addr_hit[1358]: begin - reg_rdata_next[0] = doorbell_c135_intr_qs; - reg_rdata_next[31:1] = doorbell_c135_preserve_mask_qs; - end - - addr_hit[1359]: begin - reg_rdata_next[0] = completion_interrupt_c135_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c135_preserve_mask_qs; - end - - addr_hit[1360]: begin - reg_rdata_next[31:0] = reserved_1_c136_qs; - end - - addr_hit[1361]: begin - reg_rdata_next[0] = channel_status_c136_channel_free_qs; - reg_rdata_next[1] = channel_status_c136_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c136_field1_qs; - end - - addr_hit[1362]: begin - reg_rdata_next[31:0] = reserved_2_c136_qs; - end - - addr_hit[1363]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1364]: begin - reg_rdata_next[0] = channel_flags_c136_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c136_field1_qs; - end - - addr_hit[1365]: begin - reg_rdata_next[31:0] = length_c136_qs; - end - - addr_hit[1366]: begin - reg_rdata_next[7:0] = message_header_c136_message_id_qs; - reg_rdata_next[9:8] = message_header_c136_message_type_qs; - reg_rdata_next[17:10] = message_header_c136_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c136_token_qs; - reg_rdata_next[31:28] = message_header_c136_field1_qs; - end - - addr_hit[1367]: begin - reg_rdata_next[31:0] = message_payload_1_c136_qs; - end - - addr_hit[1368]: begin - reg_rdata_next[0] = doorbell_c136_intr_qs; - reg_rdata_next[31:1] = doorbell_c136_preserve_mask_qs; - end - - addr_hit[1369]: begin - reg_rdata_next[0] = completion_interrupt_c136_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c136_preserve_mask_qs; - end - - addr_hit[1370]: begin - reg_rdata_next[31:0] = reserved_1_c137_qs; - end - - addr_hit[1371]: begin - reg_rdata_next[0] = channel_status_c137_channel_free_qs; - reg_rdata_next[1] = channel_status_c137_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c137_field1_qs; - end - - addr_hit[1372]: begin - reg_rdata_next[31:0] = reserved_2_c137_qs; - end - - addr_hit[1373]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1374]: begin - reg_rdata_next[0] = channel_flags_c137_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c137_field1_qs; - end - - addr_hit[1375]: begin - reg_rdata_next[31:0] = length_c137_qs; - end - - addr_hit[1376]: begin - reg_rdata_next[7:0] = message_header_c137_message_id_qs; - reg_rdata_next[9:8] = message_header_c137_message_type_qs; - reg_rdata_next[17:10] = message_header_c137_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c137_token_qs; - reg_rdata_next[31:28] = message_header_c137_field1_qs; - end - - addr_hit[1377]: begin - reg_rdata_next[31:0] = message_payload_1_c137_qs; - end - - addr_hit[1378]: begin - reg_rdata_next[0] = doorbell_c137_intr_qs; - reg_rdata_next[31:1] = doorbell_c137_preserve_mask_qs; - end - - addr_hit[1379]: begin - reg_rdata_next[0] = completion_interrupt_c137_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c137_preserve_mask_qs; - end - - addr_hit[1380]: begin - reg_rdata_next[31:0] = reserved_1_c138_qs; - end - - addr_hit[1381]: begin - reg_rdata_next[0] = channel_status_c138_channel_free_qs; - reg_rdata_next[1] = channel_status_c138_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c138_field1_qs; - end - - addr_hit[1382]: begin - reg_rdata_next[31:0] = reserved_2_c138_qs; - end - - addr_hit[1383]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1384]: begin - reg_rdata_next[0] = channel_flags_c138_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c138_field1_qs; - end - - addr_hit[1385]: begin - reg_rdata_next[31:0] = length_c138_qs; - end - - addr_hit[1386]: begin - reg_rdata_next[7:0] = message_header_c138_message_id_qs; - reg_rdata_next[9:8] = message_header_c138_message_type_qs; - reg_rdata_next[17:10] = message_header_c138_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c138_token_qs; - reg_rdata_next[31:28] = message_header_c138_field1_qs; - end - - addr_hit[1387]: begin - reg_rdata_next[31:0] = message_payload_1_c138_qs; - end - - addr_hit[1388]: begin - reg_rdata_next[0] = doorbell_c138_intr_qs; - reg_rdata_next[31:1] = doorbell_c138_preserve_mask_qs; - end - - addr_hit[1389]: begin - reg_rdata_next[0] = completion_interrupt_c138_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c138_preserve_mask_qs; - end - - addr_hit[1390]: begin - reg_rdata_next[31:0] = reserved_1_c139_qs; - end - - addr_hit[1391]: begin - reg_rdata_next[0] = channel_status_c139_channel_free_qs; - reg_rdata_next[1] = channel_status_c139_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c139_field1_qs; - end - - addr_hit[1392]: begin - reg_rdata_next[31:0] = reserved_2_c139_qs; - end - - addr_hit[1393]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1394]: begin - reg_rdata_next[0] = channel_flags_c139_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c139_field1_qs; - end - - addr_hit[1395]: begin - reg_rdata_next[31:0] = length_c139_qs; - end - - addr_hit[1396]: begin - reg_rdata_next[7:0] = message_header_c139_message_id_qs; - reg_rdata_next[9:8] = message_header_c139_message_type_qs; - reg_rdata_next[17:10] = message_header_c139_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c139_token_qs; - reg_rdata_next[31:28] = message_header_c139_field1_qs; - end - - addr_hit[1397]: begin - reg_rdata_next[31:0] = message_payload_1_c139_qs; - end - - addr_hit[1398]: begin - reg_rdata_next[0] = doorbell_c139_intr_qs; - reg_rdata_next[31:1] = doorbell_c139_preserve_mask_qs; - end - - addr_hit[1399]: begin - reg_rdata_next[0] = completion_interrupt_c139_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c139_preserve_mask_qs; - end - - addr_hit[1400]: begin - reg_rdata_next[31:0] = reserved_1_c140_qs; - end - - addr_hit[1401]: begin - reg_rdata_next[0] = channel_status_c140_channel_free_qs; - reg_rdata_next[1] = channel_status_c140_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c140_field1_qs; - end - - addr_hit[1402]: begin - reg_rdata_next[31:0] = reserved_2_c140_qs; - end - - addr_hit[1403]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1404]: begin - reg_rdata_next[0] = channel_flags_c140_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c140_field1_qs; - end - - addr_hit[1405]: begin - reg_rdata_next[31:0] = length_c140_qs; - end - - addr_hit[1406]: begin - reg_rdata_next[7:0] = message_header_c140_message_id_qs; - reg_rdata_next[9:8] = message_header_c140_message_type_qs; - reg_rdata_next[17:10] = message_header_c140_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c140_token_qs; - reg_rdata_next[31:28] = message_header_c140_field1_qs; - end - - addr_hit[1407]: begin - reg_rdata_next[31:0] = message_payload_1_c140_qs; - end - - addr_hit[1408]: begin - reg_rdata_next[0] = doorbell_c140_intr_qs; - reg_rdata_next[31:1] = doorbell_c140_preserve_mask_qs; - end - - addr_hit[1409]: begin - reg_rdata_next[0] = completion_interrupt_c140_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c140_preserve_mask_qs; - end - - addr_hit[1410]: begin - reg_rdata_next[31:0] = reserved_1_c141_qs; - end - - addr_hit[1411]: begin - reg_rdata_next[0] = channel_status_c141_channel_free_qs; - reg_rdata_next[1] = channel_status_c141_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c141_field1_qs; - end - - addr_hit[1412]: begin - reg_rdata_next[31:0] = reserved_2_c141_qs; - end - - addr_hit[1413]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1414]: begin - reg_rdata_next[0] = channel_flags_c141_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c141_field1_qs; - end - - addr_hit[1415]: begin - reg_rdata_next[31:0] = length_c141_qs; - end - - addr_hit[1416]: begin - reg_rdata_next[7:0] = message_header_c141_message_id_qs; - reg_rdata_next[9:8] = message_header_c141_message_type_qs; - reg_rdata_next[17:10] = message_header_c141_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c141_token_qs; - reg_rdata_next[31:28] = message_header_c141_field1_qs; - end - - addr_hit[1417]: begin - reg_rdata_next[31:0] = message_payload_1_c141_qs; - end - - addr_hit[1418]: begin - reg_rdata_next[0] = doorbell_c141_intr_qs; - reg_rdata_next[31:1] = doorbell_c141_preserve_mask_qs; - end - - addr_hit[1419]: begin - reg_rdata_next[0] = completion_interrupt_c141_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c141_preserve_mask_qs; - end - - addr_hit[1420]: begin - reg_rdata_next[31:0] = reserved_1_c142_qs; - end - - addr_hit[1421]: begin - reg_rdata_next[0] = channel_status_c142_channel_free_qs; - reg_rdata_next[1] = channel_status_c142_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c142_field1_qs; - end - - addr_hit[1422]: begin - reg_rdata_next[31:0] = reserved_2_c142_qs; - end - - addr_hit[1423]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1424]: begin - reg_rdata_next[0] = channel_flags_c142_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c142_field1_qs; - end - - addr_hit[1425]: begin - reg_rdata_next[31:0] = length_c142_qs; - end - - addr_hit[1426]: begin - reg_rdata_next[7:0] = message_header_c142_message_id_qs; - reg_rdata_next[9:8] = message_header_c142_message_type_qs; - reg_rdata_next[17:10] = message_header_c142_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c142_token_qs; - reg_rdata_next[31:28] = message_header_c142_field1_qs; - end - - addr_hit[1427]: begin - reg_rdata_next[31:0] = message_payload_1_c142_qs; - end - - addr_hit[1428]: begin - reg_rdata_next[0] = doorbell_c142_intr_qs; - reg_rdata_next[31:1] = doorbell_c142_preserve_mask_qs; - end - - addr_hit[1429]: begin - reg_rdata_next[0] = completion_interrupt_c142_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c142_preserve_mask_qs; - end - - addr_hit[1430]: begin - reg_rdata_next[31:0] = reserved_1_c143_qs; - end - - addr_hit[1431]: begin - reg_rdata_next[0] = channel_status_c143_channel_free_qs; - reg_rdata_next[1] = channel_status_c143_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c143_field1_qs; - end - - addr_hit[1432]: begin - reg_rdata_next[31:0] = reserved_2_c143_qs; - end - - addr_hit[1433]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1434]: begin - reg_rdata_next[0] = channel_flags_c143_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c143_field1_qs; - end - - addr_hit[1435]: begin - reg_rdata_next[31:0] = length_c143_qs; - end - - addr_hit[1436]: begin - reg_rdata_next[7:0] = message_header_c143_message_id_qs; - reg_rdata_next[9:8] = message_header_c143_message_type_qs; - reg_rdata_next[17:10] = message_header_c143_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c143_token_qs; - reg_rdata_next[31:28] = message_header_c143_field1_qs; - end - - addr_hit[1437]: begin - reg_rdata_next[31:0] = message_payload_1_c143_qs; - end - - addr_hit[1438]: begin - reg_rdata_next[0] = doorbell_c143_intr_qs; - reg_rdata_next[31:1] = doorbell_c143_preserve_mask_qs; - end - - addr_hit[1439]: begin - reg_rdata_next[0] = completion_interrupt_c143_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c143_preserve_mask_qs; - end - - addr_hit[1440]: begin - reg_rdata_next[31:0] = reserved_1_c144_qs; - end - - addr_hit[1441]: begin - reg_rdata_next[0] = channel_status_c144_channel_free_qs; - reg_rdata_next[1] = channel_status_c144_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c144_field1_qs; - end - - addr_hit[1442]: begin - reg_rdata_next[31:0] = reserved_2_c144_qs; - end - - addr_hit[1443]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1444]: begin - reg_rdata_next[0] = channel_flags_c144_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c144_field1_qs; - end - - addr_hit[1445]: begin - reg_rdata_next[31:0] = length_c144_qs; - end - - addr_hit[1446]: begin - reg_rdata_next[7:0] = message_header_c144_message_id_qs; - reg_rdata_next[9:8] = message_header_c144_message_type_qs; - reg_rdata_next[17:10] = message_header_c144_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c144_token_qs; - reg_rdata_next[31:28] = message_header_c144_field1_qs; - end - - addr_hit[1447]: begin - reg_rdata_next[31:0] = message_payload_1_c144_qs; - end - - addr_hit[1448]: begin - reg_rdata_next[0] = doorbell_c144_intr_qs; - reg_rdata_next[31:1] = doorbell_c144_preserve_mask_qs; - end - - addr_hit[1449]: begin - reg_rdata_next[0] = completion_interrupt_c144_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c144_preserve_mask_qs; - end - - addr_hit[1450]: begin - reg_rdata_next[31:0] = reserved_1_c145_qs; - end - - addr_hit[1451]: begin - reg_rdata_next[0] = channel_status_c145_channel_free_qs; - reg_rdata_next[1] = channel_status_c145_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c145_field1_qs; - end - - addr_hit[1452]: begin - reg_rdata_next[31:0] = reserved_2_c145_qs; - end - - addr_hit[1453]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1454]: begin - reg_rdata_next[0] = channel_flags_c145_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c145_field1_qs; - end - - addr_hit[1455]: begin - reg_rdata_next[31:0] = length_c145_qs; - end - - addr_hit[1456]: begin - reg_rdata_next[7:0] = message_header_c145_message_id_qs; - reg_rdata_next[9:8] = message_header_c145_message_type_qs; - reg_rdata_next[17:10] = message_header_c145_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c145_token_qs; - reg_rdata_next[31:28] = message_header_c145_field1_qs; - end - - addr_hit[1457]: begin - reg_rdata_next[31:0] = message_payload_1_c145_qs; - end - - addr_hit[1458]: begin - reg_rdata_next[0] = doorbell_c145_intr_qs; - reg_rdata_next[31:1] = doorbell_c145_preserve_mask_qs; - end - - addr_hit[1459]: begin - reg_rdata_next[0] = completion_interrupt_c145_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c145_preserve_mask_qs; - end - - addr_hit[1460]: begin - reg_rdata_next[31:0] = reserved_1_c146_qs; - end - - addr_hit[1461]: begin - reg_rdata_next[0] = channel_status_c146_channel_free_qs; - reg_rdata_next[1] = channel_status_c146_channel_error_qs; - reg_rdata_next[31:2] = channel_status_c146_field1_qs; - end - - addr_hit[1462]: begin - reg_rdata_next[31:0] = reserved_2_c146_qs; - end - - addr_hit[1463]: begin - reg_rdata_next[31:0] = '0; - end - - addr_hit[1464]: begin - reg_rdata_next[0] = channel_flags_c146_intr_enable_qs; - reg_rdata_next[31:1] = channel_flags_c146_field1_qs; - end - - addr_hit[1465]: begin - reg_rdata_next[31:0] = length_c146_qs; - end - - addr_hit[1466]: begin - reg_rdata_next[7:0] = message_header_c146_message_id_qs; - reg_rdata_next[9:8] = message_header_c146_message_type_qs; - reg_rdata_next[17:10] = message_header_c146_protocol_id_qs; - reg_rdata_next[27:18] = message_header_c146_token_qs; - reg_rdata_next[31:28] = message_header_c146_field1_qs; - end - - addr_hit[1467]: begin - reg_rdata_next[31:0] = message_payload_1_c146_qs; - end - - addr_hit[1468]: begin - reg_rdata_next[0] = doorbell_c146_intr_qs; - reg_rdata_next[31:1] = doorbell_c146_preserve_mask_qs; - end - - addr_hit[1469]: begin - reg_rdata_next[0] = completion_interrupt_c146_intr_qs; - reg_rdata_next[31:1] = completion_interrupt_c146_preserve_mask_qs; + addr_hit[41]: begin + reg_rdata_next[31:0] = completion_interrupt_c0_qs; end default: begin diff --git a/hw/ips/axi_scmi_mailbox/scmi.h b/hw/ips/axi_scmi_mailbox/scmi.h index caa69d6..28b4e63 100644 --- a/hw/ips/axi_scmi_mailbox/scmi.h +++ b/hw/ips/axi_scmi_mailbox/scmi.h @@ -70,4623 +70,142 @@ extern "C" { // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET 0x1c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C0_REG_OFFSET 0x20 -#define SCMI_DOORBELL_C0_INTR_BIT 0 -#define SCMI_DOORBELL_C0_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C0_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C0_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C0_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C0_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C0_REG_OFFSET 0x24 -#define SCMI_COMPLETION_INTERRUPT_C0_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C1_REG_OFFSET 0x28 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C1_REG_OFFSET 0x2c -#define SCMI_CHANNEL_STATUS_C1_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C1_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C1_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C1_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C1_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C1_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C1_REG_OFFSET 0x30 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C1_REG_OFFSET 0x34 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C1_REG_OFFSET 0x38 -#define SCMI_CHANNEL_FLAGS_C1_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C1_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C1_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C1_REG_OFFSET 0x3c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C1_REG_OFFSET 0x40 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C1_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C1_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C1_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C1_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C1_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C1_REG_OFFSET 0x44 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C1_REG_OFFSET 0x48 -#define SCMI_DOORBELL_C1_INTR_BIT 0 -#define SCMI_DOORBELL_C1_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C1_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C1_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C1_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C1_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C1_REG_OFFSET 0x4c -#define SCMI_COMPLETION_INTERRUPT_C1_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C2_REG_OFFSET 0x50 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C2_REG_OFFSET 0x54 -#define SCMI_CHANNEL_STATUS_C2_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C2_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C2_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C2_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C2_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C2_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C2_REG_OFFSET 0x58 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C2_REG_OFFSET 0x5c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C2_REG_OFFSET 0x60 -#define SCMI_CHANNEL_FLAGS_C2_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C2_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C2_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C2_REG_OFFSET 0x64 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C2_REG_OFFSET 0x68 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C2_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C2_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C2_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C2_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C2_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C2_REG_OFFSET 0x6c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C2_REG_OFFSET 0x70 -#define SCMI_DOORBELL_C2_INTR_BIT 0 -#define SCMI_DOORBELL_C2_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C2_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C2_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C2_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C2_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C2_REG_OFFSET 0x74 -#define SCMI_COMPLETION_INTERRUPT_C2_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C3_REG_OFFSET 0x78 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C3_REG_OFFSET 0x7c -#define SCMI_CHANNEL_STATUS_C3_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C3_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C3_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C3_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C3_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C3_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C3_REG_OFFSET 0x80 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C3_REG_OFFSET 0x84 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C3_REG_OFFSET 0x88 -#define SCMI_CHANNEL_FLAGS_C3_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C3_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C3_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C3_REG_OFFSET 0x8c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C3_REG_OFFSET 0x90 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C3_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C3_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C3_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C3_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C3_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C3_REG_OFFSET 0x94 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C3_REG_OFFSET 0x98 -#define SCMI_DOORBELL_C3_INTR_BIT 0 -#define SCMI_DOORBELL_C3_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C3_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C3_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C3_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C3_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C3_REG_OFFSET 0x9c -#define SCMI_COMPLETION_INTERRUPT_C3_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C4_REG_OFFSET 0xa0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C4_REG_OFFSET 0xa4 -#define SCMI_CHANNEL_STATUS_C4_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C4_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C4_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C4_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C4_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C4_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C4_REG_OFFSET 0xa8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C4_REG_OFFSET 0xac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C4_REG_OFFSET 0xb0 -#define SCMI_CHANNEL_FLAGS_C4_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C4_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C4_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C4_REG_OFFSET 0xb4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C4_REG_OFFSET 0xb8 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C4_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C4_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C4_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C4_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C4_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C4_REG_OFFSET 0xbc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C4_REG_OFFSET 0xc0 -#define SCMI_DOORBELL_C4_INTR_BIT 0 -#define SCMI_DOORBELL_C4_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C4_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C4_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C4_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C4_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C4_REG_OFFSET 0xc4 -#define SCMI_COMPLETION_INTERRUPT_C4_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C5_REG_OFFSET 0xc8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C5_REG_OFFSET 0xcc -#define SCMI_CHANNEL_STATUS_C5_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C5_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C5_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C5_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C5_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C5_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C5_REG_OFFSET 0xd0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C5_REG_OFFSET 0xd4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C5_REG_OFFSET 0xd8 -#define SCMI_CHANNEL_FLAGS_C5_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C5_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C5_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C5_REG_OFFSET 0xdc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C5_REG_OFFSET 0xe0 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C5_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C5_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C5_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C5_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C5_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C5_REG_OFFSET 0xe4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C5_REG_OFFSET 0xe8 -#define SCMI_DOORBELL_C5_INTR_BIT 0 -#define SCMI_DOORBELL_C5_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C5_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C5_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C5_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C5_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C5_REG_OFFSET 0xec -#define SCMI_COMPLETION_INTERRUPT_C5_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C6_REG_OFFSET 0xf0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C6_REG_OFFSET 0xf4 -#define SCMI_CHANNEL_STATUS_C6_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C6_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C6_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C6_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C6_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C6_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C6_REG_OFFSET 0xf8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C6_REG_OFFSET 0xfc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C6_REG_OFFSET 0x100 -#define SCMI_CHANNEL_FLAGS_C6_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C6_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C6_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C6_REG_OFFSET 0x104 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C6_REG_OFFSET 0x108 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C6_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C6_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C6_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C6_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C6_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C6_REG_OFFSET 0x10c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C6_REG_OFFSET 0x110 -#define SCMI_DOORBELL_C6_INTR_BIT 0 -#define SCMI_DOORBELL_C6_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C6_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C6_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C6_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C6_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C6_REG_OFFSET 0x114 -#define SCMI_COMPLETION_INTERRUPT_C6_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C7_REG_OFFSET 0x118 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C7_REG_OFFSET 0x11c -#define SCMI_CHANNEL_STATUS_C7_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C7_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C7_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C7_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C7_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C7_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C7_REG_OFFSET 0x120 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C7_REG_OFFSET 0x124 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C7_REG_OFFSET 0x128 -#define SCMI_CHANNEL_FLAGS_C7_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C7_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C7_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C7_REG_OFFSET 0x12c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C7_REG_OFFSET 0x130 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C7_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C7_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C7_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C7_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C7_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C7_REG_OFFSET 0x134 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C7_REG_OFFSET 0x138 -#define SCMI_DOORBELL_C7_INTR_BIT 0 -#define SCMI_DOORBELL_C7_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C7_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C7_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C7_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C7_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C7_REG_OFFSET 0x13c -#define SCMI_COMPLETION_INTERRUPT_C7_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C8_REG_OFFSET 0x140 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C8_REG_OFFSET 0x144 -#define SCMI_CHANNEL_STATUS_C8_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C8_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C8_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C8_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C8_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C8_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C8_REG_OFFSET 0x148 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C8_REG_OFFSET 0x14c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C8_REG_OFFSET 0x150 -#define SCMI_CHANNEL_FLAGS_C8_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C8_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C8_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C8_REG_OFFSET 0x154 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C8_REG_OFFSET 0x158 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C8_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C8_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C8_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C8_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C8_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C8_REG_OFFSET 0x15c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C8_REG_OFFSET 0x160 -#define SCMI_DOORBELL_C8_INTR_BIT 0 -#define SCMI_DOORBELL_C8_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C8_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C8_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C8_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C8_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C8_REG_OFFSET 0x164 -#define SCMI_COMPLETION_INTERRUPT_C8_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C9_REG_OFFSET 0x168 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C9_REG_OFFSET 0x16c -#define SCMI_CHANNEL_STATUS_C9_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C9_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C9_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C9_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C9_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C9_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C9_REG_OFFSET 0x170 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C9_REG_OFFSET 0x174 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C9_REG_OFFSET 0x178 -#define SCMI_CHANNEL_FLAGS_C9_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C9_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C9_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C9_REG_OFFSET 0x17c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C9_REG_OFFSET 0x180 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C9_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C9_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C9_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C9_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C9_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C9_REG_OFFSET 0x184 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C9_REG_OFFSET 0x188 -#define SCMI_DOORBELL_C9_INTR_BIT 0 -#define SCMI_DOORBELL_C9_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C9_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C9_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C9_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C9_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C9_REG_OFFSET 0x18c -#define SCMI_COMPLETION_INTERRUPT_C9_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C10_REG_OFFSET 0x190 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C10_REG_OFFSET 0x194 -#define SCMI_CHANNEL_STATUS_C10_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C10_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C10_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C10_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C10_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C10_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C10_REG_OFFSET 0x198 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C10_REG_OFFSET 0x19c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C10_REG_OFFSET 0x1a0 -#define SCMI_CHANNEL_FLAGS_C10_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C10_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C10_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C10_REG_OFFSET 0x1a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C10_REG_OFFSET 0x1a8 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C10_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C10_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C10_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C10_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C10_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C10_REG_OFFSET 0x1ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C10_REG_OFFSET 0x1b0 -#define SCMI_DOORBELL_C10_INTR_BIT 0 -#define SCMI_DOORBELL_C10_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C10_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C10_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C10_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C10_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C10_REG_OFFSET 0x1b4 -#define SCMI_COMPLETION_INTERRUPT_C10_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C11_REG_OFFSET 0x1b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C11_REG_OFFSET 0x1bc -#define SCMI_CHANNEL_STATUS_C11_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C11_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C11_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C11_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C11_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C11_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C11_REG_OFFSET 0x1c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C11_REG_OFFSET 0x1c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C11_REG_OFFSET 0x1c8 -#define SCMI_CHANNEL_FLAGS_C11_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C11_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C11_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C11_REG_OFFSET 0x1cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C11_REG_OFFSET 0x1d0 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C11_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C11_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C11_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C11_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C11_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C11_REG_OFFSET 0x1d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C11_REG_OFFSET 0x1d8 -#define SCMI_DOORBELL_C11_INTR_BIT 0 -#define SCMI_DOORBELL_C11_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C11_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C11_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C11_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C11_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C11_REG_OFFSET 0x1dc -#define SCMI_COMPLETION_INTERRUPT_C11_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C12_REG_OFFSET 0x1e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C12_REG_OFFSET 0x1e4 -#define SCMI_CHANNEL_STATUS_C12_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C12_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C12_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C12_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C12_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C12_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C12_REG_OFFSET 0x1e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C12_REG_OFFSET 0x1ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C12_REG_OFFSET 0x1f0 -#define SCMI_CHANNEL_FLAGS_C12_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C12_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C12_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C12_REG_OFFSET 0x1f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C12_REG_OFFSET 0x1f8 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C12_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C12_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C12_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C12_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C12_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C12_REG_OFFSET 0x1fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C12_REG_OFFSET 0x200 -#define SCMI_DOORBELL_C12_INTR_BIT 0 -#define SCMI_DOORBELL_C12_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C12_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C12_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C12_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C12_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C12_REG_OFFSET 0x204 -#define SCMI_COMPLETION_INTERRUPT_C12_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C13_REG_OFFSET 0x208 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C13_REG_OFFSET 0x20c -#define SCMI_CHANNEL_STATUS_C13_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C13_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C13_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C13_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C13_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C13_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C13_REG_OFFSET 0x210 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C13_REG_OFFSET 0x214 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C13_REG_OFFSET 0x218 -#define SCMI_CHANNEL_FLAGS_C13_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C13_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C13_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C13_REG_OFFSET 0x21c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C13_REG_OFFSET 0x220 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C13_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C13_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C13_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C13_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C13_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C13_REG_OFFSET 0x224 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C13_REG_OFFSET 0x228 -#define SCMI_DOORBELL_C13_INTR_BIT 0 -#define SCMI_DOORBELL_C13_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C13_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C13_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C13_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C13_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C13_REG_OFFSET 0x22c -#define SCMI_COMPLETION_INTERRUPT_C13_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C14_REG_OFFSET 0x230 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C14_REG_OFFSET 0x234 -#define SCMI_CHANNEL_STATUS_C14_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C14_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C14_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C14_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C14_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C14_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C14_REG_OFFSET 0x238 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C14_REG_OFFSET 0x23c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C14_REG_OFFSET 0x240 -#define SCMI_CHANNEL_FLAGS_C14_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C14_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C14_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C14_REG_OFFSET 0x244 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C14_REG_OFFSET 0x248 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C14_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C14_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C14_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C14_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C14_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C14_REG_OFFSET 0x24c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C14_REG_OFFSET 0x250 -#define SCMI_DOORBELL_C14_INTR_BIT 0 -#define SCMI_DOORBELL_C14_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C14_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C14_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C14_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C14_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C14_REG_OFFSET 0x254 -#define SCMI_COMPLETION_INTERRUPT_C14_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C15_REG_OFFSET 0x258 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C15_REG_OFFSET 0x25c -#define SCMI_CHANNEL_STATUS_C15_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C15_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C15_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C15_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C15_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C15_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C15_REG_OFFSET 0x260 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C15_REG_OFFSET 0x264 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C15_REG_OFFSET 0x268 -#define SCMI_CHANNEL_FLAGS_C15_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C15_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C15_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C15_REG_OFFSET 0x26c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C15_REG_OFFSET 0x270 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C15_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C15_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C15_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C15_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C15_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C15_REG_OFFSET 0x274 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C15_REG_OFFSET 0x278 -#define SCMI_DOORBELL_C15_INTR_BIT 0 -#define SCMI_DOORBELL_C15_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C15_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C15_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C15_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C15_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C15_REG_OFFSET 0x27c -#define SCMI_COMPLETION_INTERRUPT_C15_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C16_REG_OFFSET 0x280 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C16_REG_OFFSET 0x284 -#define SCMI_CHANNEL_STATUS_C16_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C16_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C16_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C16_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C16_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C16_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C16_REG_OFFSET 0x288 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C16_REG_OFFSET 0x28c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C16_REG_OFFSET 0x290 -#define SCMI_CHANNEL_FLAGS_C16_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C16_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C16_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C16_REG_OFFSET 0x294 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C16_REG_OFFSET 0x298 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C16_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C16_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C16_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C16_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C16_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C16_REG_OFFSET 0x29c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C16_REG_OFFSET 0x2a0 -#define SCMI_DOORBELL_C16_INTR_BIT 0 -#define SCMI_DOORBELL_C16_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C16_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C16_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C16_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C16_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C16_REG_OFFSET 0x2a4 -#define SCMI_COMPLETION_INTERRUPT_C16_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C17_REG_OFFSET 0x2a8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C17_REG_OFFSET 0x2ac -#define SCMI_CHANNEL_STATUS_C17_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C17_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C17_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C17_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C17_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C17_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C17_REG_OFFSET 0x2b0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C17_REG_OFFSET 0x2b4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C17_REG_OFFSET 0x2b8 -#define SCMI_CHANNEL_FLAGS_C17_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C17_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C17_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C17_REG_OFFSET 0x2bc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C17_REG_OFFSET 0x2c0 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C17_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C17_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C17_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C17_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C17_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C17_REG_OFFSET 0x2c4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C17_REG_OFFSET 0x2c8 -#define SCMI_DOORBELL_C17_INTR_BIT 0 -#define SCMI_DOORBELL_C17_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C17_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C17_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C17_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C17_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C17_REG_OFFSET 0x2cc -#define SCMI_COMPLETION_INTERRUPT_C17_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C18_REG_OFFSET 0x2d0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C18_REG_OFFSET 0x2d4 -#define SCMI_CHANNEL_STATUS_C18_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C18_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C18_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C18_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C18_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C18_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C18_REG_OFFSET 0x2d8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C18_REG_OFFSET 0x2dc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C18_REG_OFFSET 0x2e0 -#define SCMI_CHANNEL_FLAGS_C18_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C18_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C18_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C18_REG_OFFSET 0x2e4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C18_REG_OFFSET 0x2e8 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C18_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C18_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C18_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C18_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C18_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C18_REG_OFFSET 0x2ec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C18_REG_OFFSET 0x2f0 -#define SCMI_DOORBELL_C18_INTR_BIT 0 -#define SCMI_DOORBELL_C18_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C18_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C18_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C18_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C18_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C18_REG_OFFSET 0x2f4 -#define SCMI_COMPLETION_INTERRUPT_C18_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C19_REG_OFFSET 0x2f8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C19_REG_OFFSET 0x2fc -#define SCMI_CHANNEL_STATUS_C19_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C19_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C19_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C19_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C19_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C19_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C19_REG_OFFSET 0x300 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C19_REG_OFFSET 0x304 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C19_REG_OFFSET 0x308 -#define SCMI_CHANNEL_FLAGS_C19_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C19_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C19_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C19_REG_OFFSET 0x30c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C19_REG_OFFSET 0x310 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C19_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C19_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C19_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C19_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C19_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C19_REG_OFFSET 0x314 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C19_REG_OFFSET 0x318 -#define SCMI_DOORBELL_C19_INTR_BIT 0 -#define SCMI_DOORBELL_C19_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C19_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C19_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C19_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C19_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C19_REG_OFFSET 0x31c -#define SCMI_COMPLETION_INTERRUPT_C19_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C20_REG_OFFSET 0x320 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C20_REG_OFFSET 0x324 -#define SCMI_CHANNEL_STATUS_C20_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C20_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C20_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C20_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C20_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C20_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C20_REG_OFFSET 0x328 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C20_REG_OFFSET 0x32c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C20_REG_OFFSET 0x330 -#define SCMI_CHANNEL_FLAGS_C20_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C20_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C20_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C20_REG_OFFSET 0x334 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C20_REG_OFFSET 0x338 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C20_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C20_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C20_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C20_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C20_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C20_REG_OFFSET 0x33c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C20_REG_OFFSET 0x340 -#define SCMI_DOORBELL_C20_INTR_BIT 0 -#define SCMI_DOORBELL_C20_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C20_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C20_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C20_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C20_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C20_REG_OFFSET 0x344 -#define SCMI_COMPLETION_INTERRUPT_C20_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C21_REG_OFFSET 0x348 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C21_REG_OFFSET 0x34c -#define SCMI_CHANNEL_STATUS_C21_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C21_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C21_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C21_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C21_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C21_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C21_REG_OFFSET 0x350 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C21_REG_OFFSET 0x354 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C21_REG_OFFSET 0x358 -#define SCMI_CHANNEL_FLAGS_C21_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C21_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C21_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C21_REG_OFFSET 0x35c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C21_REG_OFFSET 0x360 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C21_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C21_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C21_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C21_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C21_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C21_REG_OFFSET 0x364 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C21_REG_OFFSET 0x368 -#define SCMI_DOORBELL_C21_INTR_BIT 0 -#define SCMI_DOORBELL_C21_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C21_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C21_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C21_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C21_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C21_REG_OFFSET 0x36c -#define SCMI_COMPLETION_INTERRUPT_C21_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C22_REG_OFFSET 0x370 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C22_REG_OFFSET 0x374 -#define SCMI_CHANNEL_STATUS_C22_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C22_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C22_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C22_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C22_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C22_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C22_REG_OFFSET 0x378 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C22_REG_OFFSET 0x37c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C22_REG_OFFSET 0x380 -#define SCMI_CHANNEL_FLAGS_C22_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C22_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C22_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C22_REG_OFFSET 0x384 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C22_REG_OFFSET 0x388 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C22_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C22_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C22_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C22_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C22_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C22_REG_OFFSET 0x38c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C22_REG_OFFSET 0x390 -#define SCMI_DOORBELL_C22_INTR_BIT 0 -#define SCMI_DOORBELL_C22_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C22_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C22_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C22_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C22_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C22_REG_OFFSET 0x394 -#define SCMI_COMPLETION_INTERRUPT_C22_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C23_REG_OFFSET 0x398 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C23_REG_OFFSET 0x39c -#define SCMI_CHANNEL_STATUS_C23_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C23_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C23_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C23_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C23_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C23_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C23_REG_OFFSET 0x3a0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C23_REG_OFFSET 0x3a4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C23_REG_OFFSET 0x3a8 -#define SCMI_CHANNEL_FLAGS_C23_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C23_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C23_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C23_REG_OFFSET 0x3ac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C23_REG_OFFSET 0x3b0 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C23_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C23_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C23_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C23_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C23_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C23_REG_OFFSET 0x3b4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C23_REG_OFFSET 0x3b8 -#define SCMI_DOORBELL_C23_INTR_BIT 0 -#define SCMI_DOORBELL_C23_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C23_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C23_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C23_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C23_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C23_REG_OFFSET 0x3bc -#define SCMI_COMPLETION_INTERRUPT_C23_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C24_REG_OFFSET 0x3c0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C24_REG_OFFSET 0x3c4 -#define SCMI_CHANNEL_STATUS_C24_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C24_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C24_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C24_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C24_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C24_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C24_REG_OFFSET 0x3c8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C24_REG_OFFSET 0x3cc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C24_REG_OFFSET 0x3d0 -#define SCMI_CHANNEL_FLAGS_C24_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C24_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C24_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C24_REG_OFFSET 0x3d4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C24_REG_OFFSET 0x3d8 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C24_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C24_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C24_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C24_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C24_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C24_REG_OFFSET 0x3dc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C24_REG_OFFSET 0x3e0 -#define SCMI_DOORBELL_C24_INTR_BIT 0 -#define SCMI_DOORBELL_C24_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C24_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C24_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C24_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C24_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C24_REG_OFFSET 0x3e4 -#define SCMI_COMPLETION_INTERRUPT_C24_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C25_REG_OFFSET 0x3e8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C25_REG_OFFSET 0x3ec -#define SCMI_CHANNEL_STATUS_C25_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C25_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C25_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C25_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C25_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C25_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C25_REG_OFFSET 0x3f0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C25_REG_OFFSET 0x3f4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C25_REG_OFFSET 0x3f8 -#define SCMI_CHANNEL_FLAGS_C25_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C25_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C25_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C25_REG_OFFSET 0x3fc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C25_REG_OFFSET 0x400 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C25_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C25_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C25_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C25_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C25_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C25_REG_OFFSET 0x404 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C25_REG_OFFSET 0x408 -#define SCMI_DOORBELL_C25_INTR_BIT 0 -#define SCMI_DOORBELL_C25_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C25_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C25_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C25_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C25_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C25_REG_OFFSET 0x40c -#define SCMI_COMPLETION_INTERRUPT_C25_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C26_REG_OFFSET 0x410 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C26_REG_OFFSET 0x414 -#define SCMI_CHANNEL_STATUS_C26_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C26_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C26_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C26_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C26_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C26_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C26_REG_OFFSET 0x418 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C26_REG_OFFSET 0x41c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C26_REG_OFFSET 0x420 -#define SCMI_CHANNEL_FLAGS_C26_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C26_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C26_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C26_REG_OFFSET 0x424 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C26_REG_OFFSET 0x428 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C26_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C26_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C26_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C26_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C26_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C26_REG_OFFSET 0x42c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C26_REG_OFFSET 0x430 -#define SCMI_DOORBELL_C26_INTR_BIT 0 -#define SCMI_DOORBELL_C26_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C26_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C26_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C26_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C26_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C26_REG_OFFSET 0x434 -#define SCMI_COMPLETION_INTERRUPT_C26_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C27_REG_OFFSET 0x438 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C27_REG_OFFSET 0x43c -#define SCMI_CHANNEL_STATUS_C27_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C27_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C27_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C27_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C27_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C27_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C27_REG_OFFSET 0x440 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C27_REG_OFFSET 0x444 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C27_REG_OFFSET 0x448 -#define SCMI_CHANNEL_FLAGS_C27_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C27_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C27_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C27_REG_OFFSET 0x44c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C27_REG_OFFSET 0x450 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C27_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C27_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C27_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C27_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C27_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C27_REG_OFFSET 0x454 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C27_REG_OFFSET 0x458 -#define SCMI_DOORBELL_C27_INTR_BIT 0 -#define SCMI_DOORBELL_C27_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C27_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C27_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C27_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C27_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C27_REG_OFFSET 0x45c -#define SCMI_COMPLETION_INTERRUPT_C27_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C28_REG_OFFSET 0x460 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C28_REG_OFFSET 0x464 -#define SCMI_CHANNEL_STATUS_C28_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C28_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C28_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C28_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C28_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C28_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C28_REG_OFFSET 0x468 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C28_REG_OFFSET 0x46c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C28_REG_OFFSET 0x470 -#define SCMI_CHANNEL_FLAGS_C28_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C28_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C28_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C28_REG_OFFSET 0x474 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C28_REG_OFFSET 0x478 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C28_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C28_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C28_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C28_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C28_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C28_REG_OFFSET 0x47c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C28_REG_OFFSET 0x480 -#define SCMI_DOORBELL_C28_INTR_BIT 0 -#define SCMI_DOORBELL_C28_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C28_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C28_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C28_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C28_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C28_REG_OFFSET 0x484 -#define SCMI_COMPLETION_INTERRUPT_C28_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C29_REG_OFFSET 0x488 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C29_REG_OFFSET 0x48c -#define SCMI_CHANNEL_STATUS_C29_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C29_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C29_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C29_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C29_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C29_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C29_REG_OFFSET 0x490 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C29_REG_OFFSET 0x494 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C29_REG_OFFSET 0x498 -#define SCMI_CHANNEL_FLAGS_C29_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C29_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C29_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C29_REG_OFFSET 0x49c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C29_REG_OFFSET 0x4a0 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C29_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C29_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C29_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C29_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C29_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C29_REG_OFFSET 0x4a4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C29_REG_OFFSET 0x4a8 -#define SCMI_DOORBELL_C29_INTR_BIT 0 -#define SCMI_DOORBELL_C29_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C29_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C29_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C29_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C29_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C29_REG_OFFSET 0x4ac -#define SCMI_COMPLETION_INTERRUPT_C29_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C30_REG_OFFSET 0x4b0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C30_REG_OFFSET 0x4b4 -#define SCMI_CHANNEL_STATUS_C30_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C30_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C30_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C30_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C30_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C30_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C30_REG_OFFSET 0x4b8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C30_REG_OFFSET 0x4bc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C30_REG_OFFSET 0x4c0 -#define SCMI_CHANNEL_FLAGS_C30_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C30_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C30_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C30_REG_OFFSET 0x4c4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C30_REG_OFFSET 0x4c8 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C30_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C30_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C30_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C30_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C30_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C30_REG_OFFSET 0x4cc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C30_REG_OFFSET 0x4d0 -#define SCMI_DOORBELL_C30_INTR_BIT 0 -#define SCMI_DOORBELL_C30_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C30_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C30_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C30_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C30_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C30_REG_OFFSET 0x4d4 -#define SCMI_COMPLETION_INTERRUPT_C30_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C31_REG_OFFSET 0x4d8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C31_REG_OFFSET 0x4dc -#define SCMI_CHANNEL_STATUS_C31_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C31_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C31_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C31_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C31_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C31_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C31_REG_OFFSET 0x4e0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C31_REG_OFFSET 0x4e4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C31_REG_OFFSET 0x4e8 -#define SCMI_CHANNEL_FLAGS_C31_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C31_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C31_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C31_REG_OFFSET 0x4ec - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C31_REG_OFFSET 0x4f0 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C31_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C31_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C31_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C31_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C31_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C31_REG_OFFSET 0x4f4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C31_REG_OFFSET 0x4f8 -#define SCMI_DOORBELL_C31_INTR_BIT 0 -#define SCMI_DOORBELL_C31_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C31_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C31_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C31_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C31_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C31_REG_OFFSET 0x4fc -#define SCMI_COMPLETION_INTERRUPT_C31_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C32_REG_OFFSET 0x500 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C32_REG_OFFSET 0x504 -#define SCMI_CHANNEL_STATUS_C32_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C32_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C32_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C32_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C32_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C32_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C32_REG_OFFSET 0x508 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C32_REG_OFFSET 0x50c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C32_REG_OFFSET 0x510 -#define SCMI_CHANNEL_FLAGS_C32_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C32_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C32_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C32_REG_OFFSET 0x514 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C32_REG_OFFSET 0x518 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C32_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C32_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C32_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C32_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C32_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C32_REG_OFFSET 0x51c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C32_REG_OFFSET 0x520 -#define SCMI_DOORBELL_C32_INTR_BIT 0 -#define SCMI_DOORBELL_C32_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C32_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C32_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C32_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C32_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C32_REG_OFFSET 0x524 -#define SCMI_COMPLETION_INTERRUPT_C32_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C33_REG_OFFSET 0x528 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C33_REG_OFFSET 0x52c -#define SCMI_CHANNEL_STATUS_C33_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C33_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C33_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C33_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C33_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C33_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C33_REG_OFFSET 0x530 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C33_REG_OFFSET 0x534 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C33_REG_OFFSET 0x538 -#define SCMI_CHANNEL_FLAGS_C33_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C33_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C33_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C33_REG_OFFSET 0x53c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C33_REG_OFFSET 0x540 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C33_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C33_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C33_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C33_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C33_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C33_REG_OFFSET 0x544 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C33_REG_OFFSET 0x548 -#define SCMI_DOORBELL_C33_INTR_BIT 0 -#define SCMI_DOORBELL_C33_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C33_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C33_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C33_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C33_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C33_REG_OFFSET 0x54c -#define SCMI_COMPLETION_INTERRUPT_C33_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C34_REG_OFFSET 0x550 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C34_REG_OFFSET 0x554 -#define SCMI_CHANNEL_STATUS_C34_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C34_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C34_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C34_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C34_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C34_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C34_REG_OFFSET 0x558 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C34_REG_OFFSET 0x55c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C34_REG_OFFSET 0x560 -#define SCMI_CHANNEL_FLAGS_C34_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C34_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C34_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C34_REG_OFFSET 0x564 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C34_REG_OFFSET 0x568 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C34_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C34_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C34_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C34_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C34_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C34_REG_OFFSET 0x56c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C34_REG_OFFSET 0x570 -#define SCMI_DOORBELL_C34_INTR_BIT 0 -#define SCMI_DOORBELL_C34_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C34_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C34_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C34_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C34_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C34_REG_OFFSET 0x574 -#define SCMI_COMPLETION_INTERRUPT_C34_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C35_REG_OFFSET 0x578 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C35_REG_OFFSET 0x57c -#define SCMI_CHANNEL_STATUS_C35_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C35_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C35_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C35_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C35_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C35_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C35_REG_OFFSET 0x580 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C35_REG_OFFSET 0x584 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C35_REG_OFFSET 0x588 -#define SCMI_CHANNEL_FLAGS_C35_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C35_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C35_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C35_REG_OFFSET 0x58c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C35_REG_OFFSET 0x590 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C35_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C35_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C35_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C35_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C35_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C35_REG_OFFSET 0x594 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C35_REG_OFFSET 0x598 -#define SCMI_DOORBELL_C35_INTR_BIT 0 -#define SCMI_DOORBELL_C35_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C35_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C35_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C35_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C35_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C35_REG_OFFSET 0x59c -#define SCMI_COMPLETION_INTERRUPT_C35_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C36_REG_OFFSET 0x5a0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C36_REG_OFFSET 0x5a4 -#define SCMI_CHANNEL_STATUS_C36_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C36_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C36_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C36_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C36_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C36_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C36_REG_OFFSET 0x5a8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C36_REG_OFFSET 0x5ac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C36_REG_OFFSET 0x5b0 -#define SCMI_CHANNEL_FLAGS_C36_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C36_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C36_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C36_REG_OFFSET 0x5b4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C36_REG_OFFSET 0x5b8 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C36_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C36_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C36_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C36_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C36_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C36_REG_OFFSET 0x5bc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C36_REG_OFFSET 0x5c0 -#define SCMI_DOORBELL_C36_INTR_BIT 0 -#define SCMI_DOORBELL_C36_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C36_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C36_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C36_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C36_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C36_REG_OFFSET 0x5c4 -#define SCMI_COMPLETION_INTERRUPT_C36_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C37_REG_OFFSET 0x5c8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C37_REG_OFFSET 0x5cc -#define SCMI_CHANNEL_STATUS_C37_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C37_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C37_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C37_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C37_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C37_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C37_REG_OFFSET 0x5d0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C37_REG_OFFSET 0x5d4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C37_REG_OFFSET 0x5d8 -#define SCMI_CHANNEL_FLAGS_C37_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C37_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C37_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C37_REG_OFFSET 0x5dc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C37_REG_OFFSET 0x5e0 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C37_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C37_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C37_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C37_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C37_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C37_REG_OFFSET 0x5e4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C37_REG_OFFSET 0x5e8 -#define SCMI_DOORBELL_C37_INTR_BIT 0 -#define SCMI_DOORBELL_C37_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C37_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C37_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C37_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C37_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C37_REG_OFFSET 0x5ec -#define SCMI_COMPLETION_INTERRUPT_C37_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C38_REG_OFFSET 0x5f0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C38_REG_OFFSET 0x5f4 -#define SCMI_CHANNEL_STATUS_C38_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C38_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C38_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C38_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C38_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C38_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C38_REG_OFFSET 0x5f8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C38_REG_OFFSET 0x5fc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C38_REG_OFFSET 0x600 -#define SCMI_CHANNEL_FLAGS_C38_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C38_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C38_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C38_REG_OFFSET 0x604 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C38_REG_OFFSET 0x608 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C38_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C38_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C38_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C38_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C38_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C38_REG_OFFSET 0x60c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C38_REG_OFFSET 0x610 -#define SCMI_DOORBELL_C38_INTR_BIT 0 -#define SCMI_DOORBELL_C38_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C38_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C38_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C38_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C38_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C38_REG_OFFSET 0x614 -#define SCMI_COMPLETION_INTERRUPT_C38_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C39_REG_OFFSET 0x618 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C39_REG_OFFSET 0x61c -#define SCMI_CHANNEL_STATUS_C39_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C39_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C39_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C39_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C39_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C39_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C39_REG_OFFSET 0x620 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C39_REG_OFFSET 0x624 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C39_REG_OFFSET 0x628 -#define SCMI_CHANNEL_FLAGS_C39_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C39_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C39_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C39_REG_OFFSET 0x62c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C39_REG_OFFSET 0x630 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C39_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C39_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C39_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C39_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C39_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C39_REG_OFFSET 0x634 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C39_REG_OFFSET 0x638 -#define SCMI_DOORBELL_C39_INTR_BIT 0 -#define SCMI_DOORBELL_C39_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C39_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C39_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C39_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C39_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C39_REG_OFFSET 0x63c -#define SCMI_COMPLETION_INTERRUPT_C39_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C40_REG_OFFSET 0x640 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C40_REG_OFFSET 0x644 -#define SCMI_CHANNEL_STATUS_C40_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C40_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C40_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C40_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C40_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C40_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C40_REG_OFFSET 0x648 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C40_REG_OFFSET 0x64c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C40_REG_OFFSET 0x650 -#define SCMI_CHANNEL_FLAGS_C40_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C40_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C40_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C40_REG_OFFSET 0x654 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C40_REG_OFFSET 0x658 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C40_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C40_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C40_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C40_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C40_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C40_REG_OFFSET 0x65c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C40_REG_OFFSET 0x660 -#define SCMI_DOORBELL_C40_INTR_BIT 0 -#define SCMI_DOORBELL_C40_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C40_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C40_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C40_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C40_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C40_REG_OFFSET 0x664 -#define SCMI_COMPLETION_INTERRUPT_C40_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C41_REG_OFFSET 0x668 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C41_REG_OFFSET 0x66c -#define SCMI_CHANNEL_STATUS_C41_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C41_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C41_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C41_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C41_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C41_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C41_REG_OFFSET 0x670 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C41_REG_OFFSET 0x674 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C41_REG_OFFSET 0x678 -#define SCMI_CHANNEL_FLAGS_C41_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C41_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C41_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C41_REG_OFFSET 0x67c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C41_REG_OFFSET 0x680 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C41_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C41_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C41_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C41_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C41_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C41_REG_OFFSET 0x684 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C41_REG_OFFSET 0x688 -#define SCMI_DOORBELL_C41_INTR_BIT 0 -#define SCMI_DOORBELL_C41_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C41_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C41_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C41_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C41_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C41_REG_OFFSET 0x68c -#define SCMI_COMPLETION_INTERRUPT_C41_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C42_REG_OFFSET 0x690 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C42_REG_OFFSET 0x694 -#define SCMI_CHANNEL_STATUS_C42_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C42_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C42_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C42_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C42_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C42_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C42_REG_OFFSET 0x698 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C42_REG_OFFSET 0x69c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C42_REG_OFFSET 0x6a0 -#define SCMI_CHANNEL_FLAGS_C42_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C42_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C42_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C42_REG_OFFSET 0x6a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C42_REG_OFFSET 0x6a8 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C42_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C42_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C42_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C42_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C42_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C42_REG_OFFSET 0x6ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C42_REG_OFFSET 0x6b0 -#define SCMI_DOORBELL_C42_INTR_BIT 0 -#define SCMI_DOORBELL_C42_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C42_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C42_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C42_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C42_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C42_REG_OFFSET 0x6b4 -#define SCMI_COMPLETION_INTERRUPT_C42_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C43_REG_OFFSET 0x6b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C43_REG_OFFSET 0x6bc -#define SCMI_CHANNEL_STATUS_C43_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C43_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C43_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C43_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C43_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C43_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C43_REG_OFFSET 0x6c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C43_REG_OFFSET 0x6c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C43_REG_OFFSET 0x6c8 -#define SCMI_CHANNEL_FLAGS_C43_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C43_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C43_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C43_REG_OFFSET 0x6cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C43_REG_OFFSET 0x6d0 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C43_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C43_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C43_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C43_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C43_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C43_REG_OFFSET 0x6d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C43_REG_OFFSET 0x6d8 -#define SCMI_DOORBELL_C43_INTR_BIT 0 -#define SCMI_DOORBELL_C43_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C43_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C43_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C43_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C43_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C43_REG_OFFSET 0x6dc -#define SCMI_COMPLETION_INTERRUPT_C43_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C44_REG_OFFSET 0x6e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C44_REG_OFFSET 0x6e4 -#define SCMI_CHANNEL_STATUS_C44_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C44_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C44_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C44_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C44_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C44_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C44_REG_OFFSET 0x6e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C44_REG_OFFSET 0x6ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C44_REG_OFFSET 0x6f0 -#define SCMI_CHANNEL_FLAGS_C44_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C44_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C44_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C44_REG_OFFSET 0x6f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C44_REG_OFFSET 0x6f8 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C44_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C44_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C44_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C44_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C44_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C44_REG_OFFSET 0x6fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C44_REG_OFFSET 0x700 -#define SCMI_DOORBELL_C44_INTR_BIT 0 -#define SCMI_DOORBELL_C44_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C44_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C44_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C44_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C44_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C44_REG_OFFSET 0x704 -#define SCMI_COMPLETION_INTERRUPT_C44_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C45_REG_OFFSET 0x708 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C45_REG_OFFSET 0x70c -#define SCMI_CHANNEL_STATUS_C45_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C45_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C45_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C45_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C45_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C45_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C45_REG_OFFSET 0x710 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C45_REG_OFFSET 0x714 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C45_REG_OFFSET 0x718 -#define SCMI_CHANNEL_FLAGS_C45_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C45_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C45_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C45_REG_OFFSET 0x71c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C45_REG_OFFSET 0x720 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C45_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C45_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C45_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C45_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C45_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C45_REG_OFFSET 0x724 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C45_REG_OFFSET 0x728 -#define SCMI_DOORBELL_C45_INTR_BIT 0 -#define SCMI_DOORBELL_C45_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C45_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C45_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C45_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C45_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C45_REG_OFFSET 0x72c -#define SCMI_COMPLETION_INTERRUPT_C45_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C46_REG_OFFSET 0x730 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C46_REG_OFFSET 0x734 -#define SCMI_CHANNEL_STATUS_C46_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C46_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C46_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C46_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C46_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C46_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C46_REG_OFFSET 0x738 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C46_REG_OFFSET 0x73c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C46_REG_OFFSET 0x740 -#define SCMI_CHANNEL_FLAGS_C46_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C46_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C46_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C46_REG_OFFSET 0x744 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C46_REG_OFFSET 0x748 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C46_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C46_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C46_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C46_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C46_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C46_REG_OFFSET 0x74c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C46_REG_OFFSET 0x750 -#define SCMI_DOORBELL_C46_INTR_BIT 0 -#define SCMI_DOORBELL_C46_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C46_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C46_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C46_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C46_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C46_REG_OFFSET 0x754 -#define SCMI_COMPLETION_INTERRUPT_C46_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C47_REG_OFFSET 0x758 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C47_REG_OFFSET 0x75c -#define SCMI_CHANNEL_STATUS_C47_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C47_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C47_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C47_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C47_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C47_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C47_REG_OFFSET 0x760 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C47_REG_OFFSET 0x764 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C47_REG_OFFSET 0x768 -#define SCMI_CHANNEL_FLAGS_C47_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C47_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C47_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C47_REG_OFFSET 0x76c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C47_REG_OFFSET 0x770 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C47_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C47_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C47_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C47_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C47_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C47_REG_OFFSET 0x774 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C47_REG_OFFSET 0x778 -#define SCMI_DOORBELL_C47_INTR_BIT 0 -#define SCMI_DOORBELL_C47_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C47_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C47_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C47_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C47_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C47_REG_OFFSET 0x77c -#define SCMI_COMPLETION_INTERRUPT_C47_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C48_REG_OFFSET 0x780 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C48_REG_OFFSET 0x784 -#define SCMI_CHANNEL_STATUS_C48_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C48_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C48_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C48_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C48_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C48_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C48_REG_OFFSET 0x788 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C48_REG_OFFSET 0x78c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C48_REG_OFFSET 0x790 -#define SCMI_CHANNEL_FLAGS_C48_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C48_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C48_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C48_REG_OFFSET 0x794 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C48_REG_OFFSET 0x798 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C48_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C48_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C48_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C48_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C48_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C48_REG_OFFSET 0x79c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C48_REG_OFFSET 0x7a0 -#define SCMI_DOORBELL_C48_INTR_BIT 0 -#define SCMI_DOORBELL_C48_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C48_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C48_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C48_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C48_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C48_REG_OFFSET 0x7a4 -#define SCMI_COMPLETION_INTERRUPT_C48_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C49_REG_OFFSET 0x7a8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C49_REG_OFFSET 0x7ac -#define SCMI_CHANNEL_STATUS_C49_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C49_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C49_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C49_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C49_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C49_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C49_REG_OFFSET 0x7b0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C49_REG_OFFSET 0x7b4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C49_REG_OFFSET 0x7b8 -#define SCMI_CHANNEL_FLAGS_C49_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C49_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C49_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C49_REG_OFFSET 0x7bc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C49_REG_OFFSET 0x7c0 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C49_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C49_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C49_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C49_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C49_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C49_REG_OFFSET 0x7c4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C49_REG_OFFSET 0x7c8 -#define SCMI_DOORBELL_C49_INTR_BIT 0 -#define SCMI_DOORBELL_C49_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C49_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C49_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C49_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C49_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C49_REG_OFFSET 0x7cc -#define SCMI_COMPLETION_INTERRUPT_C49_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C50_REG_OFFSET 0x7d0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C50_REG_OFFSET 0x7d4 -#define SCMI_CHANNEL_STATUS_C50_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C50_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C50_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C50_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C50_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C50_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C50_REG_OFFSET 0x7d8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C50_REG_OFFSET 0x7dc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C50_REG_OFFSET 0x7e0 -#define SCMI_CHANNEL_FLAGS_C50_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C50_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C50_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C50_REG_OFFSET 0x7e4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C50_REG_OFFSET 0x7e8 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C50_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C50_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C50_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C50_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C50_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C50_REG_OFFSET 0x7ec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C50_REG_OFFSET 0x7f0 -#define SCMI_DOORBELL_C50_INTR_BIT 0 -#define SCMI_DOORBELL_C50_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C50_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C50_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C50_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C50_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C50_REG_OFFSET 0x7f4 -#define SCMI_COMPLETION_INTERRUPT_C50_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C51_REG_OFFSET 0x7f8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C51_REG_OFFSET 0x7fc -#define SCMI_CHANNEL_STATUS_C51_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C51_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C51_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C51_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C51_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C51_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C51_REG_OFFSET 0x800 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C51_REG_OFFSET 0x804 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C51_REG_OFFSET 0x808 -#define SCMI_CHANNEL_FLAGS_C51_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C51_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C51_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C51_REG_OFFSET 0x80c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C51_REG_OFFSET 0x810 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C51_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C51_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C51_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C51_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C51_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET 0x1c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C51_REG_OFFSET 0x814 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C51_REG_OFFSET 0x818 -#define SCMI_DOORBELL_C51_INTR_BIT 0 -#define SCMI_DOORBELL_C51_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C51_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C51_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C51_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C51_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C51_REG_OFFSET 0x81c -#define SCMI_COMPLETION_INTERRUPT_C51_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C52_REG_OFFSET 0x820 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C52_REG_OFFSET 0x824 -#define SCMI_CHANNEL_STATUS_C52_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C52_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C52_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C52_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C52_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C52_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C52_REG_OFFSET 0x828 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C52_REG_OFFSET 0x82c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C52_REG_OFFSET 0x830 -#define SCMI_CHANNEL_FLAGS_C52_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C52_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C52_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C52_REG_OFFSET 0x834 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C52_REG_OFFSET 0x838 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C52_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C52_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C52_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C52_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C52_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET 0x20 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C52_REG_OFFSET 0x83c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C52_REG_OFFSET 0x840 -#define SCMI_DOORBELL_C52_INTR_BIT 0 -#define SCMI_DOORBELL_C52_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C52_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C52_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C52_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C52_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C52_REG_OFFSET 0x844 -#define SCMI_COMPLETION_INTERRUPT_C52_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C53_REG_OFFSET 0x848 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C53_REG_OFFSET 0x84c -#define SCMI_CHANNEL_STATUS_C53_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C53_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C53_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C53_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C53_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C53_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C53_REG_OFFSET 0x850 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C53_REG_OFFSET 0x854 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C53_REG_OFFSET 0x858 -#define SCMI_CHANNEL_FLAGS_C53_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C53_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C53_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C53_REG_OFFSET 0x85c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C53_REG_OFFSET 0x860 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C53_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C53_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C53_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C53_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C53_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_2_C0_REG_OFFSET 0x24 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C53_REG_OFFSET 0x864 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C53_REG_OFFSET 0x868 -#define SCMI_DOORBELL_C53_INTR_BIT 0 -#define SCMI_DOORBELL_C53_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C53_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C53_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C53_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C53_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C53_REG_OFFSET 0x86c -#define SCMI_COMPLETION_INTERRUPT_C53_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C54_REG_OFFSET 0x870 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C54_REG_OFFSET 0x874 -#define SCMI_CHANNEL_STATUS_C54_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C54_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C54_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C54_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C54_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C54_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C54_REG_OFFSET 0x878 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C54_REG_OFFSET 0x87c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C54_REG_OFFSET 0x880 -#define SCMI_CHANNEL_FLAGS_C54_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C54_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C54_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C54_REG_OFFSET 0x884 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C54_REG_OFFSET 0x888 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C54_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C54_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C54_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C54_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C54_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_3_C0_REG_OFFSET 0x28 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C54_REG_OFFSET 0x88c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C54_REG_OFFSET 0x890 -#define SCMI_DOORBELL_C54_INTR_BIT 0 -#define SCMI_DOORBELL_C54_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C54_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C54_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C54_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C54_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C54_REG_OFFSET 0x894 -#define SCMI_COMPLETION_INTERRUPT_C54_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C55_REG_OFFSET 0x898 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C55_REG_OFFSET 0x89c -#define SCMI_CHANNEL_STATUS_C55_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C55_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C55_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C55_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C55_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C55_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C55_REG_OFFSET 0x8a0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C55_REG_OFFSET 0x8a4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C55_REG_OFFSET 0x8a8 -#define SCMI_CHANNEL_FLAGS_C55_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C55_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C55_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C55_REG_OFFSET 0x8ac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C55_REG_OFFSET 0x8b0 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C55_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C55_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C55_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C55_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C55_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_4_C0_REG_OFFSET 0x2c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C55_REG_OFFSET 0x8b4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C55_REG_OFFSET 0x8b8 -#define SCMI_DOORBELL_C55_INTR_BIT 0 -#define SCMI_DOORBELL_C55_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C55_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C55_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C55_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C55_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C55_REG_OFFSET 0x8bc -#define SCMI_COMPLETION_INTERRUPT_C55_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C56_REG_OFFSET 0x8c0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C56_REG_OFFSET 0x8c4 -#define SCMI_CHANNEL_STATUS_C56_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C56_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C56_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C56_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C56_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C56_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C56_REG_OFFSET 0x8c8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C56_REG_OFFSET 0x8cc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C56_REG_OFFSET 0x8d0 -#define SCMI_CHANNEL_FLAGS_C56_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C56_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C56_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C56_REG_OFFSET 0x8d4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C56_REG_OFFSET 0x8d8 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C56_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C56_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C56_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C56_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C56_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_5_C0_REG_OFFSET 0x30 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C56_REG_OFFSET 0x8dc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C56_REG_OFFSET 0x8e0 -#define SCMI_DOORBELL_C56_INTR_BIT 0 -#define SCMI_DOORBELL_C56_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C56_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C56_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C56_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C56_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C56_REG_OFFSET 0x8e4 -#define SCMI_COMPLETION_INTERRUPT_C56_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C57_REG_OFFSET 0x8e8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C57_REG_OFFSET 0x8ec -#define SCMI_CHANNEL_STATUS_C57_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C57_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C57_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C57_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C57_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C57_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C57_REG_OFFSET 0x8f0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C57_REG_OFFSET 0x8f4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C57_REG_OFFSET 0x8f8 -#define SCMI_CHANNEL_FLAGS_C57_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C57_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C57_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C57_REG_OFFSET 0x8fc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C57_REG_OFFSET 0x900 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C57_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C57_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C57_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C57_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C57_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_6_C0_REG_OFFSET 0x34 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C57_REG_OFFSET 0x904 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C57_REG_OFFSET 0x908 -#define SCMI_DOORBELL_C57_INTR_BIT 0 -#define SCMI_DOORBELL_C57_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C57_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C57_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C57_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C57_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C57_REG_OFFSET 0x90c -#define SCMI_COMPLETION_INTERRUPT_C57_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C58_REG_OFFSET 0x910 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C58_REG_OFFSET 0x914 -#define SCMI_CHANNEL_STATUS_C58_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C58_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C58_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C58_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C58_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C58_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C58_REG_OFFSET 0x918 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C58_REG_OFFSET 0x91c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C58_REG_OFFSET 0x920 -#define SCMI_CHANNEL_FLAGS_C58_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C58_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C58_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C58_REG_OFFSET 0x924 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C58_REG_OFFSET 0x928 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C58_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C58_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C58_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C58_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C58_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_7_C0_REG_OFFSET 0x38 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C58_REG_OFFSET 0x92c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C58_REG_OFFSET 0x930 -#define SCMI_DOORBELL_C58_INTR_BIT 0 -#define SCMI_DOORBELL_C58_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C58_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C58_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C58_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C58_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C58_REG_OFFSET 0x934 -#define SCMI_COMPLETION_INTERRUPT_C58_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C59_REG_OFFSET 0x938 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C59_REG_OFFSET 0x93c -#define SCMI_CHANNEL_STATUS_C59_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C59_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C59_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C59_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C59_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C59_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C59_REG_OFFSET 0x940 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C59_REG_OFFSET 0x944 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C59_REG_OFFSET 0x948 -#define SCMI_CHANNEL_FLAGS_C59_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C59_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C59_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C59_REG_OFFSET 0x94c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C59_REG_OFFSET 0x950 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C59_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C59_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C59_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C59_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C59_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_8_C0_REG_OFFSET 0x3c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C59_REG_OFFSET 0x954 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C59_REG_OFFSET 0x958 -#define SCMI_DOORBELL_C59_INTR_BIT 0 -#define SCMI_DOORBELL_C59_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C59_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C59_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C59_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C59_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C59_REG_OFFSET 0x95c -#define SCMI_COMPLETION_INTERRUPT_C59_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C60_REG_OFFSET 0x960 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C60_REG_OFFSET 0x964 -#define SCMI_CHANNEL_STATUS_C60_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C60_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C60_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C60_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C60_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C60_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C60_REG_OFFSET 0x968 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C60_REG_OFFSET 0x96c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C60_REG_OFFSET 0x970 -#define SCMI_CHANNEL_FLAGS_C60_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C60_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C60_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C60_REG_OFFSET 0x974 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C60_REG_OFFSET 0x978 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C60_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C60_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C60_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C60_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C60_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_9_C0_REG_OFFSET 0x40 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C60_REG_OFFSET 0x97c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C60_REG_OFFSET 0x980 -#define SCMI_DOORBELL_C60_INTR_BIT 0 -#define SCMI_DOORBELL_C60_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C60_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C60_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C60_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C60_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C60_REG_OFFSET 0x984 -#define SCMI_COMPLETION_INTERRUPT_C60_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C61_REG_OFFSET 0x988 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C61_REG_OFFSET 0x98c -#define SCMI_CHANNEL_STATUS_C61_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C61_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C61_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C61_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C61_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C61_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C61_REG_OFFSET 0x990 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C61_REG_OFFSET 0x994 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C61_REG_OFFSET 0x998 -#define SCMI_CHANNEL_FLAGS_C61_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C61_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C61_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C61_REG_OFFSET 0x99c +#define SCMI_MESSAGE_PAYLOAD_10_C0_REG_OFFSET 0x44 -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C61_REG_OFFSET 0x9a0 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C61_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C61_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C61_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C61_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C61_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_11_C0_REG_OFFSET 0x48 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C61_REG_OFFSET 0x9a4 +#define SCMI_MESSAGE_PAYLOAD_12_C0_REG_OFFSET 0x4c -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C61_REG_OFFSET 0x9a8 -#define SCMI_DOORBELL_C61_INTR_BIT 0 -#define SCMI_DOORBELL_C61_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C61_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C61_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C61_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C61_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_13_C0_REG_OFFSET 0x50 -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C61_REG_OFFSET 0x9ac -#define SCMI_COMPLETION_INTERRUPT_C61_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_14_C0_REG_OFFSET 0x54 -// Reserved, must be 0 -#define SCMI_RESERVED_1_C62_REG_OFFSET 0x9b0 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_15_C0_REG_OFFSET 0x58 -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C62_REG_OFFSET 0x9b4 -#define SCMI_CHANNEL_STATUS_C62_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C62_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C62_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C62_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C62_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C62_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_16_C0_REG_OFFSET 0x5c -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C62_REG_OFFSET 0x9b8 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_17_C0_REG_OFFSET 0x60 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C62_REG_OFFSET 0x9bc +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_18_C0_REG_OFFSET 0x64 -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C62_REG_OFFSET 0x9c0 -#define SCMI_CHANNEL_FLAGS_C62_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C62_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C62_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_19_C0_REG_OFFSET 0x68 -// Lenght of payload + header -#define SCMI_LENGTH_C62_REG_OFFSET 0x9c4 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_20_C0_REG_OFFSET 0x6c -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C62_REG_OFFSET 0x9c8 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C62_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C62_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C62_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C62_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C62_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_21_C0_REG_OFFSET 0x70 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C62_REG_OFFSET 0x9cc +#define SCMI_MESSAGE_PAYLOAD_22_C0_REG_OFFSET 0x74 -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C62_REG_OFFSET 0x9d0 -#define SCMI_DOORBELL_C62_INTR_BIT 0 -#define SCMI_DOORBELL_C62_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C62_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C62_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C62_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C62_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_23_C0_REG_OFFSET 0x78 -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C62_REG_OFFSET 0x9d4 -#define SCMI_COMPLETION_INTERRUPT_C62_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_24_C0_REG_OFFSET 0x7c -// Reserved, must be 0 -#define SCMI_RESERVED_1_C63_REG_OFFSET 0x9d8 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_25_C0_REG_OFFSET 0x80 -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C63_REG_OFFSET 0x9dc -#define SCMI_CHANNEL_STATUS_C63_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C63_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C63_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C63_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C63_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C63_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_26_C0_REG_OFFSET 0x84 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C63_REG_OFFSET 0x9e0 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_27_C0_REG_OFFSET 0x88 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C63_REG_OFFSET 0x9e4 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_28_C0_REG_OFFSET 0x8c -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C63_REG_OFFSET 0x9e8 -#define SCMI_CHANNEL_FLAGS_C63_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C63_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C63_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_29_C0_REG_OFFSET 0x90 -// Lenght of payload + header -#define SCMI_LENGTH_C63_REG_OFFSET 0x9ec +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_30_C0_REG_OFFSET 0x94 -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C63_REG_OFFSET 0x9f0 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C63_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C63_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C63_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C63_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C63_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_31_C0_REG_OFFSET 0x98 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C63_REG_OFFSET 0x9f4 +#define SCMI_MESSAGE_PAYLOAD_32_C0_REG_OFFSET 0x9c // Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C63_REG_OFFSET 0x9f8 -#define SCMI_DOORBELL_C63_INTR_BIT 0 -#define SCMI_DOORBELL_C63_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C63_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C63_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C63_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C63_PRESERVE_MASK_OFFSET }) +#define SCMI_DOORBELL_C0_REG_OFFSET 0xa0 // Rapresent the interrupt the platform should raise when it finishes to // execute the received command -#define SCMI_COMPLETION_INTERRUPT_C63_REG_OFFSET 0x9fc -#define SCMI_COMPLETION_INTERRUPT_C63_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_OFFSET }) +#define SCMI_COMPLETION_INTERRUPT_C0_REG_OFFSET 0xa4 #ifdef __cplusplus } // extern "C" diff --git a/hw/ips/axi_scmi_mailbox/scmi.hjson b/hw/ips/axi_scmi_mailbox/scmi.hjson index a1361cf..8abfcf9 100644 --- a/hw/ips/axi_scmi_mailbox/scmi.hjson +++ b/hw/ips/axi_scmi_mailbox/scmi.hjson @@ -45,7 +45,7 @@ }, { name: "Reserved_3_c0", desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", + swaccess: "rw", hwaccess: "none", fields: [ { bits: "31:0" } @@ -95,26 +95,278 @@ } ], }, - { name: "Message_Payload_1_c0", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, + { name: "Message_Payload_0_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_1_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_2_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_3_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_4_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_5_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_6_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_7_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_8_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_9_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_10_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_11_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_12_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_13_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_14_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_15_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_16_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_17_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_18_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_19_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_20_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_21_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_22_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_23_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_24_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_25_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_26_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_27_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_28_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_29_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_30_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_31_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + { name: "Message_Payload_32_c0", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, { name: "Doorbell_c0", desc: "Rapresents the interrupt to be raised towards the platform", swaccess: "rw", hwaccess: "hro", fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", + { bits: "31:0", name: "intr", - desc: "Interrupt bit" + desc: "Interrupt bits" } ], }, @@ -123,7699 +375,9 @@ swaccess: "rw", hwaccess: "hro", fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c1", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c1", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c1", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c1", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c1", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c1", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c1", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c1", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c1", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c1", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c2", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c2", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c2", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c2", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c2", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c2", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c2", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c2", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c2", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c2", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c3", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c3", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c3", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c3", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c3", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c3", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c3", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c3", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c3", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c3", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c4", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c4", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c4", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c4", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c4", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c4", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c4", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c4", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c4", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c4", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c5", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c5", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c5", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c5", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c5", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c5", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c5", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c5", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c5", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c5", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c6", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c6", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c6", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c6", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c6", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c6", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c6", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c6", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c6", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c6", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c7", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c7", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c7", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c7", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c7", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c7", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c7", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c7", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c7", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c7", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c8", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c8", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c8", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c8", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c8", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c8", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c8", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c8", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c8", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c8", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c9", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c9", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c9", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c9", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c9", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c9", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c9", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c9", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c9", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c9", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c10", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c10", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c10", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c10", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c10", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c10", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c10", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c10", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c10", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c10", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c11", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c11", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c11", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c11", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c11", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c11", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c11", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c11", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c11", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c11", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c12", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c12", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c12", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c12", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c12", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c12", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c12", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c12", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c12", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c12", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c13", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c13", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c13", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c13", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c13", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c13", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c13", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c13", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c13", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c13", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c14", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c14", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c14", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c14", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c14", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c14", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c14", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c14", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c14", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c14", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c15", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c15", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c15", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c15", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c15", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c15", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c15", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c15", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c15", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c15", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c16", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c16", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c16", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c16", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c16", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c16", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c16", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c16", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c16", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c16", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c17", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c17", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c17", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c17", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c17", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c17", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c17", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c17", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c17", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c17", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c18", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c18", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c18", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c18", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c18", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c18", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c18", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c18", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c18", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c18", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c19", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c19", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c19", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c19", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c19", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c19", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c19", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c19", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c19", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c19", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c20", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c20", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c20", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c20", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c20", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c20", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c20", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c20", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c20", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c20", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c21", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c21", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c21", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c21", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c21", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c21", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c21", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c21", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c21", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c21", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c22", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c22", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c22", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c22", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c22", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c22", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c22", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c22", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c22", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c22", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c23", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c23", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c23", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c23", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c23", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c23", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c23", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c23", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c23", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c23", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c24", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c24", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c24", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c24", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c24", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c24", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c24", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c24", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c24", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c24", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c25", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c25", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c25", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c25", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c25", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c25", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c25", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c25", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c25", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c25", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c26", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c26", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c26", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c26", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c26", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c26", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c26", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c26", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c26", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c26", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c27", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c27", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c27", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c27", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c27", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c27", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c27", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c27", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c27", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c27", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c28", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c28", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c28", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c28", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c28", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c28", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c28", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c28", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c28", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c28", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c29", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c29", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c29", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c29", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c29", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c29", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c29", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c29", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c29", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c29", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c30", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c30", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c30", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c30", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c30", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c30", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c30", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c30", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c30", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c30", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c31", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c31", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c31", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c31", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c31", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c31", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c31", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c31", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c31", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c31", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c32", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c32", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c32", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c32", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c32", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c32", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c32", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c32", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c32", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c32", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c33", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c33", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c33", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c33", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c33", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c33", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c33", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c33", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c33", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c33", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c34", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c34", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c34", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c34", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c34", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c34", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c34", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c34", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c34", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c34", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c35", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c35", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c35", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c35", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c35", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c35", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c35", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c35", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c35", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c35", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c36", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c36", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c36", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c36", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c36", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c36", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c36", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c36", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c36", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c36", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c37", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c37", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c37", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c37", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c37", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c37", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c37", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c37", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c37", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c37", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c38", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c38", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c38", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c38", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c38", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c38", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c38", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c38", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c38", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c38", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c39", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c39", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c39", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c39", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c39", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c39", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c39", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c39", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c39", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c39", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c40", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c40", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c40", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c40", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c40", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c40", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c40", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c40", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c40", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c40", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c41", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c41", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c41", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c41", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c41", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c41", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c41", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c41", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c41", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c41", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c42", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c42", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c42", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c42", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c42", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c42", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c42", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c42", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c42", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c42", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c43", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c43", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c43", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c43", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c43", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c43", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c43", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c43", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c43", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c43", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c44", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c44", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c44", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c44", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c44", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c44", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c44", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c44", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c44", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c44", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c45", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c45", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c45", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c45", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c45", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c45", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c45", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c45", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c45", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c45", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c46", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c46", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c46", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c46", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c46", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c46", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c46", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c46", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c46", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c46", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c47", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c47", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c47", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c47", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c47", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c47", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c47", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c47", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c47", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c47", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c48", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c48", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c48", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c48", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c48", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c48", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c48", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c48", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c48", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c48", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c49", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c49", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c49", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c49", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c49", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c49", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c49", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c49", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c49", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c49", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c50", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c50", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c50", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c50", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c50", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c50", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c50", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c50", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c50", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c50", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c51", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c51", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c51", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c51", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c51", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c51", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c51", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c51", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c51", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c51", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c52", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c52", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c52", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c52", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c52", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c52", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c52", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c52", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c52", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c52", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c53", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c53", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c53", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c53", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c53", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c53", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c53", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c53", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c53", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c53", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c54", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c54", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c54", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c54", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c54", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c54", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c54", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c54", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c54", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c54", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c55", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c55", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c55", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c55", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c55", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c55", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c55", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c55", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c55", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c55", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c56", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c56", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c56", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c56", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c56", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c56", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c56", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c56", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c56", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c56", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c57", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c57", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c57", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c57", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c57", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c57", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c57", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c57", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c57", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c57", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c58", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c58", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c58", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c58", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c58", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c58", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c58", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c58", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c58", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c58", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c59", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c59", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c59", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c59", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c59", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c59", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c59", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c59", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c59", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c59", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c60", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c60", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c60", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c60", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c60", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c60", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c60", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c60", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c60", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c60", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c61", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c61", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c61", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c61", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c61", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c61", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c61", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c61", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c61", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c61", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c62", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c62", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c62", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c62", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c62", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c62", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c62", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c62", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c62", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c62", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Reserved_1_c63", - desc: "Reserved, must be 0", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Status_c63", - desc: "Indicates which entity has access to the Shared Memory", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:2" }, - { bits: "1", - name: "channel_error", - desc: "Must be 0 in absence of errors" - }, - { bits: "0", - name: "channel_free", - desc: "If 1 the agent own the channel, if 0 the platform own the channel" - } - ], - }, - { name: "Reserved_2_c63", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Reserved_3_c63", - desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Channel_Flags_c63", - desc: "Defines wheter interrupts or polling is used for communication", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:1" }, - { bits: "0", - name: "intr_enable", - desc: "If 1 interruts are used, if 0 polling is used" - } - ], - }, - { name: "Length_c63", - desc: "Lenght of payload + header", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Message_Header_c63", - desc: "Defines which commanad the message contains", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:28" }, - { bits: "27:18", - name: "Token", - desc: "must be same for the msg responses associated to a msg whith the same header" - }, - { bits: "17:10", - name: "Protocol_Id", - desc: "Identifies to which protocol the command belongs to" - }, - { bits: "9:8", - name: "Message_Type", - desc: "can be 0,1,2,3 depending on the kind of msg to be sent" - }, - { bits: "7:0", - name: "Message_Id", - desc: "unique identifier for each command availabe in the protocol pointed by protocol_id" - } - ], - }, - { name: "Message_Payload_1_c63", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, - { name: "Doorbell_c63", - desc: "Rapresents the interrupt to be raised towards the platform", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", - name: "intr", - desc: "Interrupt bit" - } - ], - }, - { name: "Completion_Interrupt_c63", - desc: "Rapresent the interrupt the platform should raise when it finishes to execute the received command", - swaccess: "rw", - hwaccess: "hro", - fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", + { bits: "31:0", name: "intr", - desc: "Interrupt bit" + desc: "Interrupt bits" } ], }, diff --git a/hw/ips/axi_scmi_mailbox/scmi.hjson.tpl b/hw/ips/axi_scmi_mailbox/scmi.hjson.tpl index 4d42f78..676d918 100644 --- a/hw/ips/axi_scmi_mailbox/scmi.hjson.tpl +++ b/hw/ips/axi_scmi_mailbox/scmi.hjson.tpl @@ -47,7 +47,7 @@ }, { name: "Reserved_3_c${i}", desc: "Reserved, implementation defined (32 bits over 64)", - swaccess: "none", + swaccess: "rw", hwaccess: "none", fields: [ { bits: "31:0" } @@ -97,26 +97,24 @@ } ], }, - { name: "Message_Payload_1_c${i}", - desc: "memory region dedicated to the parameters of the commands and their returns", - swaccess: "rw", - hwaccess: "none", - fields: [ - { bits: "31:0" } - ], - }, + % for j in range(33): + { name: "Message_Payload_${j}_c${i}", + desc: "memory region dedicated to the parameters of the commands and their returns", + swaccess: "rw", + hwaccess: "none", + fields: [ + { bits: "31:0" } + ], + }, + % endfor { name: "Doorbell_c${i}", desc: "Rapresents the interrupt to be raised towards the platform", swaccess: "rw", hwaccess: "hro", fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", + { bits: "31:0", name: "intr", - desc: "Interrupt bit" + desc: "Interrupt bits" } ], }, @@ -125,13 +123,9 @@ swaccess: "rw", hwaccess: "hro", fields: [ - { bits: "31:1", - name: "Preserve_Mask", - desc: "These bits must be constant to 0, not used with just one platform and one agent" - }, - { bits: "0", + { bits: "31:0", name: "intr", - desc: "Interrupt bit" + desc: "Interrupt bits" } ], }, diff --git a/hw/pulp/control_pulp_fpga.sv b/hw/pulp/control_pulp_fpga.sv index fb0e0c8..a90fe45 100644 --- a/hw/pulp/control_pulp_fpga.sv +++ b/hw/pulp/control_pulp_fpga.sv @@ -167,10 +167,11 @@ module control_pulp_fpga import pms_top_pkg::*; #( input logic ref_clk_i, input logic sys_clk_i, input logic rst_ni, - input logic bootsel_valid_i, - input logic [1:0] bootsel_i, - input logic fc_fetch_en_valid_i, - input logic fc_fetch_en_i, + + // input logic bootsel_valid_i, + // input logic [1:0] bootsel_i, + // input logic fc_fetch_en_valid_i, + // input logic fc_fetch_en_i, // jtag output logic jtag_tdo_o, @@ -183,6 +184,11 @@ module control_pulp_fpga import pms_top_pkg::*; #( output logic [1:0] wdt_alert_o, input logic wdt_alert_clear_i, + + //SCMI mailbox PS to PL intr signal + output logic out_completion_irq, + + // on-pmu internal peripherals as i/o pads (soc) // PMB PADS INOUT WIRES @@ -275,11 +281,22 @@ module control_pulp_fpga import pms_top_pkg::*; #( // UART PADS INOUT WIRES inout wire pad_uart1_pms0_rxd, - inout wire pad_uart1_pms0_txd + inout wire pad_uart1_pms0_txd, + + //BOOT SELECTION INOUT WIRES + inout wire pad_bootsel0, + inout wire pad_bootsel1, + inout wire pad_bootsel_valid, + inout wire pad_fc_fetch_en, + inout wire pad_fc_fetch_en_valid, + + // TEST INTERRUPT SIGNALS + inout wire pad_completion_irq, + inout wire pad_doorbell_irq ); // Doorbell interrupts - localparam int unsigned NUM_SCMI_CHANNELS = 64; + localparam int unsigned NUM_SCMI_CHANNELS = 1; logic scg_irq, scp_irq, scp_secure_irq; logic [60:0] mbox_irq; @@ -320,7 +337,7 @@ module control_pulp_fpga import pms_top_pkg::*; #( MaxSlvTrans: 8, FallThrough: 1'b1, LatencyMode: axi_pkg::NO_LATENCY, - PipelineStages: 0, + PipelineStages: 0, AxiIdWidthSlvPorts: AXI_ID_WIDTH_PS_MST, AxiIdUsedSlvPorts: AXI_ID_WIDTH_PS_MST, AxiAddrWidth: AXI_ADDR_WIDTH_PMS, // 32 but remapping is needed before connecting to PL slv @@ -595,6 +612,9 @@ module control_pulp_fpga import pms_top_pkg::*; #( // iw conv output port towards mailbox-scmi axi_req_pl_slv_t to_mailbox_req ; axi_resp_pl_slv_t to_mailbox_resp ; + logic s_completion_irq; + logic s_doorbell_irq; + axi_iw_converter #( .AxiSlvPortIdWidth ( AXI_ID_WIDTH_PS_MST+$clog2(XbarCfgPSMst.NoSlvPorts) ), @@ -636,10 +656,14 @@ module control_pulp_fpga import pms_top_pkg::*; #( .axi_mbox_req (to_mailbox_req ), .axi_mbox_rsp (to_mailbox_resp), - .irq_completion_o (/*TODO*/), // completion irq platform->agent - .irq_doorbell_o ({mbox_irq, scp_secure_irq, scp_irq, scg_irq}) // doorbell irq agent->platform - ); + // .irq_completion_o (/*TODO*/), // completion irq platform->agent + // .irq_doorbell_o ({mbox_irq, scp_secure_irq, scp_irq, scg_irq}) // doorbell irq agent->platform + .irq_completion_o (s_completion_irq), // completion irq platform->agent + .irq_doorbell_o (s_doorbell_irq) // doorbell irq agent->platform + ); + + assign out_completion_irq = s_completion_irq; // II. PL TO PS DIRECTION @@ -1561,6 +1585,11 @@ module control_pulp_fpga import pms_top_pkg::*; #( assign s_oe_i2c7_bmc_slv_scl = s_oe_i2c_slv_scl[0]; assign s_oe_i2c7_bmc_slv_sda = s_oe_i2c_slv_sda[0]; + // BOOT MODE SEL SIGNALS + logic [1:0]s_bootsel; + logic s_bootsel_valid; + logic s_fc_fetch_en; + logic s_fc_fetch_en_valid; // Instantiate pad_frame for chip-like inout signals pad_frame_fpga i_pad_frame ( @@ -1770,6 +1799,8 @@ module control_pulp_fpga import pms_top_pkg::*; #( .out_cpu_reset_out_l_i ( s_out_cpu_reset_out_l ), .out_cpu_socket_id_i ( s_out_cpu_socket_id ), .out_cpu_strap_i ( s_out_cpu_strap ), + .out_doorbell ( s_doorbell_irq ), + .out_completion ( s_completion_irq ), // EXT CHIP TP PADS .pad_pmb_vr1_pms0_sda ( pad_pmb_vr1_pms0_sda ), @@ -1851,6 +1882,19 @@ module control_pulp_fpga import pms_top_pkg::*; #( .pad_pms0_strap_2 ( pad_pms0_strap_2 ), .pad_pms0_strap_3 ( pad_pms0_strap_3 ), + .pad_bootsel0 ( pad_bootsel0 ), + .pad_bootsel1 ( pad_bootsel1 ), + .pad_bootsel_valid ( pad_bootsel_valid ), + .pad_fc_fetch_en ( pad_fc_fetch_en ), + .pad_fc_fetch_en_valid ( pad_fc_fetch_en_valid ), + .pad_completion_irq ( pad_completion_irq ), + .pad_doorbell_irq ( pad_doorbell_irq ), + + .bootsel_o ( s_bootsel ), + .bootsel_valid_o ( s_bootsel_valid ), + .fc_fetch_en_o ( s_fc_fetch_en ), + .fc_fetch_en_valid_o ( s_fc_fetch_en_valid ), + .pad_cfg_i ( s_pad_cfg ) ); @@ -2008,7 +2052,7 @@ module control_pulp_fpga import pms_top_pkg::*; #( .scg_irq_i (scg_irq ), .scp_irq_i (scp_irq ), .scp_secure_irq_i (scp_secure_irq ), - .mbox_irq_i ({11'h0, mbox_irq} ), + .mbox_irq_i ({11'h0, s_doorbell_irq} ), .mbox_secure_irq_i ('0 ), .oe_qspi_sdio_o ( s_oe_qspi_sdio ), @@ -2073,10 +2117,10 @@ module control_pulp_fpga import pms_top_pkg::*; #( .gpio_dir_o ( gpio_dir ), .gpio_cfg_o ( gpio_cfg ), - .bootsel_valid_i, - .bootsel_i ( {1'b0, bootsel_i} ), - .fc_fetch_en_valid_i, - .fc_fetch_en_i + .bootsel_valid_i (s_bootsel_valid ), + .bootsel_i ({1'b0, s_bootsel} ), + .fc_fetch_en_valid_i (s_fc_fetch_en_valid), + .fc_fetch_en_i (s_fc_fetch_en) ); endmodule // control_pulp_fpga diff --git a/hw/pulp/pms_top_fpga_behav.sv b/hw/pulp/pms_top_fpga_behav.sv index 48b956d..c38de28 100644 --- a/hw/pulp/pms_top_fpga_behav.sv +++ b/hw/pulp/pms_top_fpga_behav.sv @@ -209,7 +209,21 @@ module pms_top_fpga_behav ( // UART PADS INOUT WIRES inout wire pad_uart1_pms0_rxd, - inout wire pad_uart1_pms0_txd + inout wire pad_uart1_pms0_txd, + + // BOOT SELECTION INOUT WIRES + inout wire pad_bootsel0, + inout wire pad_bootsel1, + inout wire pad_bootsel_valid, + inout wire pad_fc_fetch_en, + inout wire pad_fc_fetch_en_valid, + + // MAILBOX COMPLETION INTERRUPT OUTPUT WIRE + output wire out_completion_irq, + + // TEST INTERRUPT SIGNALS + inout wire pad_completion_irq, + inout wire pad_doorbell_irq ); @@ -368,10 +382,10 @@ module pms_top_fpga_behav ( .ref_clk_i ( ref_clk ), .sys_clk_i ( sys_clk ), // unconnected for FPGA .rst_ni ( pad_reset ), //active_low - .bootsel_valid_i ( 1'b0 ), //0 -> memory-mapped reg - .bootsel_i ( 2'b0 ), //has no effect if bootsel_valid == 0 - .fc_fetch_en_valid_i ( 1'b0 ), //0 -> memory-mapped reg - .fc_fetch_en_i ( 1'b0 ), //has no effect if fetch_en_valid == 0 + // .bootsel_valid_i ( 1'b0 ), //0 -> memory-mapped reg + // .bootsel_i ( 2'b0 ), //has no effect if bootsel_valid == 0 + // .fc_fetch_en_valid_i ( 1'b0 ), //0 -> memory-mapped reg + // .fc_fetch_en_i ( 1'b0 ), //has no effect if fetch_en_valid == 0 .jtag_tdo_o, .jtag_tck_i, @@ -461,8 +475,15 @@ module pms_top_fpga_behav ( .pad_pms0_strap_0 ( pad_pms0_strap_0 ), .pad_pms0_strap_1 ( pad_pms0_strap_1 ), .pad_pms0_strap_2 ( pad_pms0_strap_2 ), - .pad_pms0_strap_3 ( pad_pms0_strap_3 ) - + .pad_pms0_strap_3 ( pad_pms0_strap_3 ), + .pad_bootsel0 ( pad_bootsel0 ), + .pad_bootsel1 ( pad_bootsel1 ), + .pad_bootsel_valid ( pad_bootsel_valid ), + .pad_fc_fetch_en ( pad_fc_fetch_en ), + .pad_fc_fetch_en_valid ( pad_fc_fetch_en_valid ), + .pad_completion_irq ( pad_completion_irq ), + .pad_doorbell_irq ( pad_doorbell_irq ), + .out_completion_irq ( out_completion_irq ) ); endmodule diff --git a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/Makefile b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/Makefile index 6a6320c..ed01687 100644 --- a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/Makefile +++ b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/Makefile @@ -16,9 +16,6 @@ # Alessandro Ottaviano -# Common code -#------------------------------------ - # ARE WE IN DEVELOPMENT ? ACTIVE_DEVELOP = 1 ### @@ -47,6 +44,10 @@ include $(FREERTOS_PROJ_ROOT)/default_flags.mk # rtos and pulp sources include $(FREERTOS_PROJ_ROOT)/default_srcs.mk +# ARE WE IN DEVELOPMENT ? +CPPFLAGS += -DDEBUG_ACTIVE +##### + # FreeRTOS Definitions: #CPPFLAGS += -DPCF_FREERTOS_TICK_RATE_HZ=1000 CPPFLAGS += -DDEFAULT_SYSTEM_CLOCK=20000000u @@ -61,8 +62,9 @@ CPPFLAGS += -DDEBUG_PRINTF CPPFLAGS += -UDUMP_ONLY CPPFLAGS += -DHRO_PRINTF +CPPFLAGS += -DALPHA_DEBUG # Uncomment to add debug option -#CPPFLAGS += -g +CPPFLAGS += -g CPPFLAGS += -DINITIAL_WAITING_ITERATIONS=1000 CPPFLAGS += -DINITIAL_WAITING_OVERFLOWS=4 @@ -89,8 +91,15 @@ CPPFLAGS += -DportasmHANDLE_INTERRUPT=vSystemIrqHandler CPPFLAGS += -I../../shared/include CPPFLAGS += $(addprefix -I$(USER_DIR)/, ".") +CFLAGS += -Og -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 -DFEATURE_CLUSTER=1 -D__PULP__=1 -DDEBUG #ADV SRCS += ./handler.S +ASFLAGS=-Os -g3 -march=rv32imac_zfinx_xcorev -mabi=ilp32 + # compile, simulation and analysis targets include $(FREERTOS_PROJ_ROOT)/default_targets.mk + + + # make RISCV="/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0-rc1" + # CFLAGS="" clean all diff --git a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/clic-mbox-ps-freertos.c b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/clic-mbox-ps-freertos.c index cfc5c18..78f3651 100644 --- a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/clic-mbox-ps-freertos.c +++ b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/clic-mbox-ps-freertos.c @@ -50,18 +50,28 @@ #include "target.h" #include "os.h" +void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName); void vApplicationMallocFailedHook(void); void vApplicationIdleHook(void); -void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName); void vApplicationTickHook(void); #define MBOX_START_ADDRESS 0xFFFF0000 -#define INTR_ID 32 +#define INTR_ID 35 #define CLIC_BASE_ADDR 0x1A200000 #define CLIC_END_ADDR 0x1A20FFFF +#define SUCCESS 0x0 + +#define FC_TIMER_BASE_ADDR 0x1B200400 +#define ARCHI_TIMER_SIZE 0x00000800 +#define FC_TIMER_ADDR (0x1A100000 0x0000B000) +#define DRAM_BASE_ADDR 0x20000000 + + +// volatile int *timestamp2 = (int *)(DRAM_BASE_ADDR + sizeof(int)); + #define assert(expression) \ do { \ if (!(expression)) { \ @@ -70,83 +80,552 @@ void vApplicationTickHook(void); } \ } while (0) +int first = 0; + +volatile uint32_t ft = 1; + +volatile int set_cnt = 0; + void clic_setup_mtvec(void); void clic_setup_mtvt(void); void (*clic_isr_hook[1])(void); -/* need void functions for isr table entries */ + +void exit_fail(void) +{ + exit(1); +} + void exit_success(void) { - puts("someone wrote to mailbox!"); + // printf("someone wrote to mailbox!\r\n"); callee_scmi_handler(); - exit(0); + exit(0); //---------------------------REMOVE THIS LINE IF IT IS NOT A SIMULATION } -void exit_fail(void) -{ - exit(1); + +void complete_msg(uint32_t header, uint32_t agent_id){ + // write the header back + writew(header, MBOX_START_ADDRESS + SCMI_MESSAGE_HEADER_C0_REG_OFFSET); + + // write channel status to free + writew(0x0, MBOX_START_ADDRESS + SCMI_CHANNEL_STATUS_C0_REG_OFFSET); + + // ring the completion + writew(agent_id, MBOX_START_ADDRESS + SCMI_COMPLETION_INTERRUPT_C0_REG_OFFSET); } + void callee_scmi_handler(void) -{ +{ + + // set_cnt++; + // printf("set_cnt: %d\r\n", set_cnt); + + + uint32_t agent_id = 0x0; uint32_t data = 0x0; - uint32_t address = 0x0; - uint32_t status = 0x0; uint32_t response = 0x0; uint32_t protocol_id = 0x0; uint32_t message_id = 0x0; + uint32_t payload0 = 0x0; + // uint32_t payload1 = 0x0; + // uint32_t payload2 = 0x0; - data = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET); - printf("payload: %x\n", data); + // read agent_id from doorbell + agent_id = readw(MBOX_START_ADDRESS + SCMI_DOORBELL_C0_REG_OFFSET); + + // clear doorbell TODO: doorbell must be cleared after reading the whole message not here + writew(0x0, MBOX_START_ADDRESS + SCMI_DOORBELL_C0_REG_OFFSET); + // read header data = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_HEADER_C0_REG_OFFSET); protocol_id = (data & 0x3fc00) >> 10; message_id = data & 0xff; - printf("protocol_id: %x\n", protocol_id); - printf("message_id: %x\n", message_id); - - if ((protocol_id == 0x10) && (message_id == 0x00)) { - status = 0; - response = 0x20000; - puts("protocol version asked and answered"); - } else { - status = -1; - response = 0; - puts("unknown message id or protocol id"); - } - // write the header back - writew(data, MBOX_START_ADDRESS + SCMI_MESSAGE_HEADER_C0_REG_OFFSET); - // write status - writew(status, MBOX_START_ADDRESS + SCMI_CHANNEL_STATUS_C0_REG_OFFSET); - // write payload for return values - writew(response, - MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET); - // channel free - writew(MBOX_START_ADDRESS + SCMI_DOORBELL_C0_REG_OFFSET, 0x1); - - // verification prints - data = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_HEADER_C0_REG_OFFSET); - // print header - printf("header: %x\n", data); - // print length - data = readw(MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); - printf("length: %x\n", data); - // print return payload - data = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET); - printf("return payload: %x\n", data); + // read payload + payload0 = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + // payload1 = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET); + // payload2 = readw(MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_2_C0_REG_OFFSET); + + // printf("prot_id: %u\r\n",protocol_id); + // printf("mess_id: %u\r\n",message_id); + // printf("payload0: %u\r\n",payload0); + // printf("payload1: %u\r\n",payload1); + // printf("payload2: %u\r\n",payload2); + // printf(" \r\n"); +////////////////////////////////////////////////////////////////////////////////////////// +// +// +// PROTOCOL 0x10 +// +// +////////////////////////////////////////////////////////////////////////////////////////// + + if(protocol_id == 0x10){ + if(message_id == 0x00){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x20000; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + complete_msg(data, agent_id); + }else if(message_id == 0x01){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x0101; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x03){ //vendor + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x41; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x04){ //subvendor + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x41; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x05){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x1; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x06){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + if (first == 0){ + first = 1; + + response = 0x3; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x141311; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*2, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + }else{ + response = 0x0; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x0; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*0, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + } + + complete_msg(data, agent_id); + }else if(message_id == 0x07){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x1; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x43; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*2, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + } +////////////////////////////////////////////////////////////////////////////////////////// +// +// +// PROTOCOL 0x13 +// +// +////////////////////////////////////////////////////////////////////////////////////////// + + }else if(protocol_id == 0x13){ + if(message_id == 0x00){ //protocol version + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x30000; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x01){ //protocol attributes + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x10001; //power consumption in mW, 1 perf domain + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x0; //upper statistics address + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 0x0; //lower statistics address + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + response = 0x0; //length + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 16); + + writew(8+4*4, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x03){ //performance domain attributes + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x40000000; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 1000; // minimum time between requests in usec + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 1; //sustained freq in kHz + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + response = 0x1; //performance level corresponding to sustained freq + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 16); + + response = 0x41; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 20); + + writew(8+4*5, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x04){ //performance describe levels + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x3; //n of returned perf levels + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 1;//performance level + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 1;//power cost + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + response = 500;//transition latency in usec + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 16); + + response = 2;//performance level + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 20); + + response = 2;//power cost + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 24); + + response = 500;//transition latency in usec + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 28); + + response = 3;//performance level + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 32); + + response = 3;//power cost + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 36); + + response = 500;//transition latency in usec + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 40); + + writew(8+4*10, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x07){ //perf level set + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + writew(8+4*0, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + ft = payload0; + + complete_msg(data, agent_id); + }else if(message_id == 0x08){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = ft; + + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + } +////////////////////////////////////////////////////////////////////////////////////////// +// +// +// PROTOCOL 0x14 +// +// +////////////////////////////////////////////////////////////////////////////////////////// + }else if(protocol_id == 0x14){ + if(message_id == 0x00){ //protocol version + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x20000; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x01){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x10001; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x03){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x01; //clock options, clock enable + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x41; //ascii clock name + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 1000; //clock latency to enable this clock in usec + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + writew(8+4*3, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x04){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x1001; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0; //lowest rate + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 1000; //highest rate + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + response = 1000; //step size + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 16); + + writew(8+4*4, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if(message_id == 0x06){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 1000; //lower 32 bit of physical rate in Hz + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0000; //upper 32 bit of physical rate in Hz + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*2, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + } +////////////////////////////////////////////////////////////////////////////////////////// +// +// +// PROTOCOL 0x11 +// +// +////////////////////////////////////////////////////////////////////////////////////////// + + }else if(protocol_id == 0x11){ + if(message_id == 0x00){ //protocol version + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x30000; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + }else if (message_id == 0x01){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x01; //n of power domains + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x00; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + response = 0x00; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 12); + + response = 0x00; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 16); + + writew(8+4*4, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + + }else if (message_id == 0x03){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x40000000; //asynchronus support + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + + response = 0x41; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*2, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + + }else if (message_id == 0x05){ + response = SUCCESS; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x00; //context is preserved, ON state + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 8); + + writew(8+4*1, + MBOX_START_ADDRESS + SCMI_LENGTH_C0_REG_OFFSET); + + complete_msg(data, agent_id); + } + }else{ + response = -1; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET); + + response = 0x11; + writew(response, + MBOX_START_ADDRESS + SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET + 4); + complete_msg(data, agent_id); + } } + int main(void) { - /* Init board hardware. */ system_init(); - - /* * global address map * CLIC_START_ADDR 32'h1A20_0000 @@ -165,7 +644,7 @@ int main(void) /* TODO: hook illegal insn handler to exit(1) */ - printf("test csr accesses\n"); + printf("test csr accesses\r\n"); uint32_t thresh = 0xffaa; uint32_t cmp = 0; csr_write(CSR_MINTTHRESH, thresh); @@ -175,17 +654,17 @@ int main(void) /* redirect vector table to our custom one */ - printf("set up vector table\n"); + printf("set up vector table\r\n"); clic_setup_mtvec(); clic_setup_mtvt(); /* enable selective hardware vectoring */ - printf("set shv\n"); + // printf("set shv\n"); writew((0x1 << CLIC_CLICINTATTR_SHV_BIT), CLIC_BASE_ADDR + CLIC_CLICINTATTR_REG_OFFSET(INTR_ID)); /* set trigger type to edge-triggered */ - printf("set trigger type: edge-triggered\n"); + // printf("set trigger type: edge-triggered\n"); writeb((0x1 << CLIC_CLICINTATTR_TRIG_OFFSET) | readw(CLIC_BASE_ADDR + CLIC_CLICINTATTR_REG_OFFSET(INTR_ID)), @@ -194,38 +673,39 @@ int main(void) /* set number of bits for level encoding: * nlbits */ - printf("set nlbits\n"); + // printf("set nlbits\n"); writeb((0x4 << CLIC_CLICCFG_NLBITS_OFFSET), CLIC_BASE_ADDR + CLIC_CLICCFG_REG_OFFSET); /* set interrupt level and priority*/ - printf("set interrupt priority and level\n"); + // printf("set interrupt priority and level\n"); writew(0xaa, CLIC_BASE_ADDR + CLIC_CLICINTCTL_REG_OFFSET(INTR_ID)); /* raise interrupt threshold to max and check that the interrupt doesn't * fire yet */ - printf("raise interrupt threshold to max (no interrupt should happen)\n"); + // printf("raise interrupt threshold to max (no interrupt should happen)\n"); csr_write(CSR_MINTTHRESH, 0xff); /* 0xff > 0xaa */ - clic_isr_hook[0] = exit_fail; /* if we take an interrupt then we failed - */ + clic_isr_hook[0] = exit_fail; /* if we take an interrupt then we failed */ - printf("enable interrupt\n"); + // printf("enable interrupt\n"); + // int *timestamp1 = (int *)(DRAM_BASE_ADDR); + /* enable interrupt globally */ irq_clint_global_enable(); + ft = 1; /* enable interrupt on clic */ writew(0x1, CLIC_BASE_ADDR + CLIC_CLICINTIE_REG_OFFSET(INTR_ID)); - printf("lower interrupt threshold (interrupt should happen)\n"); + // printf("lower interrupt threshold\n"); clic_isr_hook[0] = exit_success; csr_write(CSR_MINTTHRESH, 0); /* 0 < 0xaa */ - for (int i = 0; i < 100000; i++) - ; - - printf("Interrupt took too long\n"); + for(volatile int i=0; i < 1000000; i++); //---------------------------REMOVE THIS LINE IF IT IS NOT A SIMULATION + while(1); + return 1; } @@ -244,7 +724,7 @@ void vApplicationMallocFailedHook(void) free heap space that remains (although it does not provide information on how the remaining heap might be fragmented). */ taskDISABLE_INTERRUPTS(); - printf("error: application malloc failed\n\r"); + // printf("error: application malloc failed\n\r"); __asm volatile("ebreak"); for (;;) ; @@ -273,7 +753,7 @@ void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ taskDISABLE_INTERRUPTS(); - printf("error: stack overflow\n\r"); + // printf("error: stack overflow\n\r"); __asm volatile("ebreak"); for (;;) ; diff --git a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/handler.S b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/handler.S index beda764..9bb815b 100644 --- a/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/handler.S +++ b/sw/tests/control-pulp-tests/clic/clic-mbox-ext-freertos/handler.S @@ -137,5 +137,7 @@ __clic_vector_table: j __no_irq_handler j __no_irq_handler j __no_irq_handler - j __handle_clic_int - + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j __handle_clic_int \ No newline at end of file diff --git a/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/clic-mbox-freertos.c b/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/clic-mbox-freertos.c index 0d34ceb..d14f4e0 100644 --- a/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/clic-mbox-freertos.c +++ b/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/clic-mbox-freertos.c @@ -58,7 +58,7 @@ void vApplicationTickHook(void); #define MBOX_START_ADDRESS 0xFFFF0000 -#define INTR_ID 32 +#define INTR_ID 35 #define CLIC_BASE_ADDR 0x1A200000 #define CLIC_END_ADDR 0x1A20FFFF diff --git a/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/handler.S b/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/handler.S index beda764..9bb815b 100644 --- a/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/handler.S +++ b/sw/tests/control-pulp-tests/clic/clic-mbox-freertos/handler.S @@ -137,5 +137,7 @@ __clic_vector_table: j __no_irq_handler j __no_irq_handler j __no_irq_handler - j __handle_clic_int - + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j __handle_clic_int \ No newline at end of file diff --git a/sw/tests/control-pulp-tests/shared/include/scmi.h b/sw/tests/control-pulp-tests/shared/include/scmi.h index c9dd01f..28b4e63 100644 --- a/sw/tests/control-pulp-tests/shared/include/scmi.h +++ b/sw/tests/control-pulp-tests/shared/include/scmi.h @@ -70,10682 +70,142 @@ extern "C" { // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET 0x1c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C0_REG_OFFSET 0x20 -#define SCMI_DOORBELL_C0_INTR_BIT 0 -#define SCMI_DOORBELL_C0_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C0_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C0_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C0_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C0_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C0_REG_OFFSET 0x24 -#define SCMI_COMPLETION_INTERRUPT_C0_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C0_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C1_REG_OFFSET 0x28 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C1_REG_OFFSET 0x2c -#define SCMI_CHANNEL_STATUS_C1_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C1_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C1_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C1_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C1_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C1_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C1_REG_OFFSET 0x30 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C1_REG_OFFSET 0x34 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C1_REG_OFFSET 0x38 -#define SCMI_CHANNEL_FLAGS_C1_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C1_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C1_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C1_REG_OFFSET 0x3c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C1_REG_OFFSET 0x40 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C1_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C1_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C1_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C1_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C1_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C1_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C1_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C1_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C1_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C1_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C1_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C1_REG_OFFSET 0x44 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C1_REG_OFFSET 0x48 -#define SCMI_DOORBELL_C1_INTR_BIT 0 -#define SCMI_DOORBELL_C1_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C1_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C1_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C1_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C1_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C1_REG_OFFSET 0x4c -#define SCMI_COMPLETION_INTERRUPT_C1_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C1_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C2_REG_OFFSET 0x50 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C2_REG_OFFSET 0x54 -#define SCMI_CHANNEL_STATUS_C2_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C2_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C2_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C2_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C2_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C2_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C2_REG_OFFSET 0x58 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C2_REG_OFFSET 0x5c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C2_REG_OFFSET 0x60 -#define SCMI_CHANNEL_FLAGS_C2_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C2_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C2_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C2_REG_OFFSET 0x64 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C2_REG_OFFSET 0x68 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C2_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C2_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C2_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C2_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C2_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C2_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C2_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C2_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C2_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C2_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C2_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C2_REG_OFFSET 0x6c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C2_REG_OFFSET 0x70 -#define SCMI_DOORBELL_C2_INTR_BIT 0 -#define SCMI_DOORBELL_C2_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C2_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C2_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C2_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C2_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C2_REG_OFFSET 0x74 -#define SCMI_COMPLETION_INTERRUPT_C2_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C2_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C3_REG_OFFSET 0x78 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C3_REG_OFFSET 0x7c -#define SCMI_CHANNEL_STATUS_C3_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C3_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C3_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C3_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C3_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C3_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C3_REG_OFFSET 0x80 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C3_REG_OFFSET 0x84 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C3_REG_OFFSET 0x88 -#define SCMI_CHANNEL_FLAGS_C3_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C3_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C3_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C3_REG_OFFSET 0x8c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C3_REG_OFFSET 0x90 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C3_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C3_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C3_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C3_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C3_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C3_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C3_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C3_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C3_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C3_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C3_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C3_REG_OFFSET 0x94 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C3_REG_OFFSET 0x98 -#define SCMI_DOORBELL_C3_INTR_BIT 0 -#define SCMI_DOORBELL_C3_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C3_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C3_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C3_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C3_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C3_REG_OFFSET 0x9c -#define SCMI_COMPLETION_INTERRUPT_C3_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C3_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C4_REG_OFFSET 0xa0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C4_REG_OFFSET 0xa4 -#define SCMI_CHANNEL_STATUS_C4_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C4_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C4_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C4_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C4_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C4_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C4_REG_OFFSET 0xa8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C4_REG_OFFSET 0xac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C4_REG_OFFSET 0xb0 -#define SCMI_CHANNEL_FLAGS_C4_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C4_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C4_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C4_REG_OFFSET 0xb4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C4_REG_OFFSET 0xb8 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C4_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C4_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C4_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C4_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C4_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C4_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C4_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C4_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C4_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C4_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C4_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C4_REG_OFFSET 0xbc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C4_REG_OFFSET 0xc0 -#define SCMI_DOORBELL_C4_INTR_BIT 0 -#define SCMI_DOORBELL_C4_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C4_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C4_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C4_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C4_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C4_REG_OFFSET 0xc4 -#define SCMI_COMPLETION_INTERRUPT_C4_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C4_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C5_REG_OFFSET 0xc8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C5_REG_OFFSET 0xcc -#define SCMI_CHANNEL_STATUS_C5_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C5_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C5_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C5_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C5_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C5_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C5_REG_OFFSET 0xd0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C5_REG_OFFSET 0xd4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C5_REG_OFFSET 0xd8 -#define SCMI_CHANNEL_FLAGS_C5_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C5_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C5_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C5_REG_OFFSET 0xdc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C5_REG_OFFSET 0xe0 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C5_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C5_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C5_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C5_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C5_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C5_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C5_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C5_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C5_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C5_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C5_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C5_REG_OFFSET 0xe4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C5_REG_OFFSET 0xe8 -#define SCMI_DOORBELL_C5_INTR_BIT 0 -#define SCMI_DOORBELL_C5_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C5_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C5_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C5_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C5_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C5_REG_OFFSET 0xec -#define SCMI_COMPLETION_INTERRUPT_C5_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C5_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C6_REG_OFFSET 0xf0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C6_REG_OFFSET 0xf4 -#define SCMI_CHANNEL_STATUS_C6_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C6_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C6_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C6_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C6_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C6_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C6_REG_OFFSET 0xf8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C6_REG_OFFSET 0xfc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C6_REG_OFFSET 0x100 -#define SCMI_CHANNEL_FLAGS_C6_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C6_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C6_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C6_REG_OFFSET 0x104 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C6_REG_OFFSET 0x108 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C6_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C6_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C6_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C6_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C6_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C6_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C6_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C6_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C6_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C6_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C6_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C6_REG_OFFSET 0x10c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C6_REG_OFFSET 0x110 -#define SCMI_DOORBELL_C6_INTR_BIT 0 -#define SCMI_DOORBELL_C6_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C6_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C6_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C6_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C6_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C6_REG_OFFSET 0x114 -#define SCMI_COMPLETION_INTERRUPT_C6_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C6_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C7_REG_OFFSET 0x118 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C7_REG_OFFSET 0x11c -#define SCMI_CHANNEL_STATUS_C7_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C7_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C7_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C7_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C7_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C7_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C7_REG_OFFSET 0x120 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C7_REG_OFFSET 0x124 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C7_REG_OFFSET 0x128 -#define SCMI_CHANNEL_FLAGS_C7_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C7_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C7_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C7_REG_OFFSET 0x12c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C7_REG_OFFSET 0x130 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C7_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C7_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C7_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C7_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C7_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C7_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C7_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C7_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C7_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C7_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C7_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C7_REG_OFFSET 0x134 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C7_REG_OFFSET 0x138 -#define SCMI_DOORBELL_C7_INTR_BIT 0 -#define SCMI_DOORBELL_C7_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C7_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C7_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C7_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C7_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C7_REG_OFFSET 0x13c -#define SCMI_COMPLETION_INTERRUPT_C7_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C7_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C8_REG_OFFSET 0x140 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C8_REG_OFFSET 0x144 -#define SCMI_CHANNEL_STATUS_C8_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C8_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C8_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C8_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C8_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C8_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C8_REG_OFFSET 0x148 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C8_REG_OFFSET 0x14c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C8_REG_OFFSET 0x150 -#define SCMI_CHANNEL_FLAGS_C8_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C8_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C8_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C8_REG_OFFSET 0x154 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C8_REG_OFFSET 0x158 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C8_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C8_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C8_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C8_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C8_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C8_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C8_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C8_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C8_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C8_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C8_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C8_REG_OFFSET 0x15c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C8_REG_OFFSET 0x160 -#define SCMI_DOORBELL_C8_INTR_BIT 0 -#define SCMI_DOORBELL_C8_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C8_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C8_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C8_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C8_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C8_REG_OFFSET 0x164 -#define SCMI_COMPLETION_INTERRUPT_C8_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C8_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C9_REG_OFFSET 0x168 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C9_REG_OFFSET 0x16c -#define SCMI_CHANNEL_STATUS_C9_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C9_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C9_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C9_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C9_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C9_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C9_REG_OFFSET 0x170 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C9_REG_OFFSET 0x174 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C9_REG_OFFSET 0x178 -#define SCMI_CHANNEL_FLAGS_C9_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C9_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C9_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C9_REG_OFFSET 0x17c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C9_REG_OFFSET 0x180 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C9_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C9_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C9_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C9_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C9_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C9_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C9_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C9_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C9_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C9_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C9_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C9_REG_OFFSET 0x184 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C9_REG_OFFSET 0x188 -#define SCMI_DOORBELL_C9_INTR_BIT 0 -#define SCMI_DOORBELL_C9_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C9_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C9_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C9_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C9_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C9_REG_OFFSET 0x18c -#define SCMI_COMPLETION_INTERRUPT_C9_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C9_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C10_REG_OFFSET 0x190 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C10_REG_OFFSET 0x194 -#define SCMI_CHANNEL_STATUS_C10_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C10_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C10_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C10_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C10_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C10_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C10_REG_OFFSET 0x198 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C10_REG_OFFSET 0x19c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C10_REG_OFFSET 0x1a0 -#define SCMI_CHANNEL_FLAGS_C10_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C10_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C10_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C10_REG_OFFSET 0x1a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C10_REG_OFFSET 0x1a8 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C10_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C10_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C10_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C10_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C10_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C10_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C10_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C10_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C10_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C10_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C10_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C10_REG_OFFSET 0x1ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C10_REG_OFFSET 0x1b0 -#define SCMI_DOORBELL_C10_INTR_BIT 0 -#define SCMI_DOORBELL_C10_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C10_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C10_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C10_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C10_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C10_REG_OFFSET 0x1b4 -#define SCMI_COMPLETION_INTERRUPT_C10_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C10_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C11_REG_OFFSET 0x1b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C11_REG_OFFSET 0x1bc -#define SCMI_CHANNEL_STATUS_C11_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C11_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C11_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C11_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C11_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C11_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C11_REG_OFFSET 0x1c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C11_REG_OFFSET 0x1c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C11_REG_OFFSET 0x1c8 -#define SCMI_CHANNEL_FLAGS_C11_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C11_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C11_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C11_REG_OFFSET 0x1cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C11_REG_OFFSET 0x1d0 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C11_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C11_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C11_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C11_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C11_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C11_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C11_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C11_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C11_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C11_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C11_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C11_REG_OFFSET 0x1d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C11_REG_OFFSET 0x1d8 -#define SCMI_DOORBELL_C11_INTR_BIT 0 -#define SCMI_DOORBELL_C11_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C11_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C11_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C11_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C11_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C11_REG_OFFSET 0x1dc -#define SCMI_COMPLETION_INTERRUPT_C11_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C11_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C12_REG_OFFSET 0x1e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C12_REG_OFFSET 0x1e4 -#define SCMI_CHANNEL_STATUS_C12_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C12_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C12_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C12_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C12_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C12_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C12_REG_OFFSET 0x1e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C12_REG_OFFSET 0x1ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C12_REG_OFFSET 0x1f0 -#define SCMI_CHANNEL_FLAGS_C12_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C12_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C12_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C12_REG_OFFSET 0x1f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C12_REG_OFFSET 0x1f8 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C12_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C12_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C12_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C12_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C12_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C12_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C12_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C12_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C12_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C12_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C12_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C12_REG_OFFSET 0x1fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C12_REG_OFFSET 0x200 -#define SCMI_DOORBELL_C12_INTR_BIT 0 -#define SCMI_DOORBELL_C12_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C12_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C12_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C12_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C12_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C12_REG_OFFSET 0x204 -#define SCMI_COMPLETION_INTERRUPT_C12_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C12_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C13_REG_OFFSET 0x208 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C13_REG_OFFSET 0x20c -#define SCMI_CHANNEL_STATUS_C13_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C13_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C13_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C13_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C13_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C13_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C13_REG_OFFSET 0x210 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C13_REG_OFFSET 0x214 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C13_REG_OFFSET 0x218 -#define SCMI_CHANNEL_FLAGS_C13_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C13_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C13_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C13_REG_OFFSET 0x21c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C13_REG_OFFSET 0x220 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C13_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C13_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C13_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C13_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C13_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C13_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C13_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C13_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C13_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C13_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C13_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C13_REG_OFFSET 0x224 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C13_REG_OFFSET 0x228 -#define SCMI_DOORBELL_C13_INTR_BIT 0 -#define SCMI_DOORBELL_C13_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C13_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C13_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C13_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C13_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C13_REG_OFFSET 0x22c -#define SCMI_COMPLETION_INTERRUPT_C13_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C13_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C14_REG_OFFSET 0x230 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C14_REG_OFFSET 0x234 -#define SCMI_CHANNEL_STATUS_C14_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C14_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C14_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C14_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C14_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C14_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C14_REG_OFFSET 0x238 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C14_REG_OFFSET 0x23c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C14_REG_OFFSET 0x240 -#define SCMI_CHANNEL_FLAGS_C14_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C14_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C14_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C14_REG_OFFSET 0x244 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C14_REG_OFFSET 0x248 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C14_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C14_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C14_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C14_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C14_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C14_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C14_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C14_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C14_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C14_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C14_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C14_REG_OFFSET 0x24c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C14_REG_OFFSET 0x250 -#define SCMI_DOORBELL_C14_INTR_BIT 0 -#define SCMI_DOORBELL_C14_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C14_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C14_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C14_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C14_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C14_REG_OFFSET 0x254 -#define SCMI_COMPLETION_INTERRUPT_C14_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C14_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C15_REG_OFFSET 0x258 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C15_REG_OFFSET 0x25c -#define SCMI_CHANNEL_STATUS_C15_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C15_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C15_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C15_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C15_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C15_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C15_REG_OFFSET 0x260 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C15_REG_OFFSET 0x264 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C15_REG_OFFSET 0x268 -#define SCMI_CHANNEL_FLAGS_C15_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C15_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C15_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C15_REG_OFFSET 0x26c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C15_REG_OFFSET 0x270 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C15_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C15_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C15_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C15_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C15_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C15_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C15_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C15_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C15_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C15_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C15_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C15_REG_OFFSET 0x274 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C15_REG_OFFSET 0x278 -#define SCMI_DOORBELL_C15_INTR_BIT 0 -#define SCMI_DOORBELL_C15_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C15_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C15_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C15_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C15_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C15_REG_OFFSET 0x27c -#define SCMI_COMPLETION_INTERRUPT_C15_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C15_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C16_REG_OFFSET 0x280 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C16_REG_OFFSET 0x284 -#define SCMI_CHANNEL_STATUS_C16_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C16_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C16_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C16_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C16_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C16_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C16_REG_OFFSET 0x288 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C16_REG_OFFSET 0x28c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C16_REG_OFFSET 0x290 -#define SCMI_CHANNEL_FLAGS_C16_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C16_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C16_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C16_REG_OFFSET 0x294 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C16_REG_OFFSET 0x298 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C16_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C16_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C16_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C16_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C16_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C16_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C16_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C16_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C16_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C16_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C16_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C16_REG_OFFSET 0x29c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C16_REG_OFFSET 0x2a0 -#define SCMI_DOORBELL_C16_INTR_BIT 0 -#define SCMI_DOORBELL_C16_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C16_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C16_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C16_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C16_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C16_REG_OFFSET 0x2a4 -#define SCMI_COMPLETION_INTERRUPT_C16_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C16_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C17_REG_OFFSET 0x2a8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C17_REG_OFFSET 0x2ac -#define SCMI_CHANNEL_STATUS_C17_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C17_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C17_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C17_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C17_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C17_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C17_REG_OFFSET 0x2b0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C17_REG_OFFSET 0x2b4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C17_REG_OFFSET 0x2b8 -#define SCMI_CHANNEL_FLAGS_C17_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C17_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C17_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C17_REG_OFFSET 0x2bc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C17_REG_OFFSET 0x2c0 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C17_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C17_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C17_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C17_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C17_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C17_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C17_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C17_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C17_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C17_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C17_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C17_REG_OFFSET 0x2c4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C17_REG_OFFSET 0x2c8 -#define SCMI_DOORBELL_C17_INTR_BIT 0 -#define SCMI_DOORBELL_C17_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C17_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C17_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C17_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C17_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C17_REG_OFFSET 0x2cc -#define SCMI_COMPLETION_INTERRUPT_C17_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C17_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C18_REG_OFFSET 0x2d0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C18_REG_OFFSET 0x2d4 -#define SCMI_CHANNEL_STATUS_C18_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C18_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C18_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C18_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C18_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C18_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C18_REG_OFFSET 0x2d8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C18_REG_OFFSET 0x2dc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C18_REG_OFFSET 0x2e0 -#define SCMI_CHANNEL_FLAGS_C18_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C18_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C18_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C18_REG_OFFSET 0x2e4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C18_REG_OFFSET 0x2e8 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C18_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C18_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C18_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C18_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C18_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C18_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C18_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C18_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C18_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C18_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C18_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C18_REG_OFFSET 0x2ec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C18_REG_OFFSET 0x2f0 -#define SCMI_DOORBELL_C18_INTR_BIT 0 -#define SCMI_DOORBELL_C18_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C18_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C18_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C18_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C18_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C18_REG_OFFSET 0x2f4 -#define SCMI_COMPLETION_INTERRUPT_C18_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C18_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C19_REG_OFFSET 0x2f8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C19_REG_OFFSET 0x2fc -#define SCMI_CHANNEL_STATUS_C19_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C19_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C19_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C19_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C19_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C19_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C19_REG_OFFSET 0x300 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C19_REG_OFFSET 0x304 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C19_REG_OFFSET 0x308 -#define SCMI_CHANNEL_FLAGS_C19_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C19_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C19_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C19_REG_OFFSET 0x30c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C19_REG_OFFSET 0x310 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C19_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C19_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C19_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C19_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C19_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C19_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C19_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C19_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C19_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C19_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C19_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C19_REG_OFFSET 0x314 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C19_REG_OFFSET 0x318 -#define SCMI_DOORBELL_C19_INTR_BIT 0 -#define SCMI_DOORBELL_C19_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C19_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C19_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C19_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C19_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C19_REG_OFFSET 0x31c -#define SCMI_COMPLETION_INTERRUPT_C19_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C19_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C20_REG_OFFSET 0x320 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C20_REG_OFFSET 0x324 -#define SCMI_CHANNEL_STATUS_C20_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C20_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C20_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C20_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C20_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C20_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C20_REG_OFFSET 0x328 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C20_REG_OFFSET 0x32c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C20_REG_OFFSET 0x330 -#define SCMI_CHANNEL_FLAGS_C20_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C20_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C20_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C20_REG_OFFSET 0x334 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C20_REG_OFFSET 0x338 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C20_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C20_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C20_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C20_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C20_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C20_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C20_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C20_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C20_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C20_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C20_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C20_REG_OFFSET 0x33c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C20_REG_OFFSET 0x340 -#define SCMI_DOORBELL_C20_INTR_BIT 0 -#define SCMI_DOORBELL_C20_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C20_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C20_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C20_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C20_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C20_REG_OFFSET 0x344 -#define SCMI_COMPLETION_INTERRUPT_C20_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C20_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C21_REG_OFFSET 0x348 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C21_REG_OFFSET 0x34c -#define SCMI_CHANNEL_STATUS_C21_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C21_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C21_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C21_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C21_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C21_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C21_REG_OFFSET 0x350 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C21_REG_OFFSET 0x354 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C21_REG_OFFSET 0x358 -#define SCMI_CHANNEL_FLAGS_C21_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C21_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C21_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C21_REG_OFFSET 0x35c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C21_REG_OFFSET 0x360 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C21_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C21_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C21_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C21_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C21_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C21_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C21_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C21_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C21_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C21_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C21_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C21_REG_OFFSET 0x364 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C21_REG_OFFSET 0x368 -#define SCMI_DOORBELL_C21_INTR_BIT 0 -#define SCMI_DOORBELL_C21_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C21_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C21_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C21_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C21_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C21_REG_OFFSET 0x36c -#define SCMI_COMPLETION_INTERRUPT_C21_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C21_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C22_REG_OFFSET 0x370 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C22_REG_OFFSET 0x374 -#define SCMI_CHANNEL_STATUS_C22_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C22_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C22_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C22_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C22_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C22_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C22_REG_OFFSET 0x378 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C22_REG_OFFSET 0x37c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C22_REG_OFFSET 0x380 -#define SCMI_CHANNEL_FLAGS_C22_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C22_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C22_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C22_REG_OFFSET 0x384 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C22_REG_OFFSET 0x388 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C22_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C22_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C22_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C22_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C22_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C22_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C22_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C22_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C22_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C22_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C22_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C22_REG_OFFSET 0x38c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C22_REG_OFFSET 0x390 -#define SCMI_DOORBELL_C22_INTR_BIT 0 -#define SCMI_DOORBELL_C22_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C22_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C22_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C22_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C22_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C22_REG_OFFSET 0x394 -#define SCMI_COMPLETION_INTERRUPT_C22_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C22_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C23_REG_OFFSET 0x398 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C23_REG_OFFSET 0x39c -#define SCMI_CHANNEL_STATUS_C23_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C23_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C23_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C23_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C23_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C23_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C23_REG_OFFSET 0x3a0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C23_REG_OFFSET 0x3a4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C23_REG_OFFSET 0x3a8 -#define SCMI_CHANNEL_FLAGS_C23_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C23_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C23_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C23_REG_OFFSET 0x3ac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C23_REG_OFFSET 0x3b0 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C23_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C23_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C23_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C23_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C23_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C23_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C23_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C23_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C23_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C23_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C23_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C23_REG_OFFSET 0x3b4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C23_REG_OFFSET 0x3b8 -#define SCMI_DOORBELL_C23_INTR_BIT 0 -#define SCMI_DOORBELL_C23_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C23_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C23_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C23_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C23_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C23_REG_OFFSET 0x3bc -#define SCMI_COMPLETION_INTERRUPT_C23_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C23_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C24_REG_OFFSET 0x3c0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C24_REG_OFFSET 0x3c4 -#define SCMI_CHANNEL_STATUS_C24_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C24_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C24_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C24_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C24_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C24_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C24_REG_OFFSET 0x3c8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C24_REG_OFFSET 0x3cc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C24_REG_OFFSET 0x3d0 -#define SCMI_CHANNEL_FLAGS_C24_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C24_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C24_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C24_REG_OFFSET 0x3d4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C24_REG_OFFSET 0x3d8 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C24_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C24_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C24_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C24_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C24_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C24_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C24_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C24_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C24_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C24_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C24_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C24_REG_OFFSET 0x3dc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C24_REG_OFFSET 0x3e0 -#define SCMI_DOORBELL_C24_INTR_BIT 0 -#define SCMI_DOORBELL_C24_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C24_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C24_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C24_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C24_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C24_REG_OFFSET 0x3e4 -#define SCMI_COMPLETION_INTERRUPT_C24_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C24_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C25_REG_OFFSET 0x3e8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C25_REG_OFFSET 0x3ec -#define SCMI_CHANNEL_STATUS_C25_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C25_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C25_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C25_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C25_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C25_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C25_REG_OFFSET 0x3f0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C25_REG_OFFSET 0x3f4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C25_REG_OFFSET 0x3f8 -#define SCMI_CHANNEL_FLAGS_C25_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C25_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C25_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C25_REG_OFFSET 0x3fc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C25_REG_OFFSET 0x400 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C25_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C25_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C25_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C25_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C25_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C25_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C25_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C25_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C25_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C25_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C25_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C25_REG_OFFSET 0x404 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C25_REG_OFFSET 0x408 -#define SCMI_DOORBELL_C25_INTR_BIT 0 -#define SCMI_DOORBELL_C25_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C25_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C25_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C25_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C25_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C25_REG_OFFSET 0x40c -#define SCMI_COMPLETION_INTERRUPT_C25_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C25_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C26_REG_OFFSET 0x410 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C26_REG_OFFSET 0x414 -#define SCMI_CHANNEL_STATUS_C26_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C26_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C26_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C26_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C26_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C26_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C26_REG_OFFSET 0x418 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C26_REG_OFFSET 0x41c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C26_REG_OFFSET 0x420 -#define SCMI_CHANNEL_FLAGS_C26_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C26_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C26_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C26_REG_OFFSET 0x424 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C26_REG_OFFSET 0x428 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C26_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C26_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C26_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C26_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C26_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C26_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C26_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C26_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C26_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C26_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C26_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C26_REG_OFFSET 0x42c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C26_REG_OFFSET 0x430 -#define SCMI_DOORBELL_C26_INTR_BIT 0 -#define SCMI_DOORBELL_C26_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C26_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C26_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C26_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C26_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C26_REG_OFFSET 0x434 -#define SCMI_COMPLETION_INTERRUPT_C26_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C26_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C27_REG_OFFSET 0x438 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C27_REG_OFFSET 0x43c -#define SCMI_CHANNEL_STATUS_C27_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C27_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C27_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C27_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C27_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C27_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C27_REG_OFFSET 0x440 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C27_REG_OFFSET 0x444 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C27_REG_OFFSET 0x448 -#define SCMI_CHANNEL_FLAGS_C27_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C27_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C27_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C27_REG_OFFSET 0x44c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C27_REG_OFFSET 0x450 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C27_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C27_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C27_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C27_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C27_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C27_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C27_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C27_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C27_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C27_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C27_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C27_REG_OFFSET 0x454 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C27_REG_OFFSET 0x458 -#define SCMI_DOORBELL_C27_INTR_BIT 0 -#define SCMI_DOORBELL_C27_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C27_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C27_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C27_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C27_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C27_REG_OFFSET 0x45c -#define SCMI_COMPLETION_INTERRUPT_C27_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C27_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C28_REG_OFFSET 0x460 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C28_REG_OFFSET 0x464 -#define SCMI_CHANNEL_STATUS_C28_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C28_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C28_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C28_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C28_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C28_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C28_REG_OFFSET 0x468 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C28_REG_OFFSET 0x46c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C28_REG_OFFSET 0x470 -#define SCMI_CHANNEL_FLAGS_C28_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C28_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C28_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C28_REG_OFFSET 0x474 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C28_REG_OFFSET 0x478 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C28_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C28_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C28_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C28_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C28_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C28_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C28_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C28_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C28_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C28_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C28_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C28_REG_OFFSET 0x47c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C28_REG_OFFSET 0x480 -#define SCMI_DOORBELL_C28_INTR_BIT 0 -#define SCMI_DOORBELL_C28_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C28_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C28_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C28_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C28_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C28_REG_OFFSET 0x484 -#define SCMI_COMPLETION_INTERRUPT_C28_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C28_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C29_REG_OFFSET 0x488 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C29_REG_OFFSET 0x48c -#define SCMI_CHANNEL_STATUS_C29_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C29_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C29_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C29_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C29_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C29_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C29_REG_OFFSET 0x490 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C29_REG_OFFSET 0x494 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C29_REG_OFFSET 0x498 -#define SCMI_CHANNEL_FLAGS_C29_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C29_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C29_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C29_REG_OFFSET 0x49c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C29_REG_OFFSET 0x4a0 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C29_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C29_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C29_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C29_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C29_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C29_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C29_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C29_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C29_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C29_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C29_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C29_REG_OFFSET 0x4a4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C29_REG_OFFSET 0x4a8 -#define SCMI_DOORBELL_C29_INTR_BIT 0 -#define SCMI_DOORBELL_C29_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C29_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C29_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C29_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C29_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C29_REG_OFFSET 0x4ac -#define SCMI_COMPLETION_INTERRUPT_C29_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C29_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C30_REG_OFFSET 0x4b0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C30_REG_OFFSET 0x4b4 -#define SCMI_CHANNEL_STATUS_C30_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C30_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C30_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C30_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C30_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C30_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C30_REG_OFFSET 0x4b8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C30_REG_OFFSET 0x4bc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C30_REG_OFFSET 0x4c0 -#define SCMI_CHANNEL_FLAGS_C30_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C30_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C30_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C30_REG_OFFSET 0x4c4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C30_REG_OFFSET 0x4c8 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C30_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C30_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C30_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C30_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C30_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C30_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C30_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C30_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C30_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C30_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C30_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C30_REG_OFFSET 0x4cc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C30_REG_OFFSET 0x4d0 -#define SCMI_DOORBELL_C30_INTR_BIT 0 -#define SCMI_DOORBELL_C30_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C30_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C30_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C30_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C30_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C30_REG_OFFSET 0x4d4 -#define SCMI_COMPLETION_INTERRUPT_C30_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C30_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C31_REG_OFFSET 0x4d8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C31_REG_OFFSET 0x4dc -#define SCMI_CHANNEL_STATUS_C31_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C31_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C31_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C31_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C31_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C31_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C31_REG_OFFSET 0x4e0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C31_REG_OFFSET 0x4e4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C31_REG_OFFSET 0x4e8 -#define SCMI_CHANNEL_FLAGS_C31_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C31_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C31_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C31_REG_OFFSET 0x4ec - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C31_REG_OFFSET 0x4f0 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C31_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C31_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C31_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C31_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C31_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C31_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C31_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C31_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C31_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C31_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C31_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C31_REG_OFFSET 0x4f4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C31_REG_OFFSET 0x4f8 -#define SCMI_DOORBELL_C31_INTR_BIT 0 -#define SCMI_DOORBELL_C31_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C31_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C31_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C31_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C31_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C31_REG_OFFSET 0x4fc -#define SCMI_COMPLETION_INTERRUPT_C31_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C31_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C32_REG_OFFSET 0x500 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C32_REG_OFFSET 0x504 -#define SCMI_CHANNEL_STATUS_C32_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C32_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C32_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C32_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C32_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C32_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C32_REG_OFFSET 0x508 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C32_REG_OFFSET 0x50c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C32_REG_OFFSET 0x510 -#define SCMI_CHANNEL_FLAGS_C32_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C32_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C32_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C32_REG_OFFSET 0x514 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C32_REG_OFFSET 0x518 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C32_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C32_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C32_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C32_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C32_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C32_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C32_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C32_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C32_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C32_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C32_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C32_REG_OFFSET 0x51c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C32_REG_OFFSET 0x520 -#define SCMI_DOORBELL_C32_INTR_BIT 0 -#define SCMI_DOORBELL_C32_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C32_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C32_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C32_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C32_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C32_REG_OFFSET 0x524 -#define SCMI_COMPLETION_INTERRUPT_C32_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C32_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C33_REG_OFFSET 0x528 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C33_REG_OFFSET 0x52c -#define SCMI_CHANNEL_STATUS_C33_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C33_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C33_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C33_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C33_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C33_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C33_REG_OFFSET 0x530 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C33_REG_OFFSET 0x534 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C33_REG_OFFSET 0x538 -#define SCMI_CHANNEL_FLAGS_C33_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C33_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C33_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C33_REG_OFFSET 0x53c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C33_REG_OFFSET 0x540 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C33_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C33_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C33_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C33_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C33_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C33_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C33_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C33_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C33_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C33_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C33_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C33_REG_OFFSET 0x544 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C33_REG_OFFSET 0x548 -#define SCMI_DOORBELL_C33_INTR_BIT 0 -#define SCMI_DOORBELL_C33_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C33_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C33_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C33_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C33_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C33_REG_OFFSET 0x54c -#define SCMI_COMPLETION_INTERRUPT_C33_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C33_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C34_REG_OFFSET 0x550 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C34_REG_OFFSET 0x554 -#define SCMI_CHANNEL_STATUS_C34_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C34_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C34_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C34_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C34_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C34_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C34_REG_OFFSET 0x558 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C34_REG_OFFSET 0x55c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C34_REG_OFFSET 0x560 -#define SCMI_CHANNEL_FLAGS_C34_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C34_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C34_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C34_REG_OFFSET 0x564 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C34_REG_OFFSET 0x568 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C34_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C34_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C34_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C34_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C34_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C34_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C34_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C34_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C34_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C34_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C34_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C34_REG_OFFSET 0x56c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C34_REG_OFFSET 0x570 -#define SCMI_DOORBELL_C34_INTR_BIT 0 -#define SCMI_DOORBELL_C34_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C34_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C34_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C34_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C34_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C34_REG_OFFSET 0x574 -#define SCMI_COMPLETION_INTERRUPT_C34_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C34_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C35_REG_OFFSET 0x578 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C35_REG_OFFSET 0x57c -#define SCMI_CHANNEL_STATUS_C35_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C35_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C35_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C35_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C35_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C35_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C35_REG_OFFSET 0x580 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C35_REG_OFFSET 0x584 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C35_REG_OFFSET 0x588 -#define SCMI_CHANNEL_FLAGS_C35_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C35_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C35_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C35_REG_OFFSET 0x58c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C35_REG_OFFSET 0x590 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C35_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C35_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C35_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C35_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C35_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C35_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C35_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C35_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C35_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C35_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C35_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C35_REG_OFFSET 0x594 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C35_REG_OFFSET 0x598 -#define SCMI_DOORBELL_C35_INTR_BIT 0 -#define SCMI_DOORBELL_C35_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C35_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C35_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C35_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C35_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C35_REG_OFFSET 0x59c -#define SCMI_COMPLETION_INTERRUPT_C35_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C35_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C36_REG_OFFSET 0x5a0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C36_REG_OFFSET 0x5a4 -#define SCMI_CHANNEL_STATUS_C36_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C36_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C36_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C36_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C36_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C36_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C36_REG_OFFSET 0x5a8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C36_REG_OFFSET 0x5ac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C36_REG_OFFSET 0x5b0 -#define SCMI_CHANNEL_FLAGS_C36_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C36_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C36_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C36_REG_OFFSET 0x5b4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C36_REG_OFFSET 0x5b8 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C36_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C36_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C36_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C36_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C36_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C36_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C36_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C36_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C36_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C36_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C36_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C36_REG_OFFSET 0x5bc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C36_REG_OFFSET 0x5c0 -#define SCMI_DOORBELL_C36_INTR_BIT 0 -#define SCMI_DOORBELL_C36_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C36_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C36_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C36_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C36_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C36_REG_OFFSET 0x5c4 -#define SCMI_COMPLETION_INTERRUPT_C36_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C36_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C37_REG_OFFSET 0x5c8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C37_REG_OFFSET 0x5cc -#define SCMI_CHANNEL_STATUS_C37_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C37_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C37_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C37_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C37_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C37_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C37_REG_OFFSET 0x5d0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C37_REG_OFFSET 0x5d4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C37_REG_OFFSET 0x5d8 -#define SCMI_CHANNEL_FLAGS_C37_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C37_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C37_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C37_REG_OFFSET 0x5dc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C37_REG_OFFSET 0x5e0 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C37_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C37_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C37_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C37_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C37_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C37_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C37_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C37_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C37_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C37_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C37_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C37_REG_OFFSET 0x5e4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C37_REG_OFFSET 0x5e8 -#define SCMI_DOORBELL_C37_INTR_BIT 0 -#define SCMI_DOORBELL_C37_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C37_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C37_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C37_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C37_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C37_REG_OFFSET 0x5ec -#define SCMI_COMPLETION_INTERRUPT_C37_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C37_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C38_REG_OFFSET 0x5f0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C38_REG_OFFSET 0x5f4 -#define SCMI_CHANNEL_STATUS_C38_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C38_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C38_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C38_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C38_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C38_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C38_REG_OFFSET 0x5f8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C38_REG_OFFSET 0x5fc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C38_REG_OFFSET 0x600 -#define SCMI_CHANNEL_FLAGS_C38_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C38_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C38_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C38_REG_OFFSET 0x604 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C38_REG_OFFSET 0x608 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C38_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C38_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C38_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C38_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C38_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C38_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C38_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C38_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C38_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C38_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C38_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C38_REG_OFFSET 0x60c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C38_REG_OFFSET 0x610 -#define SCMI_DOORBELL_C38_INTR_BIT 0 -#define SCMI_DOORBELL_C38_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C38_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C38_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C38_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C38_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C38_REG_OFFSET 0x614 -#define SCMI_COMPLETION_INTERRUPT_C38_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C38_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C39_REG_OFFSET 0x618 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C39_REG_OFFSET 0x61c -#define SCMI_CHANNEL_STATUS_C39_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C39_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C39_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C39_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C39_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C39_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C39_REG_OFFSET 0x620 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C39_REG_OFFSET 0x624 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C39_REG_OFFSET 0x628 -#define SCMI_CHANNEL_FLAGS_C39_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C39_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C39_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C39_REG_OFFSET 0x62c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C39_REG_OFFSET 0x630 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C39_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C39_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C39_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C39_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C39_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C39_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C39_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C39_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C39_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C39_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C39_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C39_REG_OFFSET 0x634 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C39_REG_OFFSET 0x638 -#define SCMI_DOORBELL_C39_INTR_BIT 0 -#define SCMI_DOORBELL_C39_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C39_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C39_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C39_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C39_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C39_REG_OFFSET 0x63c -#define SCMI_COMPLETION_INTERRUPT_C39_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C39_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C40_REG_OFFSET 0x640 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C40_REG_OFFSET 0x644 -#define SCMI_CHANNEL_STATUS_C40_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C40_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C40_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C40_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C40_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C40_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C40_REG_OFFSET 0x648 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C40_REG_OFFSET 0x64c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C40_REG_OFFSET 0x650 -#define SCMI_CHANNEL_FLAGS_C40_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C40_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C40_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C40_REG_OFFSET 0x654 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C40_REG_OFFSET 0x658 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C40_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C40_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C40_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C40_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C40_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C40_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C40_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C40_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C40_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C40_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C40_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C40_REG_OFFSET 0x65c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C40_REG_OFFSET 0x660 -#define SCMI_DOORBELL_C40_INTR_BIT 0 -#define SCMI_DOORBELL_C40_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C40_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C40_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C40_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C40_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C40_REG_OFFSET 0x664 -#define SCMI_COMPLETION_INTERRUPT_C40_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C40_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C41_REG_OFFSET 0x668 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C41_REG_OFFSET 0x66c -#define SCMI_CHANNEL_STATUS_C41_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C41_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C41_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C41_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C41_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C41_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C41_REG_OFFSET 0x670 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C41_REG_OFFSET 0x674 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C41_REG_OFFSET 0x678 -#define SCMI_CHANNEL_FLAGS_C41_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C41_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C41_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C41_REG_OFFSET 0x67c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C41_REG_OFFSET 0x680 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C41_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C41_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C41_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C41_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C41_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C41_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C41_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C41_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C41_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C41_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C41_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C41_REG_OFFSET 0x684 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C41_REG_OFFSET 0x688 -#define SCMI_DOORBELL_C41_INTR_BIT 0 -#define SCMI_DOORBELL_C41_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C41_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C41_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C41_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C41_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C41_REG_OFFSET 0x68c -#define SCMI_COMPLETION_INTERRUPT_C41_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C41_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C42_REG_OFFSET 0x690 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C42_REG_OFFSET 0x694 -#define SCMI_CHANNEL_STATUS_C42_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C42_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C42_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C42_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C42_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C42_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C42_REG_OFFSET 0x698 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C42_REG_OFFSET 0x69c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C42_REG_OFFSET 0x6a0 -#define SCMI_CHANNEL_FLAGS_C42_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C42_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C42_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C42_REG_OFFSET 0x6a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C42_REG_OFFSET 0x6a8 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C42_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C42_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C42_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C42_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C42_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C42_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C42_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C42_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C42_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C42_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C42_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C42_REG_OFFSET 0x6ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C42_REG_OFFSET 0x6b0 -#define SCMI_DOORBELL_C42_INTR_BIT 0 -#define SCMI_DOORBELL_C42_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C42_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C42_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C42_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C42_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C42_REG_OFFSET 0x6b4 -#define SCMI_COMPLETION_INTERRUPT_C42_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C42_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C43_REG_OFFSET 0x6b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C43_REG_OFFSET 0x6bc -#define SCMI_CHANNEL_STATUS_C43_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C43_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C43_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C43_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C43_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C43_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C43_REG_OFFSET 0x6c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C43_REG_OFFSET 0x6c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C43_REG_OFFSET 0x6c8 -#define SCMI_CHANNEL_FLAGS_C43_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C43_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C43_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C43_REG_OFFSET 0x6cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C43_REG_OFFSET 0x6d0 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C43_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C43_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C43_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C43_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C43_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C43_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C43_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C43_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C43_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C43_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C43_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C43_REG_OFFSET 0x6d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C43_REG_OFFSET 0x6d8 -#define SCMI_DOORBELL_C43_INTR_BIT 0 -#define SCMI_DOORBELL_C43_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C43_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C43_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C43_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C43_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C43_REG_OFFSET 0x6dc -#define SCMI_COMPLETION_INTERRUPT_C43_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C43_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C44_REG_OFFSET 0x6e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C44_REG_OFFSET 0x6e4 -#define SCMI_CHANNEL_STATUS_C44_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C44_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C44_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C44_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C44_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C44_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C44_REG_OFFSET 0x6e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C44_REG_OFFSET 0x6ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C44_REG_OFFSET 0x6f0 -#define SCMI_CHANNEL_FLAGS_C44_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C44_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C44_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C44_REG_OFFSET 0x6f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C44_REG_OFFSET 0x6f8 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C44_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C44_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C44_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C44_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C44_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C44_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C44_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C44_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C44_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C44_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C44_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C44_REG_OFFSET 0x6fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C44_REG_OFFSET 0x700 -#define SCMI_DOORBELL_C44_INTR_BIT 0 -#define SCMI_DOORBELL_C44_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C44_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C44_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C44_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C44_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C44_REG_OFFSET 0x704 -#define SCMI_COMPLETION_INTERRUPT_C44_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C44_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C45_REG_OFFSET 0x708 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C45_REG_OFFSET 0x70c -#define SCMI_CHANNEL_STATUS_C45_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C45_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C45_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C45_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C45_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C45_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C45_REG_OFFSET 0x710 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C45_REG_OFFSET 0x714 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C45_REG_OFFSET 0x718 -#define SCMI_CHANNEL_FLAGS_C45_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C45_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C45_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C45_REG_OFFSET 0x71c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C45_REG_OFFSET 0x720 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C45_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C45_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C45_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C45_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C45_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C45_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C45_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C45_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C45_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C45_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C45_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C45_REG_OFFSET 0x724 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C45_REG_OFFSET 0x728 -#define SCMI_DOORBELL_C45_INTR_BIT 0 -#define SCMI_DOORBELL_C45_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C45_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C45_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C45_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C45_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C45_REG_OFFSET 0x72c -#define SCMI_COMPLETION_INTERRUPT_C45_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C45_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C46_REG_OFFSET 0x730 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C46_REG_OFFSET 0x734 -#define SCMI_CHANNEL_STATUS_C46_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C46_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C46_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C46_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C46_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C46_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C46_REG_OFFSET 0x738 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C46_REG_OFFSET 0x73c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C46_REG_OFFSET 0x740 -#define SCMI_CHANNEL_FLAGS_C46_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C46_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C46_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C46_REG_OFFSET 0x744 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C46_REG_OFFSET 0x748 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C46_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C46_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C46_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C46_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C46_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C46_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C46_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C46_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C46_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C46_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C46_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C46_REG_OFFSET 0x74c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C46_REG_OFFSET 0x750 -#define SCMI_DOORBELL_C46_INTR_BIT 0 -#define SCMI_DOORBELL_C46_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C46_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C46_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C46_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C46_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C46_REG_OFFSET 0x754 -#define SCMI_COMPLETION_INTERRUPT_C46_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C46_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C47_REG_OFFSET 0x758 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C47_REG_OFFSET 0x75c -#define SCMI_CHANNEL_STATUS_C47_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C47_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C47_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C47_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C47_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C47_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C47_REG_OFFSET 0x760 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C47_REG_OFFSET 0x764 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C47_REG_OFFSET 0x768 -#define SCMI_CHANNEL_FLAGS_C47_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C47_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C47_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C47_REG_OFFSET 0x76c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C47_REG_OFFSET 0x770 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C47_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C47_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C47_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C47_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C47_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C47_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C47_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C47_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C47_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C47_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C47_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C47_REG_OFFSET 0x774 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C47_REG_OFFSET 0x778 -#define SCMI_DOORBELL_C47_INTR_BIT 0 -#define SCMI_DOORBELL_C47_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C47_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C47_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C47_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C47_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C47_REG_OFFSET 0x77c -#define SCMI_COMPLETION_INTERRUPT_C47_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C47_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C48_REG_OFFSET 0x780 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C48_REG_OFFSET 0x784 -#define SCMI_CHANNEL_STATUS_C48_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C48_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C48_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C48_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C48_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C48_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C48_REG_OFFSET 0x788 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C48_REG_OFFSET 0x78c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C48_REG_OFFSET 0x790 -#define SCMI_CHANNEL_FLAGS_C48_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C48_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C48_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C48_REG_OFFSET 0x794 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C48_REG_OFFSET 0x798 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C48_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C48_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C48_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C48_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C48_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C48_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C48_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C48_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C48_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C48_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C48_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C48_REG_OFFSET 0x79c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C48_REG_OFFSET 0x7a0 -#define SCMI_DOORBELL_C48_INTR_BIT 0 -#define SCMI_DOORBELL_C48_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C48_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C48_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C48_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C48_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C48_REG_OFFSET 0x7a4 -#define SCMI_COMPLETION_INTERRUPT_C48_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C48_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C49_REG_OFFSET 0x7a8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C49_REG_OFFSET 0x7ac -#define SCMI_CHANNEL_STATUS_C49_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C49_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C49_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C49_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C49_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C49_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C49_REG_OFFSET 0x7b0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C49_REG_OFFSET 0x7b4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C49_REG_OFFSET 0x7b8 -#define SCMI_CHANNEL_FLAGS_C49_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C49_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C49_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C49_REG_OFFSET 0x7bc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C49_REG_OFFSET 0x7c0 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C49_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C49_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C49_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C49_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C49_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C49_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C49_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C49_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C49_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C49_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C49_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C49_REG_OFFSET 0x7c4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C49_REG_OFFSET 0x7c8 -#define SCMI_DOORBELL_C49_INTR_BIT 0 -#define SCMI_DOORBELL_C49_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C49_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C49_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C49_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C49_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C49_REG_OFFSET 0x7cc -#define SCMI_COMPLETION_INTERRUPT_C49_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C49_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C50_REG_OFFSET 0x7d0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C50_REG_OFFSET 0x7d4 -#define SCMI_CHANNEL_STATUS_C50_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C50_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C50_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C50_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C50_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C50_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C50_REG_OFFSET 0x7d8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C50_REG_OFFSET 0x7dc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C50_REG_OFFSET 0x7e0 -#define SCMI_CHANNEL_FLAGS_C50_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C50_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C50_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C50_REG_OFFSET 0x7e4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C50_REG_OFFSET 0x7e8 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C50_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C50_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C50_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C50_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C50_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C50_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C50_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C50_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C50_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C50_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C50_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C50_REG_OFFSET 0x7ec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C50_REG_OFFSET 0x7f0 -#define SCMI_DOORBELL_C50_INTR_BIT 0 -#define SCMI_DOORBELL_C50_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C50_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C50_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C50_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C50_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C50_REG_OFFSET 0x7f4 -#define SCMI_COMPLETION_INTERRUPT_C50_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C50_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C51_REG_OFFSET 0x7f8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C51_REG_OFFSET 0x7fc -#define SCMI_CHANNEL_STATUS_C51_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C51_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C51_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C51_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C51_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C51_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C51_REG_OFFSET 0x800 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C51_REG_OFFSET 0x804 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C51_REG_OFFSET 0x808 -#define SCMI_CHANNEL_FLAGS_C51_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C51_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C51_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C51_REG_OFFSET 0x80c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C51_REG_OFFSET 0x810 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C51_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C51_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C51_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C51_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C51_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C51_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C51_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C51_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C51_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C51_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C51_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C51_REG_OFFSET 0x814 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C51_REG_OFFSET 0x818 -#define SCMI_DOORBELL_C51_INTR_BIT 0 -#define SCMI_DOORBELL_C51_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C51_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C51_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C51_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C51_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C51_REG_OFFSET 0x81c -#define SCMI_COMPLETION_INTERRUPT_C51_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C51_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C52_REG_OFFSET 0x820 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C52_REG_OFFSET 0x824 -#define SCMI_CHANNEL_STATUS_C52_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C52_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C52_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C52_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C52_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C52_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C52_REG_OFFSET 0x828 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C52_REG_OFFSET 0x82c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C52_REG_OFFSET 0x830 -#define SCMI_CHANNEL_FLAGS_C52_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C52_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C52_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C52_REG_OFFSET 0x834 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C52_REG_OFFSET 0x838 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C52_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C52_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C52_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C52_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C52_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C52_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C52_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C52_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C52_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C52_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C52_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C52_REG_OFFSET 0x83c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C52_REG_OFFSET 0x840 -#define SCMI_DOORBELL_C52_INTR_BIT 0 -#define SCMI_DOORBELL_C52_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C52_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C52_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C52_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C52_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C52_REG_OFFSET 0x844 -#define SCMI_COMPLETION_INTERRUPT_C52_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C52_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C53_REG_OFFSET 0x848 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C53_REG_OFFSET 0x84c -#define SCMI_CHANNEL_STATUS_C53_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C53_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C53_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C53_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C53_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C53_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C53_REG_OFFSET 0x850 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C53_REG_OFFSET 0x854 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C53_REG_OFFSET 0x858 -#define SCMI_CHANNEL_FLAGS_C53_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C53_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C53_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C53_REG_OFFSET 0x85c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C53_REG_OFFSET 0x860 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C53_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C53_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C53_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C53_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C53_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C53_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C53_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C53_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C53_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C53_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C53_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C53_REG_OFFSET 0x864 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C53_REG_OFFSET 0x868 -#define SCMI_DOORBELL_C53_INTR_BIT 0 -#define SCMI_DOORBELL_C53_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C53_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C53_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C53_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C53_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C53_REG_OFFSET 0x86c -#define SCMI_COMPLETION_INTERRUPT_C53_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C53_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C54_REG_OFFSET 0x870 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C54_REG_OFFSET 0x874 -#define SCMI_CHANNEL_STATUS_C54_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C54_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C54_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C54_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C54_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C54_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C54_REG_OFFSET 0x878 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C54_REG_OFFSET 0x87c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C54_REG_OFFSET 0x880 -#define SCMI_CHANNEL_FLAGS_C54_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C54_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C54_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C54_REG_OFFSET 0x884 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C54_REG_OFFSET 0x888 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C54_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C54_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C54_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C54_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C54_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C54_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C54_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C54_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C54_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C54_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C54_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C54_REG_OFFSET 0x88c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C54_REG_OFFSET 0x890 -#define SCMI_DOORBELL_C54_INTR_BIT 0 -#define SCMI_DOORBELL_C54_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C54_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C54_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C54_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C54_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C54_REG_OFFSET 0x894 -#define SCMI_COMPLETION_INTERRUPT_C54_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C54_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C55_REG_OFFSET 0x898 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C55_REG_OFFSET 0x89c -#define SCMI_CHANNEL_STATUS_C55_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C55_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C55_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C55_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C55_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C55_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C55_REG_OFFSET 0x8a0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C55_REG_OFFSET 0x8a4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C55_REG_OFFSET 0x8a8 -#define SCMI_CHANNEL_FLAGS_C55_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C55_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C55_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C55_REG_OFFSET 0x8ac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C55_REG_OFFSET 0x8b0 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C55_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C55_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C55_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C55_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C55_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C55_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C55_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C55_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C55_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C55_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C55_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C55_REG_OFFSET 0x8b4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C55_REG_OFFSET 0x8b8 -#define SCMI_DOORBELL_C55_INTR_BIT 0 -#define SCMI_DOORBELL_C55_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C55_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C55_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C55_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C55_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C55_REG_OFFSET 0x8bc -#define SCMI_COMPLETION_INTERRUPT_C55_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C55_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C56_REG_OFFSET 0x8c0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C56_REG_OFFSET 0x8c4 -#define SCMI_CHANNEL_STATUS_C56_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C56_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C56_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C56_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C56_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C56_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C56_REG_OFFSET 0x8c8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C56_REG_OFFSET 0x8cc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C56_REG_OFFSET 0x8d0 -#define SCMI_CHANNEL_FLAGS_C56_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C56_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C56_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C56_REG_OFFSET 0x8d4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C56_REG_OFFSET 0x8d8 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C56_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C56_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C56_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C56_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C56_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C56_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C56_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C56_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C56_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C56_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C56_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C56_REG_OFFSET 0x8dc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C56_REG_OFFSET 0x8e0 -#define SCMI_DOORBELL_C56_INTR_BIT 0 -#define SCMI_DOORBELL_C56_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C56_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C56_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C56_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C56_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C56_REG_OFFSET 0x8e4 -#define SCMI_COMPLETION_INTERRUPT_C56_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C56_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C57_REG_OFFSET 0x8e8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C57_REG_OFFSET 0x8ec -#define SCMI_CHANNEL_STATUS_C57_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C57_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C57_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C57_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C57_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C57_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C57_REG_OFFSET 0x8f0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C57_REG_OFFSET 0x8f4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C57_REG_OFFSET 0x8f8 -#define SCMI_CHANNEL_FLAGS_C57_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C57_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C57_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C57_REG_OFFSET 0x8fc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C57_REG_OFFSET 0x900 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C57_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C57_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C57_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C57_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C57_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C57_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C57_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C57_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C57_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C57_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C57_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C57_REG_OFFSET 0x904 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C57_REG_OFFSET 0x908 -#define SCMI_DOORBELL_C57_INTR_BIT 0 -#define SCMI_DOORBELL_C57_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C57_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C57_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C57_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C57_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C57_REG_OFFSET 0x90c -#define SCMI_COMPLETION_INTERRUPT_C57_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C57_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C58_REG_OFFSET 0x910 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C58_REG_OFFSET 0x914 -#define SCMI_CHANNEL_STATUS_C58_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C58_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C58_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C58_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C58_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C58_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C58_REG_OFFSET 0x918 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C58_REG_OFFSET 0x91c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C58_REG_OFFSET 0x920 -#define SCMI_CHANNEL_FLAGS_C58_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C58_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C58_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C58_REG_OFFSET 0x924 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C58_REG_OFFSET 0x928 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C58_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C58_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C58_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C58_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C58_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C58_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C58_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C58_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C58_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C58_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C58_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C58_REG_OFFSET 0x92c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C58_REG_OFFSET 0x930 -#define SCMI_DOORBELL_C58_INTR_BIT 0 -#define SCMI_DOORBELL_C58_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C58_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C58_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C58_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C58_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C58_REG_OFFSET 0x934 -#define SCMI_COMPLETION_INTERRUPT_C58_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C58_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C59_REG_OFFSET 0x938 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C59_REG_OFFSET 0x93c -#define SCMI_CHANNEL_STATUS_C59_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C59_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C59_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C59_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C59_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C59_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C59_REG_OFFSET 0x940 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C59_REG_OFFSET 0x944 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C59_REG_OFFSET 0x948 -#define SCMI_CHANNEL_FLAGS_C59_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C59_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C59_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C59_REG_OFFSET 0x94c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C59_REG_OFFSET 0x950 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C59_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C59_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C59_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C59_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C59_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C59_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C59_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C59_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C59_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C59_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C59_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C59_REG_OFFSET 0x954 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C59_REG_OFFSET 0x958 -#define SCMI_DOORBELL_C59_INTR_BIT 0 -#define SCMI_DOORBELL_C59_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C59_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C59_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C59_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C59_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C59_REG_OFFSET 0x95c -#define SCMI_COMPLETION_INTERRUPT_C59_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C59_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C60_REG_OFFSET 0x960 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C60_REG_OFFSET 0x964 -#define SCMI_CHANNEL_STATUS_C60_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C60_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C60_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C60_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C60_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C60_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C60_REG_OFFSET 0x968 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C60_REG_OFFSET 0x96c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C60_REG_OFFSET 0x970 -#define SCMI_CHANNEL_FLAGS_C60_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C60_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C60_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C60_REG_OFFSET 0x974 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C60_REG_OFFSET 0x978 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C60_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C60_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C60_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C60_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C60_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C60_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C60_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C60_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C60_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C60_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C60_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C60_REG_OFFSET 0x97c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C60_REG_OFFSET 0x980 -#define SCMI_DOORBELL_C60_INTR_BIT 0 -#define SCMI_DOORBELL_C60_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C60_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C60_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C60_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C60_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C60_REG_OFFSET 0x984 -#define SCMI_COMPLETION_INTERRUPT_C60_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C60_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C61_REG_OFFSET 0x988 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C61_REG_OFFSET 0x98c -#define SCMI_CHANNEL_STATUS_C61_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C61_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C61_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C61_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C61_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C61_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C61_REG_OFFSET 0x990 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C61_REG_OFFSET 0x994 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C61_REG_OFFSET 0x998 -#define SCMI_CHANNEL_FLAGS_C61_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C61_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C61_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C61_REG_OFFSET 0x99c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C61_REG_OFFSET 0x9a0 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C61_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C61_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C61_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C61_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C61_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C61_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C61_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C61_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C61_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C61_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C61_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C61_REG_OFFSET 0x9a4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C61_REG_OFFSET 0x9a8 -#define SCMI_DOORBELL_C61_INTR_BIT 0 -#define SCMI_DOORBELL_C61_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C61_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C61_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C61_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C61_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C61_REG_OFFSET 0x9ac -#define SCMI_COMPLETION_INTERRUPT_C61_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C61_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C62_REG_OFFSET 0x9b0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C62_REG_OFFSET 0x9b4 -#define SCMI_CHANNEL_STATUS_C62_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C62_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C62_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C62_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C62_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C62_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C62_REG_OFFSET 0x9b8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C62_REG_OFFSET 0x9bc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C62_REG_OFFSET 0x9c0 -#define SCMI_CHANNEL_FLAGS_C62_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C62_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C62_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C62_REG_OFFSET 0x9c4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C62_REG_OFFSET 0x9c8 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C62_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C62_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C62_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C62_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C62_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C62_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C62_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C62_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C62_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C62_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C62_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C62_REG_OFFSET 0x9cc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C62_REG_OFFSET 0x9d0 -#define SCMI_DOORBELL_C62_INTR_BIT 0 -#define SCMI_DOORBELL_C62_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C62_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C62_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C62_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C62_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C62_REG_OFFSET 0x9d4 -#define SCMI_COMPLETION_INTERRUPT_C62_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C62_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C63_REG_OFFSET 0x9d8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C63_REG_OFFSET 0x9dc -#define SCMI_CHANNEL_STATUS_C63_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C63_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C63_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C63_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C63_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C63_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C63_REG_OFFSET 0x9e0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C63_REG_OFFSET 0x9e4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C63_REG_OFFSET 0x9e8 -#define SCMI_CHANNEL_FLAGS_C63_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C63_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C63_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C63_REG_OFFSET 0x9ec - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C63_REG_OFFSET 0x9f0 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C63_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C63_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C63_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C63_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C63_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C63_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C63_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C63_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C63_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C63_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C63_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C63_REG_OFFSET 0x9f4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C63_REG_OFFSET 0x9f8 -#define SCMI_DOORBELL_C63_INTR_BIT 0 -#define SCMI_DOORBELL_C63_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C63_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C63_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C63_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C63_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C63_REG_OFFSET 0x9fc -#define SCMI_COMPLETION_INTERRUPT_C63_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C63_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C64_REG_OFFSET 0xa00 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C64_REG_OFFSET 0xa04 -#define SCMI_CHANNEL_STATUS_C64_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C64_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C64_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C64_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C64_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C64_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C64_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C64_REG_OFFSET 0xa08 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C64_REG_OFFSET 0xa0c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C64_REG_OFFSET 0xa10 -#define SCMI_CHANNEL_FLAGS_C64_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C64_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C64_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C64_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C64_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C64_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C64_REG_OFFSET 0xa14 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C64_REG_OFFSET 0xa18 -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C64_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C64_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C64_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C64_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C64_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C64_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C64_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C64_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C64_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C64_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C64_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C64_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C64_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C64_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C64_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C64_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C64_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C64_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C64_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C64_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C64_REG_OFFSET 0xa1c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C64_REG_OFFSET 0xa20 -#define SCMI_DOORBELL_C64_INTR_BIT 0 -#define SCMI_DOORBELL_C64_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C64_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C64_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C64_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C64_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C64_REG_OFFSET 0xa24 -#define SCMI_COMPLETION_INTERRUPT_C64_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C64_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C64_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C64_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C64_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C64_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C65_REG_OFFSET 0xa28 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C65_REG_OFFSET 0xa2c -#define SCMI_CHANNEL_STATUS_C65_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C65_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C65_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C65_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C65_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C65_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C65_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C65_REG_OFFSET 0xa30 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C65_REG_OFFSET 0xa34 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C65_REG_OFFSET 0xa38 -#define SCMI_CHANNEL_FLAGS_C65_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C65_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C65_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C65_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C65_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C65_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C65_REG_OFFSET 0xa3c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C65_REG_OFFSET 0xa40 -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C65_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C65_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C65_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C65_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C65_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C65_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C65_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C65_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C65_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C65_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C65_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C65_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C65_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C65_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C65_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C65_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C65_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C65_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C65_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C65_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C65_REG_OFFSET 0xa44 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C65_REG_OFFSET 0xa48 -#define SCMI_DOORBELL_C65_INTR_BIT 0 -#define SCMI_DOORBELL_C65_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C65_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C65_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C65_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C65_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C65_REG_OFFSET 0xa4c -#define SCMI_COMPLETION_INTERRUPT_C65_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C65_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C65_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C65_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C65_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C65_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C66_REG_OFFSET 0xa50 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C66_REG_OFFSET 0xa54 -#define SCMI_CHANNEL_STATUS_C66_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C66_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C66_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C66_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C66_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C66_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C66_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C66_REG_OFFSET 0xa58 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C66_REG_OFFSET 0xa5c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C66_REG_OFFSET 0xa60 -#define SCMI_CHANNEL_FLAGS_C66_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C66_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C66_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C66_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C66_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C66_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C66_REG_OFFSET 0xa64 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C66_REG_OFFSET 0xa68 -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C66_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C66_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C66_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C66_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C66_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C66_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C66_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C66_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C66_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C66_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C66_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C66_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C66_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C66_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C66_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C66_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C66_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C66_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C66_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C66_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C66_REG_OFFSET 0xa6c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C66_REG_OFFSET 0xa70 -#define SCMI_DOORBELL_C66_INTR_BIT 0 -#define SCMI_DOORBELL_C66_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C66_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C66_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C66_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C66_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C66_REG_OFFSET 0xa74 -#define SCMI_COMPLETION_INTERRUPT_C66_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C66_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C66_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C66_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C66_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C66_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C67_REG_OFFSET 0xa78 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C67_REG_OFFSET 0xa7c -#define SCMI_CHANNEL_STATUS_C67_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C67_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C67_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C67_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C67_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C67_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C67_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C67_REG_OFFSET 0xa80 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C67_REG_OFFSET 0xa84 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C67_REG_OFFSET 0xa88 -#define SCMI_CHANNEL_FLAGS_C67_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C67_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C67_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C67_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C67_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C67_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C67_REG_OFFSET 0xa8c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C67_REG_OFFSET 0xa90 -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C67_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C67_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C67_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C67_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C67_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C67_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C67_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C67_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C67_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C67_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C67_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C67_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C67_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C67_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C67_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C67_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C67_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C67_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C67_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C67_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C67_REG_OFFSET 0xa94 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C67_REG_OFFSET 0xa98 -#define SCMI_DOORBELL_C67_INTR_BIT 0 -#define SCMI_DOORBELL_C67_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C67_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C67_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C67_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C67_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C67_REG_OFFSET 0xa9c -#define SCMI_COMPLETION_INTERRUPT_C67_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C67_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C67_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C67_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C67_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C67_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C68_REG_OFFSET 0xaa0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C68_REG_OFFSET 0xaa4 -#define SCMI_CHANNEL_STATUS_C68_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C68_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C68_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C68_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C68_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C68_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C68_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C68_REG_OFFSET 0xaa8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C68_REG_OFFSET 0xaac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C68_REG_OFFSET 0xab0 -#define SCMI_CHANNEL_FLAGS_C68_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C68_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C68_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C68_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C68_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C68_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C68_REG_OFFSET 0xab4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C68_REG_OFFSET 0xab8 -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C68_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C68_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C68_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C68_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C68_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C68_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C68_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C68_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C68_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C68_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C68_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C68_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C68_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C68_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C68_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C68_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C68_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C68_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C68_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C68_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C68_REG_OFFSET 0xabc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C68_REG_OFFSET 0xac0 -#define SCMI_DOORBELL_C68_INTR_BIT 0 -#define SCMI_DOORBELL_C68_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C68_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C68_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C68_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C68_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C68_REG_OFFSET 0xac4 -#define SCMI_COMPLETION_INTERRUPT_C68_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C68_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C68_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C68_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C68_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C68_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C69_REG_OFFSET 0xac8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C69_REG_OFFSET 0xacc -#define SCMI_CHANNEL_STATUS_C69_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C69_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C69_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C69_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C69_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C69_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C69_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C69_REG_OFFSET 0xad0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C69_REG_OFFSET 0xad4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C69_REG_OFFSET 0xad8 -#define SCMI_CHANNEL_FLAGS_C69_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C69_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C69_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C69_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C69_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C69_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C69_REG_OFFSET 0xadc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C69_REG_OFFSET 0xae0 -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C69_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C69_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C69_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C69_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C69_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C69_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C69_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C69_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C69_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C69_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C69_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C69_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C69_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C69_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C69_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C69_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C69_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C69_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C69_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C69_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C69_REG_OFFSET 0xae4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C69_REG_OFFSET 0xae8 -#define SCMI_DOORBELL_C69_INTR_BIT 0 -#define SCMI_DOORBELL_C69_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C69_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C69_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C69_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C69_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C69_REG_OFFSET 0xaec -#define SCMI_COMPLETION_INTERRUPT_C69_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C69_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C69_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C69_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C69_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C69_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C70_REG_OFFSET 0xaf0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C70_REG_OFFSET 0xaf4 -#define SCMI_CHANNEL_STATUS_C70_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C70_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C70_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C70_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C70_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C70_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C70_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C70_REG_OFFSET 0xaf8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C70_REG_OFFSET 0xafc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C70_REG_OFFSET 0xb00 -#define SCMI_CHANNEL_FLAGS_C70_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C70_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C70_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C70_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C70_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C70_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C70_REG_OFFSET 0xb04 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C70_REG_OFFSET 0xb08 -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C70_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C70_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C70_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C70_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C70_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C70_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C70_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C70_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C70_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C70_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C70_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C70_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C70_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C70_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C70_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C70_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C70_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C70_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C70_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C70_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C70_REG_OFFSET 0xb0c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C70_REG_OFFSET 0xb10 -#define SCMI_DOORBELL_C70_INTR_BIT 0 -#define SCMI_DOORBELL_C70_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C70_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C70_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C70_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C70_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C70_REG_OFFSET 0xb14 -#define SCMI_COMPLETION_INTERRUPT_C70_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C70_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C70_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C70_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C70_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C70_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C71_REG_OFFSET 0xb18 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C71_REG_OFFSET 0xb1c -#define SCMI_CHANNEL_STATUS_C71_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C71_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C71_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C71_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C71_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C71_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C71_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C71_REG_OFFSET 0xb20 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C71_REG_OFFSET 0xb24 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C71_REG_OFFSET 0xb28 -#define SCMI_CHANNEL_FLAGS_C71_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C71_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C71_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C71_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C71_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C71_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C71_REG_OFFSET 0xb2c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C71_REG_OFFSET 0xb30 -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C71_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C71_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C71_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C71_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C71_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C71_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C71_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C71_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C71_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C71_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C71_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C71_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C71_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C71_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C71_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C71_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C71_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C71_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C71_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C71_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C71_REG_OFFSET 0xb34 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C71_REG_OFFSET 0xb38 -#define SCMI_DOORBELL_C71_INTR_BIT 0 -#define SCMI_DOORBELL_C71_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C71_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C71_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C71_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C71_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C71_REG_OFFSET 0xb3c -#define SCMI_COMPLETION_INTERRUPT_C71_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C71_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C71_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C71_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C71_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C71_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C72_REG_OFFSET 0xb40 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C72_REG_OFFSET 0xb44 -#define SCMI_CHANNEL_STATUS_C72_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C72_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C72_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C72_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C72_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C72_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C72_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C72_REG_OFFSET 0xb48 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C72_REG_OFFSET 0xb4c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C72_REG_OFFSET 0xb50 -#define SCMI_CHANNEL_FLAGS_C72_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C72_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C72_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C72_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C72_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C72_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C72_REG_OFFSET 0xb54 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C72_REG_OFFSET 0xb58 -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C72_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C72_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C72_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C72_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C72_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C72_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C72_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C72_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C72_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C72_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C72_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C72_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C72_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C72_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C72_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C72_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C72_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C72_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C72_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C72_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C72_REG_OFFSET 0xb5c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C72_REG_OFFSET 0xb60 -#define SCMI_DOORBELL_C72_INTR_BIT 0 -#define SCMI_DOORBELL_C72_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C72_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C72_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C72_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C72_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C72_REG_OFFSET 0xb64 -#define SCMI_COMPLETION_INTERRUPT_C72_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C72_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C72_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C72_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C72_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C72_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C73_REG_OFFSET 0xb68 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C73_REG_OFFSET 0xb6c -#define SCMI_CHANNEL_STATUS_C73_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C73_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C73_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C73_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C73_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C73_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C73_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C73_REG_OFFSET 0xb70 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C73_REG_OFFSET 0xb74 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C73_REG_OFFSET 0xb78 -#define SCMI_CHANNEL_FLAGS_C73_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C73_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C73_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C73_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C73_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C73_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C73_REG_OFFSET 0xb7c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C73_REG_OFFSET 0xb80 -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C73_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C73_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C73_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C73_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C73_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C73_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C73_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C73_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C73_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C73_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C73_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C73_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C73_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C73_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C73_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C73_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C73_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C73_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C73_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C73_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C73_REG_OFFSET 0xb84 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C73_REG_OFFSET 0xb88 -#define SCMI_DOORBELL_C73_INTR_BIT 0 -#define SCMI_DOORBELL_C73_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C73_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C73_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C73_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C73_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C73_REG_OFFSET 0xb8c -#define SCMI_COMPLETION_INTERRUPT_C73_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C73_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C73_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C73_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C73_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C73_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C74_REG_OFFSET 0xb90 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C74_REG_OFFSET 0xb94 -#define SCMI_CHANNEL_STATUS_C74_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C74_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C74_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C74_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C74_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C74_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C74_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C74_REG_OFFSET 0xb98 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C74_REG_OFFSET 0xb9c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C74_REG_OFFSET 0xba0 -#define SCMI_CHANNEL_FLAGS_C74_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C74_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C74_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C74_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C74_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C74_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C74_REG_OFFSET 0xba4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C74_REG_OFFSET 0xba8 -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C74_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C74_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C74_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C74_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C74_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C74_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C74_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C74_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C74_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C74_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C74_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C74_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C74_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C74_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C74_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C74_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C74_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C74_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C74_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C74_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C74_REG_OFFSET 0xbac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C74_REG_OFFSET 0xbb0 -#define SCMI_DOORBELL_C74_INTR_BIT 0 -#define SCMI_DOORBELL_C74_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C74_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C74_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C74_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C74_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C74_REG_OFFSET 0xbb4 -#define SCMI_COMPLETION_INTERRUPT_C74_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C74_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C74_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C74_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C74_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C74_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C75_REG_OFFSET 0xbb8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C75_REG_OFFSET 0xbbc -#define SCMI_CHANNEL_STATUS_C75_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C75_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C75_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C75_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C75_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C75_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C75_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C75_REG_OFFSET 0xbc0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C75_REG_OFFSET 0xbc4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C75_REG_OFFSET 0xbc8 -#define SCMI_CHANNEL_FLAGS_C75_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C75_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C75_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C75_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C75_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C75_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C75_REG_OFFSET 0xbcc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C75_REG_OFFSET 0xbd0 -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C75_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C75_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C75_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C75_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C75_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C75_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C75_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C75_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C75_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C75_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C75_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C75_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C75_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C75_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C75_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C75_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C75_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C75_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C75_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C75_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C75_REG_OFFSET 0xbd4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C75_REG_OFFSET 0xbd8 -#define SCMI_DOORBELL_C75_INTR_BIT 0 -#define SCMI_DOORBELL_C75_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C75_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C75_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C75_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C75_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C75_REG_OFFSET 0xbdc -#define SCMI_COMPLETION_INTERRUPT_C75_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C75_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C75_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C75_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C75_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C75_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C76_REG_OFFSET 0xbe0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C76_REG_OFFSET 0xbe4 -#define SCMI_CHANNEL_STATUS_C76_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C76_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C76_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C76_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C76_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C76_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C76_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C76_REG_OFFSET 0xbe8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C76_REG_OFFSET 0xbec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C76_REG_OFFSET 0xbf0 -#define SCMI_CHANNEL_FLAGS_C76_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C76_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C76_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C76_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C76_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C76_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C76_REG_OFFSET 0xbf4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C76_REG_OFFSET 0xbf8 -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C76_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C76_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C76_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C76_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C76_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C76_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C76_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C76_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C76_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C76_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C76_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C76_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C76_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C76_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C76_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C76_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C76_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C76_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C76_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C76_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C76_REG_OFFSET 0xbfc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C76_REG_OFFSET 0xc00 -#define SCMI_DOORBELL_C76_INTR_BIT 0 -#define SCMI_DOORBELL_C76_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C76_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C76_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C76_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C76_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C76_REG_OFFSET 0xc04 -#define SCMI_COMPLETION_INTERRUPT_C76_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C76_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C76_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C76_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C76_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C76_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C77_REG_OFFSET 0xc08 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C77_REG_OFFSET 0xc0c -#define SCMI_CHANNEL_STATUS_C77_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C77_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C77_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C77_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C77_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C77_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C77_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C77_REG_OFFSET 0xc10 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C77_REG_OFFSET 0xc14 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C77_REG_OFFSET 0xc18 -#define SCMI_CHANNEL_FLAGS_C77_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C77_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C77_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C77_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C77_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C77_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C77_REG_OFFSET 0xc1c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C77_REG_OFFSET 0xc20 -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C77_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C77_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C77_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C77_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C77_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C77_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C77_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C77_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C77_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C77_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C77_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C77_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C77_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C77_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C77_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C77_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C77_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C77_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C77_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C77_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C77_REG_OFFSET 0xc24 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C77_REG_OFFSET 0xc28 -#define SCMI_DOORBELL_C77_INTR_BIT 0 -#define SCMI_DOORBELL_C77_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C77_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C77_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C77_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C77_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C77_REG_OFFSET 0xc2c -#define SCMI_COMPLETION_INTERRUPT_C77_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C77_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C77_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C77_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C77_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C77_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C78_REG_OFFSET 0xc30 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C78_REG_OFFSET 0xc34 -#define SCMI_CHANNEL_STATUS_C78_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C78_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C78_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C78_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C78_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C78_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C78_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C78_REG_OFFSET 0xc38 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C78_REG_OFFSET 0xc3c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C78_REG_OFFSET 0xc40 -#define SCMI_CHANNEL_FLAGS_C78_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C78_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C78_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C78_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C78_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C78_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C78_REG_OFFSET 0xc44 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C78_REG_OFFSET 0xc48 -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C78_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C78_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C78_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C78_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C78_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C78_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C78_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C78_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C78_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C78_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C78_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C78_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C78_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C78_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C78_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C78_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C78_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C78_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C78_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C78_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C78_REG_OFFSET 0xc4c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C78_REG_OFFSET 0xc50 -#define SCMI_DOORBELL_C78_INTR_BIT 0 -#define SCMI_DOORBELL_C78_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C78_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C78_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C78_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C78_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C78_REG_OFFSET 0xc54 -#define SCMI_COMPLETION_INTERRUPT_C78_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C78_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C78_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C78_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C78_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C78_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C79_REG_OFFSET 0xc58 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C79_REG_OFFSET 0xc5c -#define SCMI_CHANNEL_STATUS_C79_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C79_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C79_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C79_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C79_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C79_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C79_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C79_REG_OFFSET 0xc60 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C79_REG_OFFSET 0xc64 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C79_REG_OFFSET 0xc68 -#define SCMI_CHANNEL_FLAGS_C79_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C79_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C79_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C79_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C79_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C79_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C79_REG_OFFSET 0xc6c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C79_REG_OFFSET 0xc70 -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C79_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C79_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C79_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C79_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C79_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C79_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C79_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C79_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C79_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C79_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C79_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C79_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C79_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C79_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C79_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C79_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C79_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C79_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C79_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C79_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C79_REG_OFFSET 0xc74 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C79_REG_OFFSET 0xc78 -#define SCMI_DOORBELL_C79_INTR_BIT 0 -#define SCMI_DOORBELL_C79_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C79_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C79_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C79_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C79_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C79_REG_OFFSET 0xc7c -#define SCMI_COMPLETION_INTERRUPT_C79_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C79_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C79_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C79_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C79_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C79_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C80_REG_OFFSET 0xc80 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C80_REG_OFFSET 0xc84 -#define SCMI_CHANNEL_STATUS_C80_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C80_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C80_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C80_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C80_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C80_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C80_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C80_REG_OFFSET 0xc88 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C80_REG_OFFSET 0xc8c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C80_REG_OFFSET 0xc90 -#define SCMI_CHANNEL_FLAGS_C80_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C80_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C80_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C80_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C80_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C80_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C80_REG_OFFSET 0xc94 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C80_REG_OFFSET 0xc98 -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C80_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C80_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C80_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C80_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C80_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C80_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C80_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C80_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C80_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C80_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C80_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C80_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C80_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C80_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C80_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C80_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C80_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C80_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C80_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C80_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C80_REG_OFFSET 0xc9c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C80_REG_OFFSET 0xca0 -#define SCMI_DOORBELL_C80_INTR_BIT 0 -#define SCMI_DOORBELL_C80_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C80_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C80_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C80_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C80_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C80_REG_OFFSET 0xca4 -#define SCMI_COMPLETION_INTERRUPT_C80_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C80_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C80_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C80_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C80_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C80_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C81_REG_OFFSET 0xca8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C81_REG_OFFSET 0xcac -#define SCMI_CHANNEL_STATUS_C81_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C81_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C81_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C81_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C81_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C81_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C81_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C81_REG_OFFSET 0xcb0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C81_REG_OFFSET 0xcb4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C81_REG_OFFSET 0xcb8 -#define SCMI_CHANNEL_FLAGS_C81_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C81_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C81_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C81_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C81_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C81_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C81_REG_OFFSET 0xcbc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C81_REG_OFFSET 0xcc0 -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C81_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C81_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C81_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C81_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C81_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C81_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C81_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C81_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C81_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C81_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C81_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C81_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C81_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C81_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C81_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C81_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C81_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C81_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C81_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C81_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C81_REG_OFFSET 0xcc4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C81_REG_OFFSET 0xcc8 -#define SCMI_DOORBELL_C81_INTR_BIT 0 -#define SCMI_DOORBELL_C81_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C81_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C81_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C81_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C81_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C81_REG_OFFSET 0xccc -#define SCMI_COMPLETION_INTERRUPT_C81_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C81_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C81_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C81_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C81_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C81_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C82_REG_OFFSET 0xcd0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C82_REG_OFFSET 0xcd4 -#define SCMI_CHANNEL_STATUS_C82_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C82_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C82_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C82_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C82_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C82_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C82_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C82_REG_OFFSET 0xcd8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C82_REG_OFFSET 0xcdc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C82_REG_OFFSET 0xce0 -#define SCMI_CHANNEL_FLAGS_C82_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C82_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C82_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C82_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C82_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C82_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C82_REG_OFFSET 0xce4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C82_REG_OFFSET 0xce8 -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C82_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C82_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C82_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C82_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C82_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C82_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C82_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C82_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C82_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C82_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C82_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C82_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C82_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C82_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C82_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C82_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C82_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C82_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C82_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C82_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C82_REG_OFFSET 0xcec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C82_REG_OFFSET 0xcf0 -#define SCMI_DOORBELL_C82_INTR_BIT 0 -#define SCMI_DOORBELL_C82_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C82_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C82_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C82_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C82_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C82_REG_OFFSET 0xcf4 -#define SCMI_COMPLETION_INTERRUPT_C82_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C82_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C82_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C82_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C82_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C82_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C83_REG_OFFSET 0xcf8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C83_REG_OFFSET 0xcfc -#define SCMI_CHANNEL_STATUS_C83_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C83_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C83_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C83_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C83_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C83_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C83_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C83_REG_OFFSET 0xd00 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C83_REG_OFFSET 0xd04 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C83_REG_OFFSET 0xd08 -#define SCMI_CHANNEL_FLAGS_C83_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C83_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C83_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C83_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C83_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C83_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C83_REG_OFFSET 0xd0c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C83_REG_OFFSET 0xd10 -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C83_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C83_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C83_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C83_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C83_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C83_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C83_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C83_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C83_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C83_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C83_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C83_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C83_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C83_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C83_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C83_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C83_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C83_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C83_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C83_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C83_REG_OFFSET 0xd14 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C83_REG_OFFSET 0xd18 -#define SCMI_DOORBELL_C83_INTR_BIT 0 -#define SCMI_DOORBELL_C83_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C83_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C83_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C83_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C83_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C83_REG_OFFSET 0xd1c -#define SCMI_COMPLETION_INTERRUPT_C83_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C83_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C83_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C83_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C83_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C83_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C84_REG_OFFSET 0xd20 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C84_REG_OFFSET 0xd24 -#define SCMI_CHANNEL_STATUS_C84_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C84_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C84_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C84_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C84_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C84_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C84_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C84_REG_OFFSET 0xd28 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C84_REG_OFFSET 0xd2c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C84_REG_OFFSET 0xd30 -#define SCMI_CHANNEL_FLAGS_C84_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C84_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C84_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C84_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C84_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C84_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C84_REG_OFFSET 0xd34 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C84_REG_OFFSET 0xd38 -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C84_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C84_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C84_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C84_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C84_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C84_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C84_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C84_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C84_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C84_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C84_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C84_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C84_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C84_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C84_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C84_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C84_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C84_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C84_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C84_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C84_REG_OFFSET 0xd3c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C84_REG_OFFSET 0xd40 -#define SCMI_DOORBELL_C84_INTR_BIT 0 -#define SCMI_DOORBELL_C84_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C84_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C84_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C84_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C84_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C84_REG_OFFSET 0xd44 -#define SCMI_COMPLETION_INTERRUPT_C84_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C84_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C84_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C84_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C84_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C84_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C85_REG_OFFSET 0xd48 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C85_REG_OFFSET 0xd4c -#define SCMI_CHANNEL_STATUS_C85_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C85_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C85_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C85_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C85_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C85_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C85_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C85_REG_OFFSET 0xd50 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C85_REG_OFFSET 0xd54 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C85_REG_OFFSET 0xd58 -#define SCMI_CHANNEL_FLAGS_C85_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C85_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C85_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C85_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C85_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C85_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C85_REG_OFFSET 0xd5c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C85_REG_OFFSET 0xd60 -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C85_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C85_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C85_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C85_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C85_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C85_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C85_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C85_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C85_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C85_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C85_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C85_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C85_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C85_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C85_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C85_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C85_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C85_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C85_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C85_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C85_REG_OFFSET 0xd64 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C85_REG_OFFSET 0xd68 -#define SCMI_DOORBELL_C85_INTR_BIT 0 -#define SCMI_DOORBELL_C85_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C85_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C85_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C85_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C85_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C85_REG_OFFSET 0xd6c -#define SCMI_COMPLETION_INTERRUPT_C85_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C85_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C85_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C85_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C85_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C85_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C86_REG_OFFSET 0xd70 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C86_REG_OFFSET 0xd74 -#define SCMI_CHANNEL_STATUS_C86_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C86_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C86_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C86_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C86_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C86_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C86_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C86_REG_OFFSET 0xd78 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C86_REG_OFFSET 0xd7c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C86_REG_OFFSET 0xd80 -#define SCMI_CHANNEL_FLAGS_C86_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C86_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C86_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C86_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C86_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C86_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C86_REG_OFFSET 0xd84 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C86_REG_OFFSET 0xd88 -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C86_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C86_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C86_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C86_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C86_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C86_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C86_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C86_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C86_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C86_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C86_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C86_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C86_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C86_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C86_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C86_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C86_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C86_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C86_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C86_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C86_REG_OFFSET 0xd8c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C86_REG_OFFSET 0xd90 -#define SCMI_DOORBELL_C86_INTR_BIT 0 -#define SCMI_DOORBELL_C86_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C86_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C86_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C86_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C86_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C86_REG_OFFSET 0xd94 -#define SCMI_COMPLETION_INTERRUPT_C86_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C86_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C86_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C86_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C86_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C86_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C87_REG_OFFSET 0xd98 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C87_REG_OFFSET 0xd9c -#define SCMI_CHANNEL_STATUS_C87_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C87_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C87_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C87_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C87_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C87_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C87_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C87_REG_OFFSET 0xda0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C87_REG_OFFSET 0xda4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C87_REG_OFFSET 0xda8 -#define SCMI_CHANNEL_FLAGS_C87_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C87_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C87_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C87_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C87_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C87_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C87_REG_OFFSET 0xdac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C87_REG_OFFSET 0xdb0 -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C87_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C87_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C87_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C87_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C87_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C87_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C87_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C87_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C87_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C87_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C87_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C87_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C87_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C87_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C87_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C87_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C87_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C87_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C87_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C87_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C87_REG_OFFSET 0xdb4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C87_REG_OFFSET 0xdb8 -#define SCMI_DOORBELL_C87_INTR_BIT 0 -#define SCMI_DOORBELL_C87_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C87_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C87_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C87_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C87_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C87_REG_OFFSET 0xdbc -#define SCMI_COMPLETION_INTERRUPT_C87_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C87_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C87_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C87_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C87_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C87_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C88_REG_OFFSET 0xdc0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C88_REG_OFFSET 0xdc4 -#define SCMI_CHANNEL_STATUS_C88_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C88_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C88_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C88_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C88_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C88_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C88_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C88_REG_OFFSET 0xdc8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C88_REG_OFFSET 0xdcc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C88_REG_OFFSET 0xdd0 -#define SCMI_CHANNEL_FLAGS_C88_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C88_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C88_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C88_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C88_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C88_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C88_REG_OFFSET 0xdd4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C88_REG_OFFSET 0xdd8 -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C88_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C88_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C88_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C88_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C88_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C88_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C88_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C88_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C88_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C88_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C88_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C88_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C88_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C88_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C88_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C88_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C88_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C88_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C88_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C88_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C88_REG_OFFSET 0xddc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C88_REG_OFFSET 0xde0 -#define SCMI_DOORBELL_C88_INTR_BIT 0 -#define SCMI_DOORBELL_C88_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C88_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C88_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C88_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C88_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C88_REG_OFFSET 0xde4 -#define SCMI_COMPLETION_INTERRUPT_C88_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C88_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C88_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C88_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C88_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C88_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C89_REG_OFFSET 0xde8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C89_REG_OFFSET 0xdec -#define SCMI_CHANNEL_STATUS_C89_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C89_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C89_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C89_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C89_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C89_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C89_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C89_REG_OFFSET 0xdf0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C89_REG_OFFSET 0xdf4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C89_REG_OFFSET 0xdf8 -#define SCMI_CHANNEL_FLAGS_C89_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C89_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C89_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C89_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C89_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C89_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C89_REG_OFFSET 0xdfc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C89_REG_OFFSET 0xe00 -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C89_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C89_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C89_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C89_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C89_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C89_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C89_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C89_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C89_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C89_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C89_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C89_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C89_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C89_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C89_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C89_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C89_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C89_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C89_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C89_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C89_REG_OFFSET 0xe04 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C89_REG_OFFSET 0xe08 -#define SCMI_DOORBELL_C89_INTR_BIT 0 -#define SCMI_DOORBELL_C89_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C89_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C89_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C89_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C89_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C89_REG_OFFSET 0xe0c -#define SCMI_COMPLETION_INTERRUPT_C89_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C89_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C89_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C89_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C89_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C89_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C90_REG_OFFSET 0xe10 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C90_REG_OFFSET 0xe14 -#define SCMI_CHANNEL_STATUS_C90_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C90_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C90_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C90_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C90_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C90_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C90_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C90_REG_OFFSET 0xe18 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C90_REG_OFFSET 0xe1c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C90_REG_OFFSET 0xe20 -#define SCMI_CHANNEL_FLAGS_C90_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C90_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C90_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C90_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C90_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C90_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C90_REG_OFFSET 0xe24 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C90_REG_OFFSET 0xe28 -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C90_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C90_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C90_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C90_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C90_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C90_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C90_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C90_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C90_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C90_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C90_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C90_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C90_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C90_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C90_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C90_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C90_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C90_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C90_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C90_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C90_REG_OFFSET 0xe2c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C90_REG_OFFSET 0xe30 -#define SCMI_DOORBELL_C90_INTR_BIT 0 -#define SCMI_DOORBELL_C90_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C90_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C90_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C90_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C90_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C90_REG_OFFSET 0xe34 -#define SCMI_COMPLETION_INTERRUPT_C90_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C90_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C90_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C90_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C90_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C90_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C91_REG_OFFSET 0xe38 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C91_REG_OFFSET 0xe3c -#define SCMI_CHANNEL_STATUS_C91_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C91_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C91_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C91_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C91_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C91_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C91_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C91_REG_OFFSET 0xe40 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C91_REG_OFFSET 0xe44 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C91_REG_OFFSET 0xe48 -#define SCMI_CHANNEL_FLAGS_C91_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C91_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C91_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C91_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C91_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C91_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C91_REG_OFFSET 0xe4c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C91_REG_OFFSET 0xe50 -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C91_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C91_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C91_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C91_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C91_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C91_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C91_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C91_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C91_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C91_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C91_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C91_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C91_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C91_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C91_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C91_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C91_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C91_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C91_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C91_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C91_REG_OFFSET 0xe54 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C91_REG_OFFSET 0xe58 -#define SCMI_DOORBELL_C91_INTR_BIT 0 -#define SCMI_DOORBELL_C91_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C91_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C91_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C91_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C91_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C91_REG_OFFSET 0xe5c -#define SCMI_COMPLETION_INTERRUPT_C91_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C91_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C91_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C91_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C91_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C91_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C92_REG_OFFSET 0xe60 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C92_REG_OFFSET 0xe64 -#define SCMI_CHANNEL_STATUS_C92_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C92_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C92_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C92_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C92_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C92_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C92_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C92_REG_OFFSET 0xe68 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C92_REG_OFFSET 0xe6c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C92_REG_OFFSET 0xe70 -#define SCMI_CHANNEL_FLAGS_C92_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C92_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C92_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C92_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C92_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C92_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C92_REG_OFFSET 0xe74 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C92_REG_OFFSET 0xe78 -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C92_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C92_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C92_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C92_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C92_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C92_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C92_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C92_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C92_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C92_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C92_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C92_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C92_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C92_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C92_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C92_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C92_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C92_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C92_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C92_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C92_REG_OFFSET 0xe7c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C92_REG_OFFSET 0xe80 -#define SCMI_DOORBELL_C92_INTR_BIT 0 -#define SCMI_DOORBELL_C92_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C92_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C92_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C92_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C92_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C92_REG_OFFSET 0xe84 -#define SCMI_COMPLETION_INTERRUPT_C92_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C92_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C92_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C92_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C92_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C92_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C93_REG_OFFSET 0xe88 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C93_REG_OFFSET 0xe8c -#define SCMI_CHANNEL_STATUS_C93_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C93_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C93_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C93_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C93_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C93_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C93_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C93_REG_OFFSET 0xe90 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C93_REG_OFFSET 0xe94 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C93_REG_OFFSET 0xe98 -#define SCMI_CHANNEL_FLAGS_C93_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C93_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C93_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C93_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C93_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C93_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C93_REG_OFFSET 0xe9c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C93_REG_OFFSET 0xea0 -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C93_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C93_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C93_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C93_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C93_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C93_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C93_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C93_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C93_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C93_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C93_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C93_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C93_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C93_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C93_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C93_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C93_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C93_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C93_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C93_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C93_REG_OFFSET 0xea4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C93_REG_OFFSET 0xea8 -#define SCMI_DOORBELL_C93_INTR_BIT 0 -#define SCMI_DOORBELL_C93_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C93_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C93_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C93_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C93_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C93_REG_OFFSET 0xeac -#define SCMI_COMPLETION_INTERRUPT_C93_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C93_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C93_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C93_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C93_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C93_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C94_REG_OFFSET 0xeb0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C94_REG_OFFSET 0xeb4 -#define SCMI_CHANNEL_STATUS_C94_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C94_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C94_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C94_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C94_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C94_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C94_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C94_REG_OFFSET 0xeb8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C94_REG_OFFSET 0xebc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C94_REG_OFFSET 0xec0 -#define SCMI_CHANNEL_FLAGS_C94_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C94_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C94_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C94_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C94_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C94_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C94_REG_OFFSET 0xec4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C94_REG_OFFSET 0xec8 -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C94_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C94_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C94_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C94_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C94_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C94_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C94_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C94_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C94_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C94_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C94_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C94_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C94_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C94_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C94_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C94_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C94_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C94_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C94_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C94_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C94_REG_OFFSET 0xecc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C94_REG_OFFSET 0xed0 -#define SCMI_DOORBELL_C94_INTR_BIT 0 -#define SCMI_DOORBELL_C94_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C94_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C94_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C94_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C94_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C94_REG_OFFSET 0xed4 -#define SCMI_COMPLETION_INTERRUPT_C94_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C94_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C94_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C94_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C94_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C94_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C95_REG_OFFSET 0xed8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C95_REG_OFFSET 0xedc -#define SCMI_CHANNEL_STATUS_C95_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C95_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C95_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C95_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C95_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C95_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C95_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C95_REG_OFFSET 0xee0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C95_REG_OFFSET 0xee4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C95_REG_OFFSET 0xee8 -#define SCMI_CHANNEL_FLAGS_C95_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C95_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C95_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C95_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C95_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C95_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C95_REG_OFFSET 0xeec - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C95_REG_OFFSET 0xef0 -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C95_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C95_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C95_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C95_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C95_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C95_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C95_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C95_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C95_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C95_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C95_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C95_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C95_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C95_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C95_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C95_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C95_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C95_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C95_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C95_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C95_REG_OFFSET 0xef4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C95_REG_OFFSET 0xef8 -#define SCMI_DOORBELL_C95_INTR_BIT 0 -#define SCMI_DOORBELL_C95_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C95_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C95_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C95_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C95_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C95_REG_OFFSET 0xefc -#define SCMI_COMPLETION_INTERRUPT_C95_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C95_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C95_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C95_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C95_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C95_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C96_REG_OFFSET 0xf00 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C96_REG_OFFSET 0xf04 -#define SCMI_CHANNEL_STATUS_C96_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C96_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C96_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C96_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C96_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C96_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C96_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C96_REG_OFFSET 0xf08 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C96_REG_OFFSET 0xf0c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C96_REG_OFFSET 0xf10 -#define SCMI_CHANNEL_FLAGS_C96_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C96_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C96_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C96_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C96_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C96_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C96_REG_OFFSET 0xf14 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C96_REG_OFFSET 0xf18 -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C96_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C96_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C96_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C96_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C96_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C96_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C96_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C96_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C96_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C96_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C96_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C96_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C96_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C96_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C96_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C96_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C96_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C96_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C96_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C96_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C96_REG_OFFSET 0xf1c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C96_REG_OFFSET 0xf20 -#define SCMI_DOORBELL_C96_INTR_BIT 0 -#define SCMI_DOORBELL_C96_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C96_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C96_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C96_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C96_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C96_REG_OFFSET 0xf24 -#define SCMI_COMPLETION_INTERRUPT_C96_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C96_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C96_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C96_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C96_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C96_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C97_REG_OFFSET 0xf28 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C97_REG_OFFSET 0xf2c -#define SCMI_CHANNEL_STATUS_C97_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C97_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C97_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C97_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C97_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C97_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C97_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C97_REG_OFFSET 0xf30 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C97_REG_OFFSET 0xf34 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C97_REG_OFFSET 0xf38 -#define SCMI_CHANNEL_FLAGS_C97_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C97_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C97_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C97_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C97_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C97_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C97_REG_OFFSET 0xf3c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C97_REG_OFFSET 0xf40 -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C97_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C97_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C97_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C97_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C97_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C97_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C97_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C97_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C97_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C97_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C97_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C97_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C97_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C97_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C97_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C97_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C97_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C97_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C97_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C97_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C97_REG_OFFSET 0xf44 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C97_REG_OFFSET 0xf48 -#define SCMI_DOORBELL_C97_INTR_BIT 0 -#define SCMI_DOORBELL_C97_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C97_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C97_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C97_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C97_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C97_REG_OFFSET 0xf4c -#define SCMI_COMPLETION_INTERRUPT_C97_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C97_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C97_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C97_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C97_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C97_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C98_REG_OFFSET 0xf50 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C98_REG_OFFSET 0xf54 -#define SCMI_CHANNEL_STATUS_C98_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C98_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C98_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C98_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C98_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C98_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C98_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C98_REG_OFFSET 0xf58 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C98_REG_OFFSET 0xf5c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C98_REG_OFFSET 0xf60 -#define SCMI_CHANNEL_FLAGS_C98_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C98_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C98_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C98_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C98_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C98_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C98_REG_OFFSET 0xf64 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C98_REG_OFFSET 0xf68 -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C98_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C98_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C98_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C98_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C98_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C98_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C98_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C98_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C98_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C98_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C98_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C98_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C98_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C98_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C98_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C98_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C98_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C98_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C98_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C98_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C98_REG_OFFSET 0xf6c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C98_REG_OFFSET 0xf70 -#define SCMI_DOORBELL_C98_INTR_BIT 0 -#define SCMI_DOORBELL_C98_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C98_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C98_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C98_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C98_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C98_REG_OFFSET 0xf74 -#define SCMI_COMPLETION_INTERRUPT_C98_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C98_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C98_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C98_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C98_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C98_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C99_REG_OFFSET 0xf78 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C99_REG_OFFSET 0xf7c -#define SCMI_CHANNEL_STATUS_C99_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C99_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C99_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C99_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C99_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C99_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C99_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C99_REG_OFFSET 0xf80 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C99_REG_OFFSET 0xf84 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C99_REG_OFFSET 0xf88 -#define SCMI_CHANNEL_FLAGS_C99_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C99_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C99_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C99_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C99_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C99_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C99_REG_OFFSET 0xf8c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C99_REG_OFFSET 0xf90 -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C99_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C99_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C99_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C99_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C99_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C99_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C99_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C99_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C99_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C99_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C99_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C99_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C99_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C99_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C99_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C99_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C99_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C99_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C99_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C99_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C99_REG_OFFSET 0xf94 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C99_REG_OFFSET 0xf98 -#define SCMI_DOORBELL_C99_INTR_BIT 0 -#define SCMI_DOORBELL_C99_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C99_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C99_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C99_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C99_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C99_REG_OFFSET 0xf9c -#define SCMI_COMPLETION_INTERRUPT_C99_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C99_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C99_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C99_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C99_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C99_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C100_REG_OFFSET 0xfa0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C100_REG_OFFSET 0xfa4 -#define SCMI_CHANNEL_STATUS_C100_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C100_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C100_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C100_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C100_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C100_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C100_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C100_REG_OFFSET 0xfa8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C100_REG_OFFSET 0xfac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C100_REG_OFFSET 0xfb0 -#define SCMI_CHANNEL_FLAGS_C100_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C100_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C100_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C100_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C100_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C100_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C100_REG_OFFSET 0xfb4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C100_REG_OFFSET 0xfb8 -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C100_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C100_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C100_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C100_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C100_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C100_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C100_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C100_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C100_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C100_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C100_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C100_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C100_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C100_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C100_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C100_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C100_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C100_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C100_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C100_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C100_REG_OFFSET 0xfbc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C100_REG_OFFSET 0xfc0 -#define SCMI_DOORBELL_C100_INTR_BIT 0 -#define SCMI_DOORBELL_C100_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C100_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C100_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C100_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C100_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C100_REG_OFFSET 0xfc4 -#define SCMI_COMPLETION_INTERRUPT_C100_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C100_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C100_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C100_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C100_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C100_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C101_REG_OFFSET 0xfc8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C101_REG_OFFSET 0xfcc -#define SCMI_CHANNEL_STATUS_C101_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C101_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C101_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C101_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C101_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C101_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C101_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C101_REG_OFFSET 0xfd0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C101_REG_OFFSET 0xfd4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C101_REG_OFFSET 0xfd8 -#define SCMI_CHANNEL_FLAGS_C101_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C101_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C101_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C101_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C101_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C101_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C101_REG_OFFSET 0xfdc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C101_REG_OFFSET 0xfe0 -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C101_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C101_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C101_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C101_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C101_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C101_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C101_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C101_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C101_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C101_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C101_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C101_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C101_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C101_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C101_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C101_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C101_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C101_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C101_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C101_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C101_REG_OFFSET 0xfe4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C101_REG_OFFSET 0xfe8 -#define SCMI_DOORBELL_C101_INTR_BIT 0 -#define SCMI_DOORBELL_C101_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C101_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C101_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C101_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C101_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C101_REG_OFFSET 0xfec -#define SCMI_COMPLETION_INTERRUPT_C101_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C101_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C101_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C101_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C101_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C101_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C102_REG_OFFSET 0xff0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C102_REG_OFFSET 0xff4 -#define SCMI_CHANNEL_STATUS_C102_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C102_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C102_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C102_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C102_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C102_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C102_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C102_REG_OFFSET 0xff8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C102_REG_OFFSET 0xffc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C102_REG_OFFSET 0x1000 -#define SCMI_CHANNEL_FLAGS_C102_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C102_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C102_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C102_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C102_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C102_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C102_REG_OFFSET 0x1004 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C102_REG_OFFSET 0x1008 -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C102_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C102_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C102_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C102_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C102_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C102_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C102_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C102_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C102_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C102_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C102_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C102_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C102_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C102_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C102_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C102_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C102_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C102_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C102_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C102_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C102_REG_OFFSET 0x100c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C102_REG_OFFSET 0x1010 -#define SCMI_DOORBELL_C102_INTR_BIT 0 -#define SCMI_DOORBELL_C102_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C102_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C102_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C102_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C102_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C102_REG_OFFSET 0x1014 -#define SCMI_COMPLETION_INTERRUPT_C102_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C102_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C102_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C102_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C102_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C102_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C103_REG_OFFSET 0x1018 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C103_REG_OFFSET 0x101c -#define SCMI_CHANNEL_STATUS_C103_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C103_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C103_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C103_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C103_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C103_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C103_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C103_REG_OFFSET 0x1020 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C103_REG_OFFSET 0x1024 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C103_REG_OFFSET 0x1028 -#define SCMI_CHANNEL_FLAGS_C103_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C103_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C103_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C103_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C103_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C103_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C103_REG_OFFSET 0x102c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C103_REG_OFFSET 0x1030 -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C103_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C103_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C103_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C103_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C103_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C103_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C103_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C103_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C103_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C103_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C103_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C103_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C103_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C103_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C103_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C103_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C103_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C103_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C103_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C103_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C103_REG_OFFSET 0x1034 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C103_REG_OFFSET 0x1038 -#define SCMI_DOORBELL_C103_INTR_BIT 0 -#define SCMI_DOORBELL_C103_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C103_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C103_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C103_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C103_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C103_REG_OFFSET 0x103c -#define SCMI_COMPLETION_INTERRUPT_C103_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C103_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C103_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C103_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C103_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C103_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C104_REG_OFFSET 0x1040 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C104_REG_OFFSET 0x1044 -#define SCMI_CHANNEL_STATUS_C104_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C104_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C104_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C104_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C104_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C104_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C104_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C104_REG_OFFSET 0x1048 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C104_REG_OFFSET 0x104c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C104_REG_OFFSET 0x1050 -#define SCMI_CHANNEL_FLAGS_C104_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C104_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C104_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C104_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C104_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C104_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C104_REG_OFFSET 0x1054 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C104_REG_OFFSET 0x1058 -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C104_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C104_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C104_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C104_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C104_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C104_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C104_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C104_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C104_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C104_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C104_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C104_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C104_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C104_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C104_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C104_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C104_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C104_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C104_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C104_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C104_REG_OFFSET 0x105c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C104_REG_OFFSET 0x1060 -#define SCMI_DOORBELL_C104_INTR_BIT 0 -#define SCMI_DOORBELL_C104_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C104_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C104_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C104_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C104_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C104_REG_OFFSET 0x1064 -#define SCMI_COMPLETION_INTERRUPT_C104_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C104_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C104_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C104_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C104_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C104_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C105_REG_OFFSET 0x1068 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C105_REG_OFFSET 0x106c -#define SCMI_CHANNEL_STATUS_C105_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C105_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C105_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C105_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C105_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C105_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C105_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C105_REG_OFFSET 0x1070 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C105_REG_OFFSET 0x1074 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C105_REG_OFFSET 0x1078 -#define SCMI_CHANNEL_FLAGS_C105_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C105_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C105_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C105_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C105_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C105_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C105_REG_OFFSET 0x107c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C105_REG_OFFSET 0x1080 -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C105_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C105_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C105_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C105_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C105_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C105_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C105_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C105_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C105_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C105_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C105_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C105_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C105_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C105_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C105_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C105_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C105_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C105_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C105_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C105_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C105_REG_OFFSET 0x1084 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C105_REG_OFFSET 0x1088 -#define SCMI_DOORBELL_C105_INTR_BIT 0 -#define SCMI_DOORBELL_C105_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C105_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C105_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C105_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C105_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C105_REG_OFFSET 0x108c -#define SCMI_COMPLETION_INTERRUPT_C105_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C105_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C105_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C105_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C105_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C105_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C106_REG_OFFSET 0x1090 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C106_REG_OFFSET 0x1094 -#define SCMI_CHANNEL_STATUS_C106_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C106_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C106_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C106_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C106_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C106_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C106_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C106_REG_OFFSET 0x1098 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C106_REG_OFFSET 0x109c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C106_REG_OFFSET 0x10a0 -#define SCMI_CHANNEL_FLAGS_C106_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C106_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C106_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C106_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C106_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C106_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C106_REG_OFFSET 0x10a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C106_REG_OFFSET 0x10a8 -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C106_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C106_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C106_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C106_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C106_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C106_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C106_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C106_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C106_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C106_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C106_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C106_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C106_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C106_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C106_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C106_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C106_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C106_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C106_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C106_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C106_REG_OFFSET 0x10ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C106_REG_OFFSET 0x10b0 -#define SCMI_DOORBELL_C106_INTR_BIT 0 -#define SCMI_DOORBELL_C106_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C106_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C106_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C106_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C106_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C106_REG_OFFSET 0x10b4 -#define SCMI_COMPLETION_INTERRUPT_C106_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C106_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C106_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C106_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C106_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C106_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C107_REG_OFFSET 0x10b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C107_REG_OFFSET 0x10bc -#define SCMI_CHANNEL_STATUS_C107_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C107_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C107_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C107_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C107_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C107_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C107_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C107_REG_OFFSET 0x10c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C107_REG_OFFSET 0x10c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C107_REG_OFFSET 0x10c8 -#define SCMI_CHANNEL_FLAGS_C107_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C107_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C107_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C107_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C107_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C107_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C107_REG_OFFSET 0x10cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C107_REG_OFFSET 0x10d0 -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C107_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C107_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C107_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C107_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C107_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C107_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C107_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C107_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C107_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C107_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C107_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C107_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C107_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C107_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C107_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C107_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C107_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C107_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C107_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C107_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C107_REG_OFFSET 0x10d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C107_REG_OFFSET 0x10d8 -#define SCMI_DOORBELL_C107_INTR_BIT 0 -#define SCMI_DOORBELL_C107_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C107_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C107_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C107_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C107_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C107_REG_OFFSET 0x10dc -#define SCMI_COMPLETION_INTERRUPT_C107_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C107_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C107_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C107_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C107_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C107_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C108_REG_OFFSET 0x10e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C108_REG_OFFSET 0x10e4 -#define SCMI_CHANNEL_STATUS_C108_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C108_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C108_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C108_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C108_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C108_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C108_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C108_REG_OFFSET 0x10e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C108_REG_OFFSET 0x10ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C108_REG_OFFSET 0x10f0 -#define SCMI_CHANNEL_FLAGS_C108_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C108_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C108_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C108_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C108_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C108_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C108_REG_OFFSET 0x10f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C108_REG_OFFSET 0x10f8 -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C108_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C108_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C108_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C108_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C108_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C108_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C108_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C108_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C108_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C108_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C108_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C108_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C108_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C108_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C108_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C108_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C108_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C108_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C108_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C108_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C108_REG_OFFSET 0x10fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C108_REG_OFFSET 0x1100 -#define SCMI_DOORBELL_C108_INTR_BIT 0 -#define SCMI_DOORBELL_C108_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C108_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C108_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C108_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C108_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C108_REG_OFFSET 0x1104 -#define SCMI_COMPLETION_INTERRUPT_C108_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C108_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C108_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C108_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C108_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C108_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C109_REG_OFFSET 0x1108 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C109_REG_OFFSET 0x110c -#define SCMI_CHANNEL_STATUS_C109_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C109_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C109_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C109_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C109_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C109_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C109_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C109_REG_OFFSET 0x1110 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C109_REG_OFFSET 0x1114 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C109_REG_OFFSET 0x1118 -#define SCMI_CHANNEL_FLAGS_C109_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C109_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C109_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C109_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C109_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C109_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C109_REG_OFFSET 0x111c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C109_REG_OFFSET 0x1120 -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C109_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C109_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C109_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C109_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C109_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C109_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C109_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C109_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C109_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C109_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C109_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C109_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C109_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C109_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C109_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C109_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C109_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C109_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C109_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C109_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C109_REG_OFFSET 0x1124 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C109_REG_OFFSET 0x1128 -#define SCMI_DOORBELL_C109_INTR_BIT 0 -#define SCMI_DOORBELL_C109_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C109_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C109_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C109_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C109_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C109_REG_OFFSET 0x112c -#define SCMI_COMPLETION_INTERRUPT_C109_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C109_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C109_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C109_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C109_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C109_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C110_REG_OFFSET 0x1130 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C110_REG_OFFSET 0x1134 -#define SCMI_CHANNEL_STATUS_C110_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C110_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C110_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C110_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C110_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C110_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C110_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C110_REG_OFFSET 0x1138 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C110_REG_OFFSET 0x113c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C110_REG_OFFSET 0x1140 -#define SCMI_CHANNEL_FLAGS_C110_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C110_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C110_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C110_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C110_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C110_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C110_REG_OFFSET 0x1144 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C110_REG_OFFSET 0x1148 -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C110_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C110_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C110_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C110_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C110_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C110_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C110_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C110_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C110_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C110_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C110_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C110_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C110_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C110_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C110_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C110_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C110_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C110_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C110_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C110_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C110_REG_OFFSET 0x114c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C110_REG_OFFSET 0x1150 -#define SCMI_DOORBELL_C110_INTR_BIT 0 -#define SCMI_DOORBELL_C110_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C110_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C110_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C110_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C110_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C110_REG_OFFSET 0x1154 -#define SCMI_COMPLETION_INTERRUPT_C110_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C110_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C110_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C110_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C110_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C110_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C111_REG_OFFSET 0x1158 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C111_REG_OFFSET 0x115c -#define SCMI_CHANNEL_STATUS_C111_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C111_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C111_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C111_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C111_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C111_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C111_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C111_REG_OFFSET 0x1160 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C111_REG_OFFSET 0x1164 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C111_REG_OFFSET 0x1168 -#define SCMI_CHANNEL_FLAGS_C111_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C111_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C111_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C111_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C111_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C111_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C111_REG_OFFSET 0x116c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C111_REG_OFFSET 0x1170 -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C111_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C111_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C111_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C111_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C111_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C111_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C111_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C111_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C111_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C111_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C111_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C111_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C111_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C111_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C111_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C111_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C111_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C111_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C111_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C111_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C111_REG_OFFSET 0x1174 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C111_REG_OFFSET 0x1178 -#define SCMI_DOORBELL_C111_INTR_BIT 0 -#define SCMI_DOORBELL_C111_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C111_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C111_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C111_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C111_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C111_REG_OFFSET 0x117c -#define SCMI_COMPLETION_INTERRUPT_C111_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C111_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C111_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C111_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C111_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C111_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C112_REG_OFFSET 0x1180 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C112_REG_OFFSET 0x1184 -#define SCMI_CHANNEL_STATUS_C112_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C112_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C112_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C112_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C112_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C112_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C112_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C112_REG_OFFSET 0x1188 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C112_REG_OFFSET 0x118c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C112_REG_OFFSET 0x1190 -#define SCMI_CHANNEL_FLAGS_C112_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C112_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C112_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C112_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C112_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C112_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C112_REG_OFFSET 0x1194 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C112_REG_OFFSET 0x1198 -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C112_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C112_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C112_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C112_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C112_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C112_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C112_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C112_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C112_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C112_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C112_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C112_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C112_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C112_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C112_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C112_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C112_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C112_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C112_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C112_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C112_REG_OFFSET 0x119c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C112_REG_OFFSET 0x11a0 -#define SCMI_DOORBELL_C112_INTR_BIT 0 -#define SCMI_DOORBELL_C112_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C112_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C112_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C112_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C112_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C112_REG_OFFSET 0x11a4 -#define SCMI_COMPLETION_INTERRUPT_C112_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C112_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C112_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C112_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C112_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C112_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C113_REG_OFFSET 0x11a8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C113_REG_OFFSET 0x11ac -#define SCMI_CHANNEL_STATUS_C113_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C113_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C113_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C113_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C113_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C113_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C113_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C113_REG_OFFSET 0x11b0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C113_REG_OFFSET 0x11b4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C113_REG_OFFSET 0x11b8 -#define SCMI_CHANNEL_FLAGS_C113_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C113_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C113_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C113_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C113_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C113_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C113_REG_OFFSET 0x11bc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C113_REG_OFFSET 0x11c0 -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C113_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C113_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C113_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C113_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C113_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C113_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C113_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C113_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C113_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C113_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C113_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C113_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C113_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C113_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C113_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C113_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C113_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C113_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C113_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C113_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C113_REG_OFFSET 0x11c4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C113_REG_OFFSET 0x11c8 -#define SCMI_DOORBELL_C113_INTR_BIT 0 -#define SCMI_DOORBELL_C113_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C113_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C113_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C113_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C113_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C113_REG_OFFSET 0x11cc -#define SCMI_COMPLETION_INTERRUPT_C113_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C113_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C113_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C113_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C113_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C113_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C114_REG_OFFSET 0x11d0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C114_REG_OFFSET 0x11d4 -#define SCMI_CHANNEL_STATUS_C114_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C114_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C114_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C114_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C114_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C114_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C114_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C114_REG_OFFSET 0x11d8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C114_REG_OFFSET 0x11dc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C114_REG_OFFSET 0x11e0 -#define SCMI_CHANNEL_FLAGS_C114_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C114_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C114_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C114_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C114_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C114_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C114_REG_OFFSET 0x11e4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C114_REG_OFFSET 0x11e8 -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C114_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C114_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C114_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C114_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C114_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C114_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C114_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C114_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C114_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C114_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C114_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C114_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C114_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C114_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C114_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C114_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C114_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C114_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C114_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C114_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C114_REG_OFFSET 0x11ec - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C114_REG_OFFSET 0x11f0 -#define SCMI_DOORBELL_C114_INTR_BIT 0 -#define SCMI_DOORBELL_C114_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C114_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C114_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C114_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C114_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C114_REG_OFFSET 0x11f4 -#define SCMI_COMPLETION_INTERRUPT_C114_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C114_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C114_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C114_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C114_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C114_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C115_REG_OFFSET 0x11f8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C115_REG_OFFSET 0x11fc -#define SCMI_CHANNEL_STATUS_C115_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C115_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C115_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C115_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C115_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C115_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C115_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C115_REG_OFFSET 0x1200 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C115_REG_OFFSET 0x1204 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C115_REG_OFFSET 0x1208 -#define SCMI_CHANNEL_FLAGS_C115_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C115_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C115_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C115_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C115_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C115_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C115_REG_OFFSET 0x120c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C115_REG_OFFSET 0x1210 -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C115_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C115_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C115_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C115_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C115_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C115_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C115_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C115_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C115_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C115_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C115_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C115_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C115_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C115_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C115_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C115_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C115_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C115_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C115_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C115_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C115_REG_OFFSET 0x1214 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C115_REG_OFFSET 0x1218 -#define SCMI_DOORBELL_C115_INTR_BIT 0 -#define SCMI_DOORBELL_C115_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C115_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C115_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C115_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C115_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C115_REG_OFFSET 0x121c -#define SCMI_COMPLETION_INTERRUPT_C115_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C115_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C115_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C115_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C115_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C115_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C116_REG_OFFSET 0x1220 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C116_REG_OFFSET 0x1224 -#define SCMI_CHANNEL_STATUS_C116_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C116_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C116_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C116_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C116_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C116_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C116_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C116_REG_OFFSET 0x1228 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C116_REG_OFFSET 0x122c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C116_REG_OFFSET 0x1230 -#define SCMI_CHANNEL_FLAGS_C116_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C116_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C116_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C116_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C116_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C116_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C116_REG_OFFSET 0x1234 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C116_REG_OFFSET 0x1238 -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C116_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C116_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C116_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C116_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C116_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C116_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C116_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C116_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C116_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C116_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C116_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C116_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C116_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C116_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C116_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C116_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C116_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C116_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C116_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C116_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C116_REG_OFFSET 0x123c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C116_REG_OFFSET 0x1240 -#define SCMI_DOORBELL_C116_INTR_BIT 0 -#define SCMI_DOORBELL_C116_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C116_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C116_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C116_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C116_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C116_REG_OFFSET 0x1244 -#define SCMI_COMPLETION_INTERRUPT_C116_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C116_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C116_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C116_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C116_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C116_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C117_REG_OFFSET 0x1248 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C117_REG_OFFSET 0x124c -#define SCMI_CHANNEL_STATUS_C117_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C117_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C117_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C117_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C117_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C117_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C117_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C117_REG_OFFSET 0x1250 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C117_REG_OFFSET 0x1254 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C117_REG_OFFSET 0x1258 -#define SCMI_CHANNEL_FLAGS_C117_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C117_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C117_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C117_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C117_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C117_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C117_REG_OFFSET 0x125c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C117_REG_OFFSET 0x1260 -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C117_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C117_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C117_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C117_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C117_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C117_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C117_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C117_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C117_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C117_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C117_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C117_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C117_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C117_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C117_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C117_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C117_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C117_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C117_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C117_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C117_REG_OFFSET 0x1264 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C117_REG_OFFSET 0x1268 -#define SCMI_DOORBELL_C117_INTR_BIT 0 -#define SCMI_DOORBELL_C117_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C117_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C117_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C117_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C117_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C117_REG_OFFSET 0x126c -#define SCMI_COMPLETION_INTERRUPT_C117_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C117_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C117_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C117_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C117_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C117_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C118_REG_OFFSET 0x1270 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C118_REG_OFFSET 0x1274 -#define SCMI_CHANNEL_STATUS_C118_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C118_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C118_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C118_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C118_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C118_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C118_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C118_REG_OFFSET 0x1278 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C118_REG_OFFSET 0x127c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C118_REG_OFFSET 0x1280 -#define SCMI_CHANNEL_FLAGS_C118_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C118_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C118_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C118_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C118_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C118_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C118_REG_OFFSET 0x1284 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C118_REG_OFFSET 0x1288 -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C118_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C118_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C118_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C118_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C118_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C118_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C118_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C118_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C118_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C118_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C118_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C118_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C118_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C118_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C118_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C118_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C118_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C118_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C118_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C118_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C118_REG_OFFSET 0x128c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C118_REG_OFFSET 0x1290 -#define SCMI_DOORBELL_C118_INTR_BIT 0 -#define SCMI_DOORBELL_C118_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C118_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C118_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C118_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C118_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C118_REG_OFFSET 0x1294 -#define SCMI_COMPLETION_INTERRUPT_C118_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C118_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C118_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C118_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C118_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C118_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C119_REG_OFFSET 0x1298 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C119_REG_OFFSET 0x129c -#define SCMI_CHANNEL_STATUS_C119_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C119_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C119_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C119_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C119_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C119_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C119_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C119_REG_OFFSET 0x12a0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C119_REG_OFFSET 0x12a4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C119_REG_OFFSET 0x12a8 -#define SCMI_CHANNEL_FLAGS_C119_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C119_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C119_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C119_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C119_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C119_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C119_REG_OFFSET 0x12ac - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C119_REG_OFFSET 0x12b0 -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C119_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C119_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C119_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C119_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C119_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C119_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C119_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C119_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C119_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C119_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C119_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C119_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C119_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C119_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C119_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C119_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C119_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C119_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C119_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C119_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C119_REG_OFFSET 0x12b4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C119_REG_OFFSET 0x12b8 -#define SCMI_DOORBELL_C119_INTR_BIT 0 -#define SCMI_DOORBELL_C119_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C119_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C119_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C119_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C119_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C119_REG_OFFSET 0x12bc -#define SCMI_COMPLETION_INTERRUPT_C119_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C119_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C119_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C119_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C119_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C119_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C120_REG_OFFSET 0x12c0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C120_REG_OFFSET 0x12c4 -#define SCMI_CHANNEL_STATUS_C120_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C120_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C120_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C120_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C120_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C120_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C120_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C120_REG_OFFSET 0x12c8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C120_REG_OFFSET 0x12cc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C120_REG_OFFSET 0x12d0 -#define SCMI_CHANNEL_FLAGS_C120_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C120_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C120_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C120_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C120_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C120_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C120_REG_OFFSET 0x12d4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C120_REG_OFFSET 0x12d8 -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C120_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C120_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C120_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C120_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C120_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C120_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C120_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C120_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C120_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C120_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C120_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C120_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C120_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C120_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C120_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C120_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C120_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C120_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C120_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C120_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C120_REG_OFFSET 0x12dc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C120_REG_OFFSET 0x12e0 -#define SCMI_DOORBELL_C120_INTR_BIT 0 -#define SCMI_DOORBELL_C120_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C120_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C120_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C120_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C120_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C120_REG_OFFSET 0x12e4 -#define SCMI_COMPLETION_INTERRUPT_C120_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C120_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C120_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C120_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C120_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C120_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C121_REG_OFFSET 0x12e8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C121_REG_OFFSET 0x12ec -#define SCMI_CHANNEL_STATUS_C121_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C121_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C121_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C121_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C121_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C121_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C121_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C121_REG_OFFSET 0x12f0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C121_REG_OFFSET 0x12f4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C121_REG_OFFSET 0x12f8 -#define SCMI_CHANNEL_FLAGS_C121_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C121_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C121_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C121_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C121_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C121_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C121_REG_OFFSET 0x12fc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C121_REG_OFFSET 0x1300 -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C121_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C121_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C121_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C121_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C121_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C121_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C121_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C121_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C121_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C121_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C121_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C121_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C121_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C121_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C121_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C121_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C121_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C121_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C121_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C121_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C121_REG_OFFSET 0x1304 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C121_REG_OFFSET 0x1308 -#define SCMI_DOORBELL_C121_INTR_BIT 0 -#define SCMI_DOORBELL_C121_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C121_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C121_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C121_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C121_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C121_REG_OFFSET 0x130c -#define SCMI_COMPLETION_INTERRUPT_C121_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C121_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C121_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C121_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C121_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C121_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C122_REG_OFFSET 0x1310 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C122_REG_OFFSET 0x1314 -#define SCMI_CHANNEL_STATUS_C122_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C122_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C122_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C122_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C122_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C122_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C122_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C122_REG_OFFSET 0x1318 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C122_REG_OFFSET 0x131c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C122_REG_OFFSET 0x1320 -#define SCMI_CHANNEL_FLAGS_C122_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C122_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C122_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C122_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C122_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C122_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C122_REG_OFFSET 0x1324 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C122_REG_OFFSET 0x1328 -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C122_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C122_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C122_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C122_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C122_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C122_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C122_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C122_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C122_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C122_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C122_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C122_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C122_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C122_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C122_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C122_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C122_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C122_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C122_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C122_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C122_REG_OFFSET 0x132c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C122_REG_OFFSET 0x1330 -#define SCMI_DOORBELL_C122_INTR_BIT 0 -#define SCMI_DOORBELL_C122_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C122_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C122_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C122_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C122_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C122_REG_OFFSET 0x1334 -#define SCMI_COMPLETION_INTERRUPT_C122_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C122_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C122_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C122_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C122_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C122_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C123_REG_OFFSET 0x1338 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C123_REG_OFFSET 0x133c -#define SCMI_CHANNEL_STATUS_C123_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C123_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C123_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C123_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C123_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C123_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C123_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C123_REG_OFFSET 0x1340 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C123_REG_OFFSET 0x1344 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C123_REG_OFFSET 0x1348 -#define SCMI_CHANNEL_FLAGS_C123_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C123_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C123_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C123_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C123_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C123_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C123_REG_OFFSET 0x134c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C123_REG_OFFSET 0x1350 -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C123_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C123_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C123_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C123_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C123_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C123_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C123_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C123_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C123_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C123_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C123_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C123_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C123_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C123_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C123_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C123_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C123_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C123_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C123_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C123_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C123_REG_OFFSET 0x1354 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C123_REG_OFFSET 0x1358 -#define SCMI_DOORBELL_C123_INTR_BIT 0 -#define SCMI_DOORBELL_C123_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C123_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C123_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C123_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C123_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C123_REG_OFFSET 0x135c -#define SCMI_COMPLETION_INTERRUPT_C123_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C123_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C123_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C123_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C123_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C123_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C124_REG_OFFSET 0x1360 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C124_REG_OFFSET 0x1364 -#define SCMI_CHANNEL_STATUS_C124_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C124_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C124_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C124_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C124_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C124_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C124_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C124_REG_OFFSET 0x1368 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C124_REG_OFFSET 0x136c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C124_REG_OFFSET 0x1370 -#define SCMI_CHANNEL_FLAGS_C124_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C124_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C124_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C124_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C124_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C124_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C124_REG_OFFSET 0x1374 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C124_REG_OFFSET 0x1378 -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C124_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C124_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C124_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C124_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C124_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C124_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C124_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C124_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C124_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C124_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C124_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C124_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C124_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C124_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C124_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C124_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C124_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C124_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C124_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C124_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C124_REG_OFFSET 0x137c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C124_REG_OFFSET 0x1380 -#define SCMI_DOORBELL_C124_INTR_BIT 0 -#define SCMI_DOORBELL_C124_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C124_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C124_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C124_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C124_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C124_REG_OFFSET 0x1384 -#define SCMI_COMPLETION_INTERRUPT_C124_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C124_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C124_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C124_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C124_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C124_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C125_REG_OFFSET 0x1388 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C125_REG_OFFSET 0x138c -#define SCMI_CHANNEL_STATUS_C125_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C125_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C125_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C125_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C125_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C125_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C125_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C125_REG_OFFSET 0x1390 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C125_REG_OFFSET 0x1394 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C125_REG_OFFSET 0x1398 -#define SCMI_CHANNEL_FLAGS_C125_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C125_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C125_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C125_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C125_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C125_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C125_REG_OFFSET 0x139c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C125_REG_OFFSET 0x13a0 -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C125_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C125_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C125_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C125_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C125_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C125_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C125_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C125_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C125_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C125_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C125_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C125_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C125_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C125_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C125_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C125_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C125_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C125_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C125_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C125_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C125_REG_OFFSET 0x13a4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C125_REG_OFFSET 0x13a8 -#define SCMI_DOORBELL_C125_INTR_BIT 0 -#define SCMI_DOORBELL_C125_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C125_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C125_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C125_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C125_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C125_REG_OFFSET 0x13ac -#define SCMI_COMPLETION_INTERRUPT_C125_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C125_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C125_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C125_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C125_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C125_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C126_REG_OFFSET 0x13b0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C126_REG_OFFSET 0x13b4 -#define SCMI_CHANNEL_STATUS_C126_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C126_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C126_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C126_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C126_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C126_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C126_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C126_REG_OFFSET 0x13b8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C126_REG_OFFSET 0x13bc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C126_REG_OFFSET 0x13c0 -#define SCMI_CHANNEL_FLAGS_C126_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C126_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C126_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C126_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C126_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C126_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C126_REG_OFFSET 0x13c4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C126_REG_OFFSET 0x13c8 -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C126_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C126_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C126_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C126_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C126_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C126_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C126_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C126_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C126_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C126_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C126_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C126_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C126_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C126_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C126_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C126_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C126_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C126_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C126_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C126_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C126_REG_OFFSET 0x13cc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C126_REG_OFFSET 0x13d0 -#define SCMI_DOORBELL_C126_INTR_BIT 0 -#define SCMI_DOORBELL_C126_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C126_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C126_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C126_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C126_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C126_REG_OFFSET 0x13d4 -#define SCMI_COMPLETION_INTERRUPT_C126_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C126_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C126_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C126_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C126_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C126_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C127_REG_OFFSET 0x13d8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C127_REG_OFFSET 0x13dc -#define SCMI_CHANNEL_STATUS_C127_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C127_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C127_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C127_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C127_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C127_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C127_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C127_REG_OFFSET 0x13e0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C127_REG_OFFSET 0x13e4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C127_REG_OFFSET 0x13e8 -#define SCMI_CHANNEL_FLAGS_C127_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C127_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C127_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C127_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C127_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C127_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C127_REG_OFFSET 0x13ec - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C127_REG_OFFSET 0x13f0 -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C127_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C127_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C127_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C127_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C127_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C127_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C127_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C127_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C127_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C127_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C127_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C127_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C127_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C127_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C127_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C127_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C127_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C127_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C127_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C127_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C127_REG_OFFSET 0x13f4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C127_REG_OFFSET 0x13f8 -#define SCMI_DOORBELL_C127_INTR_BIT 0 -#define SCMI_DOORBELL_C127_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C127_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C127_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C127_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C127_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C127_REG_OFFSET 0x13fc -#define SCMI_COMPLETION_INTERRUPT_C127_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C127_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C127_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C127_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C127_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C127_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C128_REG_OFFSET 0x1400 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C128_REG_OFFSET 0x1404 -#define SCMI_CHANNEL_STATUS_C128_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C128_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C128_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C128_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C128_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C128_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C128_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C128_REG_OFFSET 0x1408 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C128_REG_OFFSET 0x140c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C128_REG_OFFSET 0x1410 -#define SCMI_CHANNEL_FLAGS_C128_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C128_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C128_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C128_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C128_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C128_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C128_REG_OFFSET 0x1414 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C128_REG_OFFSET 0x1418 -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C128_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C128_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C128_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C128_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C128_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C128_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C128_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C128_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C128_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C128_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C128_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C128_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C128_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C128_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C128_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C128_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C128_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C128_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C128_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C128_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C128_REG_OFFSET 0x141c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C128_REG_OFFSET 0x1420 -#define SCMI_DOORBELL_C128_INTR_BIT 0 -#define SCMI_DOORBELL_C128_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C128_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C128_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C128_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C128_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C128_REG_OFFSET 0x1424 -#define SCMI_COMPLETION_INTERRUPT_C128_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C128_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C128_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C128_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C128_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C128_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C129_REG_OFFSET 0x1428 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C129_REG_OFFSET 0x142c -#define SCMI_CHANNEL_STATUS_C129_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C129_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C129_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C129_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C129_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C129_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C129_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C129_REG_OFFSET 0x1430 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C129_REG_OFFSET 0x1434 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C129_REG_OFFSET 0x1438 -#define SCMI_CHANNEL_FLAGS_C129_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C129_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C129_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C129_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C129_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C129_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C129_REG_OFFSET 0x143c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C129_REG_OFFSET 0x1440 -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C129_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C129_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C129_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C129_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C129_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C129_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C129_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C129_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C129_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C129_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C129_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C129_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C129_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C129_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C129_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C129_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C129_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C129_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C129_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C129_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C129_REG_OFFSET 0x1444 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C129_REG_OFFSET 0x1448 -#define SCMI_DOORBELL_C129_INTR_BIT 0 -#define SCMI_DOORBELL_C129_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C129_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C129_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C129_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C129_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C129_REG_OFFSET 0x144c -#define SCMI_COMPLETION_INTERRUPT_C129_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C129_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C129_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C129_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C129_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C129_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C130_REG_OFFSET 0x1450 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C130_REG_OFFSET 0x1454 -#define SCMI_CHANNEL_STATUS_C130_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C130_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C130_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C130_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C130_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C130_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C130_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C130_REG_OFFSET 0x1458 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C130_REG_OFFSET 0x145c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C130_REG_OFFSET 0x1460 -#define SCMI_CHANNEL_FLAGS_C130_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C130_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C130_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C130_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C130_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C130_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C130_REG_OFFSET 0x1464 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C130_REG_OFFSET 0x1468 -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C130_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C130_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C130_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C130_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C130_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C130_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C130_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C130_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C130_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C130_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C130_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C130_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C130_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C130_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C130_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C130_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C130_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C130_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C130_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C130_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C130_REG_OFFSET 0x146c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C130_REG_OFFSET 0x1470 -#define SCMI_DOORBELL_C130_INTR_BIT 0 -#define SCMI_DOORBELL_C130_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C130_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C130_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C130_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C130_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C130_REG_OFFSET 0x1474 -#define SCMI_COMPLETION_INTERRUPT_C130_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C130_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C130_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C130_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C130_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C130_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C131_REG_OFFSET 0x1478 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C131_REG_OFFSET 0x147c -#define SCMI_CHANNEL_STATUS_C131_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C131_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C131_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C131_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C131_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C131_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C131_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C131_REG_OFFSET 0x1480 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C131_REG_OFFSET 0x1484 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C131_REG_OFFSET 0x1488 -#define SCMI_CHANNEL_FLAGS_C131_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C131_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C131_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C131_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C131_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C131_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C131_REG_OFFSET 0x148c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C131_REG_OFFSET 0x1490 -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C131_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C131_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C131_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C131_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C131_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C131_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C131_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C131_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C131_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C131_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C131_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C131_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C131_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C131_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C131_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C131_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C131_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C131_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C131_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C131_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C131_REG_OFFSET 0x1494 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C131_REG_OFFSET 0x1498 -#define SCMI_DOORBELL_C131_INTR_BIT 0 -#define SCMI_DOORBELL_C131_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C131_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C131_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C131_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C131_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C131_REG_OFFSET 0x149c -#define SCMI_COMPLETION_INTERRUPT_C131_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C131_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C131_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C131_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C131_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C131_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C132_REG_OFFSET 0x14a0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C132_REG_OFFSET 0x14a4 -#define SCMI_CHANNEL_STATUS_C132_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C132_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C132_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C132_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C132_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C132_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C132_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C132_REG_OFFSET 0x14a8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C132_REG_OFFSET 0x14ac - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C132_REG_OFFSET 0x14b0 -#define SCMI_CHANNEL_FLAGS_C132_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C132_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C132_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C132_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C132_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C132_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C132_REG_OFFSET 0x14b4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C132_REG_OFFSET 0x14b8 -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C132_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C132_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C132_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C132_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C132_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C132_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C132_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C132_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C132_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C132_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C132_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C132_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C132_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C132_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C132_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C132_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C132_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C132_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C132_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C132_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C132_REG_OFFSET 0x14bc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C132_REG_OFFSET 0x14c0 -#define SCMI_DOORBELL_C132_INTR_BIT 0 -#define SCMI_DOORBELL_C132_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C132_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C132_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C132_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C132_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C132_REG_OFFSET 0x14c4 -#define SCMI_COMPLETION_INTERRUPT_C132_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C132_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C132_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C132_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C132_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C132_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C133_REG_OFFSET 0x14c8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C133_REG_OFFSET 0x14cc -#define SCMI_CHANNEL_STATUS_C133_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C133_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C133_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C133_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C133_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C133_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C133_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C133_REG_OFFSET 0x14d0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C133_REG_OFFSET 0x14d4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C133_REG_OFFSET 0x14d8 -#define SCMI_CHANNEL_FLAGS_C133_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C133_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C133_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C133_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C133_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C133_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C133_REG_OFFSET 0x14dc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C133_REG_OFFSET 0x14e0 -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C133_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C133_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C133_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C133_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C133_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C133_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C133_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C133_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C133_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C133_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C133_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C133_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C133_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C133_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C133_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C133_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C133_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C133_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C133_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C133_FIELD1_OFFSET }) - -// memory region dedicated to the parameters of the commands and their -// returns -#define SCMI_MESSAGE_PAYLOAD_1_C133_REG_OFFSET 0x14e4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C133_REG_OFFSET 0x14e8 -#define SCMI_DOORBELL_C133_INTR_BIT 0 -#define SCMI_DOORBELL_C133_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C133_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C133_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C133_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C133_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C133_REG_OFFSET 0x14ec -#define SCMI_COMPLETION_INTERRUPT_C133_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C133_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C133_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C133_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C133_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C133_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C134_REG_OFFSET 0x14f0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C134_REG_OFFSET 0x14f4 -#define SCMI_CHANNEL_STATUS_C134_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C134_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C134_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C134_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C134_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C134_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C134_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C134_REG_OFFSET 0x14f8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C134_REG_OFFSET 0x14fc - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C134_REG_OFFSET 0x1500 -#define SCMI_CHANNEL_FLAGS_C134_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C134_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C134_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C134_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C134_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C134_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C134_REG_OFFSET 0x1504 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C134_REG_OFFSET 0x1508 -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C134_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C134_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C134_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C134_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C134_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C134_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C134_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C134_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C134_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C134_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C134_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C134_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C134_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C134_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C134_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C134_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C134_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C134_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C134_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C134_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_0_C0_REG_OFFSET 0x1c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C134_REG_OFFSET 0x150c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C134_REG_OFFSET 0x1510 -#define SCMI_DOORBELL_C134_INTR_BIT 0 -#define SCMI_DOORBELL_C134_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C134_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C134_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C134_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C134_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C134_REG_OFFSET 0x1514 -#define SCMI_COMPLETION_INTERRUPT_C134_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C134_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C134_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C134_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C134_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C134_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C135_REG_OFFSET 0x1518 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C135_REG_OFFSET 0x151c -#define SCMI_CHANNEL_STATUS_C135_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C135_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C135_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C135_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C135_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C135_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C135_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C135_REG_OFFSET 0x1520 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C135_REG_OFFSET 0x1524 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C135_REG_OFFSET 0x1528 -#define SCMI_CHANNEL_FLAGS_C135_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C135_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C135_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C135_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C135_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C135_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C135_REG_OFFSET 0x152c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C135_REG_OFFSET 0x1530 -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C135_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C135_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C135_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C135_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C135_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C135_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C135_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C135_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C135_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C135_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C135_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C135_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C135_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C135_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C135_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C135_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C135_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C135_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C135_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C135_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_1_C0_REG_OFFSET 0x20 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C135_REG_OFFSET 0x1534 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C135_REG_OFFSET 0x1538 -#define SCMI_DOORBELL_C135_INTR_BIT 0 -#define SCMI_DOORBELL_C135_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C135_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C135_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C135_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C135_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C135_REG_OFFSET 0x153c -#define SCMI_COMPLETION_INTERRUPT_C135_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C135_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C135_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C135_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C135_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C135_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C136_REG_OFFSET 0x1540 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C136_REG_OFFSET 0x1544 -#define SCMI_CHANNEL_STATUS_C136_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C136_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C136_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C136_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C136_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C136_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C136_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C136_REG_OFFSET 0x1548 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C136_REG_OFFSET 0x154c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C136_REG_OFFSET 0x1550 -#define SCMI_CHANNEL_FLAGS_C136_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C136_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C136_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C136_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C136_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C136_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C136_REG_OFFSET 0x1554 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C136_REG_OFFSET 0x1558 -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C136_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C136_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C136_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C136_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C136_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C136_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C136_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C136_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C136_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C136_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C136_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C136_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C136_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C136_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C136_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C136_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C136_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C136_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C136_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C136_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_2_C0_REG_OFFSET 0x24 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C136_REG_OFFSET 0x155c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C136_REG_OFFSET 0x1560 -#define SCMI_DOORBELL_C136_INTR_BIT 0 -#define SCMI_DOORBELL_C136_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C136_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C136_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C136_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C136_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C136_REG_OFFSET 0x1564 -#define SCMI_COMPLETION_INTERRUPT_C136_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C136_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C136_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C136_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C136_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C136_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C137_REG_OFFSET 0x1568 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C137_REG_OFFSET 0x156c -#define SCMI_CHANNEL_STATUS_C137_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C137_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C137_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C137_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C137_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C137_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C137_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C137_REG_OFFSET 0x1570 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C137_REG_OFFSET 0x1574 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C137_REG_OFFSET 0x1578 -#define SCMI_CHANNEL_FLAGS_C137_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C137_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C137_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C137_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C137_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C137_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C137_REG_OFFSET 0x157c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C137_REG_OFFSET 0x1580 -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C137_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C137_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C137_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C137_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C137_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C137_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C137_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C137_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C137_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C137_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C137_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C137_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C137_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C137_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C137_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C137_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C137_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C137_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C137_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C137_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_3_C0_REG_OFFSET 0x28 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C137_REG_OFFSET 0x1584 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C137_REG_OFFSET 0x1588 -#define SCMI_DOORBELL_C137_INTR_BIT 0 -#define SCMI_DOORBELL_C137_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C137_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C137_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C137_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C137_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C137_REG_OFFSET 0x158c -#define SCMI_COMPLETION_INTERRUPT_C137_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C137_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C137_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C137_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C137_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C137_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C138_REG_OFFSET 0x1590 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C138_REG_OFFSET 0x1594 -#define SCMI_CHANNEL_STATUS_C138_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C138_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C138_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C138_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C138_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C138_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C138_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C138_REG_OFFSET 0x1598 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C138_REG_OFFSET 0x159c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C138_REG_OFFSET 0x15a0 -#define SCMI_CHANNEL_FLAGS_C138_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C138_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C138_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C138_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C138_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C138_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C138_REG_OFFSET 0x15a4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C138_REG_OFFSET 0x15a8 -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C138_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C138_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C138_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C138_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C138_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C138_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C138_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C138_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C138_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C138_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C138_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C138_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C138_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C138_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C138_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C138_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C138_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C138_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C138_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C138_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_4_C0_REG_OFFSET 0x2c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C138_REG_OFFSET 0x15ac - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C138_REG_OFFSET 0x15b0 -#define SCMI_DOORBELL_C138_INTR_BIT 0 -#define SCMI_DOORBELL_C138_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C138_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C138_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C138_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C138_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C138_REG_OFFSET 0x15b4 -#define SCMI_COMPLETION_INTERRUPT_C138_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C138_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C138_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C138_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C138_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C138_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C139_REG_OFFSET 0x15b8 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C139_REG_OFFSET 0x15bc -#define SCMI_CHANNEL_STATUS_C139_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C139_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C139_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C139_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C139_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C139_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C139_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C139_REG_OFFSET 0x15c0 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C139_REG_OFFSET 0x15c4 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C139_REG_OFFSET 0x15c8 -#define SCMI_CHANNEL_FLAGS_C139_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C139_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C139_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C139_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C139_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C139_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C139_REG_OFFSET 0x15cc - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C139_REG_OFFSET 0x15d0 -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C139_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C139_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C139_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C139_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C139_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C139_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C139_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C139_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C139_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C139_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C139_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C139_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C139_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C139_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C139_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C139_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C139_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C139_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C139_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C139_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_5_C0_REG_OFFSET 0x30 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C139_REG_OFFSET 0x15d4 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C139_REG_OFFSET 0x15d8 -#define SCMI_DOORBELL_C139_INTR_BIT 0 -#define SCMI_DOORBELL_C139_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C139_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C139_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C139_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C139_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C139_REG_OFFSET 0x15dc -#define SCMI_COMPLETION_INTERRUPT_C139_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C139_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C139_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C139_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C139_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C139_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C140_REG_OFFSET 0x15e0 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C140_REG_OFFSET 0x15e4 -#define SCMI_CHANNEL_STATUS_C140_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C140_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C140_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C140_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C140_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C140_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C140_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C140_REG_OFFSET 0x15e8 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C140_REG_OFFSET 0x15ec - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C140_REG_OFFSET 0x15f0 -#define SCMI_CHANNEL_FLAGS_C140_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C140_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C140_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C140_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C140_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C140_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C140_REG_OFFSET 0x15f4 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C140_REG_OFFSET 0x15f8 -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C140_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C140_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C140_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C140_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C140_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C140_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C140_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C140_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C140_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C140_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C140_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C140_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C140_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C140_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C140_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C140_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C140_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C140_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C140_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C140_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_6_C0_REG_OFFSET 0x34 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C140_REG_OFFSET 0x15fc - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C140_REG_OFFSET 0x1600 -#define SCMI_DOORBELL_C140_INTR_BIT 0 -#define SCMI_DOORBELL_C140_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C140_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C140_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C140_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C140_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C140_REG_OFFSET 0x1604 -#define SCMI_COMPLETION_INTERRUPT_C140_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C140_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C140_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C140_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C140_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C140_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C141_REG_OFFSET 0x1608 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C141_REG_OFFSET 0x160c -#define SCMI_CHANNEL_STATUS_C141_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C141_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C141_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C141_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C141_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C141_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C141_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C141_REG_OFFSET 0x1610 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C141_REG_OFFSET 0x1614 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C141_REG_OFFSET 0x1618 -#define SCMI_CHANNEL_FLAGS_C141_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C141_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C141_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C141_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C141_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C141_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C141_REG_OFFSET 0x161c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C141_REG_OFFSET 0x1620 -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C141_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C141_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C141_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C141_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C141_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C141_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C141_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C141_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C141_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C141_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C141_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C141_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C141_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C141_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C141_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C141_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C141_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C141_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C141_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C141_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_7_C0_REG_OFFSET 0x38 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C141_REG_OFFSET 0x1624 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C141_REG_OFFSET 0x1628 -#define SCMI_DOORBELL_C141_INTR_BIT 0 -#define SCMI_DOORBELL_C141_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C141_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C141_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C141_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C141_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C141_REG_OFFSET 0x162c -#define SCMI_COMPLETION_INTERRUPT_C141_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C141_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C141_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C141_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C141_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C141_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C142_REG_OFFSET 0x1630 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C142_REG_OFFSET 0x1634 -#define SCMI_CHANNEL_STATUS_C142_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C142_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C142_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C142_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C142_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C142_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C142_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C142_REG_OFFSET 0x1638 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C142_REG_OFFSET 0x163c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C142_REG_OFFSET 0x1640 -#define SCMI_CHANNEL_FLAGS_C142_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C142_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C142_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C142_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C142_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C142_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C142_REG_OFFSET 0x1644 - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C142_REG_OFFSET 0x1648 -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C142_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C142_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C142_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C142_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C142_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C142_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C142_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C142_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C142_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C142_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C142_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C142_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C142_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C142_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C142_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C142_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C142_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C142_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C142_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C142_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_8_C0_REG_OFFSET 0x3c // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C142_REG_OFFSET 0x164c - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C142_REG_OFFSET 0x1650 -#define SCMI_DOORBELL_C142_INTR_BIT 0 -#define SCMI_DOORBELL_C142_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C142_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C142_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C142_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C142_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C142_REG_OFFSET 0x1654 -#define SCMI_COMPLETION_INTERRUPT_C142_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C142_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C142_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C142_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C142_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C142_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C143_REG_OFFSET 0x1658 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C143_REG_OFFSET 0x165c -#define SCMI_CHANNEL_STATUS_C143_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C143_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C143_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C143_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C143_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C143_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C143_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C143_REG_OFFSET 0x1660 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C143_REG_OFFSET 0x1664 - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C143_REG_OFFSET 0x1668 -#define SCMI_CHANNEL_FLAGS_C143_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C143_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C143_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C143_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C143_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C143_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C143_REG_OFFSET 0x166c - -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C143_REG_OFFSET 0x1670 -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C143_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C143_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C143_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C143_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C143_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C143_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C143_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C143_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C143_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C143_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C143_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C143_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C143_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C143_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C143_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C143_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C143_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C143_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C143_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C143_FIELD1_OFFSET }) +#define SCMI_MESSAGE_PAYLOAD_9_C0_REG_OFFSET 0x40 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C143_REG_OFFSET 0x1674 - -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C143_REG_OFFSET 0x1678 -#define SCMI_DOORBELL_C143_INTR_BIT 0 -#define SCMI_DOORBELL_C143_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C143_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C143_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C143_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C143_PRESERVE_MASK_OFFSET }) - -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C143_REG_OFFSET 0x167c -#define SCMI_COMPLETION_INTERRUPT_C143_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C143_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C143_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C143_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C143_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C143_PRESERVE_MASK_OFFSET }) - -// Reserved, must be 0 -#define SCMI_RESERVED_1_C144_REG_OFFSET 0x1680 - -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C144_REG_OFFSET 0x1684 -#define SCMI_CHANNEL_STATUS_C144_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C144_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C144_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C144_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C144_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C144_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C144_FIELD1_OFFSET }) - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C144_REG_OFFSET 0x1688 - -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C144_REG_OFFSET 0x168c - -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C144_REG_OFFSET 0x1690 -#define SCMI_CHANNEL_FLAGS_C144_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C144_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C144_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C144_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C144_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C144_FIELD1_OFFSET }) - -// Lenght of payload + header -#define SCMI_LENGTH_C144_REG_OFFSET 0x1694 +#define SCMI_MESSAGE_PAYLOAD_10_C0_REG_OFFSET 0x44 -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C144_REG_OFFSET 0x1698 -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C144_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C144_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C144_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C144_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C144_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C144_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C144_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C144_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C144_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C144_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C144_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C144_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C144_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C144_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C144_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C144_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C144_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C144_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C144_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C144_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_11_C0_REG_OFFSET 0x48 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C144_REG_OFFSET 0x169c +#define SCMI_MESSAGE_PAYLOAD_12_C0_REG_OFFSET 0x4c -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C144_REG_OFFSET 0x16a0 -#define SCMI_DOORBELL_C144_INTR_BIT 0 -#define SCMI_DOORBELL_C144_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C144_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C144_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C144_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C144_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_13_C0_REG_OFFSET 0x50 -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C144_REG_OFFSET 0x16a4 -#define SCMI_COMPLETION_INTERRUPT_C144_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C144_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C144_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C144_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C144_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C144_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_14_C0_REG_OFFSET 0x54 -// Reserved, must be 0 -#define SCMI_RESERVED_1_C145_REG_OFFSET 0x16a8 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_15_C0_REG_OFFSET 0x58 -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C145_REG_OFFSET 0x16ac -#define SCMI_CHANNEL_STATUS_C145_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C145_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C145_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C145_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C145_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C145_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C145_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_16_C0_REG_OFFSET 0x5c -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C145_REG_OFFSET 0x16b0 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_17_C0_REG_OFFSET 0x60 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C145_REG_OFFSET 0x16b4 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_18_C0_REG_OFFSET 0x64 -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C145_REG_OFFSET 0x16b8 -#define SCMI_CHANNEL_FLAGS_C145_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C145_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C145_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C145_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C145_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C145_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_19_C0_REG_OFFSET 0x68 -// Lenght of payload + header -#define SCMI_LENGTH_C145_REG_OFFSET 0x16bc +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_20_C0_REG_OFFSET 0x6c -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C145_REG_OFFSET 0x16c0 -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C145_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C145_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C145_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C145_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C145_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C145_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C145_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C145_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C145_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C145_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C145_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C145_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C145_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C145_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C145_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C145_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C145_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C145_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C145_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C145_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_21_C0_REG_OFFSET 0x70 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C145_REG_OFFSET 0x16c4 +#define SCMI_MESSAGE_PAYLOAD_22_C0_REG_OFFSET 0x74 -// Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C145_REG_OFFSET 0x16c8 -#define SCMI_DOORBELL_C145_INTR_BIT 0 -#define SCMI_DOORBELL_C145_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C145_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C145_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C145_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C145_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_23_C0_REG_OFFSET 0x78 -// Rapresent the interrupt the platform should raise when it finishes to -// execute the received command -#define SCMI_COMPLETION_INTERRUPT_C145_REG_OFFSET 0x16cc -#define SCMI_COMPLETION_INTERRUPT_C145_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C145_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C145_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C145_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C145_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C145_PRESERVE_MASK_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_24_C0_REG_OFFSET 0x7c -// Reserved, must be 0 -#define SCMI_RESERVED_1_C146_REG_OFFSET 0x16d0 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_25_C0_REG_OFFSET 0x80 -// Indicates which entity has access to the Shared Memory -#define SCMI_CHANNEL_STATUS_C146_REG_OFFSET 0x16d4 -#define SCMI_CHANNEL_STATUS_C146_CHANNEL_FREE_BIT 0 -#define SCMI_CHANNEL_STATUS_C146_CHANNEL_ERROR_BIT 1 -#define SCMI_CHANNEL_STATUS_C146_FIELD1_MASK 0x3fffffff -#define SCMI_CHANNEL_STATUS_C146_FIELD1_OFFSET 2 -#define SCMI_CHANNEL_STATUS_C146_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_STATUS_C146_FIELD1_MASK, .index = SCMI_CHANNEL_STATUS_C146_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_26_C0_REG_OFFSET 0x84 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_2_C146_REG_OFFSET 0x16d8 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_27_C0_REG_OFFSET 0x88 -// Reserved, implementation defined (32 bits over 64) -#define SCMI_RESERVED_3_C146_REG_OFFSET 0x16dc +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_28_C0_REG_OFFSET 0x8c -// Defines wheter interrupts or polling is used for communication -#define SCMI_CHANNEL_FLAGS_C146_REG_OFFSET 0x16e0 -#define SCMI_CHANNEL_FLAGS_C146_INTR_ENABLE_BIT 0 -#define SCMI_CHANNEL_FLAGS_C146_FIELD1_MASK 0x7fffffff -#define SCMI_CHANNEL_FLAGS_C146_FIELD1_OFFSET 1 -#define SCMI_CHANNEL_FLAGS_C146_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_CHANNEL_FLAGS_C146_FIELD1_MASK, .index = SCMI_CHANNEL_FLAGS_C146_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_29_C0_REG_OFFSET 0x90 -// Lenght of payload + header -#define SCMI_LENGTH_C146_REG_OFFSET 0x16e4 +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_30_C0_REG_OFFSET 0x94 -// Defines which commanad the message contains -#define SCMI_MESSAGE_HEADER_C146_REG_OFFSET 0x16e8 -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_ID_OFFSET 0 -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C146_MESSAGE_ID_MASK, .index = SCMI_MESSAGE_HEADER_C146_MESSAGE_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_TYPE_MASK 0x3 -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_TYPE_OFFSET 8 -#define SCMI_MESSAGE_HEADER_C146_MESSAGE_TYPE_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C146_MESSAGE_TYPE_MASK, .index = SCMI_MESSAGE_HEADER_C146_MESSAGE_TYPE_OFFSET }) -#define SCMI_MESSAGE_HEADER_C146_PROTOCOL_ID_MASK 0xff -#define SCMI_MESSAGE_HEADER_C146_PROTOCOL_ID_OFFSET 10 -#define SCMI_MESSAGE_HEADER_C146_PROTOCOL_ID_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C146_PROTOCOL_ID_MASK, .index = SCMI_MESSAGE_HEADER_C146_PROTOCOL_ID_OFFSET }) -#define SCMI_MESSAGE_HEADER_C146_TOKEN_MASK 0x3ff -#define SCMI_MESSAGE_HEADER_C146_TOKEN_OFFSET 18 -#define SCMI_MESSAGE_HEADER_C146_TOKEN_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C146_TOKEN_MASK, .index = SCMI_MESSAGE_HEADER_C146_TOKEN_OFFSET }) -#define SCMI_MESSAGE_HEADER_C146_FIELD1_MASK 0xf -#define SCMI_MESSAGE_HEADER_C146_FIELD1_OFFSET 28 -#define SCMI_MESSAGE_HEADER_C146_FIELD1_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_MESSAGE_HEADER_C146_FIELD1_MASK, .index = SCMI_MESSAGE_HEADER_C146_FIELD1_OFFSET }) +// memory region dedicated to the parameters of the commands and their +// returns +#define SCMI_MESSAGE_PAYLOAD_31_C0_REG_OFFSET 0x98 // memory region dedicated to the parameters of the commands and their // returns -#define SCMI_MESSAGE_PAYLOAD_1_C146_REG_OFFSET 0x16ec +#define SCMI_MESSAGE_PAYLOAD_32_C0_REG_OFFSET 0x9c // Rapresents the interrupt to be raised towards the platform -#define SCMI_DOORBELL_C146_REG_OFFSET 0x16f0 -#define SCMI_DOORBELL_C146_INTR_BIT 0 -#define SCMI_DOORBELL_C146_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_DOORBELL_C146_PRESERVE_MASK_OFFSET 1 -#define SCMI_DOORBELL_C146_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_DOORBELL_C146_PRESERVE_MASK_MASK, .index = SCMI_DOORBELL_C146_PRESERVE_MASK_OFFSET }) +#define SCMI_DOORBELL_C0_REG_OFFSET 0xa0 // Rapresent the interrupt the platform should raise when it finishes to // execute the received command -#define SCMI_COMPLETION_INTERRUPT_C146_REG_OFFSET 0x16f4 -#define SCMI_COMPLETION_INTERRUPT_C146_INTR_BIT 0 -#define SCMI_COMPLETION_INTERRUPT_C146_PRESERVE_MASK_MASK 0x7fffffff -#define SCMI_COMPLETION_INTERRUPT_C146_PRESERVE_MASK_OFFSET 1 -#define SCMI_COMPLETION_INTERRUPT_C146_PRESERVE_MASK_FIELD \ - ((bitfield_field32_t) { .mask = SCMI_COMPLETION_INTERRUPT_C146_PRESERVE_MASK_MASK, .index = SCMI_COMPLETION_INTERRUPT_C146_PRESERVE_MASK_OFFSET }) +#define SCMI_COMPLETION_INTERRUPT_C0_REG_OFFSET 0xa4 #ifdef __cplusplus } // extern "C" diff --git a/tb/fpga/tb_mbox_fpga.sv b/tb/fpga/tb_mbox_fpga.sv index 123053b..defad42 100644 --- a/tb/fpga/tb_mbox_fpga.sv +++ b/tb/fpga/tb_mbox_fpga.sv @@ -154,12 +154,21 @@ module tb_mbox_fpga; @(posedge fixt_pms_fpga.s_soc_clk); fixt_pms_fpga.write_to_pulp32(axi_addr32, data, resp); + // ring the completion + axi_addr32=32'hA600_00a4; + data=32'h0000_0001; + $display("[TB] %t - writing to mailbox completion register",$realtime); + @(posedge fixt_pms_fpga.s_soc_clk); + fixt_pms_fpga.write_to_pulp32(axi_addr32, data, resp); + // ring the doorbell - axi_addr32=32'hA600_0020; + axi_addr32=32'hA600_00a0; data=32'h0000_0001; $display("[TB] %t - writing to mailbox doorbell register",$realtime); @(posedge fixt_pms_fpga.s_soc_clk); fixt_pms_fpga.write_to_pulp32(axi_addr32, data, resp); #1000us; + + end endmodule