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<!DOCTYPE html>
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<title>Preethi Budi — Hardware Validation Engineer</title>
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<body>
<nav>
<div class="wrap">
<span class="nav-mark">PB / validation-log</span>
<div class="nav-links">
<a href="#about">about</a>
<a href="#experience">experience</a>
<span class="hide-mobile"><a href="#projects">projects</a></span>
<span class="hide-mobile"><a href="#skills">skills</a></span>
<a href="#education">education</a>
<a href="#contact">contact</a>
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<header class="hero">
<div class="wrap">
<div class="eyebrow">Signal locked</div>
<h1>Preethi Budi</h1>
<p class="role">Hardware Electrical Validation Engineer — <strong>post-silicon characterization, signal integrity & validation automation</strong></p>
<p class="location">San Jose, California · MS ECE, University of Florida · GPA 3.79/4.00</p>
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</svg>
<div class="cta-row">
<a class="btn primary" href="https://www.linkedin.com/in/preethi-budi" target="_blank" rel="noopener">LinkedIn ↗</a>
<a class="btn" href="https://github.com/preethi-github-29" target="_blank" rel="noopener">GitHub ↗</a>
</div>
</div>
</header>
<section id="about">
<div class="wrap">
<div class="sec-head"><span class="sec-num">01</span><h2>About</h2></div>
<div class="about">
<p>I'm committed to mastering the full hardware development path — architecture, design, verification, and validation. Semiconductors aren't just my interest; they're the ecosystem I want to grow in and contribute to.</p>
</div>
</div>
</section>
<section id="experience">
<div class="wrap">
<div class="sec-head"><span class="sec-num">02</span><h2>Experience</h2></div>
<div class="entry">
<div class="entry-date">Jan 2026 — Apr 2026</div>
<div>
<p class="entry-role">Hardware Electrical Validation Engineer Intern</p>
<p class="entry-company">Astera Labs</p>
<p class="entry-loc">San Jose, CA</p>
<ul>
<li>Performed post-silicon electrical validation and characterization of high-speed interconnect hardware (retimers, active cable modules), including PCIe and SerDes signal paths, using oscilloscopes, signal source analyzers, and lab instrumentation.</li>
<li>Validated power delivery across multiple rails by characterizing DC/DC regulators and clock synthesizers under varying load, voltage/current margins (±5%, ±10%), frequency, and thermal conditions.</li>
<li>Developed Python-based automation to control lab setups and collect characterization data, improving repeatability of silicon validation workflows and accelerating cross-functional debug.</li>
<li>Executed low-speed logic validation for I²C and JTAG, correlating digital transaction traces with analog signal integrity measurements across operating corners.</li>
<li>Ran comprehensive power-rail validation including all-GPIO and DPM power sequencing checks to guarantee safe bring-up.</li>
</ul>
</div>
</div>
<div class="entry">
<div class="entry-date">May 2025 — Aug 2025</div>
<div>
<p class="entry-role">FPGA/ML Intern</p>
<p class="entry-company">Flapmax</p>
<p class="entry-loc">Tampa, FL</p>
<ul>
<li>Benchmarked Day-0 vision models (ResNet-50, MobileNet, YOLO, UNET, i3d) on Agilex 3/5 FPGAs using FPGA AI Suite and OpenVINO, profiling latency, throughput, power, and resource utilization.</li>
<li>Designed and deployed a custom FPGA inference pipeline for the Granite-4 Tiny Preview model, optimizing CPU baselines with OpenVINO and synthesizing kernel offloads in Quartus Prime Pro.</li>
<li>Implemented INT4/INT8 quantized inference and sparsification, validating cycle-accurate performance via SystemVerilog HLS and Intel CoFluent prior to Agilex-5 hardware deployment.</li>
</ul>
</div>
</div>
<div class="entry">
<div class="entry-date">Feb 2024 — Jul 2024</div>
<div>
<p class="entry-role">Electrical Engineer Intern</p>
<p class="entry-company">Honeywell Technology Solutions</p>
<p class="entry-loc">Bengaluru, Karnataka, India</p>
<ul>
<li>Analyzed PCIe-based schematic layouts for optimal component placement and signal routing to improve signal integrity and reliability.</li>
<li>Ran SI/PI/EMI/EMC design rule checks on high-speed hardware systems using HyperLynx and Altium.</li>
<li>Verified design compliance against custom DRC thresholds, resolving violations and iteratively revising layouts.</li>
</ul>
</div>
</div>
</div>
</section>
<section id="projects">
<div class="wrap">
<div class="sec-head"><span class="sec-num">03</span><h2>Projects</h2></div>
<div class="proj-grid">
<div class="proj-card">
<p class="proj-title">Multi-Level Cache & Memory Hierarchy Simulator</p>
<p class="proj-stack">C++ · Python · Cache Coherency</p>
<ul>
<li>Built a two-level cache and memory simulator with LRU and RR replacement policies to explore architectural behaviors.</li>
<li>Evaluated performance under varying cache parameters, including block size, associativity, and write policies.</li>
</ul>
</div>
<div class="proj-card">
<p class="proj-title">1-D Time Convolution Using Zynq ZedBoard</p>
<p class="proj-stack">VHDL · Xilinx Zynq-7000 SoC · Vivado · Linux</p>
<ul>
<li>Developed a custom 1-D convolution circuit in VHDL on a Zynq-7000 SoC with ARM processor and DMA for real-time signal processing.</li>
<li>Accelerated convolution computation by 14× using parallel processing within the FPGA fabric.</li>
</ul>
</div>
<div class="proj-card">
<p class="proj-title">8-bit SRAM Block</p>
<p class="proj-stack">Cadence Virtuoso · CMOS Design</p>
<ul>
<li>Designed a 4x2 SRAM block in Cadence Virtuoso with a 6T cell layout enabling read, write, and data storage operations.</li>
<li>Performed access time and delay analysis for read/write operations to ensure timing reliability.</li>
</ul>
</div>
<div class="proj-card">
<p class="proj-title">PN Junction Diode Fabrication Using Thermal Diffusion</p>
<p class="proj-stack">KLayout · CMOS Fabrication</p>
<ul>
<li>Fabricated a PN junction diode via thermal diffusion of dopants; characterized I-V response for performance analysis.</li>
<li>Applied photolithography and oxide passivation techniques for junction definition and reliability enhancement.</li>
</ul>
</div>
</div>
</div>
</section>
<section id="skills">
<div class="wrap">
<div class="sec-head"><span class="sec-num">04</span><h2>Skills & Tools</h2></div>
<div class="panel">
<div class="panel-label">Core</div>
<div class="tag-row">
<span class="tag core">System Stability Analysis</span>
<span class="tag core">Retimers</span>
<span class="tag core">Data Logging & Analysis</span>
<span class="tag core">Silicon Validation</span>
</div>
</div>
<div class="panel">
<div class="panel-label">Programming / Scripting</div>
<div class="tag-row">
<span class="tag">Python</span>
<span class="tag">Verilog</span>
<span class="tag">VHDL</span>
<span class="tag">TCL</span>
<span class="tag">SystemVerilog</span>
</div>
</div>
<div class="panel">
<div class="panel-label">Simulation / CAD Tools</div>
<div class="tag-row">
<span class="tag">Cadence Virtuoso Layout XL</span>
<span class="tag">Xilinx Vivado</span>
<span class="tag">ModelSim</span>
<span class="tag">Synopsys VCS</span>
<span class="tag">LTspice</span>
<span class="tag">QUCS</span>
<span class="tag">GNU Radio</span>
<span class="tag">DSCH2</span>
<span class="tag">HyperLynx DRC</span>
<span class="tag">Altium</span>
<span class="tag">MATLAB</span>
<span class="tag">OpenVINO</span>
<span class="tag">Intel FPGA AI Suite</span>
<span class="tag">Quartus Prime Pro</span>
</div>
</div>
<div class="panel">
<div class="panel-label">Analog / Digital Design Expertise</div>
<div class="tag-row">
<span class="tag">RTL Design</span>
<span class="tag">Static Timing Analysis</span>
<span class="tag">Clocking Analysis</span>
<span class="tag">Schematic Designing</span>
<span class="tag">BOM</span>
<span class="tag">Layout vs Schematic Debug</span>
<span class="tag">Design Rule Check (DRC)</span>
<span class="tag">Oscilloscopes</span>
<span class="tag">PCIe</span>
</div>
</div>
<div class="panel">
<div class="panel-label">Operating Systems</div>
<div class="tag-row">
<span class="tag">Linux</span>
<span class="tag">Virtual Machine</span>
<span class="tag">Windows</span>
</div>
</div>
<div class="panel">
<div class="panel-label">Domain Knowledge</div>
<div class="tag-row">
<span class="tag">Electrical Engineering</span>
<span class="tag">Computer Engineering</span>
<span class="tag">Silicon Validation</span>
<span class="tag">Data Analysis</span>
</div>
</div>
</div>
</section>
<section id="education">
<div class="wrap">
<div class="sec-head"><span class="sec-num">05</span><h2>Education</h2></div>
<div class="edu-entry">
<div class="entry-date">2024 — Aug 2026</div>
<div>
<p class="edu-school">University of Florida</p>
<p class="edu-degree">MS, Electrical and Computer Engineering · GPA 3.79/4.00</p>
<p class="edu-degree">Coursework: Reconfigurable Computing, Hands-on Hardware Security, Semiconductor Fabrication Lab, VLSI Design, Computer Architecture</p>
</div>
</div>
<div class="edu-entry">
<div class="entry-date">2020 — 2024</div>
<div>
<p class="edu-school">Amrita Vishwa Vidyapeetham</p>
<p class="edu-degree">BTech, Electrical, Electronics and Communications Engineering</p>
</div>
</div>
</div>
</section>
<section id="certifications">
<div class="wrap">
<div class="sec-head"><span class="sec-num">06</span><h2>Certifications</h2></div>
<ul class="plain-list">
<li>SystemVerilog For RTL Design Exam</li>
<li>Introduction to MicroPython and Physical Computing</li>
<li>Certificate of Recognition — Semiconductor Education Day (UF FSI)</li>
</ul>
</div>
</section>
<section id="publications">
<div class="wrap">
<div class="sec-head"><span class="sec-num">07</span><h2>Publications</h2></div>
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<li><a href="https://ieeexplore.ieee.org/document/10560174" target="_blank" rel="noopener">Design and Implementation of an Efficient 32-Bit Fixed-Point Newton-Raphson Division-Based Reciprocal Computing Unit ↗</a></li>
<li><a href="https://dl.acm.org/doi/10.1145/3748173.3779569" target="_blank" rel="noopener">RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines — An Industry Evaluation of Control-Plane Bottlenecks and Sustained Throughput Metrics ↗</a></li>
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