|
1 | 1 | /* |
2 | 2 | ** ################################################################### |
3 | 3 | ** Version: rev. 1.0, 2017-12-15 |
4 | | -** Build: b190225 |
| 4 | +** Build: b211029 |
5 | 5 | ** |
6 | 6 | ** Abstract: |
7 | 7 | ** Chip specific module features. |
8 | 8 | ** |
9 | 9 | ** Copyright 2016 Freescale Semiconductor, Inc. |
10 | | -** Copyright 2016-2019 NXP |
| 10 | +** Copyright 2016-2021 NXP |
11 | 11 | ** All rights reserved. |
12 | 12 | ** |
13 | 13 | ** SPDX-License-Identifier: BSD-3-Clause |
|
77 | 77 | /* ADC module features */ |
78 | 78 |
|
79 | 79 | /* @brief Do not has input select (register INSEL). */ |
80 | | -#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) |
| 80 | +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) |
81 | 81 | /* @brief Has ASYNMODE bitfile in CTRL reigster. */ |
82 | 82 | #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) |
83 | 83 | /* @brief Has ASYNMODE bitfile in CTRL reigster. */ |
|
92 | 92 | #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) |
93 | 93 | /* @brief Has startup register. */ |
94 | 94 | #define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) |
95 | | -/* @brief Has ADTrim register */ |
| 95 | +/* @brief Has ADC Trim register */ |
96 | 96 | #define FSL_FEATURE_ADC_HAS_TRIM_REG (0) |
97 | 97 | /* @brief Has Calibration register. */ |
98 | 98 | #define FSL_FEATURE_ADC_HAS_CALIB_REG (1) |
99 | 99 |
|
| 100 | +/* CTIMER module features */ |
| 101 | + |
| 102 | +/* No feature definitions */ |
| 103 | + |
100 | 104 | /* DMA module features */ |
101 | 105 |
|
102 | 106 | /* @brief Number of channels */ |
|
109 | 113 | /* FLEXCOMM module features */ |
110 | 114 |
|
111 | 115 | /* @brief FLEXCOMM0 USART INDEX 0 */ |
112 | | -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) |
| 116 | +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) |
113 | 117 | /* @brief FLEXCOMM0 SPI INDEX 0 */ |
114 | | -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) |
| 118 | +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) |
115 | 119 | /* @brief FLEXCOMM0 I2C INDEX 0 */ |
116 | | -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) |
| 120 | +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) |
117 | 121 | /* @brief FLEXCOMM1 USART INDEX 1 */ |
118 | | -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) |
| 122 | +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) |
119 | 123 | /* @brief FLEXCOMM1 SPI INDEX 1 */ |
120 | | -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) |
| 124 | +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) |
121 | 125 | /* @brief FLEXCOMM1 I2C INDEX 1 */ |
122 | | -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) |
| 126 | +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) |
123 | 127 | /* @brief FLEXCOMM2 USART INDEX 2 */ |
124 | | -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) |
| 128 | +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) |
125 | 129 | /* @brief FLEXCOMM2 SPI INDEX 2 */ |
126 | | -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) |
| 130 | +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) |
127 | 131 | /* @brief FLEXCOMM2 I2C INDEX 2 */ |
128 | | -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) |
| 132 | +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) |
129 | 133 | /* @brief FLEXCOMM3 USART INDEX 3 */ |
130 | | -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) |
| 134 | +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) |
131 | 135 | /* @brief FLEXCOMM3 SPI INDEX 3 */ |
132 | | -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) |
| 136 | +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) |
133 | 137 | /* @brief FLEXCOMM3 I2C INDEX 3 */ |
134 | | -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) |
| 138 | +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) |
135 | 139 | /* @brief FLEXCOMM4 USART INDEX 4 */ |
136 | | -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) |
| 140 | +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) |
137 | 141 | /* @brief FLEXCOMM4 SPI INDEX 4 */ |
138 | | -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) |
| 142 | +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) |
139 | 143 | /* @brief FLEXCOMM4 I2C INDEX 4 */ |
140 | | -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) |
| 144 | +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) |
141 | 145 | /* @brief FLEXCOMM5 USART INDEX 5 */ |
142 | | -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) |
| 146 | +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) |
143 | 147 | /* @brief FLEXCOMM5 SPI INDEX 5 */ |
144 | | -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) |
| 148 | +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) |
145 | 149 | /* @brief FLEXCOMM5 I2C INDEX 5 */ |
146 | | -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) |
| 150 | +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) |
147 | 151 | /* @brief FLEXCOMM6 USART INDEX 6 */ |
148 | | -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) |
| 152 | +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) |
149 | 153 | /* @brief FLEXCOMM6 SPI INDEX 6 */ |
150 | | -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) |
| 154 | +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) |
151 | 155 | /* @brief FLEXCOMM6 I2C INDEX 6 */ |
152 | | -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) |
| 156 | +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) |
153 | 157 | /* @brief FLEXCOMM7 I2S INDEX 0 */ |
154 | | -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) |
| 158 | +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) |
155 | 159 | /* @brief FLEXCOMM7 USART INDEX 7 */ |
156 | | -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) |
| 160 | +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) |
157 | 161 | /* @brief FLEXCOMM7 SPI INDEX 7 */ |
158 | | -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) |
| 162 | +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) |
159 | 163 | /* @brief FLEXCOMM7 I2C INDEX 7 */ |
160 | | -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) |
| 164 | +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) |
161 | 165 | /* @brief FLEXCOMM7 I2S INDEX 1 */ |
162 | | -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) |
| 166 | +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) |
163 | 167 | /* @brief I2S has DMIC interconnection */ |
164 | 168 | #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) |
165 | 169 |
|
166 | 170 | /* I2S module features */ |
167 | 171 |
|
168 | | -/* @brief I2S support dual channel transfer */ |
| 172 | +/* @brief I2S support dual channel transfer. */ |
169 | 173 | #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) |
170 | 174 | /* @brief I2S has DMIC interconnection */ |
171 | | -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) |
| 175 | +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) |
| 176 | + |
| 177 | +/* IOCON module features */ |
| 178 | + |
| 179 | +/* @brief Func bit field width */ |
| 180 | +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (3) |
172 | 181 |
|
173 | 182 | /* MRT module features */ |
174 | 183 |
|
175 | 184 | /* @brief number of channels. */ |
176 | | -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) |
| 185 | +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) |
177 | 186 |
|
178 | 187 | /* interrupt module features */ |
179 | 188 |
|
|
207 | 216 |
|
208 | 217 | /* @brief Pointer to ROM IAP entry functions */ |
209 | 218 | #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) |
| 219 | +/* @brief IAP Reinvoke ISP command parameter is pointer */ |
| 220 | +#define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) |
210 | 221 | /* @brief Flash page size in bytes */ |
211 | 222 | #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) |
212 | 223 | /* @brief Flash sector size in bytes */ |
|
232 | 243 | /* @brief Number of the endpoint in USB FS */ |
233 | 244 | #define FSL_FEATURE_USB_EP_NUM (5) |
234 | 245 |
|
235 | | -#endif /* _LPC51U68_FEATURES_H_ */ |
| 246 | +/* WWDT module features */ |
| 247 | + |
| 248 | +/* @brief Has no RESET register. */ |
| 249 | +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) |
236 | 250 |
|
| 251 | +#endif /* _LPC51U68_FEATURES_H_ */ |
0 commit comments