Merge pull request #7 from robert-hh/v2.11

nxp_driver: Update the MIMXRT devices lib to v2.11.

Author: hathach

sdk/devices/MIMXRT1011/MIMXRT1011.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.0, 2019-08-01
-**     Build:               b200311
+**     Build:               b211108
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2020 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -87,8 +87,6 @@
 #define FSL_FEATURE_SOC_PMU_COUNT (1)
 /* @brief PWM availability on the SoC. */
 #define FSL_FEATURE_SOC_PWM_COUNT (1)
-/* @brief ROMC availability on the SoC. */
-#define FSL_FEATURE_SOC_ROMC_COUNT (1)
 /* @brief SNVS availability on the SoC. */
 #define FSL_FEATURE_SOC_SNVS_COUNT (1)
 /* @brief SPDIF availability on the SoC. */
@@ -129,6 +127,10 @@
 #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
 /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
 #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
+/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
+#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1)
+/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
+#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1)
 
 /* AOI module features */
 
@@ -177,17 +179,21 @@
 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
 /* @brief If 16 bytes transfer supported. */
 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
+/* @brief If 32 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
 
 /* DMAMUX module features */
 
 /* @brief Number of DMA channels (related to number of register CHCFGn). */
 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
 /* @brief Total number of DMA channels on all modules. */
-#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16)
 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
+/* @brief Register CHCFGn width. */
+#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
 
 /* EWM module features */
 
@@ -229,6 +235,8 @@
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4)
 /* @brief Has FLEXRAM_MAGIC_ADDR. */
 #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
+/* @brief If FLEXRAM has ECC function. */
+#define FSL_FEATURE_FLEXRAM_HAS_ECC (0)
 
 /* FLEXSPI module features */
 
@@ -280,6 +288,8 @@
 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
 /* @brief Has separate DMA RX and TX requests. */
 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has CCR1 (related to existence of registers CCR1). */
+#define FSL_FEATURE_LPSPI_HAS_CCR1 (0)
 
 /* LPUART module features */
 
@@ -315,10 +325,6 @@
 #define FSL_FEATURE_LPUART_IS_SCI (1)
 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
-/* @brief Maximal data width without parity bit. */
-#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
-/* @brief Maximal data width with parity bit. */
-#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
 /* @brief Supports two match addresses to filter incoming frames. */
 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
@@ -365,8 +371,6 @@
 #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1)
 /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
 #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0)
-/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
-#define FSL_FEATURE_OCOTP_HAS_STATUS (0)
 
 /* OTFAD module features */
 
@@ -375,7 +379,7 @@
 /* @brief OTFAD has Key Blob Processing */
 #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (1)
 /* @brief OTFAD has interrupt request enable */
-#define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (1)
+#define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (0)
 /* @brief OTFAD has Force Error */
 #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (1)
 
@@ -394,14 +398,20 @@
 
 /* PWM module features */
 
-/* @brief If EflexPWM has module A channels (outputs). */
+/* @brief If (e)FlexPWM has module A channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELA (1)
-/* @brief If EflexPWM has module B channels (outputs). */
+/* @brief If (e)FlexPWM has module B channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELB (1)
-/* @brief If EflexPWM has module X channels (outputs). */
+/* @brief If (e)FlexPWM has module X channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELX (1)
-/* @brief Number of submodules in each EflexPWM module. */
+/* @brief If (e)FlexPWM has fractional feature. */
+#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
+/* @brief If (e)FlexPWM has mux trigger source select bit field. */
+#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
+/* @brief Number of submodules in each (e)FlexPWM module. */
 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
+/* @brief Number of fault channel in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
 
 /* RTWDOG module features */
 
@@ -451,6 +461,12 @@
 
 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
 #define FSL_FEATURE_SNVS_HAS_SRTC (1)
+/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
+#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (1)
+/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
+#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0)
+/* @brief Number of TAMPER. */
+#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0)
 
 /* SRC module features */
 
@@ -534,6 +550,8 @@
 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
 /* @brief USBPHY has register TRIM_OVERRIDE_EN */
 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0)
+/* @brief USBPHY is 28FDSOI */
+#define FSL_FEATURE_USBPHY_28FDSOI (0)
 
 /* XBARA module features */
 

sdk/devices/MIMXRT1011/MIMXRT1011.xml

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpi2c component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpi2c_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpi2c_edma_MIMXRT1011)
+
+include(driver_lpi2c_MIMXRT1011)
+
+include(CMSIS_Driver_Include_I2C_MIMXRT1011)
+

sdk/devices/MIMXRT1011/MIMXRT1011_features.h

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpspi component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpspi_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpspi_edma_MIMXRT1011)
+
+include(driver_lpspi_MIMXRT1011)
+
+include(CMSIS_Driver_Include_SPI_MIMXRT1011)
+

sdk/devices/MIMXRT1011/cmsis_drivers/driver_cmsis_lpi2c_MIMXRT1011.cmake

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpuart component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpuart_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpuart_edma_MIMXRT1011)
+
+include(driver_lpuart_MIMXRT1011)
+
+include(CMSIS_Driver_Include_USART_MIMXRT1011)
+