Support peripheral register addresses of ESP32-S2/S3

wnienhaus · wnienhaus · commit d2cd7923cfeb · 2023-08-30T21:48:17.000+03:00
Peripheral registers of the ESP32-S2 and S3 are at a different
location than those of the original ESP32. The location within
the address space is mostly the same, however we need to use
the correct base address when calculating periph_sel (type of
register) used in REG_RD and REG_WR instructions.

Note 1: To avoid creating an entirely new CPU (esp32s3) just for
handling the different peripheral register addresses of the S3,
while their binary format (instruction set) is identical, our
esp32s2 CPU support will now accept both ESP32-S2 and ESP32-S3
addresses. This should make a binary for the one seamlessly
work on the other (without reassembly), given that the offsets
of different peripheral registers between the S2 and S3 are
mostly (but not entirely) identical.

Note 2: Our esp32s2 cpu support will also accept peripheral
register addresses of the original ESP32. This was originally
done because Espressif's binutils-gdb/esp32-ulp-as incorrectly
validates addresses for the esp32s2 cpu, and to make our compat
tests pass, this was needed. However this also has a nice side-
effect of allowing some assembly written for the original ESP32
to work unmodified when assembled for an S2/S3, because some of
the peripheral registers live at the same offset from the base
for all three variants.
diff --git a/esp32_ulp/opcodes_s2.py b/esp32_ulp/opcodes_s2.py
@@ -5,7 +5,6 @@
 from ucollections import namedtuple
 from uctypes import struct, addressof, LITTLE_ENDIAN, UINT32, BFUINT32, BF_POS, BF_LEN
 
-from .soc import *
 from .util import split_tokens, validate_expression
 
 # XXX dirty hack: use a global for the symbol table
@@ -374,16 +373,43 @@ def get_cond(arg):
 
 
 def _soc_reg_to_ulp_periph_sel(reg):
+    # Accept peripheral register addresses of either the S2 or S3
+    # Since the address in the reg_rd or reg_wr instruction is an
+    # offset and not the actual address, and since the range of
+    # peripheral register addresses is the same for both the S2
+    # and S3, we will accept addresses in either address range.
+    # This allows us to avoid intruducing an additional cpu type
+    # for the S3, which is otherwise identical (binary format) to
+    # the S2.
+    if 0x3f408000 <= reg <= 0x3f40afff:  # ESP32-S2 address range
+        socmod = 'soc_s2'
+    elif 0x60008000 <= reg <= 0x6000afff:  # ESP32-S3 address range
+        socmod = 'soc_s3'
+    # Accept original ESP32 range too
+    # because binutils-gdb, when using cpu esp32s2 is broken
+    # and does not accept the address ranges of the esp32s2.
+    # As a nice side-effect some assembly written for an ESP32
+    # would work as-is when re-assembled for an ESP32-S2,
+    # because many (not all!) peripheral registers live at the
+    # same offset on all 3 ESP32s.
+    elif 0x3ff48000 <= reg <= 0x3ff4afff:  # original ESP32 address range
+        socmod = 'soc'
+    else:
+        raise ValueError("invalid register base")
+
+    relative_import = 1 if '/' in __file__ else 0
+    soc = __import__(socmod, None, None, [], relative_import)
+
     # Map SoC peripheral register to periph_sel field of RD_REG and WR_REG instructions.
-    if reg < DR_REG_RTCCNTL_BASE:
+    if reg < soc.DR_REG_RTCCNTL_BASE:
         raise ValueError("invalid register base")
-    elif reg < DR_REG_RTCIO_BASE:
+    elif reg < soc.DR_REG_RTCIO_BASE:
         ret = RD_REG_PERIPH_RTC_CNTL
-    elif reg < DR_REG_SENS_BASE:
+    elif reg < soc.DR_REG_SENS_BASE:
         ret = RD_REG_PERIPH_RTC_IO
-    elif reg < DR_REG_RTC_I2C_BASE:
+    elif reg < soc.DR_REG_RTC_I2C_BASE:
         ret = RD_REG_PERIPH_SENS
-    elif reg < DR_REG_IO_MUX_BASE:
+    elif reg < soc.DR_REG_IO_MUX_BASE:
         ret = RD_REG_PERIPH_RTC_I2C
     else:
         raise ValueError("invalid register base")
diff --git a/esp32_ulp/soc_s2.py b/esp32_ulp/soc_s2.py
@@ -0,0 +1,64 @@
+"""
+Address / Register definitions for the ESP32-S2 SoC
+"""
+
+# Reference:
+# https://github.com/espressif/esp-idf/blob/v5.0.2/components/soc/esp32s2/include/soc/reg_base.h
+
+DR_REG_SYSTEM_BASE                      = 0x3f4c0000
+DR_REG_SENSITIVE_BASE                   = 0x3f4c1000
+DR_REG_INTERRUPT_BASE                   = 0x3f4c2000
+DR_REG_DMA_COPY_BASE                    = 0x3f4c3000
+DR_REG_EXTMEM_BASE                      = 0x61800000
+DR_REG_MMU_TABLE                        = 0x61801000
+DR_REG_ITAG_TABLE                       = 0x61802000
+DR_REG_DTAG_TABLE                       = 0x61803000
+DR_REG_AES_BASE                         = 0x6003a000
+DR_REG_SHA_BASE                         = 0x6003b000
+DR_REG_RSA_BASE                         = 0x6003c000
+DR_REG_HMAC_BASE                        = 0x6003e000
+DR_REG_DIGITAL_SIGNATURE_BASE           = 0x6003d000
+DR_REG_CRYPTO_DMA_BASE                  = 0x6003f000
+DR_REG_ASSIST_DEBUG_BASE                = 0x3f4ce000
+DR_REG_DEDICATED_GPIO_BASE              = 0x3f4cf000
+DR_REG_INTRUSION_BASE                   = 0x3f4d0000
+DR_REG_UART_BASE                        = 0x3f400000
+DR_REG_SPI1_BASE                        = 0x3f402000
+DR_REG_SPI0_BASE                        = 0x3f403000
+DR_REG_GPIO_BASE                        = 0x3f404000
+DR_REG_GPIO_SD_BASE                     = 0x3f404f00
+DR_REG_FE2_BASE                         = 0x3f405000
+DR_REG_FE_BASE                          = 0x3f406000
+DR_REG_FRC_TIMER_BASE                   = 0x3f407000
+DR_REG_RTCCNTL_BASE                     = 0x3f408000
+DR_REG_RTCIO_BASE                       = 0x3f408400
+DR_REG_SENS_BASE                        = 0x3f408800
+DR_REG_RTC_I2C_BASE                     = 0x3f408C00
+DR_REG_IO_MUX_BASE                      = 0x3f409000
+DR_REG_HINF_BASE                        = 0x3f40B000
+DR_REG_I2S_BASE                         = 0x3f40F000
+DR_REG_UART1_BASE                       = 0x3f410000
+DR_REG_I2C_EXT_BASE                     = 0x3f413000
+DR_REG_UHCI0_BASE                       = 0x3f414000
+DR_REG_SLCHOST_BASE                     = 0x3f415000
+DR_REG_RMT_BASE                         = 0x3f416000
+DR_REG_PCNT_BASE                        = 0x3f417000
+DR_REG_SLC_BASE                         = 0x3f418000
+DR_REG_LEDC_BASE                        = 0x3f419000
+DR_REG_CP_BASE                          = 0x3f4c3000
+DR_REG_EFUSE_BASE                       = 0x3f41A000
+DR_REG_NRX_BASE                         = 0x3f41CC00
+DR_REG_BB_BASE                          = 0x3f41D000
+DR_REG_TIMERGROUP0_BASE                 = 0x3f41F000
+DR_REG_TIMERGROUP1_BASE                 = 0x3f420000
+DR_REG_RTC_SLOWMEM_BASE                 = 0x3f421000
+DR_REG_SYSTIMER_BASE                    = 0x3f423000
+DR_REG_SPI2_BASE                        = 0x3f424000
+DR_REG_SPI3_BASE                        = 0x3f425000
+DR_REG_SYSCON_BASE                      = 0x3f426000
+DR_REG_APB_CTRL_BASE                    = 0x3f426000  # Old name for SYSCON, to be removed
+DR_REG_I2C1_EXT_BASE                    = 0x3f427000
+DR_REG_SPI4_BASE                        = 0x3f437000
+DR_REG_USB_WRAP_BASE                    = 0x3f439000
+DR_REG_APB_SARADC_BASE                  = 0x3f440000
+DR_REG_USB_BASE                         = 0x60080000
diff --git a/esp32_ulp/soc_s3.py b/esp32_ulp/soc_s3.py
@@ -0,0 +1,66 @@
+"""
+Address / Register definitions for the ESP32-S3 SoC
+"""
+
+# Reference:
+# https://github.com/espressif/esp-idf/blob/v5.0.2/components/soc/esp32s3/include/soc/reg_base.h
+
+DR_REG_UART_BASE                        = 0x60000000
+DR_REG_SPI1_BASE                        = 0x60002000
+DR_REG_SPI0_BASE                        = 0x60003000
+DR_REG_GPIO_BASE                        = 0x60004000
+DR_REG_GPIO_SD_BASE                     = 0x60004f00
+DR_REG_FE2_BASE                         = 0x60005000
+DR_REG_FE_BASE                          = 0x60006000
+DR_REG_EFUSE_BASE                       = 0x60007000
+DR_REG_RTCCNTL_BASE                     = 0x60008000
+DR_REG_RTCIO_BASE                       = 0x60008400
+DR_REG_SENS_BASE                        = 0x60008800
+DR_REG_RTC_I2C_BASE                     = 0x60008C00
+DR_REG_IO_MUX_BASE                      = 0x60009000
+DR_REG_HINF_BASE                        = 0x6000B000
+DR_REG_UHCI1_BASE                       = 0x6000C000
+DR_REG_I2S_BASE                         = 0x6000F000
+DR_REG_UART1_BASE                       = 0x60010000
+DR_REG_BT_BASE                          = 0x60011000
+DR_REG_I2C_EXT_BASE                     = 0x60013000
+DR_REG_UHCI0_BASE                       = 0x60014000
+DR_REG_SLCHOST_BASE                     = 0x60015000
+DR_REG_RMT_BASE                         = 0x60016000
+DR_REG_PCNT_BASE                        = 0x60017000
+DR_REG_SLC_BASE                         = 0x60018000
+DR_REG_LEDC_BASE                        = 0x60019000
+DR_REG_NRX_BASE                         = 0x6001CC00
+DR_REG_BB_BASE                          = 0x6001D000
+DR_REG_PWM0_BASE                        = 0x6001E000
+DR_REG_TIMERGROUP0_BASE                 = 0x6001F000
+DR_REG_TIMERGROUP1_BASE                 = 0x60020000
+DR_REG_RTC_SLOWMEM_BASE                 = 0x60021000
+DR_REG_SYSTIMER_BASE                    = 0x60023000
+DR_REG_SPI2_BASE                        = 0x60024000
+DR_REG_SPI3_BASE                        = 0x60025000
+DR_REG_SYSCON_BASE                      = 0x60026000
+DR_REG_APB_CTRL_BASE                    = 0x60026000  # Old name for SYSCON, to be removed
+DR_REG_I2C1_EXT_BASE                    = 0x60027000
+DR_REG_SDMMC_BASE                       = 0x60028000
+DR_REG_PERI_BACKUP_BASE                 = 0x6002A000
+DR_REG_TWAI_BASE                        = 0x6002B000
+DR_REG_PWM1_BASE                        = 0x6002C000
+DR_REG_I2S1_BASE                        = 0x6002D000
+DR_REG_UART2_BASE                       = 0x6002E000
+DR_REG_USB_SERIAL_JTAG_BASE             = 0x60038000
+DR_REG_USB_WRAP_BASE                    = 0x60039000
+DR_REG_AES_BASE                         = 0x6003A000
+DR_REG_SHA_BASE                         = 0x6003B000
+DR_REG_RSA_BASE                         = 0x6003C000
+DR_REG_HMAC_BASE                        = 0x6003E000
+DR_REG_DIGITAL_SIGNATURE_BASE           = 0x6003D000
+DR_REG_GDMA_BASE                        = 0x6003F000
+DR_REG_APB_SARADC_BASE                  = 0x60040000
+DR_REG_LCD_CAM_BASE                     = 0x60041000
+DR_REG_SYSTEM_BASE                      = 0x600C0000
+DR_REG_SENSITIVE_BASE                   = 0x600C1000
+DR_REG_INTERRUPT_BASE                   = 0x600C2000
+DR_REG_EXTMEM_BASE                      = 0x600C4000
+DR_REG_ASSIST_DEBUG_BASE                = 0x600CE000
+DR_REG_WCL_BASE                         = 0x600D0000
diff --git a/tests/opcodes_s2.py b/tests/opcodes_s2.py
@@ -149,9 +149,9 @@ def test_reg_direct_ulp_addressing():
     assert_raises(ValueError, opcodes.i_reg_rd, "0x400", "0", "0")
 
 
-def test_reg_address_translations():
+def test_reg_address_translations_s2():
     """
-    Test addressing of peripheral registers using full DPORT bus addresses
+    Test addressing of ESP32-S2 peripheral registers using full DPORT bus addresses
     """
 
     ins = make_ins("""
@@ -164,12 +164,37 @@ def test_reg_address_translations():
     """)
 
     # direct ULP address is derived from full address as follows:
-    # full:0x3ff484a8 == ulp:(0x3ff484a8-DR_REG_RTCCNTL_BASE) / 4
-    # full:0x3ff484a8 == ulp:(0x3ff484a8-0x3ff48000) / 4
-    # full:0x3ff484a8 == ulp:0x4a8 / 4
-    # full:0x3ff484a8 == ulp:0x12a
-    # see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32.c#L149
-    ins.all = opcodes.i_reg_rd("0x3ff484a8", "0", "0")
+    # full:0x3f4084a8 == ulp:(0x3f4084a8-DR_REG_RTCCNTL_BASE) / 4
+    # full:0x3f4084a8 == ulp:(0x3f4084a8-0x3f408000) / 4
+    # full:0x3f4084a8 == ulp:0x4a8 / 4
+    # full:0x3f4084a8 == ulp:0x12a
+    # see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32s2.c#L78
+    ins.all = opcodes.i_reg_rd("0x3f4084a8", "0", "0")
+    assert ins.periph_sel == 1  # high 2 bits of 0x12a
+    assert ins.addr == 0x2a  # low 8 bits of 0x12a
+
+
+def test_reg_address_translations_s3():
+    """
+    Test addressing of ESP32-S3 peripheral registers using full DPORT bus addresses
+    """
+
+    ins = make_ins("""
+    addr : 8        # Address within either RTC_CNTL, RTC_IO, or SARADC
+    periph_sel : 2  # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
+    unused : 8      # Unused
+    low : 5         # Low bit
+    high : 5        # High bit
+    opcode : 4      # Opcode (OPCODE_RD_REG)
+    """)
+
+    # direct ULP address is derived from full address as follows:
+    # full:0x600084a8 == ulp:(0x600084a8-DR_REG_RTCCNTL_BASE) / 4
+    # full:0x600084a8 == ulp:(0x600084a8-0x60008000) / 4
+    # full:0x600084a8 == ulp:0x4a8 / 4
+    # full:0x600084a8 == ulp:0x12a
+    # see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32s2.c#L78
+    ins.all = opcodes.i_reg_rd("0x600084a8", "0", "0")
     assert ins.periph_sel == 1  # high 2 bits of 0x12a
     assert ins.addr == 0x2a  # low 8 bits of 0x12a
 
@@ -182,4 +207,5 @@ def test_reg_address_translations():
 test_get_cond()
 test_eval_arg()
 test_reg_direct_ulp_addressing()
-test_reg_address_translations()
+test_reg_address_translations_s2()
+test_reg_address_translations_s3()
