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Add integration tests for disassembling all JUMPR/JUMPS conditions supported by the S2
The ESP32-S2 changes the comparison operators that are natively supported by the CPU for the JUMPR and JUMPS instruction. For the JUMPS instruction all comparison operators are now natively supported in hardware.
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5 files changed

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-55
lines changed

5 files changed

+128
-55
lines changed

‎tests/fixtures/all_opcodes-v.esp32.lst‎

Lines changed: 61 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
header
22
ULP magic : b'ulp\x00' (0x00706c75)
33
.text offset : 12 (0x0c)
4-
.text size : 164 (0xa4)
5-
.data offset : 176 (0xb0)
4+
.text size : 188 (0xbc)
5+
.data offset : 200 (0xc8)
66
.data size : 8 (0x08)
77
.bss size : 0 (0x00)
88
----------------------------------------
@@ -251,56 +251,102 @@ ULP magic : b'ulp\x00' (0x00706c75)
251251
opcode = 8
252252
sign = 0
253253
sub_opcode = 1
254-
0080 05000382 JUMPR 1, 5, GE
254+
0080 06000382 JUMPR 1, 6, GE
255255
cmp = 1 (GE)
256-
imm = 5
256+
imm = 6
257257
offset = 1
258258
opcode = 8
259259
sign = 0
260260
sub_opcode = 1
261-
0084 01000084 JUMPS 0, 1, LT
261+
0084 08000582 JUMPR 2, 8, GE
262+
cmp = 1 (GE)
263+
imm = 8
264+
offset = 2
265+
opcode = 8
266+
sign = 0
267+
sub_opcode = 1
268+
0088 07000582 JUMPR 2, 7, GE
269+
cmp = 1 (GE)
270+
imm = 7
271+
offset = 2
272+
opcode = 8
273+
sign = 0
274+
sub_opcode = 1
275+
008c 01000084 JUMPS 0, 1, LT
262276
cmp = 0 (LT)
263277
imm = 1
264278
offset = 0
265279
opcode = 8
266280
sign = 0
267281
sub_opcode = 2
268282
unused = 0
269-
0088 05800284 JUMPS 1, 5, GE
283+
0090 05000584 JUMPS 2, 5, LE
284+
cmp = 2 (LE)
285+
imm = 5
286+
offset = 2
287+
opcode = 8
288+
sign = 0
289+
sub_opcode = 2
290+
unused = 0
291+
0094 05800284 JUMPS 1, 5, GE
270292
cmp = 1 (GE)
271293
imm = 5
272294
offset = 1
273295
opcode = 8
274296
sign = 0
275297
sub_opcode = 2
276298
unused = 0
277-
008c 09000584 JUMPS 2, 9, LE
299+
0098 07000484 JUMPS 2, 7, LT
300+
cmp = 0 (LT)
301+
imm = 7
302+
offset = 2
303+
opcode = 8
304+
sign = 0
305+
sub_opcode = 2
306+
unused = 0
307+
009c 07000584 JUMPS 2, 7, LE
278308
cmp = 2 (LE)
279-
imm = 9
309+
imm = 7
280310
offset = 2
281311
opcode = 8
282312
sign = 0
283313
sub_opcode = 2
284314
unused = 0
285-
0090 01000090 WAKE
315+
00a0 09000784 JUMPS 3, 9, LE
316+
cmp = 2 (LE)
317+
imm = 9
318+
offset = 3
319+
opcode = 8
320+
sign = 0
321+
sub_opcode = 2
322+
unused = 0
323+
00a4 0b800884 JUMPS 4, 11, GE
324+
cmp = 1 (GE)
325+
imm = 11 (0x0b)
326+
offset = 4
327+
opcode = 8
328+
sign = 0
329+
sub_opcode = 2
330+
unused = 0
331+
00a8 01000090 WAKE
286332
opcode = 9
287333
sub_opcode = 0
288334
unused = 0
289335
wakeup = 1
290-
0094 07000092 SLEEP 7
336+
00ac 07000092 SLEEP 7
291337
cycle_sel = 7
292338
opcode = 9
293339
sub_opcode = 1
294340
unused = 0
295-
0098 090000a0 TSENS r1, 2
341+
00b0 090000a0 TSENS r1, 2
296342
delay = 2
297343
dreg = 1
298344
opcode = 10 (0x0a)
299345
unused = 0
300-
009c 000000b0 HALT
346+
00b4 000000b0 HALT
301347
opcode = 11 (0x0b)
302348
unused = 0
303-
00a0 060000d0 LD r2, r1, 0
349+
00b8 060000d0 LD r2, r1, 0
304350
dreg = 2
305351
offset = 0
306352
opcode = 13 (0x0d)
@@ -309,5 +355,5 @@ ULP magic : b'ulp\x00' (0x00706c75)
309355
unused2 = 0
310356
----------------------------------------
311357
.data
312-
00a4 00000000 <empty>
313-
00a8 fecadec0 <non-empty>
358+
00bc 00000000 <empty>
359+
00c0 fecadec0 <non-empty>

‎tests/fixtures/all_opcodes-v.esp32s2.lst‎

Lines changed: 32 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
header
22
ULP magic : b'ulp\x00' (0x00706c75)
33
.text offset : 12 (0x0c)
4-
.text size : 168 (0xa8)
5-
.data offset : 180 (0xb4)
4+
.text size : 176 (0xb0)
5+
.data offset : 188 (0xbc)
66
.data size : 8 (0x08)
77
.bss size : 0 (0x00)
88
----------------------------------------
@@ -278,10 +278,10 @@ ULP magic : b'ulp\x00' (0x00706c75)
278278
opcode = 8
279279
sign = 0
280280
sub_opcode = 0
281-
0084 05000680 JUMPR 1, 5, EQ
281+
0084 07000a80 JUMPR 2, 7, EQ
282282
cmp = 2 (EQ)
283-
imm = 5
284-
offset = 1
283+
imm = 7
284+
offset = 2
285285
opcode = 8
286286
sign = 0
287287
sub_opcode = 0
@@ -293,40 +293,56 @@ ULP magic : b'ulp\x00' (0x00706c75)
293293
sign = 0
294294
sub_opcode = 2
295295
unused = 0
296-
008c 05801388 JUMPS 4, 5, GE
297-
cmp = 7 (GE)
296+
008c 05801188 JUMPS 4, 5, GT
297+
cmp = 3 (GT)
298298
imm = 5
299299
offset = 4
300300
opcode = 8
301301
sign = 0
302302
sub_opcode = 2
303303
unused = 0
304-
0090 09802288 JUMPS 8, 9, LE
304+
0090 07002288 JUMPS 8, 7, EQ
305+
cmp = 4 (EQ)
306+
imm = 7
307+
offset = 8
308+
opcode = 8
309+
sign = 0
310+
sub_opcode = 2
311+
unused = 0
312+
0094 09803288 JUMPS 12, 9, LE
305313
cmp = 5 (LE)
306314
imm = 9
307-
offset = 8
315+
offset = 12 (0x0c)
316+
opcode = 8
317+
sign = 0
318+
sub_opcode = 2
319+
unused = 0
320+
0098 0b804388 JUMPS 16, 11, GE
321+
cmp = 7 (GE)
322+
imm = 11 (0x0b)
323+
offset = 16 (0x10)
308324
opcode = 8
309325
sign = 0
310326
sub_opcode = 2
311327
unused = 0
312-
0094 01000090 WAKE
328+
009c 01000090 WAKE
313329
opcode = 9
314330
sub_opcode = 0
315331
unused = 0
316332
wakeup = 1
317-
0098 07000040 WAIT 7
333+
00a0 07000040 WAIT 7
318334
cycles = 7
319335
opcode = 4
320336
unused = 0
321-
009c 090000a0 TSENS r1, 2
337+
00a4 090000a0 TSENS r1, 2
322338
delay = 2
323339
dreg = 1
324340
opcode = 10 (0x0a)
325341
unused = 0
326-
00a0 000000b0 HALT
342+
00a8 000000b0 HALT
327343
opcode = 11 (0x0b)
328344
unused = 0
329-
00a4 060000d0 LD r2, r1, 0
345+
00ac 060000d0 LD r2, r1, 0
330346
dreg = 2
331347
offset = 0
332348
opcode = 13 (0x0d)
@@ -335,5 +351,5 @@ ULP magic : b'ulp\x00' (0x00706c75)
335351
unused2 = 0
336352
----------------------------------------
337353
.data
338-
00a8 00000000 <empty>
339-
00ac fecadec0 <non-empty>
354+
00b0 00000000 <empty>
355+
00b4 fecadec0 <non-empty>

‎tests/fixtures/all_opcodes.S‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,11 +46,14 @@ JUMP 0, EQ
4646
JUMP 0, OV
4747

4848
JUMPR 0, 1, LT
49-
JUMPR 4, 5, GE
49+
JUMPR 4, 5, GT
50+
JUMPR 8, 7, EQ
5051

5152
JUMPS 0, 1, LT
52-
JUMPS 4, 5, GE
53-
JUMPS 8, 9, LE
53+
JUMPS 4, 5, GT
54+
JUMPS 8, 7, EQ
55+
JUMPS 12, 9, LE
56+
JUMPS 16, 11, GE
5457

5558
WAKE
5659
SLEEP 7

‎tests/fixtures/all_opcodes.esp32.lst‎

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -31,15 +31,21 @@
3131
0074 00004080 JUMP 0, EQ
3232
0078 00008080 JUMP 0, OV
3333
007c 01000082 JUMPR 0, 1, LT
34-
0080 05000382 JUMPR 1, 5, GE
35-
0084 01000084 JUMPS 0, 1, LT
36-
0088 05800284 JUMPS 1, 5, GE
37-
008c 09000584 JUMPS 2, 9, LE
38-
0090 01000090 WAKE
39-
0094 07000092 SLEEP 7
40-
0098 090000a0 TSENS r1, 2
41-
009c 000000b0 HALT
42-
00a0 060000d0 LD r2, r1, 0
34+
0080 06000382 JUMPR 1, 6, GE
35+
0084 08000582 JUMPR 2, 8, GE
36+
0088 07000582 JUMPR 2, 7, GE
37+
008c 01000084 JUMPS 0, 1, LT
38+
0090 05000584 JUMPS 2, 5, LE
39+
0094 05800284 JUMPS 1, 5, GE
40+
0098 07000484 JUMPS 2, 7, LT
41+
009c 07000584 JUMPS 2, 7, LE
42+
00a0 09000784 JUMPS 3, 9, LE
43+
00a4 0b800884 JUMPS 4, 11, GE
44+
00a8 01000090 WAKE
45+
00ac 07000092 SLEEP 7
46+
00b0 090000a0 TSENS r1, 2
47+
00b4 000000b0 HALT
48+
00b8 060000d0 LD r2, r1, 0
4349
.data
44-
00a4 00000000 <empty>
45-
00a8 fecadec0 <non-empty>
50+
00bc 00000000 <empty>
51+
00c0 fecadec0 <non-empty>

‎tests/fixtures/all_opcodes.esp32s2.lst‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,17 @@
3232
0078 00008084 JUMP 0, OV
3333
007c 01000080 JUMPR 0, 1, LT
3434
0080 05000580 JUMPR 1, 5, GT
35-
0084 05000680 JUMPR 1, 5, EQ
35+
0084 07000a80 JUMPR 2, 7, EQ
3636
0088 01800088 JUMPS 0, 1, LT
37-
008c 05801388 JUMPS 4, 5, GE
38-
0090 09802288 JUMPS 8, 9, LE
39-
0094 01000090 WAKE
40-
0098 07000040 WAIT 7
41-
009c 090000a0 TSENS r1, 2
42-
00a0 000000b0 HALT
43-
00a4 060000d0 LD r2, r1, 0
37+
008c 05801188 JUMPS 4, 5, GT
38+
0090 07002288 JUMPS 8, 7, EQ
39+
0094 09803288 JUMPS 12, 9, LE
40+
0098 0b804388 JUMPS 16, 11, GE
41+
009c 01000090 WAKE
42+
00a0 07000040 WAIT 7
43+
00a4 090000a0 TSENS r1, 2
44+
00a8 000000b0 HALT
45+
00ac 060000d0 LD r2, r1, 0
4446
.data
45-
00a8 00000000 <empty>
46-
00ac fecadec0 <non-empty>
47+
00b0 00000000 <empty>
48+
00b4 fecadec0 <non-empty>

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