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style: modifymodule's name
1 parent d744531 commit 8ca00b1

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3 files changed

+4
-4
lines changed

3 files changed

+4
-4
lines changed

rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ class TreeCoreL2 extends Module {
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protected val ifu = Module(new IFU)
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protected val idu = Module(new IDU)
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protected val exu = Module(new EXU)
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protected val mau = Module(new Memory)
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protected val wbu = Module(new WriteBack)
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protected val mau = Module(new MAU)
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protected val wbu = Module(new WBU)
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ifu.io.socEn := io.socEn
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wbu.io.socEn := io.socEn

rtl/tc_l2/src/main/scala/core/ma/Memory.scala renamed to rtl/tc_l2/src/main/scala/core/ma/MAU.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ package treecorel2
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import chisel3._
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import chisel3.util._
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6-
class Memory extends Module {
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class MAU extends Module {
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val io = IO(new Bundle {
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val globalEn = Input(Bool())
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val ex2mem = Flipped(new EX2MEMIO)

rtl/tc_l2/src/main/scala/core/wb/WriteBack.scala renamed to rtl/tc_l2/src/main/scala/core/wb/WBU.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ import difftest._
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import treecorel2.common.ConstVal
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10-
class WriteBack extends Module {
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class WBU extends Module {
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val io = IO(new Bundle {
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val globalEn = Input(Bool())
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val socEn = Input(Bool())

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