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fix: modify id field value of cache io
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+10
-13
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+10
-13
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rtl/tc_l2/src/main/scala/core/if/Cache.scala

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3,36 +3,33 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
76
class CacheReqIO extends Bundle {
87
//
98
// |--------- tag ---------|---index---|--offset--|
109
//
1110
val addr = UInt(64.W)
1211
val data = UInt(64.W)
13-
val mask = UInt((64/8).W)
14-
val op = UInt(1.W) // 0: rd 1: wr
12+
val mask = UInt((64 / 8).W)
13+
val op = UInt(1.W) // 0: rd 1: wr
1514
}
1615

17-
class CacheRespIO extends Bundle{
16+
class CacheRespIO extends Bundle {
1817
val data = UInt(64.W)
19-
val cmd = UInt(4.W)
18+
val cmd = UInt(4.W)
2019
}
2120

2221
class MemReq extends Bundle {
2322
val addr = UInt(64.W)
2423
val data = UInt(64.W)
25-
val cmd = UInt(4.W)
26-
val len = UInt(2.W) // 0: 1(64bits) 1: 2 2: 4 3: 8
27-
val id = UInt(p(IDBits).W)
24+
val cmd = UInt(4.W)
25+
val len = UInt(2.W) // 0: 1(64bits) 1: 2 2: 4 3: 8
26+
val id = UInt(4.W)
2827
}
2928

3029
class MemResp extends Bundle {
3130
val data = UInt(64.W)
32-
val cmd = UInt(4.W)
33-
val id = UInt(p(IDBits).W)
31+
val cmd = UInt(4.W)
32+
val id = UInt(4.W)
3433
}
3534

36-
class Cache extends Module {
37-
38-
}
35+
class Cache extends Module {}

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