Is it possible to add support for an "invisible" metadata channel using inter-packet timing? By modulating the delay between sequential packets (e.g., in 50ms or 100ms buckets), we can transmit node health, priority flags, or packet-parity checksums without adding a single byte to the LoRa payload.
Technical Benefits for MeshCore:
Zero-Payload Overhead: Send critical diagnostic data (like battery level or hop-count validation) without increasing Time-on-Air (ToA) or collision probability.
Range-Edge Validation: Use timing as a "Secondary Checksum." If a packet has a CRC error at extreme range, the timing key can serve as a second-tier verification to salvage the data.
Implicit Priority: Allow repeaters to identify high-priority traffic signatures based on their timing interval before they even decrypt the payload.
Implementation Note:
This would be implemented at the hardware abstraction layer (HAL) using microsecond timers on supported LoRa chips (SX1262/SX1276). It maintains full backward compatibility; legacy nodes simply ignore the specific timing gaps
Just asking
Thanks
Is it possible to add support for an "invisible" metadata channel using inter-packet timing? By modulating the delay between sequential packets (e.g., in 50ms or 100ms buckets), we can transmit node health, priority flags, or packet-parity checksums without adding a single byte to the LoRa payload.
Technical Benefits for MeshCore:
Zero-Payload Overhead: Send critical diagnostic data (like battery level or hop-count validation) without increasing Time-on-Air (ToA) or collision probability.
Range-Edge Validation: Use timing as a "Secondary Checksum." If a packet has a CRC error at extreme range, the timing key can serve as a second-tier verification to salvage the data.
Implicit Priority: Allow repeaters to identify high-priority traffic signatures based on their timing interval before they even decrypt the payload.
Implementation Note:
This would be implemented at the hardware abstraction layer (HAL) using microsecond timers on supported LoRa chips (SX1262/SX1276). It maintains full backward compatibility; legacy nodes simply ignore the specific timing gaps
Just asking
Thanks