[Intel] Load's status and CheckAccessFullyMapped result value are 1 when 0 is expected for reserved unmapped tiles.

[bob80905]

In OffloadTest\test\Feature\HLSLLib\PartiallyMappedResources.test, the intel machine consistently reads 1's for the result of status and CheckAccessFullyMapped, when reading from resources that are partially or fully unmapped.
We expect 0's from CheckAccessFullyMapped, since that tile should be unmapped, but the Intel machine reports that it is mapped.

Here's the full test as it is now:

#--- source.hlsl

struct S{
  int data[512];
};

StructuredBuffer<S> X : register(t0);
StructuredBuffer<S> Y : register(t1);

RWStructuredBuffer<int> Out : register(u2);
RWStructuredBuffer<int> CAFM : register(u3);

[numthreads(1,1,1)]
void main() {
  // 32 S structs inside X or Y occupy 64KB of data. 
  // (32 * 512 ints * 4 bytes per int)
  // So, any index into the buffer >= [32] will access a new "tile"

  int idx = 0;

  uint status;
  S Out0 = X.Load(0, status);
  Out[idx] = Out0.data[0];
  Out[idx + 4] = status;
  CAFM[idx] = CheckAccessFullyMapped(status) ? 1 : 0;
  idx += 1;

  S Out1 = X.Load(50, status);
  Out[idx] = Out1.data[0];
  Out[idx + 4] = status;
  CAFM[idx] = CheckAccessFullyMapped(status) ? 1 : 0;
  idx += 1;

  S Out2 = Y.Load(0, status);
  Out[idx] = Out2.data[0];
  Out[idx + 4] = status;
  CAFM[idx] = CheckAccessFullyMapped(status) ? 1 : 0;
  idx += 1;

  S Out3 = Y.Load(50, status);
  Out[idx] = Out3.data[0];
  Out[idx + 4] = status;
  CAFM[idx] = CheckAccessFullyMapped(status) ? 1 : 0;
}
//--- pipeline.yaml

---
Shaders:
  - Stage: Compute
    Entry: main
    DispatchSize: [1, 1, 1]
Buffers:
  - Name: X
    Format: Int32
    Stride: 2048 # S is 512 ints, 512*4 = 2048.
    FillSize: 131072
    FillValue: 9001
  - Name: Y
    Format: Int32
    Stride: 2048
    FillSize: 131072
    FillValue: 9002
  - Name: Out
    Format: Int32
    Stride: 4
    FillSize: 32
  - Name: ExpectedOut
    Format: Int32
    Stride: 4
    # first 4 values are the actual data retrieved. For non-resident loads, 0 is expected.
    # last 4 values are the status. 1 is expected for resident memory, 0 for non-resident
    Data: [9001, 0, 0, 0, 1, 0, 0, 0]
  - Name: CAFM
    Format: Int32
    Stride: 4
    FillSize: 16
    FillValue: 0
  - Name: ExpectedCAFM
    Format: Int32
    Stride: 4
    # Only the first data access should be accessing fully mapped memory
    Data: [1, 0, 0, 0]

Results:
  - Result: Test
    Rule: BufferExact
    Actual: Out
    Expected: ExpectedOut
  - Result: TestCAFM
    Rule: BufferExact
    Actual: CAFM
    Expected: ExpectedCAFM
DescriptorSets:
  - Resources:
    - Name: X
      Kind: StructuredBuffer
      DirectXBinding:
        Register: 0
        Space: 0
      VulkanBinding:
        Binding: 0
      TilesMapped: 1
    - Name: Y
      Kind: StructuredBuffer
      DirectXBinding:
        Register: 1
        Space: 0
      VulkanBinding:
        Binding: 1
      TilesMapped: 0
    - Name: Out
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 2
        Space: 0
      VulkanBinding:
        Binding: 2
    - Name: CAFM
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 3
        Space: 0
      VulkanBinding:
        Binding: 3
#--- end

# XFAIL: Intel

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o