@@ -287,7 +287,7 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
287287define i32 @pr91691 (i32 %0 ) {
288288; CHECK-LABEL: @pr91691(
289289; CHECK-NEXT: [[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
290- ; CHECK-NEXT: [[TMP3:%.*]] = tail call range( i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false)
290+ ; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false), !range [[RNG0]]
291291; CHECK-NEXT: [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
292292; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 31
293293; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
@@ -305,7 +305,7 @@ define i32 @pr91691(i32 %0) {
305305define i32 @pr91691_keep_nsw (i32 %0 ) {
306306; CHECK-LABEL: @pr91691_keep_nsw(
307307; CHECK-NEXT: [[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
308- ; CHECK-NEXT: [[TMP3:%.*]] = tail call range( i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false)
308+ ; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false), !range [[RNG0]]
309309; CHECK-NEXT: [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
310310; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 31
311311; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
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