diff --git a/.circleci/config.yml b/.circleci/config.yml index ec4607f41..0a562a18d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -196,6 +196,7 @@ jobs: - build/x86/coreboot-4.11 - build/x86/coreboot-24.02.01 - build/x86/coreboot-24.12 + - build/x86/coreboot-25.03 - build/x86/coreboot-dasharo - build/x86/coreboot-purism - build/x86/musl-cross-make-fd6be58297ee21fcba89216ccd0d4aca1e3f1c5c @@ -260,6 +261,14 @@ workflows: requires: - x86-musl-cross-make + # coreboot 25.03 + - build_and_persist: + name: msi_z790p_ddr5 + target: msi_z790p_ddr5 + subcommand: "" + requires: + - x86-musl-cross-make + # coreboot talos_2 - build_and_persist: name: UNTESTED_talos-2 diff --git a/blobs/msi_z790p_ddr5/.gitignore b/blobs/msi_z790p_ddr5/.gitignore new file mode 100644 index 000000000..07ee878b8 --- /dev/null +++ b/blobs/msi_z790p_ddr5/.gitignore @@ -0,0 +1,4 @@ +ami_bios.bin +ami_bios.zip +ifd.bin +me.bin diff --git a/blobs/msi_z790p_ddr5/download_extract.sh b/blobs/msi_z790p_ddr5/download_extract.sh new file mode 100755 index 000000000..4c9c50102 --- /dev/null +++ b/blobs/msi_z790p_ddr5/download_extract.sh @@ -0,0 +1,49 @@ +#!/usr/bin/env bash + +# +# These will change over time. +# +ami_bios_url="https://download.msi.com/bos_exe/mb/7E06vAG.zip" +ami_bios_file="E7E06IMS.AG0" +me_hash="7a33a31cf22ae7e70adcd6f46b848a1e35e030b87fec2e671daf8fb416406396" +ifd_hash="72ddb02b42d2dbb1e3ae745118905941bb4dcd4e68fa082e93598278e7b38259" +# +# + +BLOBDIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" + +if [[ -z "${COREBOOT_DIR}" ]]; then + echo "ERROR: No COREBOOT_DIR variable defined." + exit 1 +fi + +pushd "${COREBOOT_DIR}/util/ifdtool" +make +popd + +IFDTOOL="${COREBOOT_DIR}/util/ifdtool/ifdtool" + +pushd $BLOBDIR + +curl -L --output ami_bios.zip "$ami_bios_url" || { echo "Downloading MSI BIOS failed." && exit 1; } + +unzip -o -j ami_bios.zip "*/$ami_bios_file" + +mv "$ami_bios_file" ./ami_bios.bin + +$IFDTOOL -p adl ./ami_bios.bin --extract + +rm ./flashregion_1_bios.bin ./flashregion_9_device_exp.bin + +mv ./flashregion_0_flashdescriptor.bin ./ifd.bin +mv ./flashregion_2_intel_me.bin ./me.bin + +$IFDTOOL -p adl ./ifd.bin --unlock --output ./ifd.bin +$IFDTOOL -p adl ./ifd.bin --altmedisable 1 --output ./ifd.bin + +echo "$ifd_hash ifd.bin" | sha256sum --check || { echo "ifd.bin verification failed." && exit 1; } +echo "$me_hash me.bin" | sha256sum --check || { echo "me.bin verification failed." && exit 1; } + +popd + +echo "DONE!" diff --git a/boards/msi_z790p_ddr5/msi_z790p_ddr5.config b/boards/msi_z790p_ddr5/msi_z790p_ddr5.config new file mode 100644 index 000000000..752d6586b --- /dev/null +++ b/boards/msi_z790p_ddr5/msi_z790p_ddr5.config @@ -0,0 +1,50 @@ +# MSI PRO Z790-P (DDR5) board configuration + +export CONFIG_COREBOOT=y +export CONFIG_COREBOOT_VERSION=25.03 +export CONFIG_LINUX_VERSION=6.1.8 + +CONFIG_COREBOOT_CONFIG=config/coreboot-msi_z790p_ddr5.config +CONFIG_LINUX_CONFIG=config/linux-msi-z690-z790.config + +CONFIG_KEXEC=y +CONFIG_QRENCODE=y +CONFIG_TPMTOTP=y +CONFIG_POPT=y +CONFIG_FLASHTOOLS=y +CONFIG_FLASHPROG=y +CONFIG_PCIUTILS=y +CONFIG_UTIL_LINUX=y +CONFIG_CRYPTSETUP2=y +CONFIG_GPG2=y +CONFIG_LVM2=y +CONFIG_MBEDTLS=y + +CONFIG_DROPBEAR=n + +CONFIG_HOTPKEY=n + +CONFIG_CAIRO=y +CONFIG_FBWHIPTAIL=y + +CONFIG_LINUX_USB=y +CONFIG_LINUX_IGC=y + +export CONFIG_USB_KEYBOARD=n + +export CONFIG_BOOTSCRIPT=/bin/gui-init + +export CONFIG_BOOT_KERNEL_ADD="" +export CONFIG_BOOT_KERNEL_REMOVE="" + +# TPM2 requirements +export CONFIG_TPM2_TOOLS=y +export CONFIG_PRIMARY_KEY_TYPE=ecc +CONFIG_TPM2_TSS=y +CONFIG_OPENSSL=y + +export CONFIG_BOOT_DEV="/dev/nvme0n1" +export CONFIG_BOARD_NAME="MSI PRO Z790-P" +export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal" + +BOARD_TARGETS := msi_z790p_ddr5_blobs diff --git a/config/coreboot-msi_z790p_ddr5.config b/config/coreboot-msi_z790p_ddr5.config new file mode 100644 index 000000000..c79c1152e --- /dev/null +++ b/config/coreboot-msi_z790p_ddr5.config @@ -0,0 +1,879 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_LTO is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOOSTAR is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARM is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CWWK is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ERYING is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_FRAMEWORK is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HARDKERNEL is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LATTEPANDA is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MITAC_COMPUTING is not set +CONFIG_VENDOR_MSI=y +# CONFIG_VENDOR_NOVACUSTOM is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAPTOR_CS is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TOPTON is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_MAINBOARD_FAMILY="Default string" +CONFIG_MAINBOARD_PART_NUMBER="PRO Z790-P WIFI (MS-7E06)" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="msi/ms7e06" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Micro-Star International Co., Ltd." +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=32 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +# CONFIG_VGA_BIOS is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Micro-Star International Co., Ltd." +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=256 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +# CONFIG_FATAL_ASSERTS is not set +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0x4000 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="PRO Z790-P WIFI (MS-7E06)" +# CONFIG_CONSOLE_POST is not set +CONFIG_MAX_SOCKET=1 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x3f +# CONFIG_USE_PM_ACPI_TIMER is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0xc0000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x88000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="@BLOB_DIR@/msi_z790p_ddr5/ifd.bin" +CONFIG_ME_BIN_PATH="@BLOB_DIR@/msi_z790p_ddr5/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x40000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_GBB_HWID="MSI_MS7E06" +# CONFIG_DEBUG_SMI is not set +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_TTYS0_BAUD=115200 +# CONFIG_BOARD_MSI_H81M_P33 is not set +# CONFIG_BOARD_MSI_MS7707 is not set +# CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4 is not set +# CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5 is not set +# CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4 is not set +CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y +CONFIG_BOARD_MSI_MS7E06=y +# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +CONFIG_D3COLD_SUPPORT=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_FSP_TEMP_RAM_SIZE=0x20000 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" +CONFIG_EC_STARLABS_BATTERY_TYPE="LION" +CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_LINUX_COMMAND_LINE="vm.panic_on_oom=1" +CONFIG_BOARD_ROMSIZE_KB_32768=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +CONFIG_COREBOOT_ROMSIZE_KB_32768=y +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=32768 +CONFIG_ROM_SIZE=0x02000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="soc/intel/alderlake/chipset_pch_s.cb" +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_BERT_SIZE=0x0 +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=133 +CONFIG_VBOOT_HASH_BLOCK_SIZE=0x1000 +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_SOC_INTEL_ALDERLAKE=y +CONFIG_SOC_INTEL_RAPTORLAKE=y +CONFIG_SOC_INTEL_ALDERLAKE_PCH_S=y +CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S=y +CONFIG_ALDERLAKE_CAR_ENHANCED_NEM=y +CONFIG_EXT_BIOS_WIN_BASE=0xf8000000 +CONFIG_EXT_BIOS_WIN_SIZE=0x2000000 +CONFIG_IFD_CHIPSET="adl" +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_MAX_PCH_ROOT_PORTS=28 +CONFIG_MAX_CPU_ROOT_PORTS=3 +CONFIG_MAX_TBT_ROOT_PORTS=0 +CONFIG_MAX_ROOT_PORTS=28 +CONFIG_MAX_PCIE_CLOCK_SRC=18 +CONFIG_MAX_PCIE_CLOCK_REQ=18 +CONFIG_PCR_BASE_ADDRESS=0xe0000000 +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR=127 +CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR=100 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_CPU_XTAL_HZ=38400000 +CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ=19200000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=7 +CONFIG_SOC_INTEL_I2C_DEV_MAX=8 +# CONFIG_ENABLE_SATA_TEST_MODE is not set +CONFIG_SOC_INTEL_UART_DEV_MAX=7 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x25a +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0x7fff +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" +CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0 +CONFIG_DATA_BUS_WIDTH=128 +CONFIG_DIMMS_PER_CHANNEL=2 +CONFIG_MRC_CHANNEL_WIDTH=16 +CONFIG_ALDERLAKE_ENABLE_SOC_WORKAROUND=y +CONFIG_SI_DESC_REGION="SI_DESC" +CONFIG_SI_DESC_REGION_SZ=4096 +CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8258 +CONFIG_INTEL_GMA_BCLV_WIDTH=32 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8254 +CONFIG_INTEL_GMA_BCLM_WIDTH=32 +CONFIG_FSP_PUBLISH_MBP_HOB=y +# CONFIG_INCLUDE_HSPHY_IN_FMAP is not set +CONFIG_HSPHY_FW_MAX_SIZE=0x8000 +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ=0x2005 +CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003 +CONFIG_MAX_HECI_DEVICES=6 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_HAVE_PAM0_REGISTER=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 +CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0 +CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003 +CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y +CONFIG_FSP_T_LOCATION=0xfffe0000 +CONFIG_INTEL_TME=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_FIXED_SMBUS_IO_BASE=0xefa0 +CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code for IP blocks +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID=y +CONFIG_SOC_INTEL_UFS_OCP_TIMER_DISABLE=y +CONFIG_SOC_INTEL_UFS_LTR_DISQUALIFY=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ASPM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CNVI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y +# CONFIG_USE_COREBOOT_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +CONFIG_INTEL_CAR_NEM_ENHANCED=y +CONFIG_INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE=y +CONFIG_CAR_HAS_SF_MASKS=y +CONFIG_COS_MAPPED_TO_MSB=y +CONFIG_CAR_HAS_L3_PROTECTED_WAYS=y +CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI=y +CONFIG_CPU_SUPPORTS_INTEL_TME=y +# CONFIG_TME_KEY_REGENERATION_ON_WARM_BOOT is not set +CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y +CONFIG_HAVE_HYPERTHREADING=y +CONFIG_FSP_HYPERTHREADING=y +# CONFIG_INTEL_KEYLOCKER is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC=y +CONFIG_SOC_INTEL_CSE_SEND_EOP_LATE=y +CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME" +CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw" +CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version" +CONFIG_SOC_INTEL_CSE_RW_FILE="" +CONFIG_SOC_INTEL_CSE_RW_VERSION="" +CONFIG_SOC_INTEL_CSE_SET_EOP=y +CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom" +CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy" +CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE="" +CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ME_SPEC_16=y +CONFIG_ME_SPEC=16 +CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DTT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +# CONFIG_SOC_INTEL_DISABLE_IGD is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_IRQ=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_MEMINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_OC_WDT=y +# CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE_RTD3=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +CONFIG_SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_EPOC=y +CONFIG_PMC_IPC_ACPI_INTERFACE=y +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_HAVE_CAPID_A_REGISTER=y +CONFIG_HAVE_BDSM_BGSM_REGISTER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_VTD=y +# CONFIG_ENABLE_EARLY_DMA_PROTECTION is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y +CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y +CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y + +# +# Intel SoC Common coreboot stages and non-IP blocks +# +CONFIG_SOC_INTEL_COMMON_BASECODE=y +CONFIG_SOC_INTEL_COMMON_BASECODE_RAMTOP=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +CONFIG_PAVP=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set +CONFIG_HAVE_INTEL_COMPLIANCE_TEST_MODE=y +# CONFIG_SOC_INTEL_COMPLIANCE_TEST_MODE is not set +CONFIG_HAS_INTEL_CPU_ROOT_PORTS=y + +# +# CPU +# +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_CPU_PT_ROM_MAP_GB=512 +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_X86_INIT_NEED_1_SIPI=y +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM=y +CONFIG_SUPERIO_NUVOTON_NCT6687D=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ACPI_FNKEY_GEN_SCANCODE=0 +CONFIG_UDK_BASE=y +CONFIG_UDK_202305_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_202005_VERSION=202005 +CONFIG_UDK_202111_VERSION=202111 +CONFIG_UDK_202302_VERSION=202302 +CONFIG_UDK_202305_VERSION=202305 +CONFIG_UDK_VERSION=202305 +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_CUSTOM_BOOTMEDIA=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_IDT_IN_EVERY_STAGE=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0 +CONFIG_DEFAULT_EBDA_LOWMEM=0x100000 +CONFIG_DEFAULT_EBDA_SEGMENT=0xF600 +CONFIG_DEFAULT_EBDA_SIZE=0x400 +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x10000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM=y +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set +# CONFIG_DRIVERS_EFI_FW_INFO is not set +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_DRIVERS_OPTION_CFR is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +CONFIG_PLATFORM_USES_FSP2_1=y +CONFIG_PLATFORM_USES_FSP2_2=y +CONFIG_PLATFORM_USES_FSP2_3=y +CONFIG_PLATFORM_USES_FSP2_X86_32=y +CONFIG_HAVE_INTEL_FSP_REPO=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_FSP_FULL_FD=y +CONFIG_FSP_T_RESERVED_SIZE=0x0 +CONFIG_FSP_M_XIP=y +CONFIG_FSP_USES_CB_STACK=y +CONFIG_FSP_COMPRESS_FSP_S_LZ4=y +CONFIG_SOC_INTEL_COMMON_FSP_RESET=y +CONFIG_FSPS_HAS_ARCH_UPD=y +CONFIG_FSP_USES_CB_DEBUG_EVENT_HANDLER=y +# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set +CONFIG_FSP_ENABLE_SERIAL_DEBUG=y +CONFIG_FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN=y +# CONFIG_BUILDING_WITH_DEBUG_FSP is not set +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_1=y +CONFIG_INTEL_GMA_VERSION_2=y +CONFIG_HAVE_INTEL_PTT=y +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_USB_ACPI=y +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +CONFIG_MP_SERVICES_PPI=y +CONFIG_MP_SERVICES_PPI_V2=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +CONFIG_VBOOT_LIB=y +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_TPM1 is not set +CONFIG_TPM2=y +CONFIG_TPM=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_LOG_CB is not set +CONFIG_TPM_LOG_TPM2=y +# CONFIG_TPM_HASH_SHA1 is not set +CONFIG_TPM_HASH_SHA256=y +# CONFIG_TPM_HASH_SHA384 is not set +# CONFIG_TPM_HASH_SHA512 is not set +CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA="" +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# end of Memory initialization + +CONFIG_INTEL_TXT_LIB=y +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_ACPI_LPIT=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_ACPI_S1_NOT_SUPPORTED=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_IOAPIC=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_FLAT_BINARY is not set +# CONFIG_PAYLOAD_BOOTBOOT is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEAGRUB is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_EDK2 is not set +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="@BOARD_BUILD_DIR@/bzImage" +# CONFIG_PXE is not set +CONFIG_LINUX_INITRD="@BOARD_BUILD_DIR@/initrd.cpio.xz" +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set +# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set +# end of Secondary Payloads +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_VERIFY_HOBS is not set +CONFIG_DISPLAY_FSP_VERSION_INFO=y +# CONFIG_ENABLE_FSP_ERROR_INFO is not set +CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y +# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_DECOMPRESS_OFAST=y + +# +# Boot Logo Configuration +# +# CONFIG_BMP_LOGO is not set +# end of Boot Logo Configuration + +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/linux-msi-z690-z790.config b/config/linux-msi-z690-z790.config new file mode 100644 index 000000000..a4f99f503 --- /dev/null +++ b/config/linux-msi-z690-z790.config @@ -0,0 +1,3397 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86 6.1.8 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="x86_64-linux-musl-gcc (GCC) 8.3.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=80300 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23200 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23200 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=0 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="-@BRAND_NAME@" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_WATCH_QUEUE is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +# CONFIG_BPF_SYSCALL is not set +# CONFIG_BPF_JIT is not set +# end of BPF subsystem + +CONFIG_PREEMPT_BUILD=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_SCHED_CORE is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +# CONFIG_IKCONFIG is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC12_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="@BLOB_DIR@/dev.cpio" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_INITRAMFS_COMPRESSION_XZ=y +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_BOOT_CONFIG is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_EXPERT=y +# CONFIG_MULTIUSER is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_PCSPKR_PLATFORM=y +# CONFIG_BASE_FULL is not set +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +# CONFIG_AIO is not set +CONFIG_IO_URING=y +# CONFIG_ADVISE_SYSCALLS is not set +CONFIG_MEMBARRIER=y +# CONFIG_KALLSYMS is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +# CONFIG_PROFILING is not set +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_NR_GPIO=1024 +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_AUDIT_ARCH=y +CONFIG_HAVE_INTEL_TXT=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +CONFIG_X86_MPPARSE=y +# CONFIG_GOLDFISH is not set +# CONFIG_X86_CPU_RESCTRL is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_X86_INTEL_LPSS is not set +# CONFIG_X86_AMD_PLATFORM_DEVICE is not set +CONFIG_IOSF_MBI=y +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_HYPERVISOR_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_CPU_SUP_INTEL=y +# CONFIG_CPU_SUP_AMD is not set +# CONFIG_CPU_SUP_HYGON is not set +# CONFIG_CPU_SUP_CENTAUR is not set +# CONFIG_CPU_SUP_ZHAOXIN is not set +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +CONFIG_BOOT_VESA_SUPPORT=y +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=64 +CONFIG_SCHED_CLUSTER=y +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_THRESHOLD=y + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +# CONFIG_PERF_EVENTS_INTEL_RAPL is not set +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +# end of Performance monitoring + +# CONFIG_X86_VSYSCALL_EMULATION is not set +CONFIG_X86_IOPL_IOPERM=y +# CONFIG_MICROCODE is not set +# CONFIG_X86_MSR is not set +# CONFIG_X86_CPUID is not set +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_NUMA is not set +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_X86_PMEM_LEGACY_DEVICE=y +CONFIG_X86_PMEM_LEGACY=y +# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set +# CONFIG_MTRR is not set +CONFIG_X86_UMIP=y +CONFIG_CC_HAS_IBT=y +# CONFIG_X86_KERNEL_IBT is not set +# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +CONFIG_EFI=y +# CONFIG_EFI_STUB is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_ARCH_HAS_KEXEC_PURGATORY=y +# CONFIG_KEXEC_SIG is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_PHYSICAL_START=0x1000000 +# CONFIG_RELOCATABLE is not set +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +CONFIG_LEGACY_VSYSCALL_NONE=y +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_STRICT_SIGALTSTACK_SIZE is not set +CONFIG_HAVE_LIVEPATCH=y +# end of Processor type and features + +CONFIG_CC_HAS_RETURN_THUNK=y +CONFIG_SPECULATION_MITIGATIONS=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_RETPOLINE is not set +CONFIG_CPU_IBRS_ENTRY=y +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y + +# +# Power management and ACPI options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +# CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_CUSTOM_DSDT_FILE="" +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_PCI_SLOT is not set +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +# CONFIG_ACPI_SBS is not set +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_BGRT is not set +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +# CONFIG_ACPI_APEI is not set +# CONFIG_ACPI_DPTF is not set +# CONFIG_ACPI_CONFIGFS is not set +# CONFIG_ACPI_PFRUT is not set +CONFIG_ACPI_PCC=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_ACPI_PRMT=y +CONFIG_X86_PM_TIMER=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_STAT is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_PCC_CPUFREQ is not set +# CONFIG_X86_AMD_PSTATE is not set +# CONFIG_X86_AMD_PSTATE_UT is not set +# CONFIG_X86_ACPI_CPUFREQ is not set +# CONFIG_X86_SPEEDSTEP_CENTRINO is not set +# CONFIG_X86_P4_CLOCKMOD is not set + +# +# shared options +# +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# end of CPU Idle + +# CONFIG_INTEL_IDLE is not set +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_MMCONF_FAM10H=y +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +# CONFIG_IA32_EMULATION is not set +# CONFIG_X86_X32_ABI is not set +# end of Binary Emulations + +CONFIG_HAVE_KVM=y +# CONFIG_VIRTUALIZATION is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y +CONFIG_AS_TPAUSE=y + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_MERGE_VMAS=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +# CONFIG_SECCOMP is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_HAVE_OBJTOOL=y +CONFIG_HAVE_JUMP_LABEL_HACK=y +CONFIG_HAVE_NOINSTR_HACK=y +CONFIG_HAVE_NOINSTR_VALIDATION=y +CONFIG_HAVE_UACCESS_VALIDATION=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y +CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y +CONFIG_DYNAMIC_SIGFRAME=y +CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y + +# +# GCOV-based kernel profiling +# +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=1 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=m +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_COREDUMP is not set +# end of Executable file formats + +# +# Memory Management options +# +# CONFIG_SWAP is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +# CONFIG_COMPACTION is not set +# CONFIG_PAGE_REPORTING is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANTS_THP_SWAP=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +# CONFIG_CMA is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +# CONFIG_ZONE_DMA is not set +CONFIG_ZONE_DMA32=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_PERCPU_STATS is not set + +# +# GUP_TEST needs to have DEBUG_FS enabled +# +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# CONFIG_USERFAULTFD is not set +# CONFIG_LRU_GEN is not set + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +# CONFIG_XFRM_USER is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TABLE_PERTURB_ORDER=16 +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_MPTCP is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +# CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_VMD is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_CXL_BUS is not set +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# CONFIG_FW_UPLOAD is not set +# end of Firmware loader + +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# end of Bus devices + +# CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +# CONFIG_EDD is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_DMIID is not set +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_ISCSI_IBFT is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_RUNTIME_MAP=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_FD is not set +CONFIG_CDROM=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_AUTH is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +CONFIG_INTEL_MEI=m +CONFIG_INTEL_MEI_ME=m +CONFIG_INTEL_MEI_TXE=m +# CONFIG_VMWARE_VMCI is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=y +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPI3MR is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +# CONFIG_VMWARE_PVSCSI is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_ACPI=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_AHCI_DWC is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +CONFIG_DM_VERITY=y +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +CONFIG_NET_VENDOR_ASIX=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_CX_ECAT is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_TSNEP is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +# CONFIG_FUN_ETH is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_E1000E_HWTS=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +CONFIG_IGC=m +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_NGBE is not set +# CONFIG_TXGBE is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_LITEX=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +CONFIG_NET_VENDOR_MICROSOFT=y +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +CONFIG_NET_VENDOR_VERTEXCOM=y +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +# CONFIG_PHYLIB is not set +# CONFIG_PSE_CONTROLLER is not set +# CONFIG_MDIO_DEVICE is not set + +# +# PCS device drivers +# +# end of PCS device drivers + +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set +# CONFIG_WAN is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_PNP is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_8250_LPSS is not set +# CONFIG_SERIAL_8250_MID is not set +CONFIG_SERIAL_8250_PERICOM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_LANTIQ is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# end of Serial drivers + +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_TTY_PRINTK=y +CONFIG_TTY_PRINTK_LEVEL=6 +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_INTEL=y +CONFIG_HW_RANDOM_AMD=m +# CONFIG_HW_RANDOM_BA431 is not set +CONFIG_HW_RANDOM_VIA=m +# CONFIG_HW_RANDOM_XIPHERA is not set +# CONFIG_APPLICOM is not set +# CONFIG_MWAVE is not set +CONFIG_DEVMEM=y +# CONFIG_NVRAM is not set +CONFIG_DEVPORT=y +# CONFIG_HPET is not set +# CONFIG_HANGCHECK_TIMER is not set +CONFIG_TCG_TPM=y +# CONFIG_HW_RANDOM_TPM is not set +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +# CONFIG_TCG_TIS_I2C is not set +# CONFIG_TCG_TIS_I2C_CR50 is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +# CONFIG_TCG_TIS_I2C_INFINEON is not set +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +# CONFIG_TCG_NSC is not set +# CONFIG_TCG_ATMEL is not set +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_CRB=y +# CONFIG_TCG_VTPM_PROXY is not set +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TELCLOCK is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_MUX_LTC4306 is not set +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_REG=m +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +# end of I2C Algorithms + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# CONFIG_I2C_VIRTIO is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +# CONFIG_PINCTRL is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_IP5XXX_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_BATTERY_UG3105 is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +# CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_THERMAL_VECTOR=y +# CONFIG_X86_PKG_TEMP_THERMAL is not set +# CONFIG_INTEL_SOC_DTS_THERMAL is not set + +# +# ACPI INT340X thermal drivers +# +# CONFIG_INT340X_THERMAL is not set +# end of ACPI INT340X thermal drivers + +# CONFIG_INTEL_PCH_THERMAL is not set +# CONFIG_INTEL_TCC_COOLING is not set +# CONFIG_INTEL_MENLOW is not set +# CONFIG_INTEL_HFI_THERMAL is not set +# end of Intel thermal drivers + +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_LPSS_ACPI is not set +# CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_INTEL_PMC_BXT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_SY7636A is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set + +# +# CEC support +# +# CONFIG_MEDIA_CEC_SUPPORT is not set +# end of CEC support + +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +# CONFIG_AGP is not set +# CONFIG_VGA_SWITCHEROO is not set +# CONFIG_DRM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set + +# +# ARM devices +# +# end of ARM devices + +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +CONFIG_FB_VESA=y +CONFIG_FB_EFI=y +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# end of Backlight & LCD device support + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_FT260 is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VRC2 is not set +# CONFIG_HID_XIAOMI is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MEGAWORLD_FF is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SIGMAMICRO is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TOPRE is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID_ACPI is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +# CONFIG_INTEL_ISH_HID is not set +# end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_ULPI_BUS is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=m +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_MMC is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_GOLDFISH is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +# CONFIG_VHOST_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set +# CONFIG_STAGING is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +CONFIG_X86_PLATFORM_DEVICES=y +# CONFIG_ACPI_WMI is not set +# CONFIG_ACERHDF is not set +# CONFIG_ACER_WIRELESS is not set +# CONFIG_AMD_PMF is not set +# CONFIG_AMD_PMC is not set +# CONFIG_ADV_SWBUTTON is not set +# CONFIG_ASUS_WIRELESS is not set +# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set +# CONFIG_FUJITSU_TABLET is not set +# CONFIG_GPD_POCKET_FAN is not set +# CONFIG_HP_ACCEL is not set +# CONFIG_WIRELESS_HOTKEY is not set +# CONFIG_IBM_RTL is not set +# CONFIG_SENSORS_HDAPS is not set +# CONFIG_INTEL_SAR_INT1092 is not set +# CONFIG_INTEL_PMC_CORE is not set + +# +# Intel Speed Select Technology interface support +# +# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set +# end of Intel Speed Select Technology interface support + +# +# Intel Uncore Frequency Control +# +# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set +# end of Intel Uncore Frequency Control + +# CONFIG_INTEL_HID_EVENT is not set +# CONFIG_INTEL_VBTN is not set +# CONFIG_INTEL_PUNIT_IPC is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_TURBO_MAX_3 is not set +# CONFIG_INTEL_VSEC is not set +# CONFIG_SAMSUNG_Q10 is not set +# CONFIG_TOSHIBA_BT_RFKILL is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_ACPI_CMPC is not set +# CONFIG_TOPSTAR_LAPTOP is not set +# CONFIG_MLX_PLATFORM is not set +# CONFIG_INTEL_IPS is not set +# CONFIG_INTEL_SCU_PCI is not set +# CONFIG_INTEL_SCU_PLATFORM is not set +# CONFIG_SIEMENS_SIMATIC_IPC is not set +# CONFIG_WINMATE_FM07_KEYS is not set +# CONFIG_P2SB is not set +# CONFIG_COMMON_CLK is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_SVA=y +# CONFIG_AMD_IOMMU is not set +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +CONFIG_INTEL_IOMMU_SVM=y +CONFIG_INTEL_IOMMU_DEFAULT_ON=y +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +# CONFIG_IRQ_REMAP is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# end of Enable LiteX SoC Builder specific drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_USB_LGM_PHY is not set +# CONFIG_PHY_CAN_TRANSCEIVER is not set + +# +# PHY drivers for Broadcom platforms +# +# CONFIG_BCM_KONA_USB2_PHY is not set +# end of PHY drivers for Broadcom platforms + +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +# CONFIG_RAS is not set +# CONFIG_USB4 is not set + +# +# Android +# +# CONFIG_ANDROID_BINDER_IPC is not set +# end of Android + +CONFIG_LIBNVDIMM=y +# CONFIG_BLK_DEV_PMEM is not set +# CONFIG_BTT is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_PECI is not set +# CONFIG_HTE is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS3_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set +# CONFIG_PROC_CHILDREN is not set +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_TMPFS_INODE64 is not set +# CONFIG_HUGETLBFS is not set +CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +# CONFIG_CONFIGFS_FS is not set +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITYFS=y +# CONFIG_INTEL_TXT is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_FULL is not set +# CONFIG_RANDSTRUCT_PERFORMANCE is not set +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=m +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_SIMD=y +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=m +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_ANUBIS=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +# CONFIG_CRYPTO_DES is not set +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +# CONFIG_CRYPTO_SM4_GENERIC is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_HCTR2 is not set +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_OFB is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_ESSIV=y +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +# CONFIG_CRYPTO_BLAKE2B is not set +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +# CONFIG_CRYPTO_XXHASH is not set +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +# CONFIG_CRYPTO_ZSTD is not set +# end of Compression + +# +# Random number generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y + +# +# Accelerated Cryptographic Algorithms for CPU (x86) +# +# CONFIG_CRYPTO_CURVE25519_X86 is not set +CONFIG_CRYPTO_AES_NI_INTEL=y +CONFIG_CRYPTO_BLOWFISH_X86_64=m +CONFIG_CRYPTO_CAMELLIA_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m +CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m +CONFIG_CRYPTO_CAST5_AVX_X86_64=m +CONFIG_CRYPTO_CAST6_AVX_X86_64=m +CONFIG_CRYPTO_DES3_EDE_X86_64=m +CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX_X86_64=m +CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m +# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set +CONFIG_CRYPTO_TWOFISH_X86_64=m +CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m +CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m +# CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 is not set +CONFIG_CRYPTO_CHACHA20_X86_64=m +# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set +# CONFIG_CRYPTO_BLAKE2S_X86 is not set +# CONFIG_CRYPTO_POLYVAL_CLMUL_NI is not set +CONFIG_CRYPTO_POLY1305_X86_64=m +CONFIG_CRYPTO_SHA1_SSSE3=y +CONFIG_CRYPTO_SHA256_SSSE3=y +CONFIG_CRYPTO_SHA512_SSSE3=y +# CONFIG_CRYPTO_SM3_AVX_X86_64 is not set +CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m +CONFIG_CRYPTO_CRC32C_INTEL=y +CONFIG_CRYPTO_CRC32_PCLMUL=m +CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m +# end of Accelerated Cryptographic Algorithms for CPU (x86) + +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# end of Certificates for signature checking + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +# CONFIG_CRC64_ROCKSOFT is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +CONFIG_CRC7=m +# CONFIG_LIBCRC32C is not set +CONFIG_CRC8=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=m +CONFIG_842_DECOMPRESS=m +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=m +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_TEST=m +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_INTERVAL_TREE=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=m +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_MEMREGION=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_COPY_MC=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_BOOT_PRINTK_DELAY=y +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Compile-time checks and compiler options +# +CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_OBJTOOL=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +# CONFIG_DEBUG_FS is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_DEBUG_OBJECTS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +CONFIG_HAVE_ARCH_KMSAN=y +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_WQ_WATCHDOG=y +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_DEBUG_PREEMPT=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y +CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set + +# +# x86 Debugging +# +# CONFIG_X86_VERBOSE_BOOTUP is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_DBGP is not set +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_TLBFLUSH is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +# CONFIG_X86_DECODER_SELFTEST is not set +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +# CONFIG_X86_DEBUG_FPU is not set +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_SIPHASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_TEST_FPU is not set +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +CONFIG_ARCH_USE_MEMTEST=y +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/modules/coreboot b/modules/coreboot index 84b9f5130..1d6cf81d9 100644 --- a/modules/coreboot +++ b/modules/coreboot @@ -77,6 +77,10 @@ coreboot-24.02.01_hash := e56f5c0c9008bfdec1c4be6409ac093680140f9441efd3d5e47bde coreboot-blobs-24.02.01_hash := 8d03b82cd2b2593473d4cd511c7bef7fdd43839237f6c37a8383161660c14427 $(eval $(call coreboot_module,24.02.01,)) +coreboot-25.03_hash := 9182f84c0bf869cb97601594edd50f5891e97b9dc34c0e158bce2cf9ed51175a +coreboot-blobs-25.03_hash := 03e8f565f73b932f942f08f0058d37080e1d2b0ce866596c25e607d14d1e95f0 +$(eval $(call coreboot_module,25.03,)) + # coreboot git forks # talos_2 could use the 4.20.1 toolchain, but it's the only ppc64 fork, so diff --git a/patches/coreboot-25.03/0001-src-superio-nuvoton-Add-HWM-initialization-code.patch b/patches/coreboot-25.03/0001-src-superio-nuvoton-Add-HWM-initialization-code.patch new file mode 100644 index 000000000..47bb0ce6e --- /dev/null +++ b/patches/coreboot-25.03/0001-src-superio-nuvoton-Add-HWM-initialization-code.patch @@ -0,0 +1,2453 @@ +From c5acebb3c692330d3b3bda252bb045086f371675 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Sun, 10 Sep 2023 14:26:59 +0200 +Subject: [PATCH 1/4] src/superio/nuvoton: Add HWM initialization code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Michał Żygowski +Change-Id: Ib78ad052204009dc1f9b90ad2272a83b304fd39d +--- + src/superio/nuvoton/nct6687d/Makefile.mk | 5 + + src/superio/nuvoton/nct6687d/chip.h | 361 ++++++++ + src/superio/nuvoton/nct6687d/nct6687d_ec.c | 77 ++ + src/superio/nuvoton/nct6687d/nct6687d_ec.h | 27 + + src/superio/nuvoton/nct6687d/nct6687d_hwm.c | 960 ++++++++++++++++++++ + src/superio/nuvoton/nct6687d/nct6687d_hwm.h | 922 +++++++++++++++++++ + src/superio/nuvoton/nct6687d/superio.c | 10 + + 7 files changed, 2362 insertions(+) + create mode 100644 src/superio/nuvoton/nct6687d/chip.h + create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_ec.c + create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_ec.h + create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_hwm.c + create mode 100644 src/superio/nuvoton/nct6687d/nct6687d_hwm.h + +diff --git a/src/superio/nuvoton/nct6687d/Makefile.mk b/src/superio/nuvoton/nct6687d/Makefile.mk +index d4785f726e..899cf5daec 100644 +--- a/src/superio/nuvoton/nct6687d/Makefile.mk ++++ b/src/superio/nuvoton/nct6687d/Makefile.mk +@@ -1,3 +1,8 @@ + # SPDX-License-Identifier: GPL-2.0-or-later + ++bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c ++romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c ++ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c ++ ++ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_hwm.c + ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c +diff --git a/src/superio/nuvoton/nct6687d/chip.h b/src/superio/nuvoton/nct6687d/chip.h +new file mode 100644 +index 0000000000..edd0deb23a +--- /dev/null ++++ b/src/superio/nuvoton/nct6687d/chip.h +@@ -0,0 +1,361 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#ifndef SUPERIO_NUVOTON_NCT6687D_CHIP_H ++#define SUPERIO_NUVOTON_NCT6687D_CHIP_H ++ ++#include ++ ++#define MAX_TEMP_SPEED_LEVELS 7 ++#define MAX_TEMP_SRC 4 ++#define MAX_NUM_FANS 10 ++#define MAX_NUM_SENSORS 32 ++#define MAX_WEIGHT_POINTS 8 ++#define MAX_DTS_CTL_POINTS 5 ++ ++enum nct6687d_sensor_src_select { ++ /* TIN sources */ ++ SENSOR_DISABLE = 0x00, ++ SENSOR_LOCAL = 0x01, ++ TD0P_CURRENT_MODE = 0x02, ++ TD1P_CURRENT_MODE = 0x03, ++ TD2P_CURRENT_MODE = 0x04, ++ TD0P_VOLTAGE_MODE = 0x05, ++ TD1P_VOLTAGE_MODE = 0x06, ++ TD2P_VOLTAGE_MODE = 0x07, ++ THERMISTOR14 = 0x08, ++ THERMISTOR15 = 0x09, ++ THERMISTOR16 = 0x0A, ++ THERMISTOR0 = 0x0B, ++ THERMISTOR1 = 0x0C, ++ THERMISTOR2 = 0x0D, ++ THERMISTOR3 = 0x0E, ++ THERMISTOR4 = 0x0F, ++ THERMISTOR5 = 0x10, ++ THERMISTOR6 = 0x11, ++ THERMISTOR7 = 0x12, ++ THERMISTOR8 = 0x13, ++ THERMISTOR9 = 0x14, ++ THERMISTOR10 = 0x15, ++ THERMISTOR11 = 0x16, ++ THERMISTOR12 = 0x17, ++ THERMISTOR13 = 0x18, ++ PECI_AGENT0_DOMAIN0 = 0x20, ++ PECI_AGENT1_DOMAIN0 = 0x21, ++ PECI_AGENT2_DOMAIN0 = 0x22, ++ PECI_AGENT3_DOMAIN0 = 0x23, ++ PECI_AGENT0_DOMAIN1 = 0x24, ++ PECI_AGENT1_DOMAIN1 = 0x25, ++ PECI_AGENT2_DOMAIN1 = 0x26, ++ PECI_AGENT3_DOMAIN1 = 0x27, ++ PECI_DIMM_TMP0 = 0x28, ++ PECI_DIMM_TMP1 = 0x29, ++ PECI_DIMM_TMP2 = 0x2A, ++ PECI_DIMM_TMP3 = 0x2B, ++ PCH_CPU = 0x30, ++ PCH_CHIP = 0x31, ++ PCH_CHIP_CPU_MAX = 0x32, ++ PCH_MCH = 0x33, ++ PCH_DIMM0 = 0x34, ++ PCH_DIMM1 = 0x35, ++ PCH_DIMM2 = 0x36, ++ PCH_DIMM3 = 0x37, ++ SMBUS_THERMAL_SENSOR0 = 0x38, ++ SMBUS_THERMAL_SENSOR1 = 0x39, ++ SMBUS_THERMAL_SENSOR2 = 0x3A, ++ SMBUS_THERMAL_SENSOR3 = 0x3B, ++ SMBUS_THERMAL_SENSOR4 = 0x3C, ++ SMBUS_THERMAL_SENSOR5 = 0x3D, ++ DIMM_THERMAL_SENSOR0 = 0x3E, ++ DIMM_THERMAL_SENSOR1 = 0x3F, ++ DIMM_THERMAL_SENSOR2 = 0x40, ++ DIMM_THERMAL_SENSOR3 = 0x41, ++ AMD_TSI_ADDRESS_0x90 = 0x42, ++ AMD_TSI_ADDRESS_0x92 = 0x43, ++ AMD_TSI_ADDRESS_0x94 = 0x44, ++ AMD_TSI_ADDRESS_0x96 = 0x45, ++ AMD_TSI_ADDRESS_0x98 = 0x46, ++ AMD_TSI_ADDRESS_0x9A = 0x47, ++ AMD_TSI_ADDRESS_0x9C = 0x48, ++ AMD_TSI_ADDRESS_0x9D = 0x49, ++ VIRTUAL_TEMPIN0 = 0x50, ++ VIRTUAL_TEMPIN1 = 0x51, ++ VIRTUAL_TEMPIN2 = 0x52, ++ VIRTUAL_TEMPIN3 = 0x53, ++ VIRTUAL_TEMPIN4 = 0x54, ++ VIRTUAL_TEMPIN5 = 0x55, ++ VIRTUAL_TEMPIN6 = 0x56, ++ VIRTUAL_TEMPIN7= 0x57, ++ /* VIN soruces */ ++ VCC= 0x60, ++ VSB= 0x61, ++ AVSB = 0x62, ++ VTT = 0x63, ++ VBAT = 0x64, ++ VREF = 0x65, ++ VIN0 = 0x66, ++ VIN1 = 0x67, ++ VIN2 = 0x68, ++ VIN3 = 0x69, ++ VIN4 = 0x6A, ++ VIN5 = 0x6B, ++ VIN6 = 0x6C, ++ VIN7 = 0x6D, ++ VIN8 = 0x6E, ++ VIN9 = 0x6F, ++ VIN10 = 0x70, ++ VIN11 = 0x71, ++ VIN12 = 0x72, ++ VIN13 = 0x73, ++ VIN14 = 0x74, ++ VIN15 = 0x75, ++ VIN16 = 0x76, ++}; ++ ++enum nct6687d_peci_speed { ++ PECI_2MHZ = 0, ++ PECI_1200KHZ, ++ PECI_800KHZ, ++ PECI_400KHZ, ++}; ++ ++enum nct6687d_baud_rate { ++ BAUD_12_5K = 0, ++ BAUD_25K, ++ BAUD_50K, ++ BAUD_100K, ++ BAUD_200K, ++ BAUD_400K, ++ BAUD_800K, ++ BAUD_1200K, ++}; ++ ++enum nct6687d_fan_mode { ++ FAN_IGNORE = 0, ++ FAN_THERMAL_CRUISE, ++ FAN_SPEED_CRUISE, ++ FAN_SMART_FAN_IV, ++ FAN_PID_CONTROL, ++ FAN_MODE_MANUAL, ++}; ++ ++enum nct6687d_tach_pwm_sel { ++ TACH_PWM0 = 0, ++ TACH_PWM1, ++ TACH_PWM2, ++ TACH_PWM3, ++ TACH_PWM4, ++ TACH_PWM5, ++ TACH_PWM6, ++ TACH_PWM7, ++ TACH_PWM8, ++ TACH_PWM9, ++ TACH_PWM10, ++ TACH_PWM11, ++ TACH_PWM12, ++ TACH_PWM13, ++ TACH_PWM14, ++ TACH_PWM15, ++ TACH_PWM16, ++ TACH_PWM17, ++ TACH_PWM18, ++ TACH_PWM19, ++ TACH_PWM20, ++ TACH_PWM21, ++ TACH_PWM22, ++ TACH_PWM23, ++}; ++ ++enum nct6687d_fan_unit_sel { ++ FAN_PWM = 0, ++ FAN_RPM, ++}; ++ ++enum nct6687d_fast_track_weight { ++ WEIGHT_DIV_1 = 0, ++ WEIGHT_DIV_2, ++ WEIGHT_DIV_4, ++ WEIGHT_DIV_8, ++ WEIGHT_DIV_16, ++ WEIGHT_DIV_32, ++ WEIGHT_DIV_64, ++}; ++ ++struct nct6687d_pch_smbus_sensor { ++ bool sensor_en; ++ uint8_t sensor_idx; ++ bool report_one_byte; ++ uint8_t port_sel; ++ enum nct6687d_baud_rate baud_rate; ++ uint8_t sensor_addr; ++ uint8_t sensor_cmd; ++}; ++ ++struct nct6687d_dts_sensor_config { ++ uint8_t ambient_temp[MAX_DTS_CTL_POINTS]; ++ uint16_t rpm_start_point[MAX_DTS_CTL_POINTS]; ++ uint16_t rpm_end_point[MAX_DTS_CTL_POINTS]; ++ uint8_t temp_start; ++ uint8_t temp_end; ++ uint16_t max_speed; ++ bool peci_adjust; ++ uint8_t peci_agent_idx; ++}; ++ ++struct nct6687d_dts2_sensor_config { ++ int8_t target_margin; ++ uint8_t target_margin_tolerance; ++ int8_t t_control; ++ int8_t t_control_offset; ++ uint16_t step_speed; ++ uint16_t min_speed; ++ /* Unit is 1s */ ++ uint8_t delay_time; ++ uint8_t divisor; ++}; ++ ++struct nct6687d_smart_fan_iv_config { ++ uint8_t temp_src[MAX_TEMP_SRC]; ++ uint8_t temp_levels[MAX_TEMP_SPEED_LEVELS]; ++ uint16_t speed_levels[MAX_TEMP_SPEED_LEVELS]; ++ uint8_t temp_hystheresis; ++ uint8_t temp_cut_off; ++ uint8_t cut_off_delay; ++ /* Time in 100ms units */ ++ uint8_t step_up_time; ++ uint8_t step_down_time; ++}; ++ ++struct nct6687d_manual_fan_config { ++ uint8_t manual_duty; ++}; ++ ++struct nct6687d_fan_thermal_cruise_config { ++ bool keep_min_fan_output; ++ uint8_t target_temp; ++ uint8_t temp_tolerance; ++ uint8_t initial_value; ++ uint8_t stop_value; ++ /* Time in 100ms units */ ++ uint8_t stop_time; ++ uint8_t step_up_time; ++ uint8_t step_down_time; ++}; ++ ++struct nct6687d_fan_speed_cruise_config { ++ uint16_t target_rpm; ++ uint16_t rpm_tolerance; ++ /* Time in 100ms units */ ++ uint8_t step_up_time; ++ uint8_t step_down_time; ++}; ++ ++struct nct6687d_ambient_floor_fan_config { ++ /* Units is RPM */ ++ uint16_t minout_start; ++ uint16_t minout_end; ++ uint16_t minout_max; ++}; ++ ++struct nct6687d_ambient_floor_config { ++ uint8_t temp_start; ++ uint8_t temp_end; ++}; ++ ++struct nct6687d_smart_tracking_config { ++ uint8_t rpm_tolerance_low; ++ uint8_t rpm_tolerance_mid; ++ uint8_t rpm_tolerance_high; ++ ++ uint16_t speed_boundary_low; ++ uint16_t speed_boundary_high; ++ ++ /* Step tracking setting */ ++ uint8_t step_up; ++ uint8_t step_down; ++ ++ /* Fast tracking settings */ ++ uint8_t temp_boundary; ++ ++ enum nct6687d_fast_track_weight weight_up_low; ++ enum nct6687d_fast_track_weight weight_up_mid; ++ enum nct6687d_fast_track_weight weight_up_high; ++ enum nct6687d_fast_track_weight weight_down_low; ++ enum nct6687d_fast_track_weight weight_down_mid; ++ enum nct6687d_fast_track_weight weight_down_high; ++ ++ uint8_t duty_step_low; ++ uint8_t duty_step_mid; ++ uint8_t duty_step_high; ++ ++ /* Markup tracking setting */ ++ uint8_t ambient_temp_boundary; ++ uint8_t weight_val; ++}; ++ ++ ++struct nct6687d_fan_config { ++ enum nct6687d_fan_mode mode; ++ enum nct6687d_fan_unit_sel unit_sel; ++ enum nct6687d_tach_pwm_sel fanin_sel; ++ enum nct6687d_tach_pwm_sel fanout_sel; ++ ++ struct nct6687d_smart_fan_iv_config smart_fan; ++ struct nct6687d_manual_fan_config manual_fan; ++ struct nct6687d_fan_thermal_cruise_config thermal_cruise_fan; ++ struct nct6687d_fan_speed_cruise_config speed_cruise_fan; ++ ++ /* Fan ALG_FUNCTRL */ ++ uint8_t fan_alg_weight; ++ ++ uint8_t crit_temp; ++ uint8_t crit_temp_tolerance; ++ ++ uint8_t temp_err_duty; ++ ++ bool dts1_en; ++ bool dts2_en; ++ bool dts_ub_en; ++ ++ /* Fan FUN_CTRL */ ++ bool smart_tracking_en; ++ bool fast_tracking_en; ++ bool markup_tracking_en; ++ ++ bool ambient_floor_en; ++ struct nct6687d_ambient_floor_fan_config amb_floor_fan_cfg; ++ ++ uint8_t startup_duty; ++ uint8_t manual_offset; ++ uint8_t min_duty; ++}; ++ ++struct superio_nuvoton_nct6687d_config { ++ struct nct6687d_fan_config fans[MAX_NUM_FANS]; ++ enum nct6687d_sensor_src_select sensors[MAX_NUM_SENSORS]; ++ ++ enum nct6687d_peci_speed peci_speed; ++ ++ struct nct6687d_pch_smbus_sensor smbus_sensor; ++ struct nct6687d_dts_sensor_config dts_sensor; ++ struct nct6687d_dts2_sensor_config dts2_sensor; ++ ++ struct nct6687d_ambient_floor_config ambient_floor; ++ struct nct6687d_smart_tracking_config smart_tracking; ++ ++ uint8_t fan_default_val; ++}; ++ ++#define FAN1 fans[0] ++#define FAN2 fans[1] ++#define FAN3 fans[2] ++#define FAN4 fans[3] ++#define FAN5 fans[4] ++#define FAN6 fans[5] ++#define FAN7 fans[6] ++#define FAN8 fans[7] ++#define FAN9 fans[8] ++#define FAN10 fans[9] ++ ++void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf); ++ ++#endif /* SUPERIO_NUVOTON_NCT6687D_CHIP_H */ +diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.c b/src/superio/nuvoton/nct6687d/nct6687d_ec.c +new file mode 100644 +index 0000000000..0b25b164b4 +--- /dev/null ++++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.c +@@ -0,0 +1,77 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++ ++#include "nct6687d_ec.h" ++ ++void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) ++{ ++ /* Need to write 0xff first to set the page */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ outb(page, iobase + EC_PORT0_PAGE); ++ outb(index, iobase + EC_PORT0_INDEX); ++ outb(value, iobase + EC_PORT0_DATA); ++ /* Need to write 0xff at the end of transaction */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++} ++ ++void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) ++{ ++ /* Need to write 0xff first to set the page */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ outb(page, iobase + EC_PORT0_PAGE); ++ /* Extra 0xff to the index register */ ++ outb(0xff, iobase + EC_PORT0_INDEX); ++ outb(index, iobase + EC_PORT0_INDEX); ++ outb(value, iobase + EC_PORT0_DATA); ++ /* Need to write 0xff at the end of transaction */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++} ++ ++void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, ++ uint8_t and_mask, uint8_t or_mask) ++{ ++ uint8_t val; ++ /* Need to write 0xff first to set the page */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ outb(page, iobase + EC_PORT0_PAGE); ++ outb(index, iobase + EC_PORT0_INDEX); ++ val = inb(iobase + EC_PORT0_DATA); ++ val &= and_mask; ++ val |= or_mask; ++ outb(val, iobase + EC_PORT0_DATA); ++ /* Need to write 0xff at the end of transaction */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++} ++ ++void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, ++ uint8_t and_mask, uint8_t or_mask) ++{ ++ uint8_t val; ++ /* Need to write 0xff first to set the page */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ outb(page, iobase + EC_PORT0_PAGE); ++ /* Extra 0xff to the index register */ ++ outb(0xff, iobase + EC_PORT0_INDEX); ++ outb(index, iobase + EC_PORT0_INDEX); ++ val = inb(iobase + EC_PORT0_DATA); ++ val &= and_mask; ++ val |= or_mask; ++ outb(val, iobase + EC_PORT0_DATA); ++ /* Need to write 0xff at the end of transaction */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++} ++ ++uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index) ++{ ++ uint8_t value; ++ /* Need to write 0xff first to set the page */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ outb(page, iobase + EC_PORT0_PAGE); ++ outb(index, iobase + EC_PORT0_INDEX); ++ value = inb(iobase + EC_PORT0_DATA); ++ /* Need to write 0xff at the end of transaction */ ++ outb(0xff, iobase + EC_PORT0_PAGE); ++ ++ return value; ++} +diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.h b/src/superio/nuvoton/nct6687d/nct6687d_ec.h +new file mode 100644 +index 0000000000..d32f32c467 +--- /dev/null ++++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#ifndef SUPERIO_NUVOTON_NCT6687D_EC_H ++#define SUPERIO_NUVOTON_NCT6687D_EC_H ++ ++#include ++ ++/* Offsets in the EC IO base. Port0 for firmware use, Port1 for software use */ ++#define EC_PORT0_PAGE 0 ++#define EC_PORT0_INDEX 1 ++#define EC_PORT0_DATA 2 ++#define EC_PORT0_HOST_IF_EVENT 3 ++ ++#define EC_PORT1_PAGE 4 ++#define EC_PORT1_INDEX 5 ++#define EC_PORT1_DATA 6 ++#define EC_PORT1_HOST_IF_EVENT 7 ++ ++void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); ++void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); ++void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, ++ uint8_t and_mask, uint8_t or_mask); ++void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, ++ uint8_t and_mask, uint8_t or_mask); ++uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index); ++ ++#endif /* SUPERIO_NUVOTON_NCT6687D_EC_H */ +diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.c b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c +new file mode 100644 +index 0000000000..262dd8a0e9 +--- /dev/null ++++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c +@@ -0,0 +1,960 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++#include ++ ++#include "chip.h" ++#include "nct6687d_hwm.h" ++ ++uint16_t nct6687d_hwm_base = 0; ++ ++static bool check_cond(const bool cond, const char* error) ++{ ++ if (!cond) ++ printk(BIOS_ERR, "NCT6687D: %s\n", error); ++ ++ return !cond; ++} ++ ++static inline void print_status_bit(const char* status, const bool cond) ++{ ++ printk(BIOS_DEBUG, "\t%-45s: %s\n", status, cond ? "yes" : "no"); ++} ++ ++static void print_fan_engine_status(void) ++{ ++ uint8_t fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); ++ ++ printk(BIOS_DEBUG, "NCT6687D: Fan Engine Status:\n"); ++ print_status_bit("PECI configuration adjusted", fan_eng_sts & FAN_PECI_CFG_ADJUSTED); ++ print_status_bit("All enabled fan channels processed", ++ fan_eng_sts & FAN_UNFINISHED_FLAG); ++ print_status_bit("Configuration phase", fan_eng_sts & FAN_CFG_PHASE); ++ print_status_bit("Configuration invalid", fan_eng_sts & FAN_CFG_INVALID); ++ print_status_bit("Configuration check done", fan_eng_sts & FAN_CFG_CHECK_DONE); ++ print_status_bit("Configuration locked", fan_eng_sts & FAN_CFG_LOCK); ++ printk(BIOS_DEBUG, "Fans in automatic mode driven by %s register\n", ++ (fan_eng_sts & FAN_DRIVE_BY_DEFAULT_VAL) ? "DEFAULT_VAL" : "MOD_SEL"); ++} ++ ++static bool unlock_fan_register_set(void) ++{ ++ uint8_t fan_eng_sts; ++ bool done = false; ++ unsigned int i; ++ ++ fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); ++ ++ if (!(fan_eng_sts & FAN_CFG_LOCK) && (fan_eng_sts & FAN_CFG_PHASE)) ++ return true; ++ ++ for (i = 1000; i > 0; i--) { ++ /* Wait until EC exits config phase and config request is clear */ ++ if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_PHASE) == 0 && ++ (hwm_reg_read(FAN_CFG_CTRL_REG) & FAN_CFG_REQUEST) == 0) { ++ done = true; ++ break; ++ } ++ mdelay(1); ++ } ++ ++ if (!done) { ++ printk(BIOS_WARNING, "Timeout waiting for EC to exit config phase or clear" ++ "config request\n"); ++ print_fan_engine_status(); ++ return false; ++ } ++ ++ done = false; ++ ++ hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_REQUEST); ++ ++ for (i = 1000; i > 0; i--) { ++ /* Wait until EC unlock the register set */ ++ if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_LOCK) == 0) { ++ done = true; ++ break; ++ } ++ mdelay(1); ++ } ++ ++ if (!done) { ++ printk(BIOS_WARNING, "Timeout waiting for EC to unlock the fan registers\n"); ++ print_fan_engine_status(); ++ return false; ++ } ++ ++ return true; ++} ++ ++static void print_last_err(uint8_t error_code) ++{ ++ uint8_t debug_level = BIOS_WARNING; ++ uint8_t last_err_code = hwm_reg_read(FAN_LAST_ERROR_CODE_REG); ++ ++ if (last_err_code == FAN_NO_ERROR) { ++ printk(BIOS_DEBUG, "No error occurred.\n"); ++ return; ++ } ++ ++ /* Lower the debug level if it is an error we care about */ ++ if (last_err_code == error_code) ++ debug_level = BIOS_ERR; ++ ++ switch (last_err_code) { ++ case FAN_ERR_MODE_SELECT: ++ printk(debug_level, "Mode Select invalid configuration\n"); ++ break; ++ case FAN_ERR_CRIT_TEMP_PROTECT: ++ printk(debug_level, "Critical Temperature Protection invalid configuration\n"); ++ break; ++ case FAN_ERR_ITL_FAN_CONTROL: ++ printk(debug_level, "Intel DTS Sensor invalid configuration\n"); ++ break; ++ case FAN_ERR_SMART_TRACKING: ++ printk(debug_level, "Smart Tracking invalid configuration\n"); ++ break; ++ case FAN_ERR_THERMAL_CRUISE: ++ printk(debug_level, "Thermal Cruise invalid configuration\n"); ++ break; ++ case FAN_ERR_SPEED_CRUISE: ++ printk(debug_level, "Speed Cruise invalid configuration\n"); ++ break; ++ case FAN_ERR_SMART_FAN_IV: ++ printk(debug_level, "Smart Fan IV invalid configuration\n"); ++ break; ++ case FAN_ERR_PID_CONTROL: ++ printk(debug_level, "PID control invalid configuration\n"); ++ break; ++ default: ++ printk(debug_level, "Unkown fan configuration error %02x\n", last_err_code); ++ break; ++ } ++} ++ ++static void lock_fan_register_set_and_check(uint8_t error_code) ++{ ++ uint8_t fan_eng_sts; ++ bool done = false; ++ unsigned int i; ++ ++ fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); ++ ++ if (fan_eng_sts & FAN_CFG_LOCK || !(fan_eng_sts & FAN_CFG_PHASE)) { ++ printk(BIOS_DEBUG, "Fan register set already locked or not in config phase\n"); ++ return; ++ } ++ ++ hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_DONE); ++ ++ for (i = 1000; i > 0; i--) { ++ fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); ++ /* Wait until EC checks the configuration */ ++ if (fan_eng_sts & FAN_CFG_CHECK_DONE) { ++ done = true; ++ break; ++ } ++ mdelay(1); ++ } ++ ++ if (!done) { ++ printk(BIOS_WARNING, "Timeout waiting for configuration check done\n"); ++ print_fan_engine_status(); ++ return; ++ } ++ ++ fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); ++ ++ if (fan_eng_sts & FAN_CFG_INVALID) { ++ printk(BIOS_WARNING, "NCT6687D: Configuration error ocurred\n"); ++ print_last_err(error_code); ++ } ++ ++ if (!(fan_eng_sts & FAN_CFG_LOCK)) { ++ printk(BIOS_WARNING, "NCT6687D: Configuration registers did not lock\n"); ++ print_fan_engine_status(); ++ } ++} ++ ++static void init_pch_smbus_sensor(const struct nct6687d_pch_smbus_sensor *smbus_sensor) ++{ ++ if (!smbus_sensor->sensor_addr || !smbus_sensor->sensor_cmd) { ++ printk(BIOS_ERR, "NCT6687D SMBus sensor CMD or ADDR missing!\n"); ++ return; ++ } ++ ++ /* Enable SMBUS first */ ++ hwm_reg_write(SMBUS_MASTER_CFG2_REG, 0x04); ++ hwm_reg_write(SMBUS_MASTER_BAUD_RATE_SEL_REG, SMB_MASTER_BAUD_100K); ++ hwm_reg_set_bits(SMBUS_MASTER_CFG1_REG, SMB_MASTER_EN); ++ ++ hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_BAUD_SEL_MASK, ++ smbus_sensor->baud_rate & PCH_BAUD_SEL_MASK); ++ hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_PORT_SEL_MASK, ++ PCH_THERMAL_PORT(smbus_sensor->port_sel) & PCH_PORT_SEL_MASK); ++ ++ if (smbus_sensor->report_one_byte) ++ hwm_reg_set_bits(PCH_THERMAL_DATA_CFG_REG, PCH_ONE_BYTE_REPORT); ++ else ++ hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_ONE_BYTE_REPORT & 0xff, 0); ++ ++ ++ hwm_reg_write(PCH_DEVICE_ADDR_REG, smbus_sensor->sensor_addr); ++ hwm_reg_write(PCH_THERMAL_CMD_REG, smbus_sensor->sensor_cmd); ++} ++ ++static void init_sensors(const struct superio_nuvoton_nct6687d_config *conf) ++{ ++ unsigned int i; ++ bool peci_en = false; ++ const enum nct6687d_sensor_src_select *sensors = conf->sensors; ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping sensors programming\n"); ++ return; ++ } ++ ++ printk(BIOS_DEBUG, "NCT6687D programming sensors\n"); ++ /* Start monitoring */ ++ hwm_reg_set_bits(HWM_CONFIG_REG, HWM_EN); ++ ++ for (i = 0; i < MAX_NUM_SENSORS; i++) { ++ hwm_reg_write(SENSOR_CFG_REG(i), sensors[i] & SENSOR_SRC_SEL_MASK); ++ ++ if (sensors[i] >= PECI_AGENT0_DOMAIN0 && ++ sensors[i] <= PECI_AGENT3_DOMAIN1) { ++ hwm_reg_and_or(PECI_AGENT_EN_REG, ~PECI_AGENT_EN_MASK, ++ PECI_AGENT_EN(sensors[i] & 0x3)); ++ peci_en = true; ++ } ++ ++ /* Only PCH SMBus sensor supported right now */ ++ if (sensors[i] >= PCH_CPU && sensors[i] <= PCH_DIMM3 && ++ i == conf->smbus_sensor.sensor_idx && ++ conf->smbus_sensor.sensor_en) { ++ init_pch_smbus_sensor(&conf->smbus_sensor); ++ } ++ } ++ ++ if (peci_en) { ++ hwm_reg_and_or(PECI_CFG_REG, PECI_SPEED_SEL_MASK, ++ conf->peci_speed & PECI_SPEED_SEL_MASK); ++ hwm_reg_set_bits(PECI_CFG_REG, PECI_AGENT_INIT | PECI_EN); ++ } ++ ++ lock_fan_register_set_and_check(FAN_NO_ERROR); ++} ++ ++static bool intel_dts_sensor_control_point_check(const struct nct6687d_dts_sensor_config *dts, ++ unsigned int i) ++{ ++ bool failure = false; ++ ++ failure |= check_cond(dts->ambient_temp[i] <= 127, ++ "DTS Sensor Ambient Temperature Levels should be <= 127"); ++ ++ if (i < MAX_DTS_CTL_POINTS - 1) { ++ failure |= check_cond(dts->ambient_temp[i + 1] >= dts->ambient_temp[i], ++ "DTS Sensor next Ambient Temperature Level must be " ++ "higher or equal to previous Ambient Temperature Level"); ++ failure |= check_cond(dts->rpm_start_point[i + 1] > dts->rpm_start_point[i], ++ "DTS Sensor next RPM Start Point must be higher than " ++ "previous RPM Start Point"); ++ failure |= check_cond(dts->rpm_end_point[i + 1] > dts->rpm_end_point[i], ++ "DTS Sensor next RPM End Point must be higher than " ++ "previous RPM End Point"); ++ } ++ ++ failure |= check_cond(dts->rpm_end_point[i] > dts->rpm_start_point[i], ++ "DTS Sensor RPM End Point must be higher than corresponding RPM " ++ "Start Point"); ++ ++ return failure; ++} ++ ++static bool intel_dts_sensor_config_check(const struct nct6687d_dts_sensor_config *dts) ++{ ++ bool failure = false; ++ unsigned int i; ++ ++ failure |= check_cond(dts->temp_end > dts->temp_start, ++ "DTS Sensor Temperture End Point should be > " ++ "Temperture End Point"); ++ failure |= check_cond(dts->temp_start <= 127, ++ "DTS Sensor Temperture Start Point should be <= 127"); ++ failure |= check_cond(dts->temp_end <= 127, ++ "DTS Sensor Temperture End Point should be <= 127"); ++ ++ if (dts->peci_adjust) { ++ failure |= check_cond(dts->peci_agent_idx < 8, ++ "DTS Sensor PECI Agent Index should be < 8"); ++ } ++ ++ for (i = 0; i < MAX_DTS_CTL_POINTS; i++) ++ failure |= intel_dts_sensor_control_point_check(dts, i); ++ ++ return failure; ++} ++ ++static void init_intel_dts_sensor(const struct nct6687d_dts_sensor_config *dts) ++{ ++ static int init_once = 0; ++ unsigned int i; ++ ++ if (init_once) ++ return; ++ ++ if (intel_dts_sensor_config_check(dts)) { ++ printk(BIOS_ERR, "NCT6687D DTS Sensor invalid config, " ++ "skipping sensor programming\n"); ++ return; ++ } ++ ++ printk(BIOS_DEBUG, "NCT6687D programming DTS sensor\n"); ++ ++ hwm_reg_write(ITL_TEMP_START_POINT_REG, dts->temp_start); ++ hwm_reg_write(ITL_TEMP_END_POINT_REG, dts->temp_end); ++ ++ hwm_reg_write(ITL_RPM_MAX_SPEED_HI_REG, dts->max_speed >> 8); ++ hwm_reg_write(ITL_RPM_MAX_SPEED_LO_REG, dts->max_speed & 0xff); ++ ++ for (i = 0; i < MAX_DTS_CTL_POINTS; i++) { ++ hwm_reg_write(ITL_AMB_TEMP_START_POINT_REG(i), dts->ambient_temp[i]); ++ hwm_reg_write(ITL_RPM_START_POINT_HI_REG(i), dts->rpm_start_point[i] >> 8); ++ hwm_reg_write(ITL_RPM_START_POINT_LO_REG(i), dts->rpm_start_point[i] & 0xff); ++ hwm_reg_write(ITL_RPM_END_POINT_HI_REG(i), dts->rpm_end_point[i] >> 8); ++ hwm_reg_write(ITL_RPM_END_POINT_LO_REG(i), dts->rpm_end_point[i] & 0xff); ++ } ++ ++ if (dts->peci_adjust) { ++ hwm_reg_and_or(ITL_DTS_CFG_REG, ~ITL_DTS_PECI_AGENT_IDX_SEL_MASK, ++ dts->peci_agent_idx & ITL_DTS_PECI_AGENT_IDX_SEL_MASK); ++ hwm_reg_set_bits(ITL_DTS_CFG_REG, ITL_DTS_PECI_CFG_ADJUSTMENT); ++ } ++ ++ init_once = 1; ++} ++ ++static void init_intel_dts2_sensor(const struct nct6687d_dts2_sensor_config *dts2) ++{ ++ static int init_once = 0; ++ ++ if (init_once) ++ return; ++ ++ printk(BIOS_DEBUG, "NCT6687D programming DTS2 sensor\n"); ++ ++ hwm_reg_write(DTS2_TARGET_MARGIN_REG, (uint8_t)dts2->target_margin); ++ hwm_reg_write(DTS2_TCONTROL_REG, (uint8_t)dts2->t_control); ++ hwm_reg_write(DTS2_TCONTROL_OFFSET_REG, (uint8_t)dts2->t_control_offset); ++ hwm_reg_write(DTS2_TARGET_TOLERANCE_REG, dts2->target_margin_tolerance); ++ ++ hwm_reg_write(DTS2_STEP_SPEED_HI_REG, dts2->step_speed >> 8); ++ hwm_reg_write(DTS2_STEP_SPEED_LO_REG, dts2->step_speed & 0xff); ++ hwm_reg_write(DTS2_MIN_SPEED_HI_REG, dts2->min_speed >> 8); ++ hwm_reg_write(DTS2_MIN_SPEED_LO_REG, dts2->min_speed & 0xff); ++ ++ hwm_reg_write(DTS2_DELAY_TIME_COUNTER_REG, dts2->delay_time); ++ hwm_reg_write(DTS2_DIVISOR_REG, dts2->divisor); ++ ++ init_once = 1; ++} ++ ++static void lock_sensor_config(void) ++{ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping misc fan config programming\n"); ++ return; ++ } ++ hwm_reg_set_bits(HWM_CONFIG_REG, LOCK_SENSOR_CFG); ++ lock_fan_register_set_and_check(FAN_NO_ERROR); ++} ++ ++static void init_ambient_floor_alg(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ static int init_once = 0; ++ const struct nct6687d_ambient_floor_fan_config *amb_floor_fan; ++ const struct nct6687d_ambient_floor_config *amb_floor_cfg = &conf->ambient_floor; ++ ++ amb_floor_fan = &conf->fans[idx - 1].amb_floor_fan_cfg; ++ ++ printk(BIOS_DEBUG, "NCT6687D initializing ambient floor algorithm\n"); ++ ++ if (!init_once) { ++ hwm_reg_write(AMBIENT_FLOOR_TEMP_START_POINT_REG, amb_floor_cfg->temp_start); ++ hwm_reg_write(AMBIENT_FLOOR_TEMP_END_POINT_REG, amb_floor_cfg->temp_end); ++ init_once = 1; ++ } ++ ++ hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_START_REG(idx), ++ FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_start)); ++ hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_END_REG(idx), ++ FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_end)); ++ hwm_reg_write(FAN_AMB_FLOOR_MAX_OUT_REG(idx), ++ FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_max)); ++} ++ ++static void init_smart_tracking_alg(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ static int init_once = 0; ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ const struct nct6687d_smart_tracking_config *smart_track = &conf->smart_tracking; ++ ++ printk(BIOS_DEBUG, "NCT6687D initializing smart tracking algorithm\n"); ++ ++ if (!init_once) { ++ hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG, ++ smart_track->speed_boundary_low >> 8); ++ hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG, ++ smart_track->speed_boundary_low & 0xff); ++ hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG, ++ smart_track->speed_boundary_high >> 8); ++ hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG, ++ smart_track->speed_boundary_high & 0xff); ++ hwm_reg_write(FAN_LOW_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_low); ++ hwm_reg_write(FAN_MID_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_mid); ++ hwm_reg_write(FAN_HIGH_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_high); ++ ++ hwm_reg_write(FAN_TRACKING_STEP_REG, ((smart_track->step_up & 0xf) << 4) | ++ (smart_track->step_down & 0xf)); ++ ++ hwm_reg_write(FAN_FAST_TRACK_TEMP_BOUNDARY_REG, smart_track->temp_boundary); ++ ++ hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG, ++ ((smart_track->weight_up_low & 7) << 4) | ++ (smart_track->weight_down_low & 7)); ++ hwm_reg_write(FAN_MID_RPM_FAST_TRACK_WEIGHT_REG, ++ ((smart_track->weight_up_mid & 7) << 4) | ++ (smart_track->weight_down_mid & 7)); ++ hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG, ++ ((smart_track->weight_up_high & 7) << 4) | ++ (smart_track->weight_down_high & 7)); ++ ++ hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG, ++ smart_track->duty_step_low & 0xf); ++ hwm_reg_write(FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG, ++ smart_track->duty_step_mid & 0xf); ++ hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG, ++ smart_track->duty_step_high & 0xf); ++ ++ hwm_reg_write(FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG, ++ smart_track->ambient_temp_boundary); ++ ++ hwm_reg_write(FAN_MARKUP_TRACK_WEIGHT_REG, smart_track->weight_val & 7); ++ ++ init_once = 1; ++ } ++ ++ if (fan->fast_tracking_en) ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_FAST_TRACK_EN); ++ ++ ++ if (fan->markup_tracking_en) ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MARKUP_TRACK_EN); ++} ++ ++static void misc_fan_config(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping misc fan config programming\n"); ++ return; ++ } ++ ++ if (fan->fan_alg_weight) { ++ printk(BIOS_DEBUG, "Programming algorithm weight for FAN%d\n", idx); ++ hwm_reg_and_or(FAN_ALG_ENGINE_WEIGHT_VAL_REG(idx), ++ ~FAN_ALG_ENGINE_WEIGHT_MASK(idx), ++ (fan->fan_alg_weight & 0xf) << ++ FAN_ALG_ENGINE_WEIGHT_SHIFT(idx)); ++ hwm_reg_set_bits(FAN_ALG_ENGINE_WEIGHT_EN_REG(idx), ++ FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(idx)); ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_ALG_EN); ++ } ++ ++ if (fan->crit_temp) { ++ if (!check_cond(fan->crit_temp >= fan->crit_temp_tolerance, ++ "Fan Critical Temperature should be >= " ++ "Critical Temperature Tolerance")) { ++ printk(BIOS_DEBUG, "Enabling critical temperature for FAN%d\n", idx); ++ hwm_reg_write(FAN_CRIT_TEMP_CFG_REG(idx), fan->crit_temp & 0x7f); ++ if (fan->crit_temp_tolerance) ++ hwm_reg_write(FAN_CRIT_TEMP_TOLERANCE_REG(idx), ++ fan->crit_temp_tolerance & 0xf); ++ ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), ++ FAN_ALG_FUNCTRL_CRIT_TEMP_EN); ++ } ++ } ++ ++ if (fan->temp_err_duty) { ++ hwm_reg_write(FAN_TEMP_ERR_DUTY_VAL_REG(idx), fan->temp_err_duty); ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_TEMP_ERR); ++ } ++ ++ if (fan->dts1_en && fan->dts2_en) { ++ printk(BIOS_ERR, "DTS and DTS2 sensors can't coexist!\n"); ++ printk(BIOS_ERR, "Skipping DTS configuration\n"); ++ } else { ++ if (fan->dts1_en) { ++ init_intel_dts_sensor(&conf->dts_sensor); ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS1_EN); ++ } ++ ++ if (fan->dts2_en) { ++ init_intel_dts2_sensor(&conf->dts2_sensor); ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS2_EN); ++ } ++ } ++ ++ if (fan->dts_ub_en) ++ hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS_UB_EN); ++ ++ ++ if (fan->smart_tracking_en) { ++ init_smart_tracking_alg(conf, idx); ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_SMART_TRACK_EN); ++ } ++ ++ if (conf->fan_default_val && conf->fan_default_val <= 100) ++ hwm_reg_write(FAN_DEFAULT_VAL_REG, ++ FAN_PWM_PERCENT_TO_HEX(conf->fan_default_val)); ++ ++ /* Some registers for functionalities below are missing for fan 9 and 10 */ ++ if (idx > 8) { ++ lock_fan_register_set_and_check(FAN_NO_ERROR); ++ return; ++ } ++ ++ if (fan->ambient_floor_en) { ++ init_ambient_floor_alg(conf, idx); ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_AMBIENT_FLOOR_EN); ++ } ++ ++ if (fan->startup_duty && fan->startup_duty <= 100) { ++ hwm_reg_write(FAN_STARTUP_DUTY_REG(idx), ++ FAN_PWM_PERCENT_TO_HEX(fan->startup_duty)); ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_STARTUP_EN); ++ } ++ ++ if (fan->manual_offset) { ++ hwm_reg_write(FAN_MANUAL_OFFSET_REG(idx), fan->manual_offset); ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MANUAL_OFFSET_EN); ++ } ++ ++ if (fan->min_duty && fan->min_duty <= 100) { ++ hwm_reg_write(FAN_MIN_DUTY_REG(idx), FAN_PWM_PERCENT_TO_HEX(fan->min_duty)); ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MINDUTY_EN); ++ } ++ ++ lock_fan_register_set_and_check(FAN_NO_ERROR); ++} ++ ++static void set_fan_pins_and_mode(const struct nct6687d_fan_config *fan, unsigned int idx) ++{ ++ enum nct6687d_fan_mode mode = fan->mode; ++ ++ /* FAN_IGNORE takes the mapping of manual mode to detect unitialized fans */ ++ if (mode == FAN_MODE_MANUAL) ++ mode = 0; ++ ++ hwm_reg_and_or(FAN_MODE_SEL_REG(idx), ~FAN_MODE_SEL_MASK, mode & FAN_MODE_SEL_MASK); ++ hwm_reg_and_or(FANIN_CFG_REG(idx), ~FANIN_PIN_SEL_MASK, ++ fan->fanin_sel & FANIN_PIN_SEL_MASK); ++ hwm_reg_set_bits(FANIN_CFG_REG(idx), FANIN_MONITOR_EN); ++ ++ hwm_reg_and_or(FANOUT_CFG_REG(idx), ~FANOUT_PIN_SEL_MASK, ++ fan->fanout_sel & FANOUT_PIN_SEL_MASK); ++ hwm_reg_set_bits(FANOUT_CFG_REG(idx), FANOUT_EN); ++} ++ ++static bool smart_fan_level_check(const struct nct6687d_fan_config *fan, ++ const struct nct6687d_smart_fan_iv_config *s_fan, ++ int i) ++{ ++ bool failure = false; ++ ++ failure |= check_cond(s_fan->temp_levels[i] <= 127, ++ "Smart Fan IV Temperature Levels should be <= 127"); ++ if (i < MAX_TEMP_SPEED_LEVELS - 1) { ++ failure |= check_cond(s_fan->temp_levels[i + 1] >= s_fan->temp_levels[i], ++ "Smart Fan IV next Temperature Level must be higher" ++ " or equal to previous Temperature Level"); ++ failure |= check_cond(s_fan->speed_levels[i + 1] >= s_fan->speed_levels[i], ++ "Smart Fan IV next Speed Level must be higher or " ++ "equal to previous Speed Level"); ++ } ++ ++ if (fan->unit_sel == FAN_PWM) { ++ failure |= check_cond(s_fan->speed_levels[i] <= 100, ++ "Smart Fan IV PWM Speed Levels should be <= 100"); ++ } else if (fan->unit_sel == FAN_RPM) { ++ failure |= check_cond(s_fan->speed_levels[i] <= 0x3fff, ++ "Smart Fan IV RPM Speed Levels should be" ++ "<= 16383 RPM"); ++ } else { ++ failure |= check_cond(false, "Smart Fan IV invalid Fan Unit Selection"); ++ } ++ ++ return failure; ++ ++} ++ ++static bool smart_fan_config_check(const struct nct6687d_fan_config *fan, ++ const struct nct6687d_smart_fan_iv_config *s_fan) ++{ ++ bool failure = false; ++ unsigned int i; ++ ++ for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) ++ failure |= smart_fan_level_check(fan, s_fan, i); ++ ++ failure |= check_cond(s_fan->temp_levels[0] >= s_fan->temp_cut_off, ++ "Smart Fan IV Temperature Level 1 should be >= " ++ "Temperature Cut Off"); ++ failure |= check_cond(s_fan->temp_levels[0] >= ++ (s_fan->temp_cut_off + s_fan->temp_hystheresis), ++ "Smart Fan IV Temperature Level 1 should be >= " ++ "Temperature Cut Off + Temperature Hysteresis"); ++ ++ return failure; ++} ++ ++static void init_smart_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) ++{ ++ unsigned int i; ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ const struct nct6687d_smart_fan_iv_config *sfan = &fan->smart_fan; ++ ++ if (smart_fan_config_check(fan, sfan)) { ++ printk(BIOS_ERR, "NCT6687D Smart Fan IV invalid config, " ++ "skipping fan programming\n"); ++ return; ++ } ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping Smart Fan IV config programming\n"); ++ return; ++ } ++ ++ set_fan_pins_and_mode(fan, idx); ++ ++ if (fan->unit_sel == FAN_PWM) ++ hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, ++ FAN_FUN_UNIT_PWM_DUTY); ++ else if (fan->unit_sel == FAN_RPM) ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); ++ ++ /* Registers start from MSB */ ++ for (i = 0; i < MAX_TEMP_SRC; i++) { ++ hwm_reg_write(FAN_MTZ_DCS_DATA_REG(MAX_TEMP_SRC - 1 - i, idx), ++ sfan->temp_src[i]); ++ } ++ ++ for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) { ++ if (sfan->temp_levels[i]) ++ hwm_reg_write(FAN_SF4_TEMP_LVL_REG(idx, i), ++ sfan->temp_levels[i]); ++ if (sfan->speed_levels[i]) { ++ if (fan->unit_sel == FAN_PWM) { ++ hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), 0); ++ hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), ++ FAN_PWM_PERCENT_TO_HEX(sfan->speed_levels[i])); ++ } ++ ++ if (fan->unit_sel == FAN_RPM) { ++ hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), ++ sfan->speed_levels[i] >> 8); ++ hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), ++ sfan->speed_levels[i] & 0xff); ++ } ++ } ++ } ++ ++ hwm_reg_write(FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(idx), sfan->temp_hystheresis); ++ hwm_reg_write(FAN_SF4_TEMP_CUT_OFF_REG(idx), sfan->temp_cut_off); ++ hwm_reg_write(FAN_SF4_TEMP_OFF_DELAY_REG(idx), sfan->cut_off_delay); ++ ++ hwm_reg_write(FAN_STEP_UP_TIME_REG(idx), sfan->step_up_time); ++ hwm_reg_write(FAN_STEP_DOWN_TIME_REG(idx), sfan->step_down_time); ++ ++ /* Set fan mode to automatic */ ++ hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); ++ ++ hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); ++ ++ lock_fan_register_set_and_check(FAN_ERR_SMART_FAN_IV); ++ ++ misc_fan_config(conf, idx); ++} ++ ++static void init_manual_fan(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ const struct nct6687d_manual_fan_config *manual_fan = &fan->manual_fan; ++ ++ if (manual_fan->manual_duty || manual_fan->manual_duty > 100) { ++ printk(BIOS_ERR, "NCT6687D: invalid duty cycle for manual fan mode\n"); ++ return; ++ } ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping manual fan config programming\n"); ++ return; ++ } ++ ++ set_fan_pins_and_mode(fan, idx); ++ ++ if (fan->unit_sel == FAN_PWM) ++ hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, ++ FAN_FUN_UNIT_PWM_DUTY); ++ else if (fan->unit_sel == FAN_RPM) ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); ++ ++ hwm_reg_write(FAN_MANUAL_VALUE_REG(idx), ++ FAN_PWM_PERCENT_TO_HEX(manual_fan->manual_duty)); ++ ++ hwm_reg_set_bits(FAN_MANUAL_EN_REG(idx), FAN_MANUAL_EN(idx)); ++ ++ hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); ++ ++ lock_fan_register_set_and_check(FAN_NO_ERROR); ++ ++ misc_fan_config(conf, idx); ++} ++ ++static bool thermal_cruise_config_check(const struct nct6687d_fan_thermal_cruise_config *tc_fan) ++{ ++ bool failure = false; ++ ++ failure |= check_cond(tc_fan->step_down_time > 0, ++ "Thermal Cruise Step-Down Time should be > 0"); ++ failure |= check_cond(tc_fan->step_up_time > 0, ++ "Thermal Cruise Step-Up Time should be > 0"); ++ failure |= check_cond(tc_fan->initial_value > tc_fan->stop_value, ++ "Thermal Cruise Initial value should be > Stop Value"); ++ failure |= check_cond(tc_fan->target_temp >= tc_fan->temp_tolerance, ++ "Thermal Cruise Target Temperature should be" ++ " >= Temperature Tolerance"); ++ if (tc_fan->keep_min_fan_output) { ++ failure |= check_cond(tc_fan->stop_value > 0, ++ "Thermal Cruise Stop Value should be > 0"); ++ } else { ++ failure |= check_cond(tc_fan->stop_time > 0, ++ "Thermal Cruise Stop Time should be > 0"); ++ } ++ ++ return failure; ++} ++ ++static void init_thermal_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ const struct nct6687d_fan_thermal_cruise_config *tc_fan = &fan->thermal_cruise_fan; ++ ++ if (thermal_cruise_config_check(tc_fan)) { ++ printk(BIOS_ERR, "NCT6687D Thermal Cruise invalid config, " ++ "skipping fan programming\n"); ++ return; ++ } ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping Thermal Cruise fan config programming\n"); ++ return; ++ } ++ ++ set_fan_pins_and_mode(fan, idx); ++ ++ hwm_reg_write(FAN_TC_TARGET_TEMP_REG(idx), ++ tc_fan->target_temp & FAN_TC_TARGET_TEMP_MASK); ++ ++ if (tc_fan->keep_min_fan_output) { ++ hwm_reg_set_bits(FAN_TC_TARGET_TEMP_REG(idx), FAN_TC_KEEP_MIN_OUTPUT); ++ hwm_reg_write(FAN_TC_STOP_VALUE_REG(idx), tc_fan->stop_value); ++ } ++ ++ hwm_reg_write(FAN_TC_TARGET_TEMP_TOLERANCE_REG(idx), ++ tc_fan->temp_tolerance & FAN_TC_TEMP_TOLERANCE_MASK); ++ ++ hwm_reg_write(FAN_INITIAL_VALUE_REG(idx), tc_fan->initial_value); ++ ++ hwm_reg_write(FAN_TC_STOP_TIME_REG(idx), tc_fan->stop_time); ++ hwm_reg_write(FAN_TC_STEP_DOWN_TIME_REG(idx), tc_fan->step_up_time); ++ hwm_reg_write(FAN_TC_STEP_UP_TIME_REG(idx), tc_fan->step_down_time); ++ ++ /* Set fan mode to automatic */ ++ hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0); ++ ++ hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); ++ ++ lock_fan_register_set_and_check(FAN_ERR_THERMAL_CRUISE); ++ ++ misc_fan_config(conf, idx); ++} ++ ++static bool speed_cruise_config_check(const struct nct6687d_fan_speed_cruise_config *sc_fan) ++{ ++ bool failure = false; ++ ++ failure |= check_cond(sc_fan->target_rpm <= 0x3fff, ++ "Speed Cruise Target RPM should be <= 16838 RPM"); ++ failure |= check_cond(sc_fan->target_rpm >= sc_fan->rpm_tolerance, ++ "Speed Cruise Target RPM should be >= RPM Tolerance"); ++ failure |= check_cond(sc_fan->step_down_time > 0, ++ "Speed Cruise Step-Down Time should be > 0"); ++ failure |= check_cond(sc_fan->step_up_time > 0, ++ "Speed Cruise Step-Up Time should be > 0"); ++ ++ return failure; ++} ++ ++static void init_speed_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, ++ unsigned int idx) ++{ ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ const struct nct6687d_fan_speed_cruise_config *sc_fan = &fan->speed_cruise_fan; ++ ++ if (speed_cruise_config_check(sc_fan)) { ++ printk(BIOS_ERR, "NCT6687D Speed Cruise invalid config, " ++ "skipping fan programming\n"); ++ return; ++ } ++ ++ if (!unlock_fan_register_set()) { ++ printk(BIOS_ERR, "NCT6687D failed to unlock registers, " ++ "skipping Speed Cruise fan config programming\n"); ++ return; ++ } ++ ++ set_fan_pins_and_mode(fan, idx); ++ ++ /* Speed cruise should only enable RPM units */ ++ hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); ++ ++ hwm_reg_write(FAN_SC_TARGET_RPM_HI_REG(idx), sc_fan->target_rpm >> 8); ++ hwm_reg_write(FAN_SC_TARGET_RPM_LO_REG(idx), sc_fan->target_rpm & 0xff); ++ ++ hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(idx), sc_fan->rpm_tolerance >> 8); ++ hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(idx), sc_fan->rpm_tolerance & 0xff); ++ ++ hwm_reg_write(FAN_SC_STEP_DOWN_TIME_REG(idx), sc_fan->step_up_time); ++ hwm_reg_write(FAN_SC_STEP_UP_TIME_REG(idx), sc_fan->step_down_time); ++ ++ /* Set fan mode to automatic */ ++ hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); ++ ++ hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); ++ ++ lock_fan_register_set_and_check(FAN_ERR_SPEED_CRUISE); ++ ++ misc_fan_config(conf, idx); ++}; ++ ++static void init_one_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) ++{ ++ const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; ++ ++ switch(fan->mode) { ++ case FAN_THERMAL_CRUISE: ++ printk(BIOS_DEBUG, "Initializing Thermal Cruise for FAN%d\n", idx); ++ init_thermal_cruise_fan(conf, idx); ++ break; ++ case FAN_SPEED_CRUISE: ++ printk(BIOS_DEBUG, "Initializing Speed Cruise for FAN%d\n", idx); ++ init_speed_cruise_fan(conf, idx); ++ break; ++ case FAN_SMART_FAN_IV: ++ printk(BIOS_DEBUG, "Initializing Smart FAN IV for FAN%d\n", idx); ++ init_smart_fan(conf, idx); ++ break; ++ case FAN_PID_CONTROL: ++ printk(BIOS_WARNING, "NCT6687D: PID Control fan mode not yet supported\n"); ++ break; ++ case FAN_MODE_MANUAL: ++ printk(BIOS_DEBUG, "Initializing manual fan mode for FAN%d\n", idx); ++ init_manual_fan(conf, idx); ++ break; ++ default: ++ printk(BIOS_ERR, "NCT6687D: unknown fan mode detected!\n"); ++ } ++} ++ ++static void init_fans(const struct superio_nuvoton_nct6687d_config *conf) ++{ ++ unsigned int i; ++ const struct nct6687d_fan_config *fans = conf->fans; ++ ++ for (i = 1; i <= MAX_NUM_FANS; i++) { ++ if (fans[i - 1].mode == FAN_IGNORE) ++ continue; ++ ++ init_one_fan(conf, i); ++ } ++} ++ ++static void report_ec_info(void) ++{ ++ unsigned int i; ++ ++ printk(BIOS_DEBUG, "NCT6687D EC info:\n"); ++ printk(BIOS_DEBUG, "\tChip ID: %04x\n", ++ (uint16_t)hwm_reg_read(CHIP_ID0_REG) | ++ (uint16_t)(hwm_reg_read(CHIP_ID1_REG) << 8)); ++ printk(BIOS_DEBUG, "\tCustomer ID: %04x\n", ++ (uint16_t)hwm_reg_read(CUSTOMER_ID0_REG) | ++ (uint16_t)(hwm_reg_read(CUSTOMER_ID1_REG) << 8)); ++ printk(BIOS_DEBUG, "\tFW build date: %02d/%02d/20%02d\n", ++ hwm_reg_read(FW_BUILD_DAY_REG), ++ hwm_reg_read(FW_BUILD_MONTH_REG), ++ hwm_reg_read(FW_BUILD_YEAR_REG)); ++ printk(BIOS_DEBUG, "\tFW build serial number: %d\n", ++ hwm_reg_read(FW_BUILD_SERIALNUM_REG)); ++ printk(BIOS_DEBUG, "\tFW version: %d.%d\n", ++ hwm_reg_read(FW_VER0_REG), ++ hwm_reg_read(FW_VER1_REG)); ++ printk(BIOS_DEBUG, "\tProfile version: %d\n", ++ hwm_reg_read(PROFILE_VER_REG)); ++ printk(BIOS_DEBUG, "\tROM version: %d.%d.%d.%d\n", ++ hwm_reg_read(ROM_VER0_REG), hwm_reg_read(ROM_VER1_REG), ++ hwm_reg_read(ROM_VER2_REG), hwm_reg_read(ROM_VER3_REG)); ++ printk(BIOS_DEBUG, "\tISP build date: %02d/%02d/20%02d\n", ++ hwm_reg_read(ISP_BUILD_DAY_REG), ++ hwm_reg_read(ISP_BUILD_MONTH_REG), ++ hwm_reg_read(ISP_BUILD_YEAR_REG)); ++ printk(BIOS_DEBUG, "\tISP build serial number: %d\n", ++ hwm_reg_read(ISP_BUILD_SERIALNUM_REG)); ++ printk(BIOS_DEBUG, "\tISP version: %d.%d\n", ++ hwm_reg_read(ISP_VER0_REG), ++ hwm_reg_read(ISP_VER1_REG)); ++ printk(BIOS_DEBUG, "\tOEM version:"); ++ ++ for (i = 0; i < OEM_VER_LEN; i++) ++ printk(BIOS_DEBUG, "%02x", hwm_reg_read(OEM_VER_REG + i)); ++ ++ printk(BIOS_DEBUG, "\n"); ++} ++ ++void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf) ++{ ++ nct6687d_hwm_base = hwm_base; ++ ++ report_ec_info(); ++ ++ init_sensors(conf); ++ init_fans(conf); ++ ++ lock_sensor_config(); ++ print_fan_engine_status(); ++} +diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.h b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h +new file mode 100644 +index 0000000000..0a7b83b7e3 +--- /dev/null ++++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h +@@ -0,0 +1,922 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#ifndef SUPERIO_NUVOTON_NCT6687D_HWM_H ++#define SUPERIO_NUVOTON_NCT6687D_HWM_H ++ ++#include ++#include ++ ++#include "chip.h" ++#include "nct6687d_ec.h" ++ ++/* ++ * EC page number will be concatenated with the register offset to mark ++ * which page the register belongs to. ++ */ ++#define EC_PAGE(page) ((page) << 8) ++#define EC_PAGE_REG(page, reg) (EC_PAGE(page) + (reg)) ++ ++/* EC page 1 */ ++#define SENSOR_READ_HI_REG(x) EC_PAGE_REG(1, 0x00 + 2*(x)) ++#define SENSOR_READ_LO_REG(x) EC_PAGE_REG(1, 0x01 + 2*(x)) ++#define FAN_RPM_READ_HI_REG(x) EC_PAGE_REG(1, 0x40 + 2*((x) - 1)) ++#define FAN_RPM_READ_LO_REG(x) EC_PAGE_REG(1, 0x41 + 2*((x) - 1)) ++ ++#define FAN_DUTY_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(8, 0xf0 + ((fan)-8)) \ ++ : EC_PAGE_REG(1, 0x60 + 2*((fan) - 1))) ++ ++#define SENSOR_MON_STS_REG EC_PAGE_REG(1, 0x70) ++#define TEMP_OVERLOAD (1 << 1) ++#define VOLT_OVERLOAD (1 << 1) ++#define FAN_OVERLOAD (1 << 2) ++ ++/* Errors and statuses */ ++#define PROCHOT_MON_STS_REG EC_PAGE_REG(1, 0x71) ++#define SENSOR_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x74 + (x)) ++#define TMPIN_IDLE_STS_REG(x) EC_PAGE_REG(1, 0x78 + (x)) ++#define FANIN_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x7C + (x)) ++#define FANOUT_ERROR_STS_REG EC_PAGE_REG(1, 0x7e) ++#define FAN_INIT_STS_REG EC_PAGE_REG(1, 0x7f) ++ ++#define HWM_CONFIG_REG EC_PAGE_REG(1, 0x80) ++#define SMI_SCI_SEL (1 << 2) ++#define LOCK_SENSOR_CFG (1 << 5) ++#define HWM_EN (1 << 7) ++ ++#define SENSOR_MON_VCC_DELAY_REG EC_PAGE_REG(1, 0x81) ++#define TEMPIN_IDLE_COUNTER_REG EC_PAGE_REG(1, 0x82) ++#define VIRTUAL_INPUT_CFG_REG EC_PAGE_REG(1, 0x83) ++#define TMPIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x85) ++#define VIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x86) ++#define FAN_POLLING_RATE_REG EC_PAGE_REG(1, 0x87) ++ ++#define ADC_CLOCKK_DIV_REG EC_PAGE_REG(1, 0x88) ++#define ADC_AVG_NUM_REG EC_PAGE_REG(1, 0x89) ++#define ADC_SLOPE_HI_REG EC_PAGE_REG(1, 0x8a) ++#define ADC_SLOPE_LO_REG EC_PAGE_REG(1, 0x8b) ++ ++#define PROCHOT_CFG_REG EC_PAGE_REG(1, 0x8e) ++#define REFRESH_RATE_MASK (3 << 0) ++#define REFRESH_RATE_100MS (0 << 0) ++#define REFRESH_RATE_200MS (1 << 0) ++#define REFRESH_RATE_500MS (2 << 0) ++#define REFRESH_RATE_1S (3 << 0) ++#define AVG_TIME_MASK (3 << 2) ++#define AVG_TIME_1 (0 << 2) ++#define AVG_TIME_2 (1 << 2) ++#define AVG_TIME_4 (2 << 2) ++#define AVG_TIME_8 (3 << 2) ++#define MONITOR_MODE_MASK (3 << 4) ++#define MONITOR_MODE_CAPTURE (0 << 4) ++#define MONITOR_MODE_8BIT (1 << 4) ++#define MONITOR_MODE_12BIT (2 << 4) ++#define MONITOR_MODE_16BIT (3 << 4) ++#define CLK_SRC_40K (0 << 6) ++#define CLK_SRC_MCLK (1 << 6) ++#define PROCHOT_EN (1 << 7) ++ ++#define PROCHOT_OUT_REG EC_PAGE_REG(1, 0x8f) ++ ++#define VIRTUAL_SENSOR_INPUT_REG(x) EC_PAGE_REG(1, 0x90 + (x)) ++ ++#define SENSOR_CFG_REG(x) EC_PAGE_REG(1, 0xa0 + (x)) ++#define FILTER_EN (1 << 7) ++#define SENSOR_SRC_SEL_MASK 0x7f ++ ++#define FANIN_CFG_REG(fan) EC_PAGE_REG(1, 0xc0 + ((fan) - 1)) ++#define FANIN_PIN_SEL_MASK 0x1f ++#define FANIN_PULSE_REV_MASK (3 << 5) ++#define FANIN_PULSE_REV_SHIFT 5 ++#define FANIN_MONITOR_EN (1 << 7) ++ ++#define FANOUT_CFG_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(8, 0xf4 + ((fan) - 9)) \ ++ : EC_PAGE_REG(1, 0xd0 + ((fan) - 1))) ++#define FANOUT_PIN_SEL_MASK 0x1f ++#define FANOUT_TYPE_PP (0 << 5) ++#define FANOUT_TYPE_OD (1 << 5) ++#define FANOUT_INV_EN (1 << 6) ++#define FANOUT_EN (1 << 7) ++ ++#define FAN_INIT_RPM_HI_REG(fan) EC_PAGE_REG(1, 0xe0 + 2*((fan) - 1)) ++#define FAN_INIT_RPM_LO_REG(fan) EC_PAGE_REG(1, 0xe1 + 2*((fan) - 1)) ++#define FAN_INIT_DUTY_VAL_REG(fan) EC_PAGE_REG(1, 0xf0 + ((fan) - 1)) ++#define FAN_INIT_MODE_REG EC_PAGE_REG(1, 0xf8) ++#define FAN_INIT_MODE_RPM(fan) (1 << ((fan) - 1)) ++#define FAN_INIT_MODE_PWM(fan) (0 << ((fan) - 1)) ++ ++#define FAN_RPM_INIT_UNIT_REG EC_PAGE_REG(1, 0xf9) ++#define FAN_RPM_INIT_TOLERANCE_REG EC_PAGE_REG(1, 0xfa) ++#define FAN_RPM_INIT_STABLE_COUNTER_REG EC_PAGE_REG(1, 0xfb) ++#define FAN_RPM_INIT_TIME_COUNTER_REG EC_PAGE_REG(1, 0xfc) ++ ++/* EC Page 2 - GPIO */ ++ ++#define TIN_OFFSET_REG(x) EC_PAGE_REG(2, 0x00 + (x)) ++ ++#define GPI_FALLING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb0) ++#define GPI_FALLING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb1) ++#define GPI_RISING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb2) ++#define GPI_RISING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb3) ++#define GPI_DATA_HI_REG EC_PAGE_REG(2, 0xb4) ++#define GPI_DATA_LO_REG EC_PAGE_REG(2, 0xb5) ++#define GPI_SEL_REG(x) EC_PAGE_REG(2, 0xc0 + (x)) ++#define GPO_TYPE_HI_REG EC_PAGE_REG(2, 0xd0) ++#define GPO_TYPE_LO_REG EC_PAGE_REG(2, 0xd1) ++#define GPO_DATA_HI_REG EC_PAGE_REG(2, 0xd4) ++#define GPO_DATA_LO_REG EC_PAGE_REG(2, 0xd5) ++#define GPO_SEL_REG(x) EC_PAGE_REG(2, 0xe0 + (x)) ++ ++/* EC page 3 */ ++ ++#define SENSOR_INT_CFG_REG(x) EC_PAGE_REG(3, 0x10 + (x)) ++#define TMPIN_INT_SEL_MASK (7 << 0) ++#define TMPIN_INT_DISABLE (0 << 0) ++#define TMPIN_INT_SHUTDOWN_MODE (1 << 0) ++#define TMPIN_INT_SYST_FAN_COMP_MODE (2 << 0) ++#define TMPIN_INT_CPUT_FAN_COMP_MODE (3 << 0) ++#define TMPIN_INT_TWO_TIMES_MODE (4 << 0) ++#define TMPIN_INT_ONE_TIME_MODE (5 << 0) ++#define TMPIN_INT_OVT_COMP_MODE (6 << 0) ++#define TMPIN_INT_OVT_MODE (7 << 0) ++#define VIN_INT_EN (1 << 7) ++ ++#define TMPIN_HYSTERSIS_REG(x) EC_PAGE_REG(3, 0x30 + (x)) ++#define TMPIN_OVERTEMP_REG(x) EC_PAGE_REG(3, 0x50 + (x)) ++#define TIN_SHUTDOWN_VIN_LIMIT_HI_REG(x) EC_PAGE_REG(3, 0x70 + 2*(x)) ++#define TIN_SHUTDOWN_VIN_LIMIT_LO_REG(x) EC_PAGE_REG(3, 0x71 + 2*(x)) ++ ++#define FAN_RPM_INT_EN1_REG EC_PAGE_REG(3, 0xb0) ++#define FAN_RPM_INT_EN2_REG EC_PAGE_REG(3, 0xb1) ++ ++#define FAN_RPM_LIMIT_HI_REG(fan) EC_PAGE_REG(3, 0xb8 + 2*(fan)) ++#define FAN_RPM_LIMIT_LO_REG(fan) EC_PAGE_REG(3, 0xb9 + 2*(fan)) ++ ++/* EC Page 4 - SMBus */ ++ ++#define PCH_ERR_STS_REG EC_PAGE_REG(4, 0x00) ++#define TSI_ERR_STS_REG EC_PAGE_REG(4, 0x01) ++#define SMBUS_MASTER_ERR_STS_REG EC_PAGE_REG(4, 0x04) ++#define SMBUS_THERM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x06 + (x)) ++#define SMBUS_DIMM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x0c + (x)) ++ ++#define PCH_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x10) ++#define PCH_BAUD_SEL_MASK (7 << 0) ++#define PCH_BAUD_12_5K (0 << 0) ++#define PCH_BAUD_25K (1 << 0) ++#define PCH_BAUD_50K (2 << 0) ++#define PCH_BAUD_100K (3 << 0) ++#define PCH_BAUD_200K (4 << 0) ++#define PCH_BAUD_400K (5 << 0) ++#define PCH_BAUD_800K (6 << 0) ++#define PCH_BAUD_1200K (7 << 0) ++#define PCH_PORT_SEL_MASK (3 << 4) ++#define PCH_THERMAL_PORT(x) ((x) << 4) ++#define PCH_ONE_BYTE_REPORT (1 << 7) ++ ++#define PCH_DEVICE_ADDR_REG EC_PAGE_REG(4, 0x11) ++#define PCH_THERMAL_CMD_REG EC_PAGE_REG(4, 0x12) ++ ++#define TSI_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x14) ++#define TSI_BAUD_SEL_MASK (7 << 0) ++#define TSI_BAUD_12_5K (0 << 0) ++#define TSI_BAUD_25K (1 << 0) ++#define TSI_BAUD_50K (2 << 0) ++#define TSI_BAUD_100K (3 << 0) ++#define TSI_BAUD_200K (4 << 0) ++#define TSI_BAUD_400K (5 << 0) ++#define TSI_BAUD_800K (6 << 0) ++#define TSI_BAUD_1200K (7 << 0) ++#define TSI_PORT_SEL_MASK (3 << 4) ++#define TSI_THERMAL_PORT(x) ((x) << 4) ++ ++#define SMBUS_SENSOR_CFG_REG(x) EC_PAGE_REG(4, 0x1a + 5*(x)) ++#define SMB_BAUD_SEL_MASK (7 << 0) ++#define SMB_BAUD_12_5K (0 << 0) ++#define SMB_BAUD_25K (1 << 0) ++#define SMB_BAUD_50K (2 << 0) ++#define SMB_BAUD_100K (3 << 0) ++#define SMB_BAUD_200K (4 << 0) ++#define SMB_BAUD_400K (5 << 0) ++#define SMB_BAUD_800K (6 << 0) ++#define SMB_BAUD_1200K (7 << 0) ++#define SMB_PORT_SEL_MASK (3 << 4) ++#define SMB_SENSOR_PORT(x) ((x) << 4) ++#define SMB_SENSOR_DATA_LEN_1B (0 << 6) ++#define SMB_SENSOR_DATA_LEN_2B (1 << 6) ++#define SMB_SENSOR_DIRECT_ACCESS (1 << 7) ++ ++#define SMBUS_SENSOR_ADDR_REG(x) EC_PAGE_REG(4, 0x1b + 5*(x)) ++#define SMBUS_SENSOR_CMD_REG(x) EC_PAGE_REG(4, 0x1c + 5*(x)) ++#define SMBUS_SENSOR_DATA_REG(x) EC_PAGE_REG(4, 0x1d + 5*(x)) ++#define SMBUS_SENSOR_READ_CMD_REG(x) EC_PAGE_REG(4, 0x1e + 5*(x)) ++ ++#define SMBUS_DIMM_SENSOR_CFG0(x) EC_PAGE_REG(4, 0x3a + 4*(x)) ++#define SMB_DIMM_ADDR_MASK 0x07 ++#define SMB_DIMM_BAUD_SEL_MASK (7 << 4) ++#define SMB_DIMM_BAUD_12_5K (0 << 0) ++#define SMB_DIMM_BAUD_25K (1 << 0) ++#define SMB_DIMM_BAUD_50K (2 << 0) ++#define SMB_DIMM_BAUD_100K (3 << 0) ++#define SMB_DIMM_BAUD_200K (4 << 0) ++#define SMB_DIMM_BAUD_400K (5 << 0) ++#define SMB_DIMM_BAUD_800K (6 << 0) ++#define SMB_DIMM_BAUD_1200K (7 << 0) ++#define SMBUS_DIMM_SENSOR_EN (1 << 7) ++ ++#define SMBUS_DIMM_SENSOR_CFG1_REG(x) EC_PAGE_REG(4, 0x3b + 4*(x)) ++/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ ++#define SMD_DIMM_ADDR_MASK 0x07 ++#define SMB_PORT_SEL_MASK (3 << 4) ++#define SMB_SENSOR_PORT(x) ((x) << 4) ++ ++#define SMBUS_DIMM_SENSOR_CFG2_REG(x) EC_PAGE_REG(4, 0x3c + 4*(x)) ++/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ ++ ++#define SMBUS_DIMM_SENSOR_CFG3_REG(x) EC_PAGE_REG(4, 0x3d + 4*(x)) ++/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ ++ ++#define SMBUS_MASTER_CFG1_REG EC_PAGE_REG(4, 0x60) ++#define SMB_MASTER_POLLRATE_MASK 0x07 ++#define SMB_MASTER_POLLRATE_ONCE (0 << 0) ++#define SMB_MASTER_POLLRATE_100MS (0 << 0) ++#define SMB_MASTER_POLLRATE_200MS (0 << 0) ++#define SMB_MASTER_POLLRATE_400MS (0 << 0) ++#define SMB_MASTER_POLLRATE_800MS (0 << 0) ++#define SMB_MASTER_POLLRATE_1S (0 << 0) ++#define SMB_MASTER_POLLRATE_2S (0 << 0) ++#define SMB_MASTER_POLLRATE_4S (0 << 0) ++#define SMB_MASTER_CLEAR_BUF (1 << 3) ++#define SMB_MASTER_HOLD_RDY (1 << 5) ++#define SMB_MASTER_START (1 << 6) ++#define SMB_MASTER_EN (1 << 7) ++ ++#define SMBUS_MASTER_CFG2_REG EC_PAGE_REG(4, 0x61) ++#define SMB_MASTER_PORT_SEL_MASK 0x03 ++#define SMB_MASTER_PORT(x) ((x) << 0) ++#define SMB_MASTER_PEC_EN (1 << 3) ++ ++#define SMBUS_MASTER_BAUD_RATE_SEL_REG EC_PAGE_REG(4, 0x62) ++#define SMB_MASTER_BAUD_SEL_MASK (7 << 4) ++#define SMB_MASTER_BAUD_12_5K (0 << 0) ++#define SMB_MASTER_BAUD_25K (1 << 0) ++#define SMB_MASTER_BAUD_50K (2 << 0) ++#define SMB_MASTER_BAUD_100K (3 << 0) ++#define SMB_MASTER_BAUD_200K (4 << 0) ++#define SMB_MASTER_BAUD_400K (5 << 0) ++#define SMB_MASTER_BAUD_800K (6 << 0) ++#define SMB_MASTER_BAUD_1200K (7 << 0) ++ ++#define SMBUS_MASTER_PROTOCOL_SEL_REG EC_PAGE_REG(4, 0x63) ++#define SMBUS_MASTER_QUICK_WRITE 0x00 ++#define SMBUS_MASTER_SEND_BYTE 0x01 ++#define SMBUS_MASTER_WRITE_BYTE 0x02 ++#define SMBUS_MASTER_WRITE_WORD 0x03 ++#define SMBUS_MASTER_BLOCK_WRITE 0x04 ++#define SMBUS_MASTER_PROCESS_CALL 0x05 ++#define SMBUS_MASTER_BLOCK_WRITE_READ 0x06 ++#define SMBUS_MASTER_RECEIVE_BYTE 0x81 ++#define SMBUS_MASTER_READ_BYTE 0x82 ++#define SMBUS_MASTER_READ_WORD 0x83 ++#define SMBUS_MASTER_BLOCK_READ 0x84 ++ ++#define SMBUS_MASTER_BLOCK_WR_LEN_REG EC_PAGE_REG(4, 0x64) ++#define SMBUS_MASTER_DEV_ADDR_REG EC_PAGE_REG(4, 0x65) ++#define SMBUS_MASTER_CMD_REG EC_PAGE_REG(4, 0x66) ++ ++#define SMBUS_MASTER_WRITE_BUFFER(x) EC_PAGE_REG(4, 0x70 + (x)) ++#define SMBUS_MASTER_WRITE_BUFFER_LEN 64 ++#define SMBUS_MASTER_READ_BUFFER(x) EC_PAGE_REG(4, 0xb0 + (x)) ++#define SMBUS_MASTER_READ_BUFFER_LEN 64 ++ ++/* EC page 5 - PECI */ ++ ++#define PECI_PING_INFO_REG EC_PAGE_REG(5, 0x00) ++#define PECI_AGENT_ALIVE(agent) (1 << (agent)) ++#define PECI_OVER_SMBUS (1 << 7) ++ ++#define PECI_INFO_STS_REG EC_PAGE_REG(5, 0x01) ++#define PECI_AGENT_INFO_RDY(agent) (1 << (agent)) ++ ++#define PECI_DEVICE_INFO_REG EC_PAGE_REG(5, 0x02) ++#define PECI_AGENT_TWO_DOMAIN_SUPPORT (1 << 2) ++ ++#define PECI_REVISION_INFO_REG EC_PAGE_REG(5, 0x03) ++#define PECI_REV_MINOR_MASK 0x0f ++#define PECI_REV_MINOR_SHIFT 0 ++#define PECI_REV_MAJOR_MASK 0xf0 ++#define PECI_REV_MAJOR_SHIFT 4 ++ ++#define PECI_DOM0_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x20 + 2*(agent)) ++#define PECI_DOM0_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x21 + 2*(agent)) ++#define PECI_DOM1_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x28 + 2*(agent)) ++#define PECI_DOM1_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x29 + 2*(agent)) ++ ++#define PECI_DOM0_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x30 + 2*(agent)) ++#define PECI_DOM0_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x31 + 2*(agent)) ++#define PECI_DOM1_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x38 + 2*(agent)) ++#define PECI_DOM1_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x39 + 2*(agent)) ++ ++#define PECI_TCONTROL_REG(dom, agent) EC_PAGE_REG(5, 0x40 + 4*(dom) + (agent)) ++#define PECI_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x48 + 4*(dom) + (agent)) ++ ++#define PECI_PCS_ERR_STS_REG EC_PAGE_REG(5, 0x52) ++#define PECI_MASTER_ERR_STS_REG EC_PAGE_REG(5, 0x53) ++ ++#define PECI_CFG_REG EC_PAGE_REG(5, 0x60) ++#define PECI_SPEED_SEL_MASK (3 << 0) ++#define PECI_SPEED_2MHZ (0 << 0) ++#define PECI_SPEED_1_2MHZ (1 << 0) ++#define PECI_SPEED_800KHZ (2 << 0) ++#define PECI_SPEED_400KHZ (3 << 0) ++#define PECI_USER_TJMAX_FROM_CPU (0 << 5) ++#define PECI_USER_TJMAX_FROM_EC (1 << 5) ++#define PECI_AGENT_INIT (1 << 6) ++#define PECI_EN (1 << 7) ++ ++#define PECI_AGENT_EN_REG EC_PAGE_REG(5, 0x61) ++#define PECI_AGENT_EN_MASK 0xf ++#define PECI_AGENT_EN(agent) (1 << (agent)) ++ ++#define PECI_HOSTID_REG EC_PAGE_REG(5, 0x62) ++#define PECI_ERR_RETRY_CFG_REG EC_PAGE_REG(5, 0x63) ++#define PECI_MARGIN_CFG_REG EC_PAGE_REG(5, 0x64) ++#define PECI_MARGIN_POLLRATE_MASK 0x07 ++#define PECI_MARGIN_POLLRATE_ONCE (0 << 0) ++#define PECI_MARGIN_POLLRATE_100MS (1 << 0) ++#define PECI_MARGIN_POLLRATE_200MS (2 << 0) ++#define PECI_MARGIN_POLLRATE_400MS (3 << 0) ++#define PECI_MARGIN_POLLRATE_800MS (4 << 0) ++#define PECI_MARGIN_POLLRATE_1S (5 << 0) ++#define PECI_MARGIN_POLLRATE_2S (6 << 0) ++#define PECI_MARGIN_POLLRATE_4S (7 << 0) ++#define PECI_GET_MARGIN_EN (1 << 7) ++ ++#define PECI_USER_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x68 + 4*(dom) + (agent)) ++#define PECI_PCS_CFG_REG 0x70 ++#define PECI_PCS_POLLRATE_MASK 0x07 ++#define PECI_PCS_POLLRATE_ONCE (0 << 0) ++#define PECI_PCS_POLLRATE_100MS (1 << 0) ++#define PECI_PCS_POLLRATE_200MS (2 << 0) ++#define PECI_PCS_POLLRATE_400MS (3 << 0) ++#define PECI_PCS_POLLRATE_800MS (4 << 0) ++#define PECI_PCS_POLLRATE_1S (5 << 0) ++#define PECI_PCS_POLLRATE_2S (6 << 0) ++#define PECI_PCS_POLLRATE_4S (7 << 0) ++#define PECI_PCS_STOP_ERR (1 << 4) ++#define PECI_PCS_HOLD_RDY (1 << 5) ++#define PECI_PCS_START (1 << 6) ++#define PECI_PCS_EN (1 << 7) ++ ++#define PECI_PCS_CFG2_REG EC_PAGE_REG(5, 0x71) ++#define PECI_PCS_AGENT_SEL_MASK 0x03 ++#define PECI_PCS_SEL_DOM0 (0 << 4) ++#define PECI_PCS_SEL_DOM1 (1 << 4) ++#define PECI_PCS_WRITE_PKG_CFG (1 << 7) ++ ++#define PECI_PCS_IDX_REG EC_PAGE_REG(5, 0x72) ++#define PECI_PCS_PARAM_LO_REG EC_PAGE_REG(5, 0x73) ++#define PECI_PCS_PARAM_HI_REG EC_PAGE_REG(5, 0x74) ++ ++#define PECI_PCS_COMPLETION_CODE_REG EC_PAGE_REG(5, 0x75) ++#define PECI_PCS_DATA_VALID 0x40 ++#define PECI_PCS_RESP_TIMEOUT_RETRY 0x80 ++#define PECI_PCS_RESP_TIMEOUT 0x81 ++#define PECI_PCS_INVALID_REQUEST 0x90 ++#define PECI_PCS_PECI_CONTROL_HW 0x91 ++ ++#define PECI_PCS_BUF_REG(x) EC_PAGE_REG(5, 0x76 + (x)) ++#define PECI_PCS_BUF_LEN 4 ++ ++#define PECI_MASTER_CFG_REG EC_PAGE_REG(5, 0x7a) ++#define PECI_MASTER_POLLRATE_MASK 0x07 ++#define PECI_MASTER_POLLRATE_ONCE (0 << 0) ++#define PECI_MASTER_POLLRATE_100MS (1 << 0) ++#define PECI_MASTER_POLLRATE_200MS (2 << 0) ++#define PECI_MASTER_POLLRATE_400MS (3 << 0) ++#define PECI_MASTER_POLLRATE_800MS (4 << 0) ++#define PECI_MASTER_POLLRATE_1S (5 << 0) ++#define PECI_MASTER_POLLRATE_2S (6 << 0) ++#define PECI_MASTER_POLLRATE_4S (7 << 0) ++#define PECI_MASTER_STOP_ERR (1 << 4) ++#define PECI_MASTER_HOLD_RDY (1 << 5) ++#define PECI_MASTER_START (1 << 6) ++#define PECI_MASTER_EN (1 << 7) ++ ++#define PECI_MASTER_CFG2_REG EC_PAGE_REG(5, 0x7b) ++#define PECI_MASTER_CPL_CODE_SUPP (1 << 6) ++#define PECI_MASTER_AWFCS_EN (1 << 7) ++ ++#define PECI_MASTER_CLIENT_ADDR_REG EC_PAGE_REG(5, 0x7c) ++#define PECI_MASTER_CMD_CODE_REG EC_PAGE_REG(5, 0x7d) ++#define PECI_MASTER_WRITE_LEN_REG EC_PAGE_REG(5, 0x7e) ++#define PECI_MASTER_READ_LEN_REG EC_PAGE_REG(5, 0x7f) ++ ++#define PECI_MASTER_WRITE_BUF(x) EC_PAGE_REG(5, 0x80 + (x)) ++#define PECI_MASTER_WRITE_BUF_LEN 12 ++#define PECI_MASTER_READ_BUF(x) EC_PAGE_REG(5, 0x90 + (x)) ++#define PECI_MASTER_READ_BUF_LEN 12 ++ ++#define PECI_DRAM_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa0 + (x)) ++#define PECI_DIMM_AMB_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa4 + (x)) ++#define PECI_DIMM_TEMP_RD_STS_REG(x) EC_PAGE_REG(5, 0xa8 + (x)) ++#define PECI_ACC_ENERGRY_RD_STS_REG(x) EC_PAGE_REG(5, 0xac + (x)) ++ ++#define PECI_DRAM_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb0) ++#define PECI_DRAM_POLLRATE_MASK 0x07 ++#define PECI_DRAM_POLLRATE_ONCE (0 << 0) ++#define PECI_DRAM_POLLRATE_100MS (1 << 0) ++#define PECI_DRAM_POLLRATE_200MS (2 << 0) ++#define PECI_DRAM_POLLRATE_400MS (3 << 0) ++#define PECI_DRAM_POLLRATE_800MS (4 << 0) ++#define PECI_DRAM_POLLRATE_1S (5 << 0) ++#define PECI_DRAM_POLLRATE_2S (6 << 0) ++#define PECI_DRAM_POLLRATE_4S (7 << 0) ++ ++#define PECI_DIMM_AMB_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb1) ++#define PECI_DIMM_AMB_POLLRATE_MASK 0x07 ++#define PECI_DIMM_AMB_POLLRATE_ONCE (0 << 0) ++#define PECI_DIMM_AMB_POLLRATE_100MS (1 << 0) ++#define PECI_DIMM_AMB_POLLRATE_200MS (2 << 0) ++#define PECI_DIMM_AMB_POLLRATE_400MS (3 << 0) ++#define PECI_DIMM_AMB_POLLRATE_800MS (4 << 0) ++#define PECI_DIMM_AMB_POLLRATE_1S (5 << 0) ++#define PECI_DIMM_AMB_POLLRATE_2S (6 << 0) ++#define PECI_DIMM_AMB_POLLRATE_4S (7 << 0) ++ ++#define PECI_ACC_ENERGRY_RD_POLL_RATE_REG EC_PAGE_REG(5, 0xb2) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_MASK 0x07 ++#define PECI_ACC_ENERGRY_RD_POLLRATE_ONCE (0 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_100MS (1 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_200MS (2 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_400MS (3 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_800MS (4 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_1S (5 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_2S (6 << 0) ++#define PECI_ACC_ENERGRY_RD_POLLRATE_4S (7 << 0) ++ ++#define PECI_DRAM_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xb8 + 2*(x)) ++#define PECI_DRAM_TEMP_WR_CH_IDX_MASK (7 << 0) ++#define PECI_DRAM_TEMP_WR_CH_IDX_SHIFT 0 ++#define PECI_DRAM_TEMP_WR_DIMM_IDX_MASK (7 << 3) ++#define PECI_DRAM_TEMP_WR_DIMM_IDX_SHIFT 3 ++#define PECI_DRAM_TEMP_WR_POLLING (1 << 6) ++#define PECI_DRAM_TEMP_WR_START (1 << 7) ++ ++#define PECI_DRAM_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xb9 + 2*(x)) ++#define PECI_DRAM_TEMP_WR_AGENT_IDX_MASK (3 << 1) ++#define PECI_DRAM_TEMP_WR_AGENT_IDX_SHIFT 1 ++#define PECI_DRAM_TEMP_WR_DOM0 (0 << 6) ++#define PECI_DRAM_TEMP_WR_DOM1 (1 << 6) ++#define PECI_DRAM_TEMP_WR_CH_SEL (1 << 7) ++ ++#define PECI_DIMM_AMB_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xc0 + 2*(x)) ++#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_MASK (7 << 0) ++#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_SHIFT 0 ++#define PECI_DIMM_AMB_TEMP_WR_POLLING (1 << 6) ++#define PECI_DIMM_AMB_TEMP_WR_START (1 << 7) ++ ++#define PECI_DIMM_AMB_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xc1 + 2*(x)) ++#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_MASK (3 << 1) ++#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_SHIFT 1 ++#define PECI_DIMM_AMB_TEMP_WR_DOM0 (0 << 6) ++#define PECI_DIMM_AMB_TEMP_WR_DOM1 (1 << 6) ++#define PECI_DIMM_AMB_TEMP_WR_CH_SEL (1 << 7) ++ ++#define PECI_DIMM_TEMP_RD_CFG1_REG(x) EC_PAGE_REG(5, 0xc8 + (x)) ++#define PECI_DIMM_TEMP_RD_AGENT_IDX_MASK (3 << 0) ++#define PECI_DIMM_TEMP_RD_AGENT_IDX_SHIFT 0 ++#define PECI_DIMM_TEMP_RD_DOM0 (0 << 2) ++#define PECI_DIMM_TEMP_RD_DOM1 (1 << 2) ++#define PECI_DIMM_TEMP_RD_DIMM_SEL_MASK (3 << 4) ++#define PECI_DIMM_TEMP_RD_DIMM0 (0 << 4) ++#define PECI_DIMM_TEMP_RD_DIMM1 (1 << 4) ++#define PECI_DIMM_TEMP_RD_DIMM0_MAX (2 << 4) ++#define PECI_DIMM_TEMP_RD_DIMM1_MAX (3 << 4) ++#define PECI_DIMM_TEMP_RD_DIMM_CH0 (0 << 6) ++#define PECI_DIMM_TEMP_RD_DIMM_CH1 (1 << 6) ++ ++#define PECI_ACC_ENERGRY_RD_CFG_REG(x) EC_PAGE_REG(5, 0xcc + (x)) ++#define PECI_ACC_ENERGRY_RD_AGENT_IDX_MASK (3 << 0) ++#define PECI_ACC_ENERGRY_RD_AGENT_IDX_SHIFT 0 ++#define PECI_ACC_ENERGRY_RD_DOM0 (0 << 2) ++#define PECI_ACC_ENERGRY_RD_DOM1 (1 << 2) ++#define PECI_ACC_ENERGRY_RD_REPORT_CURR (0 << 3) ++#define PECI_ACC_ENERGRY_RD_REPORT_INCR (1 << 3) ++#define PECI_DIMM_TEMP_RD_PWR_PLANE_SEL_MASK (3 << 4) ++#define PECI_DIMM_TEMP_RD_PWR_PLANE0 (0 << 4) ++#define PECI_DIMM_TEMP_RD_PWR_PLANE1 (1 << 4) ++#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE0 (2 << 4) ++#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE1 (3 << 4) ++#define PECI_ACC_ENERGRY_RD_POLLING (1 << 6) ++#define PECI_ACC_ENERGRY_RD_START (1 << 7) ++ ++#define PECI_ACC_ENERGRY_RD_VAL_B0_REG(x) EC_PAGE_REG(5, 0xd0 + 4*(x)) ++#define PECI_ACC_ENERGRY_RD_VAL_B1_REG(x) EC_PAGE_REG(5, 0xd1 + 4*(x)) ++#define PECI_ACC_ENERGRY_RD_VAL_B2_REG(x) EC_PAGE_REG(5, 0xd2 + 4*(x)) ++#define PECI_ACC_ENERGRY_RD_VAL_B3_REG(x) EC_PAGE_REG(5, 0xd3 + 4*(x)) ++ ++/* EC Page 6 - EC FW Information and Configuration */ ++ ++#define CHIP_ID0_REG EC_PAGE_REG(6, 0x00) ++#define CHIP_ID1_REG EC_PAGE_REG(6, 0x01) ++#define CUSTOMER_ID0_REG EC_PAGE_REG(6, 0x02) ++#define CUSTOMER_ID1_REG EC_PAGE_REG(6, 0x03) ++#define FW_BUILD_YEAR_REG EC_PAGE_REG(6, 0x04) ++#define FW_BUILD_MONTH_REG EC_PAGE_REG(6, 0x05) ++#define FW_BUILD_DAY_REG EC_PAGE_REG(6, 0x06) ++#define FW_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x07) ++#define FW_VER0_REG EC_PAGE_REG(6, 0x08) ++#define FW_VER1_REG EC_PAGE_REG(6, 0x09) ++#define PROFILE_VER_REG EC_PAGE_REG(6, 0x0a) ++#define ROM_VER0_REG EC_PAGE_REG(6, 0x0c) ++#define ROM_VER1_REG EC_PAGE_REG(6, 0x0d) ++#define ROM_VER2_REG EC_PAGE_REG(6, 0x0e) ++#define ROM_VER3_REG EC_PAGE_REG(6, 0x0f) ++#define ISP_BUILD_YEAR_REG EC_PAGE_REG(6, 0x12) ++#define ISP_BUILD_MONTH_REG EC_PAGE_REG(6, 0x13) ++#define ISP_BUILD_DAY_REG EC_PAGE_REG(6, 0x14) ++#define ISP_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x15) ++#define ISP_VER0_REG EC_PAGE_REG(6, 0x16) ++#define ISP_VER1_REG EC_PAGE_REG(6, 0x17) ++ ++#define OEM_VER_REG EC_PAGE_REG(6, 0x18) ++#define OEM_VER_LEN 8 ++ ++#define EC_ALIVE_COUNTER_REG EC_PAGE_REG(6, 0x20) ++ ++#define EC_HEARTBEAT_CFG_REG EC_PAGE_REG(6, 0x2e) ++#define EC_HEARBEAT_TOGGLE_RATE_MASK 0x0f ++#define EC_HEARBEAT_TYPE_OD (0 << 6) ++#define EC_HEARBEAT_TYPE_PP (1 << 6) ++#define EC_HEARBEAT_EN (1 << 7) ++ ++#define EC_HEARTBEAT_GPSEL_REG EC_PAGE_REG(6, 0x2f) ++#define EC_HEARBEAT_GPIO_PIN_MASK 0x0f ++#define EC_HEARBEAT_GPIO_PIN_SHIFT 0 ++#define EC_HEARBEAT_GPIO_GROUP_MASK 0xf0 ++#define EC_HEARBEAT_GPIO_GROUP_SHIFT 4 ++ ++#define EC_MCU_SPEED_REG EC_PAGE_REG(6, 0x38) ++#define EC_MCU_SPEED_MCLK_MASK 0x0f ++#define EC_MCU_SPEED_MCLK_10KHZ (0 << 0) ++#define EC_MCU_SPEED_MCLK_160KHZ (1 << 0) ++#define EC_MCU_SPEED_MCLK_1MHZ (2 << 0) ++#define EC_MCU_SPEED_MCLK_4MHZ (3 << 0) ++#define EC_MCU_SPEED_MCLK_8MHZ (4 << 0) ++#define EC_MCU_SPEED_MCLK_16MHZ (5 << 0) ++#define EC_MCU_SPEED_MCLK_24MHZ (6 << 0) ++#define EC_MCU_SPEED_MCLK_48MHZ (7 << 0) ++#define EC_MCU_CACHE_EN (1 << 6) ++ ++#define EC_FLASH_SPEED_REG EC_PAGE_REG(6, 0x39) ++#define EC_FLASH_CLK_DIV_MASK (3 << 4) ++#define EC_FLASH_CLK_DIV_1 (0 << 4) ++#define EC_FLASH_CLK_DIV_2 (1 << 4) ++#define EC_FLASH_CLK_DIV_4 (2 << 4) ++#define EC_FLASH_CLK_DIV_16 (3 << 4) ++#define EC_FLASH_FETCH_MODE_MASK (3 << 6) ++#define EC_FLASH_FETCH_MODE_READ (0 << 6) ++#define EC_FLASH_FETCH_MODE_FAST_READ (1 << 6) ++#define EC_FLASH_FETCH_MODE_DUAL_OUT (2 << 6) ++#define EC_FLASH_FETCH_MODE_DUAL_IN_OUT (3 << 6) ++ ++#define EC_FLASH_MANUFACTURE_REG EC_PAGE_REG(6, 0x3a) ++#define EC_FLASH_MEMORY_TYPE_REG EC_PAGE_REG(6, 0x3b) ++#define EC_FLASH_CAPACITY_REG EC_PAGE_REG(6, 0x3c) ++ ++#define EC_MCU_SPEED_CTL_VSB_REG EC_PAGE_REG(6, 0x40) ++#define EC_FLASH_CLK_VSB_DIV_MASK (3 << 0) ++#define EC_FLASH_CLK_VSB_DIV_1 (0 << 0) ++#define EC_FLASH_CLK_VSB_DIV_2 (1 << 0) ++#define EC_FLASH_CLK_VSB_DIV_4 (2 << 0) ++#define EC_FLASH_CLK_VSB_DIV_16 (3 << 0) ++#define EC_FLASH_FETCH_MODE_VSB_MASK (3 << 2) ++#define EC_FLASH_FETCH_MODE_VSB_READ (0 << 2) ++#define EC_FLASH_FETCH_MODE_VSB_FAST_READ (1 << 2) ++#define EC_FLASH_FETCH_MODE_VSB_DUAL_OUT (2 << 2) ++#define EC_FLASH_FETCH_MODE_VSB_DUAL_IN_OUT (3 << 2) ++#define EC_MCU_SPEED_MCLK_VSB_MASK (3 << 4) ++#define EC_MCU_SPEED_MCLK_VSB_1MHZ (0 << 4) ++#define EC_MCU_SPEED_MCLK_VSB_4MHZ (1 << 4) ++#define EC_MCU_SPEED_MCLK_VSB_24MHZ (2 << 4) ++#define EC_MCU_SPEED_MCLK_VSB_48MHZ (3 << 4) ++#define EC_MCU_CACHE_VSB_EN (1 << 6) ++ ++#define EC_MCU_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x42) ++#define EC_MCU_SPEED_MCLK_VCC_MASK 0x0f ++#define EC_MCU_SPEED_MCLK_VCC_10KHZ (0 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_160KHZ (1 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_1MHZ (2 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_4MHZ (3 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_8MHZ (4 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_16MHZ (5 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_24MHZ (6 << 0) ++#define EC_MCU_SPEED_MCLK_VCC_48MHZ (7 << 0) ++#define EC_MCU_CACHE_VCC_EN (1 << 6) ++#define EC_MCU_SPEED_VCC_LOAD_CFG (1 << 7) ++ ++#define EC_FLASH_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x43) ++#define EC_FLASH_CLK_VCC_DIV_MASK (3 << 2) ++#define EC_FLASH_CLK_VCC_DIV_1 (0 << 2) ++#define EC_FLASH_CLK_VCC_DIV_2 (1 << 2) ++#define EC_FLASH_CLK_VCC_DIV_4 (2 << 2) ++#define EC_FLASH_CLK_VCC_DIV_16 (3 << 2) ++#define EC_FLASH_FETCH_MODE_VCC_MASK (3 << 4) ++#define EC_FLASH_FETCH_MODE_VCC_READ (0 << 4) ++#define EC_FLASH_FETCH_MODE_VCC_FAST_READ (1 << 4) ++#define EC_FLASH_FETCH_MODE_VCC_DUAL_OUT (2 << 4) ++#define EC_FLASH_FETCH_MODE_VCC_DUAL_IN_OUT (3 << 4) ++#define EC_FLASH_SPEED_VCC_LOAD_CFG (1 << 7) ++ ++#define EC_FLASH_WREN_CMD_REG EC_PAGE_REG(6, 0x47) ++ ++#define EC_FLASH_WRITE_LOCK_REG EC_PAGE_REG(6, 0x4f) ++#define EC_FLASH_WRITE_LOCK (1 << 0) ++#define EC_FLASH_WRITE_LOCK_EN (1 << 7) ++ ++/* EC Page 8 - NCT6687D specific, not present in NCT6686D */ ++ ++#define FAN9_FAN10_MANUAL_EN_REG EC_PAGE_REG(8, 0x0f) ++ ++#define FAN_STEP_UP_TIME_REG(fan) EC_PAGE_REG(8, 0x1a + ((fan) - 1)) ++#define FAN_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(8, 0x24 + ((fan) - 1)) ++ ++/* These are also included in macros in page 1, 10 and 12 */ ++#define FAN9_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe0) ++#define FAN10_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe1) ++#define FAN9_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe8) ++#define FAN10_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe9) ++#define FAN9_DUTY_REG EC_PAGE_REG(8, 0xf0) ++#define FAN10_DUTY_REG EC_PAGE_REG(8, 0xf1) ++#define FAN9OUT_CFG_REG EC_PAGE_REG(8, 0xf4) ++#define FAN10OUT_CFG_REG EC_PAGE_REG(8, 0xf5) ++ ++/* EC Page 9 - Fan Algorithm Function Control */ ++ ++#define FAN_ALG_FUNCTRL_REG(fan) EC_PAGE_REG(9, 0x00 + ((fan) - 1)) ++#define FAN_ALG_FUNCTRL_DTS_UB_EN (1 << 2) ++#define FAN_ALG_FUNCTRL_DTS2_EN (1 << 3) ++#define FAN_ALG_FUNCTRL_DTS1_EN (1 << 4) ++#define FAN_ALG_FUNCTRL_TEMP_ERR (1 << 5) ++#define FAN_ALG_FUNCTRL_CRIT_TEMP_EN (1 << 6) ++#define FAN_ALG_FUNCTRL_ALG_EN (1 << 7) ++ ++/* Main temperature zone decision */ ++#define FAN_MTZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x10 + (x) + 4*((fan) - 1)) ++/* Ambient temperature zone decision */ ++#define FAN_ATZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x50 + (x) 4*((fan) - 1)) ++ ++#define FAN_INITIAL_VALUE_REG(fan) EC_PAGE_REG(9, 0x90 + ((fan) - 1)) ++#define FAN_CRIT_TEMP_CFG_REG(fan) EC_PAGE_REG(9, 0xA0 + ((fan) - 1)) ++#define FAN_CRIT_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(9, 0xB0 + ((fan) - 1)) ++#define FAN_TEMP_ERR_DUTY_VAL_REG(fan) EC_PAGE_REG(9, 0xC0 + ((fan) - 1)) ++ ++#define FAN_MODE_SEL_REG(fan) EC_PAGE_REG(9, 0xD0 + ((fan) - 1)) ++#define FAN_MODE_SEL_MASK 0xf ++#define FAN_MODE_MODE_MANUAL (0 << 0) ++#define FAN_MODE_THERMAL_CRUISE (1 << 0) ++#define FAN_MODE_SPEED_CRUISE (2 << 0) ++#define FAN_MODE_SMART_FAN_IV (3 << 0) ++#define FAN_MODE_PID_CONTROL (4 << 0) ++ ++/* EC Page 10 - Fan Function Control & Weight Matrix */ ++ ++#define FAN_MANUAL_EN_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(8, 0x0f) \ ++ : EC_PAGE_REG(10, 0x00)) ++#define FAN_MANUAL_EN(fan) (1 << (((fan) - 1) % 8)) ++ ++#define FAN_CFG_CTRL_REG EC_PAGE_REG(10, 0x01) ++#define FAN_CFG_DONE (1 << 6) ++#define FAN_CFG_REQUEST (1 << 7) ++ ++#define FAN_FUNCTION_CTRL(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(8, 0xe0 + ((fan) - 9)) \ ++ : EC_PAGE_REG(10, 0x08 + ((fan) - 1))) ++#define FAN_FUN_MINDUTY_EN (1 << 0) ++#define FAN_FUN_MANUAL_OFFSET_EN (1 << 1) ++#define FAN_FUN_STARTUP_EN (1 << 2) ++#define FAN_FUN_AMBIENT_FLOOR_EN (1 << 3) ++#define FAN_FUN_MARKUP_TRACK_EN (1 << 4) ++#define FAN_FUN_FAST_TRACK_EN (1 << 5) ++#define FAN_FUN_SMART_TRACK_EN (1 << 6) ++#define FAN_FUN_UNIT_PWM_DUTY (0 << 7) ++#define FAN_FUN_UNIT_RPM (1 << 7) ++ ++/* The unit for below Ambient Floor register is 100 RPM */ ++#define FAN_AMB_FLOOR_RPM_TO_REG(rpm) ((rpm) ? (rpm) / 100 : 1) ++#define FAN_AMB_FLOOR_MIN_OUT_START_REG(fan) EC_PAGE_REG(10, 0x10 + ((fan) - 1)) ++#define FAN_AMB_FLOOR_MIN_OUT_END_REG(fan) EC_PAGE_REG(10, 0x18 + ((fan) - 1)) ++#define FAN_AMB_FLOOR_MAX_OUT_REG(fan) EC_PAGE_REG(10, 0x20 + ((fan) - 1)) ++ ++#define FAN_MANUAL_VALUE_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(8, 0xe8 + ((fan) - 9)) \ ++ : EC_PAGE_REG(10, 0x28 + ((fan) - 1))) ++ ++#define FAN_MANUAL_OFFSET_REG(fan) EC_PAGE_REG(10, 0x30 + ((fan) - 1)) ++#define FAN_MIN_DUTY_REG(fan) EC_PAGE_REG(10, 0x38 + ((fan) - 1)) ++#define FAN_STARTUP_DUTY_REG(fan) EC_PAGE_REG(10, 0x40 + ((fan) - 1)) ++ ++/* Smart Tracking registers */ ++ ++#define FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x48) ++#define FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x49) ++#define FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x4a) ++#define FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x4b) ++ ++#define FAN_LOW_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4c) ++#define FAN_MID_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4d) ++#define FAN_HIGH_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4e) ++ ++#define FAN_TRACKING_STEP_REG EC_PAGE_REG(10, 0x4f) ++#define FAN_TRACK_STEP_DOWN_MASK 0x0f ++#define FAN_TRACK_STEP_DOWN_SHIFT 0 ++#define FAN_TRACK_STEP_UP_MASK 0x0f ++#define FAN_TRACK_STEP_UP_SHIFT 4 ++ ++#define FAN_FAST_TRACK_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x50) ++ ++/* Below definitions are dividers for fast tracking weight registers */ ++#define FAN_FAST_TRACK_WEIGHT_DIV_1 1 ++#define FAN_FAST_TRACK_WEIGHT_DIV_2 2 ++#define FAN_FAST_TRACK_WEIGHT_DIV_4 3 ++#define FAN_FAST_TRACK_WEIGHT_DIV_8 4 ++#define FAN_FAST_TRACK_WEIGHT_DIV_16 5 ++#define FAN_FAST_TRACK_WEIGHT_DIV_32 6 ++#define FAN_FAST_TRACK_WEIGHT_DIV_64 7 ++ ++/* Below definitions are shifts and masks for fast tracking weight registers */ ++#define FAN_FAST_TRACK_WEIGHT_DOWN_MASK 0x07 ++#define FAN_FAST_TRACK_WEIGHT_DOWN_SHIFT 0 ++#define FAN_FAST_TRACK_WEIGHT_UP_MASK 0x07 ++#define FAN_FAST_TRACK_WEIGHT_UP_SHIFT 4 ++ ++#define FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x51) ++#define FAN_MID_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x52) ++#define FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x53) ++ ++/* Below definitions are shifts and masks for fast tracking duty step registers */ ++#define FAN_FAST_TRACK_DUTY_STEP_MASK 0x0f ++#define FAN_FAST_TRACK_DUTY_STEP_SHIFT 0 ++ ++#define FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x54) ++#define FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x55) ++#define FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x56) ++ ++#define FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x57) ++#define FAN_MARKUP_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x58) ++#define FAN_MARKUP_TRACK_WEIGHT_MASK 0x07 ++#define FAN_MARKUP_TRACK_WEIGHT_SHIFT 0 ++ ++/* Intel Sensor Based (DTS) Fan Control registers */ ++ ++#define ITL_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x59) ++#define ITL_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x5a) ++#define ITL_AMB_TEMP_START_POINT_REG(x) EC_PAGE_REG(10, 0x5b + (x)) ++ ++#define ITL_RPM_START_POINT_HI_REG(x) EC_PAGE_REG(10, 0x60 + 2*(x)) ++#define ITL_RPM_START_POINT_LO_REG(x) EC_PAGE_REG(10, 0x61 + 2*(x)) ++#define ITL_RPM_END_POINT_HI_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) ++#define ITL_RPM_END_POINT_LO_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) ++#define ITL_RPM_MAX_SPEED_HI_REG EC_PAGE_REG(10, 0x74) ++#define ITL_RPM_MAX_SPEED_LO_REG EC_PAGE_REG(10, 0x75) ++ ++#define ITL_DTS_CFG_REG EC_PAGE_REG(10, 0x76) ++#define ITL_DTS_PECI_AGENT_IDX_SEL_MASK 0x0f ++#define ITL_DTS_PECI_AGENT_IDX_SEL_SHIFT 0 ++#define ITL_DTS_PECI_CFG_ADJUSTMENT (1 << 7) ++ ++#define AMBIENT_FLOOR_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x77) ++#define AMBIENT_FLOOR_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x78) ++ ++/* DTS 2.0 sensor registers */ ++ ++#define DTS2_TARGET_MARGIN_REG EC_PAGE_REG(10, 0x59) ++#define DTS2_TCONTROL_REG EC_PAGE_REG(10, 0x5a) ++#define DTS2_TCONTROL_OFFSET_REG EC_PAGE_REG(10, 0x5b) ++#define DTS2_TARGET_TOLERANCE_REG EC_PAGE_REG(10, 0x5c) ++#define DTS2_DIVISOR_REG EC_PAGE_REG(10, 0x5d) ++#define DTS2_STEP_SPEED_HI_REG EC_PAGE_REG(10, 0x5e) ++#define DTS2_STEP_SPEED_LO_REG EC_PAGE_REG(10, 0x5f) ++#define DTS2_MIN_SPEED_HI_REG EC_PAGE_REG(10, 0x60) ++#define DTS2_MIN_SPEED_LO_REG EC_PAGE_REG(10, 0x61) ++#define DTS2_DELAY_TIME_COUNTER_REG EC_PAGE_REG(10, 0x62) ++ ++/* Weight Matrix Configuration */ ++ ++#define FAN_ALG_ENGINE_WEIGHT_EN_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(10, 0xC1 + 8*((fan) - 9)) \ ++ : EC_PAGE_REG(10, 0x80 + 8*((fan) - 1))) ++#define FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) ++ ++#define FAN_ALG_ENGINE_WEIGHT_VAL_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(10, 0xC3 + ((fan) - 9)/2 + 8*((fan) - 9)) \ ++ : EC_PAGE_REG(10, 0x84 + ((fan) - 1)/2 + 8*((fan) - 1))) ++#define FAN_ALG_ENGINE_WEIGHT_MASK(fan) (0xf << (4 * (((fan) - 1) % 2))) ++#define FAN_ALG_ENGINE_WEIGHT_SHIFT(fan) (4 * (((fan) - 1) % 2)) ++ ++/* EC Page 11 - Thermal Cruise, Speed Cruise, Smart Fan IV */ ++ ++#define FAN_PWM_PERCENT_TO_HEX(x) ((x) * 255 / 100) ++ ++ ++/* For x larger than 10, the registers are placed in page 12 */ ++/* Thermal Cruise (TC) Registers */ ++ ++#define FAN_TC_TARGET_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) ++#define FAN_TC_TEMP_TOLERANCE_MASK 0xf ++#define FAN_TC_TEMP_TOLERANCE_SHIFT 0 ++ ++#define FAN_TC_TARGET_TEMP_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) ++#define FAN_TC_TARGET_TEMP_MASK 0x7f ++#define FAN_TC_TARGET_TEMP_SHIFT 0 ++#define FAN_TC_KEEP_MIN_OUTPUT (1 << 7) ++ ++#define FAN_TC_STOP_VALUE_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) ++ ++#define FAN_TC_TIME_TO_SECONDS(x) ((x)*10) ++#define FAN_TC_STOP_TIME_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) ++#define FAN_TC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) ++#define FAN_TC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) ++ ++/* Speed Cruise (SC) Registers */ ++ ++#define FAN_SC_TARGET_RPM_HI_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) ++#define FAN_SC_TARGET_RPM_LO_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) ++#define FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) ++#define FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) ++ ++#define FAN_SC_TIME_TO_SECONDS(x) ((x)*10) ++#define FAN_SC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) ++#define FAN_SC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) ++ ++/* Smart Fan IV (SF4) Registers */ ++ ++#define FAN_SF4_TEMP_LVL_REG(fan, level) EC_PAGE_REG(11, 0x00 + (level) + 24*((fan) - 1)) ++#define FAN_SF4_PWM_RPM_LVL_HI_REG(fan, level) EC_PAGE_REG(11, 0x07 + (level)*2 + 24*((fan) - 1)) ++#define FAN_SF4_PWM_RPM_LVL_LO_REG(fan, level) EC_PAGE_REG(11, 0x08 + (level)*2 + 24*((fan) - 1)) ++#define FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(fan) EC_PAGE_REG(11, 0x15 + 24*((fan) - 1)) ++#define FAN_SF4_TEMP_CUT_OFF_REG(fan) EC_PAGE_REG(11, 0x16 + 24*((fan) - 1)) ++#define FAN_SF4_TEMP_OFF_DELAY_REG(fan) EC_PAGE_REG(11, 0x17 + 24*((fan) - 1)) ++ ++/* EC Page 12 - Fan Function Control */ ++ ++#define FAN_ENGINE_STS_REG EC_PAGE_REG(12, 0xf8) ++#define FAN_PECI_CFG_ADJUSTED (1 << 1) ++#define FAN_UNFINISHED_FLAG (1 << 2) ++#define FAN_CFG_PHASE (1 << 3) ++#define FAN_CFG_INVALID (1 << 4) ++#define FAN_CFG_CHECK_DONE (1 << 5) ++#define FAN_CFG_LOCK (1 << 6) ++#define FAN_DRIVE_BY_MOD_SEL (0 << 7) ++#define FAN_DRIVE_BY_DEFAULT_VAL (1 << 7) ++ ++#define FAN_LAST_ERROR_CODE_REG EC_PAGE_REG(12, 0xf9) ++#define FAN_NO_ERROR 0x00 ++#define FAN_ERR_MODE_SELECT 0x01 ++#define FAN_ERR_CRIT_TEMP_PROTECT 0x02 ++#define FAN_ERR_ITL_FAN_CONTROL 0x04 ++#define FAN_ERR_SMART_TRACKING 0x05 ++#define FAN_ERR_THERMAL_CRUISE 0x10 ++#define FAN_ERR_SPEED_CRUISE 0x20 ++#define FAN_ERR_SMART_FAN_IV 0x40 ++#define FAN_ERR_PID_CONTROL 0x50 ++ ++#define FAN_CHANNEL_EN_REG(fan) \ ++ (((fan) > 8) ? EC_PAGE_REG(12, 0xfb) \ ++ : EC_PAGE_REG(12, 0xfc)) ++#define FAN_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) ++ ++#define FAN_DEFAULT_VAL_REG EC_PAGE_REG(12, 0xfd) ++ ++extern uint16_t nct6687d_hwm_base; ++ ++static __always_inline void hwm_reg_and_or(uint16_t page_reg, uint8_t and_mask, uint8_t or_mask) ++{ ++ assert(nct6687d_hwm_base != 0); ++ nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, ++ and_mask, or_mask); ++} ++ ++static __always_inline void hwm_reg_set_bits(uint16_t page_reg, uint8_t bits) ++{ ++ assert(nct6687d_hwm_base != 0); ++ nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, ++ ~bits, bits); ++} ++ ++static __always_inline void hwm_reg_write(uint16_t page_reg, uint8_t value) ++{ ++ assert(nct6687d_hwm_base != 0); ++ nct6687d_ec_write_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, value); ++} ++ ++static __always_inline uint8_t hwm_reg_read(uint16_t page_reg) ++{ ++ assert(nct6687d_hwm_base != 0); ++ return nct6687d_ec_read_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff); ++} ++ ++#endif /* SUPERIO_NUVOTON_NCT6687D_HWM_H */ +diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c +index c28092736f..7c3c496635 100644 +--- a/src/superio/nuvoton/nct6687d/superio.c ++++ b/src/superio/nuvoton/nct6687d/superio.c +@@ -7,6 +7,7 @@ + #include + #include + ++#include "chip.h" + #include "nct6687d.h" + + #define MAINBOARD_POWER_OFF 0 +@@ -23,6 +24,9 @@ + + static void nct6687d_init(struct device *dev) + { ++ const struct superio_nuvoton_nct6687d_config *conf; ++ const struct resource *res; ++ + if (!dev->enabled) + return; + +@@ -50,6 +54,12 @@ static void nct6687d_init(struct device *dev) + printk(BIOS_INFO, "set power %s after power fail\n", + power_status ? "on" : "off"); + break; ++ case NCT6687D_EC: ++ conf = dev->chip_info; ++ res = probe_resource(dev, PNP_IDX_IO0); ++ if (!conf || !res) ++ break; ++ nct6687d_hwm_init(res->base, conf); + } + } + +-- +2.49.0 + diff --git a/patches/coreboot-25.03/0002-mb-msi-ms7d25-ms7e06-bootblock.c-Change-the-early-SI.patch b/patches/coreboot-25.03/0002-mb-msi-ms7d25-ms7e06-bootblock.c-Change-the-early-SI.patch new file mode 100644 index 000000000..5005c424e --- /dev/null +++ b/patches/coreboot-25.03/0002-mb-msi-ms7d25-ms7e06-bootblock.c-Change-the-early-SI.patch @@ -0,0 +1,224 @@ +From 1caefdabaeabc7226c6c373bf82c61079106a7b0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Sun, 10 Sep 2023 14:30:34 +0200 +Subject: [PATCH 2/4] mb/msi/{ms7d25,ms7e06}/bootblock.c: Change the early SIO + init to reflect vendor BIOS init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Michał Żygowski +Change-Id: I7cc82fc355de7982b937e9dc58b921bdf05d5b74 +--- + src/mainboard/msi/ms7d25/bootblock.c | 77 +++++++++++++++++++-------- + src/mainboard/msi/ms7e06/bootblock.c | 78 ++++++++++++++++++++-------- + 2 files changed, 111 insertions(+), 44 deletions(-) + +diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c +index 110d6828a6..1b192eb8d1 100644 +--- a/src/mainboard/msi/ms7d25/bootblock.c ++++ b/src/mainboard/msi/ms7d25/bootblock.c +@@ -4,42 +4,75 @@ + #include + #include + #include ++#include + ++#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) + #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) + #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) ++#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) ++#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) ++ ++#define EC_IO_BASE 0xa20 + + void bootblock_mainboard_early_init(void) + { + /* Replicate vendor settings for multi-function pins in global config LDN */ +- nuvoton_pnp_enter_conf_state(SERIAL_DEV); +- pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low +- pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low ++ nuvoton_pnp_enter_conf_state(GPIO_DEV); ++ pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low ++ pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ +- pnp_write_config(SERIAL_DEV, 0x15, 0xaa); +- pnp_write_config(SERIAL_DEV, 0x1a, 0x02); +- pnp_write_config(SERIAL_DEV, 0x1b, 0x02); +- pnp_write_config(SERIAL_DEV, 0x1d, 0x00); +- pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); +- pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); +- pnp_write_config(SERIAL_DEV, 0x22, 0xbd); +- pnp_write_config(SERIAL_DEV, 0x23, 0xdf); +- pnp_write_config(SERIAL_DEV, 0x24, 0x39); +- pnp_write_config(SERIAL_DEV, 0x25, 0xfe); +- pnp_write_config(SERIAL_DEV, 0x26, 0x40); +- pnp_write_config(SERIAL_DEV, 0x27, 0x77); +- pnp_write_config(SERIAL_DEV, 0x28, 0x00); +- pnp_write_config(SERIAL_DEV, 0x29, 0xfb); +- pnp_write_config(SERIAL_DEV, 0x2a, 0x80); +- pnp_write_config(SERIAL_DEV, 0x2b, 0x20); +- pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); +- pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x15, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x1a, 0x02); ++ pnp_write_config(GPIO_DEV, 0x1b, 0x02); ++ pnp_write_config(GPIO_DEV, 0x1d, 0x00); ++ pnp_write_config(GPIO_DEV, 0x1e, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x1f, 0xb2); ++ pnp_write_config(GPIO_DEV, 0x22, 0xbd); ++ pnp_write_config(GPIO_DEV, 0x23, 0xdf); ++ pnp_write_config(GPIO_DEV, 0x24, 0x39); ++ pnp_write_config(GPIO_DEV, 0x25, 0xfe); ++ pnp_write_config(GPIO_DEV, 0x26, 0x40); ++ pnp_write_config(GPIO_DEV, 0x27, 0x77); ++ pnp_write_config(GPIO_DEV, 0x28, 0x00); ++ pnp_write_config(GPIO_DEV, 0x29, 0xfb); ++ pnp_write_config(GPIO_DEV, 0x2a, 0x80); ++ pnp_write_config(GPIO_DEV, 0x2b, 0x20); ++ pnp_write_config(GPIO_DEV, 0x2c, 0x8a); ++ pnp_write_config(GPIO_DEV, 0x2d, 0xaa); ++ ++ /* Set GPIO 06 as high output */ ++ pnp_write_config(GPIO_DEV, 0xF0, 0x00); ++ pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); ++ pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + +- nuvoton_pnp_exit_conf_state(POWER_DEV); ++ /* Configure power fault detection */ ++ pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); ++ pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); ++ ++ /* Configure yellow and green LED */ ++ pnp_write_config(POWER_DEV, 0xe7, 0x88); ++ pnp_write_config(POWER_DEV, 0xe8, 0x07); ++ pnp_set_logical_device(P80_UART_DEV); ++ pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); ++ ++ /* Configure EC */ ++ pnp_set_logical_device(EC_DEV); ++ pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); ++ pnp_set_enable(EC_DEV, 1); ++ ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); ++ nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); ++ nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); ++ ++ nuvoton_pnp_exit_conf_state(EC_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c +index 110d6828a6..55c2a88dec 100644 +--- a/src/mainboard/msi/ms7e06/bootblock.c ++++ b/src/mainboard/msi/ms7e06/bootblock.c +@@ -4,42 +4,76 @@ + #include + #include + #include ++#include + ++#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) + #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) + #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) ++#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) ++#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) ++ ++#define EC_IO_BASE 0xa20 + + void bootblock_mainboard_early_init(void) + { + /* Replicate vendor settings for multi-function pins in global config LDN */ +- nuvoton_pnp_enter_conf_state(SERIAL_DEV); +- pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low +- pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low ++ nuvoton_pnp_enter_conf_state(GPIO_DEV); ++ pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low ++ pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ +- pnp_write_config(SERIAL_DEV, 0x15, 0xaa); +- pnp_write_config(SERIAL_DEV, 0x1a, 0x02); +- pnp_write_config(SERIAL_DEV, 0x1b, 0x02); +- pnp_write_config(SERIAL_DEV, 0x1d, 0x00); +- pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); +- pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); +- pnp_write_config(SERIAL_DEV, 0x22, 0xbd); +- pnp_write_config(SERIAL_DEV, 0x23, 0xdf); +- pnp_write_config(SERIAL_DEV, 0x24, 0x39); +- pnp_write_config(SERIAL_DEV, 0x25, 0xfe); +- pnp_write_config(SERIAL_DEV, 0x26, 0x40); +- pnp_write_config(SERIAL_DEV, 0x27, 0x77); +- pnp_write_config(SERIAL_DEV, 0x28, 0x00); +- pnp_write_config(SERIAL_DEV, 0x29, 0xfb); +- pnp_write_config(SERIAL_DEV, 0x2a, 0x80); +- pnp_write_config(SERIAL_DEV, 0x2b, 0x20); +- pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); +- pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x15, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x1a, 0x02); ++ pnp_write_config(GPIO_DEV, 0x1b, 0x02); ++ pnp_write_config(GPIO_DEV, 0x1d, 0x00); ++ pnp_write_config(GPIO_DEV, 0x1e, 0xaa); ++ pnp_write_config(GPIO_DEV, 0x1f, 0xb2); ++ pnp_write_config(GPIO_DEV, 0x22, 0xbd); ++ pnp_write_config(GPIO_DEV, 0x23, 0xdf); ++ pnp_write_config(GPIO_DEV, 0x24, 0x39); ++ pnp_write_config(GPIO_DEV, 0x25, 0xfe); ++ pnp_write_config(GPIO_DEV, 0x26, 0x40); ++ pnp_write_config(GPIO_DEV, 0x27, 0x77); ++ pnp_write_config(GPIO_DEV, 0x28, 0x00); ++ pnp_write_config(GPIO_DEV, 0x29, 0xfb); ++ pnp_write_config(GPIO_DEV, 0x2a, 0x80); ++ pnp_write_config(GPIO_DEV, 0x2b, 0x20); ++ pnp_write_config(GPIO_DEV, 0x2c, 0x8a); ++ pnp_write_config(GPIO_DEV, 0x2d, 0xaa); ++ ++ /* Set GPIO 06 as high output */ ++ pnp_write_config(GPIO_DEV, 0xF0, 0x00); ++ pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); ++ pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + +- nuvoton_pnp_exit_conf_state(POWER_DEV); ++ /* Configure power fault detection */ ++ pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); ++ pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); ++ ++ /* Configure yellow and green LED */ ++ pnp_write_config(POWER_DEV, 0xe7, 0x88); ++ pnp_write_config(POWER_DEV, 0xe8, 0x07); ++ pnp_set_logical_device(P80_UART_DEV); ++ pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); ++ ++ /* Configure EC */ ++ pnp_set_logical_device(EC_DEV); ++ pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); ++ pnp_set_enable(EC_DEV, 1); ++ ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); ++ nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); ++ nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); ++ nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); ++ ++ ++ nuvoton_pnp_exit_conf_state(EC_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +-- +2.49.0 + diff --git a/patches/coreboot-25.03/0003-src-mainboard-msi-ms7e06-devicetree.cb-Add-fan-contr.patch b/patches/coreboot-25.03/0003-src-mainboard-msi-ms7e06-devicetree.cb-Add-fan-contr.patch new file mode 100644 index 000000000..71aaea747 --- /dev/null +++ b/patches/coreboot-25.03/0003-src-mainboard-msi-ms7e06-devicetree.cb-Add-fan-contr.patch @@ -0,0 +1,186 @@ +From 4ca5b0f3a4a9cc467fb423c043a3c4927b3880a1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 22 Sep 2023 16:30:05 +0200 +Subject: [PATCH 3/4] src/mainboard/msi/ms7e06/devicetree.cb: Add fan control + config +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Michał Żygowski +Change-Id: I7a207a8555466f3c4ce888ad7ed90367ff2ae12e +--- + src/mainboard/msi/ms7e06/devicetree.cb | 157 +++++++++++++++++++++++++ + 1 file changed, 157 insertions(+) + +diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb +index eb179885c1..5885f2ab27 100644 +--- a/src/mainboard/msi/ms7e06/devicetree.cb ++++ b/src/mainboard/msi/ms7e06/devicetree.cb +@@ -203,6 +203,163 @@ chip soc/intel/alderlake + register "gen4_dec" = "0x000c0081" + + chip superio/nuvoton/nct6687d ++ register "sensors[0]" = "PECI_AGENT0_DOMAIN0" ++ register "sensors[1]" = "TD0P_CURRENT_MODE" ++ register "sensors[2]" = "THERMISTOR15" ++ register "sensors[3]" = "PCH_CHIP" ++ register "sensors[4]" = "THERMISTOR16" ++ register "sensors[5]" = "THERMISTOR0" ++ register "sensors[6]" = "THERMISTOR1" ++ register "sensors[16]" = "VIN0" ++ register "sensors[17]" = "VIN1" ++ register "sensors[18]" = "VIN2" ++ register "sensors[19]" = "VIN3" ++ register "sensors[20]" = "VIN4" ++ register "sensors[21]" = "VIN5" ++ register "sensors[22]" = "VIN6" ++ register "sensors[23]" = "VIN7" ++ register "sensors[24]" = "VCC" ++ ++ register "smbus_sensor.sensor_idx" = "3" ++ register "smbus_sensor.sensor_en" = "true" ++ register "smbus_sensor.sensor_cmd" = "0x40" ++ register "smbus_sensor.sensor_addr" = "0x96" ++ register "smbus_sensor.baud_rate" = "BAUD_100K" ++ register "smbus_sensor.report_one_byte" = "true" ++ register "smbus_sensor.port_sel" = "1" ++ ++ register "peci_speed" = "PECI_1200KHZ" ++ ++ register "fan_default_val" = "60" ++ ++ register "smart_tracking.speed_boundary_low" = "1500" ++ register "smart_tracking.speed_boundary_high" = "2500" ++ register "smart_tracking.rpm_tolerance_low" = "100" ++ register "smart_tracking.rpm_tolerance_mid" = "100" ++ register "smart_tracking.rpm_tolerance_high" = "100" ++ register "smart_tracking.step_up" = "1" ++ register "smart_tracking.step_down" = "1" ++ ++ # CPU_FAN ++ register "FAN1.mode" = "FAN_SMART_FAN_IV" ++ register "FAN1.unit_sel" = "FAN_PWM" ++ register "FAN1.fanin_sel" = "TACH_PWM1" ++ register "FAN1.fanout_sel" = "TACH_PWM0" ++ register "FAN1.fan_alg_weight" = "10" ++ register "FAN1.smart_tracking_en" = "true" ++ register "FAN1.crit_temp" = "101" ++ register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" ++ register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" ++ register "FAN1.smart_fan.cut_off_delay" = "5" ++ register "FAN1.smart_fan.step_up_time" = "1" ++ register "FAN1.smart_fan.step_down_time" = "1" ++ ++ # PUMP_FAN ++ register "FAN2.mode" = "FAN_SMART_FAN_IV" ++ register "FAN2.unit_sel" = "FAN_PWM" ++ register "FAN2.fanin_sel" = "TACH_PWM3" ++ register "FAN2.fanout_sel" = "TACH_PWM2" ++ register "FAN2.fan_alg_weight" = "10" ++ register "FAN2.smart_tracking_en" = "true" ++ register "FAN2.crit_temp" = "101" ++ register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" ++ register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" ++ register "FAN2.smart_fan.cut_off_delay" = "5" ++ register "FAN2.smart_fan.step_up_time" = "1" ++ register "FAN2.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN1 ++ register "FAN3.mode" = "FAN_SMART_FAN_IV" ++ register "FAN3.unit_sel" = "FAN_PWM" ++ register "FAN3.fanin_sel" = "TACH_PWM11" ++ register "FAN3.fanout_sel" = "TACH_PWM10" ++ register "FAN3.fan_alg_weight" = "10" ++ register "FAN3.smart_tracking_en" = "true" ++ register "FAN3.crit_temp" = "101" ++ register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN3.smart_fan.cut_off_delay" = "5" ++ register "FAN3.smart_fan.step_up_time" = "1" ++ register "FAN3.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN2 ++ register "FAN4.mode" = "FAN_SMART_FAN_IV" ++ register "FAN4.unit_sel" = "FAN_PWM" ++ register "FAN4.fanin_sel" = "TACH_PWM13" ++ register "FAN4.fanout_sel" = "TACH_PWM12" ++ register "FAN4.fan_alg_weight" = "10" ++ register "FAN4.smart_tracking_en" = "true" ++ register "FAN4.crit_temp" = "101" ++ register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN4.smart_fan.cut_off_delay" = "5" ++ register "FAN4.smart_fan.step_up_time" = "1" ++ register "FAN4.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN3 ++ register "FAN5.mode" = "FAN_SMART_FAN_IV" ++ register "FAN5.unit_sel" = "FAN_PWM" ++ register "FAN5.fanin_sel" = "TACH_PWM15" ++ register "FAN5.fanout_sel" = "TACH_PWM14" ++ register "FAN5.fan_alg_weight" = "10" ++ register "FAN5.smart_tracking_en" = "true" ++ register "FAN5.crit_temp" = "101" ++ register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN5.smart_fan.cut_off_delay" = "5" ++ register "FAN5.smart_fan.step_up_time" = "1" ++ register "FAN5.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN4 ++ register "FAN6.mode" = "FAN_SMART_FAN_IV" ++ register "FAN6.unit_sel" = "FAN_PWM" ++ register "FAN6.fanin_sel" = "TACH_PWM17" ++ register "FAN6.fanout_sel" = "TACH_PWM16" ++ register "FAN6.fan_alg_weight" = "10" ++ register "FAN6.smart_tracking_en" = "true" ++ register "FAN6.crit_temp" = "101" ++ register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN6.smart_fan.cut_off_delay" = "5" ++ register "FAN6.smart_fan.step_up_time" = "1" ++ register "FAN6.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN5 ++ register "FAN7.mode" = "FAN_SMART_FAN_IV" ++ register "FAN7.unit_sel" = "FAN_PWM" ++ register "FAN7.fanin_sel" = "TACH_PWM19" ++ register "FAN7.fanout_sel" = "TACH_PWM18" ++ register "FAN7.fan_alg_weight" = "10" ++ register "FAN7.smart_tracking_en" = "true" ++ register "FAN7.crit_temp" = "101" ++ register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN7.smart_fan.cut_off_delay" = "5" ++ register "FAN7.smart_fan.step_up_time" = "1" ++ register "FAN7.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN6 ++ register "FAN8.mode" = "FAN_SMART_FAN_IV" ++ register "FAN8.unit_sel" = "FAN_PWM" ++ register "FAN8.fanin_sel" = "TACH_PWM6" ++ register "FAN8.fanout_sel" = "TACH_PWM4" ++ register "FAN8.fan_alg_weight" = "10" ++ register "FAN8.smart_tracking_en" = "true" ++ register "FAN8.crit_temp" = "101" ++ register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN8.smart_fan.cut_off_delay" = "5" ++ register "FAN8.smart_fan.step_up_time" = "1" ++ register "FAN8.smart_fan.step_down_time" = "1" ++ + device pnp 4e.1 off end # Parallel port + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 +-- +2.49.0 + diff --git a/patches/coreboot-25.03/0004-src-mainboard-msi-ms7d25-devicetree.cb-Add-fan-contr.patch b/patches/coreboot-25.03/0004-src-mainboard-msi-ms7d25-devicetree.cb-Add-fan-contr.patch new file mode 100644 index 000000000..47b4f94e6 --- /dev/null +++ b/patches/coreboot-25.03/0004-src-mainboard-msi-ms7d25-devicetree.cb-Add-fan-contr.patch @@ -0,0 +1,186 @@ +From bbd9a2e318dd043f3d0dfc9c50e9f35b24a7d4ae Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 22 Sep 2023 16:31:18 +0200 +Subject: [PATCH 4/4] src/mainboard/msi/ms7d25/devicetree.cb: Add fan control + config +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Michał Żygowski +Change-Id: Ieb282c33ed9f970e02bd915ddc92e8d66b553ba6 +--- + src/mainboard/msi/ms7d25/devicetree.cb | 157 +++++++++++++++++++++++++ + 1 file changed, 157 insertions(+) + +diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb +index 73d871d346..7604776d44 100644 +--- a/src/mainboard/msi/ms7d25/devicetree.cb ++++ b/src/mainboard/msi/ms7d25/devicetree.cb +@@ -213,6 +213,163 @@ chip soc/intel/alderlake + end + device ref pch_espi on + chip superio/nuvoton/nct6687d ++ register "sensors[0]" = "PECI_AGENT0_DOMAIN0" ++ register "sensors[1]" = "TD0P_CURRENT_MODE" ++ register "sensors[2]" = "THERMISTOR15" ++ register "sensors[3]" = "PCH_CHIP" ++ register "sensors[4]" = "THERMISTOR16" ++ register "sensors[5]" = "THERMISTOR0" ++ register "sensors[6]" = "THERMISTOR1" ++ register "sensors[16]" = "VIN0" ++ register "sensors[17]" = "VIN1" ++ register "sensors[18]" = "VIN2" ++ register "sensors[19]" = "VIN3" ++ register "sensors[20]" = "VIN4" ++ register "sensors[21]" = "VIN5" ++ register "sensors[22]" = "VIN6" ++ register "sensors[23]" = "VIN7" ++ register "sensors[24]" = "VCC" ++ ++ register "smbus_sensor.sensor_idx" = "3" ++ register "smbus_sensor.sensor_en" = "true" ++ register "smbus_sensor.sensor_cmd" = "0x40" ++ register "smbus_sensor.sensor_addr" = "0x96" ++ register "smbus_sensor.baud_rate" = "BAUD_100K" ++ register "smbus_sensor.report_one_byte" = "true" ++ register "smbus_sensor.port_sel" = "1" ++ ++ register "peci_speed" = "PECI_1200KHZ" ++ ++ register "fan_default_val" = "60" ++ ++ register "smart_tracking.speed_boundary_low" = "1500" ++ register "smart_tracking.speed_boundary_high" = "2500" ++ register "smart_tracking.rpm_tolerance_low" = "100" ++ register "smart_tracking.rpm_tolerance_mid" = "100" ++ register "smart_tracking.rpm_tolerance_high" = "100" ++ register "smart_tracking.step_up" = "1" ++ register "smart_tracking.step_down" = "1" ++ ++ # CPU_FAN ++ register "FAN1.mode" = "FAN_SMART_FAN_IV" ++ register "FAN1.unit_sel" = "FAN_PWM" ++ register "FAN1.fanin_sel" = "TACH_PWM1" ++ register "FAN1.fanout_sel" = "TACH_PWM0" ++ register "FAN1.fan_alg_weight" = "10" ++ register "FAN1.smart_tracking_en" = "true" ++ register "FAN1.crit_temp" = "101" ++ register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" ++ register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" ++ register "FAN1.smart_fan.cut_off_delay" = "5" ++ register "FAN1.smart_fan.step_up_time" = "1" ++ register "FAN1.smart_fan.step_down_time" = "1" ++ ++ # PUMP_FAN ++ register "FAN2.mode" = "FAN_SMART_FAN_IV" ++ register "FAN2.unit_sel" = "FAN_PWM" ++ register "FAN2.fanin_sel" = "TACH_PWM3" ++ register "FAN2.fanout_sel" = "TACH_PWM2" ++ register "FAN2.fan_alg_weight" = "10" ++ register "FAN2.smart_tracking_en" = "true" ++ register "FAN2.crit_temp" = "101" ++ register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" ++ register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" ++ register "FAN2.smart_fan.cut_off_delay" = "5" ++ register "FAN2.smart_fan.step_up_time" = "1" ++ register "FAN2.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN1 ++ register "FAN3.mode" = "FAN_SMART_FAN_IV" ++ register "FAN3.unit_sel" = "FAN_PWM" ++ register "FAN3.fanin_sel" = "TACH_PWM11" ++ register "FAN3.fanout_sel" = "TACH_PWM10" ++ register "FAN3.fan_alg_weight" = "10" ++ register "FAN3.smart_tracking_en" = "true" ++ register "FAN3.crit_temp" = "101" ++ register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN3.smart_fan.cut_off_delay" = "5" ++ register "FAN3.smart_fan.step_up_time" = "1" ++ register "FAN3.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN2 ++ register "FAN4.mode" = "FAN_SMART_FAN_IV" ++ register "FAN4.unit_sel" = "FAN_PWM" ++ register "FAN4.fanin_sel" = "TACH_PWM13" ++ register "FAN4.fanout_sel" = "TACH_PWM12" ++ register "FAN4.fan_alg_weight" = "10" ++ register "FAN4.smart_tracking_en" = "true" ++ register "FAN4.crit_temp" = "101" ++ register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN4.smart_fan.cut_off_delay" = "5" ++ register "FAN4.smart_fan.step_up_time" = "1" ++ register "FAN4.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN3 ++ register "FAN5.mode" = "FAN_SMART_FAN_IV" ++ register "FAN5.unit_sel" = "FAN_PWM" ++ register "FAN5.fanin_sel" = "TACH_PWM15" ++ register "FAN5.fanout_sel" = "TACH_PWM14" ++ register "FAN5.fan_alg_weight" = "10" ++ register "FAN5.smart_tracking_en" = "true" ++ register "FAN5.crit_temp" = "101" ++ register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN5.smart_fan.cut_off_delay" = "5" ++ register "FAN5.smart_fan.step_up_time" = "1" ++ register "FAN5.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN4 ++ register "FAN6.mode" = "FAN_SMART_FAN_IV" ++ register "FAN6.unit_sel" = "FAN_PWM" ++ register "FAN6.fanin_sel" = "TACH_PWM17" ++ register "FAN6.fanout_sel" = "TACH_PWM16" ++ register "FAN6.fan_alg_weight" = "10" ++ register "FAN6.smart_tracking_en" = "true" ++ register "FAN6.crit_temp" = "101" ++ register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN6.smart_fan.cut_off_delay" = "5" ++ register "FAN6.smart_fan.step_up_time" = "1" ++ register "FAN6.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN5 ++ register "FAN7.mode" = "FAN_SMART_FAN_IV" ++ register "FAN7.unit_sel" = "FAN_PWM" ++ register "FAN7.fanin_sel" = "TACH_PWM19" ++ register "FAN7.fanout_sel" = "TACH_PWM18" ++ register "FAN7.fan_alg_weight" = "10" ++ register "FAN7.smart_tracking_en" = "true" ++ register "FAN7.crit_temp" = "101" ++ register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN7.smart_fan.cut_off_delay" = "5" ++ register "FAN7.smart_fan.step_up_time" = "1" ++ register "FAN7.smart_fan.step_down_time" = "1" ++ ++ # SYS_FAN6 ++ register "FAN8.mode" = "FAN_SMART_FAN_IV" ++ register "FAN8.unit_sel" = "FAN_PWM" ++ register "FAN8.fanin_sel" = "TACH_PWM6" ++ register "FAN8.fanout_sel" = "TACH_PWM4" ++ register "FAN8.fan_alg_weight" = "10" ++ register "FAN8.smart_tracking_en" = "true" ++ register "FAN8.crit_temp" = "101" ++ register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" ++ register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" ++ register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" ++ register "FAN8.smart_fan.cut_off_delay" = "5" ++ register "FAN8.smart_fan.step_up_time" = "1" ++ register "FAN8.smart_fan.step_down_time" = "1" ++ + device pnp 4e.1 off end # Parallel port + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 +-- +2.49.0 + diff --git a/targets/msi_z790p_ddr5_blobs.mk b/targets/msi_z790p_ddr5_blobs.mk new file mode 100644 index 000000000..2939b0821 --- /dev/null +++ b/targets/msi_z790p_ddr5_blobs.mk @@ -0,0 +1,7 @@ +# Make the Coreboot build depend on the following 3rd party blobs: +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ + $(pwd)/blobs/msi_z790p_ddr5/ifd.bin $(pwd)/blobs/msi_z790p_ddr5/me.bin + +$(pwd)/blobs/msi_z790p_ddr5/ifd.bin $(pwd)/blobs/msi_z790p_ddr5/me.bin: + COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ + $(pwd)/blobs/msi_z790p_ddr5/download_extract.sh