Make userCodeMap part of the class to avoid conversion issues

_userCodeMap was a global variable. It has been integrated inside the classes that use it to avoid undesired interactions.

Author: jmgc

myhdl/_extractHierarchy.py

@@ -36,16 +36,16 @@
 from ._resolverefs import _resolveRefs
 from ._util import _flatten, _genfunc, _isTupleOfInts, _isTupleOfFloats
 
-
 _profileFunc = None
 
 
 class _error:
     pass
 
+
 _error.NoInstances = "No instances found"
 _error.InconsistentHierarchy = "Inconsistent hierarchy - are all" \
-    " instances returned ?"
+                               " instances returned ?"
 _error.InconsistentToplevel = "Inconsistent top level %s for %s - should be 1"
 
 
@@ -77,6 +77,7 @@ def __init__(self, level, obj, subs, constdict, sigdict, memdict,
 
         self.name = None
 
+
 _memInfoMap = {}
 
 
@@ -174,11 +175,6 @@ def _isRom(mem):
     return id(mem) in _romInfoMap
 
 
-_userCodeMap = {'verilog': {},
-                'vhdl': {}
-                }
-
-
 class _UserCode(object):
     __slots__ = ['code', 'namespace', 'funcname', 'func', 'sourcefile',
                  'sourceline']
@@ -204,7 +200,14 @@ def __str__(self):
         code = "\n%s\n" % code
         return code
 
+    def _scrub_namespace(self):
+        for nm, obj in self.namespace.items():
+            if _isMem(obj):
+                memi = _getMemInfo(obj)
+                self.namespace[nm] = memi.name
+
     def _interpolate(self):
+        self._scrub_namespace()
         return string.Template(self.code).substitute(self.namespace)
 
 
@@ -264,40 +267,6 @@ def __str__(self):
         return s
 
 
-def _addUserCode(specs, arg, funcname, func, frame):
-    classMap = {
-                '__verilog__': _UserVerilogCodeDepr,
-                '__vhdl__': _UserVhdlCodeDepr,
-                'verilog_code': _UserVerilogCode,
-                'vhdl_code': _UserVhdlCode,
-                'verilog_instance': _UserVerilogInstance,
-                'vhdl_instance': _UserVhdlInstance,
-
-               }
-    namespace = frame.f_globals.copy()
-    namespace.update(frame.f_locals)
-    sourcefile = inspect.getsourcefile(frame)
-    sourceline = inspect.getsourcelines(frame)[1]
-    for hdl in _userCodeMap:
-        oldspec = "__%s__" % hdl
-        codespec = "%s_code" % hdl
-        instancespec = "%s_instance" % hdl
-        spec = None
-        # XXX add warning logic
-        if instancespec in specs:
-            spec = instancespec
-        elif codespec in specs:
-            spec = codespec
-        elif oldspec in specs:
-            spec = oldspec
-        if spec:
-            assert id(arg) not in _userCodeMap[hdl]
-            code = specs[spec]
-            _userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace,
-                                                        funcname, func,
-                                                        sourcefile, sourceline)
-
-
 class _CallFuncVisitor(object):
 
     def __init__(self):
@@ -319,8 +288,10 @@ def __init__(self, name, dut, *args, **kwargs):
 
         global _profileFunc
         _memInfoMap.clear()
-        for hdl in _userCodeMap:
-            _userCodeMap[hdl].clear()
+        self.userCodeMap = {'verilog': {},
+                            'vhdl': {}
+                            }
+
         self.skipNames = ('always_comb', 'instance',
                           'always_seq', '_always_seq_decorator',
                           'always', '_always_decorator',
@@ -395,7 +366,7 @@ def extractor(self, frame, event, arg):
                 isGenSeq = _isGenSeq(arg)
                 if isGenSeq:
                     specs = {}
-                    for hdl in _userCodeMap:
+                    for hdl in self.userCodeMap:
                         spec = "__%s__" % hdl
                         if spec in frame.f_locals and frame.f_locals[spec]:
                             specs[spec] = frame.f_locals[spec]
@@ -408,7 +379,7 @@ def extractor(self, frame, event, arg):
                                 getattr(func, spec):
                             specs[spec] = getattr(func, spec)
                     if specs:
-                        _addUserCode(specs, arg, funcname, func, frame)
+                        self._add_user_code(specs, arg, funcname, func, frame)
                 # building hierarchy only makes sense if there are generators
                 if isGenSeq and arg:
                     constdict = {}
@@ -462,7 +433,7 @@ def extractor(self, frame, event, arg):
 
                     subs = []
                     for n, sub in frame.f_locals.items():
-                        for elt in _inferArgs(arg):
+                        for elt in _infer_args(arg):
                             if elt is sub:
                                 subs.append((n, sub))
                     inst = _Instance(self.level, arg, subs, constdict,
@@ -474,8 +445,40 @@ def extractor(self, frame, event, arg):
             if funcname in self.skipNames:
                 self.skip -= 1
 
-
-def _inferArgs(arg):
+    def _add_user_code(self, specs, arg, funcname, func, frame):
+        classMap = {
+            '__verilog__': _UserVerilogCodeDepr,
+            '__vhdl__': _UserVhdlCodeDepr,
+            'verilog_code': _UserVerilogCode,
+            'vhdl_code': _UserVhdlCode,
+            'verilog_instance': _UserVerilogInstance,
+            'vhdl_instance': _UserVhdlInstance,
+        }
+        namespace = frame.f_globals.copy()
+        namespace.update(frame.f_locals)
+        sourcefile = inspect.getsourcefile(frame)
+        sourceline = inspect.getsourcelines(frame)[1]
+        for hdl in self.userCodeMap:
+            oldspec = "__%s__" % hdl
+            codespec = "%s_code" % hdl
+            instancespec = "%s_instance" % hdl
+            spec = None
+            # XXX add warning logic
+            if instancespec in specs:
+                spec = instancespec
+            elif codespec in specs:
+                spec = codespec
+            elif oldspec in specs:
+                spec = oldspec
+            if spec:
+                assert id(arg) not in self.userCodeMap[hdl]
+                code = specs[spec]
+                self.userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace,
+                                                           funcname, func,
+                                                           sourcefile, sourceline)
+
+
+def _infer_args(arg):
     c = [arg]
     if isinstance(arg, (tuple, list)):
         c += list(arg)

myhdl/conversion/_toVHDL.py

@@ -55,7 +55,7 @@
 from .._bin import bin
 from .._errors import ToVHDLError, ToVHDLWarning, ConversionError
 from .._extractHierarchy import (_HierExtr, _isMem, _isRom, _getMemInfo,
-                                 _UserVhdlCode, _userCodeMap, _MemInfo,
+                                 _UserVhdlCode, _MemInfo,
                                  _RomInfo, _Constant, _getRomInfo,
                                  _makeMemInfo, _makeRomInfo)
 from .._instance import _Instantiator
@@ -90,12 +90,16 @@ def __init__(self):
         self.enum_types = {}
         self.rom_types = {}
         self.sfixed = False
+        self.userCodeMap = {'verilog': {},
+                            'vhdl': {}
+                            }
 
     def __call__(self, h, stdLogicPorts):
         p_entity_dict = {}
         p_offsprings_dict = {}
         p_v_entity_dict = {}
-        entity_list = _flatten(h.hierarchy[:])
+        entity_list = self._flatten(h.hierarchy[:])
+        self.userCodeMap = h.userCodeMap
         absnames = h.absnames
 
         # Search the associated entities (components)
@@ -158,7 +162,7 @@ def __call__(self, h, stdLogicPorts):
                 components_list.append(component)
                 component._clean_signals(1)
 
-            p_entity_obj = _flatten(p_entity.obj)
+            p_entity_obj = self._flatten(p_entity.obj)
             # After having determined the signals and other elements, the
             # duplicated generators are deleted. It has to be done between
             # generating the signals and analyzing the top function to avoid
@@ -402,6 +406,18 @@ def __call__(self, h, stdLogicPorts):
 
         return self
 
+    def _flatten(self, *args):
+        arglist = []
+        for arg in args:
+            if id(arg) in self.userCodeMap['vhdl']:
+                arglist.append(self.userCodeMap['vhdl'][id(arg)])
+            elif isinstance(arg, (list, tuple, set)):
+                for item in arg:
+                    arglist.extend(self._flatten(item))
+            else:
+                arglist.append(arg)
+        return arglist
+
     def _flattenNames(self, args_list, args_dict, names_list, existing_signals,
                       base_name=''):
         sigs_dict = {}
@@ -1083,19 +1099,6 @@ def _clean_signals(self, level):
         self.entity._clean_signals(level - 1)
 
 
-def _flatten(*args):
-    arglist = []
-    for arg in args:
-        if id(arg) in _userCodeMap['vhdl']:
-            arglist.append(_userCodeMap['vhdl'][id(arg)])
-        elif isinstance(arg, (list, tuple, set)):
-            for item in arg:
-                arglist.extend(_flatten(item))
-        else:
-            arglist.append(arg)
-    return arglist
-
-
 def _makeDoc(doc, indent=''):
     if doc is None:
         return ''
@@ -4452,7 +4455,7 @@ def visit_Call(self, node):
             node.vhd = vhd_unsigned(s)
         elif f is bool:
             node.vhd = vhd_boolean()
-        elif f in _flatten(int, ord):
+        elif f in (int, ord):
             node.vhd = vhd_int()
             node.args[0].vhd = vhd_int()
         elif f is float:

myhdl/conversion/_toVerilog.py

@@ -47,7 +47,7 @@
 from .._delay import delay
 from .._errors import ToVerilogError, ToVerilogWarning
 from .._extractHierarchy import _HierExtr, _isMem, _getMemInfo, _MemInfo, \
-    _isRom, _getRomInfo, _UserVerilogCode, _userCodeMap
+    _isRom, _getRomInfo, _UserVerilogCode
 
 from .._instance import _Instantiator
 from ._misc import _error, _kind, _context, \
@@ -70,19 +70,6 @@ def _checkArgs(arglist):
             raise ToVerilogError(_error.ArgType, arg)
 
 
-def _flatten(*args):
-    arglist = []
-    for arg in args:
-        if id(arg) in _userCodeMap['verilog']:
-            arglist.append(_userCodeMap['verilog'][id(arg)])
-        elif isinstance(arg, (list, tuple, set)):
-            for item in arg:
-                arglist.extend(_flatten(item))
-        else:
-            arglist.append(arg)
-    return arglist
-
-
 def _makeDoc(doc, indent=''):
     if doc is None:
         return ''
@@ -105,7 +92,8 @@ class _ToVerilogConvertor(object):
                  "no_myhdl_header",
                  "no_testbench",
                  "portmap",
-                 "trace"
+                 "trace",
+                 "userCodeMap"
                  )
 
     def __init__(self):
@@ -119,6 +107,21 @@ def __init__(self):
         self.no_myhdl_header = False
         self.no_testbench = False
         self.trace = False
+        self.userCodeMap = {'verilog': {},
+                            'vhdl': {}
+                            }
+
+    def _flatten(self, *args):
+        arglist = []
+        for arg in args:
+            if id(arg) in self.userCodeMap['verilog']:
+                arglist.append(self.userCodeMap['verilog'][id(arg)])
+            elif isinstance(arg, (list, tuple, set)):
+                for item in arg:
+                    arglist.extend(self._flatten(item))
+            else:
+                arglist.append(arg)
+        return arglist
 
     def __call__(self, func, *args, **kwargs):
         global _converting
@@ -148,14 +151,16 @@ def __call__(self, func, *args, **kwargs):
         else:
             directory = self.directory
 
+        self.userCodeMap = h.userCodeMap
+
         vfilename = name + ".v"
         vpath = os.path.join(directory, vfilename)
         vfile = open(vpath, 'w+')
 
         # initialize properly #
         _genUniqueSuffix.reset()
 
-        arglist = _flatten(h.top)
+        arglist = self._flatten(h.top)
         # print h.top
         _checkArgs(arglist)
         genlist = _analyzeGens(arglist, h.absnames)