vISA LocalScheduler: add 6-instructions-latency to WAR dependency to a send (2nd try)

Add WAR_SEND_LATENCY=12 for instructions having WAR to sends to hide the latency in between.

A send does not read its srcs quickly. The send message sits in MAO until it grants the use
of the SF. Is until that moment where it starts reading its source. Moreover, if the message
is long (messages can red in average 6 registers), freeing the $x.src dependency can take
several cycles. If there are several EUs competing for the use of the MAO, this time can
elongate further.

Author: DianaChen

visa/LocalScheduler/LatencyTable.h

@@ -26,7 +26,8 @@ namespace vISA
         IVB_PIPELINE_LENGTH     = 14,
         EDGE_LATENCY_MATH       = 22,
         EDGE_LATENCY_MATH_TYPE2 = 30,
-        EDGE_LATENCY_SEND_WAR   = 36
+        EDGE_LATENCY_SEND_WAR   = 36,
+        WAR_SEND_LATENCY        = 12    // Latency between an inst and previous send which the inst has WAR dependency to the send
     };
 
     //

visa/LocalScheduler/LocalScheduler_G4IR.cpp

@@ -2922,6 +2922,13 @@ uint32_t DDD::getEdgeLatency_old(Node *node, DepType depT)
         break;
 
     case WAR:
+        if (inst->isSend() && getBuilder()->hasSWSB()) {
+            // enable only for platforms having swsb to avoid unexpected
+            // failures found on pre-XE platforms
+            latency = WAR_SEND_LATENCY;
+            break;
+        }
+        // fall through
     case WAR_MEMORY:
     case WAW:
     case WAW_MEMORY:  //?? WAW have the same cycle as RAW?