Convert LShr+And pattern to EE for later promotion to mov/region.

From:
  %28 = and i32 %24, 255
  %29 = lshr i32 %24, 8
  %30 = and i32 %29, 255
  %res1 = mul nuw nsw i32 %28, 9798
  %res2 = mul nuw nsw i32 %30, 19235
...
  shr (16|M0)   r32.0<1>:d  r16.0<8;8,1>:ud   8:w
  and (16|M0)   r32.0<1>:d  r32.0<8;8,1>:d    255:w
  mul (16|M0)   r32.0<1>:d  r32.0<8;8,1>:d    19235:w

To:
  %temp = bitcast i32 %24 to <4 x i8>
  %ee1 = extractelement <4 x i8> %temp, i32 0
  %ee2 = extractelement <4 x i8> %temp, i32 1
  %28 = zext i8 %ee1 to i32
  %30 = zext i8 %ee2 to i32
...
  mul (16|M0)   r32.0<1>:d  r16.1<4;1,0>:ub   19235:w

And similar pattern:
From:
  %shl = shl i32 %129, 16
  %132 = ashr exact i32 %shl, 16
  %133 = ashr i32 %129, 16

To:
  %temp = bitcast i32 %129 to <2 x i16>
  %ee1 = extractelement <2 x i16> %temp, i32 0
  %ee2 = extractelement <2 x i16> %temp, i32 1
  %132 = sext i8 %ee1 to i32
  %133 = sext i8 %ee2 to i32

Change-Id: Ia8b09bdd07ee4cc72004539ea88f0a1e27d3e796

Author: bgajdaINTC

IGC/Compiler/CustomSafeOptPass.cpp

@@ -2273,7 +2273,114 @@ void GenSpecificPattern::visitBinaryOperator(BinaryOperator& I)
         {
             createBitcastExtractInsertPattern(I, nullptr, I.getOperand(0), 0, 1);
         }
+        else
+        {
+
+            Instruction* AndSrc = nullptr;
+            ConstantInt* CI;
+
+            /*
+            From:
+              %28 = and i32 %24, 255
+              %29 = lshr i32 %24, 8
+              %30 = and i32 %29, 255
+              %31 = lshr i32 %24, 16
+              %32 = and i32 %31, 255
+
+            To:
+              %temp = bitcast i32 %24 to <4 x i8>
+              %ee1 = extractelement <4 x i8> %temp, i32 0
+              %ee2 = extractelement <4 x i8> %temp, i32 1
+              %ee3 = extractelement <4 x i8> %temp, i32 2
+              %28 = zext i8 %ee1 to i32
+              %30 = zext i8 %ee2 to i32
+              %32 = zext i8 %ee3 to i32
+
+
+            */
+            auto pattern_And_0xFF = m_And(m_Instruction(AndSrc), m_SpecificInt(0xFF));
+
+            CodeGenContext* ctx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext();
+            bool bytesAllowed = IGC_IS_FLAG_ENABLED(EnableMixInt8Operands) && ctx->platform.supportByteALUOperation();
+
+            if (bytesAllowed && match(&I, pattern_And_0xFF) && I.getType()->isIntegerTy(32) && AndSrc->getType()->isIntegerTy(32))
+            {
+                Instruction* LhsSrc = nullptr;
+
+                auto LShr_Pattern = m_LShr(m_Instruction(LhsSrc), m_ConstantInt(CI));
+                bool LShrMatch = match(AndSrc, LShr_Pattern) && LhsSrc->getType()->isIntegerTy(32) && (CI->getZExtValue() % 8 == 0);
+
+                // in case there's no shr, it will be 0
+                uint32_t newIndex = 0;
+
+                if (LShrMatch) // extract inner
+                {
+                    AndSrc = LhsSrc;
+                    newIndex = (uint32_t)CI->getZExtValue() / 8;
+                }
+
+                llvm::IRBuilder<> builder(&I);
+                VectorType* vec4 = VectorType::get(builder.getInt8Ty(), 4);
+                Value* BC = builder.CreateBitCast(AndSrc, vec4);
+                Value* EE = builder.CreateExtractElement(BC, builder.getInt32(newIndex));
+                Value* Zext = builder.CreateZExt(EE, builder.getInt32Ty());
+                I.replaceAllUsesWith(Zext);
+                I.eraseFromParent();
+
+            }
+
+        }
     }
+    else if (I.getOpcode() == Instruction::AShr)
+    {
+        /*
+            From:
+            %129 = i32...
+            %Temp = shl i32 %129, 16
+            %132 = ashr exact i32 %Temp, 16
+            %133 = ashr i32 %129, 16
+
+            To:
+            %129 = i32...
+            %temp = bitcast i32 %129 to <2 x i16>
+            %ee1 = extractelement <2 x i16> %temp, i32 0
+            %ee2 = extractelement <2 x i16> %temp, i32 1
+            %132 = sext i8 %ee1 to i32
+            %133 = sext i8 %ee2 to i32
+            Which will end up as regioning instead of 2 isntr.
+        */
+        using namespace llvm::PatternMatch;
+
+        Instruction* AShrSrc = nullptr;
+        auto pattern_1 = m_AShr(m_Instruction(AShrSrc), m_SpecificInt(16));
+
+        if (match(&I, pattern_1) && I.getType()->isIntegerTy(32) && AShrSrc->getType()->isIntegerTy(32))
+        {
+            Instruction* ShlSrc = nullptr;
+
+            auto Shl_Pattern = m_Shl(m_Instruction(ShlSrc), m_SpecificInt(16));
+            bool submatch = match(AShrSrc, Shl_Pattern) && ShlSrc->getType()->isIntegerTy(32);
+
+            // in case there's no shr, we take upper half
+            uint32_t newIndex = 1;
+
+            // if there was Shl, we take lower half
+            if (submatch)
+            {
+                AShrSrc = ShlSrc;
+                newIndex = 0;
+            }
+
+            llvm::IRBuilder<> builder(&I);
+            VectorType* vec2 = VectorType::get(builder.getInt16Ty(), 2);
+            Value* BC = builder.CreateBitCast(AShrSrc, vec2);
+            Value* EE = builder.CreateExtractElement(BC, builder.getInt32(newIndex));
+            Value* Sext = builder.CreateSExt(EE, builder.getInt32Ty());
+            I.replaceAllUsesWith(Sext);
+            I.eraseFromParent();
+        }
+    }
+
 }
 
 void GenSpecificPattern::visitCmpInst(CmpInst& I)

IGC/common/igc_flags.def

@@ -380,6 +380,7 @@ DECLARE_IGC_REGKEY(bool, cl_khr_srgb_image_writes,      false, "Enable cl_khr_sr
 DECLARE_IGC_REGKEY(bool, MSAA16BitPayloadEnable,        true,  "Enable support for MSAA 16 bit payload , a hardware DCN supporting this from ICL+ to improve perf on MSAA workloads", false)
 DECLARE_IGC_REGKEY(bool, EnableInsertElementScalarCoalescing, false,  "Enable coalescing on the scalar operand of insertelement", false)
 DECLARE_IGC_REGKEY(bool, EnableMixIntOperands,          true,  "Enable generating mix-sized operands for int ALU", false)
+DECLARE_IGC_REGKEY(bool, EnableMixInt8Operands,         true,  "Enable generating bytes in mix-sized operands for int ALU", false)
 DECLARE_IGC_REGKEY(bool, PixelShaderDoNotAbortOnSpill,  false, "Do not abort on a spill", false)
 DECLARE_IGC_REGKEY(DWORD, ForcePixelShaderSIMDMode,     0,     "Setting it to values def in igc.h will force SIMD mode compilation for pixel shaders. Note that only SIMD8 is compiled unless other ForcePixelShaderSIMD* are also selected", false)
 DECLARE_IGC_REGKEY(DWORD, StagedCompilationExperiments, 0,     "Experiment with staged compilation when != 0", false)