Support SPV_INTEL_cache_controls for 1d block reads and writes

This change implements the support for cache controls for block operations
from `SPV_INTEL_subgroups` extension.

(cherry picked from commit 6559ba2)

Author: aratajew

IGC/AdaptorOCL/preprocess_spvir/HandleSPIRVDecorations/HandleSpirvDecorationMetadata.cpp

@@ -184,6 +184,42 @@ void HandleSpirvDecorationMetadata::visitPrefetchCallInst(CallInst& I)
     }
 }
 
+void HandleSpirvDecorationMetadata::visit1DBlockReadCallInst(CallInst& I)
+{
+    Value* ptr = I.getArgOperand(0);
+    auto spirvDecorations = parseSPIRVDecorationsFromMD(ptr);
+    for (auto& [DecorationId, MDNodes] : spirvDecorations)
+    {
+        switch (DecorationId)
+        {
+            // IDecCacheControlLoadINTEL
+            case DecorationIdCacheControlLoad:
+            {
+                handleCacheControlINTELFor1DBlockIO<LoadCacheControl>(I, MDNodes);
+                break;
+            }
+        }
+    }
+}
+
+void HandleSpirvDecorationMetadata::visit1DBlockWriteCallInst(CallInst& I)
+{
+    Value* ptr = I.getArgOperand(0);
+    auto spirvDecorations = parseSPIRVDecorationsFromMD(ptr);
+    for (auto& [DecorationId, MDNodes] : spirvDecorations)
+    {
+        switch (DecorationId)
+        {
+            // IDecCacheControlStoreINTEL
+            case DecorationIdCacheControlStore:
+            {
+                handleCacheControlINTELFor1DBlockIO<StoreCacheControl>(I, MDNodes);
+                break;
+            }
+        }
+    }
+}
+
 void HandleSpirvDecorationMetadata::visitCallInst(CallInst& I)
 {
     Function* F = I.getCalledFunction();
@@ -195,8 +231,12 @@ void HandleSpirvDecorationMetadata::visitCallInst(CallInst& I)
         "_Z[0-9]+(intel_sub_group_2d_block_write_[0-9]+b_[0-9]+r[0-9]+x[0-9]+c)");
 #if defined(IGC_SCALAR_USE_KHRONOS_SPIRV_TRANSLATOR)
     Regex patternPrefetch("_Z[0-9]+__spirv_ocl_prefetch");
+    Regex pattern1DBlockRead("_Z[0-9]+__spirv_SubgroupBlockReadINTEL");
+    Regex pattern1DBlockWrite("_Z[0-9]+__spirv_SubgroupBlockWriteINTEL");
 #else // IGC Legacy SPIRV Translator
     Regex patternPrefetch("__builtin_spirv_OpenCL_prefetch");
+    Regex pattern1DBlockRead("__builtin_spirv_OpSubgroupBlockReadINTEL");
+    Regex pattern1DBlockWrite("__builtin_spirv_OpSubgroupBlockWriteINTEL");
 #endif
 
     SmallVector<StringRef, 4> Matches;
@@ -214,6 +254,14 @@ void HandleSpirvDecorationMetadata::visitCallInst(CallInst& I)
     {
         visitPrefetchCallInst(I);
     }
+    else if (pattern1DBlockRead.match(funcName, &Matches))
+    {
+        visit1DBlockReadCallInst(I);
+    }
+    else if (pattern1DBlockWrite.match(funcName, &Matches))
+    {
+        visit1DBlockWriteCallInst(I);
+    }
 }
 
 template<typename T>
@@ -327,3 +375,86 @@ void HandleSpirvDecorationMetadata::handleCacheControlINTELForPrefetch(llvm::Cal
     if (F->getNumUses() == 0)
         m_BuiltinsToRemove.insert(F);
 }
+
+template<typename T>
+void HandleSpirvDecorationMetadata::handleCacheControlINTELFor1DBlockIO(CallInst& I, SmallPtrSetImpl<MDNode*>& MDNodes)
+{
+    static_assert(std::is_same_v<T, LoadCacheControl> || std::is_same_v<T, StoreCacheControl>);
+    CacheControlFromMDNodes cacheControl = resolveCacheControlFromMDNodes<T>(m_pCtx, MDNodes);
+    if (cacheControl.isEmpty) return;
+    if (cacheControl.isInvalid)
+    {
+        m_pCtx->EmitWarning("Unsupported cache controls configuration requested. Applying default configuration.");
+        return;
+    }
+
+    Function* F = I.getCalledFunction();
+    IGC_ASSERT(F);
+
+    Type* operationType = nullptr;
+    std::string funcName;
+    if constexpr (std::is_same_v<T, LoadCacheControl>)
+    {
+        operationType = I.getType();
+        funcName = "SubgroupBlockReadINTEL";
+    }
+    else
+    {
+        operationType = I.getArgOperand(1)->getType();
+        funcName = "SubgroupBlockWriteINTEL";
+    }
+
+    std::string typeName;
+    uint32_t numElements = 1;
+    Type* elementType = operationType;
+    if (auto* vecTy = dyn_cast<IGCLLVM::FixedVectorType>(operationType))
+    {
+        numElements = (uint32_t)vecTy->getNumElements();
+        elementType = vecTy->getElementType();
+    }
+
+    if (elementType->isIntegerTy())
+    {
+        switch (elementType->getIntegerBitWidth())
+        {
+            case 8:
+                typeName = "char";
+                break;
+            case 16:
+                typeName = "short";
+                break;
+            case 32:
+                typeName = "int";
+                break;
+            case 64:
+                typeName = "long";
+                break;
+            default:
+                IGC_ASSERT(0 && "Unsupported integer type");
+                break;
+        }
+    }
+
+    if(numElements > 1)
+        typeName += std::to_string(numElements);
+
+    SmallVector<Value*, 3> args(I.args());
+    args.push_back(ConstantInt::get(Type::getInt32Ty(I.getContext()), cacheControl.value));
+
+    SmallVector<Type*, 3> argTypes;
+    for (const auto& arg : args)
+        argTypes.push_back(arg->getType());
+
+    FunctionType* funcTy = FunctionType::get(I.getType(), argTypes, false);
+    std::string newFuncName = "__internal_" + funcName + "_" + typeName + "_cache_controls";
+    auto newFunction = m_Module->getOrInsertFunction(newFuncName, funcTy);
+
+    auto newCall = CallInst::Create(newFunction, args, "", &I);
+    I.replaceAllUsesWith(newCall);
+    I.eraseFromParent();
+    m_changed = true;
+
+    // Cleanup unused function if all calls have been replaced with the internal version
+    if (F->getNumUses() == 0)
+        m_BuiltinsToRemove.insert(F);
+}

IGC/AdaptorOCL/preprocess_spvir/HandleSPIRVDecorations/HandleSpirvDecorationMetadata.h

@@ -50,6 +50,8 @@ namespace IGC
         void visit2DBlockReadCallInst(llvm::CallInst& I, llvm::StringRef unmangledName);
         void visit2DBlockWriteCallInst(llvm::CallInst& I, llvm::StringRef unmangledName);
         void visitPrefetchCallInst(llvm::CallInst& I);
+        void visit1DBlockReadCallInst(llvm::CallInst& I);
+        void visit1DBlockWriteCallInst(llvm::CallInst& I);
 
     private:
         llvm::Module* m_Module = nullptr;
@@ -67,5 +69,7 @@ namespace IGC
         template<typename T>
         void handleCacheControlINTELFor2DBlockIO(llvm::CallInst& I, llvm::SmallPtrSetImpl<llvm::MDNode*>& MDNodes, llvm::StringRef unmangledName);
         void handleCacheControlINTELForPrefetch(llvm::CallInst& I, llvm::SmallPtrSetImpl<llvm::MDNode*>& MDNodes);
+        template<typename T>
+        void handleCacheControlINTELFor1DBlockIO(llvm::CallInst& I, llvm::SmallPtrSetImpl<llvm::MDNode*>& MDNodes);
     };
 }

IGC/BiFModule/Implementation/IGCBiF_Intrinsics.cl

@@ -612,6 +612,51 @@ void    __builtin_IB_simd_block_write_2_global_l( __global ulong*, ulong2 );
 void    __builtin_IB_simd_block_write_4_global_l( __global ulong*, ulong4 );
 void    __builtin_IB_simd_block_write_8_global_l( __global ulong*, ulong8 );
 
+// 1D block reads and writes with cache control argument : global address space
+uint    __builtin_IB_cache_controls_simd_block_read_1_global(const __global uint* base, uint cacheOpt);
+uint2   __builtin_IB_cache_controls_simd_block_read_2_global(const __global uint* base, uint cacheOpt);
+uint4   __builtin_IB_cache_controls_simd_block_read_4_global(const __global uint* base, uint cacheOpt);
+uint8   __builtin_IB_cache_controls_simd_block_read_8_global(const __global uint* base, uint cacheOpt);
+
+ushort    __builtin_IB_cache_controls_simd_block_read_1_global_h(const __global ushort* base, uint cacheOpt);
+ushort2   __builtin_IB_cache_controls_simd_block_read_2_global_h(const __global ushort* base, uint cacheOpt);
+ushort4   __builtin_IB_cache_controls_simd_block_read_4_global_h(const __global ushort* base, uint cacheOpt);
+ushort8   __builtin_IB_cache_controls_simd_block_read_8_global_h(const __global ushort* base, uint cacheOpt);
+ushort16  __builtin_IB_cache_controls_simd_block_read_16_global_h(const __global ushort* base, uint cacheOpt);
+
+uchar    __builtin_IB_cache_controls_simd_block_read_1_global_b(const __global uchar* base, uint cacheOpt);
+uchar2   __builtin_IB_cache_controls_simd_block_read_2_global_b(const __global uchar* base, uint cacheOpt);
+uchar4   __builtin_IB_cache_controls_simd_block_read_4_global_b(const __global uchar* base, uint cacheOpt);
+uchar8   __builtin_IB_cache_controls_simd_block_read_8_global_b(const __global uchar* base, uint cacheOpt);
+uchar16  __builtin_IB_cache_controls_simd_block_read_16_global_b(const __global uchar* base, uint cacheOpt);
+
+ulong    __builtin_IB_cache_controls_simd_block_read_1_global_l(const __global ulong* base, uint cacheOpt);
+ulong2   __builtin_IB_cache_controls_simd_block_read_2_global_l(const __global ulong* base, uint cacheOpt);
+ulong4   __builtin_IB_cache_controls_simd_block_read_4_global_l(const __global ulong* base, uint cacheOpt);
+ulong8   __builtin_IB_cache_controls_simd_block_read_8_global_l(const __global ulong* base, uint cacheOpt);
+
+void    __builtin_IB_cache_controls_simd_block_write_1_global(__global uint* base, uint val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_2_global(__global uint* base, uint2 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_4_global(__global uint* base, uint4 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_8_global(__global uint* base, uint8 val, uint cacheOpt);
+
+void    __builtin_IB_cache_controls_simd_block_write_1_global_h(__global ushort* base, ushort val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_2_global_h(__global ushort* base, ushort2 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_4_global_h(__global ushort* base, ushort4 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_8_global_h(__global ushort* base, ushort8 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_16_global_h(__global ushort* base, ushort16 val, uint cacheOpt);
+
+void    __builtin_IB_cache_controls_simd_block_write_1_global_b(__global uchar* base, uchar val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_2_global_b(__global uchar* base, uchar2 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_4_global_b(__global uchar* base, uchar4 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_8_global_b(__global uchar* base, uchar8 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_16_global_b(__global uchar* base, uchar16 val, uint cacheOpt);
+
+void    __builtin_IB_cache_controls_simd_block_write_1_global_l(__global ulong* base, ulong val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_2_global_l(__global ulong* base, ulong2 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_4_global_l(__global ulong* base, ulong4 val, uint cacheOpt);
+void    __builtin_IB_cache_controls_simd_block_write_8_global_l(__global ulong* base, ulong8 val, uint cacheOpt);
+
 // Block read : local address space
 uint    __builtin_IB_simd_block_read_1_local( const __local uint* );
 uint2   __builtin_IB_simd_block_read_2_local( const __local uint* );