Both schedulers need to track extra dependencies on acc registers.

One extra bucket is necessary. Also fix pre-RA scheduler to allow
multiple pseudo-kills on the same variable

Change-Id: I6b68b85923ae9df4b8d377ea42f849bfb485a262

Author: wpan

visa/LocalScheduler/G4_Sched.cpp

@@ -1432,18 +1432,18 @@ bool LatencyQueue::compare(preNode* N1, preNode* N2)
 }
 
 // Find the edge with smallest ID.
-static G4_INST* minElt(const std::vector<preEdge>& Elts)
+static preNode* minElt(const std::vector<preEdge>& Elts)
 {
     assert(!Elts.empty());
     if (Elts.size() == 1)
-        return Elts.front().getNode()->getInst();
+        return Elts.front().getNode();
     auto Cmp = [](const preEdge& E1, const preEdge& E2) {
         G4_INST* Inst1 = E1.getNode()->getInst();
         G4_INST* Inst2 = E2.getNode()->getInst();
         return Inst1 && Inst2 && Inst1->getLocalId() < Inst2->getLocalId();
     };
     auto E = std::min_element(Elts.begin(), Elts.end(), Cmp);
-    return E->getNode()->getInst();
+    return E->getNode();
 }
 
 // Given an instruction stream [p1 p2 A1 A2 A4 A3]
@@ -1461,8 +1461,10 @@ void BB_Scheduler::relocatePseudoKills()
     for (auto N : ddd.getNodes()) {
         G4_INST* Inst = N->getInst();
         if (Inst && Inst->isPseudoKill()) {
-            G4_INST* Pos = minElt(N->Succs);
-            LocMap[Pos].push_back(Inst);
+            preNode* Pos = minElt(N->Succs);
+            while (Pos->getInst()->isPseudoKill())
+                Pos = minElt(Pos->Succs);
+            LocMap[Pos->getInst()].push_back(Inst);
         }
     }
 
@@ -1649,7 +1651,11 @@ void preDDD::buildGraph()
 
 static bool isPhyicallyAllocatedRegVar(G4_Operand* opnd)
 {
-    if (opnd && opnd->getBase() && opnd->getBase()->isRegVar())
+    assert(opnd);
+    G4_AccRegSel Acc = opnd->getAccRegSel();
+    if (Acc != G4_AccRegSel::ACC_UNDEFINED && Acc != G4_AccRegSel::NOACC)
+        return true;
+    if (opnd->getBase() && opnd->getBase()->isRegVar())
         return opnd->getBase()->asRegVar()->getPhyReg() != nullptr;
     return false;
 }

visa/LocalScheduler/LocalScheduler_G4IR.cpp

@@ -403,12 +403,17 @@ void DDD::getBucketsForOperand(G4_INST* inst, Gen4_Operand_Number opnd_num,
             int baseBucket = GRF_BUCKET;
             int endingBucket = baseBucket + opnd->getLinearizedEnd() / divisor;
             MUST_BE_TRUE(endingBucket >= startingBucket, "Ending bucket less than starting bucket");
+            Mask mask = getMaskForOp(opnd, opnd_num, inst->getExecSize());
             int numBuckets = endingBucket - startingBucket + 1;
             for (int j = startingBucket;
                 j < (startingBucket + numBuckets); j++) {
-                Mask mask = getMaskForOp(opnd, opnd_num, inst->getExecSize());
                 BDvec.push_back(BucketDescr(j, mask, opnd_num));
             }
+            // If this operand is a non-trivial special ACC operand, add
+            // it to the other ARF bucket for tacking extra dependencies.
+            G4_AccRegSel Acc = opnd->getAccRegSel();
+            if (Acc != G4_AccRegSel::ACC_UNDEFINED && Acc != G4_AccRegSel::NOACC)
+                BDvec.push_back(BucketDescr(OTHER_ARF_BUCKET, mask, opnd_num));
         } else {
             Mask mask = getMaskForOp(opnd, opnd_num, inst->getExecSize());
             BDvec.push_back(BucketDescr(startingBucket, mask, opnd_num));

visa/RegAlloc.cpp

@@ -2719,8 +2719,7 @@ void LivenessAnalysis::computeGenKillandPseudoKill(G4_BB* bb,
             {
                 iterToInsert--;
             } while ((*iterToInsert)->isPseudoKill());
-            G4_DstRegRegion* dstOpnd = fg.builder->createDstRegRegion(Direct, pseudoKill.first->getRegVar(), 0, 0, 1, Type_UD);
-            G4_INST* killInst = fg.builder->createInternalInst(NULL, G4_pseudo_kill, NULL, false, 1, dstOpnd, NULL, NULL, 0);
+            G4_INST* killInst = fg.builder->createPseudoKill(pseudoKill.first);
             bb->insert(iterToInsert, killInst);
         }
     }