[IGC VC] Prevent assert in GenXUnbaling

Do not call Instruction::comesBefore() if instructions are in different
basic blocks - this results in assertion

(cherry picked from commit e166627)

Author: mshelego

IGC/VectorCompiler/lib/GenXCodeGen/GenXUnbaling.cpp

@@ -442,8 +442,9 @@ bool canBeSafelyHoisted(Instruction *Inst, Instruction *InsertBefore) {
   if (!InsertBefore->comesBefore(Inst))
     return false;
   auto IsDefinedAtInsertPoint = [InsertBefore](Value *V) {
-    return !isa<Instruction>(V) ||
-           cast<Instruction>(V)->comesBefore(InsertBefore);
+    auto *Inst = dyn_cast<Instruction>(V);
+    return !Inst || Inst->getParent() == InsertBefore->getParent() &&
+                        Inst->comesBefore(InsertBefore);
   };
 #endif
   return std::all_of(Inst->value_op_begin(), Inst->value_op_end(),

IGC/VectorCompiler/test/GenXUnbaling/debug-shorten-lr.ll

@@ -38,6 +38,9 @@ entry:
   call void @llvm.dbg.value(metadata <16 x i32> %rdregioni, metadata !12, metadata !DIExpression()), !dbg !18
   %wrregioni = call <16 x i32> @llvm.genx.wrregioni.v16i32.v16i32.v16i32.i32.i1(<16 x i32> %rdregioni, <16 x i32> %load, i32 1, i32 1, i32 0, i16 4, i32 0, i1 true), !dbg !19
   call void @llvm.dbg.value(metadata <16 x i32> %wrregioni, metadata !13, metadata !DIExpression()), !dbg !19
+  br label %body
+
+body:
   %wrregioni2 = call <16 x i32> @llvm.genx.wrregioni.v16i32.v16i32.v16i32.i32.i1(<16 x i32> %wrregioni, <16 x i32> %load, i32 1, i32 1, i32 0, i16 6, i32 0, i1 true), !dbg !20
   call void @llvm.dbg.value(metadata <16 x i32> %wrregioni2, metadata !14, metadata !DIExpression()), !dbg !20
   %rdregioni3 = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> %wrregioni, i32 1, i32 1, i32 0, i16 0, i32 0), !dbg !21