[Autobackout][FuncReg]Revert of change: 7547a8d

 Enable SSOShifter by default (2nd attempt)

This includes a fix to skip sso padding when it reaches the kernel size
limit

Author: houjenko

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -6172,8 +6172,6 @@ namespace IGC
               shaderOverrideVISAFirstPass(visaOverrideFiles, kernelName);
         }
 
-        vISA::FINALIZER_INFO* jitInfo = nullptr;
-
         // Compile generated VISA text string for inlineAsm
         if (m_hasInlineAsm || visaAsmOverride || additionalVISAAsmToLink)
         {
@@ -6188,9 +6186,6 @@ namespace IGC
         else
         {
             pMainKernel = vMainKernel;
-            pMainKernel->GetJitInfo(jitInfo);
-
-            jitInfo->stats.scratchSpaceSizeLimit = m_program->ProgramOutput()->m_scratchSpaceSizeLimit;
             m_vIsaCompileStatus = vbuilder->Compile(
                 m_enableVISAdump ? GetDumpFileName("isa").c_str() : "", nullptr, emitVisaOnly);
         }
@@ -6210,6 +6205,9 @@ namespace IGC
         // Collect metrics from vISA
         context->metrics.CollectRegStats(vISAstats, m_program->entry);
 
+        vISA::FINALIZER_INFO* jitInfo = nullptr;
+        pMainKernel->GetJitInfo(jitInfo);
+
         // Depend on vISA information about barriers presence to make sure that it's
         // always set properly, even if a barrier is used as a part of Inline vISA code only.
         if (jitInfo->numBarriers != 0)

IGC/common/igc_flags.h

@@ -647,7 +647,7 @@ DECLARE_IGC_REGKEY(bool, LTOForStage1Compilation,       true, "LTO for stage 1 c
 DECLARE_IGC_REGKEY(bool, EnableTrackPtr,                false, "Track Staging Context alloc/dealloc", false)
 DECLARE_IGC_REGKEY(bool, ExtraRetrySIMD16,              false,  "Enable extra simd16 with retry for STAGE1_BEST_PREF", false)
 DECLARE_IGC_REGKEY(bool, SaveRestoreIR,                 true,  "Save/Restore IR for staged compilation to avoid duplicated compilations", false)
-DECLARE_IGC_REGKEY(DWORD, SSOShifter,                   9,     "Adjust ScratchSurfaceOffset with shl(hwtid, shifter). 0 menas disabling padding", false)
+DECLARE_IGC_REGKEY(DWORD, SSOShifter,                   0,     "Adjust ScratchSurfaceOffset with shl(hwtid, shifter). 0 menas disabling padding", false)
 DECLARE_IGC_REGKEY(DWORD, CodePatch,                    2,     "Enable Pixel Shader code patching to directly emit code after stitching", false)
 DECLARE_IGC_REGKEY(DWORD, CodePatchLimit,               0,     "Debug CodePatch via limiting the number of shader been patched", false)
 DECLARE_IGC_REGKEY(DWORD, CodePatchExperiments,         0,      "Experiment with code patching when != 0", false)

visa/BuildCISAIRImpl.cpp

@@ -1863,11 +1863,8 @@ int CISA_IR_Builder::Compile(const char *nameInput, std::ostream *os,
       {
         auto& builder = *func->getKernel()->fg.builder;
         auto& spillMemUsed = builder.getJitInfo()->stats.spillMemUsed;
-        auto& scratchSpaceSizeLimit = builder.getJitInfo()->stats.scratchSpaceSizeLimit;
         bool skip_padding =
-          builder.kernel.getuInt32Option(vISA_SkipPaddingScratchSpaceSize) >= spillMemUsed ||
-          (scratchSpaceSizeLimit != 0 &&
-           spillMemUsed + (1U << builder.kernel.getuInt32Option(vISA_SSOShifter)) * 8 > scratchSpaceSizeLimit);
+          builder.kernel.getuInt32Option(vISA_SkipPaddingScratchSpaceSize) >= spillMemUsed;
         bool SSO_padding =
           !skip_padding &&
           builder.getPlatform() == Xe_DG2 &&

visa/include/JitterDataStruct.h

@@ -56,9 +56,6 @@ struct PERF_STATS {
   // spill cost calculation.
   uint32_t numGRFSpillFillWeighted = 0;
 
-  // The limit of scratch space size per kernel
-  uint32_t scratchSpaceSizeLimit = 0;
-
   // spillMemUsed is the scratch size in byte of entire vISA stack for this
   // function/kernel. It contains spill size and caller/callee save size.
   // For kernel/entry functions, the value is the sum of potential callees