Revert "[IGC BugFix][vISA]: Fix the a0 regiter variable linear Start and linear end bound after register allocation (#62677)"

bcheng0127 · igcbot · commit 40d381262f72 · 2022-04-08T11:33:43.000+02:00
diff --git a/visa/PhyRegCompute.cpp b/visa/PhyRegCompute.cpp
@@ -37,7 +37,7 @@ void G4_SrcRegRegion::computePReg(const IR_Builder& builder)
 
             dcl->setGRFBaseOffset(linearizedStart);
         }
-
+#if 0
         if (baseVar->getPhyReg()->isA0())
         {
             G4_Declare* dcl = baseVar->getDeclare();
@@ -48,7 +48,7 @@ void G4_SrcRegRegion::computePReg(const IR_Builder& builder)
 
             dcl->setGRFBaseOffset(linearizedStart);
         }
-
+#endif
     }
 }
 
@@ -79,6 +79,7 @@ void G4_DstRegRegion::computePReg(const IR_Builder& builder)
             dcl->setGRFBaseOffset(linearizedStart);
         }
 
+#if 0
         if (baseVar->getPhyReg()->isA0())
         {
             G4_Declare* dcl = baseVar->getDeclare();
@@ -89,5 +90,6 @@ void G4_DstRegRegion::computePReg(const IR_Builder& builder)
 
             dcl->setGRFBaseOffset(linearizedStart);
         }
+#endif
     }
 }

Original file line number	Diff line number	Diff line change
`@@ -37,7 +37,7 @@ void G4_SrcRegRegion::computePReg(const IR_Builder& builder)`
`37`	`37`
`38`	`38`	`dcl->setGRFBaseOffset(linearizedStart);`
`39`	`39`	`}`
`40`		`-`
	`40`	`+#if 0`
`41`	`41`	`if (baseVar->getPhyReg()->isA0())`
`42`	`42`	`{`
`43`	`43`	`G4_Declare* dcl = baseVar->getDeclare();`
`@@ -48,7 +48,7 @@ void G4_SrcRegRegion::computePReg(const IR_Builder& builder)`
`48`	`48`
`49`	`49`	`dcl->setGRFBaseOffset(linearizedStart);`
`50`	`50`	`}`
`51`		`-`
	`51`	`+#endif`
`52`	`52`	`}`
`53`	`53`	`}`
`54`	`54`
`@@ -79,6 +79,7 @@ void G4_DstRegRegion::computePReg(const IR_Builder& builder)`
`79`	`79`	`dcl->setGRFBaseOffset(linearizedStart);`
`80`	`80`	`}`
`81`	`81`
	`82`	`+#if 0`
`82`	`83`	`if (baseVar->getPhyReg()->isA0())`
`83`	`84`	`{`
`84`	`85`	`G4_Declare* dcl = baseVar->getDeclare();`
`@@ -89,5 +90,6 @@ void G4_DstRegRegion::computePReg(const IR_Builder& builder)`
`89`	`90`
`90`	`91`	`dcl->setGRFBaseOffset(linearizedStart);`
`91`	`92`	`}`
	`93`	`+#endif`
`92`	`94`	`}`
`93`	`95`	`}`