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[Autobackout][FunctionalRegression]Revert of change: e1e8950: Report LSC stores with non default L1 cache controls in VC
Set zebin flag if a kernel has a store with non default L1 cache controls
1 parent 0b7c330 commit 31b3a5e

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5 files changed

+28
-138
lines changed

5 files changed

+28
-138
lines changed

‎IGC/VectorCompiler/igcdeps/src/cmc.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -834,9 +834,6 @@ static void setExecutionInfo(const GenXOCLRuntimeInfo::KernelInfo &BackendInfo,
834834
ExecEnv.NumGRFRequired = JitterInfo.stats.numGRFTotal;
835835
ExecEnv.RequireDisableEUFusion = BackendInfo.requireDisableEUFusion();
836836
ExecEnv.IndirectStatelessCount = BackendInfo.getIndirectCount();
837-
ExecEnv.HasLscStoresWithNonDefaultL1CacheControls =
838-
BackendInfo.hasLscStoresWithNonDefaultL1CacheControls();
839-
840837

841838
// Allocate spill-fill buffer
842839
if (JitterInfo.hasStackcalls) {

‎IGC/VectorCompiler/include/vc/GenXCodeGen/GenXOCLRuntimeInfo.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,6 @@ class GenXOCLRuntimeInfo : public ModulePass {
180180
bool UsesReadWriteImages = false;
181181
bool UsesSample = false;
182182
bool DisableMidThreadPreemption = false;
183-
bool HasLscStoresWithNonDefaultL1CacheControls = false;
184183

185184
unsigned GRFSizeInBytes;
186185
unsigned NumBarriers = 0;
@@ -278,9 +277,6 @@ class GenXOCLRuntimeInfo : public ModulePass {
278277
bool usesSample() const { return FuncInfo.UsesSample; }
279278
bool usesReadWriteImages() const { return FuncInfo.UsesReadWriteImages; }
280279
bool requireDisableEUFusion() const { return FuncInfo.DisableEUFusion; }
281-
bool hasLscStoresWithNonDefaultL1CacheControls() const {
282-
return FuncInfo.HasLscStoresWithNonDefaultL1CacheControls;
283-
}
284280

285281
// Arguments accessors.
286282
arg_iterator arg_begin() { return ArgInfos.begin(); }

‎IGC/VectorCompiler/include/vc/InternalIntrinsics/Intrinsic_definitions.py‎

Lines changed: 28 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# ========================== begin_copyright_notice ============================
22
#
3-
# Copyright (C) 2022-2025 Intel Corporation
3+
# Copyright (C) 2022-2024 Intel Corporation
44
#
55
# SPDX-License-Identifier: MIT
66
#
@@ -105,8 +105,8 @@
105105
##
106106
## * Return value: private/local/global pointer
107107
##
108-
## This intrinsic attempts to explicitly convert a generic ptr to a
109-
## private/local/global ptr. If the cast fails the intrinsic returns null pointer.
108+
## This intrisic attempts to explicitly convert a generic ptr to a
109+
## private/local/global ptr. If the cast fails the intrisic returns null pointer.
110110
"cast_to_ptr_explicit" : { "result": "anyptr",
111111
"arguments": ["ptr_generic"],
112112
"attributes": "None",
@@ -216,15 +216,11 @@
216216
"atomic_fmin" : { "result": "anyfloat",
217217
"arguments": [ "anyptr", "int", "int",
218218
"anyfloat"],
219-
"attributes": "None",
220-
"memory_effects":
221-
{ "access": "ModRef" }, },
219+
"attributes": "SideEffects", },
222220
"atomic_fmax" : { "result": "anyfloat",
223221
"arguments": [ "anyptr", "int", "int",
224222
"anyfloat"],
225-
"attributes": "None",
226-
"memory_effects":
227-
{ "access": "ModRef" }, },
223+
"attributes": "SideEffects", },
228224

229225
## ``llvm.vc.internal.rsqrtm`` : computes component-wise reciprocal square root
230226
## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -306,9 +302,7 @@
306302
"target" : [
307303
"hasLSCMessages",
308304
],
309-
"attributes": "None",
310-
"memory_effects":
311-
{ "access": "ModRef" }, },
305+
"attributes": "SideEffects", },
312306
"lsc_atomic_bss": { "result": "anyvector",
313307
"arguments": [
314308
"anyint", # vNxi1, predicate
@@ -327,9 +321,7 @@
327321
"target" : [
328322
"hasLSCMessages",
329323
],
330-
"attributes": "None",
331-
"memory_effects":
332-
{ "access": "ModRef" }, },
324+
"attributes": "SideEffects", },
333325
"lsc_atomic_slm": { "result": "anyvector",
334326
"arguments": [
335327
"anyint", # vNxi1, predicate
@@ -348,9 +340,7 @@
348340
"target" : [
349341
"hasLSCMessages",
350342
],
351-
"attributes": "None",
352-
"memory_effects":
353-
{ "access": "ModRef" }, },
343+
"attributes": "SideEffects", },
354344
"lsc_atomic_ugm": { "result": "anyvector",
355345
"arguments": [
356346
"anyint", # vNxi1, predicate
@@ -369,9 +359,7 @@
369359
"target" : [
370360
"hasLSCMessages",
371361
],
372-
"attributes": "None",
373-
"memory_effects":
374-
{ "access": "ModRef" }, },
362+
"attributes": "SideEffects", },
375363

376364
## ``llvm.vc.internal.lsc.load.*`` : LSC load intrinsics
377365
## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -861,7 +849,7 @@
861849
"anyint", # cache controls
862850
"char", # number of blocks
863851
"short", # block width
864-
"short", # block height
852+
"short", # block heigth
865853
"long", # memory base address
866854
"int", # memory matrix width (minus 1)
867855
"int", # memory matrix height (minus 1)
@@ -885,7 +873,7 @@
885873
"anyint", # cache controls
886874
"char", # number of blocks
887875
"short", # block width
888-
"short", # block height
876+
"short", # block heigth
889877
"long", # memory base address
890878
"int", # memory matrix width (minus 1)
891879
"int", # memory matrix height (minus 1)
@@ -909,7 +897,7 @@
909897
"anyint", # cache controls
910898
"char", # number of blocks
911899
"short", # block width
912-
"short", # block height
900+
"short", # block heigth
913901
"long", # memory base address
914902
"int", # memory matrix width (minus 1)
915903
"int", # memory matrix height (minus 1)
@@ -933,7 +921,7 @@
933921
"anyint", # cache controls
934922
"char", # number of blocks
935923
"short", # block width
936-
"short", # block height
924+
"short", # block heigth
937925
"long", # memory base address
938926
"int", # memory matrix width (minus 1)
939927
"int", # memory matrix height (minus 1)
@@ -954,7 +942,7 @@
954942
"anyint", # cache controls
955943
"char", # number of blocks
956944
"short", # block width
957-
"short", # block height
945+
"short", # block heigth
958946
"long", # memory base address
959947
"int", # memory matrix width (minus 1)
960948
"int", # memory matrix height (minus 1)
@@ -1336,7 +1324,7 @@
13361324
## * arg0: vNi1 Predicate (overloaded)
13371325
## * arg1: i16, Opcode [MBC]
13381326
## * arg2: i8, Channel mask [MBC]
1339-
## * arg3: i16, Address offset packed immediate (aoffimmi) [MBC]
1327+
## * arg3: i16, Address offset packed immediates (aoffimmi) [MBC]
13401328
## * arg4: i32, Surface BTI
13411329
## * arg5: vector to take values for masked simd lanes from
13421330
## * arg6: vNi32 or vNi16, first sampler message parameter (overloaded)
@@ -1619,9 +1607,7 @@
16191607
"target" : [
16201608
"!noLegacyDataport"
16211609
],
1622-
"attributes": "None",
1623-
"memory_effects":
1624-
{ "access": "ModRef" }, },
1610+
"attributes" : "SideEffects" },
16251611
"typed_atomic_sub_predef_surface" : { "result" : "anyvector",
16261612
"arguments" : [
16271613
"anyvector",
@@ -1635,9 +1621,7 @@
16351621
"target" : [
16361622
"!noLegacyDataport"
16371623
],
1638-
"attributes": "None",
1639-
"memory_effects":
1640-
{ "access": "ModRef" }, },
1624+
"attributes" : "SideEffects" },
16411625
"typed_atomic_min_predef_surface" : { "result" : "anyvector",
16421626
"arguments" : [
16431627
"anyvector",
@@ -1651,9 +1635,7 @@
16511635
"target" : [
16521636
"!noLegacyDataport"
16531637
],
1654-
"attributes": "None",
1655-
"memory_effects":
1656-
{ "access": "ModRef" }, },
1638+
"attributes" : "SideEffects" },
16571639
"typed_atomic_max_predef_surface" : { "result" : "anyvector",
16581640
"arguments" : [
16591641
"anyvector",
@@ -1667,9 +1649,7 @@
16671649
"target" : [
16681650
"!noLegacyDataport"
16691651
],
1670-
"attributes": "None",
1671-
"memory_effects":
1672-
{ "access": "ModRef" }, },
1652+
"attributes" : "SideEffects" },
16731653

16741654
"typed_atomic_xchg_predef_surface" : { "result" : "anyvector",
16751655
"arguments" : [
@@ -1684,9 +1664,7 @@
16841664
"target" : [
16851665
"!noLegacyDataport"
16861666
],
1687-
"attributes": "None",
1688-
"memory_effects":
1689-
{ "access": "ModRef" }, },
1667+
"attributes" : "SideEffects" },
16901668
"typed_atomic_and_predef_surface" : { "result" : "anyvector",
16911669
"arguments" : [
16921670
"anyvector",
@@ -1700,9 +1678,7 @@
17001678
"target" : [
17011679
"!noLegacyDataport"
17021680
],
1703-
"attributes": "None",
1704-
"memory_effects":
1705-
{ "access": "ModRef" }, },
1681+
"attributes" : "SideEffects" },
17061682
"typed_atomic_or_predef_surface" : { "result" : "anyvector",
17071683
"arguments" : [
17081684
"anyvector",
@@ -1716,9 +1692,7 @@
17161692
"target" : [
17171693
"!noLegacyDataport"
17181694
],
1719-
"attributes": "None",
1720-
"memory_effects":
1721-
{ "access": "ModRef" }, },
1695+
"attributes" : "SideEffects" },
17221696

17231697

17241698
"typed_atomic_xor_predef_surface" : { "result" : "anyvector",
@@ -1734,9 +1708,7 @@
17341708
"target" : [
17351709
"!noLegacyDataport"
17361710
],
1737-
"attributes": "None",
1738-
"memory_effects":
1739-
{ "access": "ModRef" }, },
1711+
"attributes" : "SideEffects" },
17401712
"typed_atomic_imin_predef_surface" : { "result" : "anyvector",
17411713
"arguments" : [
17421714
"anyvector",
@@ -1750,9 +1722,7 @@
17501722
"target" : [
17511723
"!noLegacyDataport"
17521724
],
1753-
"attributes": "None",
1754-
"memory_effects":
1755-
{ "access": "ModRef" }, },
1725+
"attributes" : "SideEffects" },
17561726
"typed_atomic_imax_predef_surface" : { "result" : "anyvector",
17571727
"arguments" : [
17581728
"anyvector",
@@ -1766,9 +1736,7 @@
17661736
"target" : [
17671737
"!noLegacyDataport"
17681738
],
1769-
"attributes": "None",
1770-
"memory_effects":
1771-
{ "access": "ModRef" }, },
1739+
"attributes" : "SideEffects" },
17721740

17731741
## ``llvm.vc.internal.typed.atomic.*.predef.surface.*`` : legacy atomic typed predefined surface
17741742
## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1798,9 +1766,7 @@
17981766
"target" : [
17991767
"!noLegacyDataport"
18001768
],
1801-
"attributes": "None",
1802-
"memory_effects":
1803-
{ "access": "ModRef" }, },
1769+
"attributes" : "SideEffects" },
18041770
"typed_atomic_dec_predef_surface" : { "result" : "anyvector",
18051771
"arguments" : [
18061772
"anyvector", # predicate
@@ -1813,9 +1779,7 @@
18131779
"target" : [
18141780
"!noLegacyDataport"
18151781
],
1816-
"attributes": "None",
1817-
"memory_effects":
1818-
{ "access": "ModRef" }, },
1782+
"attributes" : "SideEffects" },
18191783

18201784
## ``llvm.vc.internal.typed.atomic.*.predef.surface.cmpxchg.*`` : legacy atomic typed CMPXCHG predefined surface
18211785
## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1849,9 +1813,7 @@
18491813
"target" : [
18501814
"!noLegacyDataport"
18511815
],
1852-
"attributes": "None",
1853-
"memory_effects":
1854-
{ "access": "ModRef" }, },
1816+
"attributes" : "SideEffects" },
18551817

18561818
## ``llvm.vc.internal.gather4.typed.predef.surface.*`` : legacy cmask typed load predefined surface
18571819
## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -378,21 +378,6 @@ void GenXOCLRuntimeInfo::FunctionInfo::initInstructionLevelProperties(
378378
UsesDPAS = true;
379379
break;
380380
}
381-
382-
// a store intrinsic
383-
if (auto *CI = dyn_cast<CallInst>(&Inst);
384-
CI && !CI->doesNotAccessMemory() && !CI->onlyReadsMemory()) {
385-
// a store intrinsic has cache opt
386-
if (auto CacheOptsIndex =
387-
vc::InternalIntrinsic::getMemoryCacheControlOperandIndex(IID);
388-
CacheOptsIndex >= 0) {
389-
auto *CacheOpts = cast<Constant>(Inst.getOperand(CacheOptsIndex));
390-
auto *L1Opt = cast<ConstantInt>(CacheOpts->getAggregateElement(0u));
391-
HasLscStoresWithNonDefaultL1CacheControls |=
392-
static_cast<LSC_CACHE_OPT>(L1Opt->getZExtValue()) !=
393-
LSC_CACHING_DEFAULT;
394-
}
395-
}
396381
}
397382
}
398383

‎IGC/ocloc_tests/VC/HasLscStoresWithNonDefaultL1CacheControls/store.ll‎

Lines changed: 0 additions & 50 deletions
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