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[Autobackout][FuncReg]Revert of change: b4a533d
Optimization for udiv, urem, sdiv, srem if divisor is constant power of 2 value Optimization in VC PatternMatch, uses the same pattern as for i32 case
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IGC/VectorCompiler/lib/GenXCodeGen/GenXPatternMatch.cpp

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2824,7 +2824,10 @@ static DivRemOptimize isSuitableUDivURemOperand(Value *Operand) {
28242824
if (!isa<Constant>(Operand))
28252825
return DivRemOptimize::Not;
28262826
Type *OperandTy = Operand->getType();
2827-
if (!OperandTy->isIntOrIntVectorTy())
2827+
// TODO support i8, i16 & i64 cases
2828+
// for pow2 case just turning on the same pattern as i32 width
2829+
// Not int and not vector of int, or width wrong( not 32).
2830+
if (!OperandTy->isIntOrIntVectorTy(genx::DWordBits))
28282831
return DivRemOptimize::Not;
28292832
// TODO: Remove this as we have tests for this pattern.
28302833
if (PatternMatch::match(Operand, PatternMatch::m_Negative()))
@@ -2842,7 +2845,12 @@ static DivRemOptimize isSuitableSDivSRemOperand(Value *Operand) {
28422845
if (!isa<Constant>(Operand))
28432846
return DivRemOptimize::Not;
28442847
Type *OperandTy = Operand->getType();
2845-
if (!OperandTy->isIntOrIntVectorTy())
2848+
// TODO support i8, i16 & i64 cases
2849+
// i8, i16 - by creating zext/sext to i32
2850+
// i64 - just turning on the same pattern as i32 width,
2851+
// as emulation for shift and add much faster than emulation division.
2852+
// Not int and not vector of int, or width wrong( not 32).
2853+
if (!OperandTy->isIntOrIntVectorTy(genx::DWordBits))
28462854
return DivRemOptimize::Not;
28472855
if (PatternMatch::match(Operand, PatternMatch::m_Negative()))
28482856
return DivRemOptimize::Not;
@@ -2870,10 +2878,10 @@ static void decomposeSDivPow2(BinaryOperator &SDivOp) {
28702878
IGC_ASSERT(ElementTy);
28712879
unsigned ElementBitWidth = ElementTy->getIntegerBitWidth();
28722880

2873-
Constant *VecSignBit = Constant::getIntegerValue(
2874-
OperationTy, APInt{ElementBitWidth, ElementBitWidth - 1});
2875-
Constant *VecBitWidth = Constant::getIntegerValue(
2876-
OperationTy, APInt{ElementBitWidth, ElementBitWidth});
2881+
Constant *VecSignBit =
2882+
Constant::getIntegerValue(OperationTy, APInt{32, ElementBitWidth - 1});
2883+
Constant *VecBitWidth =
2884+
Constant::getIntegerValue(OperationTy, APInt{32, ElementBitWidth});
28772885

28782886
Constant *Log2Divisor = getFloorLog2(Divisor);
28792887
IGC_ASSERT(Log2Divisor != nullptr);
@@ -2965,13 +2973,10 @@ static void decomposeURemPow2(BinaryOperator &URemOp) {
29652973
DivRemOptimize::Pow2);
29662974
Constant *Divisor = cast<Constant>(URemOp.getOperand(1));
29672975
Type *OperationTy = Dividend->getType();
2968-
Type *ElementTy = OperationTy->getScalarType();
2969-
unsigned ElementBitWidth = ElementTy->getIntegerBitWidth();
29702976

29712977
IRBuilder<> Builder{&URemOp};
29722978

2973-
Constant *One =
2974-
Constant::getIntegerValue(OperationTy, APInt{ElementBitWidth, 1});
2979+
Constant *One = Constant::getIntegerValue(OperationTy, APInt{32, 1});
29752980
Value *Res = Builder.CreateAnd(Dividend, Builder.CreateSub(Divisor, One));
29762981
URemOp.replaceAllUsesWith(Res);
29772982
Res->takeName(&URemOp);

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