DVI-12bit timing

[bhansconnect]

This may not be a bug, but I don't think that the dvi 12bit example technically meets timing. If we look here we are running the pll output at 39.75 MHz. When the make file runs the nextpnr-ice40 it doesn't set the goal frequency, so it defaults to 12 Mhz.

If I edit the Makefile to include FREQ = 39.75. Then the build fails with:

icetime -c 39.75 -d up5k -mtr dvi-12bit.rpt dvi-12bit.asc
// Reading input .asc file..
// Reading 5k chipdb file..
// Creating timing netlist..
// Timing estimate: 30.09 ns (33.24 MHz)
// Checking 25.16 ns (39.75 MHz) clock constraint: FAILED.
make: *** [../main.mk:23: dvi-12bit.rpt] Error 1

I could be wrong, but I think that is how the tool should be setup. Am I correct about it not making timing?