arcv: fuse integer multiply-add instruction pairs

To make sure that the multiply-add pairs (split post-reload from the
madd_split instruction) are not broken up by the sched2 pass, designate
them as fusable in arcv_macro_fusion_pair_p ().

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>

Author: artemiy-volkov

gcc/config/riscv/arcv-rhx100.md

@@ -42,6 +42,11 @@
 		condmove,mvpair,zicond,cpop,clmul"))
   "((arcv_rhx100_issueA_fuse0 + arcv_rhx100_ALU_A_fuse0_early) | (arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse1_early)) | ((arcv_rhx100_issueB_fuse0 + arcv_rhx100_ALU_B_fuse0_early) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse1_early))")
 
+(define_insn_reservation "arcv_rhx100_imul_fused" 4
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "imul_fused"))
+  "(arcv_rhx100_issueA_fuse0 + arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse0_early + arcv_rhx100_ALU_A_fuse1_early + arcv_rhx100_MPY32), nothing*3")
+
 (define_insn_reservation "arcv_rhx100_jmp_insn" 1
   (and (eq_attr "tune" "arcv_rhx100")
        (eq_attr "type" "branch,jump,call,jalr,ret,trap"))

gcc/config/riscv/riscv.cc

@@ -11191,6 +11191,13 @@ arcv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
 	      && SET_DEST (prev_set) == SUBREG_REG (SET_SRC (curr_set)))))
     return true;
 
+  if (GET_CODE (SET_SRC (prev_set)) == MULT
+      && GET_CODE (SET_SRC (curr_set)) == PLUS
+      && REGNO (SET_DEST (prev_set)) == REGNO (SET_DEST (curr_set))
+      && (REGNO (SET_DEST (prev_set)) == REGNO (XEXP (SET_SRC (curr_set), 0))
+	|| REGNO (SET_DEST (prev_set)) == REGNO (XEXP (SET_SRC (curr_set), 1))))
+    return true;
+
   return false;
 }
 

gcc/config/riscv/riscv.md

@@ -518,7 +518,7 @@
    vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
    vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,
    vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,
-   vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,
+   vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,imul_fused,
    sf_vc,sf_vc_se"
   (cond [(eq_attr "got" "load") (const_string "load")
 
@@ -4528,7 +4528,7 @@
     rtx tmp0 = gen_reg_rtx (SImode), tmp1 = gen_reg_rtx (SImode);
     emit_insn (gen_zero_extendhisi2 (tmp0, operands[1]));
     emit_insn (gen_zero_extendhisi2 (tmp1, operands[2]));
-    emit_insn (gen_madd_split (operands[0], tmp0, tmp1, operands[3]));
+    emit_insn (gen_madd_split_fused (operands[0], tmp0, tmp1, operands[3]));
     DONE;
   }
 )
@@ -4542,31 +4542,26 @@
   "TARGET_XTHEADMAC"
 )
 
-(define_insn_and_split "madd_split"
+(define_insn "madd_split_fused"
   [(set (match_operand:SI 0 "register_operand" "=&r,r")
      (plus:SI
 	(mult:SI (match_operand:SI 1 "register_operand" "r,r")
 		 (match_operand:SI 2 "register_operand" "r,r"))
 	(match_operand:SI 3 "register_operand" "r,?0")))
     (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "riscv_is_micro_arch (rhx) && !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL)"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-  "{
+  "riscv_is_micro_arch (arcv_rhx100)
+   && !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL)"
+  {
      if (REGNO (operands[0]) == REGNO (operands[3]))
        {
-	 emit_insn (gen_mulsi3 (operands[4], operands[1], operands[2]));
-	 emit_insn (gen_addsi3 (operands[0], operands[3], operands[4]));
+	 return "mul\t%4,%1,%2\n\tadd\t%4,%3,%4\n\tmv\t%0,%4";
        }
      else
        {
-	 emit_insn (gen_mulsi3 (operands[0], operands[1], operands[2]));
-	 emit_insn (gen_addsi3 (operands[0], operands[0], operands[3]));
+	 return "mul\t%0,%1,%2\n\tadd\t%0,%0,%3";
        }
-    DONE;
-   }"
-  [(set_attr "type" "imul")]
+  }
+  [(set_attr "type" "imul_fused")]
 )
 
 ;; String compare with length insn.