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davidbiancolindavidbiancolin
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Fix FPGA-Level Simulation (#24)
* Fix FPGA-level RTL simulation by adding PLL synthesis * Include ILA files * Add a comment explaining why i've commented out functions in dma_common
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7 files changed

+39
-22
lines changed

7 files changed

+39
-22
lines changed

‎hdk/cl/developer_designs/cl_firesim/software/runtime/common_dma.c‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -163,22 +163,23 @@ int fpga_driver_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffe
163163
return rc;
164164
}
165165

166-
void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address) {
167-
#ifdef SV_TEST
168-
sv_fpga_start_cl_to_buffer(slot_id, channel, buffer_size, address);
169-
#else
170-
fpga_driver_read_cl_to_buffer(slot_id, channel, fd, buffer_size, address);
171-
#endif
172-
dma_memcmp(buffer_size);
173-
}
174-
175-
void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address){
176-
#ifdef SV_TEST
177-
sv_fpga_start_buffer_to_cl(slot_id, channel, buffer_size, write_buffer, address);
178-
#else
179-
fpga_driver_write_buffer_to_cl(slot_id, channel, fd, buffer_size, address);
180-
#endif
181-
}
166+
// Biancolin: We don't use these but their callouts to the SV task that implements them has changed.
167+
//void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address) {
168+
//#ifdef SV_TEST
169+
// sv_fpga_start_cl_to_buffer(slot_id, channel, buffer_size, address);
170+
//#else
171+
// fpga_driver_read_cl_to_buffer(slot_id, channel, fd, buffer_size, address);
172+
//#endif
173+
// dma_memcmp(buffer_size);
174+
//}
175+
//
176+
//void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address){
177+
//#ifdef SV_TEST
178+
// sv_fpga_start_buffer_to_cl(slot_id, channel, buffer_size, write_buffer, address);
179+
//#else
180+
// fpga_driver_write_buffer_to_cl(slot_id, channel, fd, buffer_size, address);
181+
//#endif
182+
//}
182183

183184
int dma_memcmp (size_t buffer_size) {
184185
int rc = 0;

‎hdk/cl/developer_designs/cl_firesim/software/runtime/common_dma.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,10 @@ int fpga_driver_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buff
5555

5656
int fpga_driver_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
5757

58-
void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
59-
60-
void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
58+
// Biancolin: We don't use these but their callouts to the SV task that implements them has changed.
59+
//void fpga_write_buffer_to_cl(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
60+
//
61+
//void fpga_read_cl_to_buffer(int slot_id, int channel, int fd, size_t buffer_size, size_t address);
6162

6263
int dma_example_hwsw_cosim(int slot_id);
6364

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,16 @@ export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim
5757
SV_TEST_LIST = test_firesim
5858
C_FILES = $(C_TEST_NAME) $(C_SDK_USR_UTILS_DIR)/sh_dpi_tasks.c $(C_COMMON_DIR)/src/fpga_pci_sv.c $(C_SRC_DIR)/common_dma.c
5959

60+
ELABORATED_IP_FILES = $(CL_ROOT)/ip/clk_wiz_0_firesim/clk_wiz_0_firesim_sim_netlist.v
61+
6062
ifeq ($(XCHK), 1)
6163
all: make_sim_dir compile_chk run
6264
else
6365
all: make_sim_dir compile run
6466
endif
6567

68+
$(CL_ROOT)/ip/clk_wiz_0_firesim/clk_wiz_0_firesim_sim_netlist.v:
69+
vivado -mode tcl -source synth_firesim_clk_wiz_sim.tcl -tclargs $(CL_ROOT)
70+
6671
include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc
6772

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile.vcs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@
2222
## 2. make all VCS=1 -> Runs the test
2323
##################################################################
2424

25-
compile: $(COMPLIB_DIR)
25+
compile: $(COMPLIB_DIR) $(ELABORATED_IP_FILES)
2626
mkdir -p $(SIM_DIR)
2727
cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup
2828
cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+DMA_TEST $(DEFINES) +lint=TFIPC-L
29-
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
29+
cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M -debug_access+nomemcbk+dmptf -debug_region+cell +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log
3030

3131
run:
3232

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile.vivado‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
## Makefile For Vivado compiles and simulations
1818
##################################################################
1919

20-
compile:
20+
compile: $(ELABORATED_IP_FILES)
2121
mkdir -p $(SIM_DIR)
2222
cd $(SIM_DIR) && xsc $(C_FILES) --additional_option "-I$(C_SDK_USR_INC_DIR)" --additional_option "-I$(C_SDK_USR_UTILS_DIR)" --additional_option "-I$(C_COMMON_DIR)/include" --additional_option "-I$(C_COMMON_DIR)/src" --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" --additional_option "-DSV_TEST" --additional_option "-DDMA_TEST"
2323
cd $(SIM_DIR) && xvlog --sv -m64 --define DMA_TEST --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/synth_firesim_clk_wiz_sim.tcl‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
set CL_DIR [lindex $argv 0]
2+
create_project -in_memory -part xcvu9p-flgb2104-2-i -force
3+
source $CL_DIR/design/cl_firesim_generated_env.tcl
4+
source $CL_DIR/build/scripts/synth_firesim_clk_wiz.tcl
5+
exit

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727

2828
-y ${CL_ROOT}/../common/design
2929
-y ${CL_ROOT}/design
30+
-y ${CL_ROOT}/design/ila_files
3031
-y ${CL_ROOT}/verif/sv
3132
-y ${SH_LIB_DIR}
3233
-y ${SH_INF_DIR}
@@ -37,6 +38,7 @@
3738

3839
+incdir+${CL_ROOT}/../common/design
3940
+incdir+${CL_ROOT}/design
41+
+incdir+${CL_ROOT}/design/ila_files
4042
+incdir+${CL_ROOT}/verif/sv
4143
+incdir+${SH_LIB_DIR}
4244
+incdir+${SH_INF_DIR}
@@ -76,6 +78,9 @@
7678
${CL_ROOT}/ip/axi_dwidth_converter_0/sim/axi_dwidth_converter_0.v
7779
${CL_ROOT}/ip/axi_dwidth_converter_0/hdl/axi_dwidth_converter_v2_1_vl_rfs.v
7880
${CL_ROOT}/ip/axi_dwidth_converter_0/hdl/axi_register_slice_v2_1_vl_rfs.v
81+
${CL_ROOT}/design/ila_files/firesim_ila_insert_inst.v
82+
${CL_ROOT}/design/ila_files/firesim_ila_insert_ports.v
83+
${CL_ROOT}/design/ila_files/firesim_ila_insert_wires.v
7984
${CL_ROOT}/design/cl_firesim_generated.sv
8085
${CL_ROOT}/design/cl_firesim_generated_defines.vh
8186
${CL_ROOT}/design/cl_firesim.sv

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