Merge pull request #13 from firesim/firesim-supernode-integration

Supernode Integration

Author: alonamid

hdk/cl/developer_designs/cl_firesim/build/constraints/cl_synth_user.xdc

@@ -4,3 +4,9 @@
 
 set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_0/incomingPCISdat/BRAMQueue/fq/ram_reg]
 set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_0/outgoingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_1/incomingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_1/incomingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_2/incomingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_2/outgoingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_3/outgoingPCISdat/BRAMQueue/fq/ram_reg]
+set_property RAM_STYLE ULTRA [get_cells firesim_top/top/SimpleNICWidget_3/outgoingPCISdat/BRAMQueue/fq/ram_reg]

hdk/cl/developer_designs/cl_firesim/build/scripts/encrypt.tcl

@@ -35,6 +35,7 @@ if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
 
 ## Change file names and paths below to reflect your CL area.  DO NOT include AWS RTL files.
 file copy -force $CL_DIR/design/cl_firesim_defines.vh                 $TARGET_DIR
+file copy -force $CL_DIR/design/cl_firesim_generated_defines.vh       $TARGET_DIR
 file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_inst.v   $TARGET_DIR
 file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_ports.v  $TARGET_DIR
 file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_wires.v  $TARGET_DIR

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

@@ -48,6 +48,11 @@ read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
+  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv  \
+  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv  \
   $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
 ]
 
@@ -67,6 +72,7 @@ read_ip [ list \
   $HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
   $HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
   $HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci \
+  $HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \
   $CL_DIR/ip/axi_clock_converter_dramslim/axi_clock_converter_dramslim.xci \
   $CL_DIR/ip/axi_clock_converter_oclnew/axi_clock_converter_oclnew.xci \
   $CL_DIR/ip/axi_clock_converter_512_wide/axi_clock_converter_512_wide.xci \
@@ -76,10 +82,12 @@ read_ip [ list \
 ]
 
 # Additional IP's that might be needed if using the DDR
-#read_bd [ list \
-# $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci \
-# $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
-#]
+read_ip [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci 
+]
+read_bd [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
+]
 
 puts "AWS FPGA: Reading AWS constraints";