Merge pull request #11 from firesim/auto-ila

Auto-ILA

Author: sagark

hdk/cl/developer_designs/cl_firesim/build/scripts/encrypt.tcl

@@ -35,6 +35,9 @@ if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
 
 ## Change file names and paths below to reflect your CL area.  DO NOT include AWS RTL files.
 file copy -force $CL_DIR/design/cl_firesim_defines.vh                 $TARGET_DIR
+file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_inst.v   $TARGET_DIR
+file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_ports.v  $TARGET_DIR
+file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_wires.v  $TARGET_DIR
 file copy -force $CL_DIR/design/cl_id_defines.vh                      $TARGET_DIR
 file copy -force $CL_DIR/design/cl_firesim.sv                         $TARGET_DIR 
 file copy -force $CL_DIR/design/cl_firesim_generated.sv               $TARGET_DIR 

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

@@ -1,3 +1,12 @@
+########################################
+## Generate ILA based on Recipe 
+########################################
+
+puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling firesim_ila_insert_vivado.tcl to generate ILAs from developer's specified recipe.";
+
+source $CL_DIR/design/ila_files/firesim_ila_insert_vivado.tcl
+
+
 #Param needed to avoid clock name collisions
 set_param sta.enableAutoGenClkNamePersistence 0
 set CL_MODULE $CL_MODULE
@@ -62,7 +71,8 @@ read_ip [ list \
   $CL_DIR/ip/axi_clock_converter_oclnew/axi_clock_converter_oclnew.xci \
   $CL_DIR/ip/axi_clock_converter_512_wide/axi_clock_converter_512_wide.xci \
   $CL_DIR/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci \
-  $CL_DIR/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.xci
+  $CL_DIR/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.xci \
+  $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci
 ]
 
 # Additional IP's that might be needed if using the DDR

hdk/cl/developer_designs/cl_firesim/design/cl_firesim.sv

@@ -414,6 +414,8 @@ wire fsimtop_s_axi_rlast;
 wire fsimtop_s_axi_rvalid;
 wire fsimtop_s_axi_rready;
 
+`include "firesim_ila_insert_wires.v"
+
   F1Shim firesim_top (
    .clock(firesim_internal_clock),
    .reset(!rst_firesim_n_sync),
@@ -510,6 +512,8 @@ wire fsimtop_s_axi_rready;
    .io_dma_r_bits_id(cl_sh_dma_pcis_rid_FIRESIM),
    .io_dma_r_bits_user(),    // UNUSED at top level
 
+   `include "firesim_ila_insert_ports.v"
+
    .io_slave_aw_ready(fsimtop_s_axi_awready),
    .io_slave_aw_valid(fsimtop_s_axi_awvalid),
    .io_slave_aw_bits_addr(fsimtop_s_axi_awaddr_small),
@@ -862,6 +866,8 @@ assign zeroila = 64'b0;
                    .probe5 (zeroila)
                    );
 
+`include "firesim_ila_insert_inst.v"
+
 // Debug Bridge 
  cl_debug_bridge CL_DEBUG_BRIDGE (
       .clk(clk_main_a0),

hdk/cl/developer_designs/cl_firesim/design/ila_files/firesim_ila_insert_inst.v

@@ -0,0 +1,12 @@
+create_project managed_ip_project $CL_DIR/ip/firesim_ila_ip/managed_ip_project -part xcvu9p-flgb2104-2-i -ip
+set_property simulator_language Verilog [current_project]
+set_property target_simulator XSim [current_project]
+create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_firesim_0 -dir $CL_DIR/ip/firesim_ila_ip
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE0_MU_CNT {3} CONFIG.C_NUM_OF_PROBES {1} CONFIG.C_TRIGOUT_EN {false} CONFIG.C_EN_STRG_QUAL {1} CONFIG.C_ADV_TRIGGER {true} CONFIG.C_TRIGIN_EN {false} CONFIG.ALL_PROBE_SAME_MU_CNT {3} ] [get_ips ila_firesim_0]
+generate_target {instantiation_template} [get_files $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci]
+generate_target all [get_files  $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci]
+export_ip_user_files -of_objects [get_files $CL_DIR/ip/firesim_ila_ip/ila_0/ila_firesim_0.xci] -no_script -sync -force -quiet
+create_ip_run [get_files -of_objects [get_fileset sources_1] $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci]
+launch_runs -jobs 8 ila_firesim_0_synth_1
+wait_on_run ila_firesim_0_synth_1
+export_simulation -of_objects [get_files $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci] -directory $CL_DIR/ip/firesim_ila_ip/ip_user_files/sim_scripts -ip_user_files_dir $CL_DIR/ip/firesim_ila_ip/ip_user_files -ipstatic_source_dir $CL_DIR/ip/firesim_ila_ip/ip_user_files/ipstatic -lib_map_path [list {modelsim=$CL_DIR/ip/firesim_ila_ip/managed_ip_project/managed_ip_project.cache/compile_simlib/modelsim} {questa=$CL_DIR/ip/firesim_ila_ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa} {ies=$CL_DIR/ip/firesim_ila_ip/managed_ip_project/managed_ip_project.cache/compile_simlib/ies} {vcs=$CL_DIR/ip/firesim_ila_ip/managed_ip_project/managed_ip_project.cache/compile_simlib/vcs} {riviera=$CL_DIR/ip/firesim_ila_ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet

hdk/cl/developer_designs/cl_firesim/design/ila_files/firesim_ila_insert_ports.v

@@ -27,6 +27,7 @@
 
 -sourcelibdir ${CL_ROOT}/../common/design
 -sourcelibdir ${CL_ROOT}/design
+-sourcelibdir ${CL_ROOT}/design/ila_files
 -sourcelibdir ${CL_ROOT}/verif/sv
 -sourcelibdir ${SH_LIB_DIR}
 -sourcelibdir ${SH_INF_DIR}
@@ -36,6 +37,7 @@
 
 -include ${CL_ROOT}/../common/design
 -include ${CL_ROOT}/verif/sv
+-include ${CL_ROOT}/design/ila_files
 -include ${SH_LIB_DIR}
 -include ${SH_INF_DIR}
 -include ${SH_SH_DIR}
@@ -49,6 +51,9 @@
 
 ${CL_ROOT}/../common/design/cl_common_defines.vh
 ${CL_ROOT}/design/cl_firesim_defines.vh
+${CL_ROOT}/design/ila_files/firesim_ila_insert_inst.v
+${CL_ROOT}/design/ila_files/firesim_ila_insert_ports.v
+${CL_ROOT}/design/ila_files/firesim_ila_insert_wires.v
 ${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v
 ${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v
 ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/sim/bd_a493.v