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sagarksagark
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update cl_firesim with changes required by upstream aws-fpga 1.4.6
1 parent 8408bdc commit e55961e

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6 files changed

+17
-17
lines changed

6 files changed

+17
-17
lines changed

‎hdk/cl/developer_designs/cl_firesim/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
3737
set clock_recipe_c [lindex $argv 10]
3838
set uram_option [lindex $argv 11]
3939
set notify_via_sns [lindex $argv 12]
40-
40+
set VDEFINES [lindex $argv 13]
4141
##################################################
4242
## Flow control variables
4343
##################################################
@@ -135,6 +135,8 @@ set_msg_config -id {Synth 8-3332} -suppress
135135
set_msg_config -id {Synth 8-350} -suppress
136136
set_msg_config -id {Synth 8-3848} -suppress
137137
set_msg_config -id {Synth 8-3917} -suppress
138+
set_msg_config -id {Opt 31-430} -suppress
139+
# TODO: Sagar: where did the rest of these come from?
138140
set_msg_config -id {Synth 8-6014} -suppress
139141
set_msg_config -id {Vivado 12-1580} -suppress
140142
set_msg_config -id {Constraints 18-619} -suppress
@@ -202,7 +204,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_
202204

203205
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
204206
#################################################################
205-
##### Do not remove this setting. Need to workaround bug in 2017.4
207+
##### Do not remove this setting. Need to workaround bug
206208
##################################################################
207209
set_param hd.clockRoutingWireReduction false
208210

@@ -261,6 +263,7 @@ if {$implement} {
261263
########################
262264
# CL Optimize
263265
########################
266+
set place_preHookTcl ""
264267
if {$opt} {
265268
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
266269
impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
@@ -345,18 +348,10 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for
345348
set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
346349
set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
347350
set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
348-
set vivado_version [version -short]
349-
set ver_2017_4 2017.4
351+
set vivado_version [string range [version -short] 0 5]
350352
puts "vivado_version is $vivado_version\n"
351353

352-
if { [string first $ver_2017_4 $vivado_version] == 0 } {
353354
puts $manifest_file "manifest_format_version=2\n"
354-
#puts "in 2017.4"
355-
} else {
356-
puts $manifest_file "manifest_format_version=1\n"
357-
#puts "in 2017.1"
358-
}
359-
360355
puts $manifest_file "pci_vendor_id=$vendor_id\n"
361356
puts $manifest_file "pci_device_id=$device_id\n"
362357
puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
@@ -365,9 +360,7 @@ puts $manifest_file "dcp_hash=$hash\n"
365360
puts $manifest_file "shell_version=$shell_version\n"
366361
puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
367362
puts $manifest_file "hdk_version=$hdk_version\n"
368-
if { [string first $ver_2017_4 $vivado_version] == 0} {
369-
puts $manifest_file "tool_version=v2017.4\n"
370-
}
363+
puts $manifest_file "tool_version=v$vivado_version\n"
371364
puts $manifest_file "date=$timestamp\n"
372365
puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
373366
puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"

‎hdk/cl/developer_designs/cl_firesim/build/scripts/encrypt.tcl‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,7 @@ file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DI
6262
exec chmod +w {*}[glob $TARGET_DIR/*]
6363

6464
set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
65-
set vivado_version [version -short]
66-
set ver_2017_4 2017.4
65+
set vivado_version [string range [version -short] 0 5]
6766
puts "AWS FPGA: VIVADO_TOOL_VERSION $TOOL_VERSION"
6867
puts "vivado_version $vivado_version"
6968

‎hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ source $CL_DIR/design/ila_files/firesim_ila_insert_vivado.tcl
1010
#Param needed to avoid clock name collisions
1111
set_param sta.enableAutoGenClkNamePersistence 0
1212
set CL_MODULE $CL_MODULE
13+
set VDEFINES $VDEFINES
1314

1415
create_project -in_memory -part [DEVICE_TYPE] -force
1516

@@ -114,7 +115,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
114115

115116
update_compile_order -fileset sources_1
116117
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
117-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
118+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
118119

119120
set failval [catch {exec grep "FAIL" failfast.csv}]
120121
if { $failval==0 } {

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,11 @@
1313
# implied. See the License for the specific language governing permissions and
1414
# limitations under the License.
1515

16+
ifndef VIVADO_TOOL_VERSION
17+
$(error Environment variable VIVADO_TOOL_VERSION not set. please source hdk_setup.sh)
18+
else
19+
$(info VIVADO_TOOL_VERSION = $(VIVADO_TOOL_VERSION))
20+
endif
1621

1722
export TEST ?= test_null
1823
export C_TEST ?= test_null

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
6262
${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v
6363
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v
6464
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
65+
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
6566
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
6667
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
6768
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vivado.f‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@
7373
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
7474
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
7575
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
76+
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v
7677
${HDK_SHELL_DESIGN_DIR}/ip/cl_axi_interconnect/sim/cl_axi_interconnect.v
7778
${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
7879
${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v

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