Merge pull request #9 from firesim/dev

Bump to AWS 1.4.0 Shell

Author: sagark

.gitignore

@@ -34,8 +34,13 @@ waves.shm
 *.so
 *.a
 *.ko
+fio
 
-!SDAccel/aws_platform/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/libxilinxopencl.so
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/sw/lib/x86_64/libxilinxopencl.so
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr_4_0/sw/lib/x86_64/libxilinxopencl.so
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1_4ddr-xpr-2pr-debug_4_0/sw/lib/x86_64/libxilinxopencl.so
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so 
+!SDAccel/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so
 
 nohup.out
 *.nohup.out
@@ -100,3 +105,5 @@ vivado*.log
 
 # Patches
 patches/*
+
+awsver.txt

.gitmodules

@@ -1,4 +1,4 @@
-[submodule "SDAccel/examples/xilinx"]
-	path = SDAccel/examples/xilinx
+[submodule "SDAccel/examples/xilinx_2017.4"]
+	path = SDAccel/examples/xilinx_2017.4
 	url = https://github.com/Xilinx/SDAccel_Examples.git
-	branch = 2017.1
+	branch = aws_2017.4

ERRATA.md

@@ -1,30 +1,9 @@
 
 # AWS EC2 FPGA HDK+SDK Errata
 
+## Shell (04261818)
+[Shell_04261818_Errata](./hdk/docs/AWS_Shell_ERRATA.md)
 
-## Release 1.3.X
-### Implementation Restrictions
-*    PCIE AXI4 interfaces between Custom Logic(CL) and Shell(SH) have following restrictions:
-    *    All PCIe transactions must adhere to the PCIe Express base spec
-    *    4Kbyte Address boundary for all transactions(PCIe restriction)
-    *    Multiple outstanding outbound PCIe Read transactions with same ID not supported
-    *    PCIE extended tag not supported, so read-request is limited to 32 outstanding
-    *    Address must match DoubleWord(DW) address of the transaction
-    *    WSTRB(write strobe) must reflect appropriate valid bytes for AXI write beats
-    *    Only Increment burst type is supported
-    *    AXI lock, memory type, protection type, Quality of service and Region identifier are not supported
-    *    Transactions from the Shell to CL must complete within the timeout period to avoid transaction termination by the Shell
-    *    DMA transactions from the Shell to CL must complete within the timeout period to avoid transaction termination and invalid data returned for the DMA transaction
-
-## Unsupported Features (Planned for future releases)
-* FPGA to FPGA communication over PCIe for F1.16xl
-* FPGA to FPGA over the 400Gbps Ring for F1.16xl
-* Aurora and Reliable Aurora modules for the FPGA-to-FPGA 
-* Preserving the DRAM content between different AFI loads (by the same running instance)
-* Cadence Xcelium simulations tools
-* PCIM and DMA-PCIS AXI-4 interfaces do not support AxSIZE other than 3'b110 (64B)
-
-## Known Bugs/Issues
-* F1 CL designs using the v1.3 Shell must treat all clocks within the same group as asynchronous.  For example:  If using clk_main_a1, clk_extra_a1, clk_extra_a2, and clk_extra_a3 they need to be asynchronous.  See [AWS Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md)
-* The API fpga-load-local-image, has a bug in the error messaging which does not indicate a PCI ID mismatch occurred.  The PCI ID’s listed in the AFI manifest when an AFI is submitted to the CreateFpgaImage api (Vendor ID, Device ID, SubSystem ID, or SubSystem Vendor ID) should match the actual values in the submitted DCP. If there is a mismatch between the manifest IDs and the actual device ID, calling fpga-load-local-image on the AFI should report back load-failed (error 7), with a sub-error indicating there is a device ID mismatch. However, fpga-load-local-image does not report the sub-error, leaving no description as to why the load has failed.  Until this issue has been fixed, if you experience an AFI load-failed when loading the AFI,  double check the device IDs in the submitted manifest match the device IDs in the DCP.
+## HDK
 
+## SDK

FAQs.md

@@ -49,13 +49,23 @@ A: There are 2 vivado project files:
 A: 
 1. Verify hw_emu works as expected.  Using less data in hw_emu
 1. Add assert where run fails and check same conditions for hw_emu
-1. See "Chapter 8 - Debugging Applications in the SDAccel Environment" in [latest SDAccel Environment User Guide]
+1. See "Chapter 4 - Debugging Applications in the SDAccel Environment" in [latest SDAccel Environment User Guide]
 
 ## Q: Bitstream creation fails to create design less that 60 MHz?
 A: SDAccel flow does not allow clocks running less that 60 MHz kernel clock, therefore, you will need to debug further using [HLS Debug suggestions](./docs/SDAccel_HLS_Debug.md)
 
-## Q: Using the .xcp file generated from xocc results in an error?
-A: Directly using the .xcp file without conversion to .xclbin file will result in an error - Error: ... invalid binary.  See [Instructions on how to create AFI and subsequent execution process](./README.md#createafi)
+## Q: Using the .dcp file generated from xocc results in an error?
+A: Directly using the .dcp file without conversion to .xclbin file will result in an error - Error: ... invalid binary.  See [Instructions on how to create AFI and subsequent execution process](./README.md#createafi)
+
+## Q: Debugging using gdb in SDX gui is not working? 
+A: Please make sure you executed the following commands before launching SDX gui.
+  1.	mv /usr/local/Modules/init init.bak
+  2.	unset –f switchml
+  3.	unset –f _moduleraw
+  4.	unset –f module
+  
+## Q: How do I debug error: `No current synthesis run set`? 
+A: You may have run the previous [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_Setup.md) and created a `Vivado_init.tcl` file in `~/.Xilinx/Vivado`. It is recommended to remove it before switching from hardware development flow to SDAccel. 
 
 # Additional Resources
 
@@ -69,21 +79,21 @@ Links pointing to **latest** version of the user guides
    * [UG1207: SDAccel Environment Optimization Guide][latest SDAccel Environment Optimization Guide]
    * [UG949: UltraFast Design Methodology Guide for the Vivado Design Suite][latest UG949]
 
-Links pointing to **2017.1** version of the user guides
-   * [UG1023: SDAccel Environment User Guide][UG1023 2017.1]
-   * [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.1]
-   * [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.1]
-   * [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.1]
+Links pointing to **2017.4** version of the user guides
+   * [UG1023: SDAccel Environment User Guide][UG1023 2017.4]
+   * [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4]
+   * [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4]
+   * [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4]
    * [SDAccel_landing_page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html)
    * [Vivado HLS landing page](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
    * [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html)
    * [SDAccel Environment User Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1023-sdaccel-user-guide.pdf)
    * [SDAccel Intro Tutorial](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1021-sdaccel-intro-tutorial.pdf)
    * [SDAccel Environment Optimization Guide](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1207-sdaccel-optimization-guide.pdf)
    * [Vivado Design Methodology](https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf)
-   * [2017.1 SDAccel User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1023-sdaccel-user-guide.pdf)
-   * [2017.1 SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1021-sdaccel-intro-tutorial.pdf)
-   * [2017.1 SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1207-sdaccel-optimization-guide.pdf)
+   * [2017.4 SDAccel User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf)
+   * [2017.4 SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf)
+   * [2017.4 SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf)
    * [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation)
    * [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples)
    * [AWS SDAccel Readme](README.md)