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<td width="60%" colspan="1" align="center" valign="bottom" class="table_data"><b>US 5,784,584 C1 (6943rd)</b></td>
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<td colspan="1" class="table_data"><b>HIGH PERFORMANCE MICROPROCESSOR USING INSTRUCTIONS THAT OPERATE WITHIN INSTRUCTION GROUPS</b></td>
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<td colspan="3" class="table_data"><b>Charles H. Moore, Woodside, Calif., and Russell H. Fish, III, Mt. View, Calif., assignors to Technology Properties Limited, San Jose, Calif.</b></td>
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<td colspan="3" class="table_data"><b>Reexamination Request Nos. 90/008,299, Oct. 19, 2006 and 90/008,225, Nov. 15, 2006.</b></td>
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<td colspan="3" class="table_data"><b>Reexamination Certificate for Patent 5,784,584, issued Jul. 21, 1998, Appl. No. 484,935, Jun. 7, 1995.</b></td>
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<td colspan="3" class="table_data"><b>Division of application No. 07/389,334, filed on Aug. 3, 1989, now Pat. No. 5,440,749.</b></td>
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<td colspan="3" class="table_data"><b>Int. Cl. G06F <i>9/30;12/08;7/78;9/32;7/48</i></b> (2006.01)</td>
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<td class="table_data" align="left"><b>U.S. Cl. </b><b>712—200 </b></td>
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<center><img src="584.gif" alt="OG exemplary drawing"></center>
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<td class="table_data" align="left">AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT: </td>
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<td class="table_data" align="left">Claim <b>29</b> is determined to be patentable as amended. </td>
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<td class="table_data" align="left">Claims <b>1</b>-<b>28</b> were not reexamined. </td>
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<td valign="top" class="para_text"><b>29</b>. In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and <i>literal </i> operands from said memory to said central processing unit comprising the steps of: <div class="claim_text">providing instruction groups to said instruction register from said memory<i>; </div>
<div class="claim_text"><i>wherein said instruction register is connected to circuits that decode instructions; </i> </div>
<div class="claim_text"><i>wherein each of said instruction groups is structured to comprise a set of locations, including a first location, that contain either instructions or operands or both, said operands comprising either literal operands or variable</i>-<i>length address operands, and said instructions including opcode bits or both opcode bits and address selection bits but not including variable</i>-<i>length address operands; and further </i></i> </div>
<div class="claim_text">wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an <i>instruction, or to a literal </i>operand <b>[</b>or<b>]</b> <i>and </i>an instruction <b>[</b>or both<b>]</b>, said <i>accessed literal </i>operand or <i>said accessed </i>instruction being located at a predetermined position from a boundary of said instruction groups<i>, said accessed instruction positioned at only the first location of an instruction group</i>; </div>
<div class="claim_text">decoding said at least one instruction to determine <i>at least </i>said predetermined position <i>of said accessed instruction as only the first location of the set of locations of the instruction group containing said accessed instruction</i>; </div>
<div class="claim_text">locating <i>at least </i>said predetermined position; and </div>
<div class="claim_text">supplying <i>said accessed instruction, or said accessed literal operand and said accessed instruction</i>, from said instruction groups <i>to said central processing unit</i>, using <b>[</b>the<b>]</b> <i>at least said </i>predetermined <b>[</b>location, said operand or instruction or both to said central processing unit<b>]</b> <i>position</i>. </div>
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