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Merge pull request #1 from beebdev/v2.0
Changes include: -Replaced AXI-lite interface implementation -Using AXIS-FIFO and FIFO-AXIS adapters to transfer data to and from FIFO -Added Python testbench (cocotb) to verify behaviour of system -Added driver repo as submodule
2 parents 58ba6b7 + b12e447 commit c48bdfd

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.gitignore

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results.xml
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sim_build
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venv
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*dbg*

.gitmodules

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[submodule "ip_driver"]
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path = ip_driver
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url = git@github.com:beebdev/sw__haru.git

Makefile

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SIM ?= icarus
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TOPLEVEL_LANG ?= verilog
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ifneq ($(TOPLEVEL_LANG),verilog)
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all:
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@echo "Skipping; DTW accel does not support VHDL at the top-level"
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clean::
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else
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ifeq ($(SIM),icarus)
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COMPILE_ARGS+=-I$(PWD)/src/
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else
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COMPILE_ARGS+=+incdir+$(PWD)/src/
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endif
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#DUT
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VERILOG_SOURCES += $(PWD)/src/dtw_accel.v \
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$(PWD)/src/dtw_accel_M00_AXIS.v \
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$(PWD)/src/dtw_accel_S00_AXIS.v \
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$(PWD)/src/dtw_accel_S00_AXI.v \
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$(PWD)/src/dtw_core.v \
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$(PWD)/src/dtw_core_ref_mem.v \
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$(PWD)/src/dtw_core_datapath.v \
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$(PWD)/src/dtw_core_pe.v \
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$(PWD)/src/axi_lite_slave.v \
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$(PWD)/src/axis_2_fifo.v \
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$(PWD)/src/fifo.v \
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$(PWD)/src/fifo_2_axis.v \
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$(PWD)/src/dtw_core.v \
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$(PWD)/src/dtw_core_datapath.v \
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$(PWD)/src/dtw_core_ref_mem.v \
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$(PWD)/src/dtw_core_pe.v \
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# use VHDL_SOURCES for VHDL files
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#Test Bench
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VERILOG_SOURCES += $(PWD)/src/sim/tb_dtw_accel.v
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# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
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TOPLEVEL = dtw_accel
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TOPLEVEL = tb_dtw_accel
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GPI_IMPL := vpi
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# MODULE is the basename of the Python test file
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MODULE = test_dut
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# include cocotb's make rules to take care of the simulator setup
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include $(shell cocotb-config --makefiles)/Makefile.sim
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# TODO: Add waveform generation
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endif

README.md

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pip3 install cocotbext-axi
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```
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For icarus verilog, on mac:
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For icarus verilog:
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```
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# ubuntu
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sudo apt install iverilog
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# mac
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brew install icarus-verilog
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```
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Installing gtkwave:
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```
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# ubuntu
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sudo apt-get install gtkwave
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# mac
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brew install --cask gtkwave
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```
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# Running tests
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```
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source venv/bin/activate

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