arm: dts: fix adi,axi-pwmgen clocks

After backporting the dt-bindings fix from upstream, update the existing
.dts files that use adi,axi-pwmgen-2.00.a to use the corrected clocks
binding.

In the HDL, ASYNC_CLK_EN=1 by default, so most projects have a separate
external clock. The only exceptions are ad7606x, ad7616 and dc2677a,
which have ASYNC_CLK_EN=0 and therefore only one clock.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134.dts the wrong clock
was specified for the old binding so it will have a behavior change to
use the correct clock for the PWM clock rate now.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts, we also drop
the 0 in the phandle since #clock-cells = <0>; for &ref_clk.

Signed-off-by: David Lechner <dlechner@baylibre.com>

Author: dlech

arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10_nano_ad5791.dts

@@ -45,7 +45,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x00050000 0x1000>;
 		#pwm-cells = <3>;
-		clocks = <&spi_clk 0>;
+		clocks = <&sys_clk>, <&spi_clk 0>;
+		clock-names = "axi", "ext";
 	};
 
 	tx_dma: dma-controller@30000 {

arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit_dc2677a.dts

@@ -140,6 +140,7 @@
 					reg = <0x00040000 0x1000>;
 					#pwm-cells = <2>;
 					clocks = <&sys_clk>;
+					clock-names = "axi";
 				};
 
 				gpio: gpio@9000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7689-ardz.dts

@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7946.dts

@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7984.dts

@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4001.dts

@@ -53,7 +53,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4003.dts

@@ -53,7 +53,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-coraz7s-pulsar.dtsi

@@ -52,7 +52,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4000.dtsi

@@ -56,7 +56,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@0x44a00000 {

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts

@@ -72,8 +72,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
-
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {