dc2677a: Add VADJ value & build param in READMEs

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

projects/dc2677a/README.md

@@ -3,6 +3,7 @@
 - Evaluation board product page: [DC2677A](https://www.analog.com/dc2677a)
 - System documentation: https://wiki.analog.com/resources/eval/user-guides/dc2677a
 - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/dc2677a/index.html
+- Evaluation board VADJ range: 2.5V - 3.3V
 
 ## Supported parts
 
@@ -12,4 +13,4 @@
 
 ## Building the project
 
-Please enter the folder for the FPGA carrier you want to use and read the README.md.
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/dc2677a/c5soc/README.md

@@ -1,10 +1,33 @@
+<!-- no_no_os -->
+
 # DC2677A/C5SOC HDL Project
 
+- VADJ with which it was tested in hardware: 
+  - 2.5V - LVDS
+  - 3.3V - CMOS
+
 ## Building the project
 
+The parameter configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
+
 ```
 cd projects/dc2677a/c5soc
 make
 ```
 
-Corresponding device tree: [socfpga_cyclone5_sockit_dc2677a.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit_dc2677a.dts)
+The overwritable parameter from the environment:
+
+- LVDS_CMOS_N - specific to the type of the data and clock signals
+  - 0 - Single-ended data and clock signals (default)
+  - 1 - Differential data and clock signals
+### Example configurations
+
+#### Configuration using CMOS interface (default)
+
+This specific command is equivalent to running "make" only:
+
+```
+make LVDS_CMOS_N=0
+```
+
+Corresponding device tree: [socfpga_cyclone5_sockit_dc2677a.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit_dc2677a.dts)