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whitequarkwhitequark
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Follow RFC 43.
1 parent 8ebce9b commit e126924

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4 files changed

+26
-27
lines changed

4 files changed

+26
-27
lines changed

‎.github/workflows/main.yml‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,10 +23,9 @@ jobs:
2323
- 'pypy-3.10'
2424
# this version range needs to be synchronized with the one in pyproject.toml
2525
amaranth-version:
26-
- '0.4'
2726
- 'git'
2827
allow-failure:
29-
- false
28+
- false
3029
continue-on-error: '${{ matrix.allow-failure }}'
3130
name: 'test (${{ matrix.python-version }}, HDL ${{ matrix.amaranth-version }})'
3231
steps:

‎amaranth_stdio/serial.py‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -88,12 +88,12 @@ def __init__(self, *, divisor, divisor_bits=None, data_bits=8, parity="none"):
8888
self._parity = Parity(parity)
8989

9090
super().__init__({
91-
"divisor": In(unsigned(self._divisor_bits), reset=self._divisor),
91+
"divisor": In(unsigned(self._divisor_bits), init=self._divisor),
9292
"data": Out(unsigned(self._data_bits)),
9393
"err": Out(data.StructLayout({"overflow": 1, "frame": 1, "parity": 1})),
9494
"rdy": Out(unsigned(1)),
9595
"ack": In(unsigned(1)),
96-
"i": In(unsigned(1), reset=1),
96+
"i": In(unsigned(1), init=1),
9797
})
9898

9999
@classmethod
@@ -184,7 +184,7 @@ def elaborate(self, platform):
184184
bitno = Signal(range(len(shreg.as_value())))
185185

186186
if self._pins is not None:
187-
m.submodules += FFSynchronizer(self._pins.rx.i, self.i, reset=1)
187+
m.submodules += FFSynchronizer(self._pins.rx.i, self.i, init=1)
188188

189189
with m.FSM() as fsm:
190190
with m.State("IDLE"):
@@ -265,11 +265,11 @@ def __init__(self, *, divisor, divisor_bits=None, data_bits=8, parity="none"):
265265
self._parity = Parity(parity)
266266

267267
super().__init__({
268-
"divisor": In(unsigned(self._divisor_bits), reset=self._divisor),
268+
"divisor": In(unsigned(self._divisor_bits), init=self._divisor),
269269
"data": In(unsigned(self._data_bits)),
270270
"rdy": Out(unsigned(1)),
271271
"ack": In(unsigned(1)),
272-
"o": Out(unsigned(1), reset=1),
272+
"o": Out(unsigned(1), init=1),
273273
})
274274

275275
@classmethod
@@ -425,10 +425,10 @@ def __init__(self, *, divisor, divisor_bits=None, data_bits=8, parity="none"):
425425

426426
assert rx_sig.members["divisor"] == tx_sig.members["divisor"]
427427
divisor_shape = rx_sig.members["divisor"].shape
428-
divisor_reset = rx_sig.members["divisor"].reset
428+
divisor_init = rx_sig.members["divisor"].init
429429

430430
super().__init__({
431-
"divisor": In(divisor_shape, reset=divisor_reset),
431+
"divisor": In(divisor_shape, init=divisor_init),
432432
"rx": Out(rx_sig),
433433
"tx": Out(tx_sig),
434434
})
@@ -542,7 +542,7 @@ def elaborate(self, platform):
542542
]
543543

544544
if self._pins is not None:
545-
m.submodules += FFSynchronizer(self._pins.rx.i, self.rx.i, reset=1)
545+
m.submodules += FFSynchronizer(self._pins.rx.i, self.rx.i, init=1)
546546
m.d.comb += self._pins.tx.o.eq(self.tx.o)
547547

548548
connect(m, flipped(self.rx), rx)

‎pyproject.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ license = {file = "LICENSE.txt"}
1414
requires-python = "~=3.8"
1515
dependencies = [
1616
# this version requirement needs to be synchronized with the one in .github/workflows/main.yml
17-
"amaranth>=0.4,<0.5",
17+
"amaranth @ git+https://github.com/amaranth-lang/amaranth",
1818
]
1919

2020
[project.urls]

‎tests/test_serial.py‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ def simulation_test(dut, process):
2121

2222
class _DummyPins:
2323
def __init__(self):
24-
self.rx = Signal(StructLayout({"i": 1}), reset={"i": 1})
25-
self.tx = Signal(StructLayout({"o": 1}), reset={"o": 1})
24+
self.rx = Signal(StructLayout({"i": 1}), init={"i": 1})
25+
self.tx = Signal(StructLayout({"o": 1}), init={"o": 1})
2626

2727

2828
class AsyncSerialRXSignatureTestCase(TestCase):
@@ -33,12 +33,12 @@ def test_simple(self):
3333
self.assertEqual(sig.data_bits, 7)
3434
self.assertEqual(sig.parity, Parity.EVEN)
3535
self.assertEqual(sig.members, Signature({
36-
"divisor": In(unsigned(8), reset=10),
36+
"divisor": In(unsigned(8), init=10),
3737
"data": Out(unsigned(7)),
3838
"err": Out(StructLayout({"overflow": 1, "frame": 1, "parity": 1})),
3939
"rdy": Out(unsigned(1)),
4040
"ack": In(unsigned(1)),
41-
"i": In(unsigned(1), reset=1),
41+
"i": In(unsigned(1), init=1),
4242
}).members)
4343

4444
def test_defaults(self):
@@ -67,15 +67,15 @@ def test_eq(self):
6767
def test_repr(self):
6868
sig = AsyncSerialRX.Signature(divisor=10, divisor_bits=8, data_bits=7, parity="even")
6969
self.assertEqual(repr(sig), "AsyncSerialRX.Signature(SignatureMembers({"
70-
"'divisor': In(unsigned(8), reset=10), "
70+
"'divisor': In(unsigned(8), init=10), "
7171
"'data': Out(unsigned(7)), "
7272
"'err': Out(StructLayout({"
7373
"'overflow': 1, "
7474
"'frame': 1, "
7575
"'parity': 1})), "
7676
"'rdy': Out(unsigned(1)), "
7777
"'ack': In(unsigned(1)), "
78-
"'i': In(unsigned(1), reset=1)}))")
78+
"'i': In(unsigned(1), init=1)}))")
7979

8080
def test_wrong_divisor(self):
8181
with self.assertRaisesRegex(TypeError,
@@ -242,11 +242,11 @@ def test_simple(self):
242242
self.assertEqual(sig.data_bits, 7)
243243
self.assertEqual(sig.parity, Parity.EVEN)
244244
self.assertEqual(sig.members, Signature({
245-
"divisor": In(unsigned(8), reset=10),
245+
"divisor": In(unsigned(8), init=10),
246246
"data": In(unsigned(7)),
247247
"rdy": Out(unsigned(1)),
248248
"ack": In(unsigned(1)),
249-
"o": Out(unsigned(1), reset=1),
249+
"o": Out(unsigned(1), init=1),
250250
}).members)
251251

252252
def test_defaults(self):
@@ -275,11 +275,11 @@ def test_eq(self):
275275
def test_repr(self):
276276
sig = AsyncSerialTX.Signature(divisor=10, divisor_bits=8, data_bits=7, parity="even")
277277
self.assertEqual(repr(sig), "AsyncSerialTX.Signature(SignatureMembers({"
278-
"'divisor': In(unsigned(8), reset=10), "
278+
"'divisor': In(unsigned(8), init=10), "
279279
"'data': In(unsigned(7)), "
280280
"'rdy': Out(unsigned(1)), "
281281
"'ack': In(unsigned(1)), "
282-
"'o': Out(unsigned(1), reset=1)}))")
282+
"'o': Out(unsigned(1), init=1)}))")
283283

284284
def test_wrong_divisor(self):
285285
with self.assertRaisesRegex(TypeError,
@@ -420,7 +420,7 @@ def test_simple(self):
420420
self.assertEqual(sig.data_bits, 7)
421421
self.assertEqual(sig.parity, Parity.EVEN)
422422
self.assertEqual(sig.members, Signature({
423-
"divisor": In(unsigned(8), reset=10),
423+
"divisor": In(unsigned(8), init=10),
424424
"rx": Out(AsyncSerialRX.Signature(divisor=10, divisor_bits=8, data_bits=7, parity="even")),
425425
"tx": Out(AsyncSerialTX.Signature(divisor=10, divisor_bits=8, data_bits=7, parity="even")),
426426
}).members)
@@ -451,23 +451,23 @@ def test_eq(self):
451451
def test_repr(self):
452452
sig = AsyncSerial.Signature(divisor=10, divisor_bits=8, data_bits=7, parity="even")
453453
self.assertEqual(repr(sig), "AsyncSerial.Signature(SignatureMembers({"
454-
"'divisor': In(unsigned(8), reset=10), "
454+
"'divisor': In(unsigned(8), init=10), "
455455
"'rx': Out(AsyncSerialRX.Signature(SignatureMembers({"
456-
"'divisor': In(unsigned(8), reset=10), "
456+
"'divisor': In(unsigned(8), init=10), "
457457
"'data': Out(unsigned(7)), "
458458
"'err': Out(StructLayout({"
459459
"'overflow': 1, "
460460
"'frame': 1, "
461461
"'parity': 1})), "
462462
"'rdy': Out(unsigned(1)), "
463463
"'ack': In(unsigned(1)), "
464-
"'i': In(unsigned(1), reset=1)}))), "
464+
"'i': In(unsigned(1), init=1)}))), "
465465
"'tx': Out(AsyncSerialTX.Signature(SignatureMembers({"
466-
"'divisor': In(unsigned(8), reset=10), "
466+
"'divisor': In(unsigned(8), init=10), "
467467
"'data': In(unsigned(7)), "
468468
"'rdy': Out(unsigned(1)), "
469469
"'ack': In(unsigned(1)), "
470-
"'o': Out(unsigned(1), reset=1)})))}))")
470+
"'o': Out(unsigned(1), init=1)})))}))")
471471

472472
def test_wrong_divisor(self):
473473
with self.assertRaisesRegex(TypeError,

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