From ef35f0da77817da161e282ba9c0e91beb721d128 Mon Sep 17 00:00:00 2001 From: Brendan Dahl Date: Fri, 18 Sep 2026 22:16:47 +0000 Subject: [PATCH] [spec] Fix input shape for relaxed_dot_add `i32x4.relaxed_dot_i8x16_i7x16_add_s` (`0xFD 275`) takes `i8x16` source vectors (`I8 X 16`), not `i16x8` (`I16 X 8`), matching the `vextternop` syntax constraint `4 * N_1 = N_2 = 32`. --- .../wasm-3.0/5.3-binary.instructions.spectec | 2 +- specification/wasm-3.0/6.3-text.instructions.spectec | 2 +- .../wasm-latest/5.3-binary.instructions.spectec | 2 +- .../wasm-latest/6.3-text.instructions.spectec | 2 +- spectec/test-frontend/TEST.md | 4 ++-- spectec/test-latex/TEST.md | 4 ++-- spectec/test-middlend/TEST.md | 12 ++++++------ 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/specification/wasm-3.0/5.3-binary.instructions.spectec b/specification/wasm-3.0/5.3-binary.instructions.spectec index a08d138777..fb12236759 100644 --- a/specification/wasm-3.0/5.3-binary.instructions.spectec +++ b/specification/wasm-3.0/5.3-binary.instructions.spectec @@ -679,7 +679,7 @@ grammar Binstr/vec-extbin-i32x4 : instr = ... | ... grammar Binstr/vec-exttern-i32x4 : instr = ... - | 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S + | 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S | ... grammar Binstr/vec-un-i64x2 : instr = ... diff --git a/specification/wasm-3.0/6.3-text.instructions.spectec b/specification/wasm-3.0/6.3-text.instructions.spectec index 645eb8325f..1fbfeeb0e1 100644 --- a/specification/wasm-3.0/6.3-text.instructions.spectec +++ b/specification/wasm-3.0/6.3-text.instructions.spectec @@ -1003,7 +1003,7 @@ grammar Tplaininstr_(I)/vec-extbin-i64x2 : instr = ... | ... grammar Tplaininstr_(I)/vec-exttern-i32x4 : instr = ... - | "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S + | "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S ;; Expressions diff --git a/specification/wasm-latest/5.3-binary.instructions.spectec b/specification/wasm-latest/5.3-binary.instructions.spectec index a08d138777..fb12236759 100644 --- a/specification/wasm-latest/5.3-binary.instructions.spectec +++ b/specification/wasm-latest/5.3-binary.instructions.spectec @@ -679,7 +679,7 @@ grammar Binstr/vec-extbin-i32x4 : instr = ... | ... grammar Binstr/vec-exttern-i32x4 : instr = ... - | 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S + | 0xFD 275:Bu32 => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S | ... grammar Binstr/vec-un-i64x2 : instr = ... diff --git a/specification/wasm-latest/6.3-text.instructions.spectec b/specification/wasm-latest/6.3-text.instructions.spectec index 645eb8325f..1fbfeeb0e1 100644 --- a/specification/wasm-latest/6.3-text.instructions.spectec +++ b/specification/wasm-latest/6.3-text.instructions.spectec @@ -1003,7 +1003,7 @@ grammar Tplaininstr_(I)/vec-extbin-i64x2 : instr = ... | ... grammar Tplaininstr_(I)/vec-exttern-i32x4 : instr = ... - | "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I16 X `8) RELAXED_DOT_ADD S + | "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP (I32 X `4) (I8 X `16) RELAXED_DOT_ADD S ;; Expressions diff --git a/spectec/test-frontend/TEST.md b/spectec/test-frontend/TEST.md index f0e1305f06..ab0c63e545 100644 --- a/spectec/test-frontend/TEST.md +++ b/spectec/test-frontend/TEST.md @@ -9921,7 +9921,7 @@ grammar Binstr : instr ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67 prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72 - prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42 prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42 @@ -12081,7 +12081,7 @@ grammar Tplaininstr_(I : I) : instr ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec - prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec rec { diff --git a/spectec/test-latex/TEST.md b/spectec/test-latex/TEST.md index da6bab1f64..c8ffe3263f 100644 --- a/spectec/test-latex/TEST.md +++ b/spectec/test-latex/TEST.md @@ -12105,7 +12105,7 @@ $$ & & | & \mathtt{0xFD}~~189{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\ & & | & \mathtt{0xFD}~~190{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{low}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\ & & | & \mathtt{0xFD}~~191{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\ -& & | & \mathtt{0xFD}~~275{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\ +& & | & \mathtt{0xFD}~~275{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 8}}}{\mathsf{x}}{\mathsf{{\scriptstyle 16}}}} \\ & & | & \mathtt{0xFD}~~192{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{abs} \\ & & | & \mathtt{0xFD}~~193{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{neg} \\ & & | & \mathtt{0xFD}~~195{:}{\mathtt{u32}} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} \mathsf{all\_true} \\ @@ -13616,7 +13616,7 @@ $$ & & | & \mbox{‘\texttt{i64x2.extmul\_low\_i32x4\_u}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{low}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\ & & | & \mbox{‘\texttt{i64x2.extmul\_high\_i32x4\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\ & & | & \mbox{‘\texttt{i64x2.extmul\_high\_i32x4\_u}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 64}}}{\mathsf{x}}{\mathsf{{\scriptstyle 2}}} {.} {{\mathsf{extmul}}{\mathsf{\_}}{\mathsf{high}}{\mathsf{\_}}{\mathsf{u}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}}} \\ -& & | & \mbox{‘\texttt{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 16}}}{\mathsf{x}}{\mathsf{{\scriptstyle 8}}}} \\ +& & | & \mbox{‘\texttt{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}’} & \quad\Rightarrow\quad{} & {\mathsf{i{\scriptstyle 32}}}{\mathsf{x}}{\mathsf{{\scriptstyle 4}}} {.} {{\mathsf{relaxed\_dot\_add}}{\mathsf{\_}}{\mathsf{s}}}{\mathsf{\_}}{{\mathsf{i{\scriptstyle 8}}}{\mathsf{x}}{\mathsf{{\scriptstyle 16}}}} \\ \end{array} $$ diff --git a/spectec/test-middlend/TEST.md b/spectec/test-middlend/TEST.md index 844049f8dc..88ff0f1960 100644 --- a/spectec/test-middlend/TEST.md +++ b/spectec/test-middlend/TEST.md @@ -9444,7 +9444,7 @@ grammar Binstr : instr ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67 prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72 - prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42 prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42 @@ -11604,7 +11604,7 @@ grammar Tplaininstr_(I : I) : instr ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec - prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec rec { @@ -21355,7 +21355,7 @@ grammar Binstr : instr ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67 prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72 - prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42 prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42 @@ -23515,7 +23515,7 @@ grammar Tplaininstr_(I : I) : instr ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec - prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec rec { @@ -33508,7 +33508,7 @@ grammar Binstr : instr ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:678.5-678.67 prod {{0xFD} {`%`_u32(191,):Bu32}} => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:682.5-682.72 - prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod {{0xFD} {`%`_u32(275,):Bu32}} => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:686.5-686.42 prod {{0xFD} {`%`_u32(192,):Bu32}} => VUNOP_instr(`%X%`_shape(I64_lanetype, `%`_dim(2,)), ABS_vunop_) ;; ../../../../specification/wasm-latest/5.3-binary.instructions.spectec:687.5-687.42 @@ -35668,7 +35668,7 @@ grammar Tplaininstr_(I : I) : instr ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec prod "i64x2.extmul_high_i32x4_u" => VEXTBINOP_instr(`%`_ishape(`%X%`_shape(I64_lanetype, `%`_dim(2,)),), `%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), EXTMUL_vextbinop__(HIGH_half, U_sx)) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec - prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I16_lanetype, `%`_dim(8,)),), RELAXED_DOT_ADDS_vextternop__) + prod "i32x4.relaxed_dot_i8x16_i7x16_add_s" => VEXTTERNOP_instr(`%`_ishape(`%X%`_shape(I32_lanetype, `%`_dim(4,)),), `%`_ishape(`%X%`_shape(I8_lanetype, `%`_dim(16,)),), RELAXED_DOT_ADDS_vextternop__) ;; ../../../../specification/wasm-latest/6.3-text.instructions.spectec rec {