Skip to content

Vector/SIMD registers mixed with general purpose registers in MLIL and HLIL? #8373

Description

@jpenalbae

Version and Platform:

  • Binary Ninja Version: 5.4.9926-dev
  • Edition: Commercial
  • OS: macOS
  • OS Version: 26.5
  • CPU Architecture: M5 Max

Bug Description:
Looks like Vector/SIMD registers are somehow mixed on arm64 in the MLIL/HLIL view. The MLIL and HLIL shows that a movi v0 is writing to x0 register returned from a previous function call.

Image

Expected Behavior:
Create a separate temporary variable with the 0xaa assignment, or even simplify it by not showing the initial assignment, showing only the subsequent stp q0, q0, [dest] and display the final destinations as being assigned with 0xaa

Binary:
Cannot provide it, but this behavior should happen in many macOS system binaries.

Additional Information:
Feel free to change issue title to something more meaningful/accurate as I'm just trying to guess what is going on...

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions