diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index b8880717f..ae94a200f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -281,7 +281,7 @@ def write_defaults(self): self.lib.write(" default_input_pin_cap : 1.0 ;\n") self.lib.write(" default_inout_pin_cap : 1.0 ;\n") self.lib.write(" default_output_pin_cap : 0.0 ;\n") - self.lib.write(" default_max_transition : 0.5 ;\n") + self.lib.write(" default_max_transition : {} ;\n".format(OPTS.max_transition)) self.lib.write(" default_fanout_load : 1.0 ;\n") self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") @@ -484,7 +484,8 @@ def write_addr_bus(self, port): self.lib.write(" bus_type : addr; \n") self.lib.write(" direction : input; \n") self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000)) - self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) + max_transition = max(OPTS.max_transition, self.slews[-1]) + self.lib.write(" max_transition : {0};\n".format(max_transition)) self.lib.write(" pin(addr{0}[{1}:0])".format(port,self.sram.addr_size-1)) self.lib.write("{\n") @@ -499,7 +500,8 @@ def write_wmask_bus(self, port): self.lib.write(" bus_type : wmask; \n") self.lib.write(" direction : input; \n") self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"] / 1000)) - self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) + max_transition = max(OPTS.max_transition, self.slews[-1]) + self.lib.write(" max_transition : {0};\n".format(max_transition)) self.lib.write(" pin(wmask{0}[{1}:0])".format(port, self.sram.num_wmasks - 1)) self.lib.write("{\n") diff --git a/compiler/globals.py b/compiler/globals.py index 98d6007ab..156249989 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -544,6 +544,12 @@ def set_default_corner(): if (OPTS.slew_scales == ""): OPTS.slew_scales = [0.25, 1, 8] + # Lower bound for the max_transition emitted on input pins. A + # characterized slew range can be far tighter than the technology can + # actually drive, which produces a limit downstream STA rejects. + if (OPTS.max_transition == ""): + OPTS.max_transition = 0.5 + def import_tech(): """ Dynamically adds the tech directory to the path and imports it. """ diff --git a/compiler/options.py b/compiler/options.py index 229f7c3a1..15d5c16e4 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -43,6 +43,7 @@ class options(optparse.Values): process_corners = "" load_scales = "" slew_scales = "" + max_transition = "" # Size parameters must be specified by user in config file. # num_words = 0 diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index b3ef0e0a3..c237dc7b3 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_freepdk45){ bus_type : addr; direction : input; capacitance : 0.00020910000000000001; - max_transition : 0.04; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 34be4fe4e..88328de88 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_freepdk45){ bus_type : addr; direction : input; capacitance : 0.00020910000000000001; - max_transition : 0.04; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cca9c1ed6..ce56ff8dd 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_freepdk45){ bus_type : addr; direction : input; capacitance : 0.00020910000000000001; - max_transition : 0.04; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 260288929..78f8b8410 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_freepdk45){ bus_type : addr; direction : input; capacitance : 0.00020910000000000001; - max_transition : 0.04; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 5817211b2..90ff2449e 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -165,7 +165,7 @@ cell (sram_2_16_1_freepdk45){ bus_type : addr; direction : input; capacitance : 0.2091; - max_transition : 0.04; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 6912aec73..850e3e99e 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_scn4m_subm){ bus_type : addr; direction : input; capacitance : 0.0098242; - max_transition : 0.4; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index a7605cb36..5762fa8ee 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_scn4m_subm){ bus_type : addr; direction : input; capacitance : 0.0098242; - max_transition : 0.4; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 8bec74c37..909fd826d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_scn4m_subm){ bus_type : addr; direction : input; capacitance : 0.0098242; - max_transition : 0.4; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 8bec74c37..909fd826d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -177,7 +177,7 @@ cell (sram_2_16_1_scn4m_subm){ bus_type : addr; direction : input; capacitance : 0.0098242; - max_transition : 0.4; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 7b649d0dd..fd2967874 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -165,7 +165,7 @@ cell (sram_2_16_1_scn4m_subm){ bus_type : addr; direction : input; capacitance : 9.8242; - max_transition : 0.4; + max_transition : 0.5; pin(addr0[3:0]){ timing(){ timing_type : setup_rising;