Gnerating a ROM with 6*1 works but 4*1 does not

[philiprbrenan]

I am able to create a ROM of 48 bits as 6 x 1 byte words:

python3 /opt/OpenRAM/rom_compiler.py RomPrimes.py 
|==============================================================================|
|=========                      OpenRAM v1.2.49                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 09/03/2026 17:20:22
Output files are: 
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.sp
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.v
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.lef
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.gds
create rom of word size 1 with 6 num of words
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
WARNING: file hierarchy_layout.py: line 976: Pins don't align well so copying pins instead of connecting with pin.
** Submodules: 0.3 seconds
** Placement: 0.0 seconds
** Routing: 5.0 seconds
ERROR: file magic.py: line 385: RomPrimes       LVS mismatch (results in /tmp/openram_phil_591_temp/RomPrimes.lvs.report)
** Verification: 5.1 seconds
** ROM creation: 10.5 seconds
SP: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.sp
** Spice writing: 0.0 seconds
GDS: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.gds
** GDS: 0.0 seconds
LEF: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.lef
** LEF: 0.0 seconds
LVS: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.lvs.sp
** LVS writing: 0.0 seconds
Config: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.py
** Config: 0.0 seconds
Verilog: Writing to /home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.v
** Verilog: 0.0 seconds
** End: 10.5 seconds

However, when trying to create a similar ROM with only 32 bits as 4 x 1, I get the following traceback:

phil@dd1720f73050:~/btreeList/verilog/tests/RomPrimes$ python3 /opt/OpenRAM/rom_compiler.py RomPrimes.py 
|==============================================================================|
|=========                      OpenRAM v1.2.49                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 09/03/2026 17:20:49
Output files are: 
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.sp
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.v
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.lef
/home/phil/btreeList/verilog/tests/RomPrimes/macro/RomPrimes/RomPrimes.gds
create rom of word size 1 with 4 num of words
Traceback (most recent call last):
  File "/opt/OpenRAM/rom_compiler.py", line 65, in <module>
    r = rom()
  File "/opt/OpenRAM/compiler/rom.py", line 52, in __init__
    self.r.create_netlist()
  File "/opt/OpenRAM/compiler/modules/rom_bank.py", line 68, in create_netlist
    self.add_modules()
  File "/opt/OpenRAM/compiler/modules/rom_bank.py", line 210, in add_modules
    self.column_decode = factory.create(module_name="rom_column_decode",
  File "/opt/OpenRAM/compiler/sram_factory.py", line 153, in create
    obj = mod(name=module_name, **kwargs)
  File "/opt/OpenRAM/compiler/modules/rom_decoder.py", line 37, in __init__
    self.create_netlist()
  File "/opt/OpenRAM/compiler/modules/rom_decoder.py", line 44, in create_netlist
    self.add_modules()
  File "/opt/OpenRAM/compiler/modules/rom_decoder.py", line 115, in add_modules
    self.control_array = factory.create(module_type="rom_address_control_array",
  File "/opt/OpenRAM/compiler/sram_factory.py", line 153, in create
    obj = mod(name=module_name, **kwargs)
  File "/opt/OpenRAM/compiler/modules/rom_address_control_array.py", line 40, in __init__
    self.create_layout()
  File "/opt/OpenRAM/compiler/modules/rom_address_control_array.py", line 53, in create_layout
    self.route_clk()
  File "/opt/OpenRAM/compiler/modules/rom_address_control_array.py", line 106, in route_clk
    self.route_horizontal_pins("clk", insts=self.buf_insts, layer=self.route_layer)
  File "/opt/OpenRAM/compiler/base/hierarchy_layout.py", line 961, in route_horizontal_pins
    insts = self.local_insts
AttributeError: 'rom_address_control_array' object has no attribute 'local_insts'

[philiprbrenan]

The Python used to create these ROMs:

word_size           = 1

check_lvsdrc        = True

rom_data            = "includes/RomPrimes.hex"
data_type           = "hex"

output_name         = "RomPrimes"
output_path         = "macro/RomPrimes"

tech_name           = "sky130"
nominal_corner_only = True

route_supplies      = "ring"
check_lvsdrc        = True

[mguthaus]

Please submit a PR to dev if you have a fix. Thanks!