chore(linux): Make U-Boot DDR documentation generic

Current U-Boot documentation only describes one of the many
functionalities of the U-Boot DDR driver i.e. Inline ECC. Modify it to
become generic and make sure to add the page for missing platforms
(J7200 and J721E) where Inline ECC is presently not tested officially (yet).

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>

Author: Neha Malcom Francis

configs/J7200/J7200_linux_toc.txt

@@ -37,6 +37,7 @@ linux/Foundational_Components/U-Boot/UG-NOR
 linux/Foundational_Components/U-Boot/UG-UART
 linux/Foundational_Components/U-Boot/UG-SATA
 linux/Foundational_Components/U-Boot/UG-UFS
+linux/Foundational_Components/U-Boot/UG-DDRSS-J7
 linux/Foundational_Components/U-Boot/UG-HyperBus
 linux/Foundational_Components/U-Boot/UG-RemoteProc
 linux/Foundational_Components/U-Boot/UG-AVS

configs/J721E/J721E_linux_toc.txt

@@ -37,6 +37,7 @@ linux/Foundational_Components/U-Boot/UG-NOR
 linux/Foundational_Components/U-Boot/UG-UART
 linux/Foundational_Components/U-Boot/UG-SATA
 linux/Foundational_Components/U-Boot/UG-UFS
+linux/Foundational_Components/U-Boot/UG-DDRSS-J7
 linux/Foundational_Components/U-Boot/UG-HyperBus
 linux/Foundational_Components/U-Boot/UG-RemoteProc
 linux/Foundational_Components/U-Boot/UG-AVS

source/linux/Foundational_Components/U-Boot/UG-DDRSS-J7.rst

@@ -1,18 +1,43 @@
-#########
-DDRSS ECC
-#########
+###
+DDR
+###
 
 ********
 Overview
 ********
 
-The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic
-to integrate these blocks in the device. For SDRAM data integrity, the DDRSS
+The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic to
+integrate these blocks in the device. The K3 DDRSS driver
+(:file:`drivers/ram/k3-ddrss/k3-ddrss.c`) runs during the R5 SPL stage and is
+responsible for initializing and configuring the DDR subsystem.
+
+******************
+DDR Initialization
+******************
+
+The driver utilizes an auto-generated configuration file containing the
+necessary settings for the DDR. It configures the frequency, timing parameters,
+training algorithms etc. for DDR initialization. The configuration DTSI can be
+generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_ and
+selecting the software product as "DDR Configuration for \*" as well as the
+required device.
+
+**********
+Inline ECC
+**********
+
+.. ifconfig:: CONFIG_part_variant in ('J7200', 'J721E')
+
+   .. note::
+
+      Inline ECC is currently not tested and supported for J721E and J7200
+
+For SDRAM data integrity, the DDRSS
 bridge supports inline ECC on the data written to or read from the SDRAM. ECC
 is stored together with the data so that a dedicated SDRAM device for ECC is
 not required. The 8-bit single error correction double error detection (SECDED)
 ECC data is calculated over 64-bit data quanta. For every 256-byte data block
-32 bytes of ECC is stored inline. Thus 1/9th of the total SDRAM space is used
+32 bytes of ECC is stored inline. Thus, 1/9th of the total SDRAM space is used
 for ECC storage and the remaining 8/9th of the SDRAM data space are seen as
 consecutive byte addresses. Even if there are non-ECC protected regions the
 previously described 1/9th-8/9th rule still applies and consecutive byte
@@ -25,8 +50,8 @@ protected by it. 1-bit error is correctable by ECC, but multi-bit and
 multiple 1-bit errors are not correctable and will be treated as an
 uncorrectable error. Any uncorrectable error will cause a bus abort.
 
-DDRSS inline ECC handling
-=========================
+ECC Handling
+============
 
 .. note::
 
@@ -35,31 +60,31 @@ DDRSS inline ECC handling
 Enabling inline ECC
 -------------------
 
-The inline ECC feature of DDRSS can be enabled by adding the
-``CONFIG_K3_INLINE_ECC`` config to the R5 defconfig:
+   The inline ECC feature of DDRSS can be enabled by adding the
+   ``CONFIG_K3_INLINE_ECC`` config to the R5 defconfig:
 
-      .. code-block:: kconfig
+   .. code-block:: kconfig
 
-         # u-boot/configs/*_r5_defconfig
+      # u-boot/configs/*_r5_defconfig
 
-         CONFIG_PINCTRL_SINGLE=y
-         CONFIG_POWER_DOMAIN=y
-         CONFIG_TI_POWER_DOMAIN=y
-         CONFIG_K3_INLINE_ECC=y
-         CONFIG_K3_SYSTEM_CONTROLLER=y
-         CONFIG_REMOTEPROC_TI_K3_ARM64=y
-         CONFIG_RESET_TI_SCI=y
+      CONFIG_PINCTRL_SINGLE=y
+      CONFIG_POWER_DOMAIN=y
+      CONFIG_TI_POWER_DOMAIN=y
+      CONFIG_K3_INLINE_ECC=y
+      CONFIG_K3_SYSTEM_CONTROLLER=y
+      CONFIG_REMOTEPROC_TI_K3_ARM64=y
+      CONFIG_RESET_TI_SCI=y
 
-This enables inline ECC for the entire region of the DDR.
+   This enables inline ECC for the entire region of the DDR.
 
 Priming with BIST Engine
 ------------------------
 
-The bootloader has the responsibility to pre-load the ECC protected region with
-known data before functional reads and writes are performed. During the ECC
-initialization, the R5 SPL fills the entire memory with zeros using the BIST
-engine in the DDR controller. The BIST engine method allows priming the entire
-region with zeros in much less time.
+   The bootloader has the responsibility to pre-load the ECC protected region with
+   known data before functional reads and writes are performed. During the ECC
+   initialization, the R5 SPL fills the entire memory with zeros using the BIST
+   engine in the DDR controller. The BIST engine method allows priming the entire
+   region with zeros in much less time.
 
 Enabling inline ECC for a partial region of the DDR
 ---------------------------------------------------
@@ -73,8 +98,8 @@ the absence of which it resorts to enabling for the entire DDR region:
    .. code-block:: dts
 
       inline_ecc: protected@9e780000 {
-            device_type = "ecc";
-            reg = <0x9e780000 0x0080000>;
-            bootph-all;
+         device_type = "ecc";
+         reg = <0x9e780000 0x0080000>;
+         bootph-all;
       };
 

source/linux/Foundational_Components/U-Boot/UG-DDRSS.rst

@@ -1,24 +1,44 @@
-#########
-DDRSS ECC
-#########
+###
+DDR
+###
 
 ********
 Overview
 ********
 
-The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic
-to integrate these blocks in the device. For SDRAM data integrity, the DDRSS
-bridge supports inline ECC on the data written to or read from the SDRAM. ECC
-is stored together with the data so that a dedicated SDRAM device for ECC is
-not required. The 8-bit single error correction double error detection (SECDED)
-ECC data is calculated over 64-bit data quanta. For every 256-byte data block
-32 bytes of ECC is stored inline. Thus 1/9th of the total SDRAM space is used
-for ECC storage and the remaining 8/9th of the SDRAM data space are seen as
-consecutive byte addresses. Even if there are non-ECC protected regions the
-previously described 1/9th-8/9th rule still applies and consecutive byte
-addresses are seen from system point of view. |__PART_FAMILY_DEVICE_NAMES__|
-supports up to 3 ECC protected non-overlapping memory ranges. The current
-U-Boot release supports a single region covering the entire SDRAM space.
+The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic to
+integrate these blocks in the device. The K3 DDRSS driver
+(:file:`drivers/ram/k3-ddrss/k3-ddrss.c`) runs during the R5 SPL stage and is
+responsible for initializing and configuring the DDR subsystem.
+
+******************
+DDR Initialization
+******************
+
+The driver utilizes an auto-generated configuration file containing the
+necessary settings for the DDR. It configures the frequency, timing parameters,
+training algorithms etc. for DDR initialization. The configuration DTSI can be
+generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_ and
+selecting the software product as "DDR Configuration for \*" as well as the
+required device.
+
+**************************
+Error Correction Code (ECC)
+**************************
+
+For SDRAM data integrity, the DDRSS bridge supports inline ECC on the data
+written to or read from the SDRAM. ECC is stored together with the data so that
+a dedicated SDRAM device for ECC is not required. The 8-bit single error
+correction double error detection (SECDED) ECC data is calculated over 64-bit
+data quanta. For every 256-byte data block 32 bytes of ECC is stored inline.
+Thus 1/9th of the total SDRAM space is used for ECC storage and the remaining
+8/9th of the SDRAM data space are seen as consecutive byte addresses. Even if
+there are non-ECC protected regions the previously described 1/9th-8/9th rule
+still applies and consecutive byte addresses are seen from system point of view.
+
+|__PART_FAMILY_DEVICE_NAMES__| supports up to 3 ECC protected non-overlapping
+memory ranges. The current U-Boot release supports a single region covering the
+entire SDRAM space.
 
 ECC is calculated for all accesses that are within the address ranges
 protected by it. 1-bit error is correctable by ECC, but multi-bit and
@@ -38,8 +58,8 @@ three ways to handle it:
    Options 1 and 2 doesn't report the reason. So, if there is a need to report
    the reason behind uncorrectable error handle it the third way.
 
-DDRSS ECC handling
-==================
+ECC Handling
+============
 
 .. note::