1- #########
2- DDRSS ECC
3- #########
1+ ###
2+ DDR
3+ ###
44
55********
66Overview
77********
88
9- The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic
10- to integrate these blocks in the device. For SDRAM data integrity, the DDRSS
11- bridge supports inline ECC on the data written to or read from the SDRAM. ECC
12- is stored together with the data so that a dedicated SDRAM device for ECC is
13- not required. The 8-bit single error correction double error detection (SECDED)
14- ECC data is calculated over 64-bit data quanta. For every 256-byte data block
15- 32 bytes of ECC is stored inline. Thus 1/9th of the total SDRAM space is used
16- for ECC storage and the remaining 8/9th of the SDRAM data space are seen as
17- consecutive byte addresses. Even if there are non-ECC protected regions the
18- previously described 1/9th-8/9th rule still applies and consecutive byte
19- addresses are seen from system point of view. |__PART_FAMILY_DEVICE_NAMES__ |
20- supports up to 3 ECC protected non-overlapping memory ranges. The current
21- U-Boot release supports a single region covering the entire SDRAM space.
9+ The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic to
10+ integrate these blocks in the device. The K3 DDRSS driver
11+ (:file: `drivers/ram/k3-ddrss/k3-ddrss.c `) runs during the R5 SPL stage and is
12+ responsible for initializing and configuring the DDR subsystem.
2213
23- ECC is calculated for all accesses that are within the address ranges
24- protected by it. 1-bit error is correctable by ECC, but multi-bit and
25- multiple 1-bit errors are not correctable and will be treated as an
26- uncorrectable error. Any uncorrectable error will cause a bus abort.
14+ ******************
15+ DDR Initialization
16+ ******************
2717
28- DDRSS inline ECC handling
29- =========================
18+ The driver utilizes an auto-generated configuration file containing the
19+ necessary settings for the DDR. It configures the frequency, timing parameters,
20+ training algorithms etc. for DDR initialization. The configuration DTSI can be
21+ generated using the `Sysconfig tool <https://dev.ti.com/sysconfig >`_ and
22+ selecting the software product as "DDR Configuration for \* " as well as the
23+ required device.
3024
31- .. note ::
25+ .. ifconfig :: CONFIG_part_variant not in ('J7200', 'J721E')
3226
33- The inline ECC feature of DDRSS is not enabled by default in U-Boot.
27+ ******** **
28+ Inline ECC
29+ ******** **
3430
35- Enabling inline ECC
36- -------------------
31+ For SDRAM data integrity, the DDRSS
32+ bridge supports inline ECC on the data written to or read from the SDRAM. ECC
33+ is stored together with the data so that a dedicated SDRAM device for ECC is
34+ not required. The 8-bit single error correction double error detection (SECDED)
35+ ECC data is calculated over 64-bit data quanta. For every 256-byte data block
36+ 32 bytes of ECC is stored inline. Thus 1/9th of the total SDRAM space is used
37+ for ECC storage and the remaining 8/9th of the SDRAM data space are seen as
38+ consecutive byte addresses. Even if there are non-ECC protected regions the
39+ previously described 1/9th-8/9th rule still applies and consecutive byte
40+ addresses are seen from system point of view. |__PART_FAMILY_DEVICE_NAMES__ |
41+ supports up to 3 ECC protected non-overlapping memory ranges. The current
42+ U-Boot release supports a single region covering the entire SDRAM space.
3743
38- The inline ECC feature of DDRSS can be enabled by adding the
39- ``CONFIG_K3_INLINE_ECC `` config to the R5 defconfig:
44+ ECC is calculated for all accesses that are within the address ranges
45+ protected by it. 1-bit error is correctable by ECC, but multi-bit and
46+ multiple 1-bit errors are not correctable and will be treated as an
47+ uncorrectable error. Any uncorrectable error will cause a bus abort.
48+
49+ ECC Handling
50+ ============
51+
52+ .. note ::
53+
54+ The inline ECC feature of DDRSS is not enabled by default in U-Boot.
55+
56+ Enabling inline ECC
57+ -------------------
58+
59+ The inline ECC feature of DDRSS can be enabled by adding the
60+ ``CONFIG_K3_INLINE_ECC `` config to the R5 defconfig:
4061
4162 .. code-block :: kconfig
4263
@@ -50,31 +71,31 @@ The inline ECC feature of DDRSS can be enabled by adding the
5071 CONFIG_REMOTEPROC_TI_K3_ARM64=y
5172 CONFIG_RESET_TI_SCI=y
5273
53-
74+ This enables inline ECC for the entire region of the DDR.
5475
55- Priming with BIST Engine
56- ------------------------
76+ Priming with BIST Engine
77+ ------------------------
5778
58- The bootloader has the responsibility to pre-load the ECC protected region with
59- known data before functional reads and writes are performed. During the ECC
60- initialization, the R5 SPL fills the entire memory with zeros using the BIST
61- engine in the DDR controller. The BIST engine method allows priming the entire
62- region with zeros in much less time.
79+ The bootloader has the responsibility to pre-load the ECC protected region with
80+ known data before functional reads and writes are performed. During the ECC
81+ initialization, the R5 SPL fills the entire memory with zeros using the BIST
82+ engine in the DDR controller. The BIST engine method allows priming the entire
83+ region with zeros in much less time.
6384
64- Enabling inline ECC for a partial region of the DDR
65- ---------------------------------------------------
85+ Enabling inline ECC for a partial region of the DDR
86+ ---------------------------------------------------
6687
67- Instead of defaulting to enable inline ECC for the entire DDR region, a partial
68- range can also be selected.
88+ Instead of defaulting to enable inline ECC for the entire DDR region, a partial
89+ range can also be selected.
6990
70- In this case, the DDRSS driver expects such a node within the memory node, in
71- the absence of which it resorts to enabling for the entire DDR region:
91+ In this case, the DDRSS driver expects such a node within the memory node, in
92+ the absence of which it resorts to enabling for the entire DDR region:
7293
73- .. code-block :: dts
94+ .. code-block :: dts
7495
75- inline_ecc: protected@9e780000 {
96+ inline_ecc: protected@9e780000 {
7697 device_type = "ecc";
7798 reg = <0x9e780000 0x0080000>;
7899 bootph-all;
79- };
100+ };
80101
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