From 37e2711a37f9933fd9f8da7594cf3628c71652db Mon Sep 17 00:00:00 2001 From: Pradeep HN Date: Tue, 30 Jul 2024 21:07:57 +0530 Subject: [PATCH 1/3] am263x: enet: Enable enet SBL load Signed-off-by: Pradeep HN --- .project/device/project_am263x.js | 1 + .../sbl_qspi_enet/.project/project_am263x.js | 95 ++ .../am263x-cc/r5fss0-0_nortos/board.c | 483 ++++++ .../am263x-cc/r5fss0-0_nortos/example.syscfg | 150 ++ .../am263x-cc/r5fss0-0_nortos/main.c | 305 ++++ .../am263x-cc/r5fss0-0_nortos/sbl_enet.c | 1401 +++++++++++++++++ .../am263x-cc/r5fss0-0_nortos/sbl_enet.h | 268 ++++ .../ti-arm-clang/example.projectspec | 127 ++ .../r5fss0-0_nortos/ti-arm-clang/linker.cmd | 71 + .../ti-arm-clang/linker_bkp.cmd | 71 + .../r5fss0-0_nortos/ti-arm-clang/makefile | 312 ++++ .../ti-arm-clang/makefile_ccs_bootimage_gen | 87 + .../ti-arm-clang/makefile_projectspec | 20 + .../ti-arm-clang/syscfg_c.rov.xs | 8 + makefile.am263x | 13 + .../am263x-cc/default_sbl_enet.cfg | 25 + 16 files changed, 3437 insertions(+) create mode 100644 examples/drivers/boot/sbl_qspi_enet/.project/project_am263x.js create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/board.c create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker.cmd create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker_bkp.cmd create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_ccs_bootimage_gen create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_projectspec create mode 100644 examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/syscfg_c.rov.xs create mode 100644 tools/boot/sbl_prebuilt/am263x-cc/default_sbl_enet.cfg diff --git a/.project/device/project_am263x.js b/.project/device/project_am263x.js index df2bd9013c8..1deca932a6e 100644 --- a/.project/device/project_am263x.js +++ b/.project/device/project_am263x.js @@ -29,6 +29,7 @@ const device_defines = { }; const example_file_list = [ + "examples/drivers/boot/sbl_qspi_enet/.project/project.js", "examples/drivers/adc/adc_multiple_soc_epwm/.project/project.js", "examples/drivers/adc/adc_ppb_epwm_trip/.project/project.js", "examples/drivers/adc/adc_ppb_delay/.project/project.js", diff --git a/examples/drivers/boot/sbl_qspi_enet/.project/project_am263x.js b/examples/drivers/boot/sbl_qspi_enet/.project/project_am263x.js new file mode 100644 index 00000000000..dd7275f5579 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/.project/project_am263x.js @@ -0,0 +1,95 @@ +let path = require('path'); + +let device = "am263x"; + +const files = { + common: [ + "main.c", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + ], +}; + +const libdirs_nortos = { + common: [ + "${MCU_PLUS_SDK_PATH}/source/kernel/nortos/lib", + "${MCU_PLUS_SDK_PATH}/source/drivers/lib", + "${MCU_PLUS_SDK_PATH}/source/board/lib", + "${MCU_PLUS_SDK_PATH}/source/sdl/lib", + ], +}; + +const libs_nortos_r5f = { + common: [ + "nortos.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "drivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "board.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + "sdl.am263x.r5f.ti-arm-clang.${ConfigName}.lib", + ], +}; + +const lnkfiles = { + common: [ + "linker.cmd", + ] +}; + +const r5f0_macro = { + common: [ + "R5F0_INPUTS", + ], + +}; + +const syscfgfile = "../example.syscfg"; + +const readmeDoxygenPageTag = "EXAMPLES_DRIVERS_SBL_QSPI"; + +const buildOptionCombos = [ + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am263x-cc", os: "nortos"}, + { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am263x-lp", os: "nortos"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.name = "sbl_qspi"; + property.isInternal = false; + property.isBootLoader = true; + property.buildOptionCombos = buildOptionCombos; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.libdirs = libdirs_nortos; + build_property.lnkfiles = lnkfiles; + build_property.syscfgfile = syscfgfile; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + + if(buildOption.cpu.match(/r5f*/)) { + build_property.libs = libs_nortos_r5f; + build_property.defines = r5f0_macro; + } + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/board.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/board.c new file mode 100644 index 00000000000..cc4dc3dff54 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/board.c @@ -0,0 +1,483 @@ +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "ti_board_config.h" +#include + +/* + * Board info + */ +void Board_cpswMuxSel(void) +{ + return; +} + +/* + * Tx and Rx Delay set + */ +void Board_TxRxDelaySet(const EnetBoard_PhyCfg *boardPhyCfg) +{ + return; +} + +/* + * Get ethernet board id + */ +uint32_t Board_getEthBoardId(void) +{ + return ENETBOARD_AM263X_EVM; +} + +/* + * Get ethernet type + */ +uint32_t Board_getEthType(void) +{ + return ENET_CPSW_3G; +} + +/* + * Copyright (C) 2021 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * Auto generated file + */ +#include "ti_board_config.h" + +/* + * Auto generated file + */ + + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ti_board_open_close.h" +#include + +#define CONFIG_ENET_CPSW0_PHY0_ADDR (0U) +#define CONFIG_ENET_CPSW0_PHY1_ADDR (3U) + +#include +#include + +#define IO_EXPANDER_PORT0_OUTPUT_REG (0x02U) +#define IO_EXPANDER_PORT0_DIR_REG (0x06U) +#define IO_EXPANDER_I2C_ADDR (0x20U) + +static void EnetBoard_setMacPort2IOExpanderCfg(void); + +/* PHY drivers */ +extern EnetPhy_Drv gEnetPhyDrvGeneric; +extern EnetPhy_Drv gEnetPhyDrvDp83822; +extern EnetPhy_Drv gEnetPhyDrvDp83867; +extern EnetPhy_Drv gEnetPhyDrvDp83869; +extern EnetPhy_Drv gEnetPhyDrvVsc8514; + +/*! \brief All the registered PHY specific drivers. */ +static const EnetPhyDrv_Handle gEnetPhyDrvs[] = +{ + &gEnetPhyDrvDp83869, /* DP83869 */ + &gEnetPhyDrvGeneric, /* Generic PHY - must be last */ +}; + +const EnetPhy_DrvInfoTbl gEnetPhyDrvTbl = +{ + .numHandles = ENET_ARRAYSIZE(gEnetPhyDrvs), + .hPhyDrvList = gEnetPhyDrvs, +}; + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/** + TPR:MSS_CTRL:CPSW_CONTROL + + Address offset 0x0000016C + Physical address 0x0212016C + Instance MSS_CTRL + CPSW_CONTROL_RGMII1_ID_MODE 16 Writing 1'b1 would disable the internal clock delays. And those delays need to be handled on board. + CPSW_CONTROL_RMII_REF_CLK_OE_N 8 To select the rmii_ref_clk from PAD or from MSS_RCM. 0: clock will be from mss_rcm through IO internal loopback 1: will be from + CPSW_CONTROL_PORT1_MODE_SEL 2:0 Port 1 Interface + 00 = GMII/MII + 01 = RMII + 10 = RGMII + 11 = Not Supported +*/ + +#define MSS_CPSW_CONTROL_PORT_MODE_RMII (0x1U) +#define MSS_CPSW_CONTROL_PORT_MODE_RGMII (0x2U) + +#define I2C_EEPROM_MAC_DATA_OFFSET (0x3D) +#define I2C_EEPROM_MAC_CTRL_OFFSET (0x3B) + +#define ENET_BOARD_NUM_MACADDR_MAX (3U) +#define ENET_GET_NUM_MAC_ADDR(num) ((num>>3)+1) +#define ENET_MAC_ADDR_VALIDATE_MASK (0x01U) +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort); + +static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort, + const EnetBoard_PortCfg *ethPortCfgs, + uint32_t numEthPorts); + +static void EnetBoard_enableExternalMux(); + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/*! + * \brief Common Processor Board (CPB) board's DP83869 PHY configuration. + */ +static const Dp83869_Cfg gEnetCpbBoard_dp83869PhyCfg = +{ + .txClkShiftEn = true, + .rxClkShiftEn = true, + .txDelayInPs = 500U, /* 0.5 ns */ + .rxDelayInPs = 500U, /* 0.5 ns */ + .txFifoDepth = 4U, + .impedanceInMilliOhms = 35000, /* 35 ohms */ + .idleCntThresh = 4U, /* Improves short cable performance */ + .gpio0Mode = DP83869_GPIO0_LED3, + .gpio1Mode = DP83869_GPIO1_COL, /* Unused */ + .ledMode = + { + DP83869_LED_LINKED, /* Unused */ + DP83869_LED_LINKED_100BTX, + DP83869_LED_RXTXACT, + DP83869_LED_LINKED_1000BT, + }, +}; + +/* + * AM263x board configuration. + * + * 1 x RGMII PHY connected to AM263x CPSW_3G MAC port. + */ +static const EnetBoard_PortCfg gEnetCpbBoard_am263xEthPort[] = +{ + { /* "CPSW3G" */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_1, + .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = 0, + .isStrapped = false, + .skipExtendedCfg = false, + .extendedCfg = &gEnetCpbBoard_dp83869PhyCfg, + .extendedCfgSize = sizeof(gEnetCpbBoard_dp83869PhyCfg), + }, + .flags = 0U, + }, + { /* "CPSW3G" */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_2, + .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = 3, + .isStrapped = false, + .skipExtendedCfg = false, + .extendedCfg = &gEnetCpbBoard_dp83869PhyCfg, + .extendedCfgSize = sizeof(gEnetCpbBoard_dp83869PhyCfg), + }, + .flags = 0U, + }, +}; +/* + * AM263X dummy board used for MAC loopback setup. + */ +static const EnetBoard_PortCfg gEnetLpbkBoard_am263xEthPort[] = +{ + { /* RGMII MAC loopback */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_1, + .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = ENETPHY_INVALID_PHYADDR, + }, + .flags = 0U, + }, + { /* RMII MAC loopback */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_1, + .mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = ENETPHY_INVALID_PHYADDR, + }, + .flags = 0U, + }, +}; + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +const EnetBoard_PhyCfg *EnetBoard_getPhyCfg(const EnetBoard_EthPort *ethPort) +{ + const EnetBoard_PortCfg *portCfg; + + portCfg = EnetBoard_getPortCfg(ethPort); + + return (portCfg != NULL) ? &portCfg->phyCfg : NULL; +} + +static void EnetBoard_enableExternalMux() +{ + /* Enable external MUXes, if any, as per the board design */ +} + +static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *ethPort) +{ + const EnetBoard_PortCfg *portCfg = NULL; + + if (ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_CPB_ID)) + { + portCfg = EnetBoard_findPortCfg(ethPort, + gEnetCpbBoard_am263xEthPort, + ENETPHY_ARRAYSIZE(gEnetCpbBoard_am263xEthPort)); + } + if ((portCfg == NULL) && + ENET_NOT_ZERO(ethPort->boardId & ENETBOARD_LOOPBACK_ID)) + { + portCfg = EnetBoard_findPortCfg(ethPort, + gEnetLpbkBoard_am263xEthPort, + ENETPHY_ARRAYSIZE(gEnetLpbkBoard_am263xEthPort)); + } + + return portCfg; +} + +static const EnetBoard_PortCfg *EnetBoard_findPortCfg(const EnetBoard_EthPort *ethPort, + const EnetBoard_PortCfg *ethPortCfgs, + uint32_t numEthPorts) +{ + const EnetBoard_PortCfg *ethPortCfg = NULL; + bool found = false; + uint32_t i; + + for (i = 0U; i < numEthPorts; i++) + { + ethPortCfg = ðPortCfgs[i]; + + if ((ethPortCfg->enetType == ethPort->enetType) && + (ethPortCfg->instId == ethPort->instId) && + (ethPortCfg->macPort == ethPort->macPort) && + (ethPortCfg->mii.layerType == ethPort->mii.layerType) && + (ethPortCfg->mii.sublayerType == ethPort->mii.sublayerType)) + { + found = true; + break; + } + } + + return found ? ethPortCfg : NULL; +} + +void EnetBoard_getMiiConfig(EnetMacPort_Interface *mii) +{ + mii->layerType = ENET_MAC_LAYER_GMII; + mii->variantType = ENET_MAC_VARIANT_FORCED; + mii->sublayerType = ENET_MAC_SUBLAYER_REDUCED; +} + +int32_t EnetBoard_setupPorts(EnetBoard_EthPort *ethPorts, + uint32_t numEthPorts) +{ + CSL_mss_ctrlRegs *mssCtrlRegs = (CSL_mss_ctrlRegs *)CSL_MSS_CTRL_U_BASE; + + DebugP_assert(numEthPorts == 1); + DebugP_assert(ethPorts->mii.sublayerType == ENET_MAC_SUBLAYER_REDUCED); + + EnetBoard_enableExternalMux(); + + switch(ethPorts->macPort) + { + case ENET_MAC_PORT_1: + CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_RGMII1_ID_MODE, 0U); + CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_PORT1_MODE_SEL, MSS_CPSW_CONTROL_PORT_MODE_RGMII); + break; + case ENET_MAC_PORT_2: + CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_RGMII2_ID_MODE, 0U); + CSL_FINS( mssCtrlRegs->CPSW_CONTROL,MSS_CTRL_CPSW_CONTROL_PORT2_MODE_SEL, MSS_CPSW_CONTROL_PORT_MODE_RGMII); + EnetBoard_setMacPort2IOExpanderCfg(); + break; + default: + DebugP_assert(false); + } + + /* Nothing else to do */ + return ENET_SOK; +} + +static void EnetBoard_setMacPort2IOExpanderCfg(void) +{ + I2C_Transaction i2cTransaction; + uint8_t buffer[2]; + + I2C_Transaction_init(&i2cTransaction); + i2cTransaction.writeBuf = buffer; + i2cTransaction.writeCount = 2U; + i2cTransaction.targetAddress = IO_EXPANDER_I2C_ADDR; + + /* Configure MDIO sel pin */ + /* Set output to high */ + buffer[0] = IO_EXPANDER_PORT0_OUTPUT_REG + 1; /* Port 1 */ + buffer[1] = (0x01 << 4); /* Pin 4 */ + I2C_transfer(I2C_getHandle(CONFIG_I2C1), &i2cTransaction); + + /* set pin to output */ + buffer[0] = IO_EXPANDER_PORT0_DIR_REG + 1; + buffer[1] = ~(0x1 << 4); + I2C_transfer(I2C_getHandle(CONFIG_I2C1), &i2cTransaction); + + /* Configure RGMII2 sel pin */ + /* Set output to low */ + buffer[0] = IO_EXPANDER_PORT0_OUTPUT_REG + 0; /* Port 0 */ + buffer[1] = ~(0x03 << 2); /* Pin 2 & 3 */ + I2C_transfer(I2C_getHandle(CONFIG_I2C1), &i2cTransaction); + /* set pin to output */ + buffer[0] = IO_EXPANDER_PORT0_DIR_REG + 0; + buffer[1] = ~(0x3 << 2); + I2C_transfer(I2C_getHandle(CONFIG_I2C1), &i2cTransaction); + +} + +void EnetBoard_getMacAddrList(uint8_t macAddr[][ENET_MAC_ADDR_LEN], + uint32_t maxMacEntries, + uint32_t *pAvailMacEntries) +{ + *pAvailMacEntries = 0; + // int32_t status = ENET_SOK; + // uint32_t macAddrCnt; + // uint32_t i; + // uint8_t numMacMax; + // uint8_t macAddrBuf[ENET_BOARD_NUM_MACADDR_MAX * ENET_MAC_ADDR_LEN]; + // uint8_t validNumMac = 0U; + + // status = EEPROM_read(gEepromHandle[CONFIG_EEPROM0], I2C_EEPROM_MAC_CTRL_OFFSET, &numMacMax, sizeof(uint8_t)); + // EnetAppUtils_assert(status == ENET_SOK); + // EnetAppUtils_assert(ENET_GET_NUM_MAC_ADDR(numMacMax) <= ENET_BOARD_NUM_MACADDR_MAX); + // EnetAppUtils_assert(pAvailMacEntries != NULL); + + // macAddrCnt = EnetUtils_min(ENET_GET_NUM_MAC_ADDR(numMacMax), maxMacEntries); + + // status = EEPROM_read(gEepromHandle[CONFIG_EEPROM0], I2C_EEPROM_MAC_DATA_OFFSET, macAddrBuf, (macAddrCnt * ENET_MAC_ADDR_LEN) ); + // EnetAppUtils_assert(status == ENET_SOK); + + // /* Save only those required to meet the max number of MAC entries */ + // /* Validating that the MAC addresses from the EEPROM are not MULTICAST addresses */ + // for (i = 0U; i < macAddrCnt; i++) + // { + // if(!(macAddrBuf[i * ENET_MAC_ADDR_LEN] & ENET_MAC_ADDR_VALIDATE_MASK)){ + // memcpy(macAddr[validNumMac], &macAddrBuf[i * ENET_MAC_ADDR_LEN], ENET_MAC_ADDR_LEN); + // validNumMac++; + // } + // } + + // *pAvailMacEntries = validNumMac; + + // if (macAddrCnt == 0U) + // { + // EnetAppUtils_print("EnetBoard_getMacAddrList Failed - IDK not present\n"); + // EnetAppUtils_assert(false); + // } +} + +/* + * Get ethernet board id + */ +uint32_t EnetBoard_getId(void) +{ + return ENETBOARD_AM263X_EVM; +} + + diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg new file mode 100644 index 00000000000..9c329fa641a --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg @@ -0,0 +1,150 @@ +/** + * These arguments were used when this file was generated. They will be automatically applied on subsequent loads + * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. + * @cliArgs --device "AM263x_beta" --package "ZCZ" --part "AM263x" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" + * @versions {"tool":"1.18.0+3266"} + */ + +/** + * Import the modules used in this configuration. + */ +const flash = scripting.addModule("/board/flash/flash", {}, false); +const flash1 = flash.addInstance(); +const bootloader = scripting.addModule("/drivers/bootloader/bootloader", {}, false); +const bootloader1 = bootloader.addInstance(); +const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false); +const gpio1 = gpio.addInstance(); +const hsmclient = scripting.addModule("/drivers/hsmclient/hsmclient", {}, false); +const hsmclient1 = hsmclient.addInstance(); +const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false); +const i2c1 = i2c.addInstance(); +const debug_log = scripting.addModule("/kernel/dpl/debug_log"); +const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false); +const mpu_armv71 = mpu_armv7.addInstance(); +const mpu_armv72 = mpu_armv7.addInstance(); +const mpu_armv73 = mpu_armv7.addInstance(); +const mpu_armv74 = mpu_armv7.addInstance(); +const mpu_armv75 = mpu_armv7.addInstance(); +const enet_cpsw = scripting.addModule("/networking/enet_cpsw/enet_cpsw", {}, false); +const enet_cpsw1 = enet_cpsw.addInstance(); + +/** + * Write custom configuration values to the imported modules. + */ +bootloader1.$name = "CONFIG_BOOTLOADER0"; +bootloader1.appImageOffset = "0x00080000"; + +flash1.$name = "CONFIG_FLASH0"; +bootloader1.flashDriver = flash1; +flash1.peripheralDriver.$name = "CONFIG_QSPI0"; +flash1.peripheralDriver.dmaEnable = true; +flash1.peripheralDriver.QSPI.QSPI_D2.pu_pd = "pu"; +flash1.peripheralDriver.QSPI.QSPI_D3.pu_pd = "pu"; + +const edma = scripting.addModule("/drivers/edma/edma", {}, false); +const edma1 = edma.addInstance({}, false); +edma1.$name = "CONFIG_EDMA0"; +flash1.peripheralDriver.edmaConfig = edma1; +edma1.edmaRmDmaCh[0].$name = "CONFIG_EDMA_RM0"; +edma1.edmaRmQdmaCh[0].$name = "CONFIG_EDMA_RM1"; +edma1.edmaRmTcc[0].$name = "CONFIG_EDMA_RM2"; +edma1.edmaRmParam[0].$name = "CONFIG_EDMA_RM3"; + +gpio1.$name = "ENET_TRANSFER_START_BTN"; +gpio1.trigType = "RISE_EDGE"; +gpio1.GPIO.gpioPin.$assign = "LIN2_RXD"; + +hsmclient1.$name = "CONFIG_HSMCLIENT0"; + +i2c1.$name = "CONFIG_I2C1"; +i2c1.I2C.$assign = "I2C2"; +i2c1.I2C.SCL.$assign = "UART0_RTSn"; + +debug_log.enableUartLog = true; +debug_log.uartLog.$name = "CONFIG_UART0"; +debug_log.uartLog.intrEnable = "DISABLE"; +debug_log.uartLog.UART.RXD.$assign = "UART0_RXD"; +debug_log.uartLog.UART.TXD.$assign = "UART0_TXD"; + +mpu_armv71.$name = "CONFIG_MPU_REGION0"; +mpu_armv71.size = 31; +mpu_armv71.attributes = "Device"; +mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv71.allowExecute = false; + +mpu_armv72.$name = "CONFIG_MPU_REGION1"; +mpu_armv72.size = 15; +mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv73.$name = "CONFIG_MPU_REGION2"; +mpu_armv73.baseAddr = 0x80000; +mpu_armv73.size = 15; +mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD"; + +mpu_armv74.$name = "CONFIG_MPU_REGION3"; +mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD"; +mpu_armv74.baseAddr = 0x70000000; +mpu_armv74.size = 21; +mpu_armv74.attributes = "Cached+Sharable"; + +mpu_armv75.$name = "CONFIG_MPU_REGION4"; +mpu_armv75.allowExecute = false; +mpu_armv75.attributes = "Device"; +mpu_armv75.baseAddr = 0xCE000000; +mpu_armv75.size = 24; + +enet_cpsw1.$name = "CONFIG_ENET_CPSW0"; +enet_cpsw1.RtosVariant = "NoRTOS"; +enet_cpsw1.LargePoolPktCount = 16; +enet_cpsw1.customBoardEnable = true; +enet_cpsw1.DisableMacPort2 = true; +enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0"; +enet_cpsw1.txDmaChannel[0].PacketsCount = 8; +enet_cpsw1.rxDmaChannel[0].$name = "ENET_DMA_RX_CH0"; +enet_cpsw1.rxDmaChannel[0].PacketsCount = 8; +enet_cpsw1.pinmux[0].$name = "ENET_CPSW_PINMUX0"; + +/** + * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future + * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to + * re-solve from scratch. + */ +flash1.peripheralDriver.QSPI.$suggestSolution = "QSPI"; +flash1.peripheralDriver.QSPI.QSPI_D0.$suggestSolution = "QSPI_D0"; +flash1.peripheralDriver.QSPI.QSPI_D1.$suggestSolution = "QSPI_D1"; +flash1.peripheralDriver.QSPI.QSPI_D2.$suggestSolution = "QSPI_D2"; +flash1.peripheralDriver.QSPI.QSPI_D3.$suggestSolution = "QSPI_D3"; +flash1.peripheralDriver.QSPI.QSPI_CLK.$suggestSolution = "QSPI_CLK"; +flash1.peripheralDriver.QSPI.QSPI_CSn0.$suggestSolution = "QSPI_CSn0"; +gpio1.GPIO.$suggestSolution = "GPIO0"; +i2c1.I2C.SDA.$suggestSolution = "UART0_CTSn"; +debug_log.uartLog.UART.$suggestSolution = "UART0"; +enet_cpsw1.pinmux[0].MDIO.$suggestSolution = "MDIO"; +enet_cpsw1.pinmux[0].MDIO.MDIO_MDIO.$suggestSolution = "MDIO_MDIO"; +enet_cpsw1.pinmux[0].MDIO.MDIO_MDC.$suggestSolution = "MDIO_MDC"; +enet_cpsw1.pinmux[0].RGMII1.$suggestSolution = "RGMII2"; +enet_cpsw1.pinmux[0].RGMII1.RD0.$suggestSolution = "PR0_PRU0_GPIO0"; +enet_cpsw1.pinmux[0].RGMII1.RD1.$suggestSolution = "PR0_PRU0_GPIO1"; +enet_cpsw1.pinmux[0].RGMII1.RD2.$suggestSolution = "PR0_PRU0_GPIO2"; +enet_cpsw1.pinmux[0].RGMII1.RD3.$suggestSolution = "PR0_PRU0_GPIO3"; +enet_cpsw1.pinmux[0].RGMII1.RX_CTL.$suggestSolution = "PR0_PRU0_GPIO4"; +enet_cpsw1.pinmux[0].RGMII1.RXC.$suggestSolution = "PR0_PRU0_GPIO6"; +enet_cpsw1.pinmux[0].RGMII1.TD0.$suggestSolution = "PR0_PRU0_GPIO11"; +enet_cpsw1.pinmux[0].RGMII1.TD1.$suggestSolution = "PR0_PRU0_GPIO12"; +enet_cpsw1.pinmux[0].RGMII1.TD2.$suggestSolution = "PR0_PRU0_GPIO13"; +enet_cpsw1.pinmux[0].RGMII1.TD3.$suggestSolution = "PR0_PRU0_GPIO14"; +enet_cpsw1.pinmux[0].RGMII1.TX_CTL.$suggestSolution = "PR0_PRU0_GPIO15"; +enet_cpsw1.pinmux[0].RGMII1.TXC.$suggestSolution = "PR0_PRU0_GPIO16"; +enet_cpsw1.pinmux[0].RGMII2.$suggestSolution = "RGMII1"; +enet_cpsw1.pinmux[0].RGMII2.RD0.$suggestSolution = "RGMII1_RD0"; +enet_cpsw1.pinmux[0].RGMII2.RD1.$suggestSolution = "RGMII1_RD1"; +enet_cpsw1.pinmux[0].RGMII2.RD2.$suggestSolution = "RGMII1_RD2"; +enet_cpsw1.pinmux[0].RGMII2.RD3.$suggestSolution = "RGMII1_RD3"; +enet_cpsw1.pinmux[0].RGMII2.RX_CTL.$suggestSolution = "RGMII1_RX_CTL"; +enet_cpsw1.pinmux[0].RGMII2.RXC.$suggestSolution = "RGMII1_RXC"; +enet_cpsw1.pinmux[0].RGMII2.TD0.$suggestSolution = "RGMII1_TD0"; +enet_cpsw1.pinmux[0].RGMII2.TD1.$suggestSolution = "RGMII1_TD1"; +enet_cpsw1.pinmux[0].RGMII2.TD2.$suggestSolution = "RGMII1_TD2"; +enet_cpsw1.pinmux[0].RGMII2.TD3.$suggestSolution = "RGMII1_TD3"; +enet_cpsw1.pinmux[0].RGMII2.TX_CTL.$suggestSolution = "RGMII1_TX_CTL"; +enet_cpsw1.pinmux[0].RGMII2.TXC.$suggestSolution = "RGMII1_TXC"; diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c new file mode 100644 index 00000000000..3029505e47f --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * + * This bootloader does SOC initializations in addition to providing an + * option to receive an application image via UDP over ethernet and flashing + * the received application image to 0xA0000 location in the QSPI Flash and + * attempts to boot the same multicore appimage present at 0xA0000 location + * in the QSPI Flash after successful completion of the image transferred + * over ethernet. + * + */ + +#include +#include +#include "ti_drivers_config.h" +#include "ti_drivers_open_close.h" +#include "ti_board_open_close.h" +#include "ti_board_config.h" +#include +#include +#include +#include +#include "sbl_enet.h" +#include /* hsmRt bin header file */ + +uint32_t gGpioBaseAddr = ENET_TRANSFER_START_BTN_BASE_ADDR; +uint32_t pinNum = ENET_TRANSFER_START_BTN_PIN; + +const uint8_t gHsmRtFw[HSMRT_IMG_SIZE_IN_BYTES]__attribute__((section(".rodata.hsmrt"))) + = HSMRT_IMG; + +void receiveAppImgOverEnet(); + +/* call this API to stop the booting process and spin, do that you can connect + * debugger, load symbols and then make the 'loop' variable as 0 to continue execution + * with debugger connected. + */ +void loop_forever(void) +{ + volatile uint32_t loop = 1; + while(loop); +} + +int main(void) +{ + int32_t status; +#if 1 + Bootloader_profileReset(); + Bootloader_socConfigurePll(); + Bootloader_socSetAutoClock(); +#endif + System_init(); + Bootloader_profileAddProfilePoint("System_init"); + + loop_forever(); + // Board_init(); // deta remove this? + + Drivers_open(); + Bootloader_profileAddProfilePoint("Drivers_open"); + + DebugP_log("\r\n"); +#if 1 + Bootloader_socLoadHsmRtFw(gHsmRtFw, HSMRT_IMG_SIZE_IN_BYTES); + Bootloader_socInitL2MailBoxMemory(); +#endif + Bootloader_profileAddProfilePoint("LoadHsmRtFw"); + + DebugP_log("\r\n"); + DebugP_log("Starting QSPI Bootloader ... \r\n"); + + status = Board_driversOpen(); + DebugP_assert(status == SystemP_SUCCESS); + Bootloader_profileAddProfilePoint("Board_driversOpen"); + + /* Receive application image via UDP over ethernet */ + receiveAppImgOverEnet(); + + if(SystemP_SUCCESS == status) + { + Bootloader_BootImageInfo bootImageInfo; + Bootloader_Params bootParams; + Bootloader_Handle bootHandle; + + Bootloader_Params_init(&bootParams); + Bootloader_BootImageInfo_init(&bootImageInfo); + + bootHandle = Bootloader_open(CONFIG_BOOTLOADER0, &bootParams); + if(bootHandle != NULL) + { + status = Bootloader_parseMultiCoreAppImage(bootHandle, &bootImageInfo); + /* Load CPUs */ + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1))) + { + bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_1); + Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_1); + status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]); + } + if ((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0))) + { + bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS1_0); + Bootloader_profileAddCore(CSL_CORE_ID_R5FSS1_0); + status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]); + } + if ((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_1))) + { + bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_1); + Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_1); + status = Bootloader_loadCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1]); + } + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0))) + { + bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].clkHz = Bootloader_socCpuGetClkDefault(CSL_CORE_ID_R5FSS0_0); + Bootloader_profileAddCore(CSL_CORE_ID_R5FSS0_0); + /* Skip the image load by passing TRUE, so that image load on self core doesnt corrupt the SBLs IVT. Load the image later before the reset release of the self core */ + status = Bootloader_loadSelfCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0], TRUE); + } + Bootloader_profileAddProfilePoint("CPU load"); + Bootloader_profileUpdateAppimageSize(Bootloader_getMulticoreImageSize(bootHandle)); + QSPI_Handle qspiHandle = QSPI_getHandle(CONFIG_QSPI0); + Bootloader_profileUpdateMediaAndClk(BOOTLOADER_MEDIA_FLASH, QSPI_getInputClk(qspiHandle)); + + if(status == SystemP_SUCCESS) + { + Bootloader_profileAddProfilePoint("SBL End"); + Bootloader_profilePrintProfileLog(); + DebugP_log("Image loading done, switching to application ...\r\n"); + UART_flushTxFifo(gUartHandle[CONFIG_UART0]); + } + + /* Run CPUs */ + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_1))) + { + status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_1]); + } + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS1_0))) + { + status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS1_0]); + } + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_1))) + { + status = Bootloader_runCpu(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_1]); + } + if((status == SystemP_SUCCESS) && (TRUE == Bootloader_isCorePresent(bootHandle, CSL_CORE_ID_R5FSS0_0))) + { + /* Load the image on self core now */ + if( bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0].rprcOffset != BOOTLOADER_INVALID_ID) + { + status = Bootloader_rprcImageLoad(bootHandle, &bootImageInfo.cpuInfo[CSL_CORE_ID_R5FSS0_0]); + } + /* If any of the R5 core 0 have valid image reset the R5 core. */ + status = Bootloader_runSelfCpu(bootHandle, &bootImageInfo); + } + + /* it should not return here, if it does, then there was some error */ + Bootloader_close(bootHandle); + } + } + if(status != SystemP_SUCCESS ) + { + DebugP_log("Some tests have failed!!\r\n"); + } + Drivers_close(); + System_deinit(); + + return 0; +} + +/* SEND A UDP PACKET OVER ETHERNET */ + +void receiveAppImgOverEnet() +{ + int32_t status = SystemP_SUCCESS; + uint8_t done = false; + Bootloader_UniflashConfig uniflashConfig; + Bootloader_UniflashResponseHeader respHeader; + Bootloader_UniflashFileHeader *pktInfo; + +#if (ENETSBL_TRANSFER_START_MODE == ENETSBL_BUTTON_MODE) + /* Check if SW2 is pressed, if not skip the ethernet transfer */ + if(GPIO_pinRead(gGpioBaseAddr,pinNum) == GPIO_INTR_LEVEL_LOW) + { + DebugP_log("[ ENETSBL SKIP ] Skipping enet transfer.\r\n"); + done = true; + } +#endif + + if(!done) + { + DebugP_log("\r\n[ ENETSBL ] Starting Ethernet Transfer ...\r\n"); + + /* Initialize the C66x subsystem as the DSS_L3 memory is used to store the file to flash */ + Bootloader_socCpuPowerOnReset(CSL_CORE_ID_R5FSS0_0,NULL_PTR); + + /* Initialize sbl_enet config and setup ethernet peripheral */ + memset(&gEnetSBL_LLDObj, 0, sizeof(gEnetSBL_LLDObj)); + memset(&gEnetSBL_MetaObj, 0, sizeof(gEnetSBL_MetaObj)); + memset(&respHeader, 0, sizeof(respHeader)); + memset(&uniflashConfig, 0, sizeof(uniflashConfig)); + + status = EnetSBL_setup(); + + if(status == ENET_SOK) + { + /* Send ACK packet to let host know that EVM is linked up */ + respHeader.magicNumber = ENETSBL_HEADER_MGC_NUMBER; + respHeader.statusCode = ENETSBL_HEADER_ACK; + EnetSBL_txFlashResp(respHeader); + } + else if(status == ENET_ETIMEOUT) + { + DebugP_log("[ ENETSBL TIMEOUT ] Link Up Timeout. Please check ethernet cable connections.\r\n"); + done = true; + } + + while (!done) + { + /* Run SBL application */ + status = EnetSBL_transferAppimage(); + if(gFlashFileSize >= BOOTLOADER_MAX_FILE_SIZE) + { + /* Possible overflow, send error to host side */ + status = SystemP_FAILURE; + + respHeader.magicNumber = BOOTLOADER_UNIFLASH_RESP_HEADER_MAGIC_NUMBER; + respHeader.statusCode = BOOTLOADER_UNIFLASH_STATUSCODE_FLASH_ERROR; + + EnetSBL_txFlashResp(respHeader); + + /* Exit due to possible error */ + done = 1U; + DebugP_log("[ ENETSBL ERROR ] Overflow detected.\r\n"); + break; + } + + if(status == ENET_SOK) + { + uniflashConfig.flashIndex = CONFIG_FLASH0; + uniflashConfig.buf = gFlashFileBuf; + /* Actual fileSize will be parsed from the header */ + uniflashConfig.bufSize = 0; + uniflashConfig.verifyBuf = gFlashVerifyBuf; + uniflashConfig.verifyBufSize = BOOTLOADER_VERIFY_MAX_SIZE; + + /* Process the flash commands and return a response */ + status = Bootloader_uniflashProcessFlashCommands(&uniflashConfig, &respHeader); + + /* Exit if error or timeout; Send response to host */ + if (status != SystemP_SUCCESS) + { + DebugP_log("[ ENETSBL ERROR ] Uniflash timeout error.\r\n"); + done = 1U; + } + else + { + pktInfo = (Bootloader_UniflashFileHeader*) &gFlashFileBuf; + status = EnetSBL_txFlashResp(respHeader); + DebugP_log("[ ENETSBL SUCCESS ] Ethernet Transfer Done.\r\n"); + DebugP_log("[ ENETSBL ] Packets Received : %d \r\n",pktInfo->rsv1); + DebugP_log("[ ENETSBL ] Total File Size : %d Bytes\r\n",pktInfo->actualFileSize); + DebugP_log("[ ENETSBL ] Flash Offset : 0x%X\r\n\n",pktInfo->offset); + break; + } + } + else + { + DebugP_log("[ ENETSBL TIMEOUT ] Skipping enet transfer.\r\n"); + break; + } + } + + /* Close */ + EnetSBL_destruct(); + } +} diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c new file mode 100644 index 00000000000..1930920345c --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c @@ -0,0 +1,1401 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * \file sbl_enet.c + * + * \brief This file contains the ethernet SBL implementation. + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include "sbl_enet.h" +#include +#include +#include +#include "ti_enet_config.h" +#include +#include +#include "ti_enet_open_close.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +static void EnetSBL_timerCallback(ClockP_Object *clkInst, void* arg); + +static bool EnetSBL_parseFrame(EthFrame *frame, + uint32_t dataLen); + +static uint32_t EnetSBL_retrieveFreeTxPkts(void); + +static uint32_t EnetSBL_receivePkts(void); + +static void EnetSBL_initCpswCfg(Cpsw_Cfg *cpswCfg); + +static int32_t EnetSBL_setupCpswAle(void); + +static void EnetSBL_closeEnet(void); + +static int32_t EnetSBL_showAlivePhys(void); + +static int32_t EnetSBL_waitForLinkUp(void); + +static int32_t EnetSBL_macMode2PhyMii(emac_mode macMode, + EnetPhy_Mii *mii); + +static void EnetSBL_macMode2MacMii(emac_mode macMode, + EnetMacPort_Interface *mii); + +static void EnetSBL_rxIsrFxn(void *appData); + +static void EnetSBL_txIsrFxn(void *appData); + +static void EnetSBL_initPkt(EnetDma_Pkt *pPktInfo, + uint8_t *udpPayload); + +static void EnetSBL_initTxFreePktQ(void); + +static void EnetSBL_initRxReadyPktQ(void); + +static int32_t EnetSBL_openDma(void); + +static void EnetSBL_closeDma(void); + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +const EnetSBL_AddrInfo enetAppAddrInfo = +{ + .dstMac = ENET_HOST_PC_MAC_ADDRESS, + .srcIP = ENET_SOURCE_IP_ADDRESS, + .dstIP = ENET_DESTINATION_IP_ADDRESS, + .srcPortUDP = ENET_PORT, + .dstPortUDP = ENET_PORT, +}; + +const uint32_t EnetSBL_MagicNum = 0x05B1C00D; +const uint32_t EnetSBL_Ack = 0x05B10ACD; + +uint8_t gFlashFileBuf[BOOTLOADER_MAX_FILE_SIZE] __attribute__((aligned(128), section(".bss.dss_l3"))); +uint8_t gFlashVerifyBuf[BOOTLOADER_VERIFY_MAX_SIZE] __attribute__((aligned(128), section(".bss.sbl_scratch"))); +uint32_t gFlashFileSize; + +EnetSBL_LLDObj gEnetSBL_LLDObj; +EnetSBL_MetaObj gEnetSBL_MetaObj; + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +int32_t EnetSBL_setup(void) +{ + EnetApp_HandleInfo handleInfo; + int32_t status = 0; + + gEnetSBL_LLDObj.enetType =ENET_TYPE; + gEnetSBL_LLDObj.instId = ENET_INSTANCE_ID; + gEnetSBL_LLDObj.macPort = ENET_MAC_PORT_1; + gEnetSBL_LLDObj.macMode = RGMII; + gEnetSBL_LLDObj.boardId = ENETBOARD_CPB_ID; + gEnetSBL_LLDObj.testLoopBackType = TXSG_LOOPBACK_TYPE_NONE; + + + /* Create Global Event Object */ + status = EventP_construct(&gEnetSBL_LLDObj.appEvents); + DebugP_assert(SystemP_SUCCESS == status); + + /* Enable peripheral clocks */ + EnetAppUtils_enableClocks(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId); + + /* Create TX/RX semaphores */ + status = SemaphoreP_constructBinary(&gEnetSBL_LLDObj.rxSemObj, 0); + DebugP_assert(SystemP_SUCCESS == status); + + status = SemaphoreP_constructBinary(&gEnetSBL_LLDObj.txSemObj, 0); + DebugP_assert(SystemP_SUCCESS == status); + + /* Local core id */ + gEnetSBL_LLDObj.coreId = EnetSoc_getCoreId(); + EnetApp_driverInit(); + if (status == ENET_SOK) + { + status = EnetApp_driverOpen(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId); + + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to open Enet driver: %d\r\n", status); + } + } + + + EnetApp_acquireHandleInfo(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId, &handleInfo); + gEnetSBL_LLDObj.hEnet = handleInfo.hEnet; + if (status == ENET_SOK) + { + EnetPer_AttachCoreOutArgs attachCoreOutArgs; + + EnetApp_coreAttach(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId, gEnetSBL_LLDObj.coreId, &attachCoreOutArgs); + gEnetSBL_LLDObj.coreKey = attachCoreOutArgs.coreKey; + } + + /* Open DMA driver */ + if (status == ENET_SOK) + { + status = EnetSBL_openDma(); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to open DMA: %d\r\n", status); + } + } + + + /* Show alive PHYs */ + if (status == ENET_SOK) + { + status = EnetSBL_showAlivePhys(); + } + + EnetAppUtils_print("[ ENETSBL ] Please wait for Linkup ...\r\n"); + + /* Wait for link up */ + if (status == ENET_SOK) + { + EnetApp_initPhyStateHandlerTask(&gEnetSBL_LLDObj.appEvents); + status = EnetSBL_waitForLinkUp(); + } + + if(status != ENET_ETIMEOUT) + EnetAppUtils_print("[ ENETSBL ] Linkup Done!\r\n"); + + return status; +} + +void EnetSBL_destruct(void) +{ + Enet_IoctlPrms prms; + int32_t status = 0; + + /* Disable host port */ + ENET_IOCTL_SET_NO_ARGS(&prms); + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_HOSTPORT_IOCTL_DISABLE, &prms,status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to disable host port: %d\r\n", status); + } + + /* Stop periodic tick timer */ + ClockP_stop(&gEnetSBL_LLDObj.tickTimerObj); + + /* Close Enet DMA driver */ + EnetSBL_closeDma(); + + /* Close Enet driver */ + EnetSBL_closeEnet(); + + /* Disable peripheral clocks */ + EnetAppUtils_disableClocks(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId); + + /* Deinit Enet driver */ + Enet_deinit(); + + /* Delete all TX/RX semaphores */ + SemaphoreP_destruct(&gEnetSBL_LLDObj.rxSemObj); + SemaphoreP_destruct(&gEnetSBL_LLDObj.txSemObj); +} + + +int32_t EnetSBL_transferAppimage(void) +{ + EnetDma_Pkt *pktInfoRx; + EnetDma_Pkt *pktInfoTx; + EthFrame *frame; + uint32_t rxReadyCnt; + uint32_t txFreeCnt; + bool finished = false; + bool appPkt = false; + uint32_t currPktCnt = 0U; + uint32_t totalPktCnt = 0xFFFFFFFFU; + uint32_t waitCount = 0; + int32_t status = -1; + uint32_t EthPayloadLen = 0; + Bootloader_UniflashFileHeader *fileHeader; + + /* Set appimage packet number to 0 to start transfer */ + gEnetSBL_MetaObj.appPktNum = 0U; + + while(!finished) + { + // waitCount++; + if(waitCount > 1000 && (totalPktCnt == 0xFFFFFFFFU)) + { + break; + } + SemaphoreP_pend(&gEnetSBL_LLDObj.rxSemObj, SystemP_NO_WAIT); + /* Get the packets received so far */ + rxReadyCnt = EnetSBL_receivePkts(); + if (rxReadyCnt > 0U) + { + /* Consume the received packets and release them */ + pktInfoRx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.rxReadyQ); + while (NULL != pktInfoRx) + { + EnetDma_checkPktState(&pktInfoRx->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_READYQ, + ENET_PKTSTATE_APP_WITH_FREEQ); + + /* Consume the packet by just printing its content */ + EthPayloadLen = pktInfoRx->sgList.list[0].segmentFilledLen - ETH_HDR_SIZE - IPV4_HDR_SIZE - UDP_HDR_SIZE; + frame = (EthFrame *)pktInfoRx->sgList.list[0].bufPtr; + + appPkt = EnetSBL_parseFrame(frame, EthPayloadLen); + if(appPkt) + { + /* Check if seq. numbers match with expected and received */ + if (true /*gEnetSBL_MetaObj.appPktNum == currPktCnt*/) + { + if (currPktCnt == 0U) + { + /* Initialize total pkt count from pkt 0 */ + /* It is stored in the rsv1 (reserved) field of the Uniflash header */ + gFlashFileSize = 0U; + fileHeader = (Bootloader_UniflashFileHeader*) &gEnetSBL_MetaObj.appPktData[MGC_NUM_SIZE+SEQ_NUM_SIZE]; + totalPktCnt = fileHeader->rsv1; + EnetAppUtils_print("[ ENETSBL ] Receiving file, please wait ...\r\n"); + } + /* Copy pkt contents to appimage buffer and increase file size */ + + /* TODO, REPLACE WRITING FILE INTO QSPI DIRECTLY INSTEAD OF MEMCPY INTO OCRAM */ + // memcpy(&gFlashFileBuf[gFlashFileSize], &gEnetSBL_MetaObj.appPktData[MGC_NUM_SIZE+SEQ_NUM_SIZE], (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE)); + // gFlashFileSize += (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE); + + /* Fill the TX payload with seq number and ACK code */ + memcpy(&gEnetSBL_MetaObj.txPayload[0], &currPktCnt, sizeof(currPktCnt)); + memcpy(&gEnetSBL_MetaObj.txPayload[sizeof(currPktCnt)], &EnetSBL_Ack, sizeof(EnetSBL_Ack)); + + /* Get free tx packet from queue */ + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + while (pktInfoTx == NULL) + { + txFreeCnt = EnetSBL_retrieveFreeTxPkts(); + if (txFreeCnt == 0) + { + SemaphoreP_pend(&gEnetSBL_LLDObj.txSemObj, SystemP_WAIT_FOREVER); + } + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + } + + /* Init TX packet header */ + EnetSBL_initPkt(pktInfoTx, gEnetSBL_MetaObj.txPayload); + + EnetDma_checkPktState(&pktInfoTx->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_FREEQ, + ENET_PKTSTATE_APP_WITH_DRIVER); + + /* Submit TX packet */ + status = EnetDma_submitTxPkt(gEnetSBL_LLDObj.hTxCh, + pktInfoTx); + + currPktCnt += 1U; + + /* Check for finish */ + if(currPktCnt >= totalPktCnt) + { + finished = true; + } + } + else + { + /* Check if the packet number received is for previous packet, indicating that + * the ACK (or this is second iteration of same packet) got lost in transit + * and hence the host re-transmitted it due to timeout */ + DebugP_assert(gEnetSBL_MetaObj.appPktNum == currPktCnt-1); + + uint32_t tempCurrPktCnt = currPktCnt-1; + + /* Fill the TX payload with prev seq number and ACK code */ + memcpy(&gEnetSBL_MetaObj.txPayload[0], &tempCurrPktCnt, sizeof(tempCurrPktCnt)); + memcpy(&gEnetSBL_MetaObj.txPayload[sizeof(tempCurrPktCnt)], &EnetSBL_Ack, sizeof(EnetSBL_Ack)); + + /* Get free tx packet from queue */ + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + while (pktInfoTx == NULL) + { + txFreeCnt = EnetSBL_retrieveFreeTxPkts(); + if (txFreeCnt == 0) + { + SemaphoreP_pend(&gEnetSBL_LLDObj.txSemObj, SystemP_WAIT_FOREVER); + } + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + } + + /* Init TX packet header */ + EnetSBL_initPkt(pktInfoTx, gEnetSBL_MetaObj.txPayload); + + EnetDma_checkPktState(&pktInfoTx->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_FREEQ, + ENET_PKTSTATE_APP_WITH_DRIVER); + + /* Submit TX packet */ + status = EnetDma_submitTxPkt(gEnetSBL_LLDObj.hTxCh, + pktInfoTx); + } + } + + /* Release the received packet */ + EnetQueue_enq(&gEnetSBL_LLDObj.rxFreeQ, &pktInfoRx->node); + pktInfoRx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.rxReadyQ); + + if(finished) + { + status = ENET_SOK; + break; + } + } + + /*Submit now processed buffers */ + if (status == ENET_SOK) + { + EnetAppUtils_validatePacketState(&gEnetSBL_LLDObj.rxFreeQ, + ENET_PKTSTATE_APP_WITH_FREEQ, + ENET_PKTSTATE_APP_WITH_DRIVER); + EnetDma_submitRxPktQ(gEnetSBL_LLDObj.hRxCh, + &gEnetSBL_LLDObj.rxFreeQ); + } + } + } + + return ENET_EFAIL; /* send actual status instead of failure when ethernet image is received */ +} + +int32_t EnetSBL_txFlashResp(Bootloader_UniflashResponseHeader respHeader) +{ + EnetDma_Pkt *pktInfoTx; + uint32_t txFreeCnt; + int32_t status = ENET_SOK; + + /* Fill the TX payload with seq number and ACK code */ + memcpy(&gEnetSBL_MetaObj.txPayload[0], &respHeader, sizeof(respHeader)); + + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + while (pktInfoTx == NULL) + { + txFreeCnt = EnetSBL_retrieveFreeTxPkts(); + if (txFreeCnt == 0) + { + SemaphoreP_pend(&gEnetSBL_LLDObj.txSemObj, SystemP_WAIT_FOREVER); + } + pktInfoTx = (EnetDma_Pkt *)EnetQueue_deq(&gEnetSBL_LLDObj.txFreePktInfoQ); + } + + /* Init TX packet header */ + EnetSBL_initPkt(pktInfoTx, gEnetSBL_MetaObj.txPayload); + + EnetDma_checkPktState(&pktInfoTx->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_FREEQ, + ENET_PKTSTATE_APP_WITH_DRIVER); + + /* Submit TX packet */ + status = EnetDma_submitTxPkt(gEnetSBL_LLDObj.hTxCh, + pktInfoTx); + return status; +} + +/* ========================================================================== */ +/* Static Function Definitions */ +/* ========================================================================== */ + +static uint32_t EnetSBL_retrieveFreeTxPkts(void) +{ + EnetDma_PktQ txFreeQ; + EnetDma_Pkt *pktInfo; + int32_t status = 0; + uint32_t txFreeQCnt = 0U; + + EnetQueue_initQ(&txFreeQ); + + /* Retrieve any CPSW packets that may be free now */ + status = EnetDma_retrieveTxPktQ(gEnetSBL_LLDObj.hTxCh, &txFreeQ); + + /* Push them into application object's free queue */ + if (status == ENET_SOK) + { + txFreeQCnt = EnetQueue_getQCount(&txFreeQ); + + pktInfo = (EnetDma_Pkt *)EnetQueue_deq(&txFreeQ); + while (NULL != pktInfo) + { + EnetDma_checkPktState(&pktInfo->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_DRIVER, + ENET_PKTSTATE_APP_WITH_FREEQ); + EnetQueue_enq(&gEnetSBL_LLDObj.txFreePktInfoQ, &pktInfo->node); + pktInfo = (EnetDma_Pkt *)EnetQueue_deq(&txFreeQ); + } + } + + else + { + EnetAppUtils_print("[ ENETSBL ] retrieveFreeTxPkts() failed to retrieve pkts: %d\r\n", + status); + } + + /* Return number of free packets retrieved */ + return txFreeQCnt; +} + +static uint32_t EnetSBL_receivePkts(void) +{ + EnetDma_PktQ rxReadyQ; + EnetDma_Pkt *pktInfo; + int32_t status = 0; + uint32_t rxReadyCnt = 0U; + + EnetQueue_initQ(&rxReadyQ); + + /* Retrieve any CPSW packets which are ready */ + status = EnetDma_retrieveRxPktQ(gEnetSBL_LLDObj.hRxCh, &rxReadyQ); + if (status == ENET_SOK) + { + rxReadyCnt = EnetQueue_getQCount(&rxReadyQ); + + /* Queue the received packet to rxReadyQ and pass new ones from rxFreeQ */ + pktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rxReadyQ); + while (pktInfo != NULL) + { + EnetDma_checkPktState(&pktInfo->pktState, + ENET_PKTSTATE_MODULE_APP, + ENET_PKTSTATE_APP_WITH_DRIVER, + ENET_PKTSTATE_APP_WITH_READYQ); + + EnetQueue_enq(&gEnetSBL_LLDObj.rxReadyQ, &pktInfo->node); + pktInfo = (EnetDma_Pkt *)EnetQueue_deq(&rxReadyQ); + } + } + else + { + EnetAppUtils_print("[ ENETSBL ] receivePkts() failed to retrieve pkts: %d\r\n", status); + } + + EnetAppUtils_print("[ ENETSBL ] receivePkts() failed to retrieve pkts: %d\r\n", status); + return rxReadyCnt; +} + +static void EnetSBL_initCpswCfg(Cpsw_Cfg *cpswCfg) +{ + CpswHostPort_Cfg *hostPortCfg = &cpswCfg->hostPortCfg; + CpswAle_Cfg *aleCfg = &cpswCfg->aleCfg; + CpswCpts_Cfg *cptsCfg = &cpswCfg->cptsCfg; + + /* Set initial config */ + Enet_initCfg(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId, cpswCfg, sizeof(*cpswCfg)); + + /* Peripheral config */ + cpswCfg->vlanCfg.vlanAware = false; + + /* Host port config */ + hostPortCfg->removeCrc = true; + hostPortCfg->padShortPacket = true; + hostPortCfg->passCrcErrors = true; + + /* ALE config */ + aleCfg->modeFlags = CPSW_ALE_CFG_MODULE_EN; + aleCfg->agingCfg.autoAgingEn = false; + aleCfg->agingCfg.agingPeriodInMs = 1000; + aleCfg->nwSecCfg.vid0ModeEn = true; + aleCfg->vlanCfg.aleVlanAwareMode = false; + aleCfg->vlanCfg.cpswVlanAwareMode = false; + aleCfg->vlanCfg.unknownUnregMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK; + aleCfg->vlanCfg.unknownRegMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK; + aleCfg->vlanCfg.unknownVlanMemberListMask = CPSW_ALE_ALL_PORTS_MASK; + + /* CPTS config */ + /* Note: Timestamping and MAC txsg are not supported together because of + * IP limitation, so disabling timestamping for this application */ + cptsCfg->hostRxTsEn = false; + + EnetAppUtils_initResourceConfig(ENET_TYPE, gEnetSBL_LLDObj.coreId, &cpswCfg->resCfg); +} + +static int32_t EnetSBL_setupCpswAle(void) +{ + Enet_IoctlPrms prms; + CpswAle_SetPortStateInArgs setPortStateInArgs; + CpswAle_SetUcastEntryInArgs setUcastInArgs; + uint32_t entryIdx; + int32_t status = 0; + + /* ALE entry with "secure" bit cleared is required */ + setUcastInArgs.addr.vlanId = 0U; + setUcastInArgs.info.portNum = CPSW_ALE_HOST_PORT_NUM; + setUcastInArgs.info.blocked = false; + setUcastInArgs.info.secure = false; + setUcastInArgs.info.super = false; + setUcastInArgs.info.ageable = false; + setUcastInArgs.info.trunk = false; + EnetUtils_copyMacAddr(&setUcastInArgs.addr.addr[0U], gEnetSBL_LLDObj.hostMacAddr); + ENET_IOCTL_SET_INOUT_ARGS(&prms, &setUcastInArgs, &entryIdx); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, CPSW_ALE_IOCTL_ADD_UCAST, &prms,status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to add ucast entry: %d\r\n", status); + } + + /* Set host port to 'forwarding' state */ + if (status == ENET_SOK) + { + setPortStateInArgs.portNum = CPSW_ALE_HOST_PORT_NUM; + setPortStateInArgs.portState = CPSW_ALE_PORTSTATE_FORWARD; + ENET_IOCTL_SET_IN_ARGS(&prms, &setPortStateInArgs); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, CPSW_ALE_IOCTL_SET_PORT_STATE, &prms,status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to set ALE port state: %d\r\n", status); + } + } + return status; +} + + +static void EnetSBL_closeEnet(void) +{ + Enet_IoctlPrms prms; + int32_t status = 0; + + /* Close port link */ + ENET_IOCTL_SET_IN_ARGS(&prms, &gEnetSBL_LLDObj.macPort); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_PER_IOCTL_CLOSE_PORT_LINK, &prms,status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to close port link: %d\r\n", status); + } + + /* Close Enet driver */ + Enet_close(gEnetSBL_LLDObj.hEnet); + + gEnetSBL_LLDObj.hEnet = NULL; +} + +static int32_t EnetSBL_showAlivePhys(void) +{ + Enet_IoctlPrms prms; + bool alive = false; + int32_t status; + + for (uint32_t phyAdd = 0U; phyAdd < ENET_MDIO_PHY_CNT_MAX; phyAdd++) + { + EnetApp_phyStateHandler(); + ENET_IOCTL_SET_INOUT_ARGS(&prms, &phyAdd, &alive); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_MDIO_IOCTL_IS_ALIVE, &prms,status); + if (status == ENET_SOK) + { + if (alive == true) + { + EnetAppUtils_print("[ ENETSBL ] PHY %u is alive\r\n", phyAdd); + } + } + else + { + EnetAppUtils_print("[ ENETSBL ] Failed to get PHY %u alive status: %d\r\n", phyAdd, status); + } + } + + return status; +} + +static int32_t EnetSBL_waitForLinkUp(void) +{ + Enet_IoctlPrms prms; + bool linked = false; + int32_t status = ENET_SOK; + uint8_t linkUpWaitCount = 0; + + while (!linked) + { + EnetApp_phyStateHandler(); + ENET_IOCTL_SET_INOUT_ARGS(&prms, &gEnetSBL_LLDObj.macPort, &linked); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_PER_IOCTL_IS_PORT_LINK_UP, &prms, status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to get port link status: %d\r\n", status); + linked = false; + break; + } + + if (!linked) + { + ClockP_usleep(50000U); + linkUpWaitCount++; + if(linkUpWaitCount > 200) + { + status = ENET_ETIMEOUT; + break; + } + } + } + /* Sleep for 2 sec to complete host PC link up */ + ClockP_sleep(2U); + return status; +} + + +static int32_t EnetSBL_macMode2PhyMii(emac_mode macMode, + EnetPhy_Mii *mii) +{ + int32_t status = ENET_SOK; + + switch (macMode) + { + case RMII: + *mii = ENETPHY_MAC_MII_RMII; + break; + case RGMII: + *mii = ENETPHY_MAC_MII_RGMII; + break; + default: + status = ENET_EFAIL; + EnetAppUtils_print("[ ENETSBL ] Invalid MAC mode: %u\r\n", macMode); + EnetAppUtils_assert(false); + break; + } + + return status; +} + +static void EnetSBL_macMode2MacMii(emac_mode macMode, + EnetMacPort_Interface *mii) +{ + switch (macMode) + { + case RMII: + mii->layerType = ENET_MAC_LAYER_MII; + mii->sublayerType = ENET_MAC_SUBLAYER_REDUCED; + mii->variantType = ENET_MAC_VARIANT_NONE; + break; + case RGMII: + mii->layerType = ENET_MAC_LAYER_GMII; + mii->sublayerType = ENET_MAC_SUBLAYER_REDUCED; + mii->variantType = ENET_MAC_VARIANT_FORCED; + break; + default: + EnetAppUtils_print("[ ENETSBL ] Invalid MAC mode: %u\r\n", macMode); + EnetAppUtils_assert(false); + break; + } +} + +static void EnetSBL_rxIsrFxn(void *appData) +{ + gEnetSBL_LLDObj.rxIsrCount++; + SemaphoreP_post(&gEnetSBL_LLDObj.rxSemObj); +} + +static void EnetSBL_txIsrFxn(void *appData) +{ + gEnetSBL_LLDObj.txIsrCount++; + SemaphoreP_post(&gEnetSBL_LLDObj.txSemObj); +} + +#define ENET_LPBK_ETHERTYPE_IPV4 (0x0800) + +void EnetApp_initEthFrameHdr(uint8_t *bufPtr, uint32_t *len) +{ + EthFrame *frame; + + frame = (EthFrame *)bufPtr; + memcpy(frame->hdr.dstMac, enetAppAddrInfo.dstMac, ENET_MAC_ADDR_LEN); + *len += ENET_MAC_ADDR_LEN; + memcpy(frame->hdr.srcMac, &gEnetSBL_LLDObj.hostMacAddr[0U], ENET_MAC_ADDR_LEN); + *len += ENET_MAC_ADDR_LEN; + frame->hdr.etherType = Enet_htons(ENET_LPBK_ETHERTYPE_IPV4); + *len += sizeof(frame->hdr.etherType); +} + + +static bool EnetApp_verifyIPv4Checksum(uint16_t *header) +{ + uint32_t i; + uint32_t sum = 0U; + + for(i = 0U; i < sizeof(EthAppIPv4Header)/2; i+=1) + { + sum += header[i]; + } + + /* Add the carries from top 16-bits */ + while (sum >> 16) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + return (sum == 0xFFFFU); +} + +static uint16_t EnetApp_calcIPv4Checksum(uint8_t src_ip[IPV4_ADDR_LEN], uint8_t dest_ip[IPV4_ADDR_LEN]) +{ + uint32_t sum = (uint16_t)((IPV4_HDR_VER_IHL << 8) | IPV4_HDR_TOS) + (uint16_t)(IPV4_HDR_TOTAL_PKT_LEN) + (uint16_t)(IPV4_HDR_IPID) + (uint16_t)(IPV4_HDR_FLAGFRAFOFFSET) + (uint16_t)((IPV4_HDR_TTL << 8) | IPV4_HDR_UDP); + uint32_t i; + + /* Add source IP addr*/ + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)src_ip[i] << 8) | (uint32_t)src_ip[i+1]); + } + + /* Add destination IP addr*/ + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)dest_ip[i] << 8) | (uint32_t)dest_ip[i+1]); + } + + /* Add the carries from top 16-bits */ + while (sum >> 16) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + /* Return the one's complement of sum */ + return (uint16_t)((~sum) & 0xFFFF); +} + +void EnetApp_initIPv4Hdr(uint8_t *bufPtr, uint32_t *len) +{ + EthAppIPv4Header *ipv4Hdr; + + ipv4Hdr = (EthAppIPv4Header *)bufPtr; + ipv4Hdr->verIHL = IPV4_HDR_VER_IHL; + ipv4Hdr->tos = IPV4_HDR_TOS; + ipv4Hdr->totalPktLen = Enet_htons(IPV4_HDR_TOTAL_PKT_LEN); + ipv4Hdr->ipId = Enet_htons(IPV4_HDR_IPID); + ipv4Hdr->flagFragOffset = Enet_htons(IPV4_HDR_FLAGFRAFOFFSET); + ipv4Hdr->ttl = IPV4_HDR_TTL; + ipv4Hdr->protocol = IPV4_HDR_UDP; + ipv4Hdr->hdrChksum = Enet_htons(EnetApp_calcIPv4Checksum((uint8_t*)enetAppAddrInfo.srcIP, (uint8_t*)enetAppAddrInfo.dstIP)); + memcpy(&ipv4Hdr->srcIP,enetAppAddrInfo.srcIP,sizeof(ipv4Hdr->srcIP)); + memcpy(&ipv4Hdr->dstIP,enetAppAddrInfo.dstIP,sizeof(ipv4Hdr->dstIP)); + *len += sizeof(EthAppIPv4Header); +} + +static bool EnetApp_verifyUDPChecksum(EthAppIPv4Header *ipv4Hdr, EthAppUDPHeader *udpHdr, uint8_t *data_payload) +{ + uint8_t *payload = data_payload; + uint32_t sum = 0U; + uint32_t i; + uint32_t length = (uint32_t)Enet_ntohs(udpHdr->length); + + /* Add the pseudo-header */ + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)ipv4Hdr->srcIP[i] << 8) | (uint32_t)ipv4Hdr->srcIP[i+1]); + } + + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)ipv4Hdr->dstIP[i] << 8) | (uint32_t)ipv4Hdr->dstIP[i+1]); + } + + sum += ipv4Hdr->protocol; + sum += Enet_ntohs(udpHdr->length); + sum += Enet_ntohs(udpHdr->srcPort); + sum += Enet_ntohs(udpHdr->dstPort); + sum += Enet_ntohs(udpHdr->length); + sum += Enet_ntohs(udpHdr->csum); + + /* Add payload */ + while (length > sizeof(EthAppUDPHeader)+1) + { + sum += ((uint32_t)*(payload) << 8) | (uint32_t)*(payload + 1); + payload += 2; + + /* If 32-bit number going to overflow, add accumulated carries from top 16-bits */ + if (sum & 0x80000000) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + length -= 2; + } + + if (Enet_ntohs(udpHdr->length) & 1) + { + /* Add padding if the packet length is odd */ + sum += ((uint32_t)*(payload) << 8); + } + + /* Add the carries from top 16-bits */ + while (sum >> 16) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + return (sum == 0xFFFFU); +} + +static uint16_t EnetApp_calcUDPChecksum(uint8_t src_ip[IPV4_ADDR_LEN], uint16_t src_port, uint8_t dest_ip[IPV4_ADDR_LEN], uint16_t dest_port, uint16_t ip_protocol, uint16_t len, uint8_t *data_payload) +{ + uint8_t *payload = data_payload; + uint32_t sum = 0U; + uint32_t i; + uint32_t length = (uint32_t)len; + + /* Add the pseudo-header */ + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)src_ip[i] << 8) | (uint32_t)src_ip[i+1]); + } + + for(i = 0U; i < IPV4_ADDR_LEN; i+=2) + { + sum += (((uint32_t)dest_ip[i] << 8) | (uint32_t)dest_ip[i+1]); + } + + sum += ip_protocol; + sum += len; + sum += src_port; + sum += dest_port; + sum += len; + + /* Add payload */ + while (length > sizeof(EthAppUDPHeader)+1) + { + sum += ((uint32_t)*(payload) << 8) | (uint32_t)*(payload + 1); + payload += 2; + + /* If 32-bit number going to overflow, add accumulated carries from top 16-bits */ + if (sum & 0x80000000) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + length -= 2; + } + + if (len & 1) + { + /* Add padding if the packet length is odd */ + sum += ((uint32_t)*(payload) << 8); + } + + /* Add the carries from top 16-bits */ + while (sum >> 16) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + + /* Return the one's complement of sum */ + return (uint16_t)((~sum) & 0xFFFF); +} + +static void EnetApp_initUDPHdr(uint8_t *bufPtr, uint32_t *len, uint8_t *payload) +{ + EthAppUDPHeader *udpHdr; + + udpHdr = (EthAppUDPHeader *)bufPtr; + udpHdr->srcPort = Enet_htons(enetAppAddrInfo.srcPortUDP); + udpHdr->dstPort = Enet_htons(enetAppAddrInfo.dstPortUDP); + udpHdr->length = Enet_htons(UDP_PKT_LEN); + udpHdr->csum = Enet_htons(EnetApp_calcUDPChecksum((uint8_t*)enetAppAddrInfo.srcIP, + enetAppAddrInfo.srcPortUDP, + (uint8_t*)enetAppAddrInfo.dstIP, + enetAppAddrInfo.dstPortUDP, + (uint16_t)IPV4_HDR_UDP, + (uint16_t)UDP_PKT_LEN, + payload)); + *len += sizeof(EthAppUDPHeader); +} + +static void EnetSBL_initPkt(EnetDma_Pkt *pPktInfo, uint8_t *udpPayload) +{ + uint32_t len; + + len = 0; + EnetApp_initEthFrameHdr(&gEnetSBL_MetaObj.appPktHeader[len], &len); + EnetApp_initIPv4Hdr(&gEnetSBL_MetaObj.appPktHeader[len], &len); + EnetApp_initUDPHdr(&gEnetSBL_MetaObj.appPktHeader[len], &len, &udpPayload[0]); + pPktInfo->chkSumInfo = 0U; + pPktInfo->sgList.list[0].segmentFilledLen = len; + pPktInfo->appPriv = &gEnetSBL_LLDObj; + pPktInfo->sgList.numScatterSegments = 2; + pPktInfo->sgList.list[1].bufPtr = udpPayload; + pPktInfo->sgList.list[1].segmentFilledLen = IPV4_HDR_TOTAL_PKT_LEN - (sizeof(EthAppUDPHeader) + sizeof(EthAppIPv4Header)); + pPktInfo->sgList.list[0].bufPtr = &gEnetSBL_MetaObj.appPktHeader[0]; + pPktInfo->sgList.list[0].disableCacheOps = true; + CacheP_wbInv(pPktInfo->sgList.list[0].bufPtr, len, CacheP_TYPE_ALLD); + pPktInfo->sgList.list[1].disableCacheOps = true; + CacheP_wbInv(pPktInfo->sgList.list[1].bufPtr, (IPV4_HDR_TOTAL_PKT_LEN - (sizeof(EthAppUDPHeader) + sizeof(EthAppIPv4Header))), CacheP_TYPE_ALLD); +} + +static void EnetSBL_initTxFreePktQ(void) +{ + EnetDma_Pkt *pPktInfo; + uint32_t i; + uint32_t scatterSegments[] = { ENET_MEM_LARGE_POOL_PKT_SIZE }; + + /* Initialize all queues */ + EnetQueue_initQ(&gEnetSBL_LLDObj.txFreePktInfoQ); + + /* Initialize TX EthPkts and queue them to txFreePktInfoQ */ + for (i = 0U; i < ENET_SYSCFG_TOTAL_NUM_TX_PKT; i++) + { + pPktInfo = EnetMem_allocEthPkt(&gEnetSBL_LLDObj, + ENETDMA_CACHELINE_ALIGNMENT, + ENET_ARRAYSIZE(scatterSegments), + scatterSegments); + EnetAppUtils_assert(pPktInfo != NULL); + ENET_UTILS_SET_PKT_APP_STATE(&pPktInfo->pktState, ENET_PKTSTATE_APP_WITH_FREEQ); + EnetDma_initPktInfo(pPktInfo); + + EnetQueue_enq(&gEnetSBL_LLDObj.txFreePktInfoQ, &pPktInfo->node); + } + + EnetAppUtils_print("[ ENETSBL ] initQs() txFreePktInfoQ initialized with %d pkts\r\n", + EnetQueue_getQCount(&gEnetSBL_LLDObj.txFreePktInfoQ)); +} + +static void EnetSBL_initRxReadyPktQ(void) +{ + EnetDma_PktQ rxReadyQ; + EnetDma_Pkt *pPktInfo; + int32_t status; + uint32_t i; + uint32_t scatterSegments[] = { ENET_MEM_LARGE_POOL_PKT_SIZE }; + + EnetQueue_initQ(&gEnetSBL_LLDObj.rxFreeQ); + EnetQueue_initQ(&gEnetSBL_LLDObj.rxReadyQ); + EnetQueue_initQ(&rxReadyQ); + + for (i = 0U; i < ENET_SYSCFG_TOTAL_NUM_RX_PKT; i++) + { + pPktInfo = EnetMem_allocEthPkt(&gEnetSBL_LLDObj, + ENETDMA_CACHELINE_ALIGNMENT, + ENET_ARRAYSIZE(scatterSegments), + scatterSegments); + EnetAppUtils_assert(pPktInfo != NULL); + ENET_UTILS_SET_PKT_APP_STATE(&pPktInfo->pktState, ENET_PKTSTATE_APP_WITH_FREEQ); + EnetQueue_enq(&gEnetSBL_LLDObj.rxFreeQ, &pPktInfo->node); + } + + /* Retrieve any CPSW packets which are ready */ + status = EnetDma_retrieveRxPktQ(gEnetSBL_LLDObj.hRxCh, &rxReadyQ); + EnetAppUtils_assert(status == ENET_SOK); + /* There should not be any packet with DMA during init */ + EnetAppUtils_assert(EnetQueue_getQCount(&rxReadyQ) == 0U); + + EnetAppUtils_validatePacketState(&gEnetSBL_LLDObj.rxFreeQ, + ENET_PKTSTATE_APP_WITH_FREEQ, + ENET_PKTSTATE_APP_WITH_DRIVER); + + EnetDma_submitRxPktQ(gEnetSBL_LLDObj.hRxCh, + &gEnetSBL_LLDObj.rxFreeQ); + + /* Assert here as during init no. of DMA descriptors should be equal to + * no. of free Ethernet buffers available with app */ + + EnetAppUtils_assert(0U == EnetQueue_getQCount(&gEnetSBL_LLDObj.rxFreeQ)); +} + +static int32_t EnetSBL_openDma(void) +{ + int32_t status = ENET_SOK; + + /* Open the CPSW TX channel */ + if (status == ENET_SOK) + { + EnetApp_GetDmaHandleInArgs txInArgs; + EnetApp_GetTxDmaHandleOutArgs txChInfo; + + txInArgs.cbArg = &gEnetSBL_LLDObj; + txInArgs.notifyCb = EnetSBL_txIsrFxn; + + EnetApp_getTxDmaHandle(ENET_DMA_TX_CH0, + &txInArgs, + &txChInfo); + + gEnetSBL_LLDObj.txChNum = txChInfo.txChNum; + gEnetSBL_LLDObj.hTxCh = txChInfo.hTxCh; + + gEnetSBL_LLDObj.txIsrCount = 0; + EnetSBL_initTxFreePktQ(); + + if (NULL != gEnetSBL_LLDObj.hTxCh) + { + status = ENET_SOK; + if (ENET_SOK != status) + { + EnetAppUtils_print("[ ENETSBL ] EnetUdma_startTxCh() failed: %d\r\n", status); + status = ENET_EFAIL; + } + } + else + { + EnetAppUtils_print("[ ENETSBL ] EnetDma_openTxCh() failed to open: %d\r\n", + status); + status = ENET_EFAIL; + } + } + + /* Open the CPSW RX flow */ + if (status == ENET_SOK) + { + EnetApp_GetRxDmaHandleOutArgs rxChInfo; + EnetApp_GetDmaHandleInArgs rxInArgs; + + rxInArgs.notifyCb = EnetSBL_rxIsrFxn; + rxInArgs.cbArg = &gEnetSBL_LLDObj; + + EnetApp_getRxDmaHandle(ENET_DMA_RX_CH0, + &rxInArgs, + &rxChInfo); + gEnetSBL_LLDObj.rxChNum = rxChInfo.rxChNum; + gEnetSBL_LLDObj.hRxCh = rxChInfo.hRxCh; + EnetAppUtils_assert(rxChInfo.numValidMacAddress == 1); + + if (NULL == gEnetSBL_LLDObj.hRxCh) + { + EnetAppUtils_print("[ ENETSBL ] EnetDma_openRxCh() failed to open: %d\r\n", + status); + EnetAppUtils_assert(NULL != gEnetSBL_LLDObj.hRxCh); + } + else + { + EnetAppUtils_assert(rxChInfo.numValidMacAddress > 0); + EnetUtils_copyMacAddr(gEnetSBL_LLDObj.hostMacAddr, rxChInfo.macAddr[rxChInfo.numValidMacAddress - 1]); + EnetAppUtils_print("[ ENETSBL ] EVM MAC address: "); + EnetAppUtils_printMacAddr(gEnetSBL_LLDObj.hostMacAddr); + gEnetSBL_LLDObj.rxIsrCount = 0; + /* Submit all ready RX buffers to DMA.*/ + EnetSBL_initRxReadyPktQ(); + } + } + + return status; +} + +static void EnetSBL_closeDma(void) +{ + EnetDma_PktQ fqPktInfoQ; + EnetDma_PktQ cqPktInfoQ; + + EnetQueue_initQ(&fqPktInfoQ); + EnetQueue_initQ(&cqPktInfoQ); + + + /* There should not be any ready packet */ + EnetAppUtils_assert(0U == EnetQueue_getQCount(&gEnetSBL_LLDObj.rxReadyQ)); + + /* Close RX channel */ + EnetApp_closeRxDma(ENET_DMA_RX_CH0, + gEnetSBL_LLDObj.hEnet, + gEnetSBL_LLDObj.coreKey, + gEnetSBL_LLDObj.coreId, + &fqPktInfoQ, + &cqPktInfoQ); + + EnetAppUtils_freePktInfoQ(&fqPktInfoQ); + EnetAppUtils_freePktInfoQ(&cqPktInfoQ); + + /* Close TX channel */ + EnetQueue_initQ(&fqPktInfoQ); + EnetQueue_initQ(&cqPktInfoQ); + + EnetApp_closeTxDma(ENET_DMA_TX_CH0, + gEnetSBL_LLDObj.hEnet, + gEnetSBL_LLDObj.coreKey, + gEnetSBL_LLDObj.coreId, + &fqPktInfoQ, + &cqPktInfoQ); + + EnetAppUtils_freePktInfoQ(&fqPktInfoQ); + EnetAppUtils_freePktInfoQ(&cqPktInfoQ); + + EnetAppUtils_freePktInfoQ(&gEnetSBL_LLDObj.rxFreeQ); + EnetAppUtils_freePktInfoQ(&gEnetSBL_LLDObj.txFreePktInfoQ); + +} + +static void EnetSBL_printFrame(EthFrame *frame, EthAppIPv4Header *ipv4Frame, EthAppUDPHeader *udpFrame, uint32_t dataLen) +{ + uint32_t i; + EnetAppUtils_print("[ ENETSBL ] ============================================\r\n"); + EnetAppUtils_print("[ ENETSBL ] FRAME HEADER\r\n"); + EnetAppUtils_print("[ ENETSBL ] ------------\r\n"); + + /* ETH Frame Header */ + EnetAppUtils_print("[ ENETSBL ] Dst addr : "); + EnetAppUtils_printMacAddr(&frame->hdr.dstMac[0]); + EnetAppUtils_print("[ ENETSBL ] Src addr : "); + EnetAppUtils_printMacAddr(&frame->hdr.srcMac[0]); + EnetAppUtils_print("[ ENETSBL ] EtherType: 0x%04x\r\n", Enet_ntohs(frame->hdr.etherType) & 0xFFFFU); + + /* IPv4 Frame Header */ + EnetAppUtils_print("[ ENETSBL ] Version : 0x%02x\r\n", ipv4Frame->verIHL & 0xFFU); + EnetAppUtils_print("[ ENETSBL ] TOS : 0x%02x\r\n", ipv4Frame->tos & 0xFFU); + EnetAppUtils_print("[ ENETSBL ] Total Packet Len : 0x%04x (%d)\r\n", + Enet_htons(ipv4Frame->totalPktLen) & 0xFFFFU, + Enet_htons(ipv4Frame->totalPktLen) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] IP ID : 0x%04x\r\n", Enet_htons(ipv4Frame->ipId) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] Flag/Fragmentation Offset : 0x%04x\r\n", Enet_htons(ipv4Frame->flagFragOffset) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] TTL : 0x%02x\r\n", ipv4Frame->ttl & 0xFFU); + EnetAppUtils_print("[ ENETSBL ] Protocol : 0x%02x\r\n", ipv4Frame->protocol & 0xFFU); + EnetAppUtils_print("[ ENETSBL ] Checksum : 0x%04x\r\n", Enet_htons(ipv4Frame->hdrChksum) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] Src IP addr : %d.%d.%d.%d\r\n", + ipv4Frame->srcIP[0] & 0xFF, + ipv4Frame->srcIP[1] & 0xFF, + ipv4Frame->srcIP[2] & 0xFF, + ipv4Frame->srcIP[3] & 0xFF); + EnetAppUtils_print("[ ENETSBL ] Dest IP addr : %d.%d.%d.%d\r\n", + ipv4Frame->dstIP[0] & 0xFF, + ipv4Frame->dstIP[1] & 0xFF, + ipv4Frame->dstIP[2] & 0xFF, + ipv4Frame->dstIP[3] & 0xFF); + + /* UDP Frame Header */ + EnetAppUtils_print("[ ENETSBL ] Source Port : 0x%04x (%d)\r\n", + Enet_htons(udpFrame->srcPort) & 0xFFFFU, + Enet_htons(udpFrame->srcPort) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] Destin Port : 0x%04x (%d)\r\n", + Enet_htons(udpFrame->dstPort) & 0xFFFFU, + Enet_htons(udpFrame->dstPort) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] Length : 0x%04x (%d)\r\n", + Enet_htons(udpFrame->length) & 0xFFFFU, + Enet_htons(udpFrame->length) & 0xFFFFU); + EnetAppUtils_print("[ ENETSBL ] Checksum : 0x%04x\r\n", Enet_htons(udpFrame->csum) & 0xFFFFU); + + EnetAppUtils_print("[ ENETSBL ] \r\n-----------------------------\r\n"); + + /* Payload */ + EnetAppUtils_print("[ ENETSBL ] DATA PAYLOAD\r\n"); + EnetAppUtils_print("[ ENETSBL ] ------------\r\n"); + + for (i = 0; i < dataLen; i++) + { + EnetAppUtils_print("[ ENETSBL ] 0x%02x ", gEnetSBL_MetaObj.appPktData[i]); + if (i && (((i + 1) % OCTETS_PER_ROW) == 0)) + { + EnetAppUtils_print("[ ENETSBL ] \r\n"); + } + } + + if (dataLen && ((dataLen % OCTETS_PER_ROW) != 0)) + { + EnetAppUtils_print("[ ENETSBL ] \r\n"); + } + + EnetAppUtils_print("[ ENETSBL ] \r\n"); +} + +static void EnetSBL_timerCallback(ClockP_Object *clkInst, void* arg) +{ + SemaphoreP_Object* hSem = (SemaphoreP_Object*)arg; + + /* Tick! */ + SemaphoreP_post(hSem); + Enet_periodicTick(gEnetSBL_LLDObj.hEnet); +} + +static bool EnetSBL_parseFrame(EthFrame *frame, uint32_t dataLen) +{ + uint8_t *payload; + bool matchingPkt = false; + + payload = frame->payload; + + EthAppIPv4Header *ipv4Frame = (EthAppIPv4Header *) payload; + EthAppUDPHeader *udpFrame = (EthAppUDPHeader *) &payload[sizeof(EthAppIPv4Header)]; + memset(&gEnetSBL_MetaObj.appPktData[0], 0U, ENETSBL_PKT_MAX_SIZE); + + /* Match IPv4 Address, Ethertype, UDP, Port number, IPv4 and UDP checksums, Magic Number */ + if(memcmp(&ipv4Frame->dstIP[0], &enetAppAddrInfo.srcIP[0], sizeof(ipv4Frame->dstIP)) == 0) + { + if (frame->hdr.etherType == Enet_htons(IPV4_ETHERTYPE)) + { + if (ipv4Frame->protocol == IPV4_HDR_UDP) + { + if (udpFrame->srcPort == Enet_htons(enetAppAddrInfo.srcPortUDP)) + { + if (EnetApp_verifyIPv4Checksum((uint16_t*)ipv4Frame)) + { + if (EnetApp_verifyUDPChecksum(ipv4Frame, udpFrame, &payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)])) + { + if(memcmp(&payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)], &EnetSBL_MagicNum, MGC_NUM_SIZE) == 0) + { + memcpy(&gEnetSBL_MetaObj.appPktData[0], &payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)], sizeof(gEnetSBL_MetaObj.appPktData[0])*dataLen); + matchingPkt = true; + } + } + } + } + } + } + } + + if(matchingPkt) + { + /* Copy the packet number from the payload to the global packet number */ + memcpy(&(gEnetSBL_MetaObj.appPktNum), &gEnetSBL_MetaObj.appPktData[MGC_NUM_SIZE], SEQ_NUM_SIZE); + + volatile bool printFrame = false; /* Use in debugging sessions to print appimage packets */ + if (printFrame) + { + EnetSBL_printFrame(frame, ipv4Frame, udpFrame, dataLen); + } + } + + return matchingPkt; +} + + +void EnetApp_initLinkArgs(Enet_Type enetType, + uint32_t instId, + EnetPer_PortLinkCfg *linkArgs, + Enet_MacPort macPort) +{ + EnetBoard_EthPort ethPort; + CpswMacPort_Cfg *cpswMacCfg; + EnetMacPort_LinkCfg *linkCfg = &linkArgs->linkCfg; + EnetMacPort_Interface *mii = &linkArgs->mii; + EnetPhy_Cfg *phyCfg = &linkArgs->phyCfg; + int32_t status = ENET_SOK; + EnetPhy_Mii phyMii; + + + EnetAppUtils_assert(EnetAppUtils_isDescCached() == false); + /* Set Enet global runtime log level */ + Enet_setTraceLevel(ENET_TRACE_DEBUG); + + /* Setup board for requested Ethernet port */ + ethPort.enetType = gEnetSBL_LLDObj.enetType; + ethPort.instId = gEnetSBL_LLDObj.instId; + ethPort.macPort = gEnetSBL_LLDObj.macPort; + ethPort.boardId = gEnetSBL_LLDObj.boardId; + EnetSBL_macMode2MacMii(gEnetSBL_LLDObj.macMode, ðPort.mii); + + status = EnetBoard_setupPorts(ðPort, 1U); + EnetAppUtils_assert(status == ENET_SOK); + + /* Set port link params */ + linkArgs->macPort = macPort; + + cpswMacCfg = linkArgs->macCfg; + + EnetSBL_macMode2MacMii(gEnetSBL_LLDObj.macMode, mii); + + const EnetBoard_PhyCfg *boardPhyCfg = NULL; + + /* Set PHY configuration params */ + EnetPhy_initCfg(phyCfg); + status = EnetSBL_macMode2PhyMii(gEnetSBL_LLDObj.macMode, &phyMii); + + if (status == ENET_SOK) + { + boardPhyCfg = EnetBoard_getPhyCfg(ðPort); + if (boardPhyCfg != NULL) + { + phyCfg->phyAddr = boardPhyCfg->phyAddr; + phyCfg->isStrapped = boardPhyCfg->isStrapped; + phyCfg->skipExtendedCfg = boardPhyCfg->skipExtendedCfg; + phyCfg->extendedCfgSize = boardPhyCfg->extendedCfgSize; + phyCfg->loopbackEn = false; + memcpy(phyCfg->extendedCfg, boardPhyCfg->extendedCfg, phyCfg->extendedCfgSize); + } + else + { + EnetAppUtils_print("[ ENETSBL ] PHY info not found\r\n"); + EnetAppUtils_assert(false); + } + linkCfg->speed = ENET_SPEED_AUTO; + linkCfg->duplexity = ENET_DUPLEX_AUTO; + } + /* MAC and PHY txsgs are mutually exclusive */ + phyCfg->loopbackEn = false; + cpswMacCfg->loopbackEn = false; +} + + +void EnetApp_updateCpswInitCfg(Enet_Type enetType, uint32_t instId, Cpsw_Cfg *cpswCfg) +{ + CpswHostPort_Cfg *hostPortCfg = &cpswCfg->hostPortCfg; + CpswAle_Cfg *aleCfg = &cpswCfg->aleCfg; + CpswCpts_Cfg *cptsCfg = &cpswCfg->cptsCfg; + EnetCpdma_Cfg *dmaCfg = (EnetCpdma_Cfg *)cpswCfg->dmaCfg; + + dmaCfg->rxInterruptPerMSec = 8; + dmaCfg->txInterruptPerMSec = 2; + /* Peripheral config */ + cpswCfg->vlanCfg.vlanAware = false; + + /* Host port config */ + hostPortCfg->removeCrc = true; + hostPortCfg->padShortPacket = true; + hostPortCfg->passCrcErrors = true; + + /* ALE config */ + aleCfg->modeFlags = CPSW_ALE_CFG_MODULE_EN; + aleCfg->agingCfg.autoAgingEn = true; + aleCfg->agingCfg.agingPeriodInMs = 1000; + aleCfg->nwSecCfg.vid0ModeEn = true; + aleCfg->vlanCfg.aleVlanAwareMode = false; + aleCfg->vlanCfg.cpswVlanAwareMode = false; + aleCfg->vlanCfg.unknownUnregMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK; + aleCfg->vlanCfg.unknownRegMcastFloodMask = CPSW_ALE_ALL_PORTS_MASK; + aleCfg->vlanCfg.unknownVlanMemberListMask = CPSW_ALE_ALL_PORTS_MASK; + + /* CPTS config */ + /* Note: Timestamping and MAC txsg are not supported together because of + * IP limitation, so disabling timestamping for this application */ + cptsCfg->hostRxTsEn = false; + +} diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h new file mode 100644 index 00000000000..efdc9057c57 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2023 Texas Instruments Incorporated + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * \file sbl_enet.h + * + * \brief This is the common header file of sbl_enet application. + */ + +#ifndef _SBL_ENET_H_ +#define _SBL_ENET_H_ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "ti_board_config.h" +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void Board_cpswMuxSel(void); + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* Host PC MAC Address */ +#define ENET_HOST_PC_MAC_ADDRESS { 0x28, 0x87, 0xBA, 0x3E, 0x41, 0x77} +//#define ENET_HOST_PC_MAC_ADDRESS { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF} +/* Port */ +#define ENET_PORT 5001 +/* EVM IP ADDRESS */ +#define ENET_SOURCE_IP_ADDRESS { 192U, 168U, 0U, 195U } +/* Host PC IP Address */ +#define ENET_DESTINATION_IP_ADDRESS { 192U, 168U, 0U, 136U } + +#define ENET_MTU_SIZE (1514U) +#define ENET_INSTANCE_ID (0U) +#define ENET_MAC_PORT (ENET_MAC_PORT_1) +#define ENET_MAC_MODE (RGMII) +#define ENET_TYPE (ENET_CPSW_3G) +#define ENET_BOARD_ID (ENETBOARD_CPB_ID) + +#define IPV4_HDR_VER_IHL ((0x4 << 4) | 0x5) +#define IPV4_HDR_TOS (0x00) +#define IPV4_HDR_TOTAL_PKT_LEN (36U) +#define IPV4_HDR_IPID (0x28) +#define IPV4_HDR_FLAGFRAFOFFSET (0x0000) +#define IPV4_HDR_TTL (0xFF) +#define IPV4_HDR_UDPLITE (0x88) +#define IPV4_HDR_UDP (0x11) +#define IPV4_ADDR_LEN (4U) +#define IPV4_ETHERTYPE (0x0800) + +#define UDP_PKT_LEN (IPV4_HDR_TOTAL_PKT_LEN - IPV4_HDR_SIZE) + +#define ETH_HDR_SIZE (14U) +#define IPV4_HDR_SIZE (20U) +#define UDP_HDR_SIZE (8U) +#define SEQ_NUM_SIZE (4U) +#define ACK_CODE_SIZE (4U) +#define MGC_NUM_SIZE (4U) + +#define ENETSBL_PKT_HDR_SIZE (ENET_UTILS_ALIGN((UDP_HDR_SIZE + IPV4_HDR_SIZE + ETH_HDR_SIZE),128)) +#define ENETSBL_PKT_MAX_SIZE (ENET_UTILS_ALIGN((ENET_MTU_SIZE - UDP_HDR_SIZE - IPV4_HDR_SIZE - ETH_HDR_SIZE),128)) +#define ENETSBL_TX_PAYLOAD_SIZE (ENET_UTILS_ALIGN((SEQ_NUM_SIZE + ACK_CODE_SIZE),8)) + +#define ENETSBL_HEADER_MGC_NUMBER (0x05B1C00D) +#define ENETSBL_HEADER_ACK (0x05B10ACD) + +#define BOOTLOADER_MAX_FILE_SIZE (10) +#define BOOTLOADER_VERIFY_MAX_SIZE (1) + +#define PERIODIC_TICK_MS (100U) /* 100-ms periodic tick */ + +#define COUNTING_SEM_COUNT (10U) /* Counting Semaphore count */ + +#define ENETSBL_TIMER_MODE (0xA2) +#define ENETSBL_BUTTON_MODE (0xD7) + +/* + * Select between usage of a button (ENETSBL_BUTTON_MODE, SW2) or a wait timer + * (ENETSBL_TIMER_MODE) for the start of app image transfer over ethernet. + */ +#define ENETSBL_TRANSFER_START_MODE ENETSBL_TIMER_MODE + +/* ========================================================================== */ +/* Structures and Enums */ +/* ========================================================================== */ + +typedef enum EnetSBL_type_e +{ + /* PHY txsg (internal) */ + TXSG_LOOPBACK_TYPE_PHY = 0, + /* No loopback. trasmit packets to network */ + TXSG_LOOPBACK_TYPE_NONE = 1 +} EnetSBL_type; + +typedef struct EnetSBL_LLDObj_s +{ + /* Enet driver */ + Enet_Handle hEnet; + Enet_Type enetType; + uint32_t instId; + uint32_t coreId; + uint32_t coreKey; + Enet_MacPort macPort; + uint8_t hostMacAddr[ENET_MAC_ADDR_LEN]; + + /* Tx, Rx Packet Queues */ + uint32_t rxChNum; + EnetDma_RxChHandle hRxCh; + EnetDma_PktQ rxFreeQ; + EnetDma_PktQ rxReadyQ; + EnetDma_TxChHandle hTxCh; + EnetDma_PktQ txFreePktInfoQ; + uint32_t txChNum; + + /* Periodic tick */ + ClockP_Object tickTimerObj; + SemaphoreP_Object timerSemObj; + + /* Packet transmission */ + SemaphoreP_Object txSemObj; + uint32_t totalTxCnt; + + /* Packet reception */ + SemaphoreP_Object rxSemObj; + uint32_t totalRxCnt; + + /* ISR functions */ + uint32_t rxIsrCount; + uint32_t txIsrCount; + + EnetSBL_type testLoopBackType; + bool printFrame; /* Print received Ethernet frames? */ + + emac_mode macMode; + uint32_t boardId; + EventP_Object appEvents; +} EnetSBL_LLDObj; + +typedef struct EnetSBL_MetaObj_s +{ + /* Transfer-related */ + uint32_t appPktNum; + uint8_t appPktData[ENETSBL_PKT_MAX_SIZE] __attribute__ ((aligned(128))); + uint8_t appPktHeader[ENETSBL_PKT_HDR_SIZE] __attribute__ ((aligned(128))); + uint8_t txPayload[ENETSBL_TX_PAYLOAD_SIZE] __attribute__ ((aligned(8))); +} EnetSBL_MetaObj; + +typedef struct +{ + uint8_t verIHL; + uint8_t tos; + uint16_t totalPktLen; + uint16_t ipId; + uint16_t flagFragOffset; + uint8_t ttl; + uint8_t protocol; + uint16_t hdrChksum; + uint8_t srcIP[IPV4_ADDR_LEN]; + uint8_t dstIP[IPV4_ADDR_LEN]; +} __attribute__ ((packed)) EthAppIPv4Header; + +typedef struct +{ + uint16_t srcPort; + uint16_t dstPort; + uint16_t length; + uint16_t csum; +} __attribute__ ((packed)) EthAppUDPHeader; + +typedef struct EnetSBL_AddrInfo_s +{ + uint8_t dstMac[ENET_MAC_ADDR_LEN]; + uint8_t srcIP[IPV4_ADDR_LEN]; + uint8_t dstIP[IPV4_ADDR_LEN]; + uint16_t srcPortUDP; + uint16_t dstPortUDP; +} EnetSBL_AddrInfo; + + + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +int32_t EnetSBL_setup(void); + +void EnetSBL_destruct(void); + +int32_t EnetSBL_transferAppimage(void); + +int32_t EnetSBL_txFlashResp(Bootloader_UniflashResponseHeader respHeader); + +int32_t EnetSBL_TransferStart(void); + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* Enet txsg test object declaration */ +extern EnetSBL_LLDObj gEnetSBL_LLDObj; +extern EnetSBL_MetaObj gEnetSBL_MetaObj; +extern uint8_t gFlashFileBuf[BOOTLOADER_MAX_FILE_SIZE] __attribute__((aligned(128), section(".bss.dss_l3")));; +extern uint8_t gFlashVerifyBuf[BOOTLOADER_VERIFY_MAX_SIZE] __attribute__((aligned(128), section(".bss.sbl_scratch")));; +extern uint32_t gFlashFileSize; + +#ifdef __cplusplus +} +#endif + +#endif /* _SBL_ENET_H_ */ diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec new file mode 100644 index 00000000000..c4abbb55ff4 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/example.projectspec @@ -0,0 +1,127 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker.cmd b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker.cmd new file mode 100644 index 00000000000..3546778a655 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker.cmd @@ -0,0 +1,71 @@ + +--stack_size=16384 +--heap_size=32768 +-e_vectors_sbl /* for SBL make sure to set entry point to _vectors_sbl */ + +__IRQ_STACK_SIZE = 4096; +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 256; +__ABORT_STACK_SIZE = 256; +__UNDEFINED_STACK_SIZE = 256; + +SECTIONS +{ + .sbl_init_code: palign(8), fill=0xabcdabcd + { + *(.vectors) /* IVT is put at the beginning of the section */ + . = align(8); + } load=MSRAM_VECS, run=R5F_VECS + .vectors:{} palign(8) > MSRAM_VECS + GROUP { + .text: {} palign(8) + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .data: {} palign(8) + .rodata: {} palign(8) + } > MSRAM_0 + .bss: {} palign(8) > MSRAM_0 + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) > MSRAM_0 + .stack: {} palign(8) > MSRAM_0 + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM_0 + + /* HSMRt image section */ + .rodata.hsmrt : {} palign(8) > MSRAM_HSMRT + + /* this is used only when Secure IPC is enabled */ + .bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM + .bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F +} + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000100 + R5F_TCMA : ORIGIN = 0x00000100 , LENGTH = 0x00007F00 + R5F_TCMB0: ORIGIN = 0x41010000 , LENGTH = 0x00008000 + MSRAM_VECS: ORIGIN = 0x70002000 , LENGTH = 0x00000100 + MSRAM_0 : ORIGIN = 0x70002100 , LENGTH = 0x60000 + /* 256 KB memory section HSMRt */ + MSRAM_HSMRT : ORIGIN = 0x70062100 , LENGTH = 0x40000 + MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE + MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE +} diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker_bkp.cmd b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker_bkp.cmd new file mode 100644 index 00000000000..a9fdeca0c85 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/linker_bkp.cmd @@ -0,0 +1,71 @@ + +--stack_size=8192 +--heap_size=8192 +-e_vectors_sbl /* for SBL make sure to set entry point to _vectors_sbl */ + +__IRQ_STACK_SIZE = 4096; +__FIQ_STACK_SIZE = 256; +__SVC_STACK_SIZE = 256; +__ABORT_STACK_SIZE = 256; +__UNDEFINED_STACK_SIZE = 256; + +SECTIONS +{ + .sbl_init_code: palign(8), fill=0xabcdabcd + { + *(.vectors) /* IVT is put at the beginning of the section */ + . = align(8); + } load=MSRAM_VECS, run=R5F_VECS + .vectors:{} palign(8) > MSRAM_VECS + GROUP { + .text: {} palign(8) + .text.hwi: palign(8) + .text.cache: palign(8) + .text.mpu: palign(8) + .text.boot: palign(8) + .data: {} palign(8) + .rodata: {} palign(8) + } > MSRAM_0 + .bss: {} palign(8) > MSRAM_0 + RUN_START(__BSS_START) + RUN_END(__BSS_END) + .sysmem: {} palign(8) > MSRAM_0 + .stack: {} palign(8) > MSRAM_0 + GROUP { + .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8) + RUN_START(__IRQ_STACK_START) + RUN_END(__IRQ_STACK_END) + .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8) + RUN_START(__FIQ_STACK_START) + RUN_END(__FIQ_STACK_END) + .svcstack: {. = . + __SVC_STACK_SIZE;} align(8) + RUN_START(__SVC_STACK_START) + RUN_END(__SVC_STACK_END) + .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8) + RUN_START(__ABORT_STACK_START) + RUN_END(__ABORT_STACK_END) + .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8) + RUN_START(__UNDEFINED_STACK_START) + RUN_END(__UNDEFINED_STACK_END) + } > MSRAM_0 + + /* HSMRt image section */ + .rodata.hsmrt : {} palign(8) > MSRAM_HSMRT + + /* this is used only when Secure IPC is enabled */ + .bss.sipc_hsm_queue_mem (NOLOAD) : {} > MAILBOX_HSM + .bss.sipc_r5f_queue_mem (NOLOAD) : {} > MAILBOX_R5F +} + +MEMORY +{ + R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000100 + R5F_TCMA : ORIGIN = 0x00000100 , LENGTH = 0x00007F00 + R5F_TCMB0: ORIGIN = 0x41010000 , LENGTH = 0x00008000 + MSRAM_VECS: ORIGIN = 0x70002000 , LENGTH = 0x00000100 + MSRAM_0 : ORIGIN = 0x70002100 , LENGTH = 0x60000 + /* 256 KB memory section HSMRt */ + MSRAM_HSMRT : ORIGIN = 0x70062100 , LENGTH = 0x40000 + MAILBOX_HSM: ORIGIN = 0x44000000 , LENGTH = 0x000003CE + MAILBOX_R5F: ORIGIN = 0x44000400 , LENGTH = 0x000003CE +} diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile new file mode 100644 index 00000000000..d9edb28b3c9 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile @@ -0,0 +1,312 @@ +# +# Auto generated makefile +# + +export MCU_PLUS_SDK_PATH?=$(abspath ../../../../../../..) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH) + +CC=$(CG_TOOL_ROOT)/bin/tiarmclang +LNK=$(CG_TOOL_ROOT)/bin/tiarmclang +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +PROFILE?=release +ConfigName:=$(PROFILE) + +OUTNAME:=sbl_qspi_enet.$(PROFILE).out + +BOOTIMAGE_PATH=$(abspath .) +BOOTIMAGE_NAME_GP:=sbl_qspi_enet.$(PROFILE).tiimage +BOOTIMAGE_NAME_HS:=sbl_qspi_enet.$(PROFILE).hs.tiimage +BOOTIMAGE_NAME_HS_FS:=sbl_qspi_enet.$(PROFILE).hs_fs.tiimage +BOOTIMAGE_BIN_NAME:=sbl_qspi_enet.$(PROFILE).bin + +ifeq ($(DEVICE_TYPE),HS) + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS) +else + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP) +endif + +FILES_common := \ + main.c \ + sbl_enet.c \ + board.c \ + ti_drivers_config.c \ + ti_drivers_open_close.c \ + ti_board_config.c \ + ti_board_open_close.c \ + ti_dpl_config.c \ + ti_pinmux_config.c \ + ti_power_clock_config.c \ + ti_enet_config.c \ + ti_enet_open_close.c \ + ti_enet_soc.c \ + ti_enet_lwipif.c \ + +FILES_PATH_common = \ + .. \ + ../../.. \ + generated \ + +INCLUDES_common := \ + -I${CG_TOOL_ROOT}/include/c \ + -I${MCU_PLUS_SDK_PATH}/source \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/utils \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/utils/include \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/core \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/core/include \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/core/include/phy \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/core/include/core \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/soc/am263x \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/hw_include \ + -I${MCU_PLUS_SDK_PATH}/source/networking/enet/hw_include/mdio/V4 \ + -I${MCU_PLUS_SDK_PATH}/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos \ + -Igenerated \ + +DEFINES_common := \ + -DSOC_AM263X \ + -DR5F0_INPUTS \ + +CFLAGS_common := \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Wall \ + -Werror \ + -g \ + -Wno-gnu-variable-sized-type-not-at-end \ + -Wno-unused-function \ + +CFLAGS_release := \ + -Os \ + -Oz \ + -flto \ + +CFLAGS_cpp_common := \ + -Wno-c99-designator \ + -Wno-extern-c-compat \ + -Wno-c++11-narrowing \ + -Wno-reorder-init-list \ + -Wno-deprecated-register \ + -Wno-writable-strings \ + -Wno-enum-compare \ + -Wno-reserved-user-defined-literal \ + -Wno-unused-const-variable \ + -x c++ \ + +CFLAGS_debug := \ + -D_DEBUG_=1 \ + +LNK_FILES_common = \ + linker.cmd \ + +LIBS_PATH_common = \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/kernel/nortos/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/board/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/networking/enet/lib \ + -Wl,-i${MCU_PLUS_SDK_PATH}/source/sdl/lib \ + -Wl,-i${CG_TOOL_ROOT}/lib \ + +LIBS_common = \ + -lnortos.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -ldrivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lboard.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lenet-cpsw.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -lsdl.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + -llibc.a \ + -llibsysbm.a \ + +LFLAGS_common = \ + -Wl,--diag_suppress=10063 \ + -Wl,--ram_model \ + -Wl,--reread_libs \ + +LNKOPTFLAGS_release = \ + -mcpu=cortex-r5 \ + -mfloat-abi=hard \ + -mfpu=vfpv3-d16 \ + -mthumb \ + -Oz \ + -flto \ + +LIBS_NAME = \ + nortos.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + drivers.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + board.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + enet-cpsw.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + sdl.am263x.r5f.ti-arm-clang.${ConfigName}.lib \ + libc.a \ + libsysbm.a \ + +LIBS_PATH_NAME = \ + ${MCU_PLUS_SDK_PATH}/source/kernel/nortos/lib \ + ${MCU_PLUS_SDK_PATH}/source/drivers/lib \ + ${MCU_PLUS_SDK_PATH}/source/board/lib \ + ${MCU_PLUS_SDK_PATH}/source/networking/enet/lib \ + ${MCU_PLUS_SDK_PATH}/source/sdl/lib \ + ${CG_TOOL_ROOT}/lib \ + +FILES := $(FILES_common) $(FILES_$(PROFILE)) +ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE)) +FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE)) +CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE)) +DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE)) +INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE)) +LIBS := $(LIBS_common) $(LIBS_$(PROFILE)) +LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE)) +LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE)) +LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE)) +LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE)) + +OBJDIR := obj/$(PROFILE)/ +OBJS := $(FILES:%.c=%.obj) +OBJS += $(ASMFILES:%.S=%.obj) +DEPS := $(FILES:%.c=%.d) + +vpath %.obj $(OBJDIR) +vpath %.c $(FILES_PATH) +vpath %.S $(FILES_PATH) +vpath %.lib $(LIBS_PATH_NAME) +vpath %.a $(LIBS_PATH_NAME) + +$(OBJDIR)/%.obj %.obj: %.c + @echo Compiling: am263x:r5fss0-0:nortos:ti-arm-clang $(OUTNAME): $< + $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $< + +$(OBJDIR)/%.obj %.obj: %.S + @echo Compiling: am263x:r5fss0-0:nortos:ti-arm-clang $(LIBNAME): $< + $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $< + +all: $(BOOTIMAGE_NAME) + +SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h +SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h +SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h +SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c +SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h +SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h +SYSCFG_GEN_FILES+=generated/ti_enet_config.c generated/ti_enet_config.h +SYSCFG_GEN_FILES+=generated/ti_enet_open_close.c generated/ti_enet_open_close.h +SYSCFG_GEN_FILES+=generated/ti_enet_soc.c +SYSCFG_GEN_FILES+=generated/ti_enet_lwipif.c generated/ti_enet_lwipif.h + +$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME) + @echo . + @echo Linking: am263x:r5fss0-0:nortos:ti-arm-clang $@ ... + $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES) + @echo Linking: am263x:r5fss0-0:nortos:ti-arm-clang $@ Done !!! + @echo . + +clean: + @echo Cleaning: am263x:r5fss0-0:nortos:ti-arm-clang $(OUTNAME) ... + $(RMDIR) $(OBJDIR) + $(RM) $(OUTNAME) + $(RM) $(BOOTIMAGE_NAME) + $(RM) $(BOOTIMAGE_BIN_NAME) + $(RMDIR) generated/ + +scrub: + @echo Scrubing: am263x:r5fss0-0:nortos:ti-arm-clang sbl_qspi_enet ... + $(RMDIR) obj +ifeq ($(OS),Windows_NT) + $(RM) \*.out + $(RM) \*.map + $(RM) \*.appimage* + $(RM) \*.rprc* + $(RM) \*.tiimage* + $(RM) \*.bin +else + $(RM) *.out + $(RM) *.map + $(RM) *.appimage* + $(RM) *.rprc* + $(RM) *.tiimage* + $(RM) *.bin +endif + $(RMDIR) generated + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + $(MKDIR) $@ + + +.NOTPARALLEL: + +.INTERMEDIATE: syscfg +$(SYSCFG_GEN_FILES): syscfg + +syscfg: ../example.syscfg + @echo Generating SysConfig files ... + $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part AM263x --package ZCZ --output generated/ ../example.syscfg + +syscfg-gui: + $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM263x_beta --context r5fss0-0 --part AM263x --package ZCZ --output generated/ ../example.syscfg + +# +# Generation of boot image which can be loaded by ROM Boot Loader (RBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt + + + +ifeq ($(DEVICE_TYPE),HS) +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +else +BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem +endif +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py + +SBL_RUN_ADDRESS=0x70002000 + +SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/am263x-cc + +$(BOOTIMAGE_BIN_NAME): $(OUTNAME) + $(OBJCOPY) --strip-sections -O binary $(OUTNAME) $(BOOTIMAGE_BIN_NAME) + +$(BOOTIMAGE_NAME): $(BOOTIMAGE_BIN_NAME) + @echo Boot image: am263x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ... +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DEBUG_TIFS), yes) +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --kd-salt $(KD_SALT) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) +endif +else +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --kd-salt $(KD_SALT) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +endif +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_PATH)/$(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif + $(COPY) $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME) $(SBL_PREBUILT_PATH)/ + + $(RM) $(BOOTIMAGE_TEMP_OUT_FILE) + @echo Boot image: am263x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!! + + @echo . + +-include $(addprefix $(OBJDIR)/, $(DEPS)) diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_ccs_bootimage_gen new file mode 100644 index 00000000000..c528306b934 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_ccs_bootimage_gen @@ -0,0 +1,87 @@ +# +# Auto generated makefile +# + +# Below variables need to be defined outside this file or via command line +# - MCU_PLUS_SDK_PATH +# - PROFILE +# - CG_TOOL_ROOT +# - OUTNAME +# - CCS_INSTALL_DIR +# - CCS_IDE_MODE + +CCS_PATH=$(CCS_INSTALL_DIR) +include $(MCU_PLUS_SDK_PATH)/imports.mak +include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak + +STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip +OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy +ifeq ($(OS), Windows_NT) + PYTHON=python +else + PYTHON=python3 +endif + +OUTFILE=$(PROFILE)/$(OUTNAME).out +BOOTIMAGE_PATH=$(abspath ${PROFILE}) +BOOTIMAGE_NAME_GP:=$(BOOTIMAGE_PATH)/$(OUTNAME).tiimage +BOOTIMAGE_NAME_HS:=sbl_qspi_enet.$(PROFILE).hs.tiimage +BOOTIMAGE_NAME_HS_FS:=sbl_qspi_enet.$(PROFILE).hs_fs.tiimage +ifeq ($(DEVICE_TYPE),HS) + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_HS) +else + BOOTIMAGE_NAME=$(BOOTIMAGE_NAME_GP) +endif +BOOTIMAGE_BIN_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).bin + +# +# Generation of boot image which can be loaded by ROM Boot Loader (RBL) +# +ifeq ($(OS),Windows_NT) +EXE_EXT=.exe +endif +ifeq ($(OS),Windows_NT) + BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1 +else + BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh +endif +BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt + +ifeq ($(DEVICE_TYPE),HS) +BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY) +else +BOOTIMAGE_CERT_KEY=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_gpkey.pem +endif +BOOTIMAGE_CERT_GEN_CMD=$(PYTHON) $(MCU_PLUS_SDK_PATH)/tools/boot/signing/mcu_rom_image_gen.py + +SBL_RUN_ADDRESS=0x70002000 + +SBL_PREBUILT_PATH=$(MCU_PLUS_SDK_PATH)/tools/boot/sbl_prebuilt/am263x-cc + +all: +ifeq ($(CCS_IDE_MODE),cloud) +# No post build steps +else + @echo Boot image: am263x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME) ... + $(OBJCOPY) --strip-sections -O binary $(OUTFILE) $(BOOTIMAGE_BIN_NAME) +ifeq ($(DEVICE_TYPE),HS) +ifeq ($(DEBUG_TIFS), yes) +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --kd-salt $(KD_SALT) --out-image $(BOOTIMAGE_NAME) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) +endif +else +ifeq ($(ENC_SBL_ENABLED),yes) + $(BOOTIMAGE_CERT_GEN_CMD) --sbl-enc --enc-key $(APP_ENCRYPTION_KEY) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --kd-salt $(KD_SALT) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug $(DEBUG_OPTION) +endif +endif +else + $(BOOTIMAGE_CERT_GEN_CMD) --image-bin $(BOOTIMAGE_BIN_NAME) --core R5 --swrv 1 --loadaddr $(SBL_RUN_ADDRESS) --sign-key $(BOOTIMAGE_CERT_KEY) --out-image $(BOOTIMAGE_NAME) --debug DBG_SOC_DEFAULT +endif + @echo Boot image: am263x:r5fss0-0:nortos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!! + @echo . +endif +endif diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_projectspec b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_projectspec new file mode 100644 index 00000000000..b0f8e02ca15 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/makefile_projectspec @@ -0,0 +1,20 @@ +# +# Auto generated makefile +# + +export MCU_PLUS_SDK_PATH?=$(abspath ../../../../../../..) +include $(MCU_PLUS_SDK_PATH)/imports.mak + +PROFILE?=Release + +PROJECT_NAME=sbl_qspi_enet_am263x-cc_r5fss0-0_nortos_ti-arm-clang + +all: + $(CCS_ECLIPSE) -noSplash -data $(MCU_PLUS_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) + +clean: + $(CCS_ECLIPSE) -noSplash -data $(MCU_PLUS_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean + +export: + $(MKDIR) $(MCU_PLUS_SDK_PATH)/ccs_projects + $(CCS_ECLIPSE) -noSplash -data $(MCU_PLUS_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/syscfg_c.rov.xs b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/syscfg_c.rov.xs new file mode 100644 index 00000000000..472ab38493f --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/syscfg_c.rov.xs @@ -0,0 +1,8 @@ +/* + * ======== syscfg_c.rov.xs ======== + * This file contains the information needed by the Runtime Object + * View (ROV) tool. + */ +var crovFiles = [ + "kernel/freertos/rov/FreeRTOS.rov.js", +]; diff --git a/makefile.am263x b/makefile.am263x index c0db41588ff..70a23dadb26 100644 --- a/makefile.am263x +++ b/makefile.am263x @@ -73,6 +73,7 @@ help: @echo . @echo Example build targets, @echo ====================== + @echo $(MAKE) -s -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C examples/drivers/adc/adc_multiple_soc_epwm/am263x-cc/r5fss0-0_nortos/ti-arm-clang [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C examples/drivers/adc/adc_multiple_soc_epwm/am263x-lp/r5fss0-0_nortos/ti-arm-clang [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C examples/drivers/adc/adc_ppb_epwm_trip/am263x-cc/r5fss0-0_nortos/ti-arm-clang [all clean syscfg-gui syscfg] @@ -1000,6 +1001,9 @@ examples: $(BUILD_COMBO_EXAMPLE_ALL) examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) + sbl_qspi_enet_am263x-cc_r5fss0-0_nortos_ti-arm-clang: + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile all + adc_multiple_soc_epwm_am263x-cc_r5fss0-0_nortos_ti-arm-clang: $(MAKE) -C examples/drivers/adc/adc_multiple_soc_epwm/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile all @@ -2353,6 +2357,9 @@ examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL) examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) + sbl_qspi_enet_am263x-cc_r5fss0-0_nortos_ti-arm-clang_clean: + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile clean + adc_multiple_soc_epwm_am263x-cc_r5fss0-0_nortos_ti-arm-clang_clean: $(MAKE) -C examples/drivers/adc/adc_multiple_soc_epwm/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile clean @@ -3706,6 +3713,9 @@ examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL) examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) + sbl_qspi_enet_am263x-cc_r5fss0-0_nortos_ti-arm-clang_scrub: + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile scrub + adc_multiple_soc_epwm_am263x-cc_r5fss0-0_nortos_ti-arm-clang_scrub: $(MAKE) -C examples/drivers/adc/adc_multiple_soc_epwm/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile scrub @@ -4725,6 +4735,7 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) sbl: libs + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile all $(MAKE) -C examples/drivers/boot/sbl_can/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile all $(MAKE) -C examples/drivers/boot/sbl_can/am263x-lp/r5fss0-0_nortos/ti-arm-clang -f makefile all $(MAKE) -C examples/drivers/boot/sbl_can_uniflash/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile all @@ -4743,6 +4754,7 @@ sbl: libs $(MAKE) -C examples/drivers/boot/sbl_uart_uniflash/am263x-lp/r5fss0-0_nortos/ti-arm-clang -f makefile all sbl-clean: + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile clean $(MAKE) -C examples/drivers/boot/sbl_can/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile clean $(MAKE) -C examples/drivers/boot/sbl_can/am263x-lp/r5fss0-0_nortos/ti-arm-clang -f makefile clean $(MAKE) -C examples/drivers/boot/sbl_can_uniflash/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile clean @@ -4761,6 +4773,7 @@ sbl-clean: $(MAKE) -C examples/drivers/boot/sbl_uart_uniflash/am263x-lp/r5fss0-0_nortos/ti-arm-clang -f makefile clean sbl-scrub: + $(MAKE) -C examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile scrub $(MAKE) -C examples/drivers/boot/sbl_can/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile scrub $(MAKE) -C examples/drivers/boot/sbl_can/am263x-lp/r5fss0-0_nortos/ti-arm-clang -f makefile scrub $(MAKE) -C examples/drivers/boot/sbl_can_uniflash/am263x-cc/r5fss0-0_nortos/ti-arm-clang -f makefile scrub diff --git a/tools/boot/sbl_prebuilt/am263x-cc/default_sbl_enet.cfg b/tools/boot/sbl_prebuilt/am263x-cc/default_sbl_enet.cfg new file mode 100644 index 00000000000..bc958b823c2 --- /dev/null +++ b/tools/boot/sbl_prebuilt/am263x-cc/default_sbl_enet.cfg @@ -0,0 +1,25 @@ +#-----------------------------------------------------------------------------# +# # +# DEFAULT CONFIGURATION FILE TO BE USED WITH THE FLASHWRITER SCRIPT # +# # +#-----------------------------------------------------------------------------# +# +# By default this config file, +# - points to pre-built flash writer, and SOC init bootloader or SBL NULL bootloader for this EVM +# - The SBL NULL bootloader does below +# - power-ON and clock setup for the R5F CPUs. +# - reset and run all the CPUs in a "WFI" loop. +# - It does NOT boot any applicaiton binary +# - SBL NULL is useful to init the SOC when the EVM is powered ON, +# so that one can do connect CCS and load application from CCS without needing +# to run any DMSC load scripts +# - This make the CCS development flow lot simpler as long as this one time flashing step is done. +# + +# First point to sbl_uart_uniflash binary, which function's as a server to flash one or more files +--flash-writer=sbl_prebuilt/am263x-cc/sbl_uart_uniflash.release.tiimage + +# When sending bootloader make sure to flash at offset 0x0. ROM expects bootloader at offset 0x0 +--file=/home/a0500374local/work/workarea/next/09_00/mcu_plus_sdk/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/ti-arm-clang/sbl_qspi_enet.release.tiimage --operation=flash --flash-offset=0x0 + + From 73ca289e1e043d185e6e531ff3cd01e1b440848a Mon Sep 17 00:00:00 2001 From: Pradeep HN Date: Fri, 2 Aug 2024 09:16:58 +0530 Subject: [PATCH 2/3] am263x: enet: Fix sbl bootloader issue Signed-off-by: Pradeep HN --- .../am263x-cc/r5fss0-0_nortos/example.syscfg | 3 +- .../am263x-cc/r5fss0-0_nortos/sbl_enet.c | 45 ++++++++----- .../am263x-cc/r5fss0-0_nortos/sbl_enet.h | 1 + .../boot/sbl_qspi_enet/custom_phy_addition.md | 67 +++++++++++++++++++ 4 files changed, 100 insertions(+), 16 deletions(-) create mode 100644 examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg index 9c329fa641a..d1737241121 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg @@ -2,7 +2,7 @@ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. * @cliArgs --device "AM263x_beta" --package "ZCZ" --part "AM263x" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" - * @versions {"tool":"1.18.0+3266"} + * @versions {"tool":"1.17.0+3128"} */ /** @@ -98,6 +98,7 @@ enet_cpsw1.RtosVariant = "NoRTOS"; enet_cpsw1.LargePoolPktCount = 16; enet_cpsw1.customBoardEnable = true; enet_cpsw1.DisableMacPort2 = true; +enet_cpsw1.hostportRxCsumOffloadEn = false; enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0"; enet_cpsw1.txDmaChannel[0].PacketsCount = 8; enet_cpsw1.rxDmaChannel[0].$name = "ENET_DMA_RX_CH0"; diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c index 1930920345c..80001cb1427 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c @@ -270,11 +270,15 @@ int32_t EnetSBL_transferAppimage(void) while(!finished) { - // waitCount++; +#if !SBL_TEST_STANDALONE_ENET_DEMO + waitCount++; if(waitCount > 1000 && (totalPktCnt == 0xFFFFFFFFU)) { break; } +#else + (void)waitCount ; // WA to mute the compilation warning (unused variable) +#endif SemaphoreP_pend(&gEnetSBL_LLDObj.rxSemObj, SystemP_NO_WAIT); /* Get the packets received so far */ rxReadyCnt = EnetSBL_receivePkts(); @@ -308,12 +312,20 @@ int32_t EnetSBL_transferAppimage(void) totalPktCnt = fileHeader->rsv1; EnetAppUtils_print("[ ENETSBL ] Receiving file, please wait ...\r\n"); } - /* Copy pkt contents to appimage buffer and increase file size */ +#if SBL_TEST_STANDALONE_ENET_DEMO + EnetAppUtils_print("[ ENETSBL ] ReceivedPacket:\r\n"); - /* TODO, REPLACE WRITING FILE INTO QSPI DIRECTLY INSTEAD OF MEMCPY INTO OCRAM */ - // memcpy(&gFlashFileBuf[gFlashFileSize], &gEnetSBL_MetaObj.appPktData[MGC_NUM_SIZE+SEQ_NUM_SIZE], (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE)); - // gFlashFileSize += (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE); + for (uint32_t i = 0; i < 20; i++) + { + EnetAppUtils_print("[ ENETSBL ] %x ", pktInfoRx->sgList.list[0].bufPtr[i]); + } + EnetAppUtils_print("\r\n"); +#else + /* TODO, REPLACE WRITING FILE INTO QSPI FLASH DIRECTLY INSTEAD OF MEMCPY */ + // memcpy(&gFlashFileBuf[gFlashFileSize], &gEnetSBL_MetaObj.appPktData[MGC_NUM_SIZE+SEQ_NUM_SIZE], (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE)); + gFlashFileSize += (EthPayloadLen-MGC_NUM_SIZE-SEQ_NUM_SIZE); +#endif /* Fill the TX payload with seq number and ACK code */ memcpy(&gEnetSBL_MetaObj.txPayload[0], &currPktCnt, sizeof(currPktCnt)); memcpy(&gEnetSBL_MetaObj.txPayload[sizeof(currPktCnt)], &EnetSBL_Ack, sizeof(EnetSBL_Ack)); @@ -401,17 +413,16 @@ int32_t EnetSBL_transferAppimage(void) } /*Submit now processed buffers */ - if (status == ENET_SOK) - { - EnetAppUtils_validatePacketState(&gEnetSBL_LLDObj.rxFreeQ, + EnetAppUtils_validatePacketState(&gEnetSBL_LLDObj.rxFreeQ, ENET_PKTSTATE_APP_WITH_FREEQ, ENET_PKTSTATE_APP_WITH_DRIVER); - EnetDma_submitRxPktQ(gEnetSBL_LLDObj.hRxCh, + EnetDma_submitRxPktQ(gEnetSBL_LLDObj.hRxCh, &gEnetSBL_LLDObj.rxFreeQ); - } + } } + EnetAppUtils_print("[ ENETSBL ] Status:%d\r\n", status); return ENET_EFAIL; /* send actual status instead of failure when ethernet image is received */ } @@ -525,7 +536,6 @@ static uint32_t EnetSBL_receivePkts(void) EnetAppUtils_print("[ ENETSBL ] receivePkts() failed to retrieve pkts: %d\r\n", status); } - EnetAppUtils_print("[ ENETSBL ] receivePkts() failed to retrieve pkts: %d\r\n", status); return rxReadyCnt; } @@ -1270,7 +1280,12 @@ static bool EnetSBL_parseFrame(EthFrame *frame, uint32_t dataLen) { if (EnetApp_verifyUDPChecksum(ipv4Frame, udpFrame, &payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)])) { - if(memcmp(&payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)], &EnetSBL_MagicNum, MGC_NUM_SIZE) == 0) +#if SBL_TEST_STANDALONE_ENET_DEMO + if(true /*memcmp(&payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)], &EnetSBL_MagicNum, MGC_NUM_SIZE) == 0*/) // uncomment this while testing with real application*/ +#else + +#endif + { memcpy(&gEnetSBL_MetaObj.appPktData[0], &payload[sizeof(EthAppIPv4Header)+sizeof(EthAppUDPHeader)], sizeof(gEnetSBL_MetaObj.appPktData[0])*dataLen); matchingPkt = true; @@ -1348,7 +1363,7 @@ void EnetApp_initLinkArgs(Enet_Type enetType, phyCfg->isStrapped = boardPhyCfg->isStrapped; phyCfg->skipExtendedCfg = boardPhyCfg->skipExtendedCfg; phyCfg->extendedCfgSize = boardPhyCfg->extendedCfgSize; - phyCfg->loopbackEn = false; + phyCfg->loopbackEn = false; memcpy(phyCfg->extendedCfg, boardPhyCfg->extendedCfg, phyCfg->extendedCfgSize); } else @@ -1356,8 +1371,8 @@ void EnetApp_initLinkArgs(Enet_Type enetType, EnetAppUtils_print("[ ENETSBL ] PHY info not found\r\n"); EnetAppUtils_assert(false); } - linkCfg->speed = ENET_SPEED_AUTO; - linkCfg->duplexity = ENET_DUPLEX_AUTO; + linkCfg->speed = ENET_SPEED_100MBIT; + linkCfg->duplexity = ENET_DUPLEX_FULL; } /* MAC and PHY txsgs are mutually exclusive */ phyCfg->loopbackEn = false; diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h index efdc9057c57..09c055e25f1 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h @@ -77,6 +77,7 @@ extern void Board_cpswMuxSel(void); /* ========================================================================== */ /* Macros & Typedefs */ /* ========================================================================== */ +#define SBL_TEST_STANDALONE_ENET_DEMO (1) // 1 = packet is discarded to verify enet only functionality /* Host PC MAC Address */ #define ENET_HOST_PC_MAC_ADDRESS { 0x28, 0x87, 0xBA, 0x3E, 0x41, 0x77} diff --git a/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md b/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md new file mode 100644 index 00000000000..a4d2ae3d655 --- /dev/null +++ b/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md @@ -0,0 +1,67 @@ +To add DP83TC812 PHY, please follow the below steps: + + +# Changes in enet-lld: +1. Copy the phy driver to /source/networking/enet/core/src/phy/ (src) and /source/networking/enet/core/include/phy/ (api header file) +2. Add .c file for makefile (/source/networking/enet/core/src/phy/makefile) . This adds the source file to enet-lld lib. + +Make sure gEnetPhyDrvdp83tc812 is defined in the phy driver source file. + +3. Compile enet-lld libs : +`$ cd /source/networking/enet` +`$ make -f makefile.cpsw.am263x.r5f.ti-arm-clang PROFILE=debug clean` +`$ make -f makefile.cpsw.am263x.r5f.ti-arm-clang PROFILE=release clean` +`$ make -f makefile.cpsw.am263x.r5f.ti-arm-clang PROFILE=debug all` +`$ make -f makefile.cpsw.am263x.r5f.ti-arm-clang PROFILE=release all` + +4. In application board.c (/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/board.c) file +do the following changes: + +5. Replace `#include ` with `#include ` +6. Replace `gEnetPhyDrvDp83869` with `gEnetPhyDrvdp83tc812` in the whole file +7. Define PHY specific extended configuration in board.c file + +Eg: +`static const Dp83869_Cfg gEnetCpbBoard_dp83869PhyCfg =` + +THis has to be replaced with `static const Dp83tc812_Cfg gEnetCpbBoard_dp83tc812PhyCfg + and fill eht values as the PHY settings. + +8. Change the initialition of gEnetCpbBoard_am263xEthPort to below: + +static const EnetBoard_PortCfg gEnetCpbBoard_am263xEthPort[] = +{ + { /* "CPSW3G" */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_1, + .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = < phy address>, + .isStrapped = true, + .skipExtendedCfg = false, + .extendedCfg = &gEnetCpbBoard_dp83tc812PhyCfg, + .extendedCfgSize = sizeof(gEnetCpbBoard_dp83tc812PhyCfg), + }, + .flags = 0U, + }, + { /* "CPSW3G" */ + .enetType = ENET_CPSW_3G, + .instId = 0U, + .macPort = ENET_MAC_PORT_2, + .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .phyCfg = + { + .phyAddr = < phy address>, + .isStrapped = true, + .skipExtendedCfg = false, + .extendedCfg = &gEnetCpbBoard_dp83tc812PhyCfg, + .extendedCfgSize = sizeof(gEnetCpbBoard_dp83tc812PhyCfg), + }, + .flags = 0U, + }, +}; + + +9. Thats all the changes. You may compile and run the application. From 3dd8c381c658d8bc0563d4f97fa2fd044b600ae6 Mon Sep 17 00:00:00 2001 From: Pradeep HN Date: Thu, 8 Aug 2024 22:59:12 +0530 Subject: [PATCH 3/3] Support for 2 MAC ports --- .../am263x-cc/r5fss0-0_nortos/example.syscfg | 1 - .../am263x-cc/r5fss0-0_nortos/main.c | 2 +- .../am263x-cc/r5fss0-0_nortos/sbl_enet.c | 53 ++++++++++++------- .../am263x-cc/r5fss0-0_nortos/sbl_enet.h | 9 ++-- .../boot/sbl_qspi_enet/custom_phy_addition.md | 4 +- 5 files changed, 42 insertions(+), 27 deletions(-) diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg index d1737241121..dd3fbe6fbd8 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/example.syscfg @@ -97,7 +97,6 @@ enet_cpsw1.$name = "CONFIG_ENET_CPSW0"; enet_cpsw1.RtosVariant = "NoRTOS"; enet_cpsw1.LargePoolPktCount = 16; enet_cpsw1.customBoardEnable = true; -enet_cpsw1.DisableMacPort2 = true; enet_cpsw1.hostportRxCsumOffloadEn = false; enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0"; enet_cpsw1.txDmaChannel[0].PacketsCount = 8; diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c index 3029505e47f..31ec92b20fa 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/main.c @@ -84,7 +84,7 @@ int main(void) Bootloader_profileAddProfilePoint("System_init"); loop_forever(); - // Board_init(); // deta remove this? + // Board_init(); // Todo: remove this? Drivers_open(); Bootloader_profileAddProfilePoint("Drivers_open"); diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c index 80001cb1427..3ce7bd24f9d 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.c @@ -137,14 +137,14 @@ int32_t EnetSBL_setup(void) EnetApp_HandleInfo handleInfo; int32_t status = 0; - gEnetSBL_LLDObj.enetType =ENET_TYPE; - gEnetSBL_LLDObj.instId = ENET_INSTANCE_ID; - gEnetSBL_LLDObj.macPort = ENET_MAC_PORT_1; gEnetSBL_LLDObj.macMode = RGMII; gEnetSBL_LLDObj.boardId = ENETBOARD_CPB_ID; gEnetSBL_LLDObj.testLoopBackType = TXSG_LOOPBACK_TYPE_NONE; + EnetApp_getEnetInstInfo(CONFIG_ENET_CPSW0, &gEnetSBL_LLDObj.enetType, &gEnetSBL_LLDObj.instId); + EnetApp_getEnetInstMacInfo(gEnetSBL_LLDObj.enetType, gEnetSBL_LLDObj.instId, &gEnetSBL_LLDObj.macPort[0], &gEnetSBL_LLDObj.numMacPorts); + /* Create Global Event Object */ status = EventP_construct(&gEnetSBL_LLDObj.appEvents); DebugP_assert(SystemP_SUCCESS == status); @@ -622,13 +622,16 @@ static void EnetSBL_closeEnet(void) Enet_IoctlPrms prms; int32_t status = 0; - /* Close port link */ - ENET_IOCTL_SET_IN_ARGS(&prms, &gEnetSBL_LLDObj.macPort); - - ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_PER_IOCTL_CLOSE_PORT_LINK, &prms,status); - if (status != ENET_SOK) + for (uint32_t portIdx = 0; portIdx < gEnetSBL_LLDObj.numMacPorts; portIdx++) { - EnetAppUtils_print("[ ENETSBL ] Failed to close port link: %d\r\n", status); + /* Close port link */ + ENET_IOCTL_SET_IN_ARGS(&prms, &gEnetSBL_LLDObj.macPort[portIdx]); + + ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_PER_IOCTL_CLOSE_PORT_LINK, &prms,status); + if (status != ENET_SOK) + { + EnetAppUtils_print("[ ENETSBL ] Failed to close port %d link: %d\r\n", gEnetSBL_LLDObj.macPort[portIdx], status); + } } /* Close Enet driver */ @@ -668,14 +671,17 @@ static int32_t EnetSBL_showAlivePhys(void) static int32_t EnetSBL_waitForLinkUp(void) { Enet_IoctlPrms prms; - bool linked = false; int32_t status = ENET_SOK; uint8_t linkUpWaitCount = 0; + for (uint32_t portIdx = 0; portIdx < gEnetSBL_LLDObj.numMacPorts; portIdx++) + { + // wait for both the links to be up + bool linked = false; while (!linked) { EnetApp_phyStateHandler(); - ENET_IOCTL_SET_INOUT_ARGS(&prms, &gEnetSBL_LLDObj.macPort, &linked); + ENET_IOCTL_SET_INOUT_ARGS(&prms, &gEnetSBL_LLDObj.macPort[portIdx], &linked); ENET_IOCTL(gEnetSBL_LLDObj.hEnet, gEnetSBL_LLDObj.coreId, ENET_PER_IOCTL_IS_PORT_LINK_UP, &prms, status); if (status != ENET_SOK) @@ -696,6 +702,13 @@ static int32_t EnetSBL_waitForLinkUp(void) } } } + + if (status != ENET_SOK) + { + // break if any port linkup has timedout + break; + } + } /* Sleep for 2 sec to complete host PC link up */ ClockP_sleep(2U); return status; @@ -1332,9 +1345,9 @@ void EnetApp_initLinkArgs(Enet_Type enetType, Enet_setTraceLevel(ENET_TRACE_DEBUG); /* Setup board for requested Ethernet port */ - ethPort.enetType = gEnetSBL_LLDObj.enetType; - ethPort.instId = gEnetSBL_LLDObj.instId; - ethPort.macPort = gEnetSBL_LLDObj.macPort; + ethPort.enetType = enetType; + ethPort.instId = instId; + ethPort.macPort = macPort; ethPort.boardId = gEnetSBL_LLDObj.boardId; EnetSBL_macMode2MacMii(gEnetSBL_LLDObj.macMode, ðPort.mii); @@ -1352,7 +1365,7 @@ void EnetApp_initLinkArgs(Enet_Type enetType, /* Set PHY configuration params */ EnetPhy_initCfg(phyCfg); - status = EnetSBL_macMode2PhyMii(gEnetSBL_LLDObj.macMode, &phyMii); + status = EnetSBL_macMode2PhyMii(gEnetSBL_LLDObj.macMode, &phyMii); // todo: if (status == ENET_SOK) { @@ -1363,7 +1376,7 @@ void EnetApp_initLinkArgs(Enet_Type enetType, phyCfg->isStrapped = boardPhyCfg->isStrapped; phyCfg->skipExtendedCfg = boardPhyCfg->skipExtendedCfg; phyCfg->extendedCfgSize = boardPhyCfg->extendedCfgSize; - phyCfg->loopbackEn = false; + phyCfg->loopbackEn = (gEnetSBL_LLDObj.testLoopBackType == TXSG_LOOPBACK_TYPE_PHY); memcpy(phyCfg->extendedCfg, boardPhyCfg->extendedCfg, phyCfg->extendedCfgSize); } else @@ -1371,12 +1384,12 @@ void EnetApp_initLinkArgs(Enet_Type enetType, EnetAppUtils_print("[ ENETSBL ] PHY info not found\r\n"); EnetAppUtils_assert(false); } - linkCfg->speed = ENET_SPEED_100MBIT; - linkCfg->duplexity = ENET_DUPLEX_FULL; + linkCfg->speed = ENET_SPEED_100MBIT; // todo: + linkCfg->duplexity = ENET_DUPLEX_FULL; // Todo: } /* MAC and PHY txsgs are mutually exclusive */ - phyCfg->loopbackEn = false; - cpswMacCfg->loopbackEn = false; + phyCfg->loopbackEn = (gEnetSBL_LLDObj.testLoopBackType == TXSG_LOOPBACK_TYPE_PHY); + cpswMacCfg->loopbackEn = (gEnetSBL_LLDObj.testLoopBackType == TXSG_LOOPBACK_TYPE_MAC); } diff --git a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h index 09c055e25f1..d78a0caccf1 100644 --- a/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h +++ b/examples/drivers/boot/sbl_qspi_enet/am263x-cc/r5fss0-0_nortos/sbl_enet.h @@ -65,6 +65,7 @@ #include "ti_board_config.h" #include #include +#include #include @@ -146,9 +147,10 @@ extern void Board_cpswMuxSel(void); typedef enum EnetSBL_type_e { /* PHY txsg (internal) */ - TXSG_LOOPBACK_TYPE_PHY = 0, + TXSG_LOOPBACK_TYPE_MAC = 0, + TXSG_LOOPBACK_TYPE_PHY = 1, /* No loopback. trasmit packets to network */ - TXSG_LOOPBACK_TYPE_NONE = 1 + TXSG_LOOPBACK_TYPE_NONE = 2 } EnetSBL_type; typedef struct EnetSBL_LLDObj_s @@ -159,7 +161,8 @@ typedef struct EnetSBL_LLDObj_s uint32_t instId; uint32_t coreId; uint32_t coreKey; - Enet_MacPort macPort; + Enet_MacPort macPort[ENET_SYSCFG_MAX_MAC_PORTS]; + uint8_t numMacPorts; uint8_t hostMacAddr[ENET_MAC_ADDR_LEN]; /* Tx, Rx Packet Queues */ diff --git a/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md b/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md index a4d2ae3d655..0e7b5d2f281 100644 --- a/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md +++ b/examples/drivers/boot/sbl_qspi_enet/custom_phy_addition.md @@ -35,7 +35,7 @@ static const EnetBoard_PortCfg gEnetCpbBoard_am263xEthPort[] = .enetType = ENET_CPSW_3G, .instId = 0U, .macPort = ENET_MAC_PORT_1, - .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = { .phyAddr = < phy address>, @@ -50,7 +50,7 @@ static const EnetBoard_PortCfg gEnetCpbBoard_am263xEthPort[] = .enetType = ENET_CPSW_3G, .instId = 0U, .macPort = ENET_MAC_PORT_2, - .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = { .phyAddr = < phy address>,