diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 39f375cf842b..55df77ae01d4 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -221,6 +221,7 @@ "stm32/stm32h7r7-artpi2", "stm32/stm32mp157a-st-discovery", "stm32/stm32mp157a-st-ev1", + "stm32/stm32n657-st-nucleo", "stm32/stm32u575-st-nucleo", "stm32/stm32u585-iot02a", "stm32/stm32wb55-st-nucleo" diff --git a/bsp/README.md b/bsp/README.md index da23db8e1585..848df098e2c7 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -157,6 +157,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | [stm32l552-st-nucleo](stm32/stm32l552-st-nucleo) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | [stm32mp157a-st-discovery](stm32/stm32mp157a-st-discovery) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - | ✅ | - | - | - | | [stm32mp157a-st-ev1](stm32/stm32mp157a-st-ev1) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | ✅ | - | - | - | +| [stm32n657-st-nucleo](stm32/stm32n657-st-nucleo) | ✅ | ✅ | - | - | - | - | - | ✅ | - | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | [stm32u575-st-nucleo](stm32/stm32u575-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | [stm32u585-iot02a](stm32/stm32u585-iot02a) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | [stm32wb55-st-nucleo](stm32/stm32wb55-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index 3fd2d0ff44b3..6bb11ef4dbe9 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -99,6 +99,8 @@ STM32 系列 BSP 目前支持情况如下表所示： | **MP1 系列** | | | [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 | | [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 | +| **N6 系列** | | +| [stm32n657-st-nucleo](stm32n657-st-nucleo) | ST 官方 STM32N657-Nucleo 开发板 | | **WB 系列** | | | [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 | | [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 | diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/adc_config.h new file mode 100644 index 000000000000..3314bc7e9255 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/adc_config.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-06 zylx first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .Instance = ADC1, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .Instance = ADC2, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC2_CONFIG */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .Instance = ADC3, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC3_CONFIG */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dac_config.h new file mode 100644 index 000000000000..568dc9ec6644 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 thread-liu first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_CONFIG +#define DAC1_CONFIG \ + { \ + .Instance = DAC1, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_CONFIG +#define DAC2_CONFIG \ + { \ + .Instance = DAC2, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dma_config.h new file mode 100644 index 000000000000..f598da806831 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dma_config.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code + * 2020-05-02 whj4674672 support stm32h7 dma1 and dma2 + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* N6 provides one GPDMA1 controller with 16 independent channels. Keep the + * legacy endpoint table below source-compatible while assigning each legacy + * stream a unique GPDMA channel. */ +#define DMA1_Stream0 GPDMA1_Channel0 +#define DMA1_Stream1 GPDMA1_Channel1 +#define DMA1_Stream2 GPDMA1_Channel2 +#define DMA1_Stream3 GPDMA1_Channel3 +#define DMA1_Stream4 GPDMA1_Channel4 +#define DMA1_Stream5 GPDMA1_Channel5 +#define DMA1_Stream6 GPDMA1_Channel6 +#define DMA1_Stream7 GPDMA1_Channel7 +#define DMA2_Stream0 GPDMA1_Channel8 +#define DMA2_Stream1 GPDMA1_Channel9 +#define DMA2_Stream2 GPDMA1_Channel10 +#define DMA2_Stream3 GPDMA1_Channel11 +#define DMA2_Stream4 GPDMA1_Channel12 +#define DMA2_Stream5 GPDMA1_Channel13 +#define DMA2_Stream6 GPDMA1_Channel14 +#define DMA2_Stream7 GPDMA1_Channel15 +#define DMA1_Stream0_IRQn GPDMA1_Channel0_IRQn +#define DMA1_Stream1_IRQn GPDMA1_Channel1_IRQn +#define DMA1_Stream2_IRQn GPDMA1_Channel2_IRQn +#define DMA1_Stream3_IRQn GPDMA1_Channel3_IRQn +#define DMA1_Stream4_IRQn GPDMA1_Channel4_IRQn +#define DMA1_Stream5_IRQn GPDMA1_Channel5_IRQn +#define DMA1_Stream6_IRQn GPDMA1_Channel6_IRQn +#define DMA1_Stream7_IRQn GPDMA1_Channel7_IRQn +#define DMA2_Stream0_IRQn GPDMA1_Channel8_IRQn +#define DMA2_Stream1_IRQn GPDMA1_Channel9_IRQn +#define DMA2_Stream2_IRQn GPDMA1_Channel10_IRQn +#define DMA2_Stream3_IRQn GPDMA1_Channel11_IRQn +#define DMA2_Stream4_IRQn GPDMA1_Channel12_IRQn +#define DMA2_Stream5_IRQn GPDMA1_Channel13_IRQn +#define DMA2_Stream6_IRQn GPDMA1_Channel14_IRQn +#define DMA2_Stream7_IRQn GPDMA1_Channel15_IRQn +#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_GPDMA1EN +#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_GPDMA1EN +#define SPI1_RX_DMA_REQUEST GPDMA1_REQUEST_SPI1_RX +#define SPI1_TX_DMA_REQUEST GPDMA1_REQUEST_SPI1_TX +#define SPI2_RX_DMA_REQUEST GPDMA1_REQUEST_SPI2_RX +#define SPI2_TX_DMA_REQUEST GPDMA1_REQUEST_SPI2_TX +#define SPI3_RX_DMA_REQUEST GPDMA1_REQUEST_SPI3_RX +#define SPI3_TX_DMA_REQUEST GPDMA1_REQUEST_SPI3_TX +#define SPI4_RX_DMA_REQUEST GPDMA1_REQUEST_SPI4_RX +#define SPI4_TX_DMA_REQUEST GPDMA1_REQUEST_SPI4_TX +#define SPI5_RX_DMA_REQUEST GPDMA1_REQUEST_SPI5_RX +#define SPI5_TX_DMA_REQUEST GPDMA1_REQUEST_SPI5_TX +#define SPI6_RX_DMA_REQUEST GPDMA1_REQUEST_SPI6_RX +#define SPI6_TX_DMA_REQUEST GPDMA1_REQUEST_SPI6_TX +#define DMA_REQUEST_USART2_RX GPDMA1_REQUEST_USART2_RX +#define DMA_REQUEST_USART2_TX GPDMA1_REQUEST_USART2_TX + +/* DMA1 stream0 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream0 +#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX +#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn +#endif + +/* DMA1 stream1 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Stream1 +#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX +#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn +#endif + +/* DMA1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#endif + +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +#endif + +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +#endif + + +/* DMA1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#endif + +/* DMA1 stream6 */ + +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif + +/* DMA1 stream6/7 are available for SPI6 when SPI3 TX uses stream5. */ +#if defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE) +#define SPI6_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler +#define SPI6_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI6_RX_DMA_INSTANCE DMA1_Stream6 +#define SPI6_RX_DMA_IRQ DMA1_Stream6_IRQn +#endif + +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI6_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI6_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI6_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif + +/* DMA2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream7 +#define QSPI_DMA_IRQ DMA2_Stream7_IRQn +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/lptim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/lptim_config.h new file mode 100644 index 000000000000..794289d88a14 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/lptim_config.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-11 wdfk-prog first version + */ + +#ifndef __LPTIM_CONFIG_H__ +#define __LPTIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LPTIM_DEV_INFO_CONFIG +#define LPTIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_LPTIM1 +#ifndef LPTIM1_CONFIG +#define LPTIM1_CONFIG \ + { \ + .tim_handle.Instance = LPTIM1, \ + .tim_irqn = LPTIM1_IRQn, \ + .name = "lptim1", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM2 +#ifndef LPTIM2_CONFIG +#define LPTIM2_CONFIG \ + { \ + .tim_handle.Instance = LPTIM2, \ + .tim_irqn = LPTIM2_IRQn, \ + .name = "lptim2", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM3 +#ifndef LPTIM3_CONFIG +#define LPTIM3_CONFIG \ + { \ + .tim_handle.Instance = LPTIM3, \ + .tim_irqn = LPTIM3_IRQn, \ + .name = "lptim3", \ + } +#endif /* LPTIM3_CONFIG */ +#endif /* BSP_USING_LPTIM3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPTIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/pwm_config.h new file mode 100644 index 000000000000..5c062739fde3 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/pwm_config.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + * 2022-04-14 Miaowulue add PWM1 + * 2023-04-08 Wangyuqiang complete PWM defination + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM1 +#define PWM1_CONFIG \ + { \ + .tim_handle.Instance = TIM1, \ + .name = "pwm1", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM5 */ + +#ifdef BSP_USING_PWM6 +#define PWM6_CONFIG \ + { \ + .tim_handle.Instance = TIM6, \ + .name = "pwm6", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM6 */ + +#ifdef BSP_USING_PWM7 +#define PWM7_CONFIG \ + { \ + .tim_handle.Instance = TIM7, \ + .name = "pwm7", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM7 */ + +#ifdef BSP_USING_PWM8 +#define PWM8_CONFIG \ + { \ + .tim_handle.Instance = TIM8, \ + .name = "pwm8", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM8 */ + +#ifdef BSP_USING_PWM9 +#define PWM9_CONFIG \ + { \ + .tim_handle.Instance = TIM9, \ + .name = "pwm9", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM9 */ + +#ifdef BSP_USING_PWM10 +#define PWM10_CONFIG \ + { \ + .tim_handle.Instance = TIM10, \ + .name = "pwm10", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM10 */ + +#ifdef BSP_USING_PWM11 +#define PWM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .name = "pwm11", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM11 */ + +#ifdef BSP_USING_PWM12 +#define PWM12_CONFIG \ + { \ + .tim_handle.Instance = TIM12, \ + .name = "pwm12", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM12 */ + +#ifdef BSP_USING_PWM13 +#define PWM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .name = "pwm13", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM13 */ + +#ifdef BSP_USING_PWM14 +#define PWM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .name = "pwm14", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM14 */ + +#ifdef BSP_USING_PWM15 +#define PWM15_CONFIG \ + { \ + .tim_handle.Instance = TIM15, \ + .name = "pwm15", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM15 */ + +#ifdef BSP_USING_PWM16 +#define PWM16_CONFIG \ + { \ + .tim_handle.Instance = TIM16, \ + .name = "pwm16", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM16 */ + +#ifdef BSP_USING_PWM17 +#define PWM17_CONFIG \ + { \ + .tim_handle.Instance = TIM17, \ + .name = "pwm17", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM17 */ + +#ifdef BSP_USING_PWM18 +#define PWM18_CONFIG \ + { \ + .tim_handle.Instance = TIM18, \ + .name = "pwm18", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM18 */ + +#ifdef BSP_USING_PWM19 +#define PWM19_CONFIG \ + { \ + .tim_handle.Instance = TIM19, \ + .name = "pwm19", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM19 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/qspi_config.h new file mode 100644 index 000000000000..a315b2f5cc6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/qspi_config.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/sdio_config.h new file mode 100644 index 000000000000..b56b3034e6b9 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/sdio_config.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "stm32h7xx_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDMMC1, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__SDIO_CONFIG_H__ */ + + + diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/spi_config.h new file mode 100644 index 000000000000..080c70bd6afd --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/spi_config.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ + .irq_type = SPI1_IRQn, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_PRIORITY +#define SPI1_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI1_TX_DMA_PRIORITY */ + +#ifndef SPI1_TX_DMA_PREEMPT_PRIORITY +#define SPI1_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI1_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_TX_DMA_SUB_PRIORITY +#define SPI1_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI1_TX_DMA_INSTANCE, \ + SPI1_TX_DMA_RCC, \ + SPI1_TX_DMA_IRQ, \ + SPI1_TX_DMA_REQUEST, \ + SPI1_TX_DMA_PRIORITY, \ + SPI1_TX_DMA_PREEMPT_PRIORITY, \ + SPI1_TX_DMA_SUB_PRIORITY) +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_PRIORITY +#define SPI1_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI1_RX_DMA_PRIORITY */ + +#ifndef SPI1_RX_DMA_PREEMPT_PRIORITY +#define SPI1_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI1_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI1_RX_DMA_SUB_PRIORITY +#define SPI1_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI1_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI1_RX_DMA_INSTANCE, \ + SPI1_RX_DMA_RCC, \ + SPI1_RX_DMA_IRQ, \ + SPI1_RX_DMA_REQUEST, \ + SPI1_RX_DMA_PRIORITY, \ + SPI1_RX_DMA_PREEMPT_PRIORITY, \ + SPI1_RX_DMA_SUB_PRIORITY) +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ + .irq_type = SPI2_IRQn, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_PRIORITY +#define SPI2_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI2_TX_DMA_PRIORITY */ + +#ifndef SPI2_TX_DMA_PREEMPT_PRIORITY +#define SPI2_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI2_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_TX_DMA_SUB_PRIORITY +#define SPI2_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI2_TX_DMA_INSTANCE, \ + SPI2_TX_DMA_RCC, \ + SPI2_TX_DMA_IRQ, \ + SPI2_TX_DMA_REQUEST, \ + SPI2_TX_DMA_PRIORITY, \ + SPI2_TX_DMA_PREEMPT_PRIORITY, \ + SPI2_TX_DMA_SUB_PRIORITY) +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_PRIORITY +#define SPI2_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI2_RX_DMA_PRIORITY */ + +#ifndef SPI2_RX_DMA_PREEMPT_PRIORITY +#define SPI2_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI2_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI2_RX_DMA_SUB_PRIORITY +#define SPI2_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI2_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI2_RX_DMA_INSTANCE, \ + SPI2_RX_DMA_RCC, \ + SPI2_RX_DMA_IRQ, \ + SPI2_RX_DMA_REQUEST, \ + SPI2_RX_DMA_PRIORITY, \ + SPI2_RX_DMA_PREEMPT_PRIORITY, \ + SPI2_RX_DMA_SUB_PRIORITY) +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ + .irq_type = SPI3_IRQn, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_PRIORITY +#define SPI3_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI3_TX_DMA_PRIORITY */ + +#ifndef SPI3_TX_DMA_PREEMPT_PRIORITY +#define SPI3_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI3_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_TX_DMA_SUB_PRIORITY +#define SPI3_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI3_TX_DMA_INSTANCE, \ + SPI3_TX_DMA_RCC, \ + SPI3_TX_DMA_IRQ, \ + SPI3_TX_DMA_REQUEST, \ + SPI3_TX_DMA_PRIORITY, \ + SPI3_TX_DMA_PREEMPT_PRIORITY, \ + SPI3_TX_DMA_SUB_PRIORITY) +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_PRIORITY +#define SPI3_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI3_RX_DMA_PRIORITY */ + +#ifndef SPI3_RX_DMA_PREEMPT_PRIORITY +#define SPI3_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI3_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI3_RX_DMA_SUB_PRIORITY +#define SPI3_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI3_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI3_RX_DMA_INSTANCE, \ + SPI3_RX_DMA_RCC, \ + SPI3_RX_DMA_IRQ, \ + SPI3_RX_DMA_REQUEST, \ + SPI3_RX_DMA_PRIORITY, \ + SPI3_RX_DMA_PREEMPT_PRIORITY, \ + SPI3_RX_DMA_SUB_PRIORITY) +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ + .irq_type = SPI4_IRQn, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_PRIORITY +#define SPI4_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI4_TX_DMA_PRIORITY */ + +#ifndef SPI4_TX_DMA_PREEMPT_PRIORITY +#define SPI4_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI4_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_TX_DMA_SUB_PRIORITY +#define SPI4_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI4_TX_DMA_INSTANCE, \ + SPI4_TX_DMA_RCC, \ + SPI4_TX_DMA_IRQ, \ + SPI4_TX_DMA_REQUEST, \ + SPI4_TX_DMA_PRIORITY, \ + SPI4_TX_DMA_PREEMPT_PRIORITY, \ + SPI4_TX_DMA_SUB_PRIORITY) +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_PRIORITY +#define SPI4_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI4_RX_DMA_PRIORITY */ + +#ifndef SPI4_RX_DMA_PREEMPT_PRIORITY +#define SPI4_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI4_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI4_RX_DMA_SUB_PRIORITY +#define SPI4_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI4_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI4_RX_DMA_INSTANCE, \ + SPI4_RX_DMA_RCC, \ + SPI4_RX_DMA_IRQ, \ + SPI4_RX_DMA_REQUEST, \ + SPI4_RX_DMA_PRIORITY, \ + SPI4_RX_DMA_PREEMPT_PRIORITY, \ + SPI4_RX_DMA_SUB_PRIORITY) +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ + .irq_type = SPI5_IRQn, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_PRIORITY +#define SPI5_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI5_TX_DMA_PRIORITY */ + +#ifndef SPI5_TX_DMA_PREEMPT_PRIORITY +#define SPI5_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI5_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_TX_DMA_SUB_PRIORITY +#define SPI5_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI5_TX_DMA_INSTANCE, \ + SPI5_TX_DMA_RCC, \ + SPI5_TX_DMA_IRQ, \ + SPI5_TX_DMA_REQUEST, \ + SPI5_TX_DMA_PRIORITY, \ + SPI5_TX_DMA_PREEMPT_PRIORITY, \ + SPI5_TX_DMA_SUB_PRIORITY) +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_PRIORITY +#define SPI5_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI5_RX_DMA_PRIORITY */ + +#ifndef SPI5_RX_DMA_PREEMPT_PRIORITY +#define SPI5_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI5_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI5_RX_DMA_SUB_PRIORITY +#define SPI5_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI5_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI5_RX_DMA_INSTANCE, \ + SPI5_RX_DMA_RCC, \ + SPI5_RX_DMA_IRQ, \ + SPI5_RX_DMA_REQUEST, \ + SPI5_RX_DMA_PRIORITY, \ + SPI5_RX_DMA_PREEMPT_PRIORITY, \ + SPI5_RX_DMA_SUB_PRIORITY) +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = SPI6, \ + .bus_name = "spi6", \ + .irq_type = SPI6_IRQn, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_PRIORITY +#define SPI6_TX_DMA_PRIORITY DMA_PRIORITY_LOW +#endif /* SPI6_TX_DMA_PRIORITY */ + +#ifndef SPI6_TX_DMA_PREEMPT_PRIORITY +#define SPI6_TX_DMA_PREEMPT_PRIORITY 1 +#endif /* SPI6_TX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI6_TX_DMA_SUB_PRIORITY +#define SPI6_TX_DMA_SUB_PRIORITY 0 +#endif /* SPI6_TX_DMA_SUB_PRIORITY */ + +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + STM32_GPDMA_TX_BYTE_CONFIG_INIT_EX( \ + SPI6_TX_DMA_INSTANCE, \ + SPI6_TX_DMA_RCC, \ + SPI6_TX_DMA_IRQ, \ + SPI6_TX_DMA_REQUEST, \ + SPI6_TX_DMA_PRIORITY, \ + SPI6_TX_DMA_PREEMPT_PRIORITY, \ + SPI6_TX_DMA_SUB_PRIORITY) +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_PRIORITY +#define SPI6_RX_DMA_PRIORITY DMA_PRIORITY_HIGH +#endif /* SPI6_RX_DMA_PRIORITY */ + +#ifndef SPI6_RX_DMA_PREEMPT_PRIORITY +#define SPI6_RX_DMA_PREEMPT_PRIORITY 0 +#endif /* SPI6_RX_DMA_PREEMPT_PRIORITY */ + +#ifndef SPI6_RX_DMA_SUB_PRIORITY +#define SPI6_RX_DMA_SUB_PRIORITY 0 +#endif /* SPI6_RX_DMA_SUB_PRIORITY */ + +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + STM32_GPDMA_RX_BYTE_CONFIG_INIT_EX( \ + SPI6_RX_DMA_INSTANCE, \ + SPI6_RX_DMA_RCC, \ + SPI6_RX_DMA_IRQ, \ + SPI6_RX_DMA_REQUEST, \ + SPI6_RX_DMA_PRIORITY, \ + SPI6_RX_DMA_PREEMPT_PRIORITY, \ + SPI6_RX_DMA_SUB_PRIORITY) +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/tim_config.h new file mode 100644 index 000000000000..be55a377871f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/tim_config.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CONFIG +#define TIM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .tim_irqn = TIM2_IRQn, \ + .name = "timer2", \ + } +#endif /* TIM2_CONFIG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/uart_config.h new file mode 100644 index 000000000000..fbf9715dfdb0 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/uart_config.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2019-01-05 zylx modify dma support + * 2020-05-02 whj4674672 support stm32h7 uart dma + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .request = UART1_RX_DMA_REQUEST, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .request = UART2_RX_DMA_REQUEST, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .request = UART2_TX_DMA_REQUEST, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .request = UART3_RX_DMA_REQUEST, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .request = UART4_RX_DMA_REQUEST, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = UART5, \ + .irq_type = UART5_IRQn, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_RX_CONFIG +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .request = UART5_RX_DMA_REQUEST, \ + .dma_rcc = UART5_RX_DMA_RCC, \ + .dma_irq = UART5_RX_DMA_IRQ, \ + } +#endif /* UART5_DMA_RX_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + +#if defined(BSP_USING_LPUART1) +#ifndef LPUART1_CONFIG +#define LPUART1_CONFIG \ + { \ + .name = "hlpuart1", \ + .Instance = LPUART1, \ + .irq_type = LPUART1_IRQn, \ + } +#endif /* LPUART1_CONFIG */ +#endif /* BSP_USING_LPUART1 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/usbd_config.h new file mode 100644 index 000000000000..f7207ca4539d --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/usbd_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-10 ZYH first version + * 2019-10-27 flybreak Compatible with the HS + */ +#ifndef __USBD_CONFIG_H__ +#define __USBD_CONFIG_H__ + +#include + +#ifdef BSP_USBD_TYPE_HS +#define USBD_IRQ_TYPE OTG_HS_IRQn +#define USBD_IRQ_HANDLER OTG_HS_IRQHandler +#define USBD_INSTANCE USB_OTG_HS +#else +#define USBD_IRQ_TYPE OTG_FS_IRQn +#define USBD_IRQ_HANDLER OTG_FS_IRQHandler +#define USBD_INSTANCE USB_OTG_FS +#endif + +#ifdef BSP_USBD_SPEED_HS +#define USBD_PCD_SPEED PCD_SPEED_HIGH +#elif BSP_USBD_SPEED_HSINFS +#define USBD_PCD_SPEED PCD_SPEED_HIGH_IN_FULL +#else +#define USBD_PCD_SPEED PCD_SPEED_FULL +#endif + +#ifdef BSP_USBD_PHY_ULPI +#define USBD_PCD_PHY_MODULE PCD_PHY_ULPI +#elif BSP_USBD_PHY_UTMI +#define USBD_PCD_PHY_MODULE PCD_PHY_UTMI +#else +#define USBD_PCD_PHY_MODULE PCD_PHY_EMBEDDED +#endif + +#endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index 415fde543471..c219859ee51d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -179,6 +179,15 @@ extern "C" { #include "mp1/dac_config.h" #include "mp1/tim_config.h" #include "mp1/pwm_config.h" +#elif defined(SOC_SERIES_STM32N6) +#include "n6/dma_config.h" +#include "n6/uart_config.h" +#include "n6/spi_config.h" +#include "n6/adc_config.h" +#include "n6/dac_config.h" +#include "n6/tim_config.h" +#include "n6/pwm_config.h" +#include "n6/usbd_config.h" #elif defined(SOC_SERIES_STM32WL) #include "wl/dma_config.h" #include "wl/uart_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h index 83e1535e685b..804a3bb202c9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h @@ -37,7 +37,8 @@ extern "C" { #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1) \ + || defined(SOC_SERIES_STM32N6) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) @@ -45,15 +46,16 @@ extern "C" { #endif /* defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) -|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1)*/ +|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32L1) +|| defined(SOC_SERIES_STM32N6) */ #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) #define STM32_DMA_USES_CHANNEL #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ -#if defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) +#if defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) #define STM32_DMA_USES_GPDMA -#endif /* defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) */ +#endif /* defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) */ #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) \ @@ -80,7 +82,8 @@ extern "C" { #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \ || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) \ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) \ + || defined(SOC_SERIES_STM32N6) #define STM32_DMA_USES_RCC_AHB1ENR #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c index 1a6a294d6742..2d5b03d85691 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c @@ -93,7 +93,7 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_PIN_14, EXTI4_15_IRQn}, {GPIO_PIN_15, EXTI4_15_IRQn}, #elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) \ - || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) {GPIO_PIN_0, EXTI0_IRQn}, {GPIO_PIN_1, EXTI1_IRQn}, {GPIO_PIN_2, EXTI2_IRQn}, @@ -535,7 +535,7 @@ rt_inline void pin_irq_hdr(int irqno) } } -#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) +#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32N6) void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) { pin_irq_hdr(bit2bitno(GPIO_Pin)); @@ -586,7 +586,7 @@ void EXTI4_15_IRQHandler(void) rt_interrupt_leave(); } -#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS) +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) void EXTI0_IRQHandler(void) { rt_interrupt_enter(); diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pwm.c index 7d58c1ae7222..89d38e0afaa4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pwm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pwm.c @@ -180,6 +180,10 @@ static rt_uint64_t tim_clock_get(TIM_HandleTypeDef *htim) } #endif +#if defined (SOC_SERIES_STM32N6) + tim_clock = HAL_RCCEx_GetTIMGFreq(); +#endif + return tim_clock; } @@ -376,7 +380,8 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) tim->Init.CounterMode = TIM_COUNTERMODE_UP; tim->Init.Period = 1; tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) + tim->Init.RepetitionCounter = 0; +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32N6) tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; #endif if (HAL_TIM_Base_Init(tim) != HAL_OK) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c index 2d68d48403a9..3d69926f75bb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c @@ -248,6 +248,37 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur #endif /* SOC_SERIES_STM32H7) */ #endif /* APBPERIPH_BASE */ +#if defined(SOC_SERIES_STM32N6) + if (spi_drv->config->Instance == SPI1) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1); + } + else if (spi_drv->config->Instance == SPI2) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI2); + } + else if (spi_drv->config->Instance == SPI3) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI3); + } + else if (spi_drv->config->Instance == SPI4) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI4); + } + else if (spi_drv->config->Instance == SPI5) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI5); + } + else if (spi_drv->config->Instance == SPI6) + { + spi_clock = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); + } + else + { + spi_clock = HSI_VALUE; + } +#endif /* SOC_SERIES_STM32N6) */ + if (cfg->max_hz >= spi_clock / 2) { spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; @@ -312,7 +343,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->State = HAL_SPI_STATE_RESET; #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32WB) spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; -#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) +#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32N6) spi_handle->Init.NSS = SPI_NSS_SOFT; spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW; @@ -322,9 +353,13 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; - spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; + spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE; spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; +#if defined(SOC_SERIES_STM32N6) + spi_handle->Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY; + spi_handle->Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH; +#endif /* SOC_SERIES_STM32N6 */ #endif if (HAL_SPI_Init(spi_handle) != HAL_OK) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c index a443bc1494f4..aa07d9e6a59b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c @@ -88,7 +88,11 @@ void stm32_tim_pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_ RT_ASSERT(pclk1_doubler != RT_NULL); RT_ASSERT(pclk1_doubler != RT_NULL); +#if defined(SOC_SERIES_STM32N6) + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); +#else HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency); +#endif *pclk1_doubler = 1; *pclk2_doubler = 1; @@ -447,6 +451,9 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1; } +#endif +#if defined (SOC_SERIES_STM32N6) + prescaler_value = HAL_RCCEx_GetTIMGFreq() / 1000 /1000; #endif tim->Init.Period = 10000 - 1; tim->Init.Prescaler = prescaler_value; @@ -460,7 +467,7 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) tim->Init.CounterMode = TIM_COUNTERMODE_DOWN; } tim->Init.RepetitionCounter = 0; -#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32N6) tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; #endif if (HAL_TIM_Base_Init(tim) != HAL_OK) @@ -1060,7 +1067,11 @@ static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) } else { - val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq; +#if defined(SOC_SERIES_STM32N6) + val = HAL_RCCEx_GetTIMGFreq() / freq; +#else + val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq; +#endif } __HAL_TIM_SET_PRESCALER(tim, val - 1); diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c index b430b9829353..cf5f909a79c9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c @@ -340,7 +340,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c) #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) uart->handle.Instance->TDR = c; #else uart->handle.Instance->DR = c; @@ -362,7 +362,7 @@ static int stm32_getc(struct rt_serial_device *serial) #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) ch = uart->handle.Instance->RDR & uart->DR_mask; #else ch = uart->handle.Instance->DR & uart->DR_mask; @@ -506,7 +506,8 @@ static void uart_isr(struct rt_serial_device *serial) #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \ - && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) + && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) \ + && !defined(SOC_SERIES_STM32N6) #ifdef SOC_SERIES_STM32F3 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h index dc33c5441a7a..9685864993ec 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h @@ -27,7 +27,7 @@ int rt_hw_usart_init(void); || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ - || defined(SOC_SERIES_STM32MP1) + || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32N6) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c index 13412872c7ac..ebacd3d3ed47 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.c @@ -623,7 +623,8 @@ static void uart_isr(struct rt_serial_device *serial) #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \ - && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) + && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) \ + && !defined(SOC_SERIES_STM32N6) #ifdef SOC_SERIES_STM32F3 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF)) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h index edfa6336b5d6..cefecdf46db7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart_v2.h @@ -23,7 +23,7 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) #define UART_SET_TDR(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TDR = (__DATA__)) #define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->RDR & MASK) @@ -36,7 +36,7 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \ || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \ - || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) || defined(SOC_SERIES_STM32N6) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ || defined(SOC_SERIES_STM32MP1) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c index 85752530c2da..9297e1a79f1f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c @@ -177,6 +177,8 @@ void rt_hw_us_delay(rt_uint32_t us) } } +void MPU_Config(void); + /** * This function will initial STM32 board. */ diff --git a/bsp/stm32/libraries/Kconfig b/bsp/stm32/libraries/Kconfig index 4e5c98fd0986..fe80139e54cc 100644 --- a/bsp/stm32/libraries/Kconfig +++ b/bsp/stm32/libraries/Kconfig @@ -115,6 +115,12 @@ config SOC_SERIES_STM32WB select SOC_FAMILY_STM32 select PKG_USING_STM32WB_HAL_DRIVER +config SOC_SERIES_STM32N6 + bool + select ARCH_ARM_CORTEX_M85 + select SOC_FAMILY_STM32 + select PKG_USING_STM32N6_HAL_DRIVER + config BOARD_SERIES_STM32_NUCLEO_32 bool diff --git a/bsp/stm32/stm32n657-st-nucleo/.config b/bsp/stm32/stm32n657-st-nucleo/.config new file mode 100644 index 000000000000..21f9a9bdfafb --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/.config @@ -0,0 +1,1557 @@ +CONFIG_SOC_STM32N657=y +CONFIG_BOARD_STM32N657X0_NUCLEO=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M85=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +# CONFIG_ULOG_OUTPUT_LVL_EMERG is not set +# CONFIG_ULOG_OUTPUT_LVL_ALERT is not set +# CONFIG_ULOG_OUTPUT_LVL_CRIT is not set +# CONFIG_ULOG_OUTPUT_LVL_ERROR is not set +# CONFIG_ULOG_OUTPUT_LVL_WARNING is not set +# CONFIG_ULOG_OUTPUT_LVL_NOTICE is not set +# CONFIG_ULOG_OUTPUT_LVL_INFO is not set +# CONFIG_ULOG_OUTPUT_LVL_DEBUG is not set +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +CONFIG_ULOG_TIME_USING_TIMESTAMP=y +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +# end of log format + +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +CONFIG_PKG_USING_CMSIS_CORE=y +CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core" +CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y +CONFIG_PKG_CMSIS_CORE_VER="latest" +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +CONFIG_PKG_USING_STM32N6_HAL_DRIVER=y +CONFIG_PKG_STM32N6_HAL_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32n6_hal_driver" +CONFIG_PKG_USING_STM32N6_HAL_DRIVER_LATEST_VERSION=y +CONFIG_PKG_STM32N6_HAL_DRIVER_VER="latest" +CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER=y +CONFIG_PKG_STM32N6_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32n6_cmsis_driver" +CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_STM32N6_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_STM32N657xx_FSBL=y +CONFIG_PKG_STM32N657xx_FSBL_PATH="/packages/peripherals/hal-sdk/stm32/stm32n657xx_fsbl" +CONFIG_PKG_USING_STM32N657xx_FSBL_LATEST_VERSION=y +CONFIG_PKG_STM32N657xx_FSBL_VER="latest" +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set +# CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32N6=y +CONFIG_BOARD_SERIES_STM32_NUCLEO_144=y + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_RX_BUFSIZE=256 +CONFIG_BSP_UART1_TX_BUFSIZE=0 +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_UDID is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/stm32/stm32n657-st-nucleo/.gitignore b/bsp/stm32/stm32n657-st-nucleo/.gitignore new file mode 100644 index 000000000000..94b3f1fd13c6 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/.gitignore @@ -0,0 +1,44 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +__pycache__ +Objects diff --git a/bsp/stm32/stm32n657-st-nucleo/Kconfig b/bsp/stm32/stm32n657-st-nucleo/Kconfig new file mode 100644 index 000000000000..46b5e5eb5f91 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/Kconfig @@ -0,0 +1,28 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +config SOC_STM32N657 + bool + select SOC_SERIES_STM32N6 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select PKG_USING_STM32N657xx_FSBL + default y + +config BOARD_STM32N657X0_NUCLEO + bool + select BOARD_SERIES_STM32_NUCLEO_144 + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" + +if !RT_USING_NANO +rsource "board/Kconfig" +endif diff --git a/bsp/stm32/stm32n657-st-nucleo/Project.uvmpw b/bsp/stm32/stm32n657-st-nucleo/Project.uvmpw new file mode 100644 index 000000000000..47ecf33f7de2 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/Project.uvmpw @@ -0,0 +1,21 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + stm32n657-st-nucleo + + + .\packages\stm32n657xx_fsbl-latest\MDK-ARM\FSBL\stm32n657xx_fsbl.uvprojx + 1 + + + + .\project.uvprojx + 1 + 1 + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/README.md b/bsp/stm32/stm32n657-st-nucleo/README.md new file mode 100644 index 000000000000..1140d931e7ac --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/README.md @@ -0,0 +1,242 @@ +# STM32N657-st-nucleo Board BSP Introduction + +[中文](README_zh.md) + +## Introduction + +This document describes the BSP (Board Support Package) provided by tyustli for the STM32N657-st-nucleo development board. + +The main contents are as follows: + +- Development board resources +- BSP quick start +- Advanced usage + +By reading the Quick Start section, developers can quickly get started with this BSP and run RT-Thread on the development board. The Advanced Usage section introduces more advanced features to help developers use RT-Thread to drive more onboard resources. + +## Development Board Introduction + +The STM32N657 is a development board from ST based on the ARM Cortex-M55 core, with a maximum operating frequency of 800 MHz. The board provides abundant onboard resources to fully utilize the performance of the STM32N657 chip. + +The development board is shown below: + +![board](figures/board.jpg) + +The main **onboard resources** are as follows: + +- MCU: STM32N657, 800 MHz, with built-in 32 KB instruction cache (ICACHE) and 32 KB data cache (DCACHE) + - RAM: 4.2 MB of contiguous SRAM (divided into multiple memory groups) and 8 KB of backup SRAM (operating in VBAT mode) + - Accelerator: 1 GHz ST Neural-ART accelerator, providing 600 Gops + - GPU: Neo-Chrom GPU +- Common interfaces: USB-to-UART, Ethernet, Arduino, and others +- Onboard ST-LINK (ST-LINK/V2-1, STLINK-V3E, or STLINK-V3EC) debugger/programmer, supporting USB re-enumeration as mass storage, virtual COM port, and debug port + +For more information about the development board, see the ST [STM32N657](https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html) page. + +## Peripheral Support + +The current peripheral support status of this BSP is as follows: + +| **Onboard peripheral** | **Support status** | **Notes** | +| :--------------------- | :----------------: | :-------- | +| USB-to-UART | Supported | | +| **On-chip peripheral** | **Support status** | **Notes** | +| GPIO | Supported | | +| UART | Supported | UART1 | +| SPI | Supported | | +| PWM | Supported | | +| TIM | Supported | | + +## Usage Instructions + +The usage instructions are divided into the following sections: + +- STM32N657 startup process + + This section describes the STM32N657 startup process. + +- Configure environment variables for signing/programming tools + + This section configures the environment variables required for signing and programming firmware in the subsequent steps. + +- Quick start + + This section is intended for developers who are new to RT-Thread. By following the simple steps, you can run the RT-Thread operating system on the development board and see the results. + +- Advanced usage + + This section is intended for developers who need to use more development board resources with the RT-Thread operating system. More onboard resources can be enabled through BSP configuration with the ENV tool to implement additional advanced features. + +### STM32N657 Startup Process + +The STM32N6 is ST's first MCU with an NPU. It contains only a small ROM for the first boot stage, so user code must be stored in external Flash or booted through a USB or U(S)ART interface. + +There are three STM32N6 boot modes. This BSP uses the third mode: + +#### FSBL + +FSBL stands for First Stage Boot Loader. After power-on, the on-chip BootROM executes first. It then executes the FSBL at the corresponding address according to the boot options and address. The example below shows the boot process from external Flash. + +![image-20260911113129450](figures/image-20260911113129450.png) + +As shown above, the system startup process is as follows: + +1. After BootROM starts, it verifies the FSBL header. The dark yellow area in the figure contains the 1024-byte header information. The script provided by ST can be used to sign the FSBL; the FSBL must be signed or it cannot start correctly. After verification succeeds, BootROM copies the FSBL program to internal SRAM2 at `0x34180000`, then jumps the PC to that address to begin executing the FSBL. + +2. The FSBL begins execution. + +#### FSBL + Load & Run + +The application can be debugged in internal SRAM during development. After development is complete, it can be downloaded to external Flash through an external loader. + +![image-20260911113257650](figures/image-20260911113257650.png) + +As shown above, the system startup process is as follows: + +1. As with FSBL execution, BootROM starts first, verifies the FSBL, copies it to SRAM, and jumps to the FSBL. + +2. The FSBL begins execution, then copies the complete application to internal SRAM, including data and code. It then jumps to the application code. + +3. The application code begins execution. + +#### FSBL + XiP (Execute in Place) + +![image-20260911113738785](figures/image-20260911113738785.png) + +As shown above, the system startup process is as follows: + +1. BootROM begins execution. As in the first mode, after verifying the FSBL, it copies the FSBL to SRAM. + +2. The FSBL begins execution and configures the external Flash for XiP mode. After the FSBL completes, the PC jumps to the first instruction of the application in external Flash. + +3. The application begins execution. + +### Configure Environment Variables for Signing/Programming Tools + +The following instructions use Windows as an example. Three environment variables need to be configured: + +- Signing tool + +- Programming tool + +- Programming algorithm + +All three tools can be obtained from `STM32CubeIDE_2.1.1`. First, configure the signing and programming tools: + +![image-20260911110923343](figures/image-20260911110923343.png) + +The tools numbered 2 and 3 in the figure above are required. Add their paths to the system environment variables: + +![image-20260911110954590](figures/image-20260911110954590.png) + +Add the signing and programming tool paths to the environment variables as follows: + +![image-20260911111014180](figures/image-20260911111014180.png) + +The programming algorithm is located at the following path: + +![image-20260911111036134](figures/image-20260911111036134.png) + +Add the environment variable as follows: + +![image-20260911111101078](figures/image-20260911111101078.png) + +### Quick Start + +This BSP provides MDK5 and IAR projects and also supports the GCC development environment. The following describes how to run the system. + +**Important!** + +Before compiling, open ENV and run the following commands. These commands pull the required HAL and CMSIS packages; otherwise, compilation will fail: + +```bash +pkgs --upgrade +pkgs --update +``` + +#### Hardware Connection + +Use a USB Type-C to Type-C cable to connect the development board to the PC, and make sure that ST-Link is recognized in Device Manager. + +#### Build and Download + +##### MDK Environment + +Double-click the `Project.uvmpw` file to open the workspace containing the two MDK5 projects (FSBL and APP). + +Switch projects in the workspace: + +1. Right-click the workspace name. +2. Click `Manage Multi-Project Workspace...`. + +![image-20260911112015746](figures/image-20260911112015746.png) + +3. Select the project to switch to. +4. Click `Set as Active Project`. +5. Click `OK` to complete the switch. + +![image-20260911112425301](figures/image-20260911112425301.png) + +6. The workspace is now switched to the `stm32n657xx_fsbl` project. + +![image-20260911112556644](figures/image-20260911112556644.png) + +Build and download both projects separately. + +> The projects are configured to use the ST_LINK debugger for downloading by default. After connecting the development board through ST_LINK, click the download button to download the program to the board. + +##### SCons Environment + +1. Build the FSBL firmware: + +``` +scons fsbl -j16 +``` + +2. Build the APP firmware: + +``` +scons -j16 +``` + +The program can be downloaded using `tools\STM32N6固件烧录工具.exe`. + +After opening the programming tool, select `fsbl\Signing_Programmer.bat` as the FSBL programming script and `.\Signing_Programmer.bat` as the APP programming script. Click the "One-click download complete firmware" button to download the complete firmware. + +#### Running Result + +After the program is downloaded successfully, the system runs automatically and the LED blinks. + +Connect the corresponding serial port on the development board to the PC and open the serial port in a terminal tool (`115200-8-1-N`). After resetting the device, you can see the RT-Thread output: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.3.1 build Sep 11 2026 09:31:55 + 2006 - 2026 Copyright by RT-Thread team +msh > +``` + +### Advanced Usage + +This BSP enables only GPIO and UART1 by default. To use more advanced features, configure the BSP with the ENV tool as follows: + +1. Open the ENV tool in the `bsp` directory. + +2. Enter the `menuconfig` command to configure the project, then save and exit. + +3. Enter the `pkgs --update` command to update the software packages. + +4. Enter the `scons --target=mdk4/mdk5/iar` command to regenerate the project. + +For more information, see [STM32 Series BSP Peripheral Driver Usage Tutorial](../docs/STM32系列BSP外设驱动使用教程.md). + +## Notes + +- Debug serial port mapping for UART1: + + PE5 ------> VCP_TX + + PE6 ------> VCP_RX + +- If the FSBL project cannot be found during compilation, check whether the `stm32n657xx_fsbl-latest` package exists in the `packages` directory. diff --git a/bsp/stm32/stm32n657-st-nucleo/README_zh.md b/bsp/stm32/stm32n657-st-nucleo/README_zh.md new file mode 100644 index 000000000000..ace8de978229 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/README_zh.md @@ -0,0 +1,241 @@ +# STM32N657-st-nucleo 开发板 BSP 说明 + +## 简介 + +本文档为 tyustli 为 STM32N657-st-nucleo 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32N657 是 ST 推出的一款基于 ARM Cortex-M55 内核的开发板，最高主频为 800Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32N657 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32N657，主频 800MHz，内置32 KB ICACHE、32 KB DCACHE + - RAM：4.2 MB连续SRAM（分为多个存储组）、8 KB备用SRAM（在VBAT模式下工作） + - 加速器：1 GHz的ST Neural-ART加速器，可提供600 Gops + - GPU：Neo-Chrom GPU +- 常用接口：USB 转串口、以太网接口、arduino 接口等 +- 板载ST-LINK（ST-LINK/V2-1、STLINK-V3E或STLINK-V3EC）调试器/编程器，支持USB重新枚举功能：大容量存储器、虚拟COM端口和调试端口 + + +开发板更多详细信息请参考 ST [STM32N657](https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :----------------------------------| +| USB 转串口 | 支持 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART1 | +| SPI | 支持 | | +| PWM | 支持 | | +| TIM | 支持 | | + + +## 使用说明 + +使用说明分为如下三个章节： + +- STM32N657 启动流程 + +​ 本章节介绍 STM32N657 的启动流程。 + +- 配置签名/烧录工具的环境变量 + + 本章节是为后续给固件签名和烧录固件的步骤配置好环境变量。 + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### STM32N657 启动流程 + +STM32N6 是 ST 第一颗带 NPU 的 MCU 芯片，内部只有一小块 ROM 用于第一阶段的 Boot，必须使用外部 Flash 存储用户代码或通过 USB/U(S)ART 串口启动。 + +STM32N6 启动方式有以下三种（本 BSP 使用的是第三种）： + +#### FSBL + +FSBL 的全称为 First Stage Boot Loader, 在上电后，先执行片内 ROM 区域的 BootROM，然后根据 Boot 选项和地址，执行相应地址的 FSBL，参考下图实例为外部 Flash 的启动流程。 + +![image-20260911113129450](figures/image-20260911113129450.png) + +如上图，系统启动流程如下： + +1. BootROM 启动后，会验证 FSBL 的头，如上图深黄色部分 1024Bytes 的 Header 信息，可以使用 ST 提供的脚本对 FSBL 进行签名，FSBL 程序必须完成签名，不然无法正常启动。验证成功后，BootROM 将 FSBL 程序搬运至内部 SRAM2：0x34180000 的位置，然后PC 指针跳转过去开始执行 FSBL。 + +2. FSBL 开始执行。 + +#### FSBL+Load&Run + +APP 的开发可以在内部 SRAM 中调试完成，开发完成后通过 External loader 下载到外部 Flash。 + +![image-20260911113257650](figures/image-20260911113257650.png) + +如上图，系统启动流程如下： + +1. 和 FSBL 的执行一样，BootROM 先启动，然后校验，搬运 FSBL，并跳转到 FSBL。 + +2. FSBL 开始执行，然后拷贝 Appli 的完整内容到内部 SRAM，包括 data 和 code。然后跳转到 APP 代码进行执行。 + +3. APP 代码开始执行。 + +#### FSBL+XiP（Execute in Place） + +![image-20260911113738785](figures/image-20260911113738785.png) + +如上图，系统启动流程如下： + +1. BootROM 开始执行，和第一种方式一样，校验完 FSBL 后将其搬运到 SRAM 中。 + +2. FSBL 开始执行，将外部 Flash 配置为 XiP 模式，FSBL 完成后，将 PC 跳转至外部Flash 中 App 的第一条指令。 + +3. APP 开始执行。 + +### 配置签名/烧录工具的环境变量 + +这⾥以 Windows 为例，需要配置环境变量的有三点： + +- 签名工具 + +- 烧录工具 + +- 烧录算法 + +上述三个⼯具均可以从 `STM32CubeIDE_2.1.1` 获取，⾸先是签名与烧录⼯具： + +![image-20260911110923343](figures/image-20260911110923343.png) + +上图中的 2,3 号⼯具是我们需要的⼯具，所以将上述路径加⼊系统的环境变量： + +![image-20260911110954590](figures/image-20260911110954590.png) + +按下述⽅法将签名与烧录共⼯具的路径添加⾄环境变量： + +![image-20260911111014180](figures/image-20260911111014180.png) + +还有烧录算法，位于下述路径： + +![image-20260911111036134](figures/image-20260911111036134.png) + +环境变量添加⽅式如下： + +![image-20260911111101078](figures/image-20260911111101078.png) + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面介绍如何将系统运行起来。 + +**请注意！！！** + +在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）： + +```bash +pkgs --upgrade +pkgs --update +``` + +#### 硬件连接 + +使用 C to C 数据线连接开发板到 PC，确保设备管理器中识别到 ST-Link。 + +#### 编译下载 + +##### MDK 环境 + +双击 Project.uvmpw 文件，打开包含两个 MDK5 工程（FSBL 和 APP）的工作空间。 + +在工作空间中切换工程： + +1. 在工作空间名称上右键； +2. 点击 `Manage Multi-Project Workspace...`； + +![image-20260911112015746](figures/image-20260911112015746.png) + +3. 选择要切换的工程； +4. 点击 `Set as Active Project`； +5. 点击 `OK` 按钮完成切换； + +![image-20260911112425301](figures/image-20260911112425301.png) + +6. 此时已经切换到 `stm32n657xx_fsbl` 工程。 + +![image-20260911112556644](figures/image-20260911112556644.png) + +分别编译和烧录两个工程。 + +> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +##### Scons 环境 + +1. 编译 FSBL 固件： + +``` +scons fsbl -j16 +``` + +2. 编译 APP 固件 + +``` +scons -j16 +``` + +下载程序可以使用 `tools\STM32N6固件烧录工具.exe` 。 + +打开烧录工具之后，FSBL 烧录脚本选择 `fsbl\Signing_Programmer.bat`，APP 烧录脚本选择 `.\Signing_Programmer.bat`。点击 “一键烧录完整固件” 按钮即可下载程序。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.3.1 build Sep 11 2026 09:31:55 + 2006 - 2026 Copyright by RT-Thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 调试串口为串口1 映射说明 + + PE5 ------> VCP_TX + + PE6 ------> VCP_RX + +* 在编译时如果找不到 FSBL 工程，请检查 packages 目录下是否有 `stm32n657xx_fsbl-latest` 软件包。 \ No newline at end of file diff --git a/bsp/stm32/stm32n657-st-nucleo/SConscript b/bsp/stm32/stm32n657-st-nucleo/SConscript new file mode 100644 index 000000000000..613e34744bf7 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +Import('env') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +# STM32N657xx +# You can select chips from the list above +env.Append(CPPDEFINES = ['STM32N657xx', 'USE_HAL_DRIVER']) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32n657-st-nucleo/SConstruct b/bsp/stm32/stm32n657-st-nucleo/SConstruct new file mode 100644 index 000000000000..620248db2d3d --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "CMSIS-Core-latest"), + os.path.join("packages", "stm32n6_cmsis_driver-latest"), + os.path.join("packages", "stm32n6_hal_driver-latest"), + os.path.join("packages", "stm32n657xx_fsbl-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('env') +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32n657-st-nucleo/Signing_Programmer.bat b/bsp/stm32/stm32n657-st-nucleo/Signing_Programmer.bat new file mode 100644 index 000000000000..49c685a4a7d9 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/Signing_Programmer.bat @@ -0,0 +1,114 @@ +@echo off +chcp 65001 >nul 2>&1 +setlocal enabledelayedexpansion + +:: ===================== 用户可配置参数 ====================== +set "ORIGIN_BIN=rtthread.bin" +set "SIGNED_BIN=rtthread-trusted.bin" +set "SIGN_TOOL=STM32_SigningTool_CLI.exe" +set "FLASH_TOOL=STM32_Programmer_CLI" +set "FLASH_ADDR=0x70100000" + +echo. +echo ========================================================== +echo STM32N6 固件签名下载工具 +echo ========================================================== +echo ⚠ 请确认：Boot0 = 0，Boot1 = 1，设备处于 Develop 模式 +echo 正在检查工具与文件... + +:: ===================== 依赖检查 ===================== +if not exist "%ORIGIN_BIN%" ( + echo [错误] 未找到固件文件：%ORIGIN_BIN% + echo 请先完成编译生成固件。 + pause + exit /b 1 +) + +where %SIGN_TOOL% >nul 2>&1 || ( + echo [错误] 签名工具未找到：%SIGN_TOOL% + echo 请确保该工具已加入系统 PATH。 + pause + exit /b 1 +) + +where %FLASH_TOOL% >nul 2>&1 || ( + echo [错误] 下载工具未找到：%FLASH_TOOL% + echo 请确保 STM32CubeProgrammer 已加入 PATH。 + pause + exit /b 1 +) + +if not defined N6570_ExternalLoader ( + echo [错误] 外部加载器环境变量未配置：N6570_ExternalLoader + echo 请正确设置 External Loader 路径。 + pause + exit /b 1 +) + +echo [OK] 所有依赖检查通过！ + +:: ===================== 删除旧签名文件 ===================== +echo. +echo ---------------------------------------------------------- +echo 1/3 清理旧签名固件... +echo ---------------------------------------------------------- + +if exist "%SIGNED_BIN%" ( + echo [提示] 检测到旧文件：%SIGNED_BIN% + echo [处理] 正在删除旧文件... + del /f /q /a "%SIGNED_BIN%" >nul 2>&1 + + if exist "%SIGNED_BIN%" ( + echo [错误] 无法删除旧签名文件（可能被占用） + echo 请关闭相关程序后重试。 + pause + exit /b 1 + ) + echo [OK] 旧签名文件已删除 +) else ( + echo [OK] 无需清理 +) + +:: ===================== 固件签名 ===================== +echo. +echo ---------------------------------------------------------- +echo 2/3 正在为固件生成安全签名... +echo ---------------------------------------------------------- +echo [执行] %SIGN_TOOL% -bin "%ORIGIN_BIN%" -nk -of 0x80000000 -t fsbl -o "%SIGNED_BIN%" -hv 2.3 -dump "%SIGNED_BIN%" --align + +%SIGN_TOOL% -bin "%ORIGIN_BIN%" -nk -of 0x80000000 -t fsbl -o "%SIGNED_BIN%" -hv 2.3 -dump "%SIGNED_BIN%" --align + +if not exist "%SIGNED_BIN%" ( + echo [错误] 签名失败！未生成：%SIGNED_BIN% + pause + exit /b 1 +) + +echo [OK] 签名完成！输出文件：%SIGNED_BIN% + +:: ===================== 下载固件 ===================== +echo. +echo ---------------------------------------------------------- +echo 3/3 正在下载固件到 Flash 地址：%FLASH_ADDR% +echo ---------------------------------------------------------- +echo [执行] %FLASH_TOOL% -c port=SWD mode=HOTPLUG ap=1 -el "%N6570_ExternalLoader%" -hardRst -w "%SIGNED_BIN%" %FLASH_ADDR% + +%FLASH_TOOL% -c port=SWD mode=HOTPLUG ap=1 -el "%N6570_ExternalLoader%" -hardRst -w "%SIGNED_BIN%" %FLASH_ADDR% + +if %errorlevel% equ 0 ( + echo. + echo ========================================================== + echo ✔ 固件已成功烧录！ + echo ⚠ 请切换启动方式为：Boot0 = 0，Boot1 = 0（Flash 启动） + echo ========================================================== +) else ( + echo. + echo [错误] 烧录失败，请检查： + echo 1. SWD 连接是否正常 + echo 2. External Loader 路径是否正确 + echo 3. 芯片是否上电、BOOT 模式是否正确 +) + +echo. +pause +endlocal diff --git a/bsp/stm32/stm32n657-st-nucleo/applications/SConscript b/bsp/stm32/stm32n657-st-nucleo/applications/SConscript new file mode 100644 index 000000000000..9bb9abae897a --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32n657-st-nucleo/applications/main.c b/bsp/stm32/stm32n657-st-nucleo/applications/main.c new file mode 100644 index 000000000000..0982f0ba27a1 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-11-24 WangShun first version + */ + +#include +#include +#include + +/* defined the LED0 pin: PB7 */ +#define LED3_PIN GET_PIN(G, 0) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED3_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED3_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED3_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/.mxproject new file mode 100644 index 000000000000..c97f5e40e86d --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/.mxproject @@ -0,0 +1,65 @@ +[FSBL:PreviousGenFiles] +HeaderPath=..\FSBL\Inc +HeaderFiles=stm32n6xx_it.h;stm32n6xx_hal_conf.h;main.h; +SourcePath=..\FSBL\Src +SourceFiles=stm32n6xx_it.c;stm32n6xx_hal_msp.c;main.c; + +[FSBL:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[FSBL:PreviousUsedKeilFiles] +SourceFiles=..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rif.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_usart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_lpuart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart_ex.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rif.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart_ex.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rif.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_usart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_lpuart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[Appli:PreviousUsedKeilFiles] +SourceFiles=..\Appli\Src\main.c;..\Appli\Src\stm32n6xx_it.c;..\Appli\Src\stm32n6xx_hal_msp.c;..\Appli\Src\secure_nsc.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rif.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart_ex.c;..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=..\Drivers\STM32N6xx_HAL_Driver\Inc;..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Include;..\Appli\Inc;..\Secure_nsclib;..\Drivers\STM32N6xx_HAL_Driver\Inc;..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[ExtMemLoader:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[ExtMemLoader:PreviousUsedKeilFiles] +SourceFiles=..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;;; +HeaderPath=..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\CMSIS\Include; +CDefines=STM32N657xx; + +[PreviousLibFiles] +LibFiles=Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rif.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_usart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_lpuart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart_ex.h;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rif.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart.c;Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart_ex.c;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_cortex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rif.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_rcc_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_bus.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_rcc.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_system.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_utils.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_gpio_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_gpio.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_dma_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_dma.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_pwr_ex.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_pwr.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\partition_stm32n6xx.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_def.h;Drivers\STM32N6xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_exti.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_usart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_ll_lpuart.h;Drivers\STM32N6xx_HAL_Driver\Inc\stm32n6xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n657xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Include\system_stm32n6xx.h;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Appli\Src\main.c;..\Appli\Src\stm32n6xx_it.c;..\Appli\Src\stm32n6xx_hal_msp.c;..\Appli\Src\secure_nsc.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rif.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart_ex.c;..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;..\Src\system_stm32n6xx_s.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_cortex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rif.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_rcc_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_gpio.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_dma_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_pwr_ex.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_exti.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart.c;..\Drivers\STM32N6xx_HAL_Driver\Src\stm32n6xx_hal_uart_ex.c;..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx_s.c;..\Src\system_stm32n6xx_s.c;..\Drivers\CMSIS\Device\ST\STM32N6xx\Source\Templates\system_stm32n6xx.c;..\FSBL\\Src\;..\Appli\\Src\system_stm32n6xx_s.c;..\ExtMemLoader\\Src\;;; +HeaderPath=..\Drivers\STM32N6xx_HAL_Driver\Inc;..\Drivers\CMSIS\Device\ST\STM32N6xx\Include;..\Drivers\STM32N6xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Include;..\Appli\Inc;..\Secure_nsclib; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER; + +[FSBL:] +SourceFiles=;; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER; + +[Appli:] +SourceFiles=;; +CDefines=USE_HAL_DRIVER;STM32N657xx;USE_HAL_DRIVER; + +[ExtMemLoader:] +SourceFiles=;; +CDefines=STM32N657xx; + +[] +SourceFiles=;; + +[Appli:PreviousGenFiles] +HeaderPath=..\Appli\Inc +HeaderFiles=stm32n6xx_it.h;stm32n6xx_hal_conf.h;main.h;partition_stm32n657xx.h;secure_nsc.h; +SourcePath=..\Appli\Src +SourceFiles=stm32n6xx_it.c;stm32n6xx_hal_msp.c;main.c;secure_nsc.c; + +[PreviousGenFiles] +HeaderPath=..\Appli\Inc +HeaderFiles=stm32n6xx_it.h;stm32n6xx_hal_conf.h;main.h;partition_stm32n657xx.h;secure_nsc.h; +SourcePath=..\Appli\Src +SourceFiles=stm32n6xx_it.c;stm32n6xx_hal_msp.c;main.c;secure_nsc.c; + diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/main.h b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/main.h new file mode 100644 index 000000000000..fa176d4411e7 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/main.h @@ -0,0 +1,87 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined ( __ICCARM__ ) +# define CMSE_NS_CALL __cmse_nonsecure_call +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_CALL __attribute((cmse_nonsecure_call)) +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* Function pointer declaration in non-secure*/ +#if defined ( __ICCARM__ ) +typedef void (CMSE_NS_CALL *funcptr)(void); +#else +typedef void CMSE_NS_CALL (*funcptr)(void); +#endif + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/partition_stm32n657xx.h b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/partition_stm32n657xx.h new file mode 100644 index 000000000000..e16fc1cc1bcb --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/partition_stm32n657xx.h @@ -0,0 +1,786 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* +* Copyright (c) 2009-2016 ARM Limited. All rights reserved. +* Portions Copyright (c) 2023 STMicroelectronics, all rights reserved +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the License); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an AS IS BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ +/* USER CODE END Header */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ +/* USER CODE BEGIN 0 */ +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 +/* USER CODE END 0 */ +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ +/* USER CODE BEGIN 1 */ +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ +/* USER CODE END 1 */ +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 +/* +// Interrupts 0..31 +// PVD_PVM_IRQn <0=> Secure state +// Reserved <0=> Secure state +// DTS_IRQn <0=> Secure state +// RCC_IRQn <0=> Secure state +// LOCKUP_IRQn <0=> Secure state +// CACHE_ECC_IRQn <0=> Secure state +// TCM_ECC_IRQn <0=> Secure state +// BKP_ECC_IRQn <0=> Secure state +// FPU_IRQn <0=> Secure state +// Reserved <0=> Secure state +// RTC_S_IRQn <0=> Secure state +// TAMP_IRQn <0=> Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state +// IAC_IRQn <0=> Secure state +// RCC_S_IRQn <0=> Secure state +// Reserved <0=> Secure state +// RTC_IRQn <0=> Secure state +// Reserved <0=> Secure state +// IWDG_IRQn <0=> Secure state +// WWDG_IRQn <0=> Secure state +// EXTI0_IRQn <0=> Secure state +// EXTI1_IRQn <0=> Secure state +// EXTI2_IRQn <0=> Secure state +// EXTI3_IRQn <0=> Secure state +// EXTI4_IRQn <0=> Secure state +// EXTI5_IRQn <0=> Secure state +// EXTI6_IRQn <0=> Secure state +// EXTI7_IRQn <0=> Secure state +// EXTI8_IRQn <0=> Secure state +// EXTI9_IRQn <0=> Secure state +// EXTI10_IRQn <0=> Secure state +// EXTI11_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS0_VAL 0x00000000 +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +/ Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state +// EXTI13_IRQn <0=> Secure state +// EXTI14_IRQn <0=> Secure state +// EXTI15_IRQn <0=> Secure state +// SAES_IRQn <0=> Secure state +// CRYP_IRQn <0=> Secure state +// PKA_IRQn <0=> Secure state +// HASH_IRQn <0=> Secure state +// RNG_IRQn <0=> Secure state +// Reserved <0=> Secure state +// MCE1_IRQn <0=> Secure state +// MCE2_IRQn <0=> Secure state +// MCE3_IRQn <0=> Secure state +// MCE4_IRQn <0=> Secure state +// ADC1_2_IRQn <0=> Secure state +// CSI_IRQn <0=> Secure state +// DCMIPP_IRQn <0=> Secure state +// Reserved <0=> Secure state +// Reserved <0=> Secure state +// Reserved <0=> Secure state +// PAHB_ERR_IRQn <0=> Secure state +// NPU0_IRQn <0=> Secure state +// NPU1_IRQn <0=> Secure state +// NPU2_IRQn <0=> Secure state +// NPU3_IRQn <0=> Secure state +// CACHEAXI_IRQn <0=> Secure state +// LTDC_LO_IRQn <0=> Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state +// DMA2D_IRQn <0=> Secure state +// JPEG_IRQn <0=> Secure state +// VENC_IRQn <0=> Secure state +// GFXMMU_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state +// GPU2D_IRQn <0=> Secure state +// GPU2D_ER_IRQn <0=> Secure state +// ICACHE_IRQn <0=> Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state +// I2C1_EV_IRQn <0=> Secure state +// I2C1_ER_IRQn <0=> Secure state +// I2C2_EV_IRQn <0=> Secure state +// I2C2_ER_IRQn <0=> Secure state +// I2C3_EV_IRQn <0=> Secure state +// I2C3_ER_IRQn <0=> Secure state +// I2C4_EV_IRQn <0=> Secure state +// I2C4_ER_IRQn <0=> Secure state +// I3C1_EV_IRQn <0=> Secure state +// I3C1_ER_IRQn <0=> Secure state +// I3C2_EV_IRQn <0=> Secure state +// I3C2_ER_IRQn <0=> Secure state +// TIM1_BRK_IRQn <0=> Secure state +// TIM1_UP_IRQn <0=> Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state +// TIM1_CC_IRQn <0=> Secure state +// TIM2_IRQn <0=> Secure state +// TIM3_IRQn <0=> Secure state +// TIM4_IRQn <0=> Secure state +// TIM5_IRQn <0=> Secure state +// TIM6_IRQn <0=> Secure state +// TIM7_IRQn <0=> Secure state +// TIM8_BRK_IRQn <0=> Secure state +// TIM8_UP_IRQn <0=> Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state +// TIM8_CC_IRQn <0=> Secure state +// TIM9_IRQn <0=> Secure state +// TIM10_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state +// TIM12_IRQn <0=> Secure state +// TIM13_IRQn <0=> Secure state +// TIM14_IRQn <0=> Secure state +// TIM15_IRQn <0=> Secure state +// TIM16_IRQn <0=> Secure state +// TIM17_IRQn <0=> Secure state +// TIM18_IRQn <0=> Secure state +// LPTIM1_IRQn <0=> Secure state +// LPTIM2_IRQn <0=> Secure state +// LPTIM3_IRQn <0=> Secure state +// LPTIM4_IRQn <0=> Secure state +// LPTIM5_IRQn <0=> Secure state +// ADF1_FLT0_IRQn <0=> Secure state +// MDF1_FLT0_IRQn <0=> Secure state +// MDF1_FLT1_IRQn <0=> Secure state +// MDF1_FLT2_IRQn <0=> Secure state +// MDF1_FLT3_IRQn <0=> Secure state +// MDF1_FLT4_IRQn <0=> Secure state +// MDF1_FLT5_IRQn <0=> Secure state +// SAI1_A_IRQn <0=> Secure state +// SAI1_B_IRQn <0=> Secure state +// SAI2_A_IRQn <0=> Secure state +// SAI2_B_IRQn <0=> Secure state +// SPDIFRX1_IRQn <0=> Secure state +// SPI1_IRQn <0=> Secure state +// SPI2_IRQn <0=> Secure state +// SPI3_IRQn <0=> Secure state +// SPI4_IRQn <0=> Secure state +// SPI5_IRQn <0=> Secure state +// SPI6_IRQn <0=> Secure state +// USART1_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state +// USART3_IRQn <0=> Secure state +// UART4_IRQn <0=> Secure state +// UART5_IRQn <0=> Secure state +// USART6_IRQn <0=> Secure state +// UART7_IRQn <0=> Secure state +// UART8_IRQn <0=> Secure state +// UART9_IRQn <0=> Secure state +// USART10_IRQn <0=> Secure state +// LPUART1_IRQn <0=> Secure state +// XSPI1_IRQn <0=> Secure state +// XSPI2_IRQn <0=> Secure state +// XSPI3_IRQn <0=> Secure state +// FMC_IRQn <0=> Secure state +// SDMMC1_IRQn <0=> Secure state +// SDMMC2_IRQn <0=> Secure state +// UCPD1_IRQn <0=> Secure state +// USB1_OTG_HS_IRQn <0=> Secure state +// USB2_OTG_HS_IRQn <0=> Secure state +// ETH1_IRQn <0=> Secure state +// FDCAN1_IT0_IRQn <0=> Secure state +// FDCAN1_IT1_IRQn <0=> Secure state +// FDCAN2_IT0_IRQn <0=> Secure state +// FDCAN2_IT1_IRQn <0=> Secure state +// FDCAN3_IT0_IRQn <0=> Secure state +// FDCAN3_IT1_IRQn <0=> Secure state +// FDCAN_CU_IRQn <0=> Secure state +// MDIOS_IRQn <0=> Secure state +// DCMI_PSSI_IRQn <0=> Secure state +// WAKEUP_PIN_IRQn <0=> Secure state +// CTI_INT0_IRQn <0=> Secure state +// CTI_INT1_IRQn <0=> Secure state +*/ + +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 +/* +// Interrupts 192..223 +// USART2_IRQn <0=> Secure state +// USART3_IRQn <0=> Secure state +// UART4_IRQn <0=> Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* USER CODE BEGIN 2 */ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} +/* USER CODE END 2 */ +#endif /* PARTITION_STM32N657XX_H */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_hal_conf.h b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_hal_conf.h new file mode 100644 index 000000000000..840e811fc293 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_hal_conf.h @@ -0,0 +1,504 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +#define HAL_RIF_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ######################### */ + +#define USE_SDIO_TRANSCEIVER 0U +#define SDIO_MAX_IO_NUMBER 7U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_it.h b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_it.h new file mode 100644 index 000000000000..99ae9b7ce0f0 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Inc/stm32n6xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32N6xx_IT_H +#define __STM32N6xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SecureFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32N6xx_IT_H */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/secure_nsc.c b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/secure_nsc.c new file mode 100644 index 000000000000..c0e30f596b67 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/secure_nsc.c @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file Secure/Src/secure_nsc.c + * @author MCD Application Team + * @brief This file contains the non-secure callable APIs (secure world) + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* USER CODE BEGIN Non_Secure_CallLib */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "secure_nsc.h" +/** @addtogroup STM32N6xx_HAL_Examples + + * @{ + */ + +/** @addtogroup Templates + * @{ + */ + +/* Global variables ----------------------------------------------------------*/ +void *pSecureFaultCallback = NULL; /* Pointer to secure fault callback in Non-secure */ +void *pSecureErrorCallback = NULL; /* Pointer to secure error callback in Non-secure */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Secure registration of non-secure callback. + * @param CallbackId callback identifier + * @param func pointer to non-secure function + * @retval None + */ +CMSE_NS_ENTRY void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func) +{ + if(func != NULL) + { + switch(CallbackId) + { + case SECURE_FAULT_CB_ID: /* SecureFault Interrupt occurred */ + pSecureFaultCallback = func; + break; + case GTZC_ERROR_CB_ID: /* GTZC Interrupt occurred */ + pSecureErrorCallback = func; + break; + default: + /* unknown */ + break; + } + } +} + +/** + * @} + */ + +/** + * @} + */ +/* USER CODE END Non_Secure_CallLib */ + diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_hal_msp.c b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_hal_msp.c new file mode 100644 index 000000000000..daaa85cf372c --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_hal_msp.c @@ -0,0 +1,156 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ +#include "drv_common.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_CLKP; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**USART1 GPIO Configuration + PE5 ------> USART1_TX + PE6 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + + } + +} + +/** + * @brief UART MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PE5 ------> USART1_TX + PE6 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_5|GPIO_PIN_6); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_it.c b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_it.c new file mode 100644 index 000000000000..1c403387b958 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Appli/Src/stm32n6xx_it.c @@ -0,0 +1,218 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32n6xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32n6xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Secure fault. + */ +void SecureFault_Handler(void) +{ + /* USER CODE BEGIN SecureFault_IRQn 0 */ + + /* USER CODE END SecureFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_SecureFault_IRQn 0 */ + /* USER CODE END W1_SecureFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32N6xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32n6xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 000000000000..a8d25937a1d9 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,868 @@ +#MicroXplorer Configuration settings - do not modify +Appli.IPs=CORTEX_M55_S,GPDMA1,HPDMA1,LINKEDLIST,RCC,GPIO,NVIC1\:I,USART1,RIF +CAD.formats= +CAD.pinconfig= +CAD.provider= +ExtMemLoader.IPs=EXTMEM_LOADER,EXTMEM_MANAGER,RCC\:I,GPIO +FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I,USART1,SPI5,TIM1 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32N657X0H3Q +Mcu.Context0=FSBL +Mcu.Context1=Appli +Mcu.Context2=ExtMemLoader +Mcu.ContextNb=3 +Mcu.ContextProject=FullSecure +Mcu.Family=STM32N6 +Mcu.IP0=CORTEX_M55_FSBL +Mcu.IP1=CORTEX_M55_S +Mcu.IP2=NVIC1 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RIF +Mcu.IP6=SPI5 +Mcu.IP7=TIM1 +Mcu.IP8=USART1 +Mcu.IPNb=9 +Mcu.Name=STM32N657X0HxQ +Mcu.Package=VFBGA264 +Mcu.Pin0=PE13 +Mcu.Pin1=PE15 +Mcu.Pin2=PE9 +Mcu.Pin3=PE14 +Mcu.Pin4=PE5 +Mcu.Pin5=PE6 +Mcu.Pin6=PE11 +Mcu.Pin7=PG1 +Mcu.Pin8=PG2 +Mcu.Pin9=VP_RIF_VS_RIF1 +Mcu.PinsNb=10 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32N657X0HxQ +MxCube.Version=6.15.0 +MxDb.Version=DB.6.0.150 +NVIC.BFHFNMINS=0 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PRIS=0 +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.BFHFNMINS=0 +NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.ForceEnableDMAVector=true +NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PRIS=0 +NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PCC.Checker=false +PCC.Display=Plot\: All Steps +PCC.Line=STM32N6x7 +PCC.MCU=STM32N657X0HxQ +PCC.PartNumber=STM32N657X0HxQ +PCC.Series=STM32N6 +PCC.Temperature=25 +PCC.Vdd=1.8 +PE11.GPIOParameters=PinAttribute +PE11.PinAttribute=FSBL +PE11.Signal=S_TIM1_CH2 +PE13.GPIOParameters=PinAttribute +PE13.PinAttribute=FSBL +PE13.Signal=S_TIM1_CH3 +PE14.GPIOParameters=PinAttribute +PE14.PinAttribute=FSBL +PE14.Signal=S_TIM1_CH4 +PE15.GPIOParameters=PinAttribute +PE15.Locked=true +PE15.Mode=Full_Duplex_Master +PE15.PinAttribute=FSBL +PE15.Signal=SPI5_SCK +PE5.GPIOParameters=PinAttribute +PE5.Locked=true +PE5.Mode=Asynchronous +PE5.PinAttribute=FSBL,Appli +PE5.Signal=USART1_TX +PE6.GPIOParameters=PinAttribute +PE6.Locked=true +PE6.Mode=Asynchronous +PE6.PinAttribute=FSBL,Appli +PE6.Signal=USART1_RX +PE9.GPIOParameters=PinAttribute +PE9.PinAttribute=FSBL +PE9.Signal=S_TIM1_CH1 +PG1.GPIOParameters=PinAttribute +PG1.Locked=true +PG1.Mode=Full_Duplex_Master +PG1.PinAttribute=FSBL +PG1.Signal=SPI5_MISO +PG2.GPIOParameters=PinAttribute +PG2.Locked=true +PG2.Mode=Full_Duplex_Master +PG2.PinAttribute=FSBL +PG2.Signal=SPI5_MOSI +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32N657X0HxQ +ProjectManager.FirmwarePackage=STM32Cube FW_N6 V1.2.0 +ProjectManager.FreePins=false +ProjectManager.FreePinsContext=FSBL +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=FSBL-0x200,Appli-0x200,ExtMemLoader-0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.ProjectStructure=FSBL\:FSBL\:false;Appli\:Appli\:true;ExtMemLoader\:ExtMemLoader\:false; +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=FSBL-0x800,Appli-0x800,ExtMemLoader-0x800 +ProjectManager.TargetToolchain=MDK-ARM V5.32 +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-true-FSBL,2-MX_GPIO_Init-GPIO-false-HAL-true-FSBL,3-MX_USART1_UART_Init-USART1-false-HAL-true-FSBL,4-MX_SPI5_Init-SPI5-false-HAL-true-FSBL,5-MX_TIM1_Init-TIM1-false-HAL-true-FSBL,1-MX_GPIO_Init-GPIO-false-HAL-true-Appli,2-MX_USART1_UART_Init-USART1-false-HAL-true-Appli,3-SystemIsolation_Config-RIF-false-HAL-true-Appli,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli +RCC.ADC12Freq_Value=200000000 +RCC.ADFFreq_Value=200000000 +RCC.AHB1234Freq_Value=200000000 +RCC.AHBFreq_Value=75000000 +RCC.APB1Freq_Value=200000000 +RCC.APB2Freq_Value=200000000 +RCC.APB4Freq_Value=200000000 +RCC.APB5Freq_Value=200000000 +RCC.AXIClockFreq_Value=400000000 +RCC.CKPERFreq_Value=64000000 +RCC.CPUCLKSource=RCC_CPUCLKSOURCE_IC1 +RCC.CortexFreq_Value=75000000 +RCC.CpuClockFreq_Value=600000000 +RCC.DCMIPPFreq_Value=200000000 +RCC.ETH1Freq_Value=200000000 +RCC.FBDIV1=75 +RCC.FDCANFreq_Value=200000000 +RCC.FMCFreq_Value=200000000 +RCC.FOUTPOSTDIV1Freq_Value=1200000000 +RCC.FOUTPOSTDIV2Freq_Value=1600000000 +RCC.FOUTPOSTDIV3Freq_Value=1600000000 +RCC.FOUTPOSTDIV4Freq_Value=1600000000 +RCC.FREFDIV1=4 +RCC.FamilyName=M +RCC.HSE_VALUE=48000000 +RCC.HSI_VALUE=64000000 +RCC.I2C1Freq_Value=200000000 +RCC.I2C2Freq_Value=200000000 +RCC.I2C3Freq_Value=200000000 +RCC.I2C4Freq_Value=200000000 +RCC.I3C1Freq_Value=200000000 +RCC.I3C2Freq_Value=200000000 +RCC.IC10Freq_VALUE=1600000000 +RCC.IC11Div=3 +RCC.IC11Freq_VALUE=400000000 +RCC.IC12Freq_VALUE=1600000000 +RCC.IC13Freq_VALUE=1600000000 +RCC.IC14Freq_VALUE=1600000000 +RCC.IC15Freq_VALUE=1600000000 +RCC.IC16Freq_VALUE=1600000000 +RCC.IC17Freq_VALUE=1600000000 +RCC.IC18Freq_VALUE=1600000000 +RCC.IC19Freq_VALUE=1600000000 +RCC.IC1Div=2 +RCC.IC1Freq_VALUE=600000000 +RCC.IC20Freq_VALUE=1600000000 +RCC.IC2Div=3 +RCC.IC2Freq_VALUE=400000000 +RCC.IC3Freq_VALUE=1200000000 +RCC.IC4Freq_VALUE=1200000000 +RCC.IC5Freq_VALUE=1200000000 +RCC.IC6Freq_VALUE=300000000 +RCC.IC7Freq_VALUE=1600000000 +RCC.IC8Freq_VALUE=1600000000 +RCC.IC9Freq_VALUE=1600000000 +RCC.IPParameters=ADC12Freq_Value,ADFFreq_Value,AHB1234Freq_Value,AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,CKPERFreq_Value,CPUCLKSource,CortexFreq_Value,CpuClockFreq_Value,DCMIPPFreq_Value,ETH1Freq_Value,FBDIV1,FDCANFreq_Value,FMCFreq_Value,FOUTPOSTDIV1Freq_Value,FOUTPOSTDIV2Freq_Value,FOUTPOSTDIV3Freq_Value,FOUTPOSTDIV4Freq_Value,FREFDIV1,FamilyName,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,I3C2Freq_Value,IC10Freq_VALUE,IC11Div,IC11Freq_VALUE,IC12Freq_VALUE,IC13Freq_VALUE,IC14Freq_VALUE,IC15Freq_VALUE,IC16Freq_VALUE,IC17Freq_VALUE,IC18Freq_VALUE,IC19Freq_VALUE,IC1Div,IC1Freq_VALUE,IC20Freq_VALUE,IC2Div,IC2Freq_VALUE,IC3Freq_VALUE,IC4Freq_VALUE,IC5Freq_VALUE,IC6Freq_VALUE,IC7Freq_VALUE,IC8Freq_VALUE,IC9Freq_VALUE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPUART1Freq_Value,LSE_VALUE,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MDFFreq_Value,MSI_VALUE,OTGHS1Freq_Value,OTGHS2Freq_Value,OTGPHY1Freq_Value,OTGPHY2Freq_Value,PLL1FRACV,PLL2FRACV,PLL3FRACV,PLL4FRACV,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPDIFRX1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5ClockSelection,SPI5Freq_Value,SPI6Freq_Value,SYSBCLKFreq_VALUE,SYSBCLKSource,SYSCCLKFreq_VALUE,SYSDCLKFreq_VALUE,TIMGFreq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,USART10Freq_Value,USART1ClockSelection,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value,XSPI1Freq_Value,XSPI2Freq_Value,XSPI3Freq_Value +RCC.LPTIM1Freq_Value=200000000 +RCC.LPTIM2Freq_Value=200000000 +RCC.LPTIM3Freq_Value=200000000 +RCC.LPTIM4Freq_Value=200000000 +RCC.LPTIM5Freq_Value=200000000 +RCC.LPUART1Freq_Value=200000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.LTDCFreq_Value=200000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=64000000 +RCC.MDFFreq_Value=200000000 +RCC.MSI_VALUE=16000000 +RCC.OTGHS1Freq_Value=24000000 +RCC.OTGHS2Freq_Value=24000000 +RCC.OTGPHY1Freq_Value=24000000 +RCC.OTGPHY2Freq_Value=24000000 +RCC.PLL1FRACV=0 +RCC.PLL2FRACV=0 +RCC.PLL3FRACV=0 +RCC.PLL4FRACV=0 +RCC.PSSIFreq_Value=200000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=200000000 +RCC.SAI2Freq_Value=200000000 +RCC.SDMMC1Freq_Value=200000000 +RCC.SDMMC2Freq_Value=200000000 +RCC.SPDIFRX1Freq_Value=200000000 +RCC.SPI1Freq_Value=200000000 +RCC.SPI2Freq_Value=200000000 +RCC.SPI3Freq_Value=200000000 +RCC.SPI4Freq_Value=200000000 +RCC.SPI5ClockSelection=RCC_SPI5CLKSOURCE_CLKP +RCC.SPI5Freq_Value=64000000 +RCC.SPI6Freq_Value=200000000 +RCC.SYSBCLKFreq_VALUE=400000000 +RCC.SYSBCLKSource=RCC_SYSCLKSOURCE_IC2_IC6_IC11 +RCC.SYSCCLKFreq_VALUE=300000000 +RCC.SYSDCLKFreq_VALUE=400000000 +RCC.TIMGFreq_Value=400000000 +RCC.UART4Freq_Value=200000000 +RCC.UART5Freq_Value=200000000 +RCC.UART7Freq_Value=200000000 +RCC.UART8Freq_Value=200000000 +RCC.UART9Freq_Value=200000000 +RCC.USART10Freq_Value=200000000 +RCC.USART1ClockSelection=RCC_USART1CLKSOURCE_CLKP +RCC.USART1Freq_Value=64000000 +RCC.USART2Freq_Value=200000000 +RCC.USART3Freq_Value=200000000 +RCC.USART6Freq_Value=200000000 +RCC.VCO1OutputFreq_Value=1200000000 +RCC.VCO2OutputFreq_Value=1600000000 +RCC.VCO3OutputFreq_Value=1600000000 +RCC.VCO4OutputFreq_Value=1600000000 +RCC.VCOInput1Freq_Value=16000000 +RCC.VCOInput2Freq_Value=64000000 +RCC.VCOInput3Freq_Value=64000000 +RCC.VCOInput4Freq_Value=64000000 +RCC.XSPI1Freq_Value=200000000 +RCC.XSPI2Freq_Value=200000000 +RCC.XSPI3Freq_Value=200000000 +RIF.DCMIPP_CID_RIMU=0 +RIF.DMA2D_CID_RIMU=0 +RIF.ETH1_CID_RIMU=0 +RIF.ETR_CID_RIMU=0 +RIF.GPU_CID_RIMU=0 +RIF.IPParameters=ETR_CID_RIMU,SDMMC1_CID_RIMU,SDMMC2_CID_RIMU,OTG1_CID_RIMU,OTG2_CID_RIMU,ETH1_CID_RIMU,GPU_CID_RIMU,DMA2D_CID_RIMU,DCMIPP_CID_RIMU,LTDC_L1_CID_RIMU,LTDC_L2_CID_RIMU,VENC_CID_RIMU +RIF.LTDC_L1_CID_RIMU=0 +RIF.LTDC_L2_CID_RIMU=0 +RIF.OTG1_CID_RIMU=0 +RIF.OTG2_CID_RIMU=0 +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PA9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PB9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PC9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PD9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE11\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE11\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE13\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE13\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE14\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE14\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE15\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE15\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Appli=true +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE5\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE5\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Appli=true +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE6\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE6\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PE8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PE9\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PE9\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PF9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PG1\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PG1\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Cid=1 +RIF.RIFAWARE.GPIO\ Feature\ PG2\ FSBL=true +RIF.RIFAWARE.GPIO\ Feature\ PG2\ Secure=true +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PG9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PH9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PN9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PO5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP10\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP11\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP12\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP13\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP14\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP15\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP7\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP8\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PP9\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Secure=false +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Cid=- +RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Secure=false +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Cid=- +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Privilege=true +RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Secure=false +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Cid=- +RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Secure=false +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Cid=- +RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Cid=- +RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Secure=false +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Cid=- +RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Secure=false +RIF.SDMMC1_CID_RIMU=0 +RIF.SDMMC2_CID_RIMU=0 +RIF.VENC_CID_RIMU=0 +RIF.default_config=false +SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 +SH.S_TIM1_CH1.ConfNb=1 +SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2 +SH.S_TIM1_CH2.ConfNb=1 +SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3 +SH.S_TIM1_CH3.ConfNb=1 +SH.S_TIM1_CH4.0=TIM1_CH4,PWM Generation4 CH4 +SH.S_TIM1_CH4.ConfNb=1 +SPI5.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 +SPI5.CRCCalculation=SPI_CRCCALCULATION_DISABLE +SPI5.CalculateBaudRate=8.0 MBits/s +SPI5.DataSize=SPI_DATASIZE_8BIT +SPI5.Direction=SPI_DIRECTION_2LINES +SPI5.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CRCCalculation +SPI5.Mode=SPI_MODE_MASTER +SPI5.VirtualType=VM_MASTER +TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM1.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,PulseNoDither_1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,PulseNoDither_2,PulseNoDither_3,PulseNoDither_4 +TIM1.PeriodNoDither=39 +TIM1.Prescaler=399 +TIM1.PulseNoDither_1=20 +TIM1.PulseNoDither_2=20 +TIM1.PulseNoDither_3=20 +TIM1.PulseNoDither_4=20 +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +VP_RIF_VS_RIF1.Mode=RISUP +VP_RIF_VS_RIF1.Signal=RIF_VS_RIF1 +board=custom diff --git a/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Secure_nsclib/secure_nsc.h b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Secure_nsclib/secure_nsc.h new file mode 100644 index 000000000000..f62c61405997 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/CubeMX_Config/Secure_nsclib/secure_nsc.h @@ -0,0 +1,46 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file Secure_nsclib/secure_nsc.h + * @author MCD Application Team + * @brief Header for secure non-secure callable APIs list + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* USER CODE BEGIN Non_Secure_CallLib_h */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef SECURE_NSC_H +#define SECURE_NSC_H + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief non-secure callback ID enumeration definition + */ +typedef enum +{ + SECURE_FAULT_CB_ID = 0x00U, /*!< System secure fault callback ID */ + GTZC_ERROR_CB_ID = 0x01U /*!< GTZC secure error callback ID */ +} SECURE_CallbackIDTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func); + +#endif /* SECURE_NSC_H */ +/* USER CODE END Non_Secure_CallLib_h */ + diff --git a/bsp/stm32/stm32n657-st-nucleo/board/Kconfig b/bsp/stm32/stm32n657-st-nucleo/board/Kconfig new file mode 100644 index 000000000000..57fdfbf9aeaa --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/Kconfig @@ -0,0 +1,134 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_ENABLE_MPU + bool "Enable MPU" + default y + + config BSP_SCB_ENABLE_I_CACHE + bool "Enable ICACHE" + default y + + config BSP_SCB_ENABLE_D_CACHE + bool "Enable DCACHE" + default y + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_STM32_UART_V1_TX_TIMEOUT + int "UART TX timeout" + default 6000 + depends on RT_USING_SERIAL_V1 + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n + + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output PWM" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH1 + bool "Enable PWM1 channel1" + default n + config BSP_USING_PWM1_CH2 + bool "Enable PWM1 channel2" + default n + config BSP_USING_PWM1_CH3 + bool "Enable PWM1 channel3" + default n + config BSP_USING_PWM1_CH4 + bool "Enable PWM1 channel4" + default n + endif + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + endif + + source "$(BSP_DIR)/../../libraries/HAL_Drivers/drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32n657-st-nucleo/board/SConscript b/bsp/stm32/stm32n657-st-nucleo/board/SConscript new file mode 100644 index 000000000000..6103d7a86925 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/SConscript @@ -0,0 +1,28 @@ +import os +from building import * +Import('rtconfig') + +cwd = GetCurrentDir() + +src = Split(''' +board.c +CubeMX_Config/Appli/Src/secure_nsc.c +CubeMX_Config/Appli/Src/stm32n6xx_hal_msp.c +''') + +path = [cwd] +path += [os.path.join(cwd, 'CubeMX_Config', 'Appli', 'Inc')] +path += [os.path.join(cwd, 'CubeMX_Config', 'Secure_nsclib')] + +# STM32N657xx +# You can select chips from the list above +CPPDEFINES = ['STM32N657xx'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32n657-st-nucleo/board/board.c b/bsp/stm32/stm32n657-st-nucleo/board/board.c new file mode 100644 index 000000000000..ab36c6b6be4f --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/board.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-11-24 WangShun first version + */ + +#include "board.h" + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the System Power Supply + */ + if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) + { + Error_Handler(); + } + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } + + /* Enable HSI */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Get current CPU/System buses clocks configuration and if necessary switch + to intermediate HSI clock to ensure target clock can be set + */ + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); + if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) || + (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) + { + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_NONE; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL1.PLLM = 4; + RCC_OscInitStruct.PLL1.PLLN = 75; + RCC_OscInitStruct.PLL1.PLLFractional = 0; + RCC_OscInitStruct.PLL1.PLLP1 = 1; + RCC_OscInitStruct.PLL1.PLLP2 = 1; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_CPUCLK|RCC_CLOCKTYPE_HCLK + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2|RCC_CLOCKTYPE_PCLK5 + |RCC_CLOCKTYPE_PCLK4; + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1; + RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC1Selection.ClockDivider = 2; + RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC2Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC6Selection.ClockDivider = 4; + RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC11Selection.ClockDivider = 3; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32n657-st-nucleo/board/board.h b/bsp/stm32/stm32n657-st-nucleo/board/board.h new file mode 100644 index 000000000000..c77731ea279e --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/board.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "stm32n6xx.h" +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (2048 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#define STM32_SRAM_SIZE (2048) +#define STM32_SRAM_END (0x34000000 + STM32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int _ebss; +#define HEAP_BEGIN (&_ebss) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.ld b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.ld new file mode 100644 index 000000000000..60cd008cdefa --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.ld @@ -0,0 +1,224 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32N657X0HxQ Device from STM32N6 series +** 2048KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x70100400, LENGTH = 511K + RAM (xrw) : ORIGIN = 0x34000000, LENGTH = 2048K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.sct b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.sct new file mode 100644 index 000000000000..7d7f26b55256 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_app.sct @@ -0,0 +1,107 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc + + +/*--------------------- ROM Configuration ---------------------------------- +; ROM Configuration +; ROM Base Address <0x0-0xFFFFFFFF:8> +; ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x70100400 +#define __ROM_SIZE 0x001DFC00 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x34000000 +#define __RAM_SIZE 0x00100000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000800 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000000 + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __CMSEVENEER_SIZE 0x00002000 + +/* +// <<< end of configuration section >>> + */ + +#define __STACKSEAL_SIZE ( 8 ) + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE ) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE - __STACKSEAL_SIZE ) + +#define __ER_BASE __RW_BASE + __RW_SIZE +#define __ER_SIZE 0x10000 + + + + + +LR_IROM1 0x70100400 0x001DFC00 { ; load region size_region + ER_IROM1 0x70100400 0x001DFC00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_IRAM1 0x34000000 0x00100000 { ; RW data + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER +0 ALIGN 0x4 { ; RW non-cacheable data + .ANY (.noncacheable_buffer) + } + + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} + diff --git a/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.ld b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.ld new file mode 100644 index 000000000000..12d6a7f7ce9d --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.ld @@ -0,0 +1,227 @@ +/* +****************************************************************************** +** +** @file : STM32N6XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N6XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x800; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.sct b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.sct new file mode 100644 index 000000000000..aa446fd74eb2 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/board/linker_scripts/link_fsbl.sct @@ -0,0 +1,107 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc + + +/*--------------------- ROM Configuration ---------------------------------- +; ROM Configuration +; ROM Base Address <0x0-0xFFFFFFFF:8> +; ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x34180400 +#define __ROM_SIZE 0x0003FC00 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x341C0000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000800 +#define __HEAP_SIZE 0x00000200 + +/* +// NOINIT Data Configuration +// specify the size of the section which holds the uninitialized data +// NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __NOINIT_SIZE 0x00000000 + +/* +// CMSE Veneer Configuration +// CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +// + */ +#define __CMSEVENEER_SIZE 0x00002000 + +/* +// <<< end of configuration section >>> + */ + +#define __STACKSEAL_SIZE ( 8 ) + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP ( __RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE ) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) + +#define __LR_BASE ( __ROM_BASE ) +#define __LR_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE - __STACKSEAL_SIZE ) + +#define __ER_BASE __RW_BASE + __RW_SIZE +#define __ER_SIZE 0x10000 + + + + + +LR_IROM1 0x34180400 0x0003FC00 { ; load region size_region + ER_IROM1 0x34180400 0x0003FC00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_IRAM1 0x341C0000 0x00040000 { ; RW data + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER +0 ALIGN 0x4 { ; RW non-cacheable data + .ANY (.noncacheable) + } + + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} + diff --git a/bsp/stm32/stm32n657-st-nucleo/build_app.bat b/bsp/stm32/stm32n657-st-nucleo/build_app.bat new file mode 100644 index 000000000000..28618bbd3227 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/build_app.bat @@ -0,0 +1,117 @@ +@echo off +setlocal + +REM ============================================================ +REM APP Build Script +REM %1 = AXF file path (#L) +REM %2 = Project path ($P) +REM ============================================================ + +set "AXF=%~1" +set "PROJECT=%~2" + +if not defined AXF ( + echo ERROR: AXF path is empty. + exit /b 1 +) + +if not defined PROJECT ( + echo ERROR: Project path is empty. + exit /b 1 +) + +if not exist "%AXF%" ( + echo ERROR: AXF file not found: + echo %AXF% + exit /b 1 +) + +REM Get AXF directory and filename +for %%F in ("%AXF%") do ( + set "AXF_DIR=%%~dpF" + set "AXF_NAME=%%~nxF" + set "BIN_NAME=%%~nF.bin" +) + +set "BIN=%AXF_DIR%%BIN_NAME%" + +echo. +echo ========================================== +echo APP Build / Sign +echo ========================================== +echo AXF : %AXF% +echo BIN : %BIN% +echo PROJECT : %PROJECT% +echo. + +REM ------------------------------------------------------------ +REM 1. Check BIN +REM ------------------------------------------------------------ +if not exist "%BIN%" ( + echo ERROR: BIN file not found: + echo %BIN% + exit /b 1 +) + +REM ------------------------------------------------------------ +REM 2. Copy BIN to project directory +REM ------------------------------------------------------------ +echo Copying BIN... +copy /Y "%BIN%" "%PROJECT%\" + +if errorlevel 1 ( + echo ERROR: Failed to copy BIN. + exit /b 1 +) + +REM ------------------------------------------------------------ +REM 3. Sign APP +REM ------------------------------------------------------------ +echo. +echo Signing APP... + +where STM32_SigningTool_CLI.exe >nul 2>&1 +if errorlevel 1 ( + echo ERROR: STM32_SigningTool_CLI.exe not found. + exit /b 1 +) + +if exist "%PROJECT%\rtthread-trusted.bin" ( + del /f /q "%PROJECT%\rtthread-trusted.bin" >nul 2>&1 + if exist "%PROJECT%\rtthread-trusted.bin" ( + echo ERROR: Cannot remove old signed APP image. + exit /b 1 + ) +) + +STM32_SigningTool_CLI.exe ^ + -bin "%PROJECT%\%BIN_NAME%" ^ + -nk ^ + -of 0x80000000 ^ + -t fsbl ^ + -o "%PROJECT%\rtthread-trusted.bin" ^ + -hv 2.3 ^ + -dump "%PROJECT%\rtthread-trusted.bin" ^ + --align + +if errorlevel 1 ( + echo. + echo ERROR: Signing failed. + exit /b 1 +) + +if not exist "%PROJECT%\rtthread-trusted.bin" ( + echo. + echo ERROR: Signed APP image was not generated. + exit /b 1 +) + +echo. +echo ========================================== +echo APP build and signing completed. +echo Output: +echo %PROJECT%\rtthread-trusted.bin +echo ========================================== + +endlocal +exit /b 0 diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/board.jpg b/bsp/stm32/stm32n657-st-nucleo/figures/board.jpg new file mode 100644 index 000000000000..239ef58b8c2d Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/board.jpg differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110923343.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110923343.png new file mode 100644 index 000000000000..341d6745db37 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110923343.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110954590.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110954590.png new file mode 100644 index 000000000000..80c408637059 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911110954590.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111014180.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111014180.png new file mode 100644 index 000000000000..499711ee74d3 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111014180.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111036134.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111036134.png new file mode 100644 index 000000000000..df2a954ae204 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111036134.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111101078.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111101078.png new file mode 100644 index 000000000000..acfbfa5d9f9c Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911111101078.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112015746.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112015746.png new file mode 100644 index 000000000000..d0aa1ceb8a26 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112015746.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112425301.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112425301.png new file mode 100644 index 000000000000..f6510c7fd07c Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112425301.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112556644.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112556644.png new file mode 100644 index 000000000000..efafc0330d3f Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911112556644.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113129450.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113129450.png new file mode 100644 index 000000000000..c6e630b0a4c2 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113129450.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113257650.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113257650.png new file mode 100644 index 000000000000..6774ca823084 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113257650.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113738785.png b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113738785.png new file mode 100644 index 000000000000..e71440af5932 Binary files /dev/null and b/bsp/stm32/stm32n657-st-nucleo/figures/image-20260911113738785.png differ diff --git a/bsp/stm32/stm32n657-st-nucleo/fsbl/Signing_Programmer.bat b/bsp/stm32/stm32n657-st-nucleo/fsbl/Signing_Programmer.bat new file mode 100644 index 000000000000..3d9f4c9ee794 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/fsbl/Signing_Programmer.bat @@ -0,0 +1,114 @@ +@echo off +chcp 65001 >nul 2>&1 +setlocal enabledelayedexpansion + +:: ===================== 用户可配置参数 ====================== +set "ORIGIN_BIN=stm32n657xx_fsbl.bin" +set "SIGNED_BIN=stm32n657xx_fsbl-trusted.bin" +set "SIGN_TOOL=STM32_SigningTool_CLI.exe" +set "FLASH_TOOL=STM32_Programmer_CLI" +set "FLASH_ADDR=0x70000000" + +echo. +echo ========================================================== +echo STM32N6 固件签名下载工具 +echo ========================================================== +echo ⚠ 请确认：Boot0 = 0，Boot1 = 1，设备处于 Develop 模式 +echo 正在检查工具与文件... + +:: ===================== 依赖检查 ===================== +if not exist "%ORIGIN_BIN%" ( + echo [错误] 未找到固件文件：%ORIGIN_BIN% + echo 请先完成编译生成固件。 + pause + exit /b 1 +) + +where %SIGN_TOOL% >nul 2>&1 || ( + echo [错误] 签名工具未找到：%SIGN_TOOL% + echo 请确保该工具已加入系统 PATH。 + pause + exit /b 1 +) + +where %FLASH_TOOL% >nul 2>&1 || ( + echo [错误] 下载工具未找到：%FLASH_TOOL% + echo 请确保 STM32CubeProgrammer 已加入 PATH。 + pause + exit /b 1 +) + +if not defined N6570_ExternalLoader ( + echo [错误] 外部加载器环境变量未配置：N6570_ExternalLoader + echo 请正确设置 External Loader 路径。 + pause + exit /b 1 +) + +echo [OK] 所有依赖检查通过！ + +:: ===================== 删除旧签名文件 ===================== +echo. +echo ---------------------------------------------------------- +echo 1/3 清理旧签名固件... +echo ---------------------------------------------------------- + +if exist "%SIGNED_BIN%" ( + echo [提示] 检测到旧文件：%SIGNED_BIN% + echo [处理] 正在删除旧文件... + del /f /q /a "%SIGNED_BIN%" >nul 2>&1 + + if exist "%SIGNED_BIN%" ( + echo [错误] 无法删除旧签名文件（可能被占用） + echo 请关闭相关程序后重试。 + pause + exit /b 1 + ) + echo [OK] 旧签名文件已删除 +) else ( + echo [OK] 无需清理 +) + +:: ===================== 固件签名 ===================== +echo. +echo ---------------------------------------------------------- +echo 2/3 正在为固件生成安全签名... +echo ---------------------------------------------------------- +echo [执行] %SIGN_TOOL% -bin "%ORIGIN_BIN%" -nk -of 0x80000000 -t fsbl -o "%SIGNED_BIN%" -hv 2.3 -dump "%SIGNED_BIN%" --align + +%SIGN_TOOL% -bin "%ORIGIN_BIN%" -nk -of 0x80000000 -t fsbl -o "%SIGNED_BIN%" -hv 2.3 -dump "%SIGNED_BIN%" --align + +if not exist "%SIGNED_BIN%" ( + echo [错误] 签名失败！未生成：%SIGNED_BIN% + pause + exit /b 1 +) + +echo [OK] 签名完成！输出文件：%SIGNED_BIN% + +:: ===================== 下载固件 ===================== +echo. +echo ---------------------------------------------------------- +echo 3/3 正在下载固件到 Flash 地址：%FLASH_ADDR% +echo ---------------------------------------------------------- +echo [执行] %FLASH_TOOL% -c port=SWD mode=HOTPLUG ap=1 -el "%N6570_ExternalLoader%" -hardRst -w "%SIGNED_BIN%" %FLASH_ADDR% + +%FLASH_TOOL% -c port=SWD mode=HOTPLUG ap=1 -el "%N6570_ExternalLoader%" -hardRst -w "%SIGNED_BIN%" %FLASH_ADDR% + +if %errorlevel% equ 0 ( + echo. + echo ========================================================== + echo ✔ 固件已成功烧录！ + echo ⚠ 请切换启动方式为：Boot0 = 0，Boot1 = 0（Flash 启动） + echo ========================================================== +) else ( + echo. + echo [错误] 烧录失败，请检查： + echo 1. SWD 连接是否正常 + echo 2. External Loader 路径是否正确 + echo 3. 芯片是否上电、BOOT 模式是否正确 +) + +echo. +pause +endlocal diff --git a/bsp/stm32/stm32n657-st-nucleo/program_app.bat b/bsp/stm32/stm32n657-st-nucleo/program_app.bat new file mode 100644 index 000000000000..ea9ee59f24ef --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/program_app.bat @@ -0,0 +1,77 @@ +@echo off +setlocal + +REM ============================================================ +REM APP Programming Script +REM %1 = Project path ($P) +REM ============================================================ + +set "PROJECT=%~1" + +if not defined PROJECT ( + echo ERROR: Project path is empty. + exit /b 1 +) + +if not exist "%PROJECT%\" ( + echo ERROR: Project directory not found: + echo %PROJECT% + exit /b 1 +) + +REM APP signed image directory +set "APP_BIN=%PROJECT%\rtthread-trusted.bin" +set "FLASH_ADDR=0x70100000" + +echo. +echo ========================================== +echo APP Programming +echo ========================================== +echo APP BIN : %APP_BIN% +echo Address : %FLASH_ADDR% +echo. + +REM ------------------------------------------------------------ +REM 1. Check signed APP image +REM ------------------------------------------------------------ +if not exist "%APP_BIN%" ( + echo ERROR: Signed APP image not found: + echo %APP_BIN% + exit /b 1 +) + +where STM32_Programmer_CLI.exe >nul 2>&1 +if errorlevel 1 ( + echo ERROR: STM32_Programmer_CLI.exe not found. + exit /b 1 +) + +if not defined N6570_ExternalLoader ( + echo ERROR: N6570_ExternalLoader is not defined. + exit /b 1 +) + +REM ------------------------------------------------------------ +REM 2. Program APP to external flash +REM ------------------------------------------------------------ +echo Programming APP... + +STM32_Programmer_CLI.exe ^ + -c port=SWD mode=HOTPLUG ap=1 ^ + -el "%N6570_ExternalLoader%" ^ + -hardRst ^ + -w "%APP_BIN%" %FLASH_ADDR% + +if errorlevel 1 ( + echo. + echo ERROR: APP programming failed. + exit /b 1 +) + +echo. +echo ========================================== +echo APP programming completed successfully. +echo ========================================== + +endlocal +exit /b 0 diff --git a/bsp/stm32/stm32n657-st-nucleo/project.ewp b/bsp/stm32/stm32n657-st-nucleo/project.ewp new file mode 100644 index 000000000000..5763fc842548 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/project.ewp @@ -0,0 +1,2348 @@ + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + Compiler + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\core\device.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + + + + Drivers + + $PROJ_DIR$\..\libraries\HAL_Drivers\drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32h7xx_hal_msp.c + + + $PROJ_DIR$\board\board.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\cpu_up.c + + + $PROJ_DIR$\..\..\..\src\defunct.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler_comm.c + + + $PROJ_DIR$\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + klibc + + $PROJ_DIR$\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + + + $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + libcpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + + POSIX + + + utestcases + + diff --git a/bsp/stm32/stm32n657-st-nucleo/project.eww b/bsp/stm32/stm32n657-st-nucleo/project.eww new file mode 100644 index 000000000000..c2cb02eb1e89 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/project.uvoptx b/bsp/stm32/stm32n657-st-nucleo/project.uvoptx new file mode 100644 index 000000000000..f030337a4c00 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/project.uvoptx @@ -0,0 +1,227 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template_APP_S + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + .\setup_app.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U004C00323234510333353533 -O710 -SF10000 -C0 -A1 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO1 -FD20000000 -FC1000 -FN0 -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Doc + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ../../README.md + README.md + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/project.uvprojx b/bsp/stm32/stm32n657-st-nucleo/project.uvprojx new file mode 100644 index 000000000000..71901cc243b6 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/project.uvprojx @@ -0,0 +1,1332 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + Template_APP_S + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + STM32N657X0HxQ + STMicroelectronics + Keil.STM32N6xx_DFP.1.2.0 + https://www.keil.com/pack/ + IRAM(0x30000000-0x3003FFFF) IROM(0x0C000000-0xC07DFFF) IROM2(0x0C07E000-0xC07FFFF) CLOCK(8000000) FPU3(DFPU) CPUTYPE("Cortex-M55") ELITTLE TZ DSP + + + + 0 + + + + + + + + + + + $$Device:STM32N657X0HxQ$CMSIS\SVD\STM32N657.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + rtthread + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf #L --bincombined --output=$L@L.bin + build_app.bat "#L" "$P" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "cmd.exe" (/c call "$P\program_app.bat" "$P") + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 2 + 0 + 0 + 0 + 1 + 8 + 0 + 0 + 0 + 1 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x40000 + + + 1 + 0xc000000 + 0x7e000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x70100400 + 0x1dfc00 + + + 1 + 0xc07e000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x34000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 6 + 3 + 1 + 1 + 0 + 0 + 0 + + -Wno-pointer-bool-conversion -Wno-tautological-compare + __STDC_LIMIT_MACROS, USE_HAL_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, STM32N657xx, RT_USING_ARMLIBC, __RTTHREAD__ + + .;applications;board;board\CubeMX_Config\Appli\Inc;board\CubeMX_Config\Secure_nsclib;packages\CMSIS-Core-latest\Include;packages\stm32n6_cmsis_driver-latest\Include;packages\stm32n6_hal_driver-latest\Inc;packages\stm32n6_hal_driver-latest\Inc\Legacy;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m85;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\net\utest;..\..\..\components\utilities\ulog;..\libraries\HAL_Drivers\drivers;..\libraries\HAL_Drivers\drivers\config;..\libraries\HAL_Drivers + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + ..\Templete_App_S + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + .\board\linker_scripts\link_app.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_gcc.S + 2 + ..\..\..\libcpu\arm\cortex-m85\context_gcc.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m85\cpuport.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_serial_v2.c + 1 + ..\..\..\components\drivers\serial\dev_serial_v2.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + drv_dma.c + 1 + ..\libraries\HAL_Drivers\drivers\drv_dma.c + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drivers\drv_gpio.c + + + + + drv_usart_v2.c + 1 + ..\libraries\HAL_Drivers\drivers\drv_usart_v2.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + secure_nsc.c + 1 + board\CubeMX_Config\Appli\Src\secure_nsc.c + + + + + stm32n6xx_hal_msp.c + 1 + board\CubeMX_Config\Appli\Src\stm32n6xx_hal_msp.c + + + + + board.c + 1 + board\board.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + STM32N6-CMSIS + + + system_stm32n6xx_s.c + 1 + packages\stm32n6_cmsis_driver-latest\Source\Templates\system_stm32n6xx_s.c + + + + + startup_stm32n657xx.s + 2 + packages\stm32n6_cmsis_driver-latest\Source\Templates\arm\startup_stm32n657xx.s + + + + + STM32N6-HAL + + + stm32n6xx_hal.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal.c + + + + + stm32n6xx_hal_cortex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_cortex.c + + + + + stm32n6xx_hal_crc.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_crc.c + + + + + stm32n6xx_hal_crc_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_crc_ex.c + + + + + stm32n6xx_hal_cryp.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_cryp.c + + + + + stm32n6xx_hal_cryp_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_cryp_ex.c + + + + + stm32n6xx_hal_dma.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_dma.c + + + + + stm32n6xx_hal_dma_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_dma_ex.c + + + + + stm32n6xx_hal_exti.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_exti.c + + + + + stm32n6xx_hal_gpio.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_gpio.c + + + + + stm32n6xx_hal_pwr.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_pwr.c + + + + + stm32n6xx_hal_pwr_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_pwr_ex.c + + + + + stm32n6xx_hal_rcc.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_rcc.c + + + + + stm32n6xx_hal_rcc_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_rcc_ex.c + + + + + stm32n6xx_hal_rif.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_rif.c + + + + + stm32n6xx_hal_rng.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_rng.c + + + + + stm32n6xx_hal_rng_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_rng_ex.c + + + + + stm32n6xx_hal_uart.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_uart.c + + + + + stm32n6xx_hal_uart_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_uart_ex.c + + + + + stm32n6xx_hal_usart.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_usart.c + + + + + stm32n6xx_hal_usart_ex.c + 1 + packages\stm32n6_hal_driver-latest\Src\stm32n6xx_hal_usart_ex.c + + + + + Utilities + + + ulog.c + 1 + ..\..\..\components\utilities\ulog\ulog.c + + + + + console_be.c + 1 + ..\..\..\components\utilities\ulog\backend\console_be.c + + + + + + + + + + + + + + + + + + + + + + template + 1 + + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/rtconfig.h b/bsp/stm32/stm32n657-st-nucleo/rtconfig.h new file mode 100644 index 000000000000..1ad852bc28cb --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/rtconfig.h @@ -0,0 +1,465 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_STM32N657 +#define BOARD_STM32N657X0_NUCLEO + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M85 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 128 + +/* log format */ + +#define ULOG_USING_COLOR +#define ULOG_OUTPUT_TIME +#define ULOG_TIME_USING_TIMESTAMP +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +/* end of log format */ +#define ULOG_BACKEND_USING_CONSOLE +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +#define PKG_USING_CMSIS_CORE +#define PKG_USING_CMSIS_CORE_LATEST_VERSION +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +#define PKG_USING_STM32N6_HAL_DRIVER +#define PKG_USING_STM32N6_HAL_DRIVER_LATEST_VERSION +#define PKG_USING_STM32N6_CMSIS_DRIVER +#define PKG_USING_STM32N6_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_STM32N657xx_FSBL +#define PKG_USING_STM32N657xx_FSBL_LATEST_VERSION +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32N6 +#define BOARD_SERIES_STM32_NUCLEO_144 + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_UART1_RX_BUFSIZE 256 +#define BSP_UART1_TX_BUFSIZE 0 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/stm32/stm32n657-st-nucleo/rtconfig.py b/bsp/stm32/stm32n657-st-nucleo/rtconfig.py new file mode 100644 index 000000000000..bf41af605c66 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/rtconfig.py @@ -0,0 +1,185 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m85' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH') and CROSS_TOOL == 'gcc': + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv8.1-m.main -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -mcmse -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + ' -DDEBUG -DUSE_HAL_DRIVER -DSTM32N657xx -DUSE_NUCLEO_64 -Wall -fstack-usage -mcmse -Wno-tautological-compare' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -DDEBUG ' + LFLAGS = DEVICE + ' -mcpu=cortex-m55 -Wl,--gc-sections,-Map=rtthread.map,-cref -T board/linker_scripts/link_app.ld' + ' -Wl,--gc-sections -static -Wl,--cmse-implib -Wl,--out-implib=./secure_nsclib.o -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -Wl,--end-group' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3 ' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +# GCC +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M55.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --gnu11 -Wno-pointer-bool-conversion -Wno-tautological-compare' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board/linker_scripts/link_app.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M55.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M55 ' + CFLAGS += ' -mcpu=cortex-M55 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -Wno-pointer-bool-conversion -Wno-tautological-compare' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board/linker_scripts/link_app.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu11' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M55' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M55' + AFLAGS += ' --fpu VFPv5_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32n657-st-nucleo/setup_app.ini b/bsp/stm32/stm32n657-st-nucleo/setup_app.ini new file mode 100644 index 000000000000..f080852fc4b3 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/setup_app.ini @@ -0,0 +1,7 @@ +LOAD .\fsbl\stm32n657xx_fsbl.axf INCREMENTAL +PC = _RDWORD(0x34180404); // Set Program Counter to Reset_Handler() address +G + +LOAD .\Objects\rtthread.axf CLEAR INCREMENTAL NOCODE +PC = _RDWORD(0x70100404); +G,main \ No newline at end of file diff --git a/bsp/stm32/stm32n657-st-nucleo/template.ewp b/bsp/stm32/stm32n657-st-nucleo/template.ewp new file mode 100644 index 000000000000..1ca2a5511bdc --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/template.eww b/bsp/stm32/stm32n657-st-nucleo/template.eww new file mode 100644 index 000000000000..bd036bb4c98c --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/template.uvoptx b/bsp/stm32/stm32n657-st-nucleo/template.uvoptx new file mode 100644 index 000000000000..f030337a4c00 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/template.uvoptx @@ -0,0 +1,227 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Template_APP_S + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + .\setup_app.ini + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)(6020=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U004C00323234510333353533 -O710 -SF10000 -C0 -A1 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO1 -FD20000000 -FC1000 -FN0 -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 -WK0-R0 + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Doc + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ../../README.md + README.md + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/stm32/stm32n657-st-nucleo/template.uvprojx b/bsp/stm32/stm32n657-st-nucleo/template.uvprojx new file mode 100644 index 000000000000..460be8588b46 --- /dev/null +++ b/bsp/stm32/stm32n657-st-nucleo/template.uvprojx @@ -0,0 +1,423 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Template_APP_S + 0x4 + ARM-ADS + 6210000::V6.21::ARMCLANG + 1 + + + STM32N657X0HxQ + STMicroelectronics + Keil.STM32N6xx_DFP.1.2.0 + https://www.keil.com/pack/ + IRAM(0x30000000-0x3003FFFF) IROM(0x0C000000-0xC07DFFF) IROM2(0x0C07E000-0xC07FFFF) CLOCK(8000000) FPU3(DFPU) CPUTYPE("Cortex-M55") ELITTLE TZ DSP + + + + 0 + + + + + + + + + + + $$Device:STM32N657X0HxQ$CMSIS\SVD\STM32N657.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + rtthread + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf #L --bincombined --output=$L@L.bin + build_app.bat "#L" "$P" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + + + + SARMV8M.DLL + -MPU -MVE + TCM.DLL + -pCM55 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "cmd.exe" (/c call "$P\program_app.bat" "$P") + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M55" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 2 + 0 + 0 + 0 + 1 + 8 + 0 + 0 + 0 + 1 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x30000000 + 0x40000 + + + 1 + 0xc000000 + 0x7e000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x70100400 + 0x1dfc00 + + + 1 + 0xc07e000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x34000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 6 + 3 + 1 + 1 + 0 + 0 + 0 + + -Wno-pointer-bool-conversion -Wno-tautological-compare + USE_HAL_DRIVER,STM32N657xx + + ../../FSBL/Inc;../../../../../../Drivers/BSP/STM32N6xx_Nucleo;../../../../../../Drivers/STM32N6xx_HAL_Driver/Inc;../../../../../../Drivers/CMSIS/Device/ST/STM32N6xx/Include;../../../../../../Drivers/STM32N6xx_HAL_Driver/Inc/Legacy;../../../../../../Drivers/CMSIS/Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + ..\Templete_App_S + + + + 0 + 0 + 0 + 0 + 1 + 0 + + + + .\board\linker_scripts\link_app.sct + + + --import-cmse-lib-out=".\Objects\rtthread_CMSE_Lib.o" + + + + + + + + Doc + + + README.md + 5 + ../../README.md + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git "a/bsp/stm32/stm32n657-st-nucleo/tools/STM32N6\345\233\272\344\273\266\347\203\247\345\275\225\345\267\245\345\205\267.exe" "b/bsp/stm32/stm32n657-st-nucleo/tools/STM32N6\345\233\272\344\273\266\347\203\247\345\275\225\345\267\245\345\205\267.exe" new file mode 100644 index 000000000000..33879425a18f Binary files /dev/null and "b/bsp/stm32/stm32n657-st-nucleo/tools/STM32N6\345\233\272\344\273\266\347\203\247\345\275\225\345\267\245\345\205\267.exe" differ diff --git a/tools/ci/bsp_detail.yml b/tools/ci/bsp_detail.yml index b60daf89bf77..38e0a38e98a3 100644 --- a/tools/ci/bsp_detail.yml +++ b/tools/ci/bsp_detail.yml @@ -2390,6 +2390,14 @@ stm32/stm32mp157a-st-ev1: mdk5: true menuconfig: true rtconfig.h: true +stm32/stm32n657-st-nucleo: + .config: true + README.md: true + gcc: arm-none-eabi-gcc + iar: true + mdk5: true + menuconfig: true + rtconfig.h: true stm32/stm32u575-st-nucleo: .config: true README.md: true diff --git a/tools/ci/toolchain_bsp.yml b/tools/ci/toolchain_bsp.yml index 656fabbcd560..09ab2214584e 100644 --- a/tools/ci/toolchain_bsp.yml +++ b/tools/ci/toolchain_bsp.yml @@ -301,6 +301,7 @@ arm-none-eabi-gcc: - stm32/stm32l552-st-nucleo - stm32/stm32mp157a-st-discovery - stm32/stm32mp157a-st-ev1 + - stm32/stm32n657-st-nucleo - stm32/stm32u575-st-nucleo - stm32/stm32u585-iot02a - stm32/stm32wb55-st-nucleo