diff --git a/CLAUDE.md b/CLAUDE.md index 1dd61169..227dbcf9 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -272,14 +272,15 @@ cJSON or prints diagnostics in those shared files must sit inside `tools/gen_*_padmux.py` and are in `.clang-format-hook-exclude`. Novatek's generator is the odd one: the NA51089 SDK has no pin table, only the driver's `pinmux_config_*()` code, so it compiles that code on the host with - every register write logged and runs it -- it needs a C compiler and the - SDK, and its `--selftest` needs only the compiler. + every register write logged and runs it -- once per die, NA51089, NA51055 + and NA51084 -- and it needs a C compiler and the SDK; its `--selftest` + needs only the compiler. `ipchw_padmux_by_func/_by_prefix/_by_pad` are safe to call concurrently once the SoC has been detected; detection itself is not, so call `getchipname()` once at startup. `ipchw_padmux_get/_set` touch `/dev/mem` and must stay on one thread. - `gpio get/set/scan` reach a GPIO controller per vendor: HiSilicon's bank words in `src/reginfo.c` (`get_chip_gpio_adress()`), SigmaStar Infinity6C's - per-pad registers in `src/hal/sstar_gpio.c`, and the NA51089's four + per-pad registers in `src/hal/sstar_gpio.c`, and the Novatek dies' four DATA/DIR/SET/CLR banks in `src/hal/novatek_gpio.c`. Ingenic has none, so only `gpio mux` and `reginfo --pads` work there. - `src/fake_symbols.c` holds empty definitions of HiSilicon SDK audio symbols, diff --git a/docs/gpio.md b/docs/gpio.md index 350a5e01..b916df9c 100644 --- a/docs/gpio.md +++ b/docs/gpio.md @@ -23,7 +23,8 @@ GPIO pad, decoded from the pad's own one-byte register into what it reads (`in`), what the SoC is driving (`out`) and whether it drives at all (`oe_n`, 1 meaning input/Hi-Z) — rather than the per-group data and direction words. -On Novatek (NT98562/NT98566) the pad is the kernel's GPIO number as well, and +On Novatek (NT98562/NT98566, NT9852x, NT98528/NT98529) the pad is the +kernel's GPIO number as well, and its name is accepted too: `gpio get P_GPIO22`, `gpio get 54` and `/sys/class/gpio/gpio54` are one wire (`P_GPIO(n)` is `0x20 + n`, and so on in steps of `0x20` through C, P, S, L, D, H, A and DSI). The `5_6` form is refused diff --git a/docs/padmux.md b/docs/padmux.md index bb3d9d8e..6c002988 100644 --- a/docs/padmux.md +++ b/docs/padmux.md @@ -287,13 +287,24 @@ peripheral becomes an input. ### Novatek -- a field per peripheral, and a gate per pad -NA51089 (NT98562, NT98566) is SigmaStar's arrangement with a second lock on -it. In the TOP block at `0xF0010000` each peripheral has a location field -- +NA51089 (NT98562, NT98566), NA51055 (NT9852x) and NA51084 (NT98528, +NT98529) are SigmaStar's arrangement with a second lock on it. In the TOP block at `0xF0010000` each peripheral has a location field -- `REG5[7:6]` is I2C3, and 1, 2 and 3 put it on `P_GPIO21/22`, `C_GPIO11/12` or `DSI_GPIO8/9` -- and each pad has a **gate bit** in one of eight bitmaps at `TOP + 0xA0..0xE8`, where 1 keeps the pad a GPIO whatever any field says. The vendor's `pinmux_config_*()` sets both, every time: the field, then -`GPIO_ID_EMUM_FUNC` into the gate of each pad it uses. +`GPIO_ID_EMUM_FUNC` into the gate of each pad it uses. NA51055 and NA51084 +have the same TOP layout without the DSI group, and more S, L and D pads. + +Which die it is comes from the TOP chip-ID word (`/proc/nvt_info/nvt_pinmux/ +chip_id`), and it names the die rather than the part. NT98562 and NT98566 are +both `0x7021` and differ in an eFuse package word whose decoding the SDK +ships as a binary, so both report as NT98566; `0x5021` is NA51084, which +u-boot's clock code shows to be the NT98528/NT98529 die (the 529 told apart +by OTP), and reports as NT98528. `0x4821` (NA51055, under which the SDK +mentions both NT98520 and NT98525) and `0xBC21` (NA51090, NT98636) take their +name from the device tree, as before; NA51103 (`0x8B20`) is NT98332G. The +last two have no table: see below. So a pad's alternatives are **claims**: a name and the field values under which the pad carries it. `get()` takes the first claim that holds, with the @@ -316,10 +327,17 @@ the gate. Consequences: PHY's management pin, clears `ETH` and so ends RMII. - **The parallel and CCIR sensor modes ignore the gate.** They put pixel data on the HSI pads while the vendor writes those gates to GPIO, so those claims - hold through it (`NVT_UNGATED` in the table). `gpio mux H_GPIO4 GPIO` on such + hold through it (`NVT_UNGATED` in the table), and `set()` writes the gate to + GPIO for them as the vendor does -- otherwise a gated claim under the same + fields would win, CCIR8 sync over CCIR8 data on NA51055's `P_GPIO9`. `gpio mux H_GPIO4 GPIO` on such a board has to zero `SENSOR` to mean anything, and does -- the whole parallel bus goes with it. The MIPI lanes on the same pads are the opposite: the gate cleared and no field at all. +- **The primary LCD** is muxed by `pinmux_select_primary_lcd()`, which the + display driver reaches through `pinmux_set_host()`: `REG2` `LCD_TYPE` and + the L and DSI gates. Its claims are named by type -- `LCD_PARALLE_RGB565` + on the colour pins, `LCD_DE_ENABLE` on the DE pin. TV and HDMI have no pads + to mux on these parts; `pinmux_set_host()` answers `E_ID` for both. - Pads are the kernel's GPIO numbers and names: `C_GPIO(n)` is `n`, `P_GPIO(n)` is `0x20 + n`, and so on through S, L, D, H, A and DSI. `gpio` takes the number or the name (`P_GPIO22`, and the vendor's `MC17` and @@ -391,29 +409,44 @@ tools/gen_novatek_padmux.py --sdk /path/to/na51089_linux_sdk \ There is no datasheet and no pin list in the NA51089 SDK, and `na51089_pinmux_host.c` is 2200 lines of nested `if`/`else if`/`switch` with the conflict checks interleaved. So the generator **runs** it: it cuts the -`pinmux_config_*()` functions out, wraps every `top_regN.bit.FIELD = value` -in a macro that logs the write, compiles that on the host against the SDK's -own `top_reg.h`/`top.h`, and calls every function with every combination of -up to four of its options (96,550 calls, about half a minute). A combination the -vendor refuses is retried after one option of another group, which is the -only way MIPI data lanes 1-3 appear at all: `pinmux_config_mipi_lvds()` -refuses them until the sensor group is in CSI mode. - -The source is read for one thing: which braces enclose each write. A gate +`pinmux_config_*()` functions and `pinmux_select_primary_lcd()` out, wraps +every `top_regN.bit.FIELD = value` in a macro that logs the write, compiles +that on the host against the SDK's own `top_reg.h`/`top.h`, and calls every +function with every combination of up to four of its options -- the LCD as +each type with every set of feature flags. A combination the vendor refuses +is retried after one option of another group, which is the only way MIPI data +lanes 1-3 appear at all: `pinmux_config_mipi_lvds()` refuses them until the +sensor group is in CSI mode. + +The same SDK carries the NA51055 driver, which serves NA51055 and NA51084 and +branches on `nvt_get_chip_id()` -- NA51084 alone has I2C4/5, SPI4/5 and an +RGMII. The harness answers that call with a constant, so the driver is run +once as each die and each gets its own table: about 260,000 calls for the +three, a minute and a half. + +The source is read for one thing: which braces enclose each write, and which +options the `& PIN_...` test or `case` opening each brace names. A gate write's conditions are the field writes the same call made in the blocks around it -- `SEN_MCLK=1` for `S_GPIO0`, not the sensor mode a sibling block -of the same call selected. Every state the vendor code produced is then +of the same call selected. A field an enclosing block wrote and a nested +block overwrote before the gate write takes the nested value: +`pinmux_select_primary_lcd()` resets `LCD_TYPE` at its top and sets it per +type in a `switch` before handing the pads over. Every state the vendor code produced is then replayed against the table, and three answers are acceptable: the pad reads as what the code meant; it reads as nothing because a later write of the same call moved its field away; or two claims hold, and the table carries a more specific claim for the one the code meant. Anything else is fatal. -`top.h` and `top.csv` disagree with the code in three places, and -`ANNOTATION_ERRATA` in the generator says which side wins and why: the csv's +`top.h` and `top.csv` disagree with the code, and `ANNOTATION_ERRATA` in the +generator says, per driver, which side wins and why. On NA51089: the csv's `P_GPIO29` for SIF CH2_2 (no such pad, the code uses `P_GPIO19`), `top.h`'s `P_GPIO14` for PICNT2_1 (the code and the csv use `L_GPIO1`), and `PIN_MISC_CFG_SP2CLK_3RD`, which does nothing at all, because -`pinmux_config_misc()` tests `PIN_SENSOR_CFG_SP2CLK_3RD` in its place. +`pinmux_config_misc()` tests `PIN_SENSOR_CFG_SP2CLK_3RD` in its place. On +NA51055 the MISC annotations are NA51089's, copied, and name pads its code +does not use; PWM8..11's HSI location is commented out of the driver ("52x +compatible - donot support this function"); and `P_GPIO14` for PICNT2_1 is +right there, which is why the errata are per driver. Both generators take `--verify
`, which re-derives and diffs instead of writing. That needs the SDK, so CI cannot run it; @@ -472,21 +505,27 @@ in. - **Other Ingenic parts.** T21, T23, T31 and T40 have tables. T10, T20, T30 and T41 do not, and would each need a source of one of the three kinds above -- which, for the parts checked so far, does not exist in the vendor releases. -- **Other Novatek parts, and NA51089's display.** NA51055, NA51084, NA51090 - and NA51103 have no table: their chip IDs are recognised and get none. - LCD, TV and HDMI on NA51089 are muxed by `pinmux_select_primary_lcd()` - from state the config functions only stash, and are not modelled; a pad - given to the display reads as cleared with nothing claiming it. -- **Novatek states two options create at once.** In 19,185 of the replayed - calls some pad is claimed twice -- a 12-bit sensor's pixel clock and MCLK2 - both on `S_GPIO1`, say. The vendor code checks for neither and no board - does it. The table answers by the vendor's last write, which is the best - evidence there is and not a measurement. +- **NA51090 (NT98636) and NA51103 (NT98332G).** Recognised, no table. Neither + driver is in the NA51089 SDK nor anywhere public that was found; u-boot + carries NA51090's sensor pinmux and nothing else, and its registers sit at + `0x2F0000000`, past what a 32-bit `mem_reg()` reaches. NA51068 (NT98321, + an NVR part) is in the SDK and is a per-pad selector like HiSilicon's, + which this backend is not; it has no chip ID in this tree and gets no + table. +- **NT98562 against NT98566, NT98528 against NT98529.** One die each, told + apart by eFuse or OTP words the SDK decodes only in binaries. The pad + tables are per die, so they are not affected; only the reported name is. +- **Novatek states two options create at once.** In about a fifth of the + replayed calls some pad is claimed twice -- a 12-bit sensor's pixel clock + and MCLK2 both on `S_GPIO1`, say. The vendor code checks for neither and no + board does it. The table answers by the vendor's last write, which is the + best evidence there is and not a measurement; each table's banner in the + header gives the counts. - **Hardware.** Every claim here is verified against vendor source and on a host. On top of that, HiSilicon, SigmaStar infinity6/6b0/6c, and Ingenic T21, T23, T31 and SigmaStar infinity6e have been run on real cameras and checked against an independent decode of their live registers. Ingenic T40 - and Novatek NA51089 have not: nobody here has had one. On a NA51089, + and the Novatek dies have not: nobody here has had one. On a Novatek part, `/proc/nvt_info/nvt_pinmux/pinmux_summary` is the kernel's own decode of the same registers and is the thing to compare `reginfo --pads` against. diff --git a/src/hal/novatek.c b/src/hal/novatek.c index 840ebf2d..0c99c221 100644 --- a/src/hal/novatek.c +++ b/src/hal/novatek.c @@ -23,39 +23,40 @@ static sensor_addr_t novatek_possible_i2c_addrs[] = { {0, NULL}}; static bool nvt_get_chip_id() { - uint16_t reg; - unsigned int chip_id = 0; char buf[8]; - char *endptr; - if (line_from_file("/proc/nvt_info/nvt_pinmux/chip_id", "(.+)", buf, - sizeof(buf))) { + if (!line_from_file("/proc/nvt_info/nvt_pinmux/chip_id", "(.+)", buf, + sizeof(buf))) + return false; - reg = (uint16_t)strtol(buf, &endptr, 16); - /* The TOP block's chip-ID word, which is what tells the pad-mux - * table and the GPIO controller which SoC this is. Set for every ID - * the kernel hands over, named or not: a part with no table gets no - * table, which padmux_ops() says rather than guessing one. */ - chip_generation = reg; - switch (reg) { - case 0x5021: - strcpy(chip_name, "NT98562"); - return true; - case 0x7021: - strcpy(chip_name, "NT98566"); - return true; - case 0x8B20: - strcpy(chip_name, "NT98332G"); - return true; - } + /* The TOP block's chip-ID word, which is what tells the pad-mux table and + * the GPIO controller which SoC this is. Set for every ID the kernel hands + * over, named or not: a part with no table gets no table, which + * padmux_ops() says rather than guessing one. */ + chip_generation = (uint16_t)strtol(buf, NULL, 16); + + /* The ID names the die, not the part: NT98562 and NT98566 are both + * NA51089 and differ only in an eFuse package word whose decoding is not + * in the SDK, so the two read alike here. The dies with no name below + * (NA51055, NA51090) are named by the device tree. */ + const char *name; + switch (chip_generation) { + case CHIP_NA51084: + /* u-boot's NA51084 code drives the "_528_" clock registers and allows + * 1200 MHz only on an NT98529, told apart by OTP. */ + name = "NT98528"; + break; + case CHIP_NA51089: + name = "NT98566"; + break; + case CHIP_NA51103: + name = "NT98332G"; + break; + default: + return false; } - - // if (mem_reg(IOADDR_TOP_REG_BASE + TOP_VERSION_REG_OFS, (uint32_t *)®, - // OP_READ)) { - // chip_id = (reg >> 16) & 0xFFFF; - // } - // printf("reg %x\n", chip_id); - return false; + strcpy(chip_name, name); + return true; } bool novatek_detect_cpu(char *chip_name) { @@ -65,8 +66,13 @@ bool novatek_detect_cpu(char *chip_name) { return true; if (!line_from_file("/proc/device-tree/model", "Novatek ([A-Z]+[0-9]+)", - buf, sizeof(buf))) - return false; + buf, sizeof(buf))) { + /* NA51055 has a pad table and no part name the ID can give; with + * no device-tree model either, the die is the name. */ + if (chip_generation != CHIP_NA51055) + return false; + strcpy(buf, "NA51055"); + } strcpy(chip_name, buf); @@ -100,8 +106,10 @@ float novatek_get_temp() { static int novatek_open_i2c_fd(int i2c_adapter_nr) { if (i2c_adapter_nr<0 || i2c_adapter_nr>4) i2c_adapter_nr=0; - if (!strncmp(chip_name, "NA51068", 7) || - !strncmp(chip_name, "NA51103", 7) || !strncmp(chip_name, "NA51090", 7)) + /* NA51103 by its ID: the ID path names it NT98332G, which a name test + * for "NA51103" never matched. */ + if (chip_generation == CHIP_NA51103 || !strncmp(chip_name, "NA51068", 7) || + !strncmp(chip_name, "NA51090", 7)) i2c_adapter_nr = 1; char adapter_name[FILENAME_MAX]; diff --git a/src/hal/novatek.h b/src/hal/novatek.h index 25888e69..e23d1c0c 100644 --- a/src/hal/novatek.h +++ b/src/hal/novatek.h @@ -19,14 +19,15 @@ void novatek_setup_hal(); /* na51068 */ //#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE + 0x0E030000) +/* TOP + 0xF0 bits [31:16], also /proc/nvt_info/nvt_pinmux/chip_id. One ID + * per die; the parts cut from a die are told apart by eFuse/OTP words. */ enum CHIP_ID { - CHIP_NA51055 = 0x4821, // NT98525, 128Kb L2, 5M@30 - // NT98528, 256Kb L2, 4K@30 - CHIP_NA51084 = 0x5021, - CHIP_NA51089 = 0x7021, // NT98562, 64Mb internal RAM - // NT98566, 128Mb internal RAM - CHIP_NA51090 = 0xBC21, - CHIP_NA51103 = 0x8B20 // NVT98332G + CHIP_NA51055 = 0x4821, // NT9852x: NT98520, NT98525 + CHIP_NA51084 = 0x5021, // NT98528, NT98529 (the 1.2 GHz part, by OTP) + CHIP_NA51089 = 0x7021, // NT98562 (64 MB internal RAM), + // NT98566 (128 MB), by eFuse package word + CHIP_NA51090 = 0xBC21, // NT98636 + CHIP_NA51103 = 0x8B20 // NT98332G }; #endif /* HAL_NOVATEK_H */ diff --git a/src/hal/novatek_gpio.c b/src/hal/novatek_gpio.c index 97faba37..ad333539 100644 --- a/src/hal/novatek_gpio.c +++ b/src/hal/novatek_gpio.c @@ -1,4 +1,6 @@ -/* The NA51089 GPIO controller, as the vendor's gpio-nvt-na51089.c drives it. +/* The NA51089, NA51055 and NA51084 GPIO controller, as the vendor's + * gpio-nvt-na51089.c and gpio-nvt-na51055.c drive it: the same block at the + * same address on all three. * * Four banks of eight words at 0xF0070000: DATA, DIR, SET and CLR, one word * per pad group, so a pad's bit is its Linux GPIO number modulo 32 in word @@ -16,23 +18,30 @@ #include "hal/novatek.h" #include "tools.h" -static const uint8_t group_pads[8] = { - 23, /* C_GPIO, the "MC" pads */ - 26, /* P_GPIO */ - 9, /* S_GPIO */ - 10, /* L_GPIO */ - 8, /* D_GPIO */ - 12, /* H_GPIO, the HSI pads */ - 3, /* A_GPIO */ - 11, /* DSI_GPIO */ -}; +/* C ("MC"), P, S, L, D, H (HSI), A, DSI. */ +static const uint8_t na51089_pads[8] = {23, 26, 9, 10, 8, 12, 3, 11}; +/* NA51055 and NA51084: more S, L and D pads, and no DSI group. */ +static const uint8_t na51055_pads[8] = {23, 26, 13, 25, 11, 12, 3, 0}; -bool novatek_gpio_supported(void) { return chip_generation == CHIP_NA51089; } +static const uint8_t *group_pads(void) { + switch (chip_generation) { + case CHIP_NA51089: + return na51089_pads; + case CHIP_NA51055: + case CHIP_NA51084: + return na51055_pads; + default: + return NULL; + } +} + +bool novatek_gpio_supported(void) { return group_pads() != NULL; } bool novatek_gpio_valid(int pad) { - if (!novatek_gpio_supported() || pad < 0 || pad >= NVT_GPIO_NPADS) + const uint8_t *pads = group_pads(); + if (pads == NULL || pad < 0 || pad >= NVT_GPIO_NPADS) return false; - return (pad & 31) < group_pads[pad >> 5]; + return (pad & 31) < pads[pad >> 5]; } uint32_t novatek_gpio_reg(int pad, unsigned bank) { diff --git a/src/hal/novatek_padmux.c b/src/hal/novatek_padmux.c index e68af4c7..82cc24ce 100644 --- a/src/hal/novatek_padmux.c +++ b/src/hal/novatek_padmux.c @@ -1,4 +1,6 @@ -/* Novatek NA51089 (NT98562/NT98566): the pad-mux backend. +/* Novatek NA51089 (NT98562/NT98566), NA51055 (NT9852x) and NA51084 + * (NT98528/NT98529): the pad-mux backend. The three share the TOP block + * layout below; NA51055 and NA51084 have no DSI pad group. * * Two things decide what a pad carries, and they are in different places: * @@ -63,6 +65,10 @@ typedef struct { static const novatek_soc_t *nvt_soc(void) { switch (chip_generation) { + case CHIP_NA51055: + return &NA51055_padmux; + case CHIP_NA51084: + return &NA51084_padmux; case CHIP_NA51089: return &NA51089_padmux; default: @@ -420,8 +426,13 @@ static int nvt_set(int pad, const char *func_name, const padmux_io_t *io) { (uint32_t)k->value << k->shift)) return top_undo(&t, IPCHW_PADMUX_IO); } - if (!(best->flags & NVT_UNGATED) && - !top_write_field(&t, gr, gate_bit(pad), 0)) + /* A gated claim needs the gate handed over. An ungated one is what the + * vendor sets the gate to GPIO for -- the parallel sensor modes write + * GPIO_ID_EMUM_GPIO to their data pads -- and leaving it clear would let + * a gated claim under the same fields win: CCIR8 data and CCIR8 sync + * both hold under SENSOR2=2. */ + uint32_t gate = (best->flags & NVT_UNGATED) ? gate_bit(pad) : 0; + if (!top_write_field(&t, gr, gate_bit(pad), gate)) return top_undo(&t, IPCHW_PADMUX_IO); int res = drop_competitors(soc, pad, &t, best); diff --git a/src/hal/novatek_padmux.h b/src/hal/novatek_padmux.h index ad20949e..7ca791a7 100644 --- a/src/hal/novatek_padmux.h +++ b/src/hal/novatek_padmux.h @@ -1,11 +1,9 @@ /* Generated by tools/gen_novatek_padmux.py -- do not edit. * - * What the vendor's pinmux_config_*() functions do to each pad of the - * NA51089, found by running them: see the generator for how, and - * src/hal/novatek_padmux.c for how the table is read. 96550 vendor states - * were replayed against it; in 19185 of them two claims hold at once and the - * table carries the one the vendor code meant, and 478 leave a pad cleared - * with its field moved elsewhere, which reads as unnamed. + * What the vendor's pinmux_config_*() and pinmux_select_primary_lcd() do to + * each pad, found by running them: see the generator for how, and + * src/hal/novatek_padmux.c for how the tables are read. One table per die; + * NA51055 and NA51084 come from one driver run as each. * * Regenerate with: * tools/gen_novatek_padmux.py --sdk @@ -16,6 +14,11 @@ #include "hal/novatek_padmux_types.h" +/* NA51089: 96902 vendor states replayed; in 19185 of them two claims hold + * at once and the table carries the one the vendor code meant, + * and 486 leave a pad cleared with its field moved elsewhere, + * which reads as unnamed. */ + /* Every pad the package bonds out, by Linux GPIO number. */ static const novatek_pad_t NA51089_pads[] = { {0, PMX_C_GPIO0}, @@ -176,12 +179,12 @@ static const novatek_cond_t NA51089_conds[] = { {0x18, 25, 3, 2}, {0x14, 30, 2, 2}, {0x1C, 0, 3, 1}, - {0x0C, 4, 2, 1}, - {0x0C, 4, 2, 2}, - {0x0C, 0, 3, 2}, {0x0C, 0, 3, 4}, {0x14, 10, 2, 2}, {0x24, 2, 2, 3}, + {0x0C, 4, 2, 1}, + {0x0C, 4, 2, 2}, + {0x0C, 0, 3, 2}, {0x1C, 3, 3, 1}, {0x24, 2, 2, 3}, {0x24, 8, 2, 1}, @@ -282,7 +285,52 @@ static const novatek_cond_t NA51089_conds[] = { {0x1C, 18, 3, 3}, {0x1C, 21, 3, 3}, {0x0C, 12, 2, 2}, + {0x08, 0, 4, 0}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, {0x18, 25, 3, 5}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, {0x1C, 28, 2, 1}, {0x0C, 18, 2, 2}, {0x18, 13, 2, 1}, @@ -306,15 +354,22 @@ static const novatek_cond_t NA51089_conds[] = { {0x0C, 0, 3, 4}, {0x0C, 6, 2, 1}, {0x0C, 8, 2, 2}, - {0x0C, 0, 3, 1}, - {0x0C, 8, 2, 2}, {0x0C, 0, 3, 3}, {0x0C, 8, 2, 2}, {0x0C, 8, 2, 2}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, {0x14, 2, 2, 1}, {0x1C, 0, 3, 5}, {0x24, 4, 3, 1}, {0x1C, 3, 3, 5}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, {0x24, 4, 3, 1}, {0x24, 10, 2, 1}, {0x24, 4, 3, 1}, @@ -338,6 +393,10 @@ static const novatek_cond_t NA51089_conds[] = { {0x14, 2, 2, 1}, {0x14, 30, 2, 1}, {0x18, 19, 3, 5}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 10, 1, 1}, {0x18, 28, 1, 1}, {0x18, 22, 3, 5}, }; @@ -426,108 +485,108 @@ static const novatek_claim_t NA51089_claims[] = { {22, 0, PMX_UART3_2_RX, 48, 1}, /* C_GPIO22 */ {32, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO0 */ {32, 0, PMX_PWM0_1, 51, 1}, /* P_GPIO0 */ - {32, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO0 */ - {32, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO0 */ - {32, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO0 */ - {32, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO0 */ - {32, 0, PMX_SPI2_2_CS, 56, 1}, /* P_GPIO0 */ - {32, 0, PMX_UART2_3_TX, 57, 1}, /* P_GPIO0 */ + {32, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO0 */ + {32, 0, PMX_SPI2_2_CS, 53, 1}, /* P_GPIO0 */ + {32, 0, PMX_UART2_3_TX, 54, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO0 */ {33, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO1 */ {33, 0, PMX_PWM1_1, 58, 1}, /* P_GPIO1 */ - {33, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO1 */ - {33, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO1 */ - {33, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO1 */ - {33, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO1 */ - {33, 0, PMX_SPI2_2_CLK, 56, 1}, /* P_GPIO1 */ - {33, 0, PMX_UART2_3_RX, 57, 1}, /* P_GPIO1 */ + {33, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO1 */ + {33, 0, PMX_SPI2_2_CLK, 53, 1}, /* P_GPIO1 */ + {33, 0, PMX_UART2_3_RX, 54, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO1 */ {34, 0, PMX_UART2_3_RTS, 59, 2}, /* P_GPIO2 */ {34, 0, PMX_UART2_3_RTS, 61, 2}, /* P_GPIO2 */ {34, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO2 */ {34, 0, PMX_PWM2_1, 63, 1}, /* P_GPIO2 */ - {34, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO2 */ - {34, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO2 */ - {34, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO2 */ - {34, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO2 */ - {34, 0, PMX_SPI2_2_DO, 56, 1}, /* P_GPIO2 */ + {34, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO2 */ + {34, 0, PMX_SPI2_2_DO, 53, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO2 */ {35, 0, PMX_SPI2_2_DI, 64, 2}, /* P_GPIO3 */ {35, 0, PMX_UART2_3_CTS, 59, 2}, /* P_GPIO3 */ {35, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO3 */ {35, 0, PMX_PWM3_1, 66, 1}, /* P_GPIO3 */ - {35, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO3 */ - {35, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO3 */ - {35, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO3 */ - {35, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO3 */ + {35, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO3 */ {36, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO4 */ {36, 0, PMX_PWM4_1, 67, 1}, /* P_GPIO4 */ - {36, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO4 */ - {36, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO4 */ - {36, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO4 */ - {36, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO4 */ + {36, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO4 */ {36, 0, PMX_SPI3_3_CS, 68, 1}, /* P_GPIO4 */ {36, 0, PMX_UART3_3_TX, 69, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO4 */ {37, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO5 */ {37, 0, PMX_PWM5_1, 70, 1}, /* P_GPIO5 */ - {37, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO5 */ - {37, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO5 */ - {37, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO5 */ - {37, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO5 */ + {37, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO5 */ {37, 0, PMX_SPI3_3_CLK, 68, 1}, /* P_GPIO5 */ {37, 0, PMX_UART3_3_RX, 69, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO5 */ {38, 0, PMX_UART3_3_RTS, 71, 2}, /* P_GPIO6 */ {38, 0, PMX_UART3_3_RTS, 73, 2}, /* P_GPIO6 */ {38, 0, PMX_PWM6_1, 75, 1}, /* P_GPIO6 */ - {38, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO6 */ - {38, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO6 */ - {38, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO6 */ - {38, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO6 */ + {38, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO6 */ {38, 0, PMX_SPI3_3_DO, 68, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO6 */ {39, 0, PMX_ETH_EXTPHYCLK, 76, 2}, /* P_GPIO7 */ {39, 0, PMX_SPI3_3_DI, 78, 2}, /* P_GPIO7 */ {39, 0, PMX_UART3_3_CTS, 71, 2}, /* P_GPIO7 */ {39, 0, PMX_PWM7_1, 80, 1}, /* P_GPIO7 */ {39, 0, PMX_SB4_CS, 81, 1}, /* P_GPIO7 */ - {39, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO7 */ - {39, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO7 */ - {39, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO7 */ - {39, 0, PMX_SENSOR_CCIR16BITS, 55, 1}, /* P_GPIO7 */ + {39, 0, PMX_SENSOR_CCIR16BITS, 52, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO7 */ {40, 0, PMX_SPI_CH3_RDY, 82, 2}, /* P_GPIO8 */ {40, 0, PMX_ETH_RMII_2, 50, 1}, /* P_GPIO8 */ {40, 0, PMX_I2S_MCLK_1, 84, 1}, /* P_GPIO8 */ {40, 0, PMX_PWM8_1, 85, 1}, /* P_GPIO8 */ {40, 0, PMX_SB4_CK, 81, 1}, /* P_GPIO8 */ - {40, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO8 */ - {40, 0, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO8 */ - {40, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO8 */ + {40, 0, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO8 */ {41, 0, PMX_ETH_MDIO_2, 86, 2}, /* P_GPIO9 */ {41, 0, PMX_ETH_MDIO_2, 88, 1}, /* P_GPIO9 */ {41, 0, PMX_I2S_BCLK_1, 89, 1}, /* P_GPIO9 */ {41, 0, PMX_PWM9_1, 90, 1}, /* P_GPIO9 */ {41, 0, PMX_SB4_DAT, 81, 1}, /* P_GPIO9 */ - {41, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO9 */ - {41, 0, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO9 */ - {41, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO9 */ + {41, 0, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO9 */ {42, 0, PMX_ETH_MDIO_2, 86, 2}, /* P_GPIO10 */ {42, 0, PMX_ETH_MDIO_2, 88, 1}, /* P_GPIO10 */ {42, 0, PMX_I2S_SYNC_1, 89, 1}, /* P_GPIO10 */ {42, 0, PMX_PWM10_1, 91, 1}, /* P_GPIO10 */ {42, 0, PMX_SB3_1_CS, 92, 1}, /* P_GPIO10 */ - {42, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO10 */ - {42, 0, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO10 */ - {42, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO10 */ + {42, 0, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO10 */ {43, 0, PMX_I2S_SDATAO_1, 89, 1}, /* P_GPIO11 */ {43, 0, PMX_PWM11_1, 93, 1}, /* P_GPIO11 */ {43, 0, PMX_SB3_1_CK, 92, 1}, /* P_GPIO11 */ - {43, NVT_UNGATED, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO11 */ - {43, 0, PMX_SENSOR2_CCIR8BITS, 53, 1}, /* P_GPIO11 */ - {43, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO11 */ + {43, 0, PMX_SENSOR2_CCIR8BITS, 56, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO11 */ {44, 0, PMX_SENSOR2_SN3_MCLK, 94, 2}, /* P_GPIO12 */ {44, 0, PMX_SPI_CH3_RDY, 96, 2}, /* P_GPIO12 */ {44, 0, PMX_I2S_SDATAI_1, 89, 1}, /* P_GPIO12 */ {44, 0, PMX_PICNT_1, 98, 1}, /* P_GPIO12 */ {44, 0, PMX_SB3_1_DAT, 92, 1}, /* P_GPIO12 */ - {44, 0, PMX_SENSOR2_12BITS, 52, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR2_12BITS, 55, 1}, /* P_GPIO12 */ {44, 0, PMX_SENSOR2_SN3_MCLK, 99, 1}, /* P_GPIO12 */ - {44, 0, PMX_SENSOR_12BITS_2ND, 54, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR_12BITS_2ND, 57, 1}, /* P_GPIO12 */ {49, 0, PMX_DMDAT0_1, 100, 3}, /* P_GPIO17 */ {49, 0, PMX_PICNT3_1, 103, 1}, /* P_GPIO17 */ {49, 0, PMX_REMOTE_IN_1, 104, 1}, /* P_GPIO17 */ @@ -573,7 +632,7 @@ static const novatek_claim_t NA51089_claims[] = { {66, 0, PMX_PWM1_3, 140, 1}, /* S_GPIO2 */ {66, 0, PMX_SDIO2_D0, 124, 1}, /* S_GPIO2 */ {66, 0, PMX_SENSOR_12BITS, 137, 1}, /* S_GPIO2 */ - {66, 0, PMX_SENSOR_12BITS_2ND, 54, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_12BITS_2ND, 57, 1}, /* S_GPIO2 */ {66, 0, PMX_SENSOR_CCIR8BITS, 138, 1}, /* S_GPIO2 */ {66, 0, PMX_SENSOR_LVDS_VDHD, 141, 1}, /* S_GPIO2 */ {67, 0, PMX_SENSOR_CCIR16BITS, 130, 2}, /* S_GPIO3 */ @@ -581,20 +640,20 @@ static const novatek_claim_t NA51089_claims[] = { {67, 0, PMX_SB2_CS, 143, 1}, /* S_GPIO3 */ {67, 0, PMX_SDIO2_D1, 124, 1}, /* S_GPIO3 */ {67, 0, PMX_SENSOR_12BITS, 137, 1}, /* S_GPIO3 */ - {67, 0, PMX_SENSOR_12BITS_2ND, 54, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_12BITS_2ND, 57, 1}, /* S_GPIO3 */ {67, 0, PMX_SENSOR_CCIR8BITS, 138, 1}, /* S_GPIO3 */ {67, 0, PMX_SENSOR_LVDS_VDHD, 141, 1}, /* S_GPIO3 */ {68, 0, PMX_I2C2_1_SCL, 144, 1}, /* S_GPIO4 */ {68, 0, PMX_PWM3_3, 145, 1}, /* S_GPIO4 */ {68, 0, PMX_SB2_CK, 143, 1}, /* S_GPIO4 */ - {68, 0, PMX_SENSOR2_12BITS, 52, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR2_12BITS, 55, 1}, /* S_GPIO4 */ {68, 0, PMX_SENSOR2_LVDS_VDHD, 146, 1}, /* S_GPIO4 */ {68, 0, PMX_UART3_5_TX, 147, 1}, /* S_GPIO4 */ {69, 0, PMX_SPI_2_DI, 148, 2}, /* S_GPIO5 */ {69, 0, PMX_I2C2_1_SDA, 144, 1}, /* S_GPIO5 */ {69, 0, PMX_PWM4_3, 150, 1}, /* S_GPIO5 */ {69, 0, PMX_SB2_DAT, 143, 1}, /* S_GPIO5 */ - {69, 0, PMX_SENSOR2_12BITS, 52, 1}, /* S_GPIO5 */ + {69, 0, PMX_SENSOR2_12BITS, 55, 1}, /* S_GPIO5 */ {69, 0, PMX_SENSOR2_LVDS_VDHD, 146, 1}, /* S_GPIO5 */ {69, 0, PMX_UART3_5_RX, 147, 1}, /* S_GPIO5 */ {70, 0, PMX_PWM5_3, 151, 1}, /* S_GPIO6 */ @@ -613,127 +672,375 @@ static const novatek_claim_t NA51089_claims[] = { {72, 0, PMX_SDIO2_D3, 124, 1}, /* S_GPIO8 */ {72, 0, PMX_SENSOR2_MCLK_2ND, 157, 1}, /* S_GPIO8 */ {72, 0, PMX_SPI_2_DO, 153, 1}, /* S_GPIO8 */ - {96, 0, PMX_PWM11_5, 158, 1}, /* L_GPIO0 */ - {97, 0, PMX_PICNT2_1, 159, 1}, /* L_GPIO1 */ - {98, 0, PMX_SP_CLK_2, 160, 1}, /* L_GPIO2 */ - {128, 0, PMX_ETH_LED1, 161, 1}, /* D_GPIO0 */ - {129, 0, PMX_ETH_LED1, 161, 1}, /* D_GPIO1 */ - {131, 0, PMX_PWM4_4, 162, 1}, /* D_GPIO3 */ - {131, 0, PMX_SB3_3_CS, 163, 1}, /* D_GPIO3 */ - {131, 0, PMX_SP_CLK_3, 164, 1}, /* D_GPIO3 */ - {132, 0, PMX_PWM5_4, 165, 1}, /* D_GPIO4 */ - {132, 0, PMX_SB3_3_CK, 163, 1}, /* D_GPIO4 */ - {132, 0, PMX_SP_CLK2_3, 166, 1}, /* D_GPIO4 */ - {133, 0, PMX_ETH_LED2, 167, 1}, /* D_GPIO5 */ - {133, 0, PMX_PWM6_4, 168, 1}, /* D_GPIO5 */ - {133, 0, PMX_SB3_3_DAT, 163, 1}, /* D_GPIO5 */ - {134, 0, PMX_ETH_LED2, 167, 1}, /* D_GPIO6 */ - {134, 0, PMX_PWM7_4, 169, 1}, /* D_GPIO6 */ - {135, 0, PMX_PWM11_4, 170, 1}, /* D_GPIO7 */ - {160, 0, PMX_SENSOR_CCIR_2, 171, 2}, /* H_GPIO0 */ - {160, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 158, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 161, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 164, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 167, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 170, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 173, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 176, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 179, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 182, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_DE_ENABLE, 185, 3}, /* L_GPIO0 */ + {96, 0, PMX_PWM11_5, 188, 1}, /* L_GPIO0 */ + {97, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_HVLD_VVLD, 195, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_HVLD_VVLD, 167, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO1 */ + {97, 0, PMX_PICNT2_1, 204, 1}, /* L_GPIO1 */ + {98, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_HVLD_VVLD, 195, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_HVLD_VVLD, 167, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO2 */ + {98, 0, PMX_SP_CLK_2, 205, 1}, /* L_GPIO2 */ + {99, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_FIELD, 195, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_FIELD, 167, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO3 */ + {100, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO4 */ + {101, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO5 */ + {102, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO6 */ + {103, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO7 */ + {104, 0, PMX_LCD_CCIR601_16BITS, 189, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601_16BITS, 164, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656_16BITS, 192, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656_16BITS, 161, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* L_GPIO8 */ + {128, 0, PMX_ETH_LED1, 206, 1}, /* D_GPIO0 */ + {129, 0, PMX_ETH_LED1, 206, 1}, /* D_GPIO1 */ + {131, 0, PMX_PWM4_4, 207, 1}, /* D_GPIO3 */ + {131, 0, PMX_SB3_3_CS, 208, 1}, /* D_GPIO3 */ + {131, 0, PMX_SP_CLK_3, 209, 1}, /* D_GPIO3 */ + {132, 0, PMX_PWM5_4, 210, 1}, /* D_GPIO4 */ + {132, 0, PMX_SB3_3_CK, 208, 1}, /* D_GPIO4 */ + {132, 0, PMX_SP_CLK2_3, 211, 1}, /* D_GPIO4 */ + {133, 0, PMX_ETH_LED2, 212, 1}, /* D_GPIO5 */ + {133, 0, PMX_PWM6_4, 213, 1}, /* D_GPIO5 */ + {133, 0, PMX_SB3_3_DAT, 208, 1}, /* D_GPIO5 */ + {134, 0, PMX_ETH_LED2, 212, 1}, /* D_GPIO6 */ + {134, 0, PMX_PWM7_4, 214, 1}, /* D_GPIO6 */ + {135, 0, PMX_PWM11_4, 215, 1}, /* D_GPIO7 */ + {160, 0, PMX_SENSOR_CCIR_2, 216, 2}, /* H_GPIO0 */ {160, 0, PMX_SENSOR_CCIR_2, 138, 1}, /* H_GPIO0 */ + {160, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO0 */ {160, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO0 */ - {161, 0, PMX_SENSOR_CCIR_2, 171, 2}, /* H_GPIO1 */ - {161, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO1 */ + {161, 0, PMX_SENSOR_CCIR_2, 216, 2}, /* H_GPIO1 */ {161, 0, PMX_SENSOR_CCIR_2, 138, 1}, /* H_GPIO1 */ + {161, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO1 */ {161, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO1 */ {162, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO2 */ - {162, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO2 */ + {162, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO2 */ {162, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO2 */ {162, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO2 */ {163, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO3 */ - {163, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO3 */ + {163, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO3 */ {163, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO3 */ {163, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO3 */ {164, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO4 */ - {164, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO4 */ + {164, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO4 */ {164, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO4 */ {164, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO4 */ {165, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO5 */ - {165, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO5 */ + {165, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO5 */ {165, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO5 */ {165, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO5 */ - {166, 0, PMX_PWM8_3, 173, 1}, /* H_GPIO6 */ + {166, 0, PMX_PWM8_3, 218, 1}, /* H_GPIO6 */ {166, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO6 */ - {166, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO6 */ + {166, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO6 */ {166, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO6 */ {166, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO6 */ - {167, 0, PMX_PWM9_3, 174, 1}, /* H_GPIO7 */ + {167, 0, PMX_PWM9_3, 219, 1}, /* H_GPIO7 */ + {167, 0, PMX_SENSOR_LVDS_VDHD2, 220, 1}, /* H_GPIO7 */ {167, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO7 */ - {167, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO7 */ + {167, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO7 */ {167, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO7 */ - {167, 0, PMX_SENSOR_LVDS_VDHD2, 175, 1}, /* H_GPIO7 */ {167, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO7 */ - {168, 0, PMX_PWM10_3, 176, 1}, /* H_GPIO8 */ + {168, 0, PMX_PWM10_3, 221, 1}, /* H_GPIO8 */ + {168, 0, PMX_SENSOR_LVDS_VDHD2, 220, 1}, /* H_GPIO8 */ {168, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO8 */ - {168, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO8 */ + {168, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO8 */ {168, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO8 */ - {168, 0, PMX_SENSOR_LVDS_VDHD2, 175, 1}, /* H_GPIO8 */ {168, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO8 */ - {169, 0, PMX_I2C_2_SCL, 177, 1}, /* H_GPIO9 */ - {169, 0, PMX_PWM11_3, 178, 1}, /* H_GPIO9 */ + {169, 0, PMX_I2C_2_SCL, 222, 1}, /* H_GPIO9 */ + {169, 0, PMX_PWM11_3, 223, 1}, /* H_GPIO9 */ {169, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO9 */ - {169, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 55, 1}, /* H_GPIO9 */ + {169, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 52, 1}, /* H_GPIO9 */ {169, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 138, 1}, /* H_GPIO9 */ {169, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO9 */ - {170, 0, PMX_SENSOR_CCIR_2, 171, 2}, /* H_GPIO10 */ - {170, 0, PMX_I2C_2_SDA, 177, 1}, /* H_GPIO10 */ - {170, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO10 */ + {170, 0, PMX_SENSOR_CCIR_2, 216, 2}, /* H_GPIO10 */ + {170, 0, PMX_I2C_2_SDA, 222, 1}, /* H_GPIO10 */ {170, 0, PMX_SENSOR_CCIR_2, 138, 1}, /* H_GPIO10 */ + {170, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO10 */ {170, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO10 */ - {171, 0, PMX_SENSOR_MCLK_2ND, 179, 3}, /* H_GPIO11 */ - {171, 0, PMX_SENSOR_CCIR_2, 171, 2}, /* H_GPIO11 */ - {171, 0, PMX_SENSOR_MCLK_2ND, 182, 2}, /* H_GPIO11 */ - {171, 0, PMX_SENSOR_MCLK_2ND, 184, 2}, /* H_GPIO11 */ - {171, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO11 */ + {171, 0, PMX_SENSOR_MCLK_2ND, 224, 3}, /* H_GPIO11 */ + {171, 0, PMX_SENSOR_CCIR_2, 216, 2}, /* H_GPIO11 */ + {171, 0, PMX_SENSOR_MCLK_2ND, 227, 2}, /* H_GPIO11 */ {171, 0, PMX_SENSOR_CCIR_2, 138, 1}, /* H_GPIO11 */ - {171, 0, PMX_SENSOR_MCLK_2ND, 186, 1}, /* H_GPIO11 */ + {171, 0, PMX_SENSOR_MCLK_2ND, 229, 1}, /* H_GPIO11 */ + {171, NVT_UNGATED, PMX_SENSOR_12BITS, 137, 1}, /* H_GPIO11 */ {171, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO11 */ - {224, 0, PMX_ETH_MDIO, 187, 1}, /* DSI_GPIO0 */ - {224, 0, PMX_PWM0_5, 188, 1}, /* DSI_GPIO0 */ - {224, 0, PMX_UART3_1_TX, 189, 1}, /* DSI_GPIO0 */ - {225, 0, PMX_ETH_MDIO, 187, 1}, /* DSI_GPIO1 */ - {225, 0, PMX_PWM1_5, 190, 1}, /* DSI_GPIO1 */ - {225, 0, PMX_UART3_1_RX, 189, 1}, /* DSI_GPIO1 */ - {226, 0, PMX_UART3_1_RTS, 191, 2}, /* DSI_GPIO2 */ - {226, 0, PMX_UART3_1_RTS, 193, 2}, /* DSI_GPIO2 */ - {226, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO2 */ - {226, 0, PMX_PWM2_5, 196, 1}, /* DSI_GPIO2 */ - {226, 0, PMX_SDIO2_D0, 197, 1}, /* DSI_GPIO2 */ - {227, 0, PMX_UART3_1_CTS, 191, 2}, /* DSI_GPIO3 */ - {227, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO3 */ - {227, 0, PMX_PWM3_5, 198, 1}, /* DSI_GPIO3 */ - {227, 0, PMX_SDIO2_D1, 197, 1}, /* DSI_GPIO3 */ - {228, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO4 */ - {228, 0, PMX_PWM4_5, 199, 1}, /* DSI_GPIO4 */ - {228, 0, PMX_SDIO2_D2, 197, 1}, /* DSI_GPIO4 */ - {228, 0, PMX_SPI2_1_CS, 200, 1}, /* DSI_GPIO4 */ - {229, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO5 */ - {229, 0, PMX_PWM5_5, 201, 1}, /* DSI_GPIO5 */ - {229, 0, PMX_SDIO2_D3, 197, 1}, /* DSI_GPIO5 */ - {229, 0, PMX_SPI2_1_CLK, 200, 1}, /* DSI_GPIO5 */ - {230, 0, PMX_PWM6_5, 202, 1}, /* DSI_GPIO6 */ - {230, 0, PMX_SDIO2_CMD, 197, 1}, /* DSI_GPIO6 */ - {230, 0, PMX_SPI2_1_DO, 200, 1}, /* DSI_GPIO6 */ - {231, 0, PMX_SPI2_1_DI, 203, 2}, /* DSI_GPIO7 */ - {231, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO7 */ - {231, 0, PMX_PWM7_5, 205, 1}, /* DSI_GPIO7 */ - {231, 0, PMX_SDIO2_CLK, 197, 1}, /* DSI_GPIO7 */ - {232, 0, PMX_DMDAT0_2, 206, 3}, /* DSI_GPIO8 */ - {232, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO8 */ - {232, 0, PMX_I2C3_3_SDA, 209, 1}, /* DSI_GPIO8 */ - {232, 0, PMX_PWM8_5, 210, 1}, /* DSI_GPIO8 */ - {233, 0, PMX_DMDAT1_2, 206, 3}, /* DSI_GPIO9 */ - {233, 0, PMX_ETH_RMII, 211, 2}, /* DSI_GPIO9 */ - {233, 0, PMX_ETH_MDIO, 187, 1}, /* DSI_GPIO9 */ - {233, 0, PMX_ETH_RMII, 195, 1}, /* DSI_GPIO9 */ - {233, 0, PMX_I2C3_3_SCL, 209, 1}, /* DSI_GPIO9 */ - {233, 0, PMX_PWM9_5, 213, 1}, /* DSI_GPIO9 */ - {234, 0, PMX_DMCLK_2, 206, 3}, /* DSI_GPIO10 */ - {234, 0, PMX_ETH_EXTPHYCLK, 214, 1}, /* DSI_GPIO10 */ - {234, 0, PMX_ETH_MDIO, 187, 1}, /* DSI_GPIO10 */ - {234, 0, PMX_PWM10_5, 215, 1}, /* DSI_GPIO10 */ + {224, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO0 */ + {224, 0, PMX_ETH_MDIO, 236, 1}, /* DSI_GPIO0 */ + {224, 0, PMX_PWM0_5, 237, 1}, /* DSI_GPIO0 */ + {224, 0, PMX_UART3_1_TX, 238, 1}, /* DSI_GPIO0 */ + {225, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO1 */ + {225, 0, PMX_ETH_MDIO, 236, 1}, /* DSI_GPIO1 */ + {225, 0, PMX_PWM1_5, 239, 1}, /* DSI_GPIO1 */ + {225, 0, PMX_UART3_1_RX, 238, 1}, /* DSI_GPIO1 */ + {226, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO2 */ + {226, 0, PMX_UART3_1_RTS, 243, 2}, /* DSI_GPIO2 */ + {226, 0, PMX_UART3_1_RTS, 245, 2}, /* DSI_GPIO2 */ + {226, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO2 */ + {226, 0, PMX_PWM2_5, 248, 1}, /* DSI_GPIO2 */ + {226, 0, PMX_SDIO2_D0, 249, 1}, /* DSI_GPIO2 */ + {227, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO3 */ + {227, 0, PMX_UART3_1_CTS, 243, 2}, /* DSI_GPIO3 */ + {227, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO3 */ + {227, 0, PMX_PWM3_5, 250, 1}, /* DSI_GPIO3 */ + {227, 0, PMX_SDIO2_D1, 249, 1}, /* DSI_GPIO3 */ + {228, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO4 */ + {228, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO4 */ + {228, 0, PMX_PWM4_5, 251, 1}, /* DSI_GPIO4 */ + {228, 0, PMX_SDIO2_D2, 249, 1}, /* DSI_GPIO4 */ + {228, 0, PMX_SPI2_1_CS, 252, 1}, /* DSI_GPIO4 */ + {229, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO5 */ + {229, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO5 */ + {229, 0, PMX_PWM5_5, 253, 1}, /* DSI_GPIO5 */ + {229, 0, PMX_SDIO2_D3, 249, 1}, /* DSI_GPIO5 */ + {229, 0, PMX_SPI2_1_CLK, 252, 1}, /* DSI_GPIO5 */ + {230, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO6 */ + {230, 0, PMX_PWM6_5, 254, 1}, /* DSI_GPIO6 */ + {230, 0, PMX_SDIO2_CMD, 249, 1}, /* DSI_GPIO6 */ + {230, 0, PMX_SPI2_1_DO, 252, 1}, /* DSI_GPIO6 */ + {231, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO7 */ + {231, 0, PMX_SPI2_1_DI, 255, 2}, /* DSI_GPIO7 */ + {231, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO7 */ + {231, 0, PMX_PWM7_5, 257, 1}, /* DSI_GPIO7 */ + {231, 0, PMX_SDIO2_CLK, 249, 1}, /* DSI_GPIO7 */ + {232, 0, PMX_DMDAT0_2, 258, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 189, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 195, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 164, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 167, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 198, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 170, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 233, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 173, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 240, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 176, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 201, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 179, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 230, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_LCD_NO_HVSYNC, 185, 3}, /* DSI_GPIO8 */ + {232, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO8 */ + {232, 0, PMX_I2C3_3_SDA, 261, 1}, /* DSI_GPIO8 */ + {232, 0, PMX_PWM8_5, 262, 1}, /* DSI_GPIO8 */ + {233, 0, PMX_DMDAT1_2, 258, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 189, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 195, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 164, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 167, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 198, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 170, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 233, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 173, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 240, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 176, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 201, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 179, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 230, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_LCD_NO_HVSYNC, 185, 3}, /* DSI_GPIO9 */ + {233, 0, PMX_ETH_RMII, 263, 2}, /* DSI_GPIO9 */ + {233, 0, PMX_ETH_MDIO, 236, 1}, /* DSI_GPIO9 */ + {233, 0, PMX_ETH_RMII, 247, 1}, /* DSI_GPIO9 */ + {233, 0, PMX_I2C3_3_SCL, 261, 1}, /* DSI_GPIO9 */ + {233, 0, PMX_PWM9_5, 265, 1}, /* DSI_GPIO9 */ + {234, 0, PMX_LCD_TE_ENABLE, 266, 4}, /* DSI_GPIO10 */ + {234, 0, PMX_DMCLK_2, 258, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR601, 189, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR601, 195, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR601, 164, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR601, 167, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR656, 192, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_CCIR656, 161, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_PARALLE_RGB565, 198, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_PARALLE_RGB565, 170, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_PARALLE_RGB888, 230, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_PARALLE_RGB888, 185, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_RGB_16BITS, 201, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_RGB_16BITS, 179, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_SERIAL_RGB_6BITS, 240, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_SERIAL_RGB_6BITS, 176, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_SERIAL_RGB_8BITS, 233, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_LCD_SERIAL_RGB_8BITS, 173, 3}, /* DSI_GPIO10 */ + {234, 0, PMX_ETH_EXTPHYCLK, 270, 1}, /* DSI_GPIO10 */ + {234, 0, PMX_ETH_MDIO, 236, 1}, /* DSI_GPIO10 */ + {234, 0, PMX_PWM10_5, 271, 1}, /* DSI_GPIO10 */ }; /* The field each function's walk row shows: {pad, name, reg, @@ -817,95 +1124,95 @@ static const novatek_sel_t NA51089_sels[] = { {22, PMX_UART3_2_RX, 0x24, 4, 3, 2}, {32, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {32, PMX_PWM0_1, 0x1C, 0, 3, 1}, - {32, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, - {32, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, - {32, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {32, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {32, PMX_SPI2_2_CS, 0x14, 10, 2, 2}, {32, PMX_UART2_3_TX, 0x24, 2, 2, 3}, + {32, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {32, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {32, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {33, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {33, PMX_PWM1_1, 0x1C, 3, 3, 1}, - {33, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, - {33, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, - {33, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {33, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {33, PMX_SPI2_2_CLK, 0x14, 10, 2, 2}, {33, PMX_UART2_3_RX, 0x24, 2, 2, 3}, + {33, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {33, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {33, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {34, PMX_UART2_3_RTS, 0x24, 2, 2, 3}, {34, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {34, PMX_PWM2_1, 0x1C, 6, 3, 1}, + {34, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {34, PMX_SPI2_2_DO, 0x14, 10, 2, 2}, {34, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {34, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, {34, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, - {34, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, - {34, PMX_SPI2_2_DO, 0x14, 10, 2, 2}, {35, PMX_SPI2_2_DI, 0x14, 10, 2, 2}, {35, PMX_UART2_3_CTS, 0x24, 2, 2, 3}, {35, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {35, PMX_PWM3_1, 0x1C, 9, 3, 1}, + {35, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {35, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {35, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, {35, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, - {35, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {36, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {36, PMX_PWM4_1, 0x1C, 12, 3, 1}, - {36, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, - {36, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, - {36, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {36, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {36, PMX_SPI3_3_CS, 0x14, 12, 2, 3}, {36, PMX_UART3_3_TX, 0x24, 4, 3, 3}, + {36, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {36, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {36, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {37, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {37, PMX_PWM5_1, 0x1C, 15, 3, 1}, - {37, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, - {37, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, - {37, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {37, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {37, PMX_SPI3_3_CLK, 0x14, 12, 2, 3}, {37, PMX_UART3_3_RX, 0x24, 4, 3, 3}, + {37, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {37, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {37, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {38, PMX_UART3_3_RTS, 0x24, 4, 3, 3}, {38, PMX_PWM6_1, 0x1C, 18, 3, 1}, + {38, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {38, PMX_SPI3_3_DO, 0x14, 12, 2, 3}, {38, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {38, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, {38, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, - {38, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, - {38, PMX_SPI3_3_DO, 0x14, 12, 2, 3}, {39, PMX_ETH_EXTPHYCLK, 0x14, 30, 2, 2}, {39, PMX_SPI3_3_DI, 0x14, 12, 2, 3}, {39, PMX_UART3_3_CTS, 0x24, 4, 3, 3}, {39, PMX_PWM7_1, 0x1C, 21, 3, 1}, {39, PMX_SB4_CS, 0x14, 26, 1, 1}, + {39, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {39, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {39, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, {39, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, - {39, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {40, PMX_SPI_CH3_RDY, 0x14, 12, 2, 3}, {40, PMX_ETH_RMII_2, 0x14, 30, 2, 2}, {40, PMX_I2S_MCLK_1, 0x18, 2, 2, 1}, {40, PMX_PWM8_1, 0x18, 16, 3, 1}, {40, PMX_SB4_CK, 0x14, 26, 1, 1}, - {40, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {40, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {40, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {40, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {41, PMX_ETH_MDIO_2, 0x14, 2, 2, 2}, {41, PMX_I2S_BCLK_1, 0x18, 0, 2, 1}, {41, PMX_PWM9_1, 0x18, 19, 3, 1}, {41, PMX_SB4_DAT, 0x14, 26, 1, 1}, - {41, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {41, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {41, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {41, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {42, PMX_ETH_MDIO_2, 0x14, 2, 2, 2}, {42, PMX_I2S_SYNC_1, 0x18, 0, 2, 1}, {42, PMX_PWM10_1, 0x18, 22, 3, 1}, {42, PMX_SB3_1_CS, 0x14, 24, 2, 1}, - {42, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {42, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {42, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {42, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {43, PMX_I2S_SDATAO_1, 0x18, 0, 2, 1}, {43, PMX_PWM11_1, 0x18, 25, 3, 1}, {43, PMX_SB3_1_CK, 0x14, 24, 2, 1}, - {43, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {43, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {43, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, {43, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, {44, PMX_SENSOR2_SN3_MCLK, 0x0C, 16, 1, 1}, {44, PMX_SPI_CH3_RDY, 0x14, 12, 2, 1}, @@ -995,9 +1302,45 @@ static const novatek_sel_t NA51089_sels[] = { {72, PMX_SDIO2_D3, 0x04, 18, 2, 2}, {72, PMX_SENSOR2_MCLK_2ND, 0x0C, 12, 2, 2}, {72, PMX_SPI_2_DO, 0x14, 8, 2, 2}, + {96, PMX_LCD_DE_ENABLE, 0x08, 6, 1, 1}, {96, PMX_PWM11_5, 0x18, 25, 3, 5}, + {97, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {97, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {97, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {97, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {97, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, {97, PMX_PICNT2_1, 0x1C, 28, 2, 1}, + {98, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {98, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {98, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {98, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {98, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, {98, PMX_SP_CLK_2, 0x0C, 18, 2, 2}, + {99, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {99, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {99, PMX_LCD_FIELD, 0x08, 8, 1, 1}, + {99, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {99, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {100, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {100, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {100, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {100, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {101, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {101, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {101, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {101, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {102, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {102, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {102, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {102, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {103, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {103, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {103, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {103, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {104, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {104, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {104, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {104, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, {128, PMX_ETH_LED1, 0x18, 13, 2, 1}, {129, PMX_ETH_LED1, 0x18, 13, 2, 1}, {131, PMX_PWM4_4, 0x1C, 12, 3, 4}, @@ -1040,16 +1383,16 @@ static const novatek_sel_t NA51089_sels[] = { {166, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, {166, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, {167, PMX_PWM9_3, 0x18, 19, 3, 3}, + {167, PMX_SENSOR_LVDS_VDHD2, 0x0C, 10, 2, 2}, {167, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, {167, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {167, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, - {167, PMX_SENSOR_LVDS_VDHD2, 0x0C, 10, 2, 2}, {167, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, {168, PMX_PWM10_3, 0x18, 22, 3, 3}, + {168, PMX_SENSOR_LVDS_VDHD2, 0x0C, 10, 2, 2}, {168, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, {168, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, {168, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, - {168, PMX_SENSOR_LVDS_VDHD2, 0x0C, 10, 2, 2}, {168, PMX_MIPI_LVDS_DAT3, NVT_GATE, 0, 0, 0}, {169, PMX_I2C_2_SCL, 0x14, 0, 2, 2}, {169, PMX_PWM11_3, 0x18, 25, 3, 3}, @@ -1065,53 +1408,3265 @@ static const novatek_sel_t NA51089_sels[] = { {171, PMX_SENSOR_CCIR_2, 0x0C, 0, 3, 3}, {171, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, {171, PMX_MIPI_LVDS_CLK1, NVT_GATE, 0, 0, 0}, + {224, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {224, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {224, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {224, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {224, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {224, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {224, PMX_ETH_MDIO, 0x14, 2, 2, 1}, {224, PMX_PWM0_5, 0x1C, 0, 3, 5}, {224, PMX_UART3_1_TX, 0x24, 4, 3, 1}, + {225, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {225, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {225, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {225, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {225, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {225, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {225, PMX_ETH_MDIO, 0x14, 2, 2, 1}, {225, PMX_PWM1_5, 0x1C, 3, 3, 5}, {225, PMX_UART3_1_RX, 0x24, 4, 3, 1}, + {226, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {226, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {226, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {226, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {226, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {226, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {226, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {226, PMX_UART3_1_RTS, 0x24, 4, 3, 1}, {226, PMX_ETH_RMII, 0x14, 30, 2, 1}, {226, PMX_PWM2_5, 0x1C, 6, 3, 5}, {226, PMX_SDIO2_D0, 0x04, 18, 2, 3}, + {227, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {227, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {227, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {227, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {227, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {227, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {227, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {227, PMX_UART3_1_CTS, 0x24, 4, 3, 1}, {227, PMX_ETH_RMII, 0x14, 30, 2, 1}, {227, PMX_PWM3_5, 0x1C, 9, 3, 5}, {227, PMX_SDIO2_D1, 0x04, 18, 2, 3}, + {228, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {228, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {228, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {228, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {228, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {228, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {228, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {228, PMX_ETH_RMII, 0x14, 30, 2, 1}, {228, PMX_PWM4_5, 0x1C, 12, 3, 5}, {228, PMX_SDIO2_D2, 0x04, 18, 2, 3}, {228, PMX_SPI2_1_CS, 0x14, 10, 2, 1}, + {229, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {229, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {229, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {229, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {229, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {229, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {229, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {229, PMX_ETH_RMII, 0x14, 30, 2, 1}, {229, PMX_PWM5_5, 0x1C, 15, 3, 5}, {229, PMX_SDIO2_D3, 0x04, 18, 2, 3}, {229, PMX_SPI2_1_CLK, 0x14, 10, 2, 1}, + {230, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {230, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {230, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {230, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {230, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {230, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {230, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {230, PMX_PWM6_5, 0x1C, 18, 3, 5}, {230, PMX_SDIO2_CMD, 0x04, 18, 2, 3}, {230, PMX_SPI2_1_DO, 0x14, 10, 2, 1}, + {231, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {231, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {231, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {231, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {231, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {231, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {231, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {231, PMX_SPI2_1_DI, 0x14, 10, 2, 1}, {231, PMX_ETH_RMII, 0x14, 30, 2, 1}, {231, PMX_PWM7_5, 0x1C, 21, 3, 5}, {231, PMX_SDIO2_CLK, 0x04, 18, 2, 3}, {232, PMX_DMDAT0_2, 0x18, 5, 1, 1}, + {232, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, {232, PMX_ETH_RMII, 0x14, 30, 2, 1}, {232, PMX_I2C3_3_SDA, 0x14, 6, 2, 3}, {232, PMX_PWM8_5, 0x18, 16, 3, 5}, {233, PMX_DMDAT1_2, 0x18, 5, 1, 1}, + {233, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, {233, PMX_ETH_RMII, 0x14, 30, 2, 1}, {233, PMX_ETH_MDIO, 0x14, 2, 2, 1}, {233, PMX_I2C3_3_SCL, 0x14, 6, 2, 3}, {233, PMX_PWM9_5, 0x18, 19, 3, 5}, + {234, PMX_LCD_TE_ENABLE, 0x08, 0, 4, 9}, {234, PMX_DMCLK_2, 0x18, 5, 1, 1}, + {234, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {234, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {234, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {234, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {234, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {234, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {234, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, {234, PMX_ETH_EXTPHYCLK, 0x18, 28, 1, 1}, {234, PMX_ETH_MDIO, 0x14, 2, 2, 1}, {234, PMX_PWM10_5, 0x18, 22, 3, 5}, }; static const novatek_soc_t NA51089_padmux = { - NA51089_pads, 102, NA51089_claims, 388, NA51089_conds, - NA51089_sels, 368, + NA51089_pads, 102, NA51089_claims, 636, NA51089_conds, + NA51089_sels, 468, +}; + +/* NA51055: 83715 vendor states replayed; in 28642 of them two claims hold + * at once and the table carries the one the vendor code meant, + * and 292 leave a pad cleared with its field moved elsewhere, + * which reads as unnamed. */ + +/* Every pad the package bonds out, by Linux GPIO number. */ +static const novatek_pad_t NA51055_pads[] = { + {0, PMX_C_GPIO0}, + {1, PMX_C_GPIO1}, + {2, PMX_C_GPIO2}, + {3, PMX_C_GPIO3}, + {4, PMX_C_GPIO4}, + {5, PMX_C_GPIO5}, + {6, PMX_C_GPIO6}, + {7, PMX_C_GPIO7}, + {8, PMX_C_GPIO8}, + {9, PMX_C_GPIO9}, + {10, PMX_C_GPIO10}, + {11, PMX_C_GPIO11}, + {12, PMX_C_GPIO12}, + {13, PMX_C_GPIO13}, + {14, PMX_C_GPIO14}, + {15, PMX_C_GPIO15}, + {16, PMX_C_GPIO16}, + {17, PMX_C_GPIO17}, + {18, PMX_C_GPIO18}, + {19, PMX_C_GPIO19}, + {20, PMX_C_GPIO20}, + {21, PMX_C_GPIO21}, + {22, PMX_C_GPIO22}, + {32, PMX_P_GPIO0}, + {33, PMX_P_GPIO1}, + {34, PMX_P_GPIO2}, + {35, PMX_P_GPIO3}, + {36, PMX_P_GPIO4}, + {37, PMX_P_GPIO5}, + {38, PMX_P_GPIO6}, + {39, PMX_P_GPIO7}, + {40, PMX_P_GPIO8}, + {41, PMX_P_GPIO9}, + {42, PMX_P_GPIO10}, + {43, PMX_P_GPIO11}, + {44, PMX_P_GPIO12}, + {45, PMX_P_GPIO13}, + {46, PMX_P_GPIO14}, + {47, PMX_P_GPIO15}, + {48, PMX_P_GPIO16}, + {49, PMX_P_GPIO17}, + {50, PMX_P_GPIO18}, + {51, PMX_P_GPIO19}, + {52, PMX_P_GPIO20}, + {53, PMX_P_GPIO21}, + {54, PMX_P_GPIO22}, + {55, PMX_P_GPIO23}, + {56, PMX_P_GPIO24}, + {57, PMX_P_GPIO25}, + {64, PMX_S_GPIO0}, + {65, PMX_S_GPIO1}, + {66, PMX_S_GPIO2}, + {67, PMX_S_GPIO3}, + {68, PMX_S_GPIO4}, + {69, PMX_S_GPIO5}, + {70, PMX_S_GPIO6}, + {71, PMX_S_GPIO7}, + {72, PMX_S_GPIO8}, + {73, PMX_S_GPIO9}, + {74, PMX_S_GPIO10}, + {75, PMX_S_GPIO11}, + {76, PMX_S_GPIO12}, + {96, PMX_L_GPIO0}, + {97, PMX_L_GPIO1}, + {98, PMX_L_GPIO2}, + {99, PMX_L_GPIO3}, + {100, PMX_L_GPIO4}, + {101, PMX_L_GPIO5}, + {102, PMX_L_GPIO6}, + {103, PMX_L_GPIO7}, + {104, PMX_L_GPIO8}, + {105, PMX_L_GPIO9}, + {106, PMX_L_GPIO10}, + {107, PMX_L_GPIO11}, + {108, PMX_L_GPIO12}, + {109, PMX_L_GPIO13}, + {110, PMX_L_GPIO14}, + {111, PMX_L_GPIO15}, + {112, PMX_L_GPIO16}, + {113, PMX_L_GPIO17}, + {114, PMX_L_GPIO18}, + {115, PMX_L_GPIO19}, + {116, PMX_L_GPIO20}, + {117, PMX_L_GPIO21}, + {118, PMX_L_GPIO22}, + {119, PMX_L_GPIO23}, + {120, PMX_L_GPIO24}, + {128, PMX_D_GPIO0}, + {129, PMX_D_GPIO1}, + {130, PMX_D_GPIO2}, + {131, PMX_D_GPIO3}, + {132, PMX_D_GPIO4}, + {133, PMX_D_GPIO5}, + {134, PMX_D_GPIO6}, + {135, PMX_D_GPIO7}, + {136, PMX_D_GPIO8}, + {137, PMX_D_GPIO9}, + {138, PMX_D_GPIO10}, + {160, PMX_H_GPIO0}, + {161, PMX_H_GPIO1}, + {162, PMX_H_GPIO2}, + {163, PMX_H_GPIO3}, + {164, PMX_H_GPIO4}, + {165, PMX_H_GPIO5}, + {166, PMX_H_GPIO6}, + {167, PMX_H_GPIO7}, + {168, PMX_H_GPIO8}, + {169, PMX_H_GPIO9}, + {170, PMX_H_GPIO10}, + {171, PMX_H_GPIO11}, + {192, PMX_A_GPIO0}, + {193, PMX_A_GPIO1}, + {194, PMX_A_GPIO2}, +}; + +/* TOP register offset, field shift, width, value. */ +static const novatek_cond_t NA51055_conds[] = { + {0x04, 17, 1, 1}, + {0x24, 4, 3, 5}, + {0x04, 17, 1, 1}, + {0x04, 31, 1, 1}, + {0x18, 0, 2, 2}, + {0x1C, 0, 3, 4}, + {0x24, 12, 2, 2}, + {0x1C, 3, 3, 4}, + {0x24, 12, 2, 2}, + {0x24, 18, 2, 1}, + {0x24, 12, 2, 2}, + {0x24, 18, 2, 2}, + {0x1C, 6, 3, 4}, + {0x1C, 9, 3, 4}, + {0x18, 10, 2, 2}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 3}, + {0x14, 6, 2, 2}, + {0x1C, 12, 3, 2}, + {0x04, 14, 1, 1}, + {0x14, 12, 2, 2}, + {0x1C, 15, 3, 2}, + {0x24, 2, 2, 2}, + {0x24, 8, 2, 1}, + {0x1C, 0, 3, 2}, + {0x14, 12, 2, 2}, + {0x14, 18, 1, 1}, + {0x24, 2, 2, 2}, + {0x24, 8, 2, 2}, + {0x1C, 3, 3, 2}, + {0x18, 7, 2, 2}, + {0x14, 12, 2, 2}, + {0x14, 14, 2, 2}, + {0x1C, 6, 3, 2}, + {0x24, 2, 2, 2}, + {0x1C, 9, 3, 2}, + {0x14, 4, 2, 2}, + {0x1C, 18, 3, 2}, + {0x04, 15, 1, 1}, + {0x14, 8, 2, 1}, + {0x1C, 21, 3, 2}, + {0x24, 4, 3, 2}, + {0x24, 10, 2, 1}, + {0x18, 16, 3, 2}, + {0x14, 8, 2, 1}, + {0x14, 16, 1, 1}, + {0x24, 4, 3, 2}, + {0x24, 10, 2, 2}, + {0x18, 19, 3, 2}, + {0x18, 22, 3, 2}, + {0x24, 4, 3, 2}, + {0x18, 25, 3, 2}, + {0x1C, 0, 3, 1}, + {0x0C, 0, 3, 4}, + {0x14, 10, 2, 2}, + {0x24, 2, 2, 3}, + {0x24, 12, 2, 1}, + {0x0C, 4, 2, 1}, + {0x0C, 4, 2, 2}, + {0x0C, 0, 3, 2}, + {0x1C, 3, 3, 1}, + {0x18, 9, 1, 1}, + {0x24, 2, 2, 3}, + {0x24, 8, 2, 1}, + {0x24, 2, 2, 3}, + {0x24, 8, 2, 2}, + {0x24, 12, 2, 1}, + {0x24, 18, 2, 1}, + {0x24, 12, 2, 1}, + {0x24, 18, 2, 2}, + {0x1C, 6, 3, 1}, + {0x14, 10, 2, 2}, + {0x14, 17, 1, 1}, + {0x1C, 9, 3, 1}, + {0x1C, 12, 3, 1}, + {0x14, 12, 2, 3}, + {0x24, 4, 3, 3}, + {0x24, 14, 2, 1}, + {0x1C, 15, 3, 1}, + {0x24, 4, 3, 3}, + {0x24, 10, 2, 1}, + {0x24, 4, 3, 3}, + {0x24, 10, 2, 2}, + {0x24, 14, 2, 1}, + {0x24, 20, 2, 1}, + {0x24, 14, 2, 1}, + {0x24, 20, 2, 2}, + {0x1C, 18, 3, 1}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 1}, + {0x14, 12, 2, 3}, + {0x14, 18, 1, 1}, + {0x1C, 21, 3, 1}, + {0x18, 16, 3, 1}, + {0x14, 8, 2, 3}, + {0x24, 16, 2, 1}, + {0x18, 19, 3, 1}, + {0x24, 16, 2, 1}, + {0x24, 22, 2, 1}, + {0x24, 16, 2, 1}, + {0x24, 22, 2, 2}, + {0x18, 22, 3, 1}, + {0x14, 8, 2, 3}, + {0x14, 16, 1, 1}, + {0x18, 25, 3, 1}, + {0x0C, 4, 2, 1}, + {0x0C, 16, 1, 1}, + {0x14, 12, 2, 1}, + {0x14, 14, 2, 1}, + {0x1C, 26, 2, 1}, + {0x0C, 16, 1, 1}, + {0x14, 26, 1, 1}, + {0x14, 10, 2, 1}, + {0x24, 4, 3, 1}, + {0x1C, 28, 2, 1}, + {0x24, 4, 3, 1}, + {0x24, 10, 2, 1}, + {0x24, 4, 3, 1}, + {0x24, 10, 2, 2}, + {0x14, 10, 2, 1}, + {0x14, 17, 1, 1}, + {0x18, 2, 2, 1}, + {0x14, 24, 2, 2}, + {0x18, 0, 2, 1}, + {0x1C, 30, 2, 1}, + {0x18, 7, 2, 1}, + {0x0C, 18, 2, 1}, + {0x14, 12, 2, 1}, + {0x24, 2, 2, 1}, + {0x1C, 26, 2, 2}, + {0x18, 10, 2, 1}, + {0x24, 2, 2, 1}, + {0x24, 8, 2, 1}, + {0x24, 2, 2, 1}, + {0x24, 8, 2, 2}, + {0x1C, 28, 2, 2}, + {0x0C, 18, 2, 2}, + {0x14, 12, 2, 1}, + {0x14, 18, 1, 1}, + {0x1C, 30, 2, 2}, + {0x14, 6, 2, 1}, + {0x24, 0, 1, 1}, + {0x0C, 8, 2, 1}, + {0x0C, 0, 3, 1}, + {0x0C, 12, 2, 1}, + {0x0C, 0, 3, 3}, + {0x0C, 12, 2, 1}, + {0x0C, 0, 3, 4}, + {0x0C, 12, 2, 1}, + {0x1C, 0, 3, 3}, + {0x0C, 0, 3, 1}, + {0x0C, 0, 3, 3}, + {0x0C, 12, 2, 1}, + {0x1C, 3, 3, 3}, + {0x0C, 10, 1, 1}, + {0x1C, 6, 3, 3}, + {0x1C, 9, 3, 3}, + {0x0C, 14, 1, 1}, + {0x24, 4, 3, 4}, + {0x1C, 12, 3, 3}, + {0x1C, 15, 3, 3}, + {0x14, 20, 1, 1}, + {0x14, 0, 2, 1}, + {0x1C, 18, 3, 3}, + {0x1C, 21, 3, 3}, + {0x14, 22, 1, 1}, + {0x14, 8, 2, 2}, + {0x14, 4, 2, 1}, + {0x14, 8, 2, 2}, + {0x14, 16, 1, 1}, + {0x0C, 12, 2, 2}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 8}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 8}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x1C, 0, 3, 5}, + {0x1C, 3, 3, 5}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x1C, 6, 3, 5}, + {0x1C, 9, 3, 5}, + {0x1C, 12, 3, 5}, + {0x1C, 15, 3, 5}, + {0x1C, 18, 3, 5}, + {0x18, 28, 1, 1}, + {0x1C, 21, 3, 5}, + {0x18, 16, 3, 5}, + {0x18, 19, 3, 5}, + {0x18, 22, 3, 5}, + {0x08, 0, 4, 0}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x18, 25, 3, 5}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 10, 1, 1}, + {0x14, 24, 2, 1}, + {0x18, 13, 2, 1}, + {0x18, 7, 2, 3}, + {0x1C, 12, 3, 4}, + {0x0C, 18, 2, 3}, + {0x1C, 15, 3, 4}, + {0x18, 10, 2, 3}, + {0x18, 13, 2, 2}, + {0x1C, 18, 3, 4}, + {0x1C, 21, 3, 4}, + {0x18, 2, 2, 2}, + {0x18, 25, 3, 4}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 2}, + {0x18, 16, 3, 4}, + {0x14, 24, 2, 3}, + {0x18, 19, 3, 4}, + {0x18, 22, 3, 4}, +}; + +/* Per pad, most conditions first: the first claim that holds + * is what the pad carries. {pad, flags, name, first + * condition, how many}. */ +static const novatek_claim_t NA51055_claims[] = { + {0, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO0 */ + {0, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO0 */ + {1, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO1 */ + {1, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO1 */ + {2, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO2 */ + {2, 0, PMX_UART_CH3_5TH, 1, 1}, /* C_GPIO2 */ + {2, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO2 */ + {3, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO3 */ + {3, 0, PMX_UART_CH3_5TH, 1, 1}, /* C_GPIO3 */ + {3, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO3 */ + {4, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO4 */ + {4, 0, PMX_I2S_BCLK_2, 4, 1}, /* C_GPIO4 */ + {4, 0, PMX_PWM0_4, 5, 1}, /* C_GPIO4 */ + {4, 0, PMX_UART_CH4_2ND, 6, 1}, /* C_GPIO4 */ + {5, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO5 */ + {5, 0, PMX_I2S_SYNC_2, 4, 1}, /* C_GPIO5 */ + {5, 0, PMX_PWM1_4, 7, 1}, /* C_GPIO5 */ + {5, 0, PMX_UART_CH4_2ND, 6, 1}, /* C_GPIO5 */ + {6, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO6 */ + {6, 0, PMX_UART_CH4_CTSRTS, 8, 2}, /* C_GPIO6 */ + {6, 0, PMX_UART_CH4_DIROE, 10, 2}, /* C_GPIO6 */ + {6, 0, PMX_I2S_SDATAO_2, 4, 1}, /* C_GPIO6 */ + {6, 0, PMX_PWM2_4, 12, 1}, /* C_GPIO6 */ + {7, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO7 */ + {7, 0, PMX_UART_CH4_CTSRTS, 8, 2}, /* C_GPIO7 */ + {7, 0, PMX_I2S_SDATAI_2, 4, 1}, /* C_GPIO7 */ + {7, 0, PMX_PWM3_4, 13, 1}, /* C_GPIO7 */ + {8, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO8 */ + {8, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO8 */ + {9, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO9 */ + {9, 0, PMX_SENSOR_SP2CLK_2ND, 14, 1}, /* C_GPIO9 */ + {10, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO10 */ + {11, 0, PMX_DMCLK_3, 15, 3}, /* C_GPIO11 */ + {11, 0, PMX_I2C3_2_SCL, 18, 1}, /* C_GPIO11 */ + {11, 0, PMX_PWM4_2, 19, 1}, /* C_GPIO11 */ + {11, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO11 */ + {11, 0, PMX_SPI3_2_CLK, 21, 1}, /* C_GPIO11 */ + {12, 0, PMX_DMDAT0_3, 15, 3}, /* C_GPIO12 */ + {12, 0, PMX_I2C3_2_SDA, 18, 1}, /* C_GPIO12 */ + {12, 0, PMX_PWM5_2, 22, 1}, /* C_GPIO12 */ + {12, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO12 */ + {12, 0, PMX_SPI3_2_DO, 21, 1}, /* C_GPIO12 */ + {13, 0, PMX_DMDAT1_3, 15, 3}, /* C_GPIO13 */ + {13, 0, PMX_UART2_2_CTS, 23, 2}, /* C_GPIO13 */ + {13, 0, PMX_PWM0_2, 25, 1}, /* C_GPIO13 */ + {13, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO13 */ + {13, 0, PMX_SPI3_2_CS, 21, 1}, /* C_GPIO13 */ + {14, 0, PMX_SPI3_2_DI, 26, 2}, /* C_GPIO14 */ + {14, 0, PMX_UART2_2_RTS, 23, 2}, /* C_GPIO14 */ + {14, 0, PMX_UART2_2_RTS, 28, 2}, /* C_GPIO14 */ + {14, 0, PMX_PWM1_2, 30, 1}, /* C_GPIO14 */ + {14, 0, PMX_REMOTE_IN_2, 31, 1}, /* C_GPIO14 */ + {14, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO14 */ + {15, 0, PMX_SPI_CH3_RDY, 32, 2}, /* C_GPIO15 */ + {15, 0, PMX_PWM2_2, 34, 1}, /* C_GPIO15 */ + {15, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO15 */ + {15, 0, PMX_UART2_2_TX, 35, 1}, /* C_GPIO15 */ + {16, 0, PMX_PWM3_2, 36, 1}, /* C_GPIO16 */ + {16, 0, PMX_SDIO_4BITS, 20, 1}, /* C_GPIO16 */ + {16, 0, PMX_UART2_2_RX, 35, 1}, /* C_GPIO16 */ + {17, 0, PMX_I2C2_2_SCL, 37, 1}, /* C_GPIO17 */ + {17, 0, PMX_PWM6_2, 38, 1}, /* C_GPIO17 */ + {17, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO17 */ + {17, 0, PMX_SPI_1_CLK, 40, 1}, /* C_GPIO17 */ + {18, 0, PMX_I2C2_2_SDA, 37, 1}, /* C_GPIO18 */ + {18, 0, PMX_PWM7_2, 41, 1}, /* C_GPIO18 */ + {18, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO18 */ + {18, 0, PMX_SPI_1_DO, 40, 1}, /* C_GPIO18 */ + {19, 0, PMX_UART3_2_CTS, 42, 2}, /* C_GPIO19 */ + {19, 0, PMX_PWM8_2, 44, 1}, /* C_GPIO19 */ + {19, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO19 */ + {19, 0, PMX_SPI_1_CS, 40, 1}, /* C_GPIO19 */ + {20, 0, PMX_SPI_1_DI, 45, 2}, /* C_GPIO20 */ + {20, 0, PMX_UART3_2_RTS, 42, 2}, /* C_GPIO20 */ + {20, 0, PMX_UART3_2_RTS, 47, 2}, /* C_GPIO20 */ + {20, 0, PMX_PWM9_2, 49, 1}, /* C_GPIO20 */ + {20, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO20 */ + {21, 0, PMX_PWM10_2, 50, 1}, /* C_GPIO21 */ + {21, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO21 */ + {21, 0, PMX_UART3_2_TX, 51, 1}, /* C_GPIO21 */ + {22, 0, PMX_PWM11_2, 52, 1}, /* C_GPIO22 */ + {22, 0, PMX_SDIO_4BITS, 39, 1}, /* C_GPIO22 */ + {22, 0, PMX_UART3_2_RX, 51, 1}, /* C_GPIO22 */ + {32, 0, PMX_PWM0_1, 53, 1}, /* P_GPIO0 */ + {32, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO0 */ + {32, 0, PMX_SPI2_2_CS, 55, 1}, /* P_GPIO0 */ + {32, 0, PMX_UART2_3_TX, 56, 1}, /* P_GPIO0 */ + {32, 0, PMX_UART2_3_TX, 57, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO0 */ + {33, 0, PMX_PWM1_1, 61, 1}, /* P_GPIO1 */ + {33, 0, PMX_RTC_CLK, 62, 1}, /* P_GPIO1 */ + {33, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO1 */ + {33, 0, PMX_SPI2_2_CLK, 55, 1}, /* P_GPIO1 */ + {33, 0, PMX_UART2_3_RX, 56, 1}, /* P_GPIO1 */ + {33, 0, PMX_UART2_3_RX, 57, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO1 */ + {34, 0, PMX_UART2_3_RTS, 63, 2}, /* P_GPIO2 */ + {34, 0, PMX_UART2_3_RTS, 65, 2}, /* P_GPIO2 */ + {34, 0, PMX_UART2_3_RTS, 67, 2}, /* P_GPIO2 */ + {34, 0, PMX_UART2_3_RTS, 69, 2}, /* P_GPIO2 */ + {34, 0, PMX_PWM2_1, 71, 1}, /* P_GPIO2 */ + {34, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO2 */ + {34, 0, PMX_SPI2_2_DO, 55, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO2 */ + {35, 0, PMX_SPI2_2_DI, 72, 2}, /* P_GPIO3 */ + {35, 0, PMX_UART2_3_CTS, 63, 2}, /* P_GPIO3 */ + {35, 0, PMX_UART2_3_CTS, 67, 2}, /* P_GPIO3 */ + {35, 0, PMX_PWM3_1, 74, 1}, /* P_GPIO3 */ + {35, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO3 */ + {36, 0, PMX_PWM4_1, 75, 1}, /* P_GPIO4 */ + {36, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO4 */ + {36, 0, PMX_SPI3_3_CS, 76, 1}, /* P_GPIO4 */ + {36, 0, PMX_UART3_3_TX, 77, 1}, /* P_GPIO4 */ + {36, 0, PMX_UART3_3_TX, 78, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO4 */ + {37, 0, PMX_PWM5_1, 79, 1}, /* P_GPIO5 */ + {37, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO5 */ + {37, 0, PMX_SPI3_3_CLK, 76, 1}, /* P_GPIO5 */ + {37, 0, PMX_UART3_3_RX, 77, 1}, /* P_GPIO5 */ + {37, 0, PMX_UART3_3_RX, 78, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO5 */ + {38, 0, PMX_UART3_3_RTS, 80, 2}, /* P_GPIO6 */ + {38, 0, PMX_UART3_3_RTS, 82, 2}, /* P_GPIO6 */ + {38, 0, PMX_UART3_3_RTS, 84, 2}, /* P_GPIO6 */ + {38, 0, PMX_UART3_3_RTS, 86, 2}, /* P_GPIO6 */ + {38, 0, PMX_PWM6_1, 88, 1}, /* P_GPIO6 */ + {38, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO6 */ + {38, 0, PMX_SPI3_3_DO, 76, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO6 */ + {39, 0, PMX_DMDAT0_1, 89, 3}, /* P_GPIO7 */ + {39, 0, PMX_SPI3_3_DI, 92, 2}, /* P_GPIO7 */ + {39, 0, PMX_UART3_3_CTS, 80, 2}, /* P_GPIO7 */ + {39, 0, PMX_UART3_3_CTS, 84, 2}, /* P_GPIO7 */ + {39, 0, PMX_PWM7_1, 94, 1}, /* P_GPIO7 */ + {39, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO7 */ + {40, 0, PMX_DMDAT1_1, 89, 3}, /* P_GPIO8 */ + {40, 0, PMX_PWM8_1, 95, 1}, /* P_GPIO8 */ + {40, 0, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO8 */ + {40, 0, PMX_SPI_3_CS, 96, 1}, /* P_GPIO8 */ + {40, 0, PMX_UART_CH6, 97, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO8 */ + {41, 0, PMX_DMCLK_1, 89, 3}, /* P_GPIO9 */ + {41, 0, PMX_PWM9_1, 98, 1}, /* P_GPIO9 */ + {41, 0, PMX_SENSOR2_CCIR8BITS_VDHD, 59, 1}, /* P_GPIO9 */ + {41, 0, PMX_SPI_3_CLK, 96, 1}, /* P_GPIO9 */ + {41, 0, PMX_UART_CH6, 97, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO9 */ + {42, 0, PMX_UART_CH6_CTSRTS, 99, 2}, /* P_GPIO10 */ + {42, 0, PMX_UART_CH6_DIROE, 101, 2}, /* P_GPIO10 */ + {42, 0, PMX_PWM10_1, 103, 1}, /* P_GPIO10 */ + {42, 0, PMX_SENSOR2_CCIR8BITS_VDHD, 59, 1}, /* P_GPIO10 */ + {42, 0, PMX_SPI_3_DO, 96, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO10 */ + {43, 0, PMX_SPI_3_DI, 104, 2}, /* P_GPIO11 */ + {43, 0, PMX_UART_CH6_CTSRTS, 99, 2}, /* P_GPIO11 */ + {43, 0, PMX_PWM11_1, 106, 1}, /* P_GPIO11 */ + {43, 0, PMX_SENSOR2_CCIR8BITS_FIELD, 59, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 59, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO11 */ + {44, 0, PMX_SENSOR2_SN3_MCLK, 107, 2}, /* P_GPIO12 */ + {44, 0, PMX_SPI_CH3_RDY, 109, 2}, /* P_GPIO12 */ + {44, 0, PMX_PICNT_1, 111, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR2_12BITS, 58, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR2_SN3_MCLK, 112, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR_12BITS_2ND, 60, 1}, /* P_GPIO12 */ + {45, 0, PMX_SB4_CS, 113, 1}, /* P_GPIO13 */ + {45, 0, PMX_SPI2_1_CS, 114, 1}, /* P_GPIO13 */ + {45, 0, PMX_UART3_1_TX, 115, 1}, /* P_GPIO13 */ + {46, 0, PMX_PICNT2_1, 116, 1}, /* P_GPIO14 */ + {46, 0, PMX_SB4_CK, 113, 1}, /* P_GPIO14 */ + {46, 0, PMX_SPI2_1_CLK, 114, 1}, /* P_GPIO14 */ + {46, 0, PMX_UART3_1_RX, 115, 1}, /* P_GPIO14 */ + {47, 0, PMX_UART3_1_RTS, 117, 2}, /* P_GPIO15 */ + {47, 0, PMX_UART3_1_RTS, 119, 2}, /* P_GPIO15 */ + {47, 0, PMX_SB4_DAT, 113, 1}, /* P_GPIO15 */ + {47, 0, PMX_SPI2_1_DO, 114, 1}, /* P_GPIO15 */ + {47, 0, PMX_SP_CLK2_2, 14, 1}, /* P_GPIO15 */ + {48, 0, PMX_SPI2_1_DI, 121, 2}, /* P_GPIO16 */ + {48, 0, PMX_UART3_1_CTS, 117, 2}, /* P_GPIO16 */ + {48, 0, PMX_I2S_1_MCLK, 123, 1}, /* P_GPIO16 */ + {48, 0, PMX_SB3_2_CS, 124, 1}, /* P_GPIO16 */ + {49, 0, PMX_I2S_BCLK_1, 125, 1}, /* P_GPIO17 */ + {49, 0, PMX_PICNT3_1, 126, 1}, /* P_GPIO17 */ + {49, 0, PMX_REMOTE_IN_1, 127, 1}, /* P_GPIO17 */ + {49, 0, PMX_SENSOR_SPCLK, 128, 1}, /* P_GPIO17 */ + {49, 0, PMX_SPI3_1_CS, 129, 1}, /* P_GPIO17 */ + {49, 0, PMX_UART2_1_TX, 130, 1}, /* P_GPIO17 */ + {50, 0, PMX_I2S_SYNC_1, 125, 1}, /* P_GPIO18 */ + {50, 0, PMX_PICNT_2, 131, 1}, /* P_GPIO18 */ + {50, 0, PMX_SENSOR_SP2CLK, 132, 1}, /* P_GPIO18 */ + {50, 0, PMX_SPI3_1_CLK, 129, 1}, /* P_GPIO18 */ + {50, 0, PMX_UART2_1_RX, 130, 1}, /* P_GPIO18 */ + {51, 0, PMX_UART2_1_RTS, 133, 2}, /* P_GPIO19 */ + {51, 0, PMX_UART2_1_RTS, 135, 2}, /* P_GPIO19 */ + {51, 0, PMX_I2S_SDATAO_1, 125, 1}, /* P_GPIO19 */ + {51, 0, PMX_PICNT2_2, 137, 1}, /* P_GPIO19 */ + {51, 0, PMX_SB3_2_CK, 124, 1}, /* P_GPIO19 */ + {51, 0, PMX_SPI3_1_DO, 129, 1}, /* P_GPIO19 */ + {51, 0, PMX_SP_CLK_2, 138, 1}, /* P_GPIO19 */ + {52, 0, PMX_SPI3_1_DI, 139, 2}, /* P_GPIO20 */ + {52, 0, PMX_UART2_1_CTS, 133, 2}, /* P_GPIO20 */ + {52, 0, PMX_I2S_SDATAI_1, 125, 1}, /* P_GPIO20 */ + {52, 0, PMX_PICNT3_2, 141, 1}, /* P_GPIO20 */ + {52, 0, PMX_SB3_2_DAT, 124, 1}, /* P_GPIO20 */ + {53, 0, PMX_I2C3_1_SDA, 142, 1}, /* P_GPIO21 */ + {54, 0, PMX_I2C3_1_SCL, 142, 1}, /* P_GPIO22 */ + {55, 0, PMX_UART_TX, 143, 1}, /* P_GPIO23 */ + {56, 0, PMX_SP_CLK2_1, 132, 1}, /* P_GPIO24 */ + {56, 0, PMX_UART_RX, 143, 1}, /* P_GPIO24 */ + {64, 0, PMX_SENSOR_MCLK, 144, 1}, /* S_GPIO0 */ + {65, 0, PMX_SENSOR_MCLK2, 145, 2}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 147, 2}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 149, 2}, /* S_GPIO1 */ + {65, 0, PMX_PWM0_3, 151, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_12BITS, 152, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_CCIR8BITS, 153, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 154, 1}, /* S_GPIO1 */ + {66, 0, PMX_PWM1_3, 155, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_12BITS, 152, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_12BITS_2ND, 60, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_CCIR8BITS, 153, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_LVDS_VDHD, 156, 1}, /* S_GPIO2 */ + {67, 0, PMX_PWM2_3, 157, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_12BITS, 152, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_12BITS_2ND, 60, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_CCIR8BITS, 153, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_LVDS_VDHD, 156, 1}, /* S_GPIO3 */ + {68, 0, PMX_PWM3_3, 158, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR2_12BITS, 58, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR2_LVDS_VDHD, 159, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR_CCIR16BITS, 54, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR_CCIR8BITS, 153, 1}, /* S_GPIO4 */ + {68, 0, PMX_UART_CH3_4TH, 160, 1}, /* S_GPIO4 */ + {69, 0, PMX_PWM4_3, 161, 1}, /* S_GPIO5 */ + {69, 0, PMX_SENSOR2_12BITS, 58, 1}, /* S_GPIO5 */ + {69, 0, PMX_SENSOR2_LVDS_VDHD, 159, 1}, /* S_GPIO5 */ + {70, 0, PMX_PWM5_3, 162, 1}, /* S_GPIO6 */ + {70, 0, PMX_SB_CS, 163, 1}, /* S_GPIO6 */ + {70, 0, PMX_UART_CH3_4TH, 160, 1}, /* S_GPIO6 */ + {71, 0, PMX_I2C_SCL_1, 164, 1}, /* S_GPIO7 */ + {71, 0, PMX_PWM6_3, 165, 1}, /* S_GPIO7 */ + {71, 0, PMX_SB_CK, 163, 1}, /* S_GPIO7 */ + {72, 0, PMX_I2C_SDA_1, 164, 1}, /* S_GPIO8 */ + {72, 0, PMX_PWM7_3, 166, 1}, /* S_GPIO8 */ + {72, 0, PMX_SB_DAT, 163, 1}, /* S_GPIO8 */ + {73, 0, PMX_SB2_CS, 167, 1}, /* S_GPIO9 */ + {73, 0, PMX_SPI_2_CS, 168, 1}, /* S_GPIO9 */ + {74, 0, PMX_I2C2_1_SCL, 169, 1}, /* S_GPIO10 */ + {74, 0, PMX_SB2_CK, 167, 1}, /* S_GPIO10 */ + {74, 0, PMX_SPI_2_CLK, 168, 1}, /* S_GPIO10 */ + {75, 0, PMX_I2C2_1_SDA, 169, 1}, /* S_GPIO11 */ + {75, 0, PMX_SB2_DAT, 167, 1}, /* S_GPIO11 */ + {75, 0, PMX_SPI_2_DO, 168, 1}, /* S_GPIO11 */ + {76, 0, PMX_SPI_2_DI, 170, 2}, /* S_GPIO12 */ + {76, 0, PMX_SENSOR2_MCLK_2ND, 172, 1}, /* S_GPIO12 */ + {96, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO0 */ + {96, 0, PMX_PWM0_5, 221, 1}, /* L_GPIO0 */ + {96, 0, PMX_TXD0, 1, 0}, /* L_GPIO0 */ + {97, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO1 */ + {97, 0, PMX_PWM1_5, 222, 1}, /* L_GPIO1 */ + {97, 0, PMX_TXD1, 1, 0}, /* L_GPIO1 */ + {98, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO2 */ + {98, 0, PMX_PWM2_5, 229, 1}, /* L_GPIO2 */ + {98, 0, PMX_TX_EN, 1, 0}, /* L_GPIO2 */ + {99, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO3 */ + {99, 0, PMX_PWM3_5, 230, 1}, /* L_GPIO3 */ + {99, 0, PMX_RXD0, 1, 0}, /* L_GPIO3 */ + {100, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO4 */ + {100, 0, PMX_PWM4_5, 231, 1}, /* L_GPIO4 */ + {100, 0, PMX_RXD1, 1, 0}, /* L_GPIO4 */ + {101, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO5 */ + {101, 0, PMX_PWM5_5, 232, 1}, /* L_GPIO5 */ + {101, 0, PMX_CRS_DV, 1, 0}, /* L_GPIO5 */ + {102, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO6 */ + {102, 0, PMX_PWM6_5, 233, 1}, /* L_GPIO6 */ + {102, 0, PMX_RX_ER, 1, 0}, /* L_GPIO6 */ + {103, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO7 */ + {103, 0, PMX_ETH_PHYCLK, 234, 1}, /* L_GPIO7 */ + {103, 0, PMX_PWM7_5, 235, 1}, /* L_GPIO7 */ + {103, 0, PMX_ETH_PHYCLK, 1, 0}, /* L_GPIO7 */ + {104, 0, PMX_LCD_CCIR601, 173, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 176, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 179, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 182, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656, 185, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656, 188, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB888, 203, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB888, 206, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_6BITS, 223, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_6BITS, 226, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_8BITS, 215, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_8BITS, 218, 3}, /* L_GPIO8 */ + {104, 0, PMX_PWM8_5, 236, 1}, /* L_GPIO8 */ + {104, 0, PMX_REFCLK, 1, 0}, /* L_GPIO8 */ + {105, 0, PMX_LCD_NO_HVSYNC, 173, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 176, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 179, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 182, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 191, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 194, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 215, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 218, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 223, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 226, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 209, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 212, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 197, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 200, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 203, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 206, 3}, /* L_GPIO9 */ + {105, 0, PMX_PWM9_5, 237, 1}, /* L_GPIO9 */ + {105, 0, PMX_MDC, 1, 0}, /* L_GPIO9 */ + {106, 0, PMX_LCD_NO_HVSYNC, 173, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 176, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 179, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 182, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 191, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 194, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 215, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 218, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 223, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 226, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 209, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 212, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 197, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 200, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 203, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 206, 3}, /* L_GPIO10 */ + {106, 0, PMX_PWM10_5, 238, 1}, /* L_GPIO10 */ + {106, 0, PMX_MDIO, 1, 0}, /* L_GPIO10 */ + {107, 0, PMX_LCD_DE_ENABLE, 239, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 188, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 179, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 182, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 194, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 218, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 226, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 212, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 200, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 242, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 206, 3}, /* L_GPIO11 */ + {107, 0, PMX_PWM11_5, 245, 1}, /* L_GPIO11 */ + {108, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_HVLD_VVLD, 176, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_HVLD_VVLD, 182, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO12 */ + {109, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_HVLD_VVLD, 176, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_HVLD_VVLD, 182, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO13 */ + {110, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_FIELD, 176, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_FIELD, 182, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO14 */ + {111, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO15 */ + {112, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO16 */ + {113, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO17 */ + {114, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO18 */ + {115, 0, PMX_LCD_CCIR601_16BITS, 173, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR601_16BITS, 179, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR656_16BITS, 185, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR656_16BITS, 188, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB565, 191, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB565, 194, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_RGB_16BITS, 209, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_RGB_16BITS, 212, 3}, /* L_GPIO19 */ + {116, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO20 */ + {116, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO20 */ + {116, 0, PMX_SP_CLK_1, 128, 1}, /* L_GPIO20 */ + {117, 0, PMX_LCD_PARALLE_RGB666, 197, 3}, /* L_GPIO21 */ + {117, 0, PMX_LCD_PARALLE_RGB666, 200, 3}, /* L_GPIO21 */ + {118, 0, PMX_LCD_TE_ENABLE, 246, 4}, /* L_GPIO22 */ + {118, 0, PMX_SB3_1_CS, 250, 1}, /* L_GPIO22 */ + {119, 0, PMX_SB3_1_CK, 250, 1}, /* L_GPIO23 */ + {119, 0, PMX_SENSOR_SPCLK_2ND, 138, 1}, /* L_GPIO23 */ + {120, 0, PMX_SB3_1_DAT, 250, 1}, /* L_GPIO24 */ + {128, 0, PMX_ETH_PHYCLK, 251, 1}, /* D_GPIO0 */ + {129, 0, PMX_ETH_LED1, 251, 1}, /* D_GPIO1 */ + {130, 0, PMX_REMOTE_CH3, 252, 1}, /* D_GPIO2 */ + {131, 0, PMX_PWM4_4, 253, 1}, /* D_GPIO3 */ + {131, 0, PMX_SENSOR_SPCLK_3RD, 254, 1}, /* D_GPIO3 */ + {132, 0, PMX_PWM5_4, 255, 1}, /* D_GPIO4 */ + {132, 0, PMX_SP_CLK2_3, 256, 1}, /* D_GPIO4 */ + {133, 0, PMX_ETH_LED2, 257, 1}, /* D_GPIO5 */ + {133, 0, PMX_PWM6_4, 258, 1}, /* D_GPIO5 */ + {134, 0, PMX_ETH_LED2, 257, 1}, /* D_GPIO6 */ + {134, 0, PMX_PWM7_4, 259, 1}, /* D_GPIO6 */ + {135, 0, PMX_I2S_2_MCLK, 260, 1}, /* D_GPIO7 */ + {135, 0, PMX_PWM11_4, 261, 1}, /* D_GPIO7 */ + {136, 0, PMX_DMCLK_2, 262, 3}, /* D_GPIO8 */ + {136, 0, PMX_PWM8_4, 265, 1}, /* D_GPIO8 */ + {136, 0, PMX_SB3_3_CS, 266, 1}, /* D_GPIO8 */ + {137, 0, PMX_DMDAT0_2, 262, 3}, /* D_GPIO9 */ + {137, 0, PMX_PWM9_4, 267, 1}, /* D_GPIO9 */ + {137, 0, PMX_SB3_3_CK, 266, 1}, /* D_GPIO9 */ + {138, 0, PMX_DMDAT1_2, 262, 3}, /* D_GPIO10 */ + {138, 0, PMX_PWM10_4, 268, 1}, /* D_GPIO10 */ + {138, 0, PMX_SB3_3_DAT, 266, 1}, /* D_GPIO10 */ + {160, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO0 */ + {160, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO0 */ + {161, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO1 */ + {161, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO1 */ + {162, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO2 */ + {162, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO2 */ + {162, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO2 */ + {162, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO2 */ + {163, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO3 */ + {163, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO3 */ + {163, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO3 */ + {163, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO3 */ + {164, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO4 */ + {164, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO4 */ + {164, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO4 */ + {164, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO4 */ + {165, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO5 */ + {165, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO5 */ + {165, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO5 */ + {165, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO5 */ + {166, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO6 */ + {166, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO6 */ + {166, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO6 */ + {166, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO6 */ + {167, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO7 */ + {167, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO7 */ + {167, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO7 */ + {167, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO7 */ + {168, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO8 */ + {168, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO8 */ + {168, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO8 */ + {168, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO8 */ + {169, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO9 */ + {169, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 54, 1}, /* H_GPIO9 */ + {169, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 153, 1}, /* H_GPIO9 */ + {169, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO9 */ + {170, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO10 */ + {170, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO10 */ + {171, NVT_UNGATED, PMX_SENSOR_12BITS, 152, 1}, /* H_GPIO11 */ + {171, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO11 */ +}; + +/* The field each function's walk row shows: {pad, name, reg, + * shift, width, value}, reg NVT_GATE for the pad's gate bit. */ +static const novatek_sel_t NA51055_sels[] = { + {0, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {0, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {1, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {1, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {2, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {2, PMX_UART_CH3_5TH, 0x24, 4, 3, 5}, + {2, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {3, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {3, PMX_UART_CH3_5TH, 0x24, 4, 3, 5}, + {3, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {4, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {4, PMX_I2S_BCLK_2, 0x18, 0, 2, 2}, + {4, PMX_PWM0_4, 0x1C, 0, 3, 4}, + {4, PMX_UART_CH4_2ND, 0x24, 12, 2, 2}, + {5, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {5, PMX_I2S_SYNC_2, 0x18, 0, 2, 2}, + {5, PMX_PWM1_4, 0x1C, 3, 3, 4}, + {5, PMX_UART_CH4_2ND, 0x24, 12, 2, 2}, + {6, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {6, PMX_UART_CH4_CTSRTS, 0x24, 18, 2, 1}, + {6, PMX_UART_CH4_DIROE, 0x24, 18, 2, 2}, + {6, PMX_I2S_SDATAO_2, 0x18, 0, 2, 2}, + {6, PMX_PWM2_4, 0x1C, 6, 3, 4}, + {7, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {7, PMX_UART_CH4_CTSRTS, 0x24, 12, 2, 2}, + {7, PMX_I2S_SDATAI_2, 0x18, 0, 2, 2}, + {7, PMX_PWM3_4, 0x1C, 9, 3, 4}, + {8, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {8, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {9, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {9, PMX_SENSOR_SP2CLK_2ND, 0x18, 10, 2, 2}, + {10, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {11, PMX_DMCLK_3, 0x18, 5, 1, 1}, + {11, PMX_I2C3_2_SCL, 0x14, 6, 2, 2}, + {11, PMX_PWM4_2, 0x1C, 12, 3, 2}, + {11, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {11, PMX_SPI3_2_CLK, 0x14, 12, 2, 2}, + {12, PMX_DMDAT0_3, 0x18, 5, 1, 1}, + {12, PMX_I2C3_2_SDA, 0x14, 6, 2, 2}, + {12, PMX_PWM5_2, 0x1C, 15, 3, 2}, + {12, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {12, PMX_SPI3_2_DO, 0x14, 12, 2, 2}, + {13, PMX_DMDAT1_3, 0x18, 5, 1, 1}, + {13, PMX_UART2_2_CTS, 0x24, 2, 2, 2}, + {13, PMX_PWM0_2, 0x1C, 0, 3, 2}, + {13, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {13, PMX_SPI3_2_CS, 0x14, 12, 2, 2}, + {14, PMX_SPI3_2_DI, 0x14, 12, 2, 2}, + {14, PMX_UART2_2_RTS, 0x24, 2, 2, 2}, + {14, PMX_PWM1_2, 0x1C, 3, 3, 2}, + {14, PMX_REMOTE_IN_2, 0x18, 7, 2, 2}, + {14, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {15, PMX_SPI_CH3_RDY, 0x14, 12, 2, 2}, + {15, PMX_PWM2_2, 0x1C, 6, 3, 2}, + {15, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {15, PMX_UART2_2_TX, 0x24, 2, 2, 2}, + {16, PMX_PWM3_2, 0x1C, 9, 3, 2}, + {16, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {16, PMX_UART2_2_RX, 0x24, 2, 2, 2}, + {17, PMX_I2C2_2_SCL, 0x14, 4, 2, 2}, + {17, PMX_PWM6_2, 0x1C, 18, 3, 2}, + {17, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {17, PMX_SPI_1_CLK, 0x14, 8, 2, 1}, + {18, PMX_I2C2_2_SDA, 0x14, 4, 2, 2}, + {18, PMX_PWM7_2, 0x1C, 21, 3, 2}, + {18, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {18, PMX_SPI_1_DO, 0x14, 8, 2, 1}, + {19, PMX_UART3_2_CTS, 0x24, 4, 3, 2}, + {19, PMX_PWM8_2, 0x18, 16, 3, 2}, + {19, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {19, PMX_SPI_1_CS, 0x14, 8, 2, 1}, + {20, PMX_SPI_1_DI, 0x14, 8, 2, 1}, + {20, PMX_UART3_2_RTS, 0x24, 4, 3, 2}, + {20, PMX_PWM9_2, 0x18, 19, 3, 2}, + {20, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {21, PMX_PWM10_2, 0x18, 22, 3, 2}, + {21, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {21, PMX_UART3_2_TX, 0x24, 4, 3, 2}, + {22, PMX_PWM11_2, 0x18, 25, 3, 2}, + {22, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {22, PMX_UART3_2_RX, 0x24, 4, 3, 2}, + {32, PMX_PWM0_1, 0x1C, 0, 3, 1}, + {32, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {32, PMX_SPI2_2_CS, 0x14, 10, 2, 2}, + {32, PMX_UART2_3_TX, 0x24, 2, 2, 3}, + {32, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {32, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {32, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {33, PMX_PWM1_1, 0x1C, 3, 3, 1}, + {33, PMX_RTC_CLK, 0x18, 9, 1, 1}, + {33, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {33, PMX_SPI2_2_CLK, 0x14, 10, 2, 2}, + {33, PMX_UART2_3_RX, 0x24, 2, 2, 3}, + {33, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {33, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {33, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {34, PMX_UART2_3_RTS, 0x24, 2, 2, 3}, + {34, PMX_PWM2_1, 0x1C, 6, 3, 1}, + {34, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {34, PMX_SPI2_2_DO, 0x14, 10, 2, 2}, + {34, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {34, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {34, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {35, PMX_SPI2_2_DI, 0x14, 10, 2, 2}, + {35, PMX_UART2_3_CTS, 0x24, 2, 2, 3}, + {35, PMX_PWM3_1, 0x1C, 9, 3, 1}, + {35, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {35, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {35, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {35, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {36, PMX_PWM4_1, 0x1C, 12, 3, 1}, + {36, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {36, PMX_SPI3_3_CS, 0x14, 12, 2, 3}, + {36, PMX_UART3_3_TX, 0x24, 4, 3, 3}, + {36, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {36, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {36, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {37, PMX_PWM5_1, 0x1C, 15, 3, 1}, + {37, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {37, PMX_SPI3_3_CLK, 0x14, 12, 2, 3}, + {37, PMX_UART3_3_RX, 0x24, 4, 3, 3}, + {37, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {37, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {37, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {38, PMX_UART3_3_RTS, 0x24, 4, 3, 3}, + {38, PMX_PWM6_1, 0x1C, 18, 3, 1}, + {38, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {38, PMX_SPI3_3_DO, 0x14, 12, 2, 3}, + {38, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {38, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {38, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {39, PMX_DMDAT0_1, 0x18, 5, 1, 1}, + {39, PMX_SPI3_3_DI, 0x14, 12, 2, 3}, + {39, PMX_UART3_3_CTS, 0x24, 4, 3, 3}, + {39, PMX_PWM7_1, 0x1C, 21, 3, 1}, + {39, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {39, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {39, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {39, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {40, PMX_DMDAT1_1, 0x18, 5, 1, 1}, + {40, PMX_PWM8_1, 0x18, 16, 3, 1}, + {40, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {40, PMX_SPI_3_CS, 0x14, 8, 2, 3}, + {40, PMX_UART_CH6, 0x24, 16, 2, 1}, + {40, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {40, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {41, PMX_DMCLK_1, 0x18, 5, 1, 1}, + {41, PMX_PWM9_1, 0x18, 19, 3, 1}, + {41, PMX_SENSOR2_CCIR8BITS_VDHD, 0x0C, 4, 2, 2}, + {41, PMX_SPI_3_CLK, 0x14, 8, 2, 3}, + {41, PMX_UART_CH6, 0x24, 16, 2, 1}, + {41, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {41, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {41, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {42, PMX_UART_CH6_CTSRTS, 0x24, 22, 2, 1}, + {42, PMX_UART_CH6_DIROE, 0x24, 22, 2, 2}, + {42, PMX_PWM10_1, 0x18, 22, 3, 1}, + {42, PMX_SENSOR2_CCIR8BITS_VDHD, 0x0C, 4, 2, 2}, + {42, PMX_SPI_3_DO, 0x14, 8, 2, 3}, + {42, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {42, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {42, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {43, PMX_SPI_3_DI, 0x14, 8, 2, 3}, + {43, PMX_UART_CH6_CTSRTS, 0x24, 16, 2, 1}, + {43, PMX_PWM11_1, 0x18, 25, 3, 1}, + {43, PMX_SENSOR2_CCIR8BITS_FIELD, 0x0C, 4, 2, 2}, + {43, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {43, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {43, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {44, PMX_SENSOR2_SN3_MCLK, 0x0C, 16, 1, 1}, + {44, PMX_SPI_CH3_RDY, 0x14, 12, 2, 1}, + {44, PMX_PICNT_1, 0x1C, 26, 2, 1}, + {44, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {44, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {45, PMX_SB4_CS, 0x14, 26, 1, 1}, + {45, PMX_SPI2_1_CS, 0x14, 10, 2, 1}, + {45, PMX_UART3_1_TX, 0x24, 4, 3, 1}, + {46, PMX_PICNT2_1, 0x1C, 28, 2, 1}, + {46, PMX_SB4_CK, 0x14, 26, 1, 1}, + {46, PMX_SPI2_1_CLK, 0x14, 10, 2, 1}, + {46, PMX_UART3_1_RX, 0x24, 4, 3, 1}, + {47, PMX_UART3_1_RTS, 0x24, 4, 3, 1}, + {47, PMX_SB4_DAT, 0x14, 26, 1, 1}, + {47, PMX_SPI2_1_DO, 0x14, 10, 2, 1}, + {47, PMX_SP_CLK2_2, 0x18, 10, 2, 2}, + {48, PMX_SPI2_1_DI, 0x14, 10, 2, 1}, + {48, PMX_UART3_1_CTS, 0x24, 4, 3, 1}, + {48, PMX_I2S_1_MCLK, 0x18, 2, 2, 1}, + {48, PMX_SB3_2_CS, 0x14, 24, 2, 2}, + {49, PMX_I2S_BCLK_1, 0x18, 0, 2, 1}, + {49, PMX_PICNT3_1, 0x1C, 30, 2, 1}, + {49, PMX_REMOTE_IN_1, 0x18, 7, 2, 1}, + {49, PMX_SENSOR_SPCLK, 0x0C, 18, 2, 1}, + {49, PMX_SPI3_1_CS, 0x14, 12, 2, 1}, + {49, PMX_UART2_1_TX, 0x24, 2, 2, 1}, + {50, PMX_I2S_SYNC_1, 0x18, 0, 2, 1}, + {50, PMX_PICNT_2, 0x1C, 26, 2, 2}, + {50, PMX_SENSOR_SP2CLK, 0x18, 10, 2, 1}, + {50, PMX_SPI3_1_CLK, 0x14, 12, 2, 1}, + {50, PMX_UART2_1_RX, 0x24, 2, 2, 1}, + {51, PMX_UART2_1_RTS, 0x24, 2, 2, 1}, + {51, PMX_I2S_SDATAO_1, 0x18, 0, 2, 1}, + {51, PMX_PICNT2_2, 0x1C, 28, 2, 2}, + {51, PMX_SB3_2_CK, 0x14, 24, 2, 2}, + {51, PMX_SPI3_1_DO, 0x14, 12, 2, 1}, + {51, PMX_SP_CLK_2, 0x0C, 18, 2, 2}, + {52, PMX_SPI3_1_DI, 0x14, 12, 2, 1}, + {52, PMX_UART2_1_CTS, 0x24, 2, 2, 1}, + {52, PMX_I2S_SDATAI_1, 0x18, 0, 2, 1}, + {52, PMX_PICNT3_2, 0x1C, 30, 2, 2}, + {52, PMX_SB3_2_DAT, 0x14, 24, 2, 2}, + {53, PMX_I2C3_1_SDA, 0x14, 6, 2, 1}, + {54, PMX_I2C3_1_SCL, 0x14, 6, 2, 1}, + {55, PMX_UART_TX, 0x24, 0, 1, 1}, + {56, PMX_SP_CLK2_1, 0x18, 10, 2, 1}, + {56, PMX_UART_RX, 0x24, 0, 1, 1}, + {64, PMX_SENSOR_MCLK, 0x0C, 8, 2, 1}, + {65, PMX_SENSOR_MCLK2, 0x0C, 12, 2, 1}, + {65, PMX_PWM0_3, 0x1C, 0, 3, 3}, + {65, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {65, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {65, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {66, PMX_PWM1_3, 0x1C, 3, 3, 3}, + {66, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {66, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {66, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {66, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {66, PMX_SENSOR_LVDS_VDHD, 0x0C, 10, 1, 1}, + {67, PMX_PWM2_3, 0x1C, 6, 3, 3}, + {67, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {67, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {67, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {67, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {67, PMX_SENSOR_LVDS_VDHD, 0x0C, 10, 1, 1}, + {68, PMX_PWM3_3, 0x1C, 9, 3, 3}, + {68, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {68, PMX_SENSOR2_LVDS_VDHD, 0x0C, 14, 1, 1}, + {68, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {68, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {68, PMX_UART_CH3_4TH, 0x24, 4, 3, 4}, + {69, PMX_PWM4_3, 0x1C, 12, 3, 3}, + {69, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {69, PMX_SENSOR2_LVDS_VDHD, 0x0C, 14, 1, 1}, + {70, PMX_PWM5_3, 0x1C, 15, 3, 3}, + {70, PMX_SB_CS, 0x14, 20, 1, 1}, + {70, PMX_UART_CH3_4TH, 0x24, 4, 3, 4}, + {71, PMX_I2C_SCL_1, 0x14, 0, 2, 1}, + {71, PMX_PWM6_3, 0x1C, 18, 3, 3}, + {71, PMX_SB_CK, 0x14, 20, 1, 1}, + {72, PMX_I2C_SDA_1, 0x14, 0, 2, 1}, + {72, PMX_PWM7_3, 0x1C, 21, 3, 3}, + {72, PMX_SB_DAT, 0x14, 20, 1, 1}, + {73, PMX_SB2_CS, 0x14, 22, 1, 1}, + {73, PMX_SPI_2_CS, 0x14, 8, 2, 2}, + {74, PMX_I2C2_1_SCL, 0x14, 4, 2, 1}, + {74, PMX_SB2_CK, 0x14, 22, 1, 1}, + {74, PMX_SPI_2_CLK, 0x14, 8, 2, 2}, + {75, PMX_I2C2_1_SDA, 0x14, 4, 2, 1}, + {75, PMX_SB2_DAT, 0x14, 22, 1, 1}, + {75, PMX_SPI_2_DO, 0x14, 8, 2, 2}, + {76, PMX_SPI_2_DI, 0x14, 8, 2, 2}, + {76, PMX_SENSOR2_MCLK_2ND, 0x0C, 12, 2, 2}, + {96, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {96, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {96, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {96, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {96, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {96, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {96, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {96, PMX_PWM0_5, 0x1C, 0, 3, 5}, + {96, PMX_TXD0, NVT_GATE, 0, 0, 0}, + {97, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {97, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {97, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {97, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {97, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {97, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {97, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {97, PMX_PWM1_5, 0x1C, 3, 3, 5}, + {97, PMX_TXD1, NVT_GATE, 0, 0, 0}, + {98, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {98, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {98, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {98, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {98, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {98, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {98, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {98, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {98, PMX_PWM2_5, 0x1C, 6, 3, 5}, + {98, PMX_TX_EN, NVT_GATE, 0, 0, 0}, + {99, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {99, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {99, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {99, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {99, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {99, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {99, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {99, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {99, PMX_PWM3_5, 0x1C, 9, 3, 5}, + {99, PMX_RXD0, NVT_GATE, 0, 0, 0}, + {100, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {100, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {100, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {100, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {100, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {100, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {100, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {100, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {100, PMX_PWM4_5, 0x1C, 12, 3, 5}, + {100, PMX_RXD1, NVT_GATE, 0, 0, 0}, + {101, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {101, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {101, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {101, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {101, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {101, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {101, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {101, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {101, PMX_PWM5_5, 0x1C, 15, 3, 5}, + {101, PMX_CRS_DV, NVT_GATE, 0, 0, 0}, + {102, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {102, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {102, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {102, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {102, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {102, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {102, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {102, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {102, PMX_PWM6_5, 0x1C, 18, 3, 5}, + {102, PMX_RX_ER, NVT_GATE, 0, 0, 0}, + {103, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {103, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {103, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {103, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {103, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {103, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {103, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {103, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {103, PMX_ETH_PHYCLK, 0x18, 28, 1, 1}, + {103, PMX_PWM7_5, 0x1C, 21, 3, 5}, + {104, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {104, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {104, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {104, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {104, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {104, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {104, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {104, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {104, PMX_PWM8_5, 0x18, 16, 3, 5}, + {104, PMX_REFCLK, NVT_GATE, 0, 0, 0}, + {105, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, + {105, PMX_PWM9_5, 0x18, 19, 3, 5}, + {105, PMX_MDC, NVT_GATE, 0, 0, 0}, + {106, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, + {106, PMX_PWM10_5, 0x18, 22, 3, 5}, + {106, PMX_MDIO, NVT_GATE, 0, 0, 0}, + {107, PMX_LCD_DE_ENABLE, 0x08, 6, 1, 1}, + {107, PMX_PWM11_5, 0x18, 25, 3, 5}, + {108, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {108, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {108, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {108, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {108, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {108, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {109, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {109, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {109, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {109, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {109, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {109, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {110, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {110, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {110, PMX_LCD_FIELD, 0x08, 8, 1, 1}, + {110, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {110, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {110, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {111, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {111, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {111, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {111, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {111, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {112, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {112, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {112, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {112, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {112, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {113, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {113, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {113, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {113, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {113, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {114, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {114, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {114, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {114, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {114, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {115, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {115, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {115, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {115, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {115, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {116, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {116, PMX_SP_CLK_1, 0x0C, 18, 2, 1}, + {117, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {118, PMX_LCD_TE_ENABLE, 0x08, 0, 4, 9}, + {118, PMX_SB3_1_CS, 0x14, 24, 2, 1}, + {119, PMX_SB3_1_CK, 0x14, 24, 2, 1}, + {119, PMX_SENSOR_SPCLK_2ND, 0x0C, 18, 2, 2}, + {120, PMX_SB3_1_DAT, 0x14, 24, 2, 1}, + {128, PMX_ETH_PHYCLK, 0x18, 13, 2, 1}, + {129, PMX_ETH_LED1, 0x18, 13, 2, 1}, + {130, PMX_REMOTE_CH3, 0x18, 7, 2, 3}, + {131, PMX_PWM4_4, 0x1C, 12, 3, 4}, + {131, PMX_SENSOR_SPCLK_3RD, 0x0C, 18, 2, 3}, + {132, PMX_PWM5_4, 0x1C, 15, 3, 4}, + {132, PMX_SP_CLK2_3, 0x18, 10, 2, 3}, + {133, PMX_ETH_LED2, 0x18, 13, 2, 2}, + {133, PMX_PWM6_4, 0x1C, 18, 3, 4}, + {134, PMX_ETH_LED2, 0x18, 13, 2, 2}, + {134, PMX_PWM7_4, 0x1C, 21, 3, 4}, + {135, PMX_I2S_2_MCLK, 0x18, 2, 2, 2}, + {135, PMX_PWM11_4, 0x18, 25, 3, 4}, + {136, PMX_DMCLK_2, 0x18, 5, 1, 1}, + {136, PMX_PWM8_4, 0x18, 16, 3, 4}, + {136, PMX_SB3_3_CS, 0x14, 24, 2, 3}, + {137, PMX_DMDAT0_2, 0x18, 5, 1, 1}, + {137, PMX_PWM9_4, 0x18, 19, 3, 4}, + {137, PMX_SB3_3_CK, 0x14, 24, 2, 3}, + {138, PMX_DMDAT1_2, 0x18, 5, 1, 1}, + {138, PMX_PWM10_4, 0x18, 22, 3, 4}, + {138, PMX_SB3_3_DAT, 0x14, 24, 2, 3}, + {160, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {160, PMX_MIPI_LVDS_DAT0, NVT_GATE, 0, 0, 0}, + {161, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {161, PMX_MIPI_LVDS_DAT0, NVT_GATE, 0, 0, 0}, + {162, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {162, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {162, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {162, PMX_MIPI_LVDS_DAT1, NVT_GATE, 0, 0, 0}, + {163, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {163, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {163, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {163, PMX_MIPI_LVDS_DAT1, NVT_GATE, 0, 0, 0}, + {164, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {164, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {164, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {164, PMX_MIPI_LVDS_CLK0, NVT_GATE, 0, 0, 0}, + {165, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {165, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {165, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {165, PMX_MIPI_LVDS_CLK0, NVT_GATE, 0, 0, 0}, + {166, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {166, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {166, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {166, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, + {167, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {167, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {167, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {167, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, + {168, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {168, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {168, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {168, PMX_MIPI_LVDS_DAT3, NVT_GATE, 0, 0, 0}, + {169, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {169, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {169, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {169, PMX_MIPI_LVDS_DAT3, NVT_GATE, 0, 0, 0}, + {170, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {170, PMX_MIPI_LVDS_CLK1, NVT_GATE, 0, 0, 0}, + {171, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {171, PMX_MIPI_LVDS_CLK1, NVT_GATE, 0, 0, 0}, +}; + +static const novatek_soc_t NA51055_padmux = { + NA51055_pads, 113, NA51055_claims, 665, NA51055_conds, + NA51055_sels, 471, +}; + +/* NA51084: 81229 vendor states replayed; in 27520 of them two claims hold + * at once and the table carries the one the vendor code meant, + * and 408 leave a pad cleared with its field moved elsewhere, + * which reads as unnamed. */ + +/* Every pad the package bonds out, by Linux GPIO number. */ +static const novatek_pad_t NA51084_pads[] = { + {0, PMX_C_GPIO0}, + {1, PMX_C_GPIO1}, + {2, PMX_C_GPIO2}, + {3, PMX_C_GPIO3}, + {4, PMX_C_GPIO4}, + {5, PMX_C_GPIO5}, + {6, PMX_C_GPIO6}, + {7, PMX_C_GPIO7}, + {8, PMX_C_GPIO8}, + {9, PMX_C_GPIO9}, + {10, PMX_C_GPIO10}, + {11, PMX_C_GPIO11}, + {12, PMX_C_GPIO12}, + {13, PMX_C_GPIO13}, + {14, PMX_C_GPIO14}, + {15, PMX_C_GPIO15}, + {16, PMX_C_GPIO16}, + {17, PMX_C_GPIO17}, + {18, PMX_C_GPIO18}, + {19, PMX_C_GPIO19}, + {20, PMX_C_GPIO20}, + {21, PMX_C_GPIO21}, + {22, PMX_C_GPIO22}, + {32, PMX_P_GPIO0}, + {33, PMX_P_GPIO1}, + {34, PMX_P_GPIO2}, + {35, PMX_P_GPIO3}, + {36, PMX_P_GPIO4}, + {37, PMX_P_GPIO5}, + {38, PMX_P_GPIO6}, + {39, PMX_P_GPIO7}, + {40, PMX_P_GPIO8}, + {41, PMX_P_GPIO9}, + {42, PMX_P_GPIO10}, + {43, PMX_P_GPIO11}, + {44, PMX_P_GPIO12}, + {45, PMX_P_GPIO13}, + {46, PMX_P_GPIO14}, + {47, PMX_P_GPIO15}, + {48, PMX_P_GPIO16}, + {49, PMX_P_GPIO17}, + {50, PMX_P_GPIO18}, + {51, PMX_P_GPIO19}, + {52, PMX_P_GPIO20}, + {53, PMX_P_GPIO21}, + {54, PMX_P_GPIO22}, + {55, PMX_P_GPIO23}, + {56, PMX_P_GPIO24}, + {57, PMX_P_GPIO25}, + {64, PMX_S_GPIO0}, + {65, PMX_S_GPIO1}, + {66, PMX_S_GPIO2}, + {67, PMX_S_GPIO3}, + {68, PMX_S_GPIO4}, + {69, PMX_S_GPIO5}, + {70, PMX_S_GPIO6}, + {71, PMX_S_GPIO7}, + {72, PMX_S_GPIO8}, + {73, PMX_S_GPIO9}, + {74, PMX_S_GPIO10}, + {75, PMX_S_GPIO11}, + {76, PMX_S_GPIO12}, + {96, PMX_L_GPIO0}, + {97, PMX_L_GPIO1}, + {98, PMX_L_GPIO2}, + {99, PMX_L_GPIO3}, + {100, PMX_L_GPIO4}, + {101, PMX_L_GPIO5}, + {102, PMX_L_GPIO6}, + {103, PMX_L_GPIO7}, + {104, PMX_L_GPIO8}, + {105, PMX_L_GPIO9}, + {106, PMX_L_GPIO10}, + {107, PMX_L_GPIO11}, + {108, PMX_L_GPIO12}, + {109, PMX_L_GPIO13}, + {110, PMX_L_GPIO14}, + {111, PMX_L_GPIO15}, + {112, PMX_L_GPIO16}, + {113, PMX_L_GPIO17}, + {114, PMX_L_GPIO18}, + {115, PMX_L_GPIO19}, + {116, PMX_L_GPIO20}, + {117, PMX_L_GPIO21}, + {118, PMX_L_GPIO22}, + {119, PMX_L_GPIO23}, + {120, PMX_L_GPIO24}, + {128, PMX_D_GPIO0}, + {129, PMX_D_GPIO1}, + {130, PMX_D_GPIO2}, + {131, PMX_D_GPIO3}, + {132, PMX_D_GPIO4}, + {133, PMX_D_GPIO5}, + {134, PMX_D_GPIO6}, + {135, PMX_D_GPIO7}, + {136, PMX_D_GPIO8}, + {137, PMX_D_GPIO9}, + {138, PMX_D_GPIO10}, + {160, PMX_H_GPIO0}, + {161, PMX_H_GPIO1}, + {162, PMX_H_GPIO2}, + {163, PMX_H_GPIO3}, + {164, PMX_H_GPIO4}, + {165, PMX_H_GPIO5}, + {166, PMX_H_GPIO6}, + {167, PMX_H_GPIO7}, + {168, PMX_H_GPIO8}, + {169, PMX_H_GPIO9}, + {170, PMX_H_GPIO10}, + {171, PMX_H_GPIO11}, + {192, PMX_A_GPIO0}, + {193, PMX_A_GPIO1}, + {194, PMX_A_GPIO2}, +}; + +/* TOP register offset, field shift, width, value. */ +static const novatek_cond_t NA51084_conds[] = { + {0x04, 17, 1, 1}, + {0x24, 4, 3, 5}, + {0x04, 17, 1, 1}, + {0x04, 31, 1, 1}, + {0x18, 0, 2, 2}, + {0x1C, 0, 3, 4}, + {0x10, 2, 2, 2}, + {0x24, 12, 2, 2}, + {0x1C, 3, 3, 4}, + {0x24, 12, 2, 2}, + {0x24, 18, 2, 1}, + {0x24, 12, 2, 2}, + {0x24, 18, 2, 2}, + {0x14, 2, 2, 2}, + {0x1C, 6, 3, 4}, + {0x10, 2, 2, 2}, + {0x10, 6, 1, 1}, + {0x1C, 9, 3, 4}, + {0x18, 10, 2, 2}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 3}, + {0x14, 6, 2, 2}, + {0x1C, 12, 3, 2}, + {0x04, 14, 1, 1}, + {0x14, 12, 2, 2}, + {0x1C, 15, 3, 2}, + {0x24, 2, 2, 2}, + {0x24, 8, 2, 1}, + {0x1C, 0, 3, 2}, + {0x14, 12, 2, 2}, + {0x14, 18, 1, 1}, + {0x24, 2, 2, 2}, + {0x24, 8, 2, 2}, + {0x1C, 3, 3, 2}, + {0x18, 7, 2, 2}, + {0x14, 12, 2, 2}, + {0x14, 14, 2, 2}, + {0x1C, 6, 3, 2}, + {0x24, 2, 2, 2}, + {0x1C, 9, 3, 2}, + {0x14, 4, 2, 2}, + {0x1C, 18, 3, 2}, + {0x04, 15, 1, 1}, + {0x14, 8, 2, 1}, + {0x1C, 21, 3, 2}, + {0x24, 4, 3, 2}, + {0x24, 10, 2, 1}, + {0x18, 16, 3, 2}, + {0x14, 8, 2, 1}, + {0x14, 16, 1, 1}, + {0x24, 4, 3, 2}, + {0x24, 10, 2, 2}, + {0x18, 19, 3, 2}, + {0x18, 22, 3, 2}, + {0x24, 4, 3, 2}, + {0x18, 25, 3, 2}, + {0x1C, 0, 3, 1}, + {0x0C, 0, 3, 4}, + {0x10, 2, 2, 1}, + {0x24, 12, 2, 1}, + {0x0C, 4, 2, 1}, + {0x0C, 4, 2, 2}, + {0x0C, 0, 3, 2}, + {0x1C, 3, 3, 1}, + {0x18, 9, 1, 1}, + {0x24, 12, 2, 1}, + {0x24, 18, 2, 1}, + {0x24, 12, 2, 1}, + {0x24, 18, 2, 2}, + {0x10, 0, 2, 1}, + {0x1C, 6, 3, 1}, + {0x10, 2, 2, 1}, + {0x10, 6, 1, 1}, + {0x1C, 9, 3, 1}, + {0x1C, 12, 3, 1}, + {0x10, 4, 2, 1}, + {0x24, 14, 2, 1}, + {0x1C, 15, 3, 1}, + {0x24, 14, 2, 1}, + {0x24, 20, 2, 1}, + {0x24, 14, 2, 1}, + {0x24, 20, 2, 2}, + {0x1C, 18, 3, 1}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 1}, + {0x10, 4, 2, 1}, + {0x10, 7, 1, 1}, + {0x1C, 21, 3, 1}, + {0x18, 16, 3, 1}, + {0x14, 8, 2, 3}, + {0x24, 16, 2, 1}, + {0x18, 19, 3, 1}, + {0x24, 16, 2, 1}, + {0x24, 22, 2, 1}, + {0x24, 16, 2, 1}, + {0x24, 22, 2, 2}, + {0x18, 22, 3, 1}, + {0x14, 8, 2, 3}, + {0x14, 16, 1, 1}, + {0x14, 2, 2, 1}, + {0x18, 25, 3, 1}, + {0x0C, 4, 2, 1}, + {0x0C, 16, 1, 1}, + {0x14, 12, 2, 1}, + {0x14, 14, 2, 1}, + {0x1C, 26, 2, 1}, + {0x0C, 16, 1, 1}, + {0x14, 26, 1, 1}, + {0x14, 10, 2, 1}, + {0x24, 4, 3, 1}, + {0x1C, 28, 2, 1}, + {0x24, 4, 3, 1}, + {0x24, 10, 2, 1}, + {0x24, 4, 3, 1}, + {0x24, 10, 2, 2}, + {0x14, 10, 2, 1}, + {0x14, 17, 1, 1}, + {0x18, 2, 2, 1}, + {0x14, 24, 2, 2}, + {0x18, 0, 2, 1}, + {0x1C, 30, 2, 1}, + {0x18, 7, 2, 1}, + {0x0C, 18, 2, 1}, + {0x14, 12, 2, 1}, + {0x24, 2, 2, 1}, + {0x1C, 26, 2, 2}, + {0x18, 10, 2, 1}, + {0x24, 2, 2, 1}, + {0x24, 8, 2, 1}, + {0x24, 2, 2, 1}, + {0x24, 8, 2, 2}, + {0x1C, 28, 2, 2}, + {0x0C, 18, 2, 2}, + {0x14, 12, 2, 1}, + {0x14, 18, 1, 1}, + {0x1C, 30, 2, 2}, + {0x14, 6, 2, 1}, + {0x24, 0, 1, 1}, + {0x0C, 8, 2, 1}, + {0x0C, 0, 3, 1}, + {0x0C, 12, 2, 1}, + {0x0C, 0, 3, 3}, + {0x0C, 12, 2, 1}, + {0x0C, 0, 3, 4}, + {0x0C, 12, 2, 1}, + {0x1C, 0, 3, 3}, + {0x0C, 0, 3, 1}, + {0x0C, 0, 3, 3}, + {0x0C, 12, 2, 1}, + {0x1C, 3, 3, 3}, + {0x0C, 10, 1, 1}, + {0x1C, 6, 3, 3}, + {0x1C, 9, 3, 3}, + {0x0C, 14, 1, 1}, + {0x24, 4, 3, 4}, + {0x1C, 12, 3, 3}, + {0x1C, 15, 3, 3}, + {0x14, 20, 1, 1}, + {0x14, 0, 2, 1}, + {0x1C, 18, 3, 3}, + {0x1C, 21, 3, 3}, + {0x14, 22, 1, 1}, + {0x14, 8, 2, 2}, + {0x14, 4, 2, 1}, + {0x14, 8, 2, 2}, + {0x14, 16, 1, 1}, + {0x0C, 12, 2, 2}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 2}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 1}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 1}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 3}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 8}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 8}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 10}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 7}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 4}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x1C, 0, 3, 5}, + {0x1C, 3, 3, 5}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 5}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x1C, 6, 3, 5}, + {0x1C, 9, 3, 5}, + {0x1C, 12, 3, 5}, + {0x1C, 15, 3, 5}, + {0x1C, 18, 3, 5}, + {0x18, 28, 1, 1}, + {0x1C, 21, 3, 5}, + {0x18, 16, 3, 5}, + {0x18, 19, 3, 5}, + {0x18, 22, 3, 5}, + {0x08, 0, 4, 0}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 1}, + {0x08, 8, 1, 0}, + {0x18, 25, 3, 5}, + {0x10, 8, 2, 3}, + {0x10, 8, 2, 2}, + {0x08, 0, 4, 9}, + {0x08, 6, 1, 0}, + {0x08, 8, 1, 0}, + {0x08, 10, 1, 1}, + {0x14, 24, 2, 1}, + {0x10, 8, 2, 2}, + {0x18, 28, 1, 1}, + {0x10, 8, 2, 3}, + {0x18, 28, 1, 1}, + {0x18, 13, 2, 1}, + {0x18, 7, 2, 3}, + {0x1C, 12, 3, 4}, + {0x0C, 18, 2, 3}, + {0x1C, 15, 3, 4}, + {0x18, 10, 2, 3}, + {0x18, 13, 2, 2}, + {0x1C, 18, 3, 4}, + {0x1C, 21, 3, 4}, + {0x18, 2, 2, 2}, + {0x18, 25, 3, 4}, + {0x18, 5, 1, 1}, + {0x18, 6, 1, 1}, + {0x18, 30, 2, 2}, + {0x18, 16, 3, 4}, + {0x14, 24, 2, 3}, + {0x18, 19, 3, 4}, + {0x18, 22, 3, 4}, +}; + +/* Per pad, most conditions first: the first claim that holds + * is what the pad carries. {pad, flags, name, first + * condition, how many}. */ +static const novatek_claim_t NA51084_claims[] = { + {0, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO0 */ + {0, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO0 */ + {1, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO1 */ + {1, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO1 */ + {2, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO2 */ + {2, 0, PMX_UART_CH3_5TH, 1, 1}, /* C_GPIO2 */ + {2, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO2 */ + {3, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO3 */ + {3, 0, PMX_UART_CH3_5TH, 1, 1}, /* C_GPIO3 */ + {3, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO3 */ + {4, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO4 */ + {4, 0, PMX_I2S_BCLK_2, 4, 1}, /* C_GPIO4 */ + {4, 0, PMX_PWM0_4, 5, 1}, /* C_GPIO4 */ + {4, 0, PMX_SPI4_2_CS, 6, 1}, /* C_GPIO4 */ + {4, 0, PMX_UART_CH4_2ND, 7, 1}, /* C_GPIO4 */ + {5, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO5 */ + {5, 0, PMX_I2S_SYNC_2, 4, 1}, /* C_GPIO5 */ + {5, 0, PMX_PWM1_4, 8, 1}, /* C_GPIO5 */ + {5, 0, PMX_SPI4_2_CLK, 6, 1}, /* C_GPIO5 */ + {5, 0, PMX_UART_CH4_2ND, 7, 1}, /* C_GPIO5 */ + {6, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO6 */ + {6, 0, PMX_UART_CH4_CTSRTS, 9, 2}, /* C_GPIO6 */ + {6, 0, PMX_UART_CH4_DIROE, 11, 2}, /* C_GPIO6 */ + {6, 0, PMX_I2C4_2_SCL, 13, 1}, /* C_GPIO6 */ + {6, 0, PMX_I2S_SDATAO_2, 4, 1}, /* C_GPIO6 */ + {6, 0, PMX_PWM2_4, 14, 1}, /* C_GPIO6 */ + {6, 0, PMX_SPI4_2_DO, 6, 1}, /* C_GPIO6 */ + {7, 0, PMX_SDIO_8BITS, 2, 2}, /* C_GPIO7 */ + {7, 0, PMX_SPI4_2_DI, 15, 2}, /* C_GPIO7 */ + {7, 0, PMX_UART_CH4_CTSRTS, 9, 2}, /* C_GPIO7 */ + {7, 0, PMX_I2C4_2_SDA, 13, 1}, /* C_GPIO7 */ + {7, 0, PMX_I2S_SDATAI_2, 4, 1}, /* C_GPIO7 */ + {7, 0, PMX_PWM3_4, 17, 1}, /* C_GPIO7 */ + {8, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO8 */ + {8, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO8 */ + {9, 0, PMX_SDIO_4BITS, 0, 1}, /* C_GPIO9 */ + {9, 0, PMX_SENSOR_SP2CLK_2ND, 18, 1}, /* C_GPIO9 */ + {10, 0, PMX_NAND_1CS, 1, 0}, /* C_GPIO10 */ + {11, 0, PMX_DMCLK_3, 19, 3}, /* C_GPIO11 */ + {11, 0, PMX_I2C3_2_SCL, 22, 1}, /* C_GPIO11 */ + {11, 0, PMX_PWM4_2, 23, 1}, /* C_GPIO11 */ + {11, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO11 */ + {11, 0, PMX_SPI3_2_CLK, 25, 1}, /* C_GPIO11 */ + {12, 0, PMX_DMDAT0_3, 19, 3}, /* C_GPIO12 */ + {12, 0, PMX_I2C3_2_SDA, 22, 1}, /* C_GPIO12 */ + {12, 0, PMX_PWM5_2, 26, 1}, /* C_GPIO12 */ + {12, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO12 */ + {12, 0, PMX_SPI3_2_DO, 25, 1}, /* C_GPIO12 */ + {13, 0, PMX_DMDAT1_3, 19, 3}, /* C_GPIO13 */ + {13, 0, PMX_UART2_2_CTS, 27, 2}, /* C_GPIO13 */ + {13, 0, PMX_PWM0_2, 29, 1}, /* C_GPIO13 */ + {13, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO13 */ + {13, 0, PMX_SPI3_2_CS, 25, 1}, /* C_GPIO13 */ + {14, 0, PMX_SPI3_2_DI, 30, 2}, /* C_GPIO14 */ + {14, 0, PMX_UART2_2_RTS, 27, 2}, /* C_GPIO14 */ + {14, 0, PMX_UART2_2_RTS, 32, 2}, /* C_GPIO14 */ + {14, 0, PMX_PWM1_2, 34, 1}, /* C_GPIO14 */ + {14, 0, PMX_REMOTE_IN_2, 35, 1}, /* C_GPIO14 */ + {14, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO14 */ + {15, 0, PMX_SPI_CH3_RDY, 36, 2}, /* C_GPIO15 */ + {15, 0, PMX_PWM2_2, 38, 1}, /* C_GPIO15 */ + {15, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO15 */ + {15, 0, PMX_UART2_2_TX, 39, 1}, /* C_GPIO15 */ + {16, 0, PMX_PWM3_2, 40, 1}, /* C_GPIO16 */ + {16, 0, PMX_SDIO_4BITS, 24, 1}, /* C_GPIO16 */ + {16, 0, PMX_UART2_2_RX, 39, 1}, /* C_GPIO16 */ + {17, 0, PMX_I2C2_2_SCL, 41, 1}, /* C_GPIO17 */ + {17, 0, PMX_PWM6_2, 42, 1}, /* C_GPIO17 */ + {17, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO17 */ + {17, 0, PMX_SPI_1_CLK, 44, 1}, /* C_GPIO17 */ + {18, 0, PMX_I2C2_2_SDA, 41, 1}, /* C_GPIO18 */ + {18, 0, PMX_PWM7_2, 45, 1}, /* C_GPIO18 */ + {18, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO18 */ + {18, 0, PMX_SPI_1_DO, 44, 1}, /* C_GPIO18 */ + {19, 0, PMX_UART3_2_CTS, 46, 2}, /* C_GPIO19 */ + {19, 0, PMX_PWM8_2, 48, 1}, /* C_GPIO19 */ + {19, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO19 */ + {19, 0, PMX_SPI_1_CS, 44, 1}, /* C_GPIO19 */ + {20, 0, PMX_SPI_1_DI, 49, 2}, /* C_GPIO20 */ + {20, 0, PMX_UART3_2_RTS, 46, 2}, /* C_GPIO20 */ + {20, 0, PMX_UART3_2_RTS, 51, 2}, /* C_GPIO20 */ + {20, 0, PMX_PWM9_2, 53, 1}, /* C_GPIO20 */ + {20, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO20 */ + {21, 0, PMX_PWM10_2, 54, 1}, /* C_GPIO21 */ + {21, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO21 */ + {21, 0, PMX_UART3_2_TX, 55, 1}, /* C_GPIO21 */ + {22, 0, PMX_PWM11_2, 56, 1}, /* C_GPIO22 */ + {22, 0, PMX_SDIO_4BITS, 43, 1}, /* C_GPIO22 */ + {22, 0, PMX_UART3_2_RX, 55, 1}, /* C_GPIO22 */ + {32, 0, PMX_PWM0_1, 57, 1}, /* P_GPIO0 */ + {32, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO0 */ + {32, 0, PMX_SPI4_1_CS, 59, 1}, /* P_GPIO0 */ + {32, 0, PMX_UART2_3_TX, 60, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO0 */ + {32, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO0 */ + {33, 0, PMX_PWM1_1, 64, 1}, /* P_GPIO1 */ + {33, 0, PMX_RTC_CLK, 65, 1}, /* P_GPIO1 */ + {33, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO1 */ + {33, 0, PMX_SPI4_1_CLK, 59, 1}, /* P_GPIO1 */ + {33, 0, PMX_UART2_3_RX, 60, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO1 */ + {33, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO1 */ + {34, 0, PMX_UART2_3_RTS, 66, 2}, /* P_GPIO2 */ + {34, 0, PMX_UART2_3_RTS, 68, 2}, /* P_GPIO2 */ + {34, 0, PMX_I2C5_1_SCL, 70, 1}, /* P_GPIO2 */ + {34, 0, PMX_PWM2_1, 71, 1}, /* P_GPIO2 */ + {34, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO2 */ + {34, 0, PMX_SPI4_1_DO, 59, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO2 */ + {34, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO2 */ + {35, 0, PMX_SPI4_1_DI, 72, 2}, /* P_GPIO3 */ + {35, 0, PMX_UART2_3_CTS, 66, 2}, /* P_GPIO3 */ + {35, 0, PMX_I2C5_1_SDA, 70, 1}, /* P_GPIO3 */ + {35, 0, PMX_PWM3_1, 74, 1}, /* P_GPIO3 */ + {35, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO3 */ + {35, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO3 */ + {36, 0, PMX_PWM4_1, 75, 1}, /* P_GPIO4 */ + {36, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO4 */ + {36, 0, PMX_SPI5_1_CS, 76, 1}, /* P_GPIO4 */ + {36, 0, PMX_UART3_3_TX, 77, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO4 */ + {36, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO4 */ + {37, 0, PMX_PWM5_1, 78, 1}, /* P_GPIO5 */ + {37, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO5 */ + {37, 0, PMX_SPI5_1_CLK, 76, 1}, /* P_GPIO5 */ + {37, 0, PMX_UART3_3_RX, 77, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO5 */ + {37, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO5 */ + {38, 0, PMX_UART3_3_RTS, 79, 2}, /* P_GPIO6 */ + {38, 0, PMX_UART3_3_RTS, 81, 2}, /* P_GPIO6 */ + {38, 0, PMX_PWM6_1, 83, 1}, /* P_GPIO6 */ + {38, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO6 */ + {38, 0, PMX_SPI5_1_DO, 76, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO6 */ + {38, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO6 */ + {39, 0, PMX_DMDAT0_1, 84, 3}, /* P_GPIO7 */ + {39, 0, PMX_SPI5_1_DI, 87, 2}, /* P_GPIO7 */ + {39, 0, PMX_UART3_3_CTS, 79, 2}, /* P_GPIO7 */ + {39, 0, PMX_PWM7_1, 89, 1}, /* P_GPIO7 */ + {39, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO7 */ + {39, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO7 */ + {40, 0, PMX_DMDAT1_1, 84, 3}, /* P_GPIO8 */ + {40, 0, PMX_PWM8_1, 90, 1}, /* P_GPIO8 */ + {40, 0, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO8 */ + {40, 0, PMX_SPI_3_CS, 91, 1}, /* P_GPIO8 */ + {40, 0, PMX_UART_CH6, 92, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO8 */ + {40, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO8 */ + {41, 0, PMX_DMCLK_1, 84, 3}, /* P_GPIO9 */ + {41, 0, PMX_PWM9_1, 93, 1}, /* P_GPIO9 */ + {41, 0, PMX_SENSOR2_CCIR8BITS_VDHD, 62, 1}, /* P_GPIO9 */ + {41, 0, PMX_SPI_3_CLK, 91, 1}, /* P_GPIO9 */ + {41, 0, PMX_UART_CH6, 92, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO9 */ + {41, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO9 */ + {42, 0, PMX_UART_CH6_CTSRTS, 94, 2}, /* P_GPIO10 */ + {42, 0, PMX_UART_CH6_DIROE, 96, 2}, /* P_GPIO10 */ + {42, 0, PMX_PWM10_1, 98, 1}, /* P_GPIO10 */ + {42, 0, PMX_SENSOR2_CCIR8BITS_VDHD, 62, 1}, /* P_GPIO10 */ + {42, 0, PMX_SPI_3_DO, 91, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO10 */ + {42, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO10 */ + {43, 0, PMX_SPI_3_DI, 99, 2}, /* P_GPIO11 */ + {43, 0, PMX_UART_CH6_CTSRTS, 94, 2}, /* P_GPIO11 */ + {43, 0, PMX_I2C4_1_SCL, 101, 1}, /* P_GPIO11 */ + {43, 0, PMX_PWM11_1, 102, 1}, /* P_GPIO11 */ + {43, 0, PMX_SENSOR2_CCIR8BITS_FIELD, 62, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR2_CCIR8BITS, 62, 1}, /* P_GPIO11 */ + {43, NVT_UNGATED, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO11 */ + {44, 0, PMX_SENSOR2_SN3_MCLK, 103, 2}, /* P_GPIO12 */ + {44, 0, PMX_SPI_CH3_RDY, 105, 2}, /* P_GPIO12 */ + {44, 0, PMX_I2C4_1_SDA, 101, 1}, /* P_GPIO12 */ + {44, 0, PMX_PICNT_1, 107, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR2_12BITS, 61, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR2_SN3_MCLK, 108, 1}, /* P_GPIO12 */ + {44, 0, PMX_SENSOR_12BITS_2ND, 63, 1}, /* P_GPIO12 */ + {45, 0, PMX_SB4_CS, 109, 1}, /* P_GPIO13 */ + {45, 0, PMX_SPI2_1_CS, 110, 1}, /* P_GPIO13 */ + {45, 0, PMX_UART3_1_TX, 111, 1}, /* P_GPIO13 */ + {46, 0, PMX_PICNT2_1, 112, 1}, /* P_GPIO14 */ + {46, 0, PMX_SB4_CK, 109, 1}, /* P_GPIO14 */ + {46, 0, PMX_SPI2_1_CLK, 110, 1}, /* P_GPIO14 */ + {46, 0, PMX_UART3_1_RX, 111, 1}, /* P_GPIO14 */ + {47, 0, PMX_UART3_1_RTS, 113, 2}, /* P_GPIO15 */ + {47, 0, PMX_UART3_1_RTS, 115, 2}, /* P_GPIO15 */ + {47, 0, PMX_SB4_DAT, 109, 1}, /* P_GPIO15 */ + {47, 0, PMX_SPI2_1_DO, 110, 1}, /* P_GPIO15 */ + {47, 0, PMX_SP_CLK2_2, 18, 1}, /* P_GPIO15 */ + {48, 0, PMX_SPI2_1_DI, 117, 2}, /* P_GPIO16 */ + {48, 0, PMX_UART3_1_CTS, 113, 2}, /* P_GPIO16 */ + {48, 0, PMX_I2S_1_MCLK, 119, 1}, /* P_GPIO16 */ + {48, 0, PMX_SB3_2_CS, 120, 1}, /* P_GPIO16 */ + {49, 0, PMX_I2S_BCLK_1, 121, 1}, /* P_GPIO17 */ + {49, 0, PMX_PICNT3_1, 122, 1}, /* P_GPIO17 */ + {49, 0, PMX_REMOTE_IN_1, 123, 1}, /* P_GPIO17 */ + {49, 0, PMX_SENSOR_SPCLK, 124, 1}, /* P_GPIO17 */ + {49, 0, PMX_SPI3_1_CS, 125, 1}, /* P_GPIO17 */ + {49, 0, PMX_UART2_1_TX, 126, 1}, /* P_GPIO17 */ + {50, 0, PMX_I2S_SYNC_1, 121, 1}, /* P_GPIO18 */ + {50, 0, PMX_PICNT_2, 127, 1}, /* P_GPIO18 */ + {50, 0, PMX_SENSOR_SP2CLK, 128, 1}, /* P_GPIO18 */ + {50, 0, PMX_SPI3_1_CLK, 125, 1}, /* P_GPIO18 */ + {50, 0, PMX_UART2_1_RX, 126, 1}, /* P_GPIO18 */ + {51, 0, PMX_UART2_1_RTS, 129, 2}, /* P_GPIO19 */ + {51, 0, PMX_UART2_1_RTS, 131, 2}, /* P_GPIO19 */ + {51, 0, PMX_I2S_SDATAO_1, 121, 1}, /* P_GPIO19 */ + {51, 0, PMX_PICNT2_2, 133, 1}, /* P_GPIO19 */ + {51, 0, PMX_SB3_2_CK, 120, 1}, /* P_GPIO19 */ + {51, 0, PMX_SPI3_1_DO, 125, 1}, /* P_GPIO19 */ + {51, 0, PMX_SP_CLK_2, 134, 1}, /* P_GPIO19 */ + {52, 0, PMX_SPI3_1_DI, 135, 2}, /* P_GPIO20 */ + {52, 0, PMX_UART2_1_CTS, 129, 2}, /* P_GPIO20 */ + {52, 0, PMX_I2S_SDATAI_1, 121, 1}, /* P_GPIO20 */ + {52, 0, PMX_PICNT3_2, 137, 1}, /* P_GPIO20 */ + {52, 0, PMX_SB3_2_DAT, 120, 1}, /* P_GPIO20 */ + {53, 0, PMX_I2C3_1_SDA, 138, 1}, /* P_GPIO21 */ + {54, 0, PMX_I2C3_1_SCL, 138, 1}, /* P_GPIO22 */ + {55, 0, PMX_UART_TX, 139, 1}, /* P_GPIO23 */ + {56, 0, PMX_SP_CLK2_1, 128, 1}, /* P_GPIO24 */ + {56, 0, PMX_UART_RX, 139, 1}, /* P_GPIO24 */ + {64, 0, PMX_SENSOR_MCLK, 140, 1}, /* S_GPIO0 */ + {65, 0, PMX_SENSOR_MCLK2, 141, 2}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 143, 2}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 145, 2}, /* S_GPIO1 */ + {65, 0, PMX_PWM0_3, 147, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_12BITS, 148, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_CCIR8BITS, 149, 1}, /* S_GPIO1 */ + {65, 0, PMX_SENSOR_MCLK2, 150, 1}, /* S_GPIO1 */ + {66, 0, PMX_PWM1_3, 151, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_12BITS, 148, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_12BITS_2ND, 63, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_CCIR8BITS, 149, 1}, /* S_GPIO2 */ + {66, 0, PMX_SENSOR_LVDS_VDHD, 152, 1}, /* S_GPIO2 */ + {67, 0, PMX_PWM2_3, 153, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_12BITS, 148, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_12BITS_2ND, 63, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_CCIR8BITS, 149, 1}, /* S_GPIO3 */ + {67, 0, PMX_SENSOR_LVDS_VDHD, 152, 1}, /* S_GPIO3 */ + {68, 0, PMX_PWM3_3, 154, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR2_12BITS, 61, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR2_LVDS_VDHD, 155, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR_CCIR16BITS, 58, 1}, /* S_GPIO4 */ + {68, 0, PMX_SENSOR_CCIR8BITS, 149, 1}, /* S_GPIO4 */ + {68, 0, PMX_UART_CH3_4TH, 156, 1}, /* S_GPIO4 */ + {69, 0, PMX_PWM4_3, 157, 1}, /* S_GPIO5 */ + {69, 0, PMX_SENSOR2_12BITS, 61, 1}, /* S_GPIO5 */ + {69, 0, PMX_SENSOR2_LVDS_VDHD, 155, 1}, /* S_GPIO5 */ + {70, 0, PMX_PWM5_3, 158, 1}, /* S_GPIO6 */ + {70, 0, PMX_SB_CS, 159, 1}, /* S_GPIO6 */ + {70, 0, PMX_UART_CH3_4TH, 156, 1}, /* S_GPIO6 */ + {71, 0, PMX_I2C_SCL_1, 160, 1}, /* S_GPIO7 */ + {71, 0, PMX_PWM6_3, 161, 1}, /* S_GPIO7 */ + {71, 0, PMX_SB_CK, 159, 1}, /* S_GPIO7 */ + {72, 0, PMX_I2C_SDA_1, 160, 1}, /* S_GPIO8 */ + {72, 0, PMX_PWM7_3, 162, 1}, /* S_GPIO8 */ + {72, 0, PMX_SB_DAT, 159, 1}, /* S_GPIO8 */ + {73, 0, PMX_SB2_CS, 163, 1}, /* S_GPIO9 */ + {73, 0, PMX_SPI_2_CS, 164, 1}, /* S_GPIO9 */ + {74, 0, PMX_I2C2_1_SCL, 165, 1}, /* S_GPIO10 */ + {74, 0, PMX_SB2_CK, 163, 1}, /* S_GPIO10 */ + {74, 0, PMX_SPI_2_CLK, 164, 1}, /* S_GPIO10 */ + {75, 0, PMX_I2C2_1_SDA, 165, 1}, /* S_GPIO11 */ + {75, 0, PMX_SB2_DAT, 163, 1}, /* S_GPIO11 */ + {75, 0, PMX_SPI_2_DO, 164, 1}, /* S_GPIO11 */ + {76, 0, PMX_SPI_2_DI, 166, 2}, /* S_GPIO12 */ + {76, 0, PMX_SENSOR2_MCLK_2ND, 168, 1}, /* S_GPIO12 */ + {96, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO0 */ + {96, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO0 */ + {96, 0, PMX_PWM0_5, 217, 1}, /* L_GPIO0 */ + {96, 0, PMX_TXD0, 1, 0}, /* L_GPIO0 */ + {97, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO1 */ + {97, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO1 */ + {97, 0, PMX_PWM1_5, 218, 1}, /* L_GPIO1 */ + {97, 0, PMX_TXD1, 1, 0}, /* L_GPIO1 */ + {98, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO2 */ + {98, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO2 */ + {98, 0, PMX_PWM2_5, 225, 1}, /* L_GPIO2 */ + {98, 0, PMX_TX_EN, 1, 0}, /* L_GPIO2 */ + {99, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO3 */ + {99, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO3 */ + {99, 0, PMX_PWM3_5, 226, 1}, /* L_GPIO3 */ + {99, 0, PMX_RXD0, 1, 0}, /* L_GPIO3 */ + {100, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO4 */ + {100, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO4 */ + {100, 0, PMX_PWM4_5, 227, 1}, /* L_GPIO4 */ + {100, 0, PMX_RXD1, 1, 0}, /* L_GPIO4 */ + {101, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO5 */ + {101, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO5 */ + {101, 0, PMX_PWM5_5, 228, 1}, /* L_GPIO5 */ + {101, 0, PMX_CRS_DV, 1, 0}, /* L_GPIO5 */ + {102, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO6 */ + {102, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO6 */ + {102, 0, PMX_PWM6_5, 229, 1}, /* L_GPIO6 */ + {102, 0, PMX_RX_ER, 1, 0}, /* L_GPIO6 */ + {103, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO7 */ + {103, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO7 */ + {103, 0, PMX_ETH_PHYCLK, 230, 1}, /* L_GPIO7 */ + {103, 0, PMX_PWM7_5, 231, 1}, /* L_GPIO7 */ + {103, 0, PMX_ETH_PHYCLK, 1, 0}, /* L_GPIO7 */ + {104, 0, PMX_LCD_CCIR601, 169, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 172, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 175, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR601, 178, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656, 181, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_CCIR656, 184, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB888, 199, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_PARALLE_RGB888, 202, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_6BITS, 219, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_6BITS, 222, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_8BITS, 211, 3}, /* L_GPIO8 */ + {104, 0, PMX_LCD_SERIAL_RGB_8BITS, 214, 3}, /* L_GPIO8 */ + {104, 0, PMX_PWM8_5, 232, 1}, /* L_GPIO8 */ + {104, 0, PMX_REFCLK, 1, 0}, /* L_GPIO8 */ + {105, 0, PMX_LCD_NO_HVSYNC, 169, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 172, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 175, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 178, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 187, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 190, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 211, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 214, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 219, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 222, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 205, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 208, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 193, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 196, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 199, 3}, /* L_GPIO9 */ + {105, 0, PMX_LCD_NO_HVSYNC, 202, 3}, /* L_GPIO9 */ + {105, 0, PMX_PWM9_5, 233, 1}, /* L_GPIO9 */ + {105, 0, PMX_MDC, 1, 0}, /* L_GPIO9 */ + {106, 0, PMX_LCD_NO_HVSYNC, 169, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 172, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 175, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 178, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 187, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 190, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 211, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 214, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 219, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 222, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 205, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 208, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 193, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 196, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 199, 3}, /* L_GPIO10 */ + {106, 0, PMX_LCD_NO_HVSYNC, 202, 3}, /* L_GPIO10 */ + {106, 0, PMX_PWM10_5, 234, 1}, /* L_GPIO10 */ + {106, 0, PMX_MDIO, 1, 0}, /* L_GPIO10 */ + {107, 0, PMX_LCD_DE_ENABLE, 235, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 184, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 175, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 178, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 190, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 214, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 222, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 208, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 196, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 238, 3}, /* L_GPIO11 */ + {107, 0, PMX_LCD_DE_ENABLE, 202, 3}, /* L_GPIO11 */ + {107, 0, PMX_PWM11_5, 241, 1}, /* L_GPIO11 */ + {107, 0, PMX_TX_CTL, 242, 1}, /* L_GPIO11 */ + {107, 0, PMX_TX_EN, 243, 1}, /* L_GPIO11 */ + {108, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_HVLD_VVLD, 172, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_HVLD_VVLD, 178, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO12 */ + {108, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO12 */ + {108, 0, PMX_TXD0, 243, 1}, /* L_GPIO12 */ + {108, 0, PMX_TXD0, 242, 1}, /* L_GPIO12 */ + {109, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_HVLD_VVLD, 172, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_HVLD_VVLD, 178, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO13 */ + {109, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO13 */ + {109, 0, PMX_TXD1, 243, 1}, /* L_GPIO13 */ + {109, 0, PMX_TXD1, 242, 1}, /* L_GPIO13 */ + {110, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_FIELD, 172, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_FIELD, 178, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO14 */ + {110, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO14 */ + {110, 0, PMX_TXD2, 242, 1}, /* L_GPIO14 */ + {111, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO15 */ + {111, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO15 */ + {111, 0, PMX_TXD3, 242, 1}, /* L_GPIO15 */ + {112, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO16 */ + {112, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO16 */ + {112, 0, PMX_REFCLK, 243, 1}, /* L_GPIO16 */ + {112, 0, PMX_RX_CLK, 242, 1}, /* L_GPIO16 */ + {113, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO17 */ + {113, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO17 */ + {113, 0, PMX_CRS_DV, 243, 1}, /* L_GPIO17 */ + {113, 0, PMX_RX_CTL, 242, 1}, /* L_GPIO17 */ + {114, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO18 */ + {114, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO18 */ + {114, 0, PMX_RXD0, 243, 1}, /* L_GPIO18 */ + {114, 0, PMX_RXD0, 242, 1}, /* L_GPIO18 */ + {115, 0, PMX_LCD_CCIR601_16BITS, 169, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR601_16BITS, 175, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR656_16BITS, 181, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_CCIR656_16BITS, 184, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB565, 187, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB565, 190, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_RGB_16BITS, 205, 3}, /* L_GPIO19 */ + {115, 0, PMX_LCD_RGB_16BITS, 208, 3}, /* L_GPIO19 */ + {115, 0, PMX_RXD1, 243, 1}, /* L_GPIO19 */ + {115, 0, PMX_RXD1, 242, 1}, /* L_GPIO19 */ + {116, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO20 */ + {116, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO20 */ + {116, 0, PMX_RXD2, 242, 1}, /* L_GPIO20 */ + {116, 0, PMX_SP_CLK_1, 124, 1}, /* L_GPIO20 */ + {117, 0, PMX_LCD_PARALLE_RGB666, 193, 3}, /* L_GPIO21 */ + {117, 0, PMX_LCD_PARALLE_RGB666, 196, 3}, /* L_GPIO21 */ + {117, 0, PMX_RXD3, 242, 1}, /* L_GPIO21 */ + {118, 0, PMX_LCD_TE_ENABLE, 244, 4}, /* L_GPIO22 */ + {118, 0, PMX_SB3_1_CS, 248, 1}, /* L_GPIO22 */ + {118, 0, PMX_TX_CLK, 242, 1}, /* L_GPIO22 */ + {119, 0, PMX_MDC, 243, 1}, /* L_GPIO23 */ + {119, 0, PMX_MDC, 242, 1}, /* L_GPIO23 */ + {119, 0, PMX_SB3_1_CK, 248, 1}, /* L_GPIO23 */ + {119, 0, PMX_SENSOR_SPCLK_2ND, 134, 1}, /* L_GPIO23 */ + {120, 0, PMX_MDIO, 243, 1}, /* L_GPIO24 */ + {120, 0, PMX_MDIO, 242, 1}, /* L_GPIO24 */ + {120, 0, PMX_SB3_1_DAT, 248, 1}, /* L_GPIO24 */ + {128, 0, PMX_ETH_PHYCLK, 249, 2}, /* D_GPIO0 */ + {128, 0, PMX_ETH_PHYCLK, 251, 2}, /* D_GPIO0 */ + {128, 0, PMX_ETH_PHYCLK, 253, 1}, /* D_GPIO0 */ + {129, 0, PMX_ETH_LED1, 253, 1}, /* D_GPIO1 */ + {130, 0, PMX_REMOTE_CH3, 254, 1}, /* D_GPIO2 */ + {131, 0, PMX_PWM4_4, 255, 1}, /* D_GPIO3 */ + {131, 0, PMX_SENSOR_SPCLK_3RD, 256, 1}, /* D_GPIO3 */ + {132, 0, PMX_PWM5_4, 257, 1}, /* D_GPIO4 */ + {132, 0, PMX_SP_CLK2_3, 258, 1}, /* D_GPIO4 */ + {133, 0, PMX_ETH_LED2, 259, 1}, /* D_GPIO5 */ + {133, 0, PMX_PWM6_4, 260, 1}, /* D_GPIO5 */ + {134, 0, PMX_ETH_LED2, 259, 1}, /* D_GPIO6 */ + {134, 0, PMX_PWM7_4, 261, 1}, /* D_GPIO6 */ + {135, 0, PMX_I2S_2_MCLK, 262, 1}, /* D_GPIO7 */ + {135, 0, PMX_PWM11_4, 263, 1}, /* D_GPIO7 */ + {136, 0, PMX_DMCLK_2, 264, 3}, /* D_GPIO8 */ + {136, 0, PMX_PWM8_4, 267, 1}, /* D_GPIO8 */ + {136, 0, PMX_SB3_3_CS, 268, 1}, /* D_GPIO8 */ + {137, 0, PMX_DMDAT0_2, 264, 3}, /* D_GPIO9 */ + {137, 0, PMX_PWM9_4, 269, 1}, /* D_GPIO9 */ + {137, 0, PMX_SB3_3_CK, 268, 1}, /* D_GPIO9 */ + {138, 0, PMX_DMDAT1_2, 264, 3}, /* D_GPIO10 */ + {138, 0, PMX_PWM10_4, 270, 1}, /* D_GPIO10 */ + {138, 0, PMX_SB3_3_DAT, 268, 1}, /* D_GPIO10 */ + {160, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO0 */ + {160, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO0 */ + {161, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO1 */ + {161, 0, PMX_MIPI_LVDS_DAT0, 1, 0}, /* H_GPIO1 */ + {162, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO2 */ + {162, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO2 */ + {162, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO2 */ + {162, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO2 */ + {163, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO3 */ + {163, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO3 */ + {163, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO3 */ + {163, 0, PMX_MIPI_LVDS_DAT1, 1, 0}, /* H_GPIO3 */ + {164, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO4 */ + {164, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO4 */ + {164, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO4 */ + {164, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO4 */ + {165, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO5 */ + {165, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO5 */ + {165, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO5 */ + {165, 0, PMX_MIPI_LVDS_CLK0, 1, 0}, /* H_GPIO5 */ + {166, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO6 */ + {166, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO6 */ + {166, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO6 */ + {166, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO6 */ + {167, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO7 */ + {167, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO7 */ + {167, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO7 */ + {167, 0, PMX_MIPI_LVDS_DAT2, 1, 0}, /* H_GPIO7 */ + {168, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO8 */ + {168, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO8 */ + {168, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO8 */ + {168, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO8 */ + {169, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO9 */ + {169, NVT_UNGATED, PMX_SENSOR_CCIR16BITS, 58, 1}, /* H_GPIO9 */ + {169, NVT_UNGATED, PMX_SENSOR_CCIR8BITS, 149, 1}, /* H_GPIO9 */ + {169, 0, PMX_MIPI_LVDS_DAT3, 1, 0}, /* H_GPIO9 */ + {170, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO10 */ + {170, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO10 */ + {171, NVT_UNGATED, PMX_SENSOR_12BITS, 148, 1}, /* H_GPIO11 */ + {171, 0, PMX_MIPI_LVDS_CLK1, 1, 0}, /* H_GPIO11 */ +}; + +/* The field each function's walk row shows: {pad, name, reg, + * shift, width, value}, reg NVT_GATE for the pad's gate bit. */ +static const novatek_sel_t NA51084_sels[] = { + {0, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {0, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {1, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {1, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {2, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {2, PMX_UART_CH3_5TH, 0x24, 4, 3, 5}, + {2, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {3, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {3, PMX_UART_CH3_5TH, 0x24, 4, 3, 5}, + {3, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {4, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {4, PMX_I2S_BCLK_2, 0x18, 0, 2, 2}, + {4, PMX_PWM0_4, 0x1C, 0, 3, 4}, + {4, PMX_SPI4_2_CS, 0x10, 2, 2, 2}, + {4, PMX_UART_CH4_2ND, 0x24, 12, 2, 2}, + {5, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {5, PMX_I2S_SYNC_2, 0x18, 0, 2, 2}, + {5, PMX_PWM1_4, 0x1C, 3, 3, 4}, + {5, PMX_SPI4_2_CLK, 0x10, 2, 2, 2}, + {5, PMX_UART_CH4_2ND, 0x24, 12, 2, 2}, + {6, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {6, PMX_UART_CH4_CTSRTS, 0x24, 18, 2, 1}, + {6, PMX_UART_CH4_DIROE, 0x24, 18, 2, 2}, + {6, PMX_I2C4_2_SCL, 0x14, 2, 2, 2}, + {6, PMX_I2S_SDATAO_2, 0x18, 0, 2, 2}, + {6, PMX_PWM2_4, 0x1C, 6, 3, 4}, + {6, PMX_SPI4_2_DO, 0x10, 2, 2, 2}, + {7, PMX_SDIO_8BITS, 0x04, 17, 1, 1}, + {7, PMX_SPI4_2_DI, 0x10, 2, 2, 2}, + {7, PMX_UART_CH4_CTSRTS, 0x24, 12, 2, 2}, + {7, PMX_I2C4_2_SDA, 0x14, 2, 2, 2}, + {7, PMX_I2S_SDATAI_2, 0x18, 0, 2, 2}, + {7, PMX_PWM3_4, 0x1C, 9, 3, 4}, + {8, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {8, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {9, PMX_SDIO_4BITS, 0x04, 17, 1, 1}, + {9, PMX_SENSOR_SP2CLK_2ND, 0x18, 10, 2, 2}, + {10, PMX_NAND_1CS, NVT_GATE, 0, 0, 0}, + {11, PMX_DMCLK_3, 0x18, 5, 1, 1}, + {11, PMX_I2C3_2_SCL, 0x14, 6, 2, 2}, + {11, PMX_PWM4_2, 0x1C, 12, 3, 2}, + {11, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {11, PMX_SPI3_2_CLK, 0x14, 12, 2, 2}, + {12, PMX_DMDAT0_3, 0x18, 5, 1, 1}, + {12, PMX_I2C3_2_SDA, 0x14, 6, 2, 2}, + {12, PMX_PWM5_2, 0x1C, 15, 3, 2}, + {12, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {12, PMX_SPI3_2_DO, 0x14, 12, 2, 2}, + {13, PMX_DMDAT1_3, 0x18, 5, 1, 1}, + {13, PMX_UART2_2_CTS, 0x24, 2, 2, 2}, + {13, PMX_PWM0_2, 0x1C, 0, 3, 2}, + {13, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {13, PMX_SPI3_2_CS, 0x14, 12, 2, 2}, + {14, PMX_SPI3_2_DI, 0x14, 12, 2, 2}, + {14, PMX_UART2_2_RTS, 0x24, 2, 2, 2}, + {14, PMX_PWM1_2, 0x1C, 3, 3, 2}, + {14, PMX_REMOTE_IN_2, 0x18, 7, 2, 2}, + {14, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {15, PMX_SPI_CH3_RDY, 0x14, 12, 2, 2}, + {15, PMX_PWM2_2, 0x1C, 6, 3, 2}, + {15, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {15, PMX_UART2_2_TX, 0x24, 2, 2, 2}, + {16, PMX_PWM3_2, 0x1C, 9, 3, 2}, + {16, PMX_SDIO_4BITS, 0x04, 14, 1, 1}, + {16, PMX_UART2_2_RX, 0x24, 2, 2, 2}, + {17, PMX_I2C2_2_SCL, 0x14, 4, 2, 2}, + {17, PMX_PWM6_2, 0x1C, 18, 3, 2}, + {17, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {17, PMX_SPI_1_CLK, 0x14, 8, 2, 1}, + {18, PMX_I2C2_2_SDA, 0x14, 4, 2, 2}, + {18, PMX_PWM7_2, 0x1C, 21, 3, 2}, + {18, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {18, PMX_SPI_1_DO, 0x14, 8, 2, 1}, + {19, PMX_UART3_2_CTS, 0x24, 4, 3, 2}, + {19, PMX_PWM8_2, 0x18, 16, 3, 2}, + {19, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {19, PMX_SPI_1_CS, 0x14, 8, 2, 1}, + {20, PMX_SPI_1_DI, 0x14, 8, 2, 1}, + {20, PMX_UART3_2_RTS, 0x24, 4, 3, 2}, + {20, PMX_PWM9_2, 0x18, 19, 3, 2}, + {20, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {21, PMX_PWM10_2, 0x18, 22, 3, 2}, + {21, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {21, PMX_UART3_2_TX, 0x24, 4, 3, 2}, + {22, PMX_PWM11_2, 0x18, 25, 3, 2}, + {22, PMX_SDIO_4BITS, 0x04, 15, 1, 1}, + {22, PMX_UART3_2_RX, 0x24, 4, 3, 2}, + {32, PMX_PWM0_1, 0x1C, 0, 3, 1}, + {32, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {32, PMX_SPI4_1_CS, 0x10, 2, 2, 1}, + {32, PMX_UART2_3_TX, 0x24, 12, 2, 1}, + {32, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {32, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {32, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {33, PMX_PWM1_1, 0x1C, 3, 3, 1}, + {33, PMX_RTC_CLK, 0x18, 9, 1, 1}, + {33, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {33, PMX_SPI4_1_CLK, 0x10, 2, 2, 1}, + {33, PMX_UART2_3_RX, 0x24, 12, 2, 1}, + {33, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {33, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {33, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {34, PMX_UART2_3_RTS, 0x24, 12, 2, 1}, + {34, PMX_I2C5_1_SCL, 0x10, 0, 2, 1}, + {34, PMX_PWM2_1, 0x1C, 6, 3, 1}, + {34, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {34, PMX_SPI4_1_DO, 0x10, 2, 2, 1}, + {34, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {34, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {34, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {35, PMX_SPI4_1_DI, 0x10, 2, 2, 1}, + {35, PMX_UART2_3_CTS, 0x24, 12, 2, 1}, + {35, PMX_I2C5_1_SDA, 0x10, 0, 2, 1}, + {35, PMX_PWM3_1, 0x1C, 9, 3, 1}, + {35, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {35, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {35, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {35, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {36, PMX_PWM4_1, 0x1C, 12, 3, 1}, + {36, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {36, PMX_SPI5_1_CS, 0x10, 4, 2, 1}, + {36, PMX_UART3_3_TX, 0x24, 14, 2, 1}, + {36, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {36, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {36, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {37, PMX_PWM5_1, 0x1C, 15, 3, 1}, + {37, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {37, PMX_SPI5_1_CLK, 0x10, 4, 2, 1}, + {37, PMX_UART3_3_RX, 0x24, 14, 2, 1}, + {37, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {37, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {37, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {38, PMX_UART3_3_RTS, 0x24, 14, 2, 1}, + {38, PMX_PWM6_1, 0x1C, 18, 3, 1}, + {38, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {38, PMX_SPI5_1_DO, 0x10, 4, 2, 1}, + {38, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {38, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {38, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {39, PMX_DMDAT0_1, 0x18, 5, 1, 1}, + {39, PMX_SPI5_1_DI, 0x10, 4, 2, 1}, + {39, PMX_UART3_3_CTS, 0x24, 14, 2, 1}, + {39, PMX_PWM7_1, 0x1C, 21, 3, 1}, + {39, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {39, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {39, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {39, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {40, PMX_DMDAT1_1, 0x18, 5, 1, 1}, + {40, PMX_PWM8_1, 0x18, 16, 3, 1}, + {40, PMX_SENSOR2_CCIR8BITS, 0x0C, 4, 2, 2}, + {40, PMX_SPI_3_CS, 0x14, 8, 2, 3}, + {40, PMX_UART_CH6, 0x24, 16, 2, 1}, + {40, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {40, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {41, PMX_DMCLK_1, 0x18, 5, 1, 1}, + {41, PMX_PWM9_1, 0x18, 19, 3, 1}, + {41, PMX_SENSOR2_CCIR8BITS_VDHD, 0x0C, 4, 2, 2}, + {41, PMX_SPI_3_CLK, 0x14, 8, 2, 3}, + {41, PMX_UART_CH6, 0x24, 16, 2, 1}, + {41, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {41, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {41, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {42, PMX_UART_CH6_CTSRTS, 0x24, 22, 2, 1}, + {42, PMX_UART_CH6_DIROE, 0x24, 22, 2, 2}, + {42, PMX_PWM10_1, 0x18, 22, 3, 1}, + {42, PMX_SENSOR2_CCIR8BITS_VDHD, 0x0C, 4, 2, 2}, + {42, PMX_SPI_3_DO, 0x14, 8, 2, 3}, + {42, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {42, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {42, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {43, PMX_SPI_3_DI, 0x14, 8, 2, 3}, + {43, PMX_UART_CH6_CTSRTS, 0x24, 16, 2, 1}, + {43, PMX_I2C4_1_SCL, 0x14, 2, 2, 1}, + {43, PMX_PWM11_1, 0x18, 25, 3, 1}, + {43, PMX_SENSOR2_CCIR8BITS_FIELD, 0x0C, 4, 2, 2}, + {43, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {43, PMX_SENSOR2_CCIR8BITS, NVT_GATE, 0, 0, 0}, + {43, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {44, PMX_SENSOR2_SN3_MCLK, 0x0C, 16, 1, 1}, + {44, PMX_SPI_CH3_RDY, 0x14, 12, 2, 1}, + {44, PMX_I2C4_1_SDA, 0x14, 2, 2, 1}, + {44, PMX_PICNT_1, 0x1C, 26, 2, 1}, + {44, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {44, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {45, PMX_SB4_CS, 0x14, 26, 1, 1}, + {45, PMX_SPI2_1_CS, 0x14, 10, 2, 1}, + {45, PMX_UART3_1_TX, 0x24, 4, 3, 1}, + {46, PMX_PICNT2_1, 0x1C, 28, 2, 1}, + {46, PMX_SB4_CK, 0x14, 26, 1, 1}, + {46, PMX_SPI2_1_CLK, 0x14, 10, 2, 1}, + {46, PMX_UART3_1_RX, 0x24, 4, 3, 1}, + {47, PMX_UART3_1_RTS, 0x24, 4, 3, 1}, + {47, PMX_SB4_DAT, 0x14, 26, 1, 1}, + {47, PMX_SPI2_1_DO, 0x14, 10, 2, 1}, + {47, PMX_SP_CLK2_2, 0x18, 10, 2, 2}, + {48, PMX_SPI2_1_DI, 0x14, 10, 2, 1}, + {48, PMX_UART3_1_CTS, 0x24, 4, 3, 1}, + {48, PMX_I2S_1_MCLK, 0x18, 2, 2, 1}, + {48, PMX_SB3_2_CS, 0x14, 24, 2, 2}, + {49, PMX_I2S_BCLK_1, 0x18, 0, 2, 1}, + {49, PMX_PICNT3_1, 0x1C, 30, 2, 1}, + {49, PMX_REMOTE_IN_1, 0x18, 7, 2, 1}, + {49, PMX_SENSOR_SPCLK, 0x0C, 18, 2, 1}, + {49, PMX_SPI3_1_CS, 0x14, 12, 2, 1}, + {49, PMX_UART2_1_TX, 0x24, 2, 2, 1}, + {50, PMX_I2S_SYNC_1, 0x18, 0, 2, 1}, + {50, PMX_PICNT_2, 0x1C, 26, 2, 2}, + {50, PMX_SENSOR_SP2CLK, 0x18, 10, 2, 1}, + {50, PMX_SPI3_1_CLK, 0x14, 12, 2, 1}, + {50, PMX_UART2_1_RX, 0x24, 2, 2, 1}, + {51, PMX_UART2_1_RTS, 0x24, 2, 2, 1}, + {51, PMX_I2S_SDATAO_1, 0x18, 0, 2, 1}, + {51, PMX_PICNT2_2, 0x1C, 28, 2, 2}, + {51, PMX_SB3_2_CK, 0x14, 24, 2, 2}, + {51, PMX_SPI3_1_DO, 0x14, 12, 2, 1}, + {51, PMX_SP_CLK_2, 0x0C, 18, 2, 2}, + {52, PMX_SPI3_1_DI, 0x14, 12, 2, 1}, + {52, PMX_UART2_1_CTS, 0x24, 2, 2, 1}, + {52, PMX_I2S_SDATAI_1, 0x18, 0, 2, 1}, + {52, PMX_PICNT3_2, 0x1C, 30, 2, 2}, + {52, PMX_SB3_2_DAT, 0x14, 24, 2, 2}, + {53, PMX_I2C3_1_SDA, 0x14, 6, 2, 1}, + {54, PMX_I2C3_1_SCL, 0x14, 6, 2, 1}, + {55, PMX_UART_TX, 0x24, 0, 1, 1}, + {56, PMX_SP_CLK2_1, 0x18, 10, 2, 1}, + {56, PMX_UART_RX, 0x24, 0, 1, 1}, + {64, PMX_SENSOR_MCLK, 0x0C, 8, 2, 1}, + {65, PMX_SENSOR_MCLK2, 0x0C, 12, 2, 1}, + {65, PMX_PWM0_3, 0x1C, 0, 3, 3}, + {65, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {65, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {65, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {66, PMX_PWM1_3, 0x1C, 3, 3, 3}, + {66, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {66, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {66, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {66, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {66, PMX_SENSOR_LVDS_VDHD, 0x0C, 10, 1, 1}, + {67, PMX_PWM2_3, 0x1C, 6, 3, 3}, + {67, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {67, PMX_SENSOR_12BITS_2ND, 0x0C, 0, 3, 2}, + {67, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {67, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {67, PMX_SENSOR_LVDS_VDHD, 0x0C, 10, 1, 1}, + {68, PMX_PWM3_3, 0x1C, 9, 3, 3}, + {68, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {68, PMX_SENSOR2_LVDS_VDHD, 0x0C, 14, 1, 1}, + {68, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {68, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {68, PMX_UART_CH3_4TH, 0x24, 4, 3, 4}, + {69, PMX_PWM4_3, 0x1C, 12, 3, 3}, + {69, PMX_SENSOR2_12BITS, 0x0C, 4, 2, 1}, + {69, PMX_SENSOR2_LVDS_VDHD, 0x0C, 14, 1, 1}, + {70, PMX_PWM5_3, 0x1C, 15, 3, 3}, + {70, PMX_SB_CS, 0x14, 20, 1, 1}, + {70, PMX_UART_CH3_4TH, 0x24, 4, 3, 4}, + {71, PMX_I2C_SCL_1, 0x14, 0, 2, 1}, + {71, PMX_PWM6_3, 0x1C, 18, 3, 3}, + {71, PMX_SB_CK, 0x14, 20, 1, 1}, + {72, PMX_I2C_SDA_1, 0x14, 0, 2, 1}, + {72, PMX_PWM7_3, 0x1C, 21, 3, 3}, + {72, PMX_SB_DAT, 0x14, 20, 1, 1}, + {73, PMX_SB2_CS, 0x14, 22, 1, 1}, + {73, PMX_SPI_2_CS, 0x14, 8, 2, 2}, + {74, PMX_I2C2_1_SCL, 0x14, 4, 2, 1}, + {74, PMX_SB2_CK, 0x14, 22, 1, 1}, + {74, PMX_SPI_2_CLK, 0x14, 8, 2, 2}, + {75, PMX_I2C2_1_SDA, 0x14, 4, 2, 1}, + {75, PMX_SB2_DAT, 0x14, 22, 1, 1}, + {75, PMX_SPI_2_DO, 0x14, 8, 2, 2}, + {76, PMX_SPI_2_DI, 0x14, 8, 2, 2}, + {76, PMX_SENSOR2_MCLK_2ND, 0x0C, 12, 2, 2}, + {96, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {96, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {96, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {96, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {96, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {96, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {96, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {96, PMX_PWM0_5, 0x1C, 0, 3, 5}, + {96, PMX_TXD0, NVT_GATE, 0, 0, 0}, + {97, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {97, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {97, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {97, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {97, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {97, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {97, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {97, PMX_PWM1_5, 0x1C, 3, 3, 5}, + {97, PMX_TXD1, NVT_GATE, 0, 0, 0}, + {98, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {98, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {98, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {98, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {98, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {98, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {98, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {98, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {98, PMX_PWM2_5, 0x1C, 6, 3, 5}, + {98, PMX_TX_EN, NVT_GATE, 0, 0, 0}, + {99, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {99, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {99, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {99, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {99, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {99, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {99, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {99, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {99, PMX_PWM3_5, 0x1C, 9, 3, 5}, + {99, PMX_RXD0, NVT_GATE, 0, 0, 0}, + {100, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {100, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {100, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {100, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {100, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {100, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {100, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {100, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {100, PMX_PWM4_5, 0x1C, 12, 3, 5}, + {100, PMX_RXD1, NVT_GATE, 0, 0, 0}, + {101, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {101, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {101, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {101, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {101, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {101, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {101, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {101, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {101, PMX_PWM5_5, 0x1C, 15, 3, 5}, + {101, PMX_CRS_DV, NVT_GATE, 0, 0, 0}, + {102, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {102, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {102, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {102, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {102, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {102, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {102, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {102, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {102, PMX_PWM6_5, 0x1C, 18, 3, 5}, + {102, PMX_RX_ER, NVT_GATE, 0, 0, 0}, + {103, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {103, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {103, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {103, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {103, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {103, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {103, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {103, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {103, PMX_ETH_PHYCLK, 0x18, 28, 1, 1}, + {103, PMX_PWM7_5, 0x1C, 21, 3, 5}, + {104, PMX_LCD_CCIR601, 0x08, 0, 4, 2}, + {104, PMX_LCD_CCIR656, 0x08, 0, 4, 1}, + {104, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {104, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {104, PMX_LCD_PARALLE_RGB888, 0x08, 0, 4, 10}, + {104, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {104, PMX_LCD_SERIAL_RGB_6BITS, 0x08, 0, 4, 5}, + {104, PMX_LCD_SERIAL_RGB_8BITS, 0x08, 0, 4, 4}, + {104, PMX_PWM8_5, 0x18, 16, 3, 5}, + {104, PMX_REFCLK, NVT_GATE, 0, 0, 0}, + {105, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, + {105, PMX_PWM9_5, 0x18, 19, 3, 5}, + {105, PMX_MDC, NVT_GATE, 0, 0, 0}, + {106, PMX_LCD_NO_HVSYNC, 0x08, 0, 4, 2}, + {106, PMX_PWM10_5, 0x18, 22, 3, 5}, + {106, PMX_MDIO, NVT_GATE, 0, 0, 0}, + {107, PMX_LCD_DE_ENABLE, 0x08, 6, 1, 1}, + {107, PMX_PWM11_5, 0x18, 25, 3, 5}, + {107, PMX_TX_CTL, 0x10, 8, 2, 3}, + {107, PMX_TX_EN, 0x10, 8, 2, 2}, + {108, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {108, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {108, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {108, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {108, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {108, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {108, PMX_TXD0, 0x10, 8, 2, 2}, + {109, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {109, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {109, PMX_LCD_HVLD_VVLD, 0x08, 8, 1, 1}, + {109, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {109, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {109, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {109, PMX_TXD1, 0x10, 8, 2, 2}, + {110, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {110, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {110, PMX_LCD_FIELD, 0x08, 8, 1, 1}, + {110, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {110, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {110, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {110, PMX_TXD2, 0x10, 8, 2, 3}, + {111, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {111, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {111, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {111, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {111, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {111, PMX_TXD3, 0x10, 8, 2, 3}, + {112, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {112, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {112, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {112, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {112, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {112, PMX_REFCLK, 0x10, 8, 2, 2}, + {112, PMX_RX_CLK, 0x10, 8, 2, 3}, + {113, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {113, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {113, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {113, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {113, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {113, PMX_CRS_DV, 0x10, 8, 2, 2}, + {113, PMX_RX_CTL, 0x10, 8, 2, 3}, + {114, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {114, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {114, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {114, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {114, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {114, PMX_RXD0, 0x10, 8, 2, 2}, + {115, PMX_LCD_CCIR601_16BITS, 0x08, 0, 4, 2}, + {115, PMX_LCD_CCIR656_16BITS, 0x08, 0, 4, 1}, + {115, PMX_LCD_PARALLE_RGB565, 0x08, 0, 4, 3}, + {115, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {115, PMX_LCD_RGB_16BITS, 0x08, 0, 4, 7}, + {115, PMX_RXD1, 0x10, 8, 2, 2}, + {116, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {116, PMX_RXD2, 0x10, 8, 2, 3}, + {116, PMX_SP_CLK_1, 0x0C, 18, 2, 1}, + {117, PMX_LCD_PARALLE_RGB666, 0x08, 0, 4, 8}, + {117, PMX_RXD3, 0x10, 8, 2, 3}, + {118, PMX_LCD_TE_ENABLE, 0x08, 0, 4, 9}, + {118, PMX_SB3_1_CS, 0x14, 24, 2, 1}, + {118, PMX_TX_CLK, 0x10, 8, 2, 3}, + {119, PMX_MDC, 0x10, 8, 2, 2}, + {119, PMX_SB3_1_CK, 0x14, 24, 2, 1}, + {119, PMX_SENSOR_SPCLK_2ND, 0x0C, 18, 2, 2}, + {120, PMX_MDIO, 0x10, 8, 2, 2}, + {120, PMX_SB3_1_DAT, 0x14, 24, 2, 1}, + {128, PMX_ETH_PHYCLK, 0x10, 8, 2, 2}, + {129, PMX_ETH_LED1, 0x18, 13, 2, 1}, + {130, PMX_REMOTE_CH3, 0x18, 7, 2, 3}, + {131, PMX_PWM4_4, 0x1C, 12, 3, 4}, + {131, PMX_SENSOR_SPCLK_3RD, 0x0C, 18, 2, 3}, + {132, PMX_PWM5_4, 0x1C, 15, 3, 4}, + {132, PMX_SP_CLK2_3, 0x18, 10, 2, 3}, + {133, PMX_ETH_LED2, 0x18, 13, 2, 2}, + {133, PMX_PWM6_4, 0x1C, 18, 3, 4}, + {134, PMX_ETH_LED2, 0x18, 13, 2, 2}, + {134, PMX_PWM7_4, 0x1C, 21, 3, 4}, + {135, PMX_I2S_2_MCLK, 0x18, 2, 2, 2}, + {135, PMX_PWM11_4, 0x18, 25, 3, 4}, + {136, PMX_DMCLK_2, 0x18, 5, 1, 1}, + {136, PMX_PWM8_4, 0x18, 16, 3, 4}, + {136, PMX_SB3_3_CS, 0x14, 24, 2, 3}, + {137, PMX_DMDAT0_2, 0x18, 5, 1, 1}, + {137, PMX_PWM9_4, 0x18, 19, 3, 4}, + {137, PMX_SB3_3_CK, 0x14, 24, 2, 3}, + {138, PMX_DMDAT1_2, 0x18, 5, 1, 1}, + {138, PMX_PWM10_4, 0x18, 22, 3, 4}, + {138, PMX_SB3_3_DAT, 0x14, 24, 2, 3}, + {160, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {160, PMX_MIPI_LVDS_DAT0, NVT_GATE, 0, 0, 0}, + {161, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {161, PMX_MIPI_LVDS_DAT0, NVT_GATE, 0, 0, 0}, + {162, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {162, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {162, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {162, PMX_MIPI_LVDS_DAT1, NVT_GATE, 0, 0, 0}, + {163, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {163, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {163, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {163, PMX_MIPI_LVDS_DAT1, NVT_GATE, 0, 0, 0}, + {164, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {164, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {164, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {164, PMX_MIPI_LVDS_CLK0, NVT_GATE, 0, 0, 0}, + {165, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {165, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {165, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {165, PMX_MIPI_LVDS_CLK0, NVT_GATE, 0, 0, 0}, + {166, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {166, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {166, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {166, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, + {167, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {167, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {167, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {167, PMX_MIPI_LVDS_DAT2, NVT_GATE, 0, 0, 0}, + {168, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {168, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {168, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {168, PMX_MIPI_LVDS_DAT3, NVT_GATE, 0, 0, 0}, + {169, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {169, PMX_SENSOR_CCIR16BITS, 0x0C, 0, 3, 4}, + {169, PMX_SENSOR_CCIR8BITS, 0x0C, 0, 3, 3}, + {169, PMX_MIPI_LVDS_DAT3, NVT_GATE, 0, 0, 0}, + {170, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {170, PMX_MIPI_LVDS_CLK1, NVT_GATE, 0, 0, 0}, + {171, PMX_SENSOR_12BITS, 0x0C, 0, 3, 1}, + {171, PMX_MIPI_LVDS_CLK1, NVT_GATE, 0, 0, 0}, +}; + +static const novatek_soc_t NA51084_padmux = { + NA51084_pads, 113, NA51084_claims, 690, NA51084_conds, + NA51084_sels, 498, }; #endif /* HAL_NOVATEK_PADMUX_H */ diff --git a/src/hal/novatek_reginfo.h b/src/hal/novatek_reginfo.h index 05305a4f..340d9205 100644 --- a/src/hal/novatek_reginfo.h +++ b/src/hal/novatek_reginfo.h @@ -3,9 +3,9 @@ #include "reginfo.h" -/* What plain `reginfo` dumps on a NA51089: the TOP block's pad-mux state, - * whole. The first eleven are the per-peripheral location fields -- REG5 - * holds I2C, SPI, SIF and ETH, REG9 the UARTs, and so on; the vendor's +/* What plain `reginfo` dumps on a NA51089, NA51055 or NA51084: the TOP block's + * pad-mux state, whole. The first eleven are the per-peripheral location fields + * -- REG5 holds I2C, SPI, SIF and ETH, REG9 the UARTs, and so on; the vendor's * plat-na51089/top_reg.h has the bit layout. The last eight are the per-pad * gate bitmaps, one per pad group, where a set bit keeps the pad a GPIO. * `reginfo --pads` is the same state read pad by pad. */ @@ -36,4 +36,25 @@ static const muxctrl_reg_t *NA51089_regs[] = { &NA51089_reg12, &NA51089_reg13, &NA51089_reg14, &NA51089_reg15, &NA51089_reg16, &NA51089_reg17, &NA51089_reg18, 0}; +/* NA51055 and NA51084: the same block with no DSI pad group. */ +static const muxctrl_reg_t *NA51055_regs[] = {&NA51089_reg0, + &NA51089_reg1, + &NA51089_reg2, + &NA51089_reg3, + &NA51089_reg4, + &NA51089_reg5, + &NA51089_reg6, + &NA51089_reg7, + &NA51089_reg8, + &NA51089_reg9, + &NA51089_reg10, + &NA51089_reg11, + &NA51089_reg12, + &NA51089_reg13, + &NA51089_reg14, + &NA51089_reg15, + &NA51089_reg16, + &NA51089_reg17, + 0}; + #endif /* HAL_NOVATEK_REGINFO_H */ diff --git a/src/padmux.c b/src/padmux.c index d213599c..a5e6493e 100644 --- a/src/padmux.c +++ b/src/padmux.c @@ -64,6 +64,8 @@ const padmux_ops_t *padmux_ops(void) { return &PADMUX_OPS_INGENIC; #endif #ifdef IPCHW_PADMUX_NOVATEK + case CHIP_NA51055: + case CHIP_NA51084: case CHIP_NA51089: return &PADMUX_OPS_NOVATEK; #endif diff --git a/src/padmux_names.c b/src/padmux_names.c index 043c56fd..9baa18c8 100644 --- a/src/padmux_names.c +++ b/src/padmux_names.c @@ -76,6 +76,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) .CLK_TEST_OUT3 = "CLK_TEST_OUT3", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .CRS_DV = "CRS_DV", +#endif #if defined(IPCHW_PADMUX_INGENIC) .CS2 = "CS2", #endif @@ -379,6 +382,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .D_GPIO1 = "D_GPIO1", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .D_GPIO10 = "D_GPIO10", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .D_GPIO2 = "D_GPIO2", #endif @@ -397,6 +403,12 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .D_GPIO7 = "D_GPIO7", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .D_GPIO8 = "D_GPIO8", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .D_GPIO9 = "D_GPIO9", +#endif #if defined(IPCHW_PADMUX_SSTAR) .EJ_MODE_1 = "EJ_MODE_1", #endif @@ -529,6 +541,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_SSTAR) .ETH_MODE_3 = "ETH_MODE_3", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .ETH_PHYCLK = "ETH_PHYCLK", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .ETH_RMII = "ETH_RMII", #endif @@ -1207,12 +1222,30 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .I2C3_SDA = "I2C3_SDA", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C4_1_SCL = "I2C4_1_SCL", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C4_1_SDA = "I2C4_1_SDA", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C4_2_SCL = "I2C4_2_SCL", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C4_2_SDA = "I2C4_2_SDA", +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .I2C4_SCL = "I2C4_SCL", #endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .I2C4_SDA = "I2C4_SDA", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C5_1_SCL = "I2C5_1_SCL", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2C5_1_SDA = "I2C5_1_SDA", +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .I2C5_SCL = "I2C5_SCL", #endif @@ -1285,6 +1318,12 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_3536C) .I2S2_WS_TX = "I2S2_WS_TX", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2S_1_MCLK = "I2S_1_MCLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .I2S_2_MCLK = "I2S_2_MCLK", +#endif #if defined(IPCHW_PADMUX_INGENIC) .I2S_ADC_BCLK = "I2S_ADC_BCLK", #endif @@ -1462,6 +1501,18 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .JTAG_TRSTN = "JTAG_TRSTN", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_CCIR601 = "LCD_CCIR601", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_CCIR601_16BITS = "LCD_CCIR601_16BITS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_CCIR656 = "LCD_CCIR656", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_CCIR656_16BITS = "LCD_CCIR656_16BITS", +#endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .LCD_CLK = "LCD_CLK", #endif @@ -1540,12 +1591,45 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .LCD_DE = "LCD_DE", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_DE_ENABLE = "LCD_DE_ENABLE", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_FIELD = "LCD_FIELD", +#endif #if defined(IPCHW_PADMUX_V4) .LCD_HS = "LCD_HS", #endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4A) .LCD_HSYNC = "LCD_HSYNC", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_HVLD_VVLD = "LCD_HVLD_VVLD", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_NO_HVSYNC = "LCD_NO_HVSYNC", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_PARALLE_RGB565 = "LCD_PARALLE_RGB565", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_PARALLE_RGB666 = "LCD_PARALLE_RGB666", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_PARALLE_RGB888 = "LCD_PARALLE_RGB888", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_RGB_16BITS = "LCD_RGB_16BITS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_SERIAL_RGB_6BITS = "LCD_SERIAL_RGB_6BITS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_SERIAL_RGB_8BITS = "LCD_SERIAL_RGB_8BITS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .LCD_TE_ENABLE = "LCD_TE_ENABLE", +#endif #if defined(IPCHW_PADMUX_V4) .LCD_VS = "LCD_VS", #endif @@ -1594,9 +1678,54 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .L_GPIO1 = "L_GPIO1", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO10 = "L_GPIO10", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO11 = "L_GPIO11", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO12 = "L_GPIO12", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO13 = "L_GPIO13", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO14 = "L_GPIO14", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO15 = "L_GPIO15", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO16 = "L_GPIO16", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO17 = "L_GPIO17", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO18 = "L_GPIO18", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO19 = "L_GPIO19", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .L_GPIO2 = "L_GPIO2", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO20 = "L_GPIO20", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO21 = "L_GPIO21", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO22 = "L_GPIO22", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO23 = "L_GPIO23", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .L_GPIO24 = "L_GPIO24", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .L_GPIO3 = "L_GPIO3", #endif @@ -1627,6 +1756,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .MCLK_PORTA = "MCLK_PORTA", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .MDC = "MDC", +#endif #if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .MDCK = "MDCK", #endif @@ -1636,7 +1768,7 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_3536C) .MDCK1 = "MDCK1", #endif -#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_NOVATEK) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) .MDIO = "MDIO", #endif #if defined(IPCHW_PADMUX_3536C) @@ -1906,6 +2038,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .MSC1_PORTC = "MSC1_PORTC", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .NAND_1CS = "NAND_1CS", +#endif #if defined(IPCHW_PADMUX_V2A) .NF_ALE = "NF_ALE", #endif @@ -4075,6 +4210,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .PWM10_3 = "PWM10_3", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .PWM10_4 = "PWM10_4", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .PWM10_5 = "PWM10_5", #endif @@ -4414,6 +4552,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .PWM8_3 = "PWM8_3", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .PWM8_4 = "PWM8_4", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .PWM8_5 = "PWM8_5", #endif @@ -4453,6 +4594,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .PWM9_3 = "PWM9_3", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .PWM9_4 = "PWM9_4", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .PWM9_5 = "PWM9_5", #endif @@ -4633,6 +4777,12 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_INGENIC) .RD = "RD", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .REFCLK = "REFCLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .REMOTE_CH3 = "REMOTE_CH3", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .REMOTE_EXT = "REMOTE_EXT", #endif @@ -4900,6 +5050,27 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) .RTC_TEST_CLK = "RTC_TEST_CLK", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RXD0 = "RXD0", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RXD1 = "RXD1", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RXD2 = "RXD2", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RXD3 = "RXD3", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RX_CLK = "RX_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RX_CTL = "RX_CTL", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .RX_ER = "RX_ER", +#endif #if defined(IPCHW_PADMUX_INGENIC) .SA0 = "SA0", #endif @@ -5188,6 +5359,12 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .SDIO3_D7 = "SDIO3_D7", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SDIO_4BITS = "SDIO_4BITS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SDIO_8BITS = "SDIO_8BITS", +#endif #if defined(IPCHW_PADMUX_V1) .SDIO_CARD_DETECT = "SDIO_CARD_DETECT", #endif @@ -5299,6 +5476,12 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .SENSOR2_CCIR8BITS = "SENSOR2_CCIR8BITS", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR2_CCIR8BITS_FIELD = "SENSOR2_CCIR8BITS_FIELD", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR2_CCIR8BITS_VDHD = "SENSOR2_CCIR8BITS_VDHD", +#endif #if defined(IPCHW_PADMUX_V5) .SENSOR2_CLK = "SENSOR2_CLK", #endif @@ -5353,6 +5536,21 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) .SENSOR_RSTN = "SENSOR_RSTN", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR_SP2CLK = "SENSOR_SP2CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR_SP2CLK_2ND = "SENSOR_SP2CLK_2ND", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR_SPCLK = "SENSOR_SPCLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR_SPCLK_2ND = "SENSOR_SPCLK_2ND", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SENSOR_SPCLK_3RD = "SENSOR_SPCLK_3RD", +#endif #if defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) .SENSOR_VS = "SENSOR_VS", #endif @@ -5695,6 +5893,42 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V5) .SPI3_SDO = "SPI3_SDO", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_1_CLK = "SPI4_1_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_1_CS = "SPI4_1_CS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_1_DI = "SPI4_1_DI", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_1_DO = "SPI4_1_DO", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_2_CLK = "SPI4_2_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_2_CS = "SPI4_2_CS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_2_DI = "SPI4_2_DI", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI4_2_DO = "SPI4_2_DO", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI5_1_CLK = "SPI5_1_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI5_1_CS = "SPI5_1_CS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI5_1_DI = "SPI5_1_DI", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI5_1_DO = "SPI5_1_DO", +#endif #if defined(IPCHW_PADMUX_SSTAR) .SPICSZ1_GPIO_0 = "SPICSZ1_GPIO_0", #endif @@ -5761,6 +5995,18 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V5) .SPI_3WIRE_DATA = "SPI_3WIRE_DATA", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI_3_CLK = "SPI_3_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI_3_CS = "SPI_3_CS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI_3_DI = "SPI_3_DI", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .SPI_3_DO = "SPI_3_DO", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .SPI_CH3_RDY = "SPI_CH3_RDY", #endif @@ -6085,6 +6331,15 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .S_GPIO1 = "S_GPIO1", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .S_GPIO10 = "S_GPIO10", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .S_GPIO11 = "S_GPIO11", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .S_GPIO12 = "S_GPIO12", +#endif #if defined(IPCHW_PADMUX_NOVATEK) .S_GPIO2 = "S_GPIO2", #endif @@ -6106,6 +6361,9 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_NOVATEK) .S_GPIO8 = "S_GPIO8", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .S_GPIO9 = "S_GPIO9", +#endif #if defined(IPCHW_PADMUX_INGENIC) .TCK = "TCK", #endif @@ -6283,6 +6541,27 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_SSTAR) .TTL_MODE_2 = "TTL_MODE_2", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TXD0 = "TXD0", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TXD1 = "TXD1", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TXD2 = "TXD2", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TXD3 = "TXD3", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TX_CLK = "TX_CLK", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TX_CTL = "TX_CTL", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .TX_EN = "TX_EN", +#endif #if defined(IPCHW_PADMUX_INGENIC) .UART0_CTS = "UART0_CTS", #endif @@ -6520,6 +6799,30 @@ const struct padmux_names padmux_names = { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) .UART4_TXD = "UART4_TXD", #endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH3_4TH = "UART_CH3_4TH", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH3_5TH = "UART_CH3_5TH", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH4_2ND = "UART_CH4_2ND", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH4_CTSRTS = "UART_CH4_CTSRTS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH4_DIROE = "UART_CH4_DIROE", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH6 = "UART_CH6", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH6_CTSRTS = "UART_CH6_CTSRTS", +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + .UART_CH6_DIROE = "UART_CH6_DIROE", +#endif #if defined(IPCHW_PADMUX_SSTAR) .UART_IS_GPIO_0 = "UART_IS_GPIO_0", #endif diff --git a/src/padmux_names.h b/src/padmux_names.h index 8c692698..cd24c240 100644 --- a/src/padmux_names.h +++ b/src/padmux_names.h @@ -82,6 +82,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) char CLK_TEST_OUT3[sizeof "CLK_TEST_OUT3"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char CRS_DV[sizeof "CRS_DV"]; +#endif #if defined(IPCHW_PADMUX_INGENIC) char CS2[sizeof "CS2"]; #endif @@ -385,6 +388,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char D_GPIO1[sizeof "D_GPIO1"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char D_GPIO10[sizeof "D_GPIO10"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char D_GPIO2[sizeof "D_GPIO2"]; #endif @@ -403,6 +409,12 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char D_GPIO7[sizeof "D_GPIO7"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char D_GPIO8[sizeof "D_GPIO8"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char D_GPIO9[sizeof "D_GPIO9"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char EJ_MODE_1[sizeof "EJ_MODE_1"]; #endif @@ -535,6 +547,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_SSTAR) char ETH_MODE_3[sizeof "ETH_MODE_3"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char ETH_PHYCLK[sizeof "ETH_PHYCLK"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char ETH_RMII[sizeof "ETH_RMII"]; #endif @@ -1213,12 +1228,30 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char I2C3_SDA[sizeof "I2C3_SDA"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C4_1_SCL[sizeof "I2C4_1_SCL"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C4_1_SDA[sizeof "I2C4_1_SDA"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C4_2_SCL[sizeof "I2C4_2_SCL"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C4_2_SDA[sizeof "I2C4_2_SDA"]; +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char I2C4_SCL[sizeof "I2C4_SCL"]; #endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char I2C4_SDA[sizeof "I2C4_SDA"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C5_1_SCL[sizeof "I2C5_1_SCL"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2C5_1_SDA[sizeof "I2C5_1_SDA"]; +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char I2C5_SCL[sizeof "I2C5_SCL"]; #endif @@ -1291,6 +1324,12 @@ struct padmux_names { #if defined(IPCHW_PADMUX_3536C) char I2S2_WS_TX[sizeof "I2S2_WS_TX"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2S_1_MCLK[sizeof "I2S_1_MCLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char I2S_2_MCLK[sizeof "I2S_2_MCLK"]; +#endif #if defined(IPCHW_PADMUX_INGENIC) char I2S_ADC_BCLK[sizeof "I2S_ADC_BCLK"]; #endif @@ -1468,6 +1507,18 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char JTAG_TRSTN[sizeof "JTAG_TRSTN"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_CCIR601[sizeof "LCD_CCIR601"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_CCIR601_16BITS[sizeof "LCD_CCIR601_16BITS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_CCIR656[sizeof "LCD_CCIR656"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_CCIR656_16BITS[sizeof "LCD_CCIR656_16BITS"]; +#endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char LCD_CLK[sizeof "LCD_CLK"]; #endif @@ -1546,12 +1597,45 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char LCD_DE[sizeof "LCD_DE"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_DE_ENABLE[sizeof "LCD_DE_ENABLE"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_FIELD[sizeof "LCD_FIELD"]; +#endif #if defined(IPCHW_PADMUX_V4) char LCD_HS[sizeof "LCD_HS"]; #endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4A) char LCD_HSYNC[sizeof "LCD_HSYNC"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_HVLD_VVLD[sizeof "LCD_HVLD_VVLD"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_NO_HVSYNC[sizeof "LCD_NO_HVSYNC"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_PARALLE_RGB565[sizeof "LCD_PARALLE_RGB565"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_PARALLE_RGB666[sizeof "LCD_PARALLE_RGB666"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_PARALLE_RGB888[sizeof "LCD_PARALLE_RGB888"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_RGB_16BITS[sizeof "LCD_RGB_16BITS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_SERIAL_RGB_6BITS[sizeof "LCD_SERIAL_RGB_6BITS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_SERIAL_RGB_8BITS[sizeof "LCD_SERIAL_RGB_8BITS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char LCD_TE_ENABLE[sizeof "LCD_TE_ENABLE"]; +#endif #if defined(IPCHW_PADMUX_V4) char LCD_VS[sizeof "LCD_VS"]; #endif @@ -1600,9 +1684,54 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char L_GPIO1[sizeof "L_GPIO1"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO10[sizeof "L_GPIO10"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO11[sizeof "L_GPIO11"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO12[sizeof "L_GPIO12"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO13[sizeof "L_GPIO13"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO14[sizeof "L_GPIO14"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO15[sizeof "L_GPIO15"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO16[sizeof "L_GPIO16"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO17[sizeof "L_GPIO17"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO18[sizeof "L_GPIO18"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO19[sizeof "L_GPIO19"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char L_GPIO2[sizeof "L_GPIO2"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO20[sizeof "L_GPIO20"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO21[sizeof "L_GPIO21"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO22[sizeof "L_GPIO22"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO23[sizeof "L_GPIO23"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char L_GPIO24[sizeof "L_GPIO24"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char L_GPIO3[sizeof "L_GPIO3"]; #endif @@ -1633,6 +1762,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char MCLK_PORTA[sizeof "MCLK_PORTA"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char MDC[sizeof "MDC"]; +#endif #if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char MDCK[sizeof "MDCK"]; #endif @@ -1642,7 +1774,7 @@ struct padmux_names { #if defined(IPCHW_PADMUX_3536C) char MDCK1[sizeof "MDCK1"]; #endif -#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_NOVATEK) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) char MDIO[sizeof "MDIO"]; #endif #if defined(IPCHW_PADMUX_3536C) @@ -1912,6 +2044,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char MSC1_PORTC[sizeof "MSC1_PORTC"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char NAND_1CS[sizeof "NAND_1CS"]; +#endif #if defined(IPCHW_PADMUX_V2A) char NF_ALE[sizeof "NF_ALE"]; #endif @@ -4081,6 +4216,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char PWM10_3[sizeof "PWM10_3"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char PWM10_4[sizeof "PWM10_4"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char PWM10_5[sizeof "PWM10_5"]; #endif @@ -4420,6 +4558,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char PWM8_3[sizeof "PWM8_3"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char PWM8_4[sizeof "PWM8_4"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char PWM8_5[sizeof "PWM8_5"]; #endif @@ -4459,6 +4600,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char PWM9_3[sizeof "PWM9_3"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char PWM9_4[sizeof "PWM9_4"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char PWM9_5[sizeof "PWM9_5"]; #endif @@ -4639,6 +4783,12 @@ struct padmux_names { #if defined(IPCHW_PADMUX_INGENIC) char RD[sizeof "RD"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char REFCLK[sizeof "REFCLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char REMOTE_CH3[sizeof "REMOTE_CH3"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char REMOTE_EXT[sizeof "REMOTE_EXT"]; #endif @@ -4906,6 +5056,27 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) char RTC_TEST_CLK[sizeof "RTC_TEST_CLK"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RXD0[sizeof "RXD0"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RXD1[sizeof "RXD1"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RXD2[sizeof "RXD2"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RXD3[sizeof "RXD3"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RX_CLK[sizeof "RX_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RX_CTL[sizeof "RX_CTL"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char RX_ER[sizeof "RX_ER"]; +#endif #if defined(IPCHW_PADMUX_INGENIC) char SA0[sizeof "SA0"]; #endif @@ -5194,6 +5365,12 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char SDIO3_D7[sizeof "SDIO3_D7"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SDIO_4BITS[sizeof "SDIO_4BITS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SDIO_8BITS[sizeof "SDIO_8BITS"]; +#endif #if defined(IPCHW_PADMUX_V1) char SDIO_CARD_DETECT[sizeof "SDIO_CARD_DETECT"]; #endif @@ -5305,6 +5482,12 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char SENSOR2_CCIR8BITS[sizeof "SENSOR2_CCIR8BITS"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR2_CCIR8BITS_FIELD[sizeof "SENSOR2_CCIR8BITS_FIELD"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR2_CCIR8BITS_VDHD[sizeof "SENSOR2_CCIR8BITS_VDHD"]; +#endif #if defined(IPCHW_PADMUX_V5) char SENSOR2_CLK[sizeof "SENSOR2_CLK"]; #endif @@ -5359,6 +5542,21 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) char SENSOR_RSTN[sizeof "SENSOR_RSTN"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR_SP2CLK[sizeof "SENSOR_SP2CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR_SP2CLK_2ND[sizeof "SENSOR_SP2CLK_2ND"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR_SPCLK[sizeof "SENSOR_SPCLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR_SPCLK_2ND[sizeof "SENSOR_SPCLK_2ND"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SENSOR_SPCLK_3RD[sizeof "SENSOR_SPCLK_3RD"]; +#endif #if defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) char SENSOR_VS[sizeof "SENSOR_VS"]; #endif @@ -5701,6 +5899,42 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V5) char SPI3_SDO[sizeof "SPI3_SDO"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_1_CLK[sizeof "SPI4_1_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_1_CS[sizeof "SPI4_1_CS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_1_DI[sizeof "SPI4_1_DI"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_1_DO[sizeof "SPI4_1_DO"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_2_CLK[sizeof "SPI4_2_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_2_CS[sizeof "SPI4_2_CS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_2_DI[sizeof "SPI4_2_DI"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI4_2_DO[sizeof "SPI4_2_DO"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI5_1_CLK[sizeof "SPI5_1_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI5_1_CS[sizeof "SPI5_1_CS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI5_1_DI[sizeof "SPI5_1_DI"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI5_1_DO[sizeof "SPI5_1_DO"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char SPICSZ1_GPIO_0[sizeof "SPICSZ1_GPIO_0"]; #endif @@ -5767,6 +6001,18 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V5) char SPI_3WIRE_DATA[sizeof "SPI_3WIRE_DATA"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI_3_CLK[sizeof "SPI_3_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI_3_CS[sizeof "SPI_3_CS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI_3_DI[sizeof "SPI_3_DI"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char SPI_3_DO[sizeof "SPI_3_DO"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char SPI_CH3_RDY[sizeof "SPI_CH3_RDY"]; #endif @@ -6091,6 +6337,15 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char S_GPIO1[sizeof "S_GPIO1"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char S_GPIO10[sizeof "S_GPIO10"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char S_GPIO11[sizeof "S_GPIO11"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char S_GPIO12[sizeof "S_GPIO12"]; +#endif #if defined(IPCHW_PADMUX_NOVATEK) char S_GPIO2[sizeof "S_GPIO2"]; #endif @@ -6112,6 +6367,9 @@ struct padmux_names { #if defined(IPCHW_PADMUX_NOVATEK) char S_GPIO8[sizeof "S_GPIO8"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char S_GPIO9[sizeof "S_GPIO9"]; +#endif #if defined(IPCHW_PADMUX_INGENIC) char TCK[sizeof "TCK"]; #endif @@ -6289,6 +6547,27 @@ struct padmux_names { #if defined(IPCHW_PADMUX_SSTAR) char TTL_MODE_2[sizeof "TTL_MODE_2"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TXD0[sizeof "TXD0"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TXD1[sizeof "TXD1"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TXD2[sizeof "TXD2"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TXD3[sizeof "TXD3"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TX_CLK[sizeof "TX_CLK"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TX_CTL[sizeof "TX_CTL"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char TX_EN[sizeof "TX_EN"]; +#endif #if defined(IPCHW_PADMUX_INGENIC) char UART0_CTS[sizeof "UART0_CTS"]; #endif @@ -6526,6 +6805,30 @@ struct padmux_names { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) char UART4_TXD[sizeof "UART4_TXD"]; #endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH3_4TH[sizeof "UART_CH3_4TH"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH3_5TH[sizeof "UART_CH3_5TH"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH4_2ND[sizeof "UART_CH4_2ND"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH4_CTSRTS[sizeof "UART_CH4_CTSRTS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH4_DIROE[sizeof "UART_CH4_DIROE"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH6[sizeof "UART_CH6"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH6_CTSRTS[sizeof "UART_CH6_CTSRTS"]; +#endif +#if defined(IPCHW_PADMUX_NOVATEK) + char UART_CH6_DIROE[sizeof "UART_CH6_DIROE"]; +#endif #if defined(IPCHW_PADMUX_SSTAR) char UART_IS_GPIO_0[sizeof "UART_IS_GPIO_0"]; #endif @@ -7240,6 +7543,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) #define PMX_CLK_TEST_OUT3 ((uint16_t)offsetof(struct padmux_names, CLK_TEST_OUT3)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_CRS_DV ((uint16_t)offsetof(struct padmux_names, CRS_DV)) +#endif #if defined(IPCHW_PADMUX_INGENIC) #define PMX_CS2 ((uint16_t)offsetof(struct padmux_names, CS2)) #endif @@ -7544,6 +7850,9 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_D_GPIO1 ((uint16_t)offsetof(struct padmux_names, D_GPIO1)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_D_GPIO10 ((uint16_t)offsetof(struct padmux_names, D_GPIO10)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_D_GPIO2 ((uint16_t)offsetof(struct padmux_names, D_GPIO2)) #endif #if defined(IPCHW_PADMUX_NOVATEK) @@ -7561,6 +7870,12 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_NOVATEK) #define PMX_D_GPIO7 ((uint16_t)offsetof(struct padmux_names, D_GPIO7)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_D_GPIO8 ((uint16_t)offsetof(struct padmux_names, D_GPIO8)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_D_GPIO9 ((uint16_t)offsetof(struct padmux_names, D_GPIO9)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_EJ_MODE_1 ((uint16_t)offsetof(struct padmux_names, EJ_MODE_1)) #endif @@ -7694,6 +8009,9 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_ETH_MODE_3 ((uint16_t)offsetof(struct padmux_names, ETH_MODE_3)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_ETH_PHYCLK ((uint16_t)offsetof(struct padmux_names, ETH_PHYCLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_ETH_RMII ((uint16_t)offsetof(struct padmux_names, ETH_RMII)) #endif #if defined(IPCHW_PADMUX_NOVATEK) @@ -8371,12 +8689,30 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_I2C3_SDA ((uint16_t)offsetof(struct padmux_names, I2C3_SDA)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C4_1_SCL ((uint16_t)offsetof(struct padmux_names, I2C4_1_SCL)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C4_1_SDA ((uint16_t)offsetof(struct padmux_names, I2C4_1_SDA)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C4_2_SCL ((uint16_t)offsetof(struct padmux_names, I2C4_2_SCL)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C4_2_SDA ((uint16_t)offsetof(struct padmux_names, I2C4_2_SDA)) +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_I2C4_SCL ((uint16_t)offsetof(struct padmux_names, I2C4_SCL)) #endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_I2C4_SDA ((uint16_t)offsetof(struct padmux_names, I2C4_SDA)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C5_1_SCL ((uint16_t)offsetof(struct padmux_names, I2C5_1_SCL)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2C5_1_SDA ((uint16_t)offsetof(struct padmux_names, I2C5_1_SDA)) +#endif #if defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_I2C5_SCL ((uint16_t)offsetof(struct padmux_names, I2C5_SCL)) #endif @@ -8449,6 +8785,12 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_3536C) #define PMX_I2S2_WS_TX ((uint16_t)offsetof(struct padmux_names, I2S2_WS_TX)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2S_1_MCLK ((uint16_t)offsetof(struct padmux_names, I2S_1_MCLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_I2S_2_MCLK ((uint16_t)offsetof(struct padmux_names, I2S_2_MCLK)) +#endif #if defined(IPCHW_PADMUX_INGENIC) #define PMX_I2S_ADC_BCLK ((uint16_t)offsetof(struct padmux_names, I2S_ADC_BCLK)) #endif @@ -8626,6 +8968,18 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_JTAG_TRSTN ((uint16_t)offsetof(struct padmux_names, JTAG_TRSTN)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_CCIR601 ((uint16_t)offsetof(struct padmux_names, LCD_CCIR601)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_CCIR601_16BITS ((uint16_t)offsetof(struct padmux_names, LCD_CCIR601_16BITS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_CCIR656 ((uint16_t)offsetof(struct padmux_names, LCD_CCIR656)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_CCIR656_16BITS ((uint16_t)offsetof(struct padmux_names, LCD_CCIR656_16BITS)) +#endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_LCD_CLK ((uint16_t)offsetof(struct padmux_names, LCD_CLK)) #endif @@ -8704,12 +9058,45 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_LCD_DE ((uint16_t)offsetof(struct padmux_names, LCD_DE)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_DE_ENABLE ((uint16_t)offsetof(struct padmux_names, LCD_DE_ENABLE)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_FIELD ((uint16_t)offsetof(struct padmux_names, LCD_FIELD)) +#endif #if defined(IPCHW_PADMUX_V4) #define PMX_LCD_HS ((uint16_t)offsetof(struct padmux_names, LCD_HS)) #endif #if defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4A) #define PMX_LCD_HSYNC ((uint16_t)offsetof(struct padmux_names, LCD_HSYNC)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_HVLD_VVLD ((uint16_t)offsetof(struct padmux_names, LCD_HVLD_VVLD)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_NO_HVSYNC ((uint16_t)offsetof(struct padmux_names, LCD_NO_HVSYNC)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_PARALLE_RGB565 ((uint16_t)offsetof(struct padmux_names, LCD_PARALLE_RGB565)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_PARALLE_RGB666 ((uint16_t)offsetof(struct padmux_names, LCD_PARALLE_RGB666)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_PARALLE_RGB888 ((uint16_t)offsetof(struct padmux_names, LCD_PARALLE_RGB888)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_RGB_16BITS ((uint16_t)offsetof(struct padmux_names, LCD_RGB_16BITS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_SERIAL_RGB_6BITS ((uint16_t)offsetof(struct padmux_names, LCD_SERIAL_RGB_6BITS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_SERIAL_RGB_8BITS ((uint16_t)offsetof(struct padmux_names, LCD_SERIAL_RGB_8BITS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_LCD_TE_ENABLE ((uint16_t)offsetof(struct padmux_names, LCD_TE_ENABLE)) +#endif #if defined(IPCHW_PADMUX_V4) #define PMX_LCD_VS ((uint16_t)offsetof(struct padmux_names, LCD_VS)) #endif @@ -8759,9 +9146,54 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_L_GPIO1 ((uint16_t)offsetof(struct padmux_names, L_GPIO1)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO10 ((uint16_t)offsetof(struct padmux_names, L_GPIO10)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO11 ((uint16_t)offsetof(struct padmux_names, L_GPIO11)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO12 ((uint16_t)offsetof(struct padmux_names, L_GPIO12)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO13 ((uint16_t)offsetof(struct padmux_names, L_GPIO13)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO14 ((uint16_t)offsetof(struct padmux_names, L_GPIO14)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO15 ((uint16_t)offsetof(struct padmux_names, L_GPIO15)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO16 ((uint16_t)offsetof(struct padmux_names, L_GPIO16)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO17 ((uint16_t)offsetof(struct padmux_names, L_GPIO17)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO18 ((uint16_t)offsetof(struct padmux_names, L_GPIO18)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO19 ((uint16_t)offsetof(struct padmux_names, L_GPIO19)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_L_GPIO2 ((uint16_t)offsetof(struct padmux_names, L_GPIO2)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO20 ((uint16_t)offsetof(struct padmux_names, L_GPIO20)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO21 ((uint16_t)offsetof(struct padmux_names, L_GPIO21)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO22 ((uint16_t)offsetof(struct padmux_names, L_GPIO22)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO23 ((uint16_t)offsetof(struct padmux_names, L_GPIO23)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_L_GPIO24 ((uint16_t)offsetof(struct padmux_names, L_GPIO24)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_L_GPIO3 ((uint16_t)offsetof(struct padmux_names, L_GPIO3)) #endif #if defined(IPCHW_PADMUX_NOVATEK) @@ -8791,6 +9223,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_MCLK_PORTA ((uint16_t)offsetof(struct padmux_names, MCLK_PORTA)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_MDC ((uint16_t)offsetof(struct padmux_names, MDC)) +#endif #if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_MDCK ((uint16_t)offsetof(struct padmux_names, MDCK)) #endif @@ -8800,7 +9235,7 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_3536C) #define PMX_MDCK1 ((uint16_t)offsetof(struct padmux_names, MDCK1)) #endif -#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) +#if defined(IPCHW_PADMUX_3536D) || defined(IPCHW_PADMUX_NOVATEK) || defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) || defined(IPCHW_PADMUX_V5) #define PMX_MDIO ((uint16_t)offsetof(struct padmux_names, MDIO)) #endif #if defined(IPCHW_PADMUX_3536C) @@ -9070,6 +9505,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_INGENIC) #define PMX_MSC1_PORTC ((uint16_t)offsetof(struct padmux_names, MSC1_PORTC)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_NAND_1CS ((uint16_t)offsetof(struct padmux_names, NAND_1CS)) +#endif #if defined(IPCHW_PADMUX_V2A) #define PMX_NF_ALE ((uint16_t)offsetof(struct padmux_names, NF_ALE)) #endif @@ -11240,6 +11678,9 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_PWM10_3 ((uint16_t)offsetof(struct padmux_names, PWM10_3)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_PWM10_4 ((uint16_t)offsetof(struct padmux_names, PWM10_4)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_PWM10_5 ((uint16_t)offsetof(struct padmux_names, PWM10_5)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -11579,6 +12020,9 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_PWM8_3 ((uint16_t)offsetof(struct padmux_names, PWM8_3)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_PWM8_4 ((uint16_t)offsetof(struct padmux_names, PWM8_4)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_PWM8_5 ((uint16_t)offsetof(struct padmux_names, PWM8_5)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -11618,6 +12062,9 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_PWM9_3 ((uint16_t)offsetof(struct padmux_names, PWM9_3)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_PWM9_4 ((uint16_t)offsetof(struct padmux_names, PWM9_4)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_PWM9_5 ((uint16_t)offsetof(struct padmux_names, PWM9_5)) #endif #if defined(IPCHW_PADMUX_SSTAR) @@ -11798,6 +12245,12 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_RD ((uint16_t)offsetof(struct padmux_names, RD)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_REFCLK ((uint16_t)offsetof(struct padmux_names, REFCLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_REMOTE_CH3 ((uint16_t)offsetof(struct padmux_names, REMOTE_CH3)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_REMOTE_EXT ((uint16_t)offsetof(struct padmux_names, REMOTE_EXT)) #endif #if defined(IPCHW_PADMUX_NOVATEK) @@ -12064,6 +12517,27 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V1) || defined(IPCHW_PADMUX_V2A) #define PMX_RTC_TEST_CLK ((uint16_t)offsetof(struct padmux_names, RTC_TEST_CLK)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RXD0 ((uint16_t)offsetof(struct padmux_names, RXD0)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RXD1 ((uint16_t)offsetof(struct padmux_names, RXD1)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RXD2 ((uint16_t)offsetof(struct padmux_names, RXD2)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RXD3 ((uint16_t)offsetof(struct padmux_names, RXD3)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RX_CLK ((uint16_t)offsetof(struct padmux_names, RX_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RX_CTL ((uint16_t)offsetof(struct padmux_names, RX_CTL)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_RX_ER ((uint16_t)offsetof(struct padmux_names, RX_ER)) +#endif #if defined(IPCHW_PADMUX_INGENIC) #define PMX_SA0 ((uint16_t)offsetof(struct padmux_names, SA0)) #endif @@ -12352,6 +12826,12 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_NOVATEK) #define PMX_SDIO3_D7 ((uint16_t)offsetof(struct padmux_names, SDIO3_D7)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SDIO_4BITS ((uint16_t)offsetof(struct padmux_names, SDIO_4BITS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SDIO_8BITS ((uint16_t)offsetof(struct padmux_names, SDIO_8BITS)) +#endif #if defined(IPCHW_PADMUX_V1) #define PMX_SDIO_CARD_DETECT ((uint16_t)offsetof(struct padmux_names, SDIO_CARD_DETECT)) #endif @@ -12463,6 +12943,12 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_NOVATEK) #define PMX_SENSOR2_CCIR8BITS ((uint16_t)offsetof(struct padmux_names, SENSOR2_CCIR8BITS)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR2_CCIR8BITS_FIELD ((uint16_t)offsetof(struct padmux_names, SENSOR2_CCIR8BITS_FIELD)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR2_CCIR8BITS_VDHD ((uint16_t)offsetof(struct padmux_names, SENSOR2_CCIR8BITS_VDHD)) +#endif #if defined(IPCHW_PADMUX_V5) #define PMX_SENSOR2_CLK ((uint16_t)offsetof(struct padmux_names, SENSOR2_CLK)) #endif @@ -12517,6 +13003,21 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V2) || defined(IPCHW_PADMUX_V2A) || defined(IPCHW_PADMUX_V3) || defined(IPCHW_PADMUX_V4) #define PMX_SENSOR_RSTN ((uint16_t)offsetof(struct padmux_names, SENSOR_RSTN)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR_SP2CLK ((uint16_t)offsetof(struct padmux_names, SENSOR_SP2CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR_SP2CLK_2ND ((uint16_t)offsetof(struct padmux_names, SENSOR_SP2CLK_2ND)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR_SPCLK ((uint16_t)offsetof(struct padmux_names, SENSOR_SPCLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR_SPCLK_2ND ((uint16_t)offsetof(struct padmux_names, SENSOR_SPCLK_2ND)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SENSOR_SPCLK_3RD ((uint16_t)offsetof(struct padmux_names, SENSOR_SPCLK_3RD)) +#endif #if defined(IPCHW_PADMUX_V4) || defined(IPCHW_PADMUX_V4A) #define PMX_SENSOR_VS ((uint16_t)offsetof(struct padmux_names, SENSOR_VS)) #endif @@ -12859,6 +13360,42 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V5) #define PMX_SPI3_SDO ((uint16_t)offsetof(struct padmux_names, SPI3_SDO)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_1_CLK ((uint16_t)offsetof(struct padmux_names, SPI4_1_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_1_CS ((uint16_t)offsetof(struct padmux_names, SPI4_1_CS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_1_DI ((uint16_t)offsetof(struct padmux_names, SPI4_1_DI)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_1_DO ((uint16_t)offsetof(struct padmux_names, SPI4_1_DO)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_2_CLK ((uint16_t)offsetof(struct padmux_names, SPI4_2_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_2_CS ((uint16_t)offsetof(struct padmux_names, SPI4_2_CS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_2_DI ((uint16_t)offsetof(struct padmux_names, SPI4_2_DI)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI4_2_DO ((uint16_t)offsetof(struct padmux_names, SPI4_2_DO)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI5_1_CLK ((uint16_t)offsetof(struct padmux_names, SPI5_1_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI5_1_CS ((uint16_t)offsetof(struct padmux_names, SPI5_1_CS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI5_1_DI ((uint16_t)offsetof(struct padmux_names, SPI5_1_DI)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI5_1_DO ((uint16_t)offsetof(struct padmux_names, SPI5_1_DO)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_SPICSZ1_GPIO_0 ((uint16_t)offsetof(struct padmux_names, SPICSZ1_GPIO_0)) #endif @@ -12926,6 +13463,18 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_SPI_3WIRE_DATA ((uint16_t)offsetof(struct padmux_names, SPI_3WIRE_DATA)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI_3_CLK ((uint16_t)offsetof(struct padmux_names, SPI_3_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI_3_CS ((uint16_t)offsetof(struct padmux_names, SPI_3_CS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI_3_DI ((uint16_t)offsetof(struct padmux_names, SPI_3_DI)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_SPI_3_DO ((uint16_t)offsetof(struct padmux_names, SPI_3_DO)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_SPI_CH3_RDY ((uint16_t)offsetof(struct padmux_names, SPI_CH3_RDY)) #endif #if defined(IPCHW_PADMUX_3536C) @@ -13250,6 +13799,15 @@ static inline const char *padmux_name(uint16_t off) { #define PMX_S_GPIO1 ((uint16_t)offsetof(struct padmux_names, S_GPIO1)) #endif #if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_S_GPIO10 ((uint16_t)offsetof(struct padmux_names, S_GPIO10)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_S_GPIO11 ((uint16_t)offsetof(struct padmux_names, S_GPIO11)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_S_GPIO12 ((uint16_t)offsetof(struct padmux_names, S_GPIO12)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) #define PMX_S_GPIO2 ((uint16_t)offsetof(struct padmux_names, S_GPIO2)) #endif #if defined(IPCHW_PADMUX_NOVATEK) @@ -13270,6 +13828,9 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_NOVATEK) #define PMX_S_GPIO8 ((uint16_t)offsetof(struct padmux_names, S_GPIO8)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_S_GPIO9 ((uint16_t)offsetof(struct padmux_names, S_GPIO9)) +#endif #if defined(IPCHW_PADMUX_INGENIC) #define PMX_TCK ((uint16_t)offsetof(struct padmux_names, TCK)) #endif @@ -13447,6 +14008,27 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_SSTAR) #define PMX_TTL_MODE_2 ((uint16_t)offsetof(struct padmux_names, TTL_MODE_2)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TXD0 ((uint16_t)offsetof(struct padmux_names, TXD0)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TXD1 ((uint16_t)offsetof(struct padmux_names, TXD1)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TXD2 ((uint16_t)offsetof(struct padmux_names, TXD2)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TXD3 ((uint16_t)offsetof(struct padmux_names, TXD3)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TX_CLK ((uint16_t)offsetof(struct padmux_names, TX_CLK)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TX_CTL ((uint16_t)offsetof(struct padmux_names, TX_CTL)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_TX_EN ((uint16_t)offsetof(struct padmux_names, TX_EN)) +#endif #if defined(IPCHW_PADMUX_INGENIC) #define PMX_UART0_CTS ((uint16_t)offsetof(struct padmux_names, UART0_CTS)) #endif @@ -13684,6 +14266,30 @@ static inline const char *padmux_name(uint16_t off) { #if defined(IPCHW_PADMUX_V3A) || defined(IPCHW_PADMUX_V4A) #define PMX_UART4_TXD ((uint16_t)offsetof(struct padmux_names, UART4_TXD)) #endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH3_4TH ((uint16_t)offsetof(struct padmux_names, UART_CH3_4TH)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH3_5TH ((uint16_t)offsetof(struct padmux_names, UART_CH3_5TH)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH4_2ND ((uint16_t)offsetof(struct padmux_names, UART_CH4_2ND)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH4_CTSRTS ((uint16_t)offsetof(struct padmux_names, UART_CH4_CTSRTS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH4_DIROE ((uint16_t)offsetof(struct padmux_names, UART_CH4_DIROE)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH6 ((uint16_t)offsetof(struct padmux_names, UART_CH6)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH6_CTSRTS ((uint16_t)offsetof(struct padmux_names, UART_CH6_CTSRTS)) +#endif +#if defined(IPCHW_PADMUX_NOVATEK) +#define PMX_UART_CH6_DIROE ((uint16_t)offsetof(struct padmux_names, UART_CH6_DIROE)) +#endif #if defined(IPCHW_PADMUX_SSTAR) #define PMX_UART_IS_GPIO_0 ((uint16_t)offsetof(struct padmux_names, UART_IS_GPIO_0)) #endif diff --git a/src/reginfo.c b/src/reginfo.c index 0b837687..b90aa18c 100644 --- a/src/reginfo.c +++ b/src/reginfo.c @@ -3445,6 +3445,9 @@ static const muxctrl_reg_t **dump_regs_by_chip(void) { return T31_regs; #endif #ifdef IPCHW_VENDOR_NOVATEK + case CHIP_NA51055: + case CHIP_NA51084: + return NA51055_regs; case CHIP_NA51089: return NA51089_regs; #endif @@ -3473,6 +3476,8 @@ static uint32_t dump_mask(void) { case T23: case T31: case T40: + case CHIP_NA51055: + case CHIP_NA51084: case CHIP_NA51089: /* Not a selector at all: these are whole 32-bit registers and every * bit of them is worth printing. */ diff --git a/src/reginfo_test.c b/src/reginfo_test.c index 99b5c32f..dce2dbfa 100644 --- a/src/reginfo_test.c +++ b/src/reginfo_test.c @@ -1019,6 +1019,55 @@ static void test_novatek(void) { !strcmp(r.func_name, "ETH_RMII")); CHECK(ipchw_padmux_set(54, "UART2_2_TX") == IPCHW_PADMUX_NO_FUNC); + + puts("Novatek: the primary LCD, from pinmux_select_primary_lcd()"); + nvt_boot_state(); + /* PINMUX_LCD_SEL_PARALLE_RGB565: LCD_TYPE = LCDTYPE_ENUM_PARALLEL_LCD + * (3) in REG2[3:0], and L_GPIO1..8 handed over for the colour bits. */ + CHECK(ipchw_padmux_set(0x60 + 1, "LCD_PARALLE_RGB565") == 0); + CHECK((reg_of(0xF0010008u) & 0xF) == 3); + CHECK(reg_of(0xF00100B8u) == ~(1u << 1)); + CHECK(ipchw_padmux_get(0x60 + 1, &r) == 1 && + !strcmp(r.func_name, "LCD_PARALLE_RGB565")); + + /* A panel with DE: PLCD_DE (REG2 bit 6) set and L_GPIO0 handed over. + * Both the colour pin and the DE pin read as the LCD, and putting DE on + * its pin leaves the panel type where it is. */ + nvt_boot_state(); + fake_write(0xF0010008u, 3 | (1u << 6), 32); + fake_write(0xF00100B8u, ~3u, 32); + CHECK(ipchw_padmux_get(0x60 + 1, &r) == 1 && + !strcmp(r.func_name, "LCD_PARALLE_RGB565")); + CHECK(ipchw_padmux_get(0x60 + 0, &r) == 1 && + !strcmp(r.func_name, "LCD_DE_ENABLE")); + nvt_boot_state(); + fake_write(0xF0010008u, 3, 32); + CHECK(ipchw_padmux_set(0x60 + 0, "LCD_DE_ENABLE") == 0); + CHECK(reg_of(0xF0010008u) == (3 | (1u << 6))); + as_chip(T31, "T31"); +} + +/* One driver, two dies: the na51055 driver branches on the chip ID, and the + * two tables are what it does as each. */ +static void test_novatek_na51055_na51084(void) { + puts("Novatek: NA51055 and NA51084 from one driver"); + ipchw_padmux_t rows[8], r; + + as_chip(CHIP_NA51084, "NT98528"); + CHECK(ipchw_padmux_by_func("I2C4_1_SCL", rows, 8) >= 1); + CHECK(ipchw_padmux_by_func("TXD2", rows, 8) >= 1); /* RGMII */ + /* No DSI group on these dies. */ + CHECK(ipchw_padmux_get(0xE0 + 9, &r) == IPCHW_PADMUX_NO_PAD); + /* L_GPIO24 is bonded out here, and not on NA51089. */ + CHECK(ipchw_padmux_by_pad(0x60 + 24, rows, 8) >= 1); + + as_chip(CHIP_NA51055, "NA51055"); + CHECK(ipchw_padmux_by_func("I2C4_1_SCL", rows, 8) == 0); + CHECK(ipchw_padmux_by_func("SPI3_3_CLK", rows, 8) >= 1); + CHECK(ipchw_padmux_by_pad(0x60 + 24, rows, 8) >= 1); + + as_chip(CHIP_NA51089, "NT98566"); + CHECK(ipchw_padmux_by_pad(0x60 + 24, rows, 8) == 0); /* not a pad here */ as_chip(T31, "T31"); } @@ -1029,10 +1078,9 @@ static void test_novatek(void) { * field moved half-way unmuxes the peripheral from its other pads. */ #include "hal/novatek_padmux.h" -static void test_novatek_set_from_every_state(void) { - puts("Novatek: set() from every claim's state reads back or undoes"); - as_chip(CHIP_NA51089, "NT98566"); - const novatek_soc_t *soc = &NA51089_padmux; +static void novatek_set_from_every_state(int chip, const char *name, + const novatek_soc_t *soc) { + as_chip(chip, name); int done = 0, refused = 0; for (int i = 0; i < soc->nclaims; i++) { @@ -1085,10 +1133,17 @@ static void test_novatek_set_from_every_state(void) { } } } - printf(" (%d set, %d refused and undone)\n", done, refused); + printf(" %s: %d set, %d refused and undone\n", name, done, refused); CHECK(done > 0); as_chip(T31, "T31"); } + +static void test_novatek_set_from_every_state(void) { + puts("Novatek: set() from every claim's state reads back or undoes"); + novatek_set_from_every_state(CHIP_NA51089, "NT98566", &NA51089_padmux); + novatek_set_from_every_state(CHIP_NA51055, "NA51055", &NA51055_padmux); + novatek_set_from_every_state(CHIP_NA51084, "NT98528", &NA51084_padmux); +} #endif #ifdef IPCHW_VENDOR_NOVATEK @@ -1114,6 +1169,12 @@ static void test_novatek_gpio_regs(void) { CHECK(novatek_gpio_window(&base, &len)); CHECK(base == 0xF0070000u && len == 0x80); + /* NA51055 and NA51084: 13 S, 25 L and 11 D pads, and no DSI. */ + as_chip(CHIP_NA51084, "NT98528"); + CHECK(novatek_gpio_valid(0x60 + 24) && !novatek_gpio_valid(0x60 + 25)); + CHECK(novatek_gpio_valid(0x80 + 10) && !novatek_gpio_valid(0xE0)); + CHECK(novatek_gpio_reg(0x60 + 24, NVT_GPIO_DATA) == 0xF007000Cu); + as_chip(0, "none"); CHECK(!novatek_gpio_supported()); CHECK(novatek_gpio_reg(0, NVT_GPIO_DATA) == 0); @@ -1312,6 +1373,8 @@ static void test_table_integrity(void) { #endif #ifdef IPCHW_PADMUX_NOVATEK {CHIP_NA51089, "NT98566"}, + {CHIP_NA51055, "NA51055"}, + {CHIP_NA51084, "NT98528"}, #endif }; @@ -1459,6 +1522,7 @@ int main(void) { #endif #ifdef IPCHW_PADMUX_NOVATEK test_novatek(); + test_novatek_na51055_na51084(); test_novatek_set_from_every_state(); #endif #ifdef IPCHW_VENDOR_NOVATEK diff --git a/tools/gen_novatek_padmux.py b/tools/gen_novatek_padmux.py index 5175b868..ce041424 100755 --- a/tools/gen_novatek_padmux.py +++ b/tools/gen_novatek_padmux.py @@ -110,6 +110,25 @@ ("audio", "PIN_AUDIO_CFG"), ("eth", "PINMUX_ETH_CFG"), ("misc", "PINMUX_MISC_CFG"), + # Not a pinmux_config_*(): pinmux_select_primary_lcd(), which is what the + # display driver calls through pinmux_set_host(). Its argument is one LCD + # type plus feature flags, so it is run as each type with every set of + # flags rather than as combinations of bits. TV and HDMI have no pads to + # mux on these parts: pinmux_set_host() answers E_ID for both. + ("lcd", "PINMUX_LCD_SEL"), +] + +# The function a FUNCS entry calls, when it is not pinmux_config_(). +SPECIAL = {"lcd": "pinmux_select_primary_lcd"} + +# The drivers this runs, and the SoCs each is run as. The na51055 driver +# serves two dies and branches on nvt_get_chip_id() -- NA51084 refuses UART2's +# 3rd location, for one -- so it is run once as each, and each gets a table. +# The third field says whether build/nvt-tools/.../top.csv describes it: the +# csv is the NA51089 tool's. +FAMILIES = [ + ("na51089", [("NA51089", 0x7021)], True), + ("na51055", [("NA51055", 0x4821), ("NA51084", 0x5021)], False), ] # The groups whose GPIO writes are claims rather than releases. sensor and @@ -151,20 +170,43 @@ ] # Where the two vendor sources disagree with the code, and what was decided. -# Key: (option, pad as the source spells it). Value: the (option, pad) it -# means, or None to drop the annotation. +# Key: (family, option, pad as the source spells it). Value: the (option, +# pad) it means, or None to drop the annotation. ANNOTATION_ERRATA = { # top.csv only; top.h has P_GPIO19, and so does the code. - ("PIN_SIF_CFG_CH2_2ND_PINMUX", "P_GPIO29"): + ("na51089", "PIN_SIF_CFG_CH2_2ND_PINMUX", "P_GPIO29"): ("PIN_SIF_CFG_CH2_2ND_PINMUX", "P_GPIO19"), - # top.h only; the code and top.csv both put PICNT2_1 on L_GPIO1. - ("PIN_PWM_CFG_CCNT2", "P_GPIO14"): ("PIN_PWM_CFG_CCNT2", "L_GPIO1"), + # top.h only; the code and top.csv both put PICNT2_1 on L_GPIO1. On + # NA51055 the same annotation is right: its code uses P_GPIO14. + ("na51089", "PIN_PWM_CFG_CCNT2", "P_GPIO14"): + ("PIN_PWM_CFG_CCNT2", "L_GPIO1"), # pinmux_config_misc() tests PIN_SENSOR_CFG_SP2CLK_3RD where it means # this option, so this option does nothing at all. The same pad and field # are reached through the sensor group's SP2CLK_3RD, which top.h does not # annotate; the name goes there. - ("PIN_MISC_CFG_SP2CLK_3RD", "D_GPIO4"): + ("na51089", "PIN_MISC_CFG_SP2CLK_3RD", "D_GPIO4"): ("PIN_SENSOR_CFG_SP2CLK_3RD", "D_GPIO4"), + + # NA51055's top.h carries NA51089's MISC annotations; its own code puts + # the special clocks elsewhere, and has no 3rd SP_CLK location at all. + ("na51055", "PIN_MISC_CFG_SPCLK", "P_GPIO17"): + ("PIN_MISC_CFG_SPCLK", "L_GPIO20"), + ("na51055", "PIN_MISC_CFG_SPCLK_2ND", "L_GPIO23"): + ("PIN_MISC_CFG_SPCLK_2ND", "P_GPIO19"), + ("na51055", "PIN_MISC_CFG_SPCLK_3RD", "D_GPIO3"): None, + # As on NA51089, only the sensor group reaches SP_CLK2's 3rd location. + ("na51055", "PIN_MISC_CFG_SP2CLK_3RD", "D_GPIO4"): + ("PIN_SENSOR_CFG_SP2CLK_3RD", "D_GPIO4"), + ("na51055", "PIN_MISC_CFG_SP2CLK", "P_GPIO18"): + ("PIN_MISC_CFG_SP2CLK", "P_GPIO24"), + ("na51055", "PIN_MISC_CFG_SP2CLK_2ND", "MC9"): + ("PIN_MISC_CFG_SP2CLK_2ND", "P_GPIO15"), + # "52x compatible - donot support this function": the driver comments + # out the HSI location of PWM8..11 on NA51055. + ("na51055", "PIN_PWM_CFG_PWM8_3", "HSI_GPIO6"): None, + ("na51055", "PIN_PWM_CFG_PWM9_3", "HSI_GPIO7"): None, + ("na51055", "PIN_PWM_CFG2_PWM10_3", "HSI_GPIO8"): None, + ("na51055", "PIN_PWM_CFG2_PWM11_3", "HSI_GPIO9"): None, } # One annotation: PAD[NAME]. The csv has unclosed brackets and stray @@ -202,7 +244,11 @@ def pad_number(name): def option_label(option): - """PIN_SENSOR_CFG_12BITS -> SENSOR_12BITS.""" + """PIN_SENSOR_CFG_12BITS -> SENSOR_12BITS, PINMUX_LCD_SEL_CCIR656 -> + LCD_CCIR656.""" + m = re.match(r"^PINMUX_LCD_SEL_(\w+)$", option) + if m: + return "LCD_%s" % m.group(1) m = re.match(r"^PIN_(\w+?)_CFG2?_(\w+)$", option) if not m: die("cannot make a name of %s" % option) @@ -215,13 +261,14 @@ def option_label(option): class Sources: """The SDK files this reads, located from the SDK root.""" - def __init__(self, sdk): + def __init__(self, sdk, family="na51089"): kernel = os.path.join(sdk, "BSP", "linux-kernel") + self.family = family self.drv = os.path.join(kernel, "drivers", "pinctrl", "novatek", - "na51089") - self.host_c = os.path.join(self.drv, "na51089_pinmux_host.c") + family) + self.host_c = os.path.join(self.drv, "%s_pinmux_host.c" % family) self.plat = os.path.join(kernel, "arch", "arm", "plat-novatek", - "include", "plat-na51089") + "include", "plat-%s" % family) self.mach = os.path.join(kernel, "arch", "arm", "mach-nvt-ivot", "include", "mach") self.top_h = os.path.join(self.plat, "top.h") @@ -231,7 +278,7 @@ def __init__(self, sdk): for path in (self.host_c, self.top_h, self.gpio_h, os.path.join(self.mach, "rcw_macro.h")): if not os.path.isfile(path): - die("not an NA51089 SDK: no %s" % path) + die("not a %s SDK: no %s" % (family.upper(), path)) if not os.path.isfile(self.csv): self.csv = None @@ -252,19 +299,33 @@ def parse_enums(text): r"\s*(.*)$", line) if not mm or mm.group(1).startswith("ENUM_DUMMY"): continue - try: - val = int(mm.group(2), 0) if mm.group(2) else None - except ValueError: - val = None + val = enum_value(mm.group(2)) if mm.group(2) else None members.append((mm.group(1), val, mm.group(3))) out[m.group(2)] = members return out +def enum_value(expr): + """An enumerator's value: `0x40`, and also `0x01 << 23`, which is how + PINMUX_LCD_SEL spells its feature flags. Anything else -- another + enumerator's name, a macro -- is None, as a member with no value is.""" + expr = expr.strip() + if not re.match(r"^[0-9a-fA-FxX\s<|()]+$", expr): + return None + try: + return int(eval(expr, {"__builtins__": {}}, {})) + except Exception: + return None + + def option_bits(enums, enum_name): - """The options of one group that are a bit of their own, in order.""" + """The options of one group that are a bit of their own, in order. For + the LCD selector: its types, then its feature flags.""" if enum_name not in enums: die("top.h has no enum %s" % enum_name) + if enum_name == "PINMUX_LCD_SEL": + types, flags = lcd_options(enums) + return types + flags seen = set() bits = [] for name, val, _ in enums[enum_name]: @@ -274,7 +335,21 @@ def option_bits(enums, enum_name): return bits -def annotations(enums, csv_text): +def lcd_options(enums): + """PINMUX_LCD_SEL's types -- the members with implicit values, which + count from 0 -- and its feature flags, the ones with explicit values. + A mask is neither.""" + types, flags = [], [] + for name, val, _ in enums["PINMUX_LCD_SEL"]: + if name.endswith("_MSK"): + continue + (types if val is None else flags).append(name) + if not flags: + die("PINMUX_LCD_SEL has no feature flags this can read") + return types, flags + + +def annotations(enums, csv_text, family="na51089"): """{(func or None, option, pad): name} and the list of what was found. top.h annotations hold for every group that takes the option; the csv's @@ -284,7 +359,7 @@ def annotations(enums, csv_text): found = [] def add(func, option, pad_raw, name_raw): - key = (option, pad_raw.strip().upper()) + key = (family, option, pad_raw.strip().upper()) if key in ANNOTATION_ERRATA: if ANNOTATION_ERRATA[key] is None: return @@ -326,6 +401,10 @@ def bonded_pads(gpio_h_text): for _, prefix, _, macro in GROUPS: m = re.search(r"#define\s+%s\s+(\d+)" % macro, gpio_h_text) if not m: + # NA51055 has no DSI group. Any other group missing is a + # renamed macro, and would drop every pad of it unseen. + if macro == "DSI_GPIO_NUM": + continue die("nvt-gpio.h has no %s" % macro) pads.extend("%s%d" % (prefix, i) for i in range(int(m.group(1)))) return pads @@ -336,7 +415,22 @@ def bonded_pads(gpio_h_text): ASSIGN = re.compile(r"\b(top_reg\w+)\.bit\.(\w+)\s*=(?!=)\s*([^;]+);") OTHER_WRITE = re.compile( r"\btop_reg\w+\.(?:bit\.\w+|reg)\s*(?:[-+*/&|^]|<<|>>)?=(?!=)") -CASE = re.compile(r"\bcase\s+(PIN_\w+)\s*:") +CASE = re.compile(r"\bcase\s+(PIN(?:MUX)?_\w+)\s*:") + +# The options a block's header tests: `config & PIN_X`, `pinmux & +# (PIN_A | PIN_B)`. Only a bit test names a block's option. A range test -- +# `(pinmux_type >= PINMUX_LCD_SEL_CCIR656) && (pinmux_type <= ...)` -- names +# the ends of a range, and an `==` test against the group's NONE opens an +# empty block. +TESTED = re.compile(r"(? final value in place self.blocks = {} # block -> {Field: last value written in it} - self.gates = {} # pad -> (0 function / 1 GPIO, rec id) + self.gates = {} # pad -> (0 function / 1 GPIO, rec id, seq) + self.writes = {} # Field -> [(seq, value, block, rec id)] + self.seq = 0 self.regs = None # register offset -> final value @@ -683,11 +825,14 @@ def parse_runs(out, enums, recs): if mask & (mask - 1): die("a multi-bit gate write at %#x" % ofs) pad = "%s%d" % (GATE_REGS[ofs][1], field_shift(mask)) - cur.gates[pad] = (1 if val else 0, rid) + cur.gates[pad] = (1 if val else 0, rid, cur.seq) else: f = Field(ofs, mask) cur.fields[f] = val cur.blocks.setdefault(recs[rid].path[-1], {})[f] = val + cur.writes.setdefault(f, []).append( + (cur.seq, val, recs[rid].path[-1], rid)) + cur.seq += 1 elif tag == "E": if int(rest) == 0: regs = collections.defaultdict(int) @@ -709,8 +854,11 @@ def __init__(self, pad, name, conds, ungated): self.ungated = ungated def sort_key(self): - return (pad_number(self.pad), -len(self.conds), self.name, - self.conds, self.ungated) + # Most conditions first; then, of two alike, the gated one, whose + # cleared gate is one more piece of evidence -- CCIR8 data and CCIR8 + # sync both hold under SENSOR2=2, and a handed-over pad is the sync. + return (pad_number(self.pad), -len(self.conds), self.ungated, + self.name, self.conds) def holds(self, regs, gate): return (self.ungated or gate == 0) and all( @@ -731,6 +879,7 @@ def __init__(self, runs, recs, names, bonded): self.order = {f: i for i, (f, _) in enumerate(FUNCS)} self.claims = {} # pad -> [Claim], resolver order self.chosen = {} # (pad, conds, ungated) -> (unnamed?, name) + self.chosen_by = {} # ... -> FUNCS index of the group named it self.explained = set() # (option, pad) the code touches self.problems = [] self.conflicts = 0 # states where two claims hold at once @@ -741,16 +890,41 @@ def own(self, run, pad): (conds, ungated, rec), or None for a pad it leaves a GPIO.""" if pad not in run.gates: return None - val, rid = run.gates[pad] + val, rid, seq = run.gates[pad] rec = self.recs[rid] if rec.func != run.func: return PREFIX if val == 1 and run.func not in UNGATED_FUNCS: return None + return tuple(sorted(self.conds_at(run, rec, seq).items())), \ + val == 1, rec + + @staticmethod + def conds_at(run, rec, seq): + """The fields a gate write at `seq` depends on, and their values. + + A field counts when a block enclosing the gate write writes it, and + it takes the value the last such write gave it -- UART2 = 2 comes + after its pads' gates in the same block and still counts. One + exception. A field an enclosing block wrote and a block NESTED in it + then overwrote, both before the gate write, takes the nested value: + pinmux_select_primary_lcd() resets LCD_TYPE to GPIO at its top, sets + it per type in a switch, and only then hands over the pads.""" + enclosing = set(rec.path) conds = {} - for blk in rec.path: - conds.update(run.blocks.get(blk, {})) - return tuple(sorted(conds.items())), val == 1, rec + for f, writes in run.writes.items(): + own = [w for w in writes if w[2] in enclosing] + if not own: + continue + value = own[-1][1] + before = [w for w in writes if w[0] < seq] + own_before = [w for w in own if w[0] < seq] + if (before and before[-1][2] not in enclosing and own_before and + before[-1][0] > own_before[-1][0] and + not any(w[0] > seq for w in own)): + value = before[-1][1] + conds[f] = value + return conds def name_for(self, run, pad, rec): """(unnamed?, name): the enclosing options innermost first, then the @@ -762,6 +936,8 @@ def name_for(self, run, pad, rec): return (False, n) if rec.chain: return (True, option_label(rec.chain[0])) + if run.func == "lcd": + return (True, option_label(run.opts[0])) # the type, not a flag return (True, option_label(run.opts[-1])) def add(self, pad, name, conds, ungated): @@ -799,8 +975,9 @@ def build(self): if len(named) > 1: self.problems.append("%s is %s under the same writes" % (key[0], " and ".join(sorted(named)))) - u, _, n = min(cands) + u, order, n = min(cands) self.chosen[key] = (u, n) + self.chosen_by[key] = order # A state nothing names inherits the name of the state it extends: # SPI_CFG_CH1_2BITS on its own does everything CH1 does plus SPI_DAT, @@ -812,6 +989,11 @@ def build(self): pad, conds, ungated = key best = None for other, (u, name) in self.chosen.items(): + # Only within one group: NA51055's RMII claims L_GPIO0 with + # no condition at all, and an empty set is a subset of every + # LCD state on that pad. + if self.chosen_by[other] != self.chosen_by[key]: + continue if (not u and other[0] == pad and other[2] == ungated and len(other[1]) < len(conds) and set(other[1]) <= set(conds) and @@ -841,7 +1023,7 @@ def replay(self): if any(c.ungated for c in lst)} for run in self.runs: for pad in sorted((set(run.gates) | ungated_pads) & self.bonded): - gate = run.gates.get(pad, (1, None))[0] + gate = run.gates.get(pad, (1,))[0] held = [c for c in self.claims.get(pad, ()) if c.holds(run.regs, gate)] held_names = {c.name for c in held} @@ -886,6 +1068,10 @@ def replay(self): % (pad, list(run.opts), res.name, want)) elif res: added += 1 + else: + self.problems.append( + "%s after %s reads as %s, and %s cannot be made to " + "win" % (pad, list(run.opts), held[0].name, want)) return added def check_annotations(self, found): @@ -965,7 +1151,8 @@ def packed(f, v): return f.reg, shift, width, v >> shift -def render(model, bonded, regen): +def render_soc(chip, model, bonded): + """One SoC's four tables and its novatek_soc_t, `chip`_padmux.""" pads = sorted(model.claims, key=pad_number) conds = [] index = {} @@ -981,32 +1168,21 @@ def render(model, bonded, regen): sel = pick_selectors(model.claims) o = [] - o.append("""/* Generated by tools/gen_novatek_padmux.py -- do not edit. - * - * What the vendor's pinmux_config_*() functions do to each pad of the - * NA51089, found by running them: see the generator for how, and - * src/hal/novatek_padmux.c for how the table is read. %d vendor states - * were replayed against it; in %d of them two claims hold at once and the - * table carries the one the vendor code meant, and %d leave a pad cleared - * with its field moved elsewhere, which reads as unnamed. - * - * Regenerate with: - * %s - */ - -#ifndef HAL_NOVATEK_PADMUX_H -#define HAL_NOVATEK_PADMUX_H - -#include "hal/novatek_padmux_types.h" -""" % (len(model.runs), model.conflicts, model.orphans, regen)) + o.append("/* %s: %d vendor states replayed; in %d of them two claims hold" + % (chip, len(model.runs), model.conflicts)) + o.append(" * at once and the table carries the one the vendor code meant,") + o.append(" * and %d leave a pad cleared with its field moved elsewhere," + % model.orphans) + o.append(" * which reads as unnamed. */") + o.append("") o.append("/* Every pad the package bonds out, by Linux GPIO number. */") - o.append("static const novatek_pad_t NA51089_pads[] = {") + o.append("static const novatek_pad_t %s_pads[] = {" % chip) for p in bonded: o.append(" {%d, PMX_%s}," % (pad_number(p), p)) o.append("};") o.append("") o.append("/* TOP register offset, field shift, width, value. */") - o.append("static const novatek_cond_t NA51089_conds[] = {") + o.append("static const novatek_cond_t %s_conds[] = {" % chip) for f, v in conds: o.append(" {0x%02X, %d, %d, %d}," % packed(f, v)) o.append("};") @@ -1014,7 +1190,7 @@ def render(model, bonded, regen): o.append("/* Per pad, most conditions first: the first claim that holds") o.append(" * is what the pad carries. {pad, flags, name, first") o.append(" * condition, how many}. */") - o.append("static const novatek_claim_t NA51089_claims[] = {") + o.append("static const novatek_claim_t %s_claims[] = {" % chip) for c, idx in rows: o.append(" {%d, %s, PMX_%s, %d, %d}, /* %s */" % ( pad_number(c.pad), "NVT_UNGATED" if c.ungated else "0", @@ -1023,7 +1199,7 @@ def render(model, bonded, regen): o.append("") o.append("/* The field each function's walk row shows: {pad, name, reg,") o.append(" * shift, width, value}, reg NVT_GATE for the pad's gate bit. */") - o.append("static const novatek_sel_t NA51089_sels[] = {") + o.append("static const novatek_sel_t %s_sels[] = {" % chip) nsels = 0 for pad in pads: done = set() @@ -1042,12 +1218,35 @@ def render(model, bonded, regen): nsels += 1 o.append("};") o.append("") - o.append("static const novatek_soc_t NA51089_padmux = {") - o.append(" NA51089_pads, %d, NA51089_claims, %d, NA51089_conds," - % (len(bonded), len(rows))) - o.append(" NA51089_sels, %d," % nsels) + o.append("static const novatek_soc_t %s_padmux = {" % chip) + o.append(" %s_pads, %d, %s_claims, %d, %s_conds," + % (chip, len(bonded), chip, len(rows), chip)) + o.append(" %s_sels, %d," % (chip, nsels)) o.append("};") - o.append("") + return o + + +def render(socs, regen): + o = [] + o.append("""/* Generated by tools/gen_novatek_padmux.py -- do not edit. + * + * What the vendor's pinmux_config_*() and pinmux_select_primary_lcd() do to + * each pad, found by running them: see the generator for how, and + * src/hal/novatek_padmux.c for how the tables are read. One table per die; + * NA51055 and NA51084 come from one driver run as each. + * + * Regenerate with: + * %s + */ + +#ifndef HAL_NOVATEK_PADMUX_H +#define HAL_NOVATEK_PADMUX_H + +#include "hal/novatek_padmux_types.h" +""" % regen) + for chip, model, bonded in socs: + o.extend(render_soc(chip, model, bonded)) + o.append("") o.append("#endif /* HAL_NOVATEK_PADMUX_H */") return "\n".join(o) + "\n" @@ -1056,19 +1255,41 @@ def render(model, bonded, regen): def generate(sdk): - src = Sources(sdk) - enums = parse_enums(read(src.top_h)) - bonded = bonded_pads(read(src.gpio_h)) - names, found = annotations(enums, read(src.csv) if src.csv else "") - recs = [] - out = run_harness(src, enums, recs) - runs = parse_runs(out, enums, recs) - model = Model(runs, recs, names, bonded) - model.build() - model.check_annotations(found) - if model.problems: - die("the sources disagree:\n " + "\n ".join(model.problems[:40])) - return render(model, bonded, REGEN), model + """Every family the SDK carries, each run as every die it serves. + Returns the header and {chip: Model}.""" + socs = [] + models = {} + problems = [] + for family, chips, uses_csv in FAMILIES: + src = Sources(sdk, family) + enums = parse_enums(read(src.top_h)) + bonded = bonded_pads(read(src.gpio_h)) + csv = read(src.csv) if uses_csv and src.csv else "" + names, found = annotations(enums, csv, family) + explained = set() + family_models = [] + for chip, chip_id in chips: + recs = [] + out = run_harness(src, enums, recs, chip_id) + runs = parse_runs(out, enums, recs) + model = Model(runs, recs, names, bonded) + model.build() + problems.extend("%s: %s" % (chip, p) for p in model.problems) + explained |= model.explained + family_models.append(model) + socs.append((chip, model, bonded)) + models[chip] = model + # An annotation one die of the family explains is not a source error: + # NA51084 refuses UART2's 3rd location, NA51055 does not. + for model in family_models: + model.explained = explained + family_models[0].problems = [] + family_models[0].check_annotations(found) + problems.extend("%s: %s" % (family, p) + for p in family_models[0].problems) + if problems: + die("the sources disagree:\n " + "\n ".join(problems[:40])) + return render(socs, REGEN), models # ---------------------------------------------------------------- selftest @@ -1087,6 +1308,9 @@ def generate(sdk): "BSP/linux-kernel/arch/arm/plat-novatek/include/plat-na51089/top_reg.h": """ #include +#define TOP_REG2_OFS 0x08 +union TOP_REG2 { uint32_t reg; struct { + unsigned int LCD_TYPE:4; unsigned int r0:28; } bit; }; #define TOP_REG3_OFS 0x0C union TOP_REG3 { uint32_t reg; struct { unsigned int SENSOR:3; unsigned int r0:3; @@ -1103,7 +1327,8 @@ def generate(sdk): unsigned int UART2_CTSRTS:2; unsigned int r2:22; } bit; }; #define TOP_REGCGPIO0_OFS 0xA0 union TOP_REGCGPIO0 { uint32_t reg; struct { - unsigned int CGPIO_0:1; unsigned int r:10; unsigned int CGPIO_11:1; + unsigned int CGPIO_0:1; unsigned int CGPIO_1:1; unsigned int r:9; + unsigned int CGPIO_11:1; unsigned int CGPIO_12:1; unsigned int CGPIO_13:1; unsigned int r2:18; } bit; }; #define TOP_REGPGPIO0_OFS 0xA8 @@ -1133,6 +1358,7 @@ def generate(sdk): PIN_SENSOR_CFG_CCIR8BITS = 0x08, ///< no annotation PIN_SENSOR_CFG_MCLK = 0x10, ///< mclk on C0 PIN_SENSOR_CFG_MCLK_2ND = 0x20, ///< mclk on HSI1 + PIN_SENSOR_CFG_VDHD = 0x40, ///< sync on HSI0, inside the 12-bit mode } PIN_SENSOR_CFG; typedef enum { PIN_SPI_CFG_NONE, @@ -1145,6 +1371,11 @@ def generate(sdk): PIN_ETH_CFG_INTERANL = 2, PIN_ETH_CFG_MDIO = 4, } PINMUX_ETH_CFG; +typedef enum { + PIN_MISC_CFG_NONE, + PIN_MISC_CFG_A = 0x1 << 0, + PIN_MISC_CFG_B = 0x1 << 1, +} PINMUX_MISC_CFG; """, "BSP/linux-kernel/arch/arm/plat-novatek/include/plat-na51089/" "nvt-gpio.h": """ @@ -1171,8 +1402,10 @@ def generate(sdk): static int pinmux_config_sensor(uint32_t config); static int pinmux_config_spi(uint32_t config); static int pinmux_config_eth(uint32_t config); +static int pinmux_config_misc(uint32_t config); static int sticky = 0; +union TOP_REG2 top_reg2; union TOP_REG3 top_reg3; union TOP_REG5 top_reg5; union TOP_REG9 top_reg9; @@ -1229,6 +1462,9 @@ def generate(sdk): top_reg3.bit.SENSOR = 1; top_reg_hgpio0.bit.HSIGPIO_0 = GPIO_ID_EMUM_GPIO; top_reg_hgpio0.bit.HSIGPIO_1 = GPIO_ID_EMUM_GPIO; + if (config & PIN_SENSOR_CFG_VDHD) { + top_reg_hgpio0.bit.HSIGPIO_0 = GPIO_ID_EMUM_FUNC; + } break; case PIN_SENSOR_CFG_CCIR8BITS: top_reg3.bit.SENSOR = 3; @@ -1278,6 +1514,26 @@ def generate(sdk): } return E_OK; } + +static int pinmux_config_misc(uint32_t config) +{ + top_reg2.bit.LCD_TYPE = 0; + switch (config & (PIN_MISC_CFG_A | PIN_MISC_CFG_B)) { + case PIN_MISC_CFG_A: + top_reg2.bit.LCD_TYPE = 1; + break; + case PIN_MISC_CFG_B: + top_reg2.bit.LCD_TYPE = 2; + top_reg_pgpio0.bit.PGPIO_2 = GPIO_ID_EMUM_FUNC; + break; + default: + break; + } + if ((config >= PIN_MISC_CFG_A) && (config <= PIN_MISC_CFG_B)) { + top_reg_cgpio0.bit.CGPIO_1 = GPIO_ID_EMUM_FUNC; + } + return E_OK; +} """, "build/nvt-tools/nvt_pinctrl_tool/top.csv": """\ PIN_SPI_CFG_CH1,1,P_GPIO2[spi_clk(BS)], @@ -1287,13 +1543,13 @@ def generate(sdk): SELFTEST_FUNCS = [("i2c", "PIN_I2C_CFG"), ("uart", "PIN_UART_CFG"), ("sensor", "PIN_SENSOR_CFG"), ("spi", "PIN_SPI_CFG"), - ("eth", "PINMUX_ETH_CFG")] + ("eth", "PINMUX_ETH_CFG"), ("misc", "PINMUX_MISC_CFG")] def selftest(): - global FUNCS + global FUNCS, FAMILIES tmp = tempfile.mkdtemp(prefix="nvt_padmux_selftest_") - saved = FUNCS, dict(ANNOTATION_ERRATA) + saved = FUNCS, dict(ANNOTATION_ERRATA), FAMILIES failures = [] def check(cond, what): @@ -1307,6 +1563,7 @@ def check(cond, what): with open(path, "w") as f: f.write(text) FUNCS = SELFTEST_FUNCS + FAMILIES = [("na51089", [("NA51089", 0x7021)], True)] # The csv's P_GPIO29 is a typo. Without an erratum the sources # disagree and the generator has to say so rather than guess. @@ -1317,9 +1574,10 @@ def check(cond, what): check("PIN_I2C_CFG_CH3 names P_GPIO29" in str(e), "refusal names the pad: %s" % e) - ANNOTATION_ERRATA[("PIN_I2C_CFG_CH3", "P_GPIO29")] = ( + ANNOTATION_ERRATA[("na51089", "PIN_I2C_CFG_CH3", "P_GPIO29")] = ( "PIN_I2C_CFG_CH3", "P_GPIO1") - text, model = generate(tmp) + text, models = generate(tmp) + model = models["NA51089"] claims = model.claims def names(pad): @@ -1345,8 +1603,12 @@ def read_as(pad, writes, gate): check([c.name for c in rts] == ["UART2_2_RTS"], "C13 %s" % [c.name for c in rts]) check(rts and len(rts[0].conds) == 2, "C13 needs UART2 and CTSRTS") - check(names("P_GPIO2") == {"UART2_1_TX", "SPI_CLK"}, "P2 %s" - % names("P_GPIO2")) + # SPI_CLK claims P_GPIO2 with no condition at all; MISC_B's claim + # there is a superset of that and of another group, and keeps its + # own name. MISC_B is also a `0x1 << 1`, which has to be read. + check(names("P_GPIO2") == {"UART2_1_TX", "SPI_CLK", "MISC_B"}, + "P2 %s" % names("P_GPIO2")) + check(enum_value("0x01 << 23") == 1 << 23, "enum shift") check("SENSOR_12BITS" in names("H_GPIO0"), "H0 %s" % names("H_GPIO0")) # MCLK depends on SEN_MCLK alone, not on the sensor mode the same # call selected in another block. @@ -1387,9 +1649,23 @@ def read_as(pad, writes, gate): % read_as("P_GPIO1", both, 0)) check(read_as("P_GPIO1", {MDIO: 0x4}, 0) == "ETH_MDIO", "P1 MDIO") + # Gated before ungated, conditions alike: a handed-over HSI0 under + # the 12-bit mode is the sync, a gated one is still the data. + check(read_as("H_GPIO0", {SENSOR: 1}, 0) == "SENSOR_VDHD", + "H0 gate clear %s" % read_as("H_GPIO0", {SENSOR: 1}, 0)) + check(read_as("H_GPIO0", {SENSOR: 1}, 1) == "SENSOR_12BITS", + "H0 gate set") + # Reset at the top, set in a switch, then the pad: the switch's + # value is the condition, and a range test names no option. + LCD = (0x08, 0x0F) + check(names("C_GPIO1") == {"MISC_A", "MISC_B"}, "C1 %s" + % names("C_GPIO1")) + check(read_as("C_GPIO1", {LCD: 2}, 0) == "MISC_B", "C1 under 2") + check(read_as("C_GPIO1", {LCD: 0}, 0) == "?", "C1 under 0") + check("PMX_C_GPIO13" in text and "NA51089_claims" in text, "render") finally: - FUNCS = saved[0] + FUNCS, FAMILIES = saved[0], saved[2] ANNOTATION_ERRATA.clear() ANNOTATION_ERRATA.update(saved[1]) shutil.rmtree(tmp, ignore_errors=True)