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JingJerYenJingJerYen
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add examples for APB
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‎examples/CMakeLists.txt‎

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if(NOT USE_CWR_SYSTEMC)
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add_subdirectory(ace-axi)
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add_subdirectory(ace-ace)
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add_subdirectory(apb_bfm)
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add_subdirectory(axi-axi)
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add_subdirectory(axi4_tlm-pin-tlm)
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add_subdirectory(axi4lite_tlm-pin-tlm)

‎examples/apb_bfm/CMakeLists.txt‎

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project (apb_bfm)
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add_executable(${PROJECT_NAME} sc_main.cpp)
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target_link_libraries (${PROJECT_NAME} PUBLIC scc)
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target_link_libraries (${PROJECT_NAME} LINK_PUBLIC ${CMAKE_THREAD_LIBS_INIT})
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target_link_libraries (${PROJECT_NAME} LINK_PUBLIC ${CMAKE_DL_LIBS})
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if(APPLE)
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set_target_properties (${PROJECT_NAME} PROPERTIES LINK_FLAGS
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-Wl,-U,_sc_main,-U,___sanitizer_start_switch_fiber,-U,___sanitizer_finish_switch_fiber)
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endif()

‎examples/apb_bfm/sc_main.cpp‎

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#include <cci_configuration>
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#include <fstream>
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#include <interfaces/apb/pin/initiator.h>
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#include <interfaces/apb/pin/target.h>
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#include <iomanip>
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#include <scc/configurable_tracer.h>
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#include <scc/configurer.h>
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#include <scc/report.h>
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#include <scc/traceable.h>
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#include <scc/tracer.h>
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#include <tlm/scc/initiator_mixin.h>
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#include <tlm/scc/target_mixin.h>
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using namespace sc_core;
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using namespace scc;
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class testbench : public sc_module, public scc::traceable {
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public:
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enum { WIDTH = 32 };
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<WIDTH>> isck{"isck"};
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apb::pin::initiator<WIDTH> intor{"intor"};
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sc_core::sc_clock PCLK{"PCLK", 1_ns};
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sc_core::sc_signal<bool> PRESETn{"PRESETn"};
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sc_core::sc_signal<sc_dt::sc_uint<32>> PADDR{"PADDR"};
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sc_core::sc_signal<sc_dt::sc_uint<3>> PPROT{"PPROT"};
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sc_core::sc_signal<bool> PNSE{"PNSE"};
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sc_core::sc_signal<bool> PSELx{"PSELx"};
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sc_core::sc_signal<bool> PENABLE{"PENABLE"};
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sc_core::sc_signal<bool> PWRITE{"PWRITE"};
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sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> PWDATA{"PWDATA"};
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sc_core::sc_signal<sc_dt::sc_uint<WIDTH / 8>> PSTRB{"PSTRB"};
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sc_core::sc_signal<bool> PREADY{"PREADY"};
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sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> PRDATA{"PRDATA"};
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sc_core::sc_signal<bool> PSLVERR{"PSLVERR"};
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apb::pin::target<WIDTH, 32> target{"target"};
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tlm::scc::target_mixin<tlm::tlm_target_socket<scc::LT>> tsck{"tsck"};
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testbench(sc_module_name nm)
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: sc_module(nm) {
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SC_HAS_PROCESS(testbench);
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isck(intor.tsckt);
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intor.PCLK_i(PCLK);
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intor.PRESETn_i(PRESETn);
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intor.PADDR_o(PADDR);
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intor.PPROT_o(PPROT);
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intor.PNSE_o(PNSE);
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intor.PSELx_o(PSELx);
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intor.PENABLE_o(PENABLE);
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intor.PWRITE_o(PWRITE);
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intor.PWDATA_o(PWDATA);
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intor.PSTRB_o(PSTRB);
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intor.PREADY_i(PREADY);
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intor.PRDATA_i(PRDATA);
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intor.PSLVERR_i(PSLVERR);
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target.PCLK_i(PCLK);
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target.PRESETn_i(PRESETn);
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target.PADDR_i(PADDR);
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target.PPROT_i(PPROT);
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target.PNSE_i(PNSE);
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target.PSELx_i(PSELx);
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target.PENABLE_i(PENABLE);
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target.PWRITE_i(PWRITE);
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target.PWDATA_i(PWDATA);
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target.PSTRB_i(PSTRB);
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target.PRDATA_o(PRDATA);
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target.PREADY_o(PREADY);
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target.PSLVERR_o(PSLVERR);
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target.isckt(tsck);
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SC_THREAD(run);
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tsck.register_b_transport([this](tlm::tlm_generic_payload& gp, sc_time& delay) {
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gp.set_response_status(tlm::TLM_OK_RESPONSE);
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if(gp.is_write()) {
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SCCDEBUG(SCMOD) << "Received write access to addr 0x" << std::hex << gp.get_address();
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// Print all data bytes with their byte enable values
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if(gp.get_byte_enable_length() > 0) {
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SCCDEBUG(SCMOD) << " Data with byte enables:";
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for(size_t i = 0; i < gp.get_data_length(); ++i) {
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SCCDEBUG(SCMOD) << " Byte[" << i << "]: data=0x" << std::hex << std::setw(2) << std::setfill('0')
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<< (unsigned)gp.get_data_ptr()[i] << " BE=0x" << std::hex << std::setw(2) << std::setfill('0')
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<< (unsigned)gp.get_byte_enable_ptr()[i]
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<< (gp.get_byte_enable_ptr()[i] ? " (enabled)" : " (disabled)");
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}
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} else {
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SCCDEBUG(SCMOD) << " Data (no byte enables):";
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for(size_t i = 0; i < gp.get_data_length(); ++i) {
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SCCDEBUG(SCMOD) << " Byte[" << i << "]: data=0x" << std::hex << std::setw(2) << std::setfill('0')
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<< (unsigned)gp.get_data_ptr()[i];
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}
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}
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} else {
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memset(gp.get_data_ptr(), 0x55, gp.get_data_length());
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SCCDEBUG(SCMOD) << "Received read access from addr 0x" << std::hex << gp.get_address();
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}
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});
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}
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void run() {
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///////////////////////////////////////////////////////////////////////////
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// Test data preparation
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///////////////////////////////////////////////////////////////////////////
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std::array<uint8_t, 8> write_data;
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std::array<uint8_t, 8> read_data;
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std::array<uint8_t, 4> byte_enable;
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write_data[0] = 0xAA;
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write_data[1] = 0xBB;
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write_data[2] = 0xCC;
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write_data[3] = 0xDD;
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write_data[4] = 0xEE;
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write_data[5] = 0xFF;
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write_data[6] = 0x66;
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write_data[7] = 0x77;
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///////////////////////////////////////////////////////////////////////////
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// Reset sequence
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///////////////////////////////////////////////////////////////////////////
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PRESETn.write(false);
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for(size_t i = 0; i < 10; ++i)
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wait(PCLK.posedge_event());
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PRESETn.write(true);
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wait(PCLK.posedge_event());
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///////////////////////////////////////////////////////////////////////////
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// Test 1: Pin-level target - Aligned write (full word, all strobes)
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///////////////////////////////////////////////////////////////////////////
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PENABLE.write(0);
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for(int i = 0; i < 2; i++) {
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// setup phase
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PSELx.write(1);
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PADDR.write(0x1000);
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PWDATA.write(*reinterpret_cast<uint32_t*>(write_data.data() + i * 4));
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PWRITE.write(1);
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PSTRB.write(0b1111);
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wait(PCLK.posedge_event());
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// access phase
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PENABLE.write(1);
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while(!PREADY.read())
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wait(PREADY.value_changed_event());
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wait(PCLK.posedge_event());
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// cleanup
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PENABLE.write(0);
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PSELx.write(0);
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}
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///////////////////////////////////////////////////////////////////////////
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// Test 2: Pin-level target - Aligned read (full word)
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///////////////////////////////////////////////////////////////////////////
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for(int i = 0; i < 2; i++) {
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// setup phase
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PSELx.write(1);
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PADDR.write(0x1004);
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PWRITE.write(0);
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PSTRB.write(0);
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wait(PCLK.posedge_event());
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// access phase
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PENABLE.write(1);
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while(!PREADY.read())
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wait(PREADY.value_changed_event());
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wait(PCLK.posedge_event());
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// cleanup
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PENABLE.write(0);
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PSELx.write(0);
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SCCDEBUG(SCMOD) << std::hex << "read data : " << PRDATA.read();
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}
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///////////////////////////////////////////////////////////////////////////
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// Test 3: Pin-level target - Write with alternating byte strobes (0b1010)
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///////////////////////////////////////////////////////////////////////////
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// setup phase
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PSELx.write(1);
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PADDR.write(0x1008);
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PWDATA.write(*reinterpret_cast<uint32_t*>(write_data.data()));
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PWRITE.write(1);
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PSTRB.write(0b1010);
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wait(PCLK.posedge_event());
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// access phase
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PENABLE.write(1);
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while(!PREADY.read())
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wait(PREADY.value_changed_event());
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wait(PCLK.posedge_event());
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// cleanup
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PENABLE.write(0);
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PSELx.write(0);
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wait(PCLK.posedge_event());
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///////////////////////////////////////////////////////////////////////////
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// Test 4: TLM initiator via pin - Write with byte enables (BE: 0xFF, 0x00, 0x00, 0xFF)
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///////////////////////////////////////////////////////////////////////////
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tlm::tlm_generic_payload gp;
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sc_time delay;
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byte_enable[0] = 0xFF;
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byte_enable[1] = 0x00;
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byte_enable[2] = 0x00;
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byte_enable[3] = 0xFF;
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gp.set_address(0x1010);
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gp.set_data_length(4);
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gp.set_data_ptr(write_data.data() + 2);
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gp.set_byte_enable_ptr(byte_enable.data());
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gp.set_byte_enable_length(4);
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gp.set_streaming_width(4);
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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delay = SC_ZERO_TIME;
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isck->b_transport(gp, delay);
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///////////////////////////////////////////////////////////////////////////
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// Test 5: TLM initiator via pin - Aligned read (full word)
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///////////////////////////////////////////////////////////////////////////
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gp.set_address(0x1014);
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gp.set_data_length(4);
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gp.set_data_ptr(read_data.data());
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gp.set_streaming_width(4);
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gp.set_command(tlm::TLM_READ_COMMAND);
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delay = SC_ZERO_TIME;
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isck->b_transport(gp, delay);
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SCCDEBUG(SCMOD) << std::hex << "read data : " << *(uint32_t*)read_data.data();
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///////////////////////////////////////////////////////////////////////////
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// Test 6: TLM initiator via pin - Unaligned partial write
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// Note: Unaligned write (0x1016-0x1018) is converted to strobe write (0x1014-0x1018)
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///////////////////////////////////////////////////////////////////////////
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gp.set_address(0x1016);
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gp.set_data_length(2);
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gp.set_data_ptr(write_data.data() + 2);
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gp.set_byte_enable_ptr(nullptr);
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gp.set_byte_enable_length(0);
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gp.set_streaming_width(2);
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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delay = SC_ZERO_TIME;
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isck->b_transport(gp, delay);
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///////////////////////////////////////////////////////////////////////////
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// Test 7: Invalid case - Transaction exceeding 32-bit boundary (disabled)
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// Note: This test is disabled as it tests an invalid scenario
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///////////////////////////////////////////////////////////////////////////
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if(0) {
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gp.set_address(0x1018);
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gp.set_data_length(8);
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gp.set_data_ptr(read_data.data());
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gp.set_streaming_width(8);
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gp.set_command(tlm::TLM_READ_COMMAND);
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delay = SC_ZERO_TIME;
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isck->b_transport(gp, delay);
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}
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sc_stop();
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return;
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}
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};
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int sc_main(int argc, char* argv[]) {
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sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING);
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sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
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///////////////////////////////////////////////////////////////////////////
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// configure logging
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///////////////////////////////////////////////////////////////////////////
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scc::init_logging(LogConfig().logLevel(scc::log::DEBUG).logAsync(false));
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///////////////////////////////////////////////////////////////////////////
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// set up configuration and tracing
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///////////////////////////////////////////////////////////////////////////
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scc::configurer cfg("apb_bfm.json");
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scc::configurable_tracer trace("apb_bfm", true, true);
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///////////////////////////////////////////////////////////////////////////
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// create modules/channels and trace
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///////////////////////////////////////////////////////////////////////////
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testbench tb("tb");
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///////////////////////////////////////////////////////////////////////////
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// Create VCD trace file
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///////////////////////////////////////////////////////////////////////////
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sc_trace_file *vcd_trace = sc_create_vcd_trace_file("apb_trace");
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vcd_trace->set_time_unit(1, SC_PS); // Set time unit to picoseconds
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// Trace clock and reset
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sc_trace(vcd_trace, tb.PCLK, "PCLK");
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sc_trace(vcd_trace, tb.PRESETn, "PRESETn");
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// Trace APB address phase signals
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sc_trace(vcd_trace, tb.PADDR, "PADDR");
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sc_trace(vcd_trace, tb.PSELx, "PSELx");
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sc_trace(vcd_trace, tb.PENABLE, "PENABLE");
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sc_trace(vcd_trace, tb.PWRITE, "PWRITE");
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sc_trace(vcd_trace, tb.PPROT, "PPROT");
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sc_trace(vcd_trace, tb.PNSE, "PNSE");
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// Trace APB data signals
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sc_trace(vcd_trace, tb.PWDATA, "PWDATA");
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sc_trace(vcd_trace, tb.PSTRB, "PSTRB");
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sc_trace(vcd_trace, tb.PRDATA, "PRDATA");
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// Trace APB response signals
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sc_trace(vcd_trace, tb.PREADY, "PREADY");
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sc_trace(vcd_trace, tb.PSLVERR, "PSLVERR");
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cfg.configure();
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cfg.dump_configuration("apb_test.default.json");
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///////////////////////////////////////////////////////////////////////////
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// run the simulation
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///////////////////////////////////////////////////////////////////////////
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try {
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sc_core::sc_start();
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if(!sc_core::sc_end_of_simulation_invoked())
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sc_core::sc_stop();
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} catch(sc_report& e) {
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SCCERR() << "Caught sc_report exception during simulation: " << e.what() << ":" << e.get_msg();
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} catch(std::exception& e) {
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SCCERR() << "Caught exception during simulation: " << e.what();
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} catch(...) {
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SCCERR() << "Caught unspecified exception during simulation";
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}
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///////////////////////////////////////////////////////////////////////////
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// Close VCD trace file
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///////////////////////////////////////////////////////////////////////////
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sc_close_vcd_trace_file(vcd_trace);
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return 0;
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}

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