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Commit 025ceaa

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EAlexJEAlexJ
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adds newly generated files, addressing the concerns of #59 
1 parent 145547c commit 025ceaa

7 files changed

Lines changed: 96 additions & 76 deletions

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‎gen_input/ISA‎

‎src/vm/interp/vm_rv32gc.cpp‎

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
156156
}
157157
else {
158158
uint64_t box = ~((uint64_t)0);
159-
return (uint64_t)(((uint128_t)box<<32)|val);
159+
return (uint64_t)(((uint128_t)(box)<<32)|val);
160160
}
161161
}
162162

@@ -175,7 +175,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
175175
}
176176
else {
177177
uint64_t box = ~((uint64_t)0);
178-
return (uint64_t)(((uint128_t)box<<64)|val);
178+
return (uint64_t)(((uint128_t)(box)<<64)|val);
179179
}
180180
}
181181

@@ -2809,7 +2809,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
28092809
*NEXT_PC = *PC + 2;
28102810
// execute instruction
28112811
{
2812-
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
2812+
if(shamt) {
2813+
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
2814+
}
28132815
}
28142816
break;
28152817
}// @suppress("No break at end of case")
@@ -3006,13 +3008,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
30063008
break;
30073009
}// @suppress("No break at end of case")
30083010
case arch::traits<ARCH>::opcode_e::C__SLLI: {
3009-
uint8_t nzuimm = ((bit_sub<2,5>(instr)));
3011+
uint8_t shamt = ((bit_sub<2,5>(instr)));
30103012
uint8_t rs1 = ((bit_sub<7,5>(instr)));
30113013
if(this->disass_enabled){
30123014
/* generate console output when executing the command */
30133015
auto mnemonic = fmt::format(
3014-
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
3015-
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
3016+
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"),
3017+
fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
30163018
this->core.disass_output(pc.val, mnemonic);
30173019
}
30183020
// used registers
@@ -3026,7 +3028,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
30263028
}
30273029
else {
30283030
if(rs1 != 0) {
3029-
*(X+rs1) = *(X+rs1) << nzuimm;
3031+
*(X+rs1) = *(X+rs1) << shamt;
30303032
}
30313033
}
30323034
}
@@ -3721,7 +3723,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
37213723
*NEXT_PC = *PC + 4;
37223724
// execute instruction
37233725
{
3724-
*(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
3726+
*(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
37253727
}
37263728
break;
37273729
}// @suppress("No break at end of case")
@@ -3742,7 +3744,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
37423744
*NEXT_PC = *PC + 4;
37433745
// execute instruction
37443746
{
3745-
*(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
3747+
*(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
37463748
}
37473749
break;
37483750
}// @suppress("No break at end of case")
@@ -4324,8 +4326,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
43244326
*NEXT_PC = *PC + 4;
43254327
// execute instruction
43264328
{
4327-
uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
4328-
*(F+rd) = res;
4329+
*(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
43294330
uint32_t flags = fget_flags();
43304331
*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
43314332
}
@@ -4545,12 +4546,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
45454546
this->core.disass_output(pc.val, mnemonic);
45464547
}
45474548
// used registers
4548-
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
4549+
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
4550+
auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
45494551
// calculate next pc value
45504552
*NEXT_PC = *PC + 4;
45514553
// execute instruction
45524554
{
45534555
*(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
4556+
uint32_t flags = fget_flags();
4557+
*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
45544558
}
45554559
break;
45564560
}// @suppress("No break at end of case")
@@ -4571,7 +4575,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
45714575
*NEXT_PC = *PC + 4;
45724576
// execute instruction
45734577
{
4574-
*(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
4578+
*(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
45754579
}
45764580
break;
45774581
}// @suppress("No break at end of case")
@@ -4592,7 +4596,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
45924596
*NEXT_PC = *PC + 4;
45934597
// execute instruction
45944598
{
4595-
*(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
4599+
*(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
45964600
}
45974601
break;
45984602
}// @suppress("No break at end of case")
@@ -4858,7 +4862,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
48584862
*NEXT_PC = *PC + 4;
48594863
// execute instruction
48604864
{
4861-
super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
4865+
super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
48624866
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
48634867
}
48644868
break;

‎src/vm/interp/vm_rv32gcv.cpp‎

Lines changed: 23 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
268268
}
269269
else {
270270
uint64_t box = ~((uint64_t)0);
271-
return (uint64_t)(((uint128_t)box<<32)|val);
271+
return (uint64_t)(((uint128_t)(box)<<32)|val);
272272
}
273273
}
274274

@@ -287,7 +287,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
287287
}
288288
else {
289289
uint64_t box = ~((uint64_t)0);
290-
return (uint64_t)(((uint128_t)box<<64)|val);
290+
return (uint64_t)(((uint128_t)(box)<<64)|val);
291291
}
292292
}
293293

@@ -3780,7 +3780,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
37803780
*NEXT_PC = *PC + 2;
37813781
// execute instruction
37823782
{
3783-
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
3783+
if(shamt) {
3784+
*(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
3785+
}
37843786
}
37853787
break;
37863788
}// @suppress("No break at end of case")
@@ -3977,13 +3979,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
39773979
break;
39783980
}// @suppress("No break at end of case")
39793981
case arch::traits<ARCH>::opcode_e::C__SLLI: {
3980-
uint8_t nzuimm = ((bit_sub<2,5>(instr)));
3982+
uint8_t shamt = ((bit_sub<2,5>(instr)));
39813983
uint8_t rs1 = ((bit_sub<7,5>(instr)));
39823984
if(this->disass_enabled){
39833985
/* generate console output when executing the command */
39843986
auto mnemonic = fmt::format(
3985-
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
3986-
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
3987+
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"),
3988+
fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
39873989
this->core.disass_output(pc.val, mnemonic);
39883990
}
39893991
// used registers
@@ -3997,7 +3999,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
39973999
}
39984000
else {
39994001
if(rs1 != 0) {
4000-
*(X+rs1) = *(X+rs1) << nzuimm;
4002+
*(X+rs1) = *(X+rs1) << shamt;
40014003
}
40024004
}
40034005
}
@@ -4692,7 +4694,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
46924694
*NEXT_PC = *PC + 4;
46934695
// execute instruction
46944696
{
4695-
*(F+rd) = NaNBox32(((uint32_t)bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2)))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
4697+
*(F+rd) = NaNBox32(((uint32_t)(bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
46964698
}
46974699
break;
46984700
}// @suppress("No break at end of case")
@@ -4713,7 +4715,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
47134715
*NEXT_PC = *PC + 4;
47144716
// execute instruction
47154717
{
4716-
*(F+rd) = NaNBox32(((uint32_t)(~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
4718+
*(F+rd) = NaNBox32(((uint32_t)((~bit_sub<31, 31-31+1>(unbox_s(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<31)|bit_sub<0, 30-0+1>(unbox_s(traits::FLEN, *(F+rs1))));
47174719
}
47184720
break;
47194721
}// @suppress("No break at end of case")
@@ -5295,8 +5297,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
52955297
*NEXT_PC = *PC + 4;
52965298
// execute instruction
52975299
{
5298-
uint64_t res = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
5299-
*(F+rd) = res;
5300+
*(F+rd) = NaNBox64(fmadd_d(unbox_d(traits::FLEN, *(F+rs1)), unbox_d(traits::FLEN, *(F+rs2)), unbox_d(traits::FLEN, *(F+rs3)), 1, get_rm(rm)));
53005301
uint32_t flags = fget_flags();
53015302
*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
53025303
}
@@ -5516,12 +5517,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
55165517
this->core.disass_output(pc.val, mnemonic);
55175518
}
55185519
// used registers
5519-
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
5520+
auto* F = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::F0]);
5521+
auto* FCSR = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::FCSR]);
55205522
// calculate next pc value
55215523
*NEXT_PC = *PC + 4;
55225524
// execute instruction
55235525
{
55245526
*(F+rd) = NaNBox64(f32tof64(unbox_s(traits::FLEN, *(F+rs1)), get_rm(rm)));
5527+
uint32_t flags = fget_flags();
5528+
*FCSR = (*FCSR & ~traits::FFLAG_MASK) | (flags & traits::FFLAG_MASK);
55255529
}
55265530
break;
55275531
}// @suppress("No break at end of case")
@@ -5542,7 +5546,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
55425546
*NEXT_PC = *PC + 4;
55435547
// execute instruction
55445548
{
5545-
*(F+rd) = NaNBox64(((uint64_t)bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2)))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
5549+
*(F+rd) = NaNBox64(((uint64_t)(bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
55465550
}
55475551
break;
55485552
}// @suppress("No break at end of case")
@@ -5563,7 +5567,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
55635567
*NEXT_PC = *PC + 4;
55645568
// execute instruction
55655569
{
5566-
*(F+rd) = NaNBox64(((uint64_t)(~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1)<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
5570+
*(F+rd) = NaNBox64(((uint64_t)((~bit_sub<63, 63-63+1>(unbox_d(traits::FLEN, *(F+rs2))))& ((1ULL << 1)-1))<<63)|bit_sub<0, 62-0+1>(unbox_d(traits::FLEN, *(F+rs1))));
55675571
}
55685572
break;
55695573
}// @suppress("No break at end of case")
@@ -5829,7 +5833,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
58295833
*NEXT_PC = *PC + 4;
58305834
// execute instruction
58315835
{
5832-
super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)(uint8_t)rs1<<8)|(uint8_t)asid);
5836+
super::template write_mem<uint32_t>(traits::FENCE, traits::fencevma, ((uint16_t)((uint8_t)rs1)<<8)|(uint8_t)asid);
58335837
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
58345838
}
58355839
break;
@@ -5880,7 +5884,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
58805884
uint8_t orig_ratio = (uint8_t)(get_sew_pow() - get_lmul_pow());
58815885
uint32_t orig_vstart = *vstart;
58825886
*vstart = 0;
5883-
*vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
5887+
*vtype = (uint32_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
58845888
if(! valid_sew_lmul()) {
58855889
handle_illegal_vtype();
58865890
*vstart = orig_vstart;
@@ -5939,7 +5943,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
59395943
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
59405944
}
59415945
else {
5942-
*vtype = (uint32_t)((ma<<7)|(ta<<6)|(sew<<3)|lmul);
5946+
*vtype = (uint32_t)(((ma)<<7)|((ta)<<6)|((sew)<<3)|lmul);
59435947
if(! valid_sew_lmul()) {
59445948
handle_illegal_vtype();
59455949
}
@@ -12574,7 +12578,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
1257412578
if(illegal_vd_unmasked()) {
1257512579
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
1257612580
}
12577-
uint32_t _vtype = (bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
12581+
uint32_t _vtype = ((bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint32_t)(1)<<6)|((uint32_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
1257812582
*vstart = (uint32_t)vsseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vs3, *(X+rs1), 0, 1);
1257912583
}
1258012584
}
@@ -12608,7 +12612,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
1260812612
if(illegal_vd_unmasked()) {
1260912613
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
1261012614
}
12611-
uint32_t _vtype = (bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1)<<7)|((uint32_t)1<<6)|((uint32_t)0<<3)|bit_sub<0, 2-0+1>(*vtype);
12615+
uint32_t _vtype = ((bit_sub<uint32_t>(*vtype, 7, (uint64_t)(traits::XLEN) - (uint64_t)(1)-7+1))<<7)|((uint32_t)(1)<<6)|((uint32_t)(0)<<3)|bit_sub<0, 2-0+1>(*vtype);
1261212616
*vstart = (uint32_t)vlseg(this->get_arch(), (uint8_t*)V, evl, *vstart, _vtype, 1, vd, *(X+rs1), 0, 1);
1261312617
}
1261412618
}

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