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@mstorsjo
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The condition CR=0 isn't correct here; the same about the first store for float registers doing the predecrement for any variant where there are no integer registers stored before the floats - this goes for both CR=0, CR=2 and CR=3.

The condition CR=0 isn't correct here; the same about the first
store for float registers doing the predecrement for any variant
where there are no integer registers stored before the floats -
this goes for both CR=0, CR=2 and CR=3.
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@mstorsjo : Thanks for your contribution! The author(s) and reviewer(s) have been notified to review your proposed change.

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CC @pmsjt

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Learn Build status updates of commit 2008082:

✅ Validation status: passed

File Status Preview URL Details
docs/build/arm64-exception-handling.md ✅Succeeded

For more details, please refer to the build report.

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@TylerMSFT

Can you review the proposed changes?

IMPORTANT: When the changes are ready for publication, adding a #sign-off comment is the best way to signal that the PR is ready for the review team to merge.

#label:"aq-pr-triaged"
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@prmerger-automator prmerger-automator bot added the aq-pr-triaged Tracking label for the PR review team label Nov 28, 2025
@pmsjt
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pmsjt commented Nov 28, 2025

The replacement is accurate.

When

    fnent_pdata.RegF != 0;
    fnent_pdata.RegI == 0;

the only case where we get save_fregp instead of a save_fregp_x is when

    fnent_pdata.CR == PdataCrUnchainedSavedLr // 1

Thank you for the fix @mstorsjo .

But we might have to finesse this statement a little better. "the decrement" means which decrement? See, in both the PdataCrChainedWithPac (2) and the PdataCrChained (3) we end up with 2 pre-decrements.

For example:

    fnent_pdata.Flag = PdataPackedUnwindFunction;
    fnent_pdata.RegF = 1;
    fnent_pdata.RegI = 0;
    fnent_pdata.H = 0;
    fnent_pdata.CR = PdataCrChainedWithPac;
    fnent_pdata.FrameSize = 64 / 16;

Results in

end
pac
save_fregp_x    (d8, d9, -16)
save_fplr_x     (-48)
set_fp

So, we should clarify that this pre-decrement is just to cover for the FP/SIMD registers. This is true even for the PdataCrUnchained (0) case:

    fnent_pdata.Flag = PdataPackedUnwindFunction;
    fnent_pdata.FunctionLength = 0xB0 / 4;
    fnent_pdata.RegF = 1;
    fnent_pdata.RegI = 0;
    fnent_pdata.H = 0;
    fnent_pdata.CR = PdataCrUnchained;
    fnent_pdata.FrameSize = 64 / 16;

results in

end
save_fregp_x    (d8, d9, -16)
alloc           (48)

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4 participants