From 782fc81cabcf89454f9cb7608fba0008191bfbe4 Mon Sep 17 00:00:00 2001 From: ag Date: Wed, 11 Mar 2026 00:58:14 -0400 Subject: [PATCH 1/2] test 1 --- .../sources_1/new/top.v | 3 +- src/main/scala/RISCV/Main.scala | 3 +- src/main/scala/RISCV/VGAController.scala | 67 +++++++++++-------- 3 files changed, 42 insertions(+), 31 deletions(-) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v index 4ba7bff..1a1cf91 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v @@ -66,7 +66,8 @@ module Top( .io_vsync (vgaVSync), .io_rgb (rgb), .io_blanking (blanking), - .io_btns(btns) + .io_vga_clk (clk_25) +// .io_btns(btns) ); diff --git a/src/main/scala/RISCV/Main.scala b/src/main/scala/RISCV/Main.scala index 39c7c78..7299498 100644 --- a/src/main/scala/RISCV/Main.scala +++ b/src/main/scala/RISCV/Main.scala @@ -10,6 +10,7 @@ class Main() extends Module { val io = IO(new Bundle { val execute = Input(Bool()); + val vga_clk = Input(Clock()); val debug_write = Input(Bool()); val debug_write_address = Input(UInt(32.W)); val debug_write_data = Input(UInt(32.W)); @@ -48,7 +49,7 @@ class Main() extends Module { vga_controller.io.address := memory.io.address_vga vga_controller.io.write := memory.io.write_vga vga_controller.io.write_value := memory.io.write_value_vga - + vga_controller.io.read_clk := io.vga_clk io.hsync := vga_controller.io.hsync io.vsync := vga_controller.io.vsync io.rgb := vga_controller.io.rgb diff --git a/src/main/scala/RISCV/VGAController.scala b/src/main/scala/RISCV/VGAController.scala index f01a553..c7a4e24 100644 --- a/src/main/scala/RISCV/VGAController.scala +++ b/src/main/scala/RISCV/VGAController.scala @@ -21,58 +21,67 @@ class VGAController extends Module { val address = Input(UInt(32.W)) val write = Input(Bool()) val write_value = Input(UInt(8.W)) + val read_clk = Input(Clock()) val hsync = Output(Bool()) val vsync = Output(Bool()) val rgb = Output(UInt(12.W)) val blanking = Output(Bool()) + }) val memory = SyncReadMem(320 * 240, UInt(8.W)) - val hCount = RegInit(0.U(10.W)) - val vCount = RegInit(0.U(10.W)) + when(io.write) { memory.write(io.address, io.write_value) } - when(hCount === (H_TOTAL - 1).U) { - hCount := 0.U + withClock(io.read_clk) { + val hCount = RegInit(0.U(10.W)) + val vCount = RegInit(0.U(10.W)) + - when(vCount === (V_TOTAL - 1).U) { - vCount := 0.U + when(hCount === (H_TOTAL - 1).U) { + hCount := 0.U + + when(vCount === (V_TOTAL - 1).U) { + vCount := 0.U + }.otherwise { + vCount := vCount + 1.U + } }.otherwise { - vCount := vCount + 1.U + hCount := hCount + 1.U } - }.otherwise { - hCount := hCount + 1.U - } - val hSyncStart = (H_VISIBLE + H_FRONT).U - val hSyncEnd = (H_VISIBLE + H_FRONT + H_SYNC).U - val vSyncStart = (V_VISIBLE + V_FRONT).U - val vSyncEnd = (V_VISIBLE + V_FRONT + V_SYNC).U + val hSyncStart = (H_VISIBLE + H_FRONT).U + val hSyncEnd = (H_VISIBLE + H_FRONT + H_SYNC).U + val vSyncStart = (V_VISIBLE + V_FRONT).U + val vSyncEnd = (V_VISIBLE + V_FRONT + V_SYNC).U - io.hsync := !(hCount >= hSyncStart && hCount < hSyncEnd) - io.vsync := !(vCount >= vSyncStart && vCount < vSyncEnd) + io.hsync := !(hCount >= hSyncStart && hCount < hSyncEnd) + io.vsync := !(vCount >= vSyncStart && vCount < vSyncEnd) - val hActive = hCount < H_VISIBLE.U - val vActive = vCount < V_VISIBLE.U - val active = hActive && vActive + val hActive = hCount < H_VISIBLE.U + val vActive = vCount < V_VISIBLE.U + val active = hActive && vActive - io.blanking := !active + io.blanking := !active - val read_address = WireInit(0.U(32.W)) + val read_address = WireInit(0.U(32.W)) - when(active) { - read_address := vCount / 2.U * 320.U + hCount / 2.U + 1.U - }.otherwise { - read_address := (vCount + 1.U) / 2.U * 320.U - } + when(active) { + read_address := vCount / 2.U * 320.U + hCount / 2.U + 1.U + }.otherwise { + read_address := (vCount + 1.U) / 2.U * 320.U + } - val color = memory.read(read_address, true.B) - val pixel = color(7, 5) ## color(5) ## color(4, 2) ## color(2) ## color(1, 0) ## color(0) ## color(0) + val color = memory.read(read_address, true.B) + val pixel = color(7, 5) ## color(5) ## color(4, 2) ## color(2) ## color(1, 0) ## color(0) ## color(0) - io.rgb := Mux(active, pixel, 0.U) + io.rgb := Mux(active, pixel, 0.U) + + } + } From e46f5f4bdcc6b6d8ca5d796214198744c9a2b115 Mon Sep 17 00:00:00 2001 From: ag Date: Wed, 11 Mar 2026 01:40:09 -0400 Subject: [PATCH 2/2] vga decoupling works --- .../sources_1/ip/clk_wiz_0/clk_wiz_0.v | 92 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.veo | 81 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.xdc | 57 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.xml | 5122 +++++++++++++++++ .../ip/clk_wiz_0/clk_wiz_0_board.xdc | 2 + .../ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 211 + .../sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc | 55 + .../ip/clk_wiz_0/clk_wiz_0_sim_netlist.v | 269 + .../ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 198 + .../sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v | 27 + .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 35 + .../clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt | 355 ++ .../ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh | 680 +++ .../ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh | 542 ++ .../ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh | 680 +++ .../ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh | 555 ++ .../mmcm_pll_drp_func_us_plus_mmcm.vh | 886 +++ .../mmcm_pll_drp_func_us_plus_pll.vh | 561 ++ .../ip/clk_wiz_0/clk_wiz_0.veo | 81 + .../ip/clk_wiz_0/clk_wiz_0_stub.v | 27 + .../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 35 + .../ipstatic/mmcm_pll_drp_func_7s_mmcm.vh | 680 +++ .../ipstatic/mmcm_pll_drp_func_7s_pll.vh | 542 ++ .../ipstatic/mmcm_pll_drp_func_us_mmcm.vh | 680 +++ .../ipstatic/mmcm_pll_drp_func_us_pll.vh | 555 ++ .../mmcm_pll_drp_func_us_plus_mmcm.vh | 886 +++ .../ipstatic/mmcm_pll_drp_func_us_plus_pll.vh | 561 ++ .../sim_scripts/clk_wiz_0/modelsim/README.txt | 50 + .../clk_wiz_0/modelsim/clk_wiz_0.sh | 335 ++ .../clk_wiz_0/modelsim/clk_wiz_0.udo | 0 .../sim_scripts/clk_wiz_0/modelsim/compile.do | 22 + .../clk_wiz_0/modelsim/file_info.txt | 5 + .../sim_scripts/clk_wiz_0/modelsim/glbl.v | 84 + .../clk_wiz_0/modelsim/simulate.do | 19 + .../sim_scripts/clk_wiz_0/modelsim/wave.do | 2 + .../sim_scripts/clk_wiz_0/questa/README.txt | 50 + .../sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh | 347 ++ .../clk_wiz_0/questa/clk_wiz_0.udo | 0 .../sim_scripts/clk_wiz_0/questa/compile.do | 22 + .../sim_scripts/clk_wiz_0/questa/elaborate.do | 1 + .../clk_wiz_0/questa/file_info.txt | 5 + .../sim_scripts/clk_wiz_0/questa/glbl.v | 84 + .../sim_scripts/clk_wiz_0/questa/simulate.do | 19 + .../sim_scripts/clk_wiz_0/questa/wave.do | 2 + .../sim_scripts/clk_wiz_0/riviera/README.txt | 50 + .../clk_wiz_0/riviera/clk_wiz_0.sh | 314 + .../clk_wiz_0/riviera/clk_wiz_0.udo | 0 .../sim_scripts/clk_wiz_0/riviera/compile.do | 25 + .../clk_wiz_0/riviera/file_info.txt | 5 + .../sim_scripts/clk_wiz_0/riviera/glbl.v | 84 + .../sim_scripts/clk_wiz_0/riviera/simulate.do | 14 + .../sim_scripts/clk_wiz_0/vcs/README.txt | 50 + .../sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh | 394 ++ .../sim_scripts/clk_wiz_0/vcs/file_info.txt | 5 + .../sim_scripts/clk_wiz_0/vcs/glbl.v | 84 + .../sim_scripts/clk_wiz_0/vcs/simulate.do | 2 + .../sim_scripts/clk_wiz_0/xcelium/README.txt | 50 + .../clk_wiz_0/xcelium/clk_wiz_0.sh | 398 ++ .../clk_wiz_0/xcelium/file_info.txt | 5 + .../sim_scripts/clk_wiz_0/xcelium/glbl.v | 84 + .../sim_scripts/clk_wiz_0/xcelium/hdl.var | 0 .../sim_scripts/clk_wiz_0/xcelium/simulate.do | 7 + .../sim_scripts/clk_wiz_0/xsim/README.txt | 50 + .../sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh | 387 ++ .../sim_scripts/clk_wiz_0/xsim/cmd.tcl | 12 + .../sim_scripts/clk_wiz_0/xsim/file_info.txt | 3 + .../sim_scripts/clk_wiz_0/xsim/glbl.v | 84 + .../sources_1/ip/clk_wiz_0/clk_wiz_0.xci | 690 +++ .../sources_1/new/top.v | 6 +- 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All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module clk_wiz_0 + ( + // Clock out ports + output clk_out1, + output clk_out2, + // Status and control signals + input reset, + output locked, + // Clock in ports + input clk_in1 + ); + + clk_wiz_0_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + .clk_out2(clk_out2), + // Status and control signals + .reset(reset), + .locked(locked), + // Clock in ports + .clk_in1(clk_in1) + ); + +endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..c57b207 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,81 @@ + +// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + .clk_out2(clk_out2), // output clk_out2 + // Status and control signals + .reset(reset), // input reset + .locked(locked), // output locked + // Clock in ports + .clk_in1(clk_in1) // input clk_in1 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc new file mode 100644 index 0000000..c65617e --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc @@ -0,0 +1,57 @@ + +# file: clk_wiz_0.xdc +# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system. If required +# commented constraints can be used in the top level xdc +#---------------------------------------------------------------- +# Connect to input port when clock capable pin is selected for input +create_clock -period 10.000 [get_ports clk_in1] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100 + + +set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100644 index 0000000..c9aef3b --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,5122 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_aclk + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi_lite + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + EDGE_RISING + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock input + + + + + + + CLK_N + + + clk_in1_n + + + + + CLK_P + + + clk_in1_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLK_IN2_D + CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + true + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + clock_CLK_IN1 + + + + + + + CLK_IN1 + + + clk_in1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + clk_out1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + clock_CLK_OUT2 + + + + + + + CLK_OUT2 + + + clk_out2 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_17 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:a7935ab4 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + clk_wiz_0 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:a7935ab4 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_17 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + clk_wiz_0 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + xilinx_blockmodel + Block Model files + :vivado.xilinx.com:block_model + + + outputProductCRC + 9:8117688b + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 9:74b33944 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:49 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:8117688b + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + clk_wiz_v6_0_17 + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:29 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Wed Mar 11 05:32:31 UTC 2026 + + + outputProductCRC + 9:8117688b + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_araddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in2_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in2_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clkfb_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clkfb_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_stop + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_glitch + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + interrupt + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_oor + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + user_clk3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_in1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_out1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_out2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + locked + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_CLKOUT2_USED + 1 + + + C_USER_CLK_FREQ0 + 100.0 + + + C_AUTO_PRIMITIVE + MMCM + + + C_USER_CLK_FREQ1 + 100.0 + + + C_USER_CLK_FREQ2 + 100.0 + + + C_USER_CLK_FREQ3 + 100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_wiz_0 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 1 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_OPTIMIZE_CLOCKING_STRUCTURE_EN + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Single_ended_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 1 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 2 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__200.00000______0.000______50.0______114.829_____98.575 + + + C_OUTCLK_SUM_ROW2 + clk_out2__25.00000______0.000______50.0______175.402_____98.575 + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 25.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 200.00000 + + + C_CLKOUT2_OUT_FREQ + 25.00000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.0 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 10.000 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + C_MMCM_CLKOUT1_DIVIDE + 40 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 8.0 + + + C_DIVIDE3_AUTO + 0.2 + + + C_DIVIDE4_AUTO + 0.2 + + + C_DIVIDE5_AUTO + 0.2 + + + C_DIVIDE6_AUTO + 0.2 + + + C_DIVIDE7_AUTO + 0.2 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 200.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 25.00000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 80.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1200.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_17 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_anylanguagesynthesis_view_fileset + + clk_wiz_0.xdc + xdc + + processing_order + early + + + + clk_wiz_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_17 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_17 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_externalfiles_view_fileset + + clk_wiz_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + clk_wiz_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + clk_wiz_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_implementation_view_fileset + + clk_wiz_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_veriloginstantiationtemplate_view_fileset + + clk_wiz_0.veo + verilogTemplate + + + + xilinx_versioninformation_view_fileset + + doc/clk_wiz_v6_0_changelog.txt + text + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + OPTIMIZE_CLOCKING_STRUCTURE_EN + Optimize Clocking Structure + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + true + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 2 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 25.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Single_ended_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 10.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 40 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 114.829 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 98.575 + + + CLKOUT2_JITTER + Clkout2 Jitter + 175.402 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 98.575 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 17 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2025.2 + + + + + + + + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v new file mode 100644 index 0000000..9531d13 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -0,0 +1,211 @@ + +// file: clk_wiz_0.v +// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module clk_wiz_0_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + output clk_out2, + // Status and control signals + input reset, + output locked, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_clk_wiz_0; +wire clk_in1_clk_wiz_0_buf; +wire clk_in2_clk_wiz_0; + IBUF clkin1_ibufg + (.O (clk_in1_clk_wiz_0), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_clk_wiz_0; + wire clk_out2_clk_wiz_0; + wire clk_out3_clk_wiz_0; + wire clk_out4_clk_wiz_0; + wire clk_out5_clk_wiz_0; + wire clk_out6_clk_wiz_0; + wire clk_out7_clk_wiz_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + wire reset_high; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (10.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (5.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (40), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_clk_wiz_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_clk_wiz_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clk_out2_clk_wiz_0), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_clk_wiz_0), + .CLKIN1 (clk_in1_clk_wiz_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (reset_high)); + assign reset_high = reset; + + assign locked = locked_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_clk_wiz_0), + .I (clkfbout_clk_wiz_0)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_clk_wiz_0)); + + + BUFG clkout2_buf + (.O (clk_out2), + .I (clk_out2_clk_wiz_0)); + + + +endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc new file mode 100644 index 0000000..6470178 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc @@ -0,0 +1,55 @@ + +# file: clk_wiz_0_ooc.xdc +# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of AMD and is protected under U.S. and international copyright +# and other intellectual property laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# AMD, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) AMD shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or AMD had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# AMD products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of AMD products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +################# +#DEFAULT CLOCK CONSTRAINTS + +############################################################ +# Clock Period Constraints # +############################################################ +#create_clock -period 10.000 [get_ports clk_in1] + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..ddf41ec --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -0,0 +1,269 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Wed Mar 11 01:32:49 2026 +// Host : arya running 64-bit EndeavourOS Linux +// Command : write_verilog -force -mode funcsim +// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_wiz_0 + (clk_out1, + clk_out2, + reset, + locked, + clk_in1); + output clk_out1; + output clk_out2; + input reset; + output locked; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + wire clk_out2; + wire locked; + wire reset; + + clk_wiz_0_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1), + .clk_out2(clk_out2), + .locked(locked), + .reset(reset)); +endmodule + +module clk_wiz_0_clk_wiz + (clk_out1, + clk_out2, + reset, + locked, + clk_in1); + output clk_out1; + output clk_out2; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire clk_in1_clk_wiz_0; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clk_out2; + wire clk_out2_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire locked; + wire reset; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout2_buf + (.I(clk_out2_clk_wiz_0), + .O(clk_out2)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(10.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(5.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(40), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(clk_out2_clk_wiz_0), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..fed34b1 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,198 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +-- Date : Wed Mar 11 01:32:49 2026 +-- Host : arya running 64-bit EndeavourOS Linux +-- Command : write_vhdl -force -mode funcsim +-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); +end clk_wiz_0_clk_wiz; + +architecture STRUCTURE of clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clk_out2_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +clkout2_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out2_clk_wiz_0, + O => clk_out2 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 10.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 5.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 40, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => clk_out2_clk_wiz_0, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => reset + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0 is + port ( + clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_wiz_0 : entity is true; +end clk_wiz_0; + +architecture STRUCTURE of clk_wiz_0 is +begin +inst: entity work.clk_wiz_0_clk_wiz + port map ( + clk_in1 => clk_in1, + clk_out1 => clk_out1, + clk_out2 => clk_out2, + locked => locked, + reset => reset + ); +end STRUCTURE; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..e131b23 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Wed Mar 11 01:32:49 2026 +// Host : arya running 64-bit EndeavourOS Linux +// Command : write_verilog -force -mode synth_stub +// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ +/* synthesis syn_force_seq_prim="clk_out1" */ +/* synthesis syn_force_seq_prim="clk_out2" */; + output clk_out1 /* synthesis syn_isclock = 1 */; + output clk_out2 /* synthesis syn_isclock = 1 */; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..c1fa710 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +-- Date : Wed Mar 11 01:32:49 2026 +-- Host : arya running 64-bit EndeavourOS Linux +-- Command : write_vhdl -force -mode synth_stub +-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; +end clk_wiz_0; + +architecture stub of clk_wiz_0 is + attribute syn_black_box : boolean; + attribute black_box_pad_pin : string; + attribute syn_black_box of stub : architecture is true; + attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; +begin +end; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt new file mode 100755 index 0000000..ae8e6b2 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt @@ -0,0 +1,355 @@ +2025.2: + * Version 6.0 (Rev. 17) + * General: Updated for 2025.2 + +2025.1.1: + * Version 6.0 (Rev. 16) + * No changes + +2025.1: + * Version 6.0 (Rev. 16) + * General: Updated IP Catalog taxonomy structure. This change has no impact to the IP. + +2024.2.2: + * Version 6.0 (Rev. 15) + * No changes + +2024.2.1: + * Version 6.0 (Rev. 15) + * No changes + +2024.2: + * Version 6.0 (Rev. 15) + * General: Updated for 2024.2 + +2024.1.2: + * Version 6.0 (Rev. 14) + * No changes + +2024.1.1: + * Version 6.0 (Rev. 14) + * No changes + +2024.1: + * Version 6.0 (Rev. 14) + * General: IP packaging adjustments to address warnings from IP Packager integrity check + +2023.2.2: + * Version 6.0 (Rev. 13) + * No changes + +2023.2.1: + * Version 6.0 (Rev. 13) + * No changes + +2023.2: + * Version 6.0 (Rev. 13) + * Bug Fix: CR Fixes + * Other: CR Fixes + +2023.1.2: + * Version 6.0 (Rev. 12) + * No changes + +2023.1.1: + * Version 6.0 (Rev. 12) + * No changes + +2023.1: + * Version 6.0 (Rev. 12) + * Bug Fix: CR Fixes + * Other: CR Fixes + +2022.2.2: + * Version 6.0 (Rev. 11) + * No changes + +2022.2.1: + * Version 6.0 (Rev. 11) + * No changes + +2022.2: + * Version 6.0 (Rev. 11) + * Bug Fix: CR Fixes + * Other: CR Fixes + +2022.1.2: + * Version 6.0 (Rev. 10) + * No changes + +2022.1.1: + * Version 6.0 (Rev. 10) + * No changes + +2022.1: + * Version 6.0 (Rev. 10) + * Bug Fix: CR Fixes + * Other: CR Fixes + +2021.2.2: + * Version 6.0 (Rev. 9) + * No changes + +2021.2.1: + * Version 6.0 (Rev. 9) + * No changes + +2021.2: + * Version 6.0 (Rev. 9) + * Bug Fix: CR Fixes + * Other: CR Fixes + +2021.1.1: + * Version 6.0 (Rev. 8) + * No changes + +2021.1: + * Version 6.0 (Rev. 8) + * Bug Fix: Internal GUI fixes + * Other: CR Fixes + +2020.3: + * Version 6.0 (Rev. 7) + * Bug Fix: Internal GUI fixes + * Other: CR Fixes + +2020.2.2: + * Version 6.0 (Rev. 6) + * No changes + +2020.2.1: + * Version 6.0 (Rev. 6) + * No changes + +2020.2: + * Version 6.0 (Rev. 6) + * Bug Fix: Internal GUI fixes + * Other: CR Fixes + +2020.1.1: + * Version 6.0 (Rev. 5) + * No changes + +2020.1: + * Version 6.0 (Rev. 5) + * Bug Fix: Internal GUI fixes + * Other: CR Fixes + +2019.2.2: + * Version 6.0 (Rev. 4) + * No changes + +2019.2.1: + * Version 6.0 (Rev. 4) + * No changes + +2019.2: + * Version 6.0 (Rev. 4) + * Bug Fix: Internal GUI fixes + * Other: CR Fixes + +2019.1.3: + * Version 6.0 (Rev. 3) + * No changes + +2019.1.2: + * Version 6.0 (Rev. 3) + * No changes + +2019.1.1: + * Version 6.0 (Rev. 3) + * No changes + +2019.1: + * Version 6.0 (Rev. 3) + * Bug Fix: Internal GUI fixes + * Other: New family support added + +2018.3.1: + * Version 6.0 (Rev. 2) + * No changes + +2018.3: + * Version 6.0 (Rev. 2) + * Bug Fix: Made input source independent for primary and secondary clock + * Other: New family support added + +2018.2: + * Version 6.0 (Rev. 1) + * Bug Fix: Removed vco freq check when Primitive is None + * Other: New family support added + +2018.1: + * Version 6.0 + * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature + * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI + * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. + * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support + * Other: DRCs added for invalid input values in Override mode + +2017.4: + * Version 5.4 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL + * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 + +2017.3: + * Version 5.4 (Rev. 2) + * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices + +2017.2: + * Version 5.4 (Rev. 1) + * General: Internal GUI changes. No effect on the customer design. + +2017.1: + * Version 5.4 + * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. + * Other: Added support for new zynq ultrascale plus devices. + +2016.4: + * Version 5.3 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed. + +2016.3: + * Version 5.3 (Rev. 2) + * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. + * Feature Enhancement: Added Matched Routing Option for better timing solutions. + * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. + * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user + * Other: Added support for Spartan7 devices. + +2016.2: + * Version 5.3 (Rev. 1) + * Internal register bit update, no effect on customer designs. + +2016.1: + * Version 5.3 + * Added Clock Monitor Feature as part of clocking wizard + * DRP registers can be directly written through AXI without resource utilization + * Changes to HDL library management to support Vivado IP simulation library + +2015.4.2: + * Version 5.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 5.2 (Rev. 1) + * No changes + +2015.4: + * Version 5.2 (Rev. 1) + * Internal device family change, no functional changes + +2015.3: + * Version 5.2 + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported + * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature + * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format + * Example design and simulation files are delivered in verilog only + +2015.2.1: + * Version 5.1 (Rev. 6) + * No changes + +2015.2: + * Version 5.1 (Rev. 6) + * No changes + +2015.1: + * Version 5.1 (Rev. 6) + * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.1 (Rev. 5) + * No changes + +2014.4: + * Version 5.1 (Rev. 5) + * Internal device family change, no functional changes + * updates related to the source selection based on board interface for zed board + +2014.3: + * Version 5.1 (Rev. 4) + * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface + +2014.2: + * Version 5.1 (Rev. 3) + * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 + +2014.1: + * Version 5.1 (Rev. 2) + * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock + * Internal device family name change, no functional changes + +2013.4: + * Version 5.1 (Rev. 1) + * Added support for Ultrascale devices + * Updated Board Flow GUI to select the clock interfaces + * Fixed issue with Stub file parameter error for BUFR output driver + +2013.3: + * Version 5.1 + * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL + * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies + * Fixed precision issues between displayed and actual frequencies + * Added tool tips to GUI + * Added Jitter and Phase error values to IP properties + * Added support for Cadence IES and Synopsys VCS simulators + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + +2013.2: + * Version 5.0 (Rev. 1) + * Fixed issue with clock constraints for multiple instances of clocking wizard + * Updated Life-Cycle status of devices + +2013.1: + * Version 5.0 + * Lower case ports for Verilog + * Added Safe Clock Startup and Clock Sequencing + +(c) Copyright 2008 - 2025 Advanced Micro Devices, Inc. All rights reserved. + +This file contains confidential and proprietary information +of AMD and is protected under U.S. and international copyright +and other intellectual property laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +AMD, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) AMD shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or AMD had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +AMD products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of AMD products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100755 index 0000000..6c4981a --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,680 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh new file mode 100755 index 0000000..b662a3e --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,542 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh new file mode 100755 index 0000000..154c81f --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,680 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh new file mode 100755 index 0000000..ff369d1 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,555 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100755 index 0000000..fd26211 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,886 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100755 index 0000000..0899943 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,561 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100755 index 0000000..c57b207 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,81 @@ + +// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1__200.00000______0.000______50.0______114.829_____98.575 +// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + .clk_out2(clk_out2), // output clk_out2 + // Status and control signals + .reset(reset), // input reset + .locked(locked), // output locked + // Clock in ports + .clk_in1(clk_in1) // input clk_in1 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..e131b23 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Wed Mar 11 01:32:49 2026 +// Host : arya running 64-bit EndeavourOS Linux +// Command : write_verilog -force -mode synth_stub +// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ +/* synthesis syn_force_seq_prim="clk_out1" */ +/* synthesis syn_force_seq_prim="clk_out2" */; + output clk_out1 /* synthesis syn_isclock = 1 */; + output clk_out2 /* synthesis syn_isclock = 1 */; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..c1fa710 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +-- Date : Wed Mar 11 01:32:49 2026 +-- Host : arya running 64-bit EndeavourOS Linux +-- Command : write_vhdl -force -mode synth_stub +-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; +end clk_wiz_0; + +architecture stub of clk_wiz_0 is + attribute syn_black_box : boolean; + attribute black_box_pad_pin : string; + attribute syn_black_box of stub : architecture is true; + attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; +begin +end; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100755 index 0000000..6c4981a --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,680 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh new file mode 100755 index 0000000..b662a3e --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,542 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh new file mode 100755 index 0000000..154c81f --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,680 @@ +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh new file mode 100755 index 0000000..ff369d1 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,555 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100755 index 0000000..fd26211 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,886 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100755 index 0000000..0899943 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,561 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: AMD +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh new file mode 100755 index 0000000..5bc4c64 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -0,0 +1,335 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : Siemens ModelSim Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'clk_wiz_0.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** + +# catch pipeline exit status +set -Eeuo pipefail + +# simulation root library directory +sim_lib_dir="modelsim_lib" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + simulate + fi +} + +# RUN_STEP: +compile() +{ + source compile.do 2>&1 | tee -a compile.log +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.cache/compile_simlib/modelsim" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + fi +} + +# create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + mkdir $lib_dir +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaborate.log simulate.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do new file mode 100644 index 0000000..2e49167 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt new file mode 100644 index 0000000..8121d70 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do new file mode 100644 index 0000000..543e3d7 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do @@ -0,0 +1,19 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +set NumericStdNoWarnings 1 +set StdArithNoWarnings 1 + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run 1000ns + +quit -force diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh new file mode 100755 index 0000000..0d604f9 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -0,0 +1,347 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : Siemens Questa Advanced Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'clk_wiz_0.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** +export SIM_VER_QUESTA= +export GCC_VER_QUESTA= + +# catch pipeline exit status +set -Eeuo pipefail + +# simulation root library directory +sim_lib_dir="questa_lib" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + source compile.do 2>&1 | tee -a compile.log +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.cache/compile_simlib/questa" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + fi +} + +# create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + mkdir $lib_dir +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaborate.log simulate.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do new file mode 100644 index 0000000..302cf97 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do new file mode 100644 index 0000000..327f0a7 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 -l elaborate.log +acc=npr -suppress 10016 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt new file mode 100644 index 0000000..8121d70 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do new file mode 100644 index 0000000..81ab20f --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do @@ -0,0 +1,19 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib clk_wiz_0_opt + +set NumericStdNoWarnings 1 +set StdArithNoWarnings 1 + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run 1000ns + +quit -force diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh new file mode 100755 index 0000000..1307451 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -0,0 +1,314 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'clk_wiz_0.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** +export SIM_VER_RIVIERA= +export GCC_VER_RIVIERA= + +# catch pipeline exit status +set -Eeuo pipefail + +# simulation root library directory +sim_lib_dir="riviera" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + simulate + fi +} + +# RUN_STEP: +compile() +{ + runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # map simulator index file + map_setup_file + fi +} + +# map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do new file mode 100644 index 0000000..93083a2 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do @@ -0,0 +1,25 @@ +transcript off +onbreak {quit -force} +onerror {quit -force} +transcript on + +vlib work +vlib riviera/xpm +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -incr "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" -l xpm -l xil_defaultlib \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 -incr \ +"/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -incr -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" -l xpm -l xil_defaultlib \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt new file mode 100644 index 0000000..8121d70 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do new file mode 100644 index 0000000..2873d98 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do @@ -0,0 +1,14 @@ +transcript off +onbreak {quit -force} +onerror {quit -force} +transcript on + +asim +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {clk_wiz_0.udo} + +run 1000ns + +endsim + +quit -force diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh new file mode 100755 index 0000000..2f2b698 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -0,0 +1,394 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'clk_wiz_0.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** +export SIM_VER_VCS= +export GCC_VER_VCS= + +# catch pipeline exit status +set -Eeuo pipefail + +# set vhdlan compile options +vhdlan_opts="-full64 -l .tmp_log" + +# set vlogan compile options +vlogan_opts="-full64 -l .tmp_log" + +# set vcs elaboration options +vcs_elab_opts="-full64 -debug_acc -t ps -licqueue -l elaborate.log" + +# set vcs simulation options +vcs_sim_opts="-ucli -licqueue -l simulate.log " + +# set design libraries +design_libs=(xpm xil_defaultlib) + +# simulation root library directory +sim_lib_dir="vcs_lib" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + vlogan -work xpm $vlogan_opts -sverilog +incdir+"../../../ipstatic" +incdir+"../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ + "/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null + + vhdlan -work xpm $vhdlan_opts \ + "/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log > vhdlan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../ipstatic" +incdir+"../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ + "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv +} + +# RUN_STEP: +simulate() +{ + ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # define design library mappings + create_lib_mappings + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($lib_map_path == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.cache/compile_simlib/vcs" + fi + + echo "LIBRARY_SCAN=TRUE" >> $file + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# create design library directory +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc clk_wiz_0_simv.daidir vcs_lib c.obj) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt new file mode 100644 index 0000000..8121d70 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do new file mode 100644 index 0000000..b77c6f1 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do @@ -0,0 +1,2 @@ +run 1000ns +quit diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh new file mode 100755 index 0000000..63a1c2e --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -0,0 +1,398 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library +# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help' +# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path +# switch with the directory path where the library is created while generating the script +# with export_simulation. +# +# Alternatively, you can set the library path by setting the following project property:- +# +# set_property compxlib._compiled_library_dir [current_project] +# +# You can also point to the simulation library by either setting the 'lib_map_path' global +# variable in this script or specify it with the '-lib_map_path' switch while executing this +# script (type 'clk_wiz_0.sh -help' for more information). +# +# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the +# generated script, but if design is targetted for system simulation containing SystemC/C++/C +# sources, then the library path MUST be specified upfront when calling export_simulation. +# +# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************** +export SIM_VER_XCELIUM= +export GCC_VER_XCELIUM= + +# catch pipeline exit status +set -Eeuo pipefail + +# set xmvhdl compile options +xmvhdl_opts="-64bit -messages -relax -logfile .tmp_log -update" + +# set xmvlog compile options +xmvlog_opts="-64bit -messages -logfile .tmp_log -update" + +# set xmelab elaboration options +xmelab_opts="-64bit -relax -access +r -namemap_mixgen -messages -logfile elaborate.log" + +# set xmsim simulation options +xmsim_opts="-64bit -logfile simulate.log" + +# set design libraries for elaboration +design_libs_elab="-libname xpm -libname xil_defaultlib -libname unisims_ver -libname unimacro_ver -libname secureip" + +# set design libraries +design_libs=(simprims_ver xpm xil_defaultlib) + +# simulation root library directory +sim_lib_dir="xcelium_lib" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + xmvlog -work xpm $xmvlog_opts -sv +incdir+"../../../ipstatic" +incdir+"../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ + "/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee compile.log; cat .tmp_log > xmvlog.log 2>/dev/null + + xmvhdl -work xpm -V93 $xmvhdl_opts \ + "/home/arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a compile.log; cat .tmp_log > xmvhdl.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../ipstatic" +incdir+"../../../../../../../../Xilinx2/2025.2/data/rsb/busdef" \ + "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null + + xmvlog -work xil_defaultlib $xmvlog_opts \ + glbl.v \ + 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null +} + +# RUN_STEP: +elaborate() +{ + xmelab $xmelab_opts $design_libs_elab xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl +} + +# RUN_STEP: +simulate() +{ + xmsim $xmsim_opts xil_defaultlib.clk_wiz_0 -input simulate.do +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous design library mappings + true + else + # define design library mappings + create_lib_mappings + fi + + if [[ ($b_keep_index == 1) ]]; then + # do not recreate design library directories + true + else + # create design library directories + create_lib_dir + fi +} + +# define design library mappings +create_lib_mappings() +{ + file="hdl.var" + touch $file + + file="cds.lib" + if [[ -e $file ]]; then + if [[ ($lib_map_path == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.cache/compile_simlib/xcelium" + fi + + if [[ ($lib_map_path != "") ]]; then + incl_ref="INCLUDE $lib_map_path/cds.lib" + echo $incl_ref >> $file + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="DEFINE $lib $sim_lib_dir/$lib" + echo $mapping >> $file + done +} + +# create design library directory +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log clk_wiz_0_sc.so .tmp_log xcelium_lib waves.shm c.obj) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log .tmp_log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt new file mode 100644 index 0000000..8121d70 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,arya/Xilinx2/2025.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var new file mode 100644 index 0000000..e69de29 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do new file mode 100644 index 0000000..baf3d48 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do @@ -0,0 +1,7 @@ +set pack_assert_off {numeric_std std_logic_arith} + +database -open waves -into waves.shm -default +catch {probe -create -shm -all -variables -depth 1} msg + +run 1000ns +exit diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt new file mode 100644 index 0000000..48b09e6 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -0,0 +1,50 @@ +################################################################################ +# Vivado (TM) v2025.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and how to fetch design source file details +# from the file_info.txt file. +# +# Generated by export_simulation on Wed Mar 11 01:32:32 EDT 2026 +# +################################################################################ + +1. Steps to run the generated simulation script + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first calls the 'check_args' function, the purpose of which +is to verify the generated script arguments and print error if incorrect switch +is specified. The 'run' function then calls the 'setup' function, the purpose of +which is to specify custom or initialization commands. The function also executes +following sub-functions:- +'reset_run' if -reset_run switch is specified. +'reset_log' if -reset_log switch is specified. + +The purpose of 'reset_run' function' is to delete the simulator generated design +data from the previous run and the purpose of 'reset_log' function' is to delete +the simulator generated log files. + +The 'run' function then calls the 'init_lib' function, the purpose of which is to +create design library mappings and directories. This function is called before the +'compile' step. By default, if '-step' switch is specified with the script then the +script will execute that specfic step, else it will execute all steps applicable +for the target simulator. + +For more information on the script, please type './clk_wiz_0.sh -help' + +2. Design source file information + +export_simulation generates a 'file_info.txt' file that contains design file information +based on the compile order when export_simulation was executed from Vivado. The file +contains information about the file name, type, library it is compiled into, whether +it is part of the IP, associated library, file path information in a comma separated +format. This file can be parsed to extract the required information for generating a +custom script or can be read from verification test infra. + diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh new file mode 100755 index 0000000..aa5c174 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -0,0 +1,387 @@ +#!/bin/bash -f +#********************************************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Script generated by Vivado on Wed Mar 11 01:32:32 EDT 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Filename : clk_wiz_0.sh +# Simulator : AMD Vivado Simulator +# Description : Simulation script generated by export_simulation Tcl command +# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the +# design. The script will copy the library mapping file from the compiled library directory, +# create design library directories and library mappings in the mapping file. +# +# Usage : clk_wiz_0.sh +# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]* +# clk_wiz_0.sh [-rerun] +# clk_wiz_0.sh [-reset_run] +# clk_wiz_0.sh [-clean] +# clk_wiz_0.sh [-reset_log] +# clk_wiz_0.sh [-help] +# +# * The -noclean_files switch is deprecated and will not peform any function (by default, the +# simulator generated files will not be removed unless -reset_run switch is used) +# +#********************************************************************************************************** +export SIM_VER_XSIM= +export GCC_VER_XSIM= + +# catch pipeline exit status +set -Eeuo pipefail + +# resolve compiled library path in xsim.ini +export RDI_DATADIR="/home/arya/Xilinx2/2025.2/data" + +# set xvlog options +xvlog_opts="--incr --relax " + +# simulation root library directory +sim_lib_dir="xsim.dir" + +# script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2025.2 (64-bit)-id)\n" + +# main steps +run() +{ + check_args $* + setup + if [[ ($b_step == 1) ]]; then + case $step in + "compile" ) + init_lib + compile + ;; + "elaborate" ) + elaborate + ;; + "simulate" ) + simulate + ;; + * ) + echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + esac + else + init_lib + compile + elaborate + simulate + fi +} + +# RUN_STEP: +compile() +{ + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log +} + +# RUN_STEP: +elaborate() +{ + xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + # delete previous files for a clean rerun + if [[ ($b_reset_run == 1) ]]; then + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + fi + + # delete previous design library generated data + if [[ ($b_clean == 1) ]]; then + clean + echo -e "INFO: Design library generated data deleted.\n" + exit 0 + fi + + # delete previous log files + if [[ ($b_reset_log == 1) ]]; then + reset_log + echo -e "INFO: Simulation run log files deleted.\n" + exit 0 + fi + + # add any setup/initialization commands here:- + + # + +} + +# simulator index file/library directory processing +init_lib() +{ + if [[ ($b_rerun == 1) ]]; then + # keep previous state for incremental run + return 0 + fi + + if [[ ($b_keep_index == 1) ]]; then + # keep previous simulator index file + true + else + # copy simulator index file to current directory + copy_setup_file + fi + + if [[ ($lib_map_path != "") ]]; then + ref_lib_dir=$lib_map_path + fi +} + +# copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + + if [[ ($lib_map_path == "") ]]; then + lib_map_path="/home/arya/Xilinx2/2025.2/data/xsim" + fi + + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # map local design libraries to xsim.ini + map_local_libs + fi +} + +# map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + + # create a backup copy of the xsim.ini file + cp $file $file_backup + + # read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + + # split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + + # if local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + + # add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + + # append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + + if [[ (${#local_mappings[@]} -eq 0) ]] ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + elif `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + + # write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir libdpi.so) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# delete generated design library data from the previous run +clean() +{ + files_to_remove=("${design_libs[@]}") + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="$sim_lib_dir/${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + # delete design library directory + rm -rf $sim_lib_dir +} + +# delete generated log files from the previous run +reset_log() +{ + files_to_remove=(xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# check switch argument value +check_arg_value() +{ + if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then + echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi +} + +# check command line arguments +check_args() +{ + arg_count=$# + if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then + usage + fi + while [[ "$#" -gt 0 ]]; do + case $1 in + -step) check_arg_value $1 $2;step=$2; b_step=1; shift;; + -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;; + -gen_bypass) b_gen_bypass=1 ;; + -rerun) b_rerun=1 ;; + -reset_run) b_reset_run=1 ;; + -clean) b_clean=1 ;; + -reset_log) b_reset_log=1 ;; + -keep_index) b_keep_index=1 ;; + -noclean_files) b_noclean_files=1 ;; + -help|-h) ;; + *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;; + esac + shift + done + + # -reset_run is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then + echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -clean is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then + echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -reset_log is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then + echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -keep_index is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then + echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi + + # -noclean_files is not applicable with other switches + if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then + echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n" + exit 1 + fi +} + +# script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-step]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-rerun]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-clean]\n\ +Usage: clk_wiz_0.sh [-reset_log]\n\ +Usage: clk_wiz_0.sh [-keep_index]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-step ] -- Execute specified step (compile, elaborate, simulate)\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\ +To rerun a specific step, pass the -step switch in addition to -rerun switch.\n\n\ +[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\ +file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\ +NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\ +NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\ +[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\ +execute steps defined in the script.\n\n\ +[-reset_log] -- Delete simulator generated log files from the previous run\n\n\ +[-keep_index] -- Keep simulator index file settings from the previous run\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n" + echo -e $msg + exit 0 +} + +# initialize globals +step="" +lib_map_path="" +b_step=0 +b_lib_map_path=0 +b_gen_bypass=0 +b_rerun=0 +b_reset_run=0 +b_clean=0 +b_reset_log=0 +b_keep_index=0 +b_noclean_files=0 + +# launch script +run $* diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl new file mode 100644 index 0000000..6ac0dc8 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns +quit diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt new file mode 100644 index 0000000..d469d95 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt @@ -0,0 +1,3 @@ +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../../../../../../Xilinx2/2025.2/data/rsb/busdef"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..26b6580 --- /dev/null +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,690 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "clk_wiz_0", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "17", + "gen_directory": "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "clk_wiz_0", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], + "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "114.829", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], + "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "c_component_name": [ { "value": "clk_wiz_0", "resolve_type": "generated", "usage": "all" } ], + "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ], + "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ], + "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ], + "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ], + "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], + "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], + "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ], + "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__200.00000______0.000______50.0______114.829_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ], + "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ], + "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ], + "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ], + "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ], + "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ], + "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ], + "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ], + "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ], + "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ], + "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ], + "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ], + "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ], + "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ], + "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ], + "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ], + "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ], + "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ], + "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], + "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], + "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], + "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ], + "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ], + "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "8.0", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.2", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.2", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.2", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.2", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.2", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], + "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "BASE_BOARD_PART": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "BOARD_CONNECTIONS": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "DEVICE": [ { "value": "xc7a35t", "resolve_type": "generated", "usage": "all" } ], + "PACKAGE": [ { "value": "cpg236", "resolve_type": "generated", "usage": "all" } ], + "PREFHDL": [ { "value": "VERILOG", "resolve_type": "generated", "usage": "all" } ], + "SILICON_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED", "resolve_type": "generated", "usage": "all" } ], + "SPEEDGRADE": [ { "value": "-1", "resolve_type": "generated", "usage": "all" } ], + "STATIC_POWER": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], + "TEMPERATURE_GRADE": [ { "value": "", "resolve_type": "generated", "usage": "all" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "17" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2025.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "reset": [ { "direction": "in", "driver_value": "0" } ], + "clk_in1": [ { "direction": "in" } ], + "clk_out1": [ { "direction": "out" } ], + "clk_out2": [ { "direction": "out" } ], + "locked": [ { "direction": "out" } ] + }, + "interfaces": { + "reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "reset" } ] + } + }, + "clock_CLK_IN1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] + }, + "port_maps": { + "CLK_IN1": [ { "physical_name": "clk_in1" } ] + } + }, + "clock_CLK_OUT1": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + }, + "clock_CLK_OUT2": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT2": [ { "physical_name": "clk_out2" } ] + } + } + } + } + }, + "checksum": "ae444813" +} \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v index 1a1cf91..cee8080 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v @@ -54,7 +54,7 @@ module Top( wire [31:0] debug_1, debug_2; Main cpu ( - .clock (clk_25), + .clock (clk), .reset (reset), .io_execute (execute), .io_debug_write (debug_write), @@ -66,8 +66,8 @@ module Top( .io_vsync (vgaVSync), .io_rgb (rgb), .io_blanking (blanking), - .io_vga_clk (clk_25) -// .io_btns(btns) + .io_vga_clk (clk_25), + .io_btns(btns) ); diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 3d30847..8313f8b 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -4,7 +4,7 @@ - +