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Use highest numbered MPU regions for kernel
ARMv7-M allows overlapping MPU regions. When 2 MPU regions overlap, the MPU configuration of the higher numbered MPU region is applied. For example, if a memory area is covered by 2 MPU regions 0 and 1, the memory permissions for MPU region 1 are applied. We use 5 MPU regions for kernel code and kernel data protections and leave the remaining for the application writer. We were using lowest numbered MPU regions (0-4) for kernel protections and leaving the remaining for the application writer. The application writer could configure those higher numbered MPU regions to override kernel protections. This commit changes the code to use highest numbered MPU regions for kernel protections and leave the remaining for the application writer. This ensures that the application writer cannot override kernel protections. We thank the SecLab team at Northeastern University for reporting this issue. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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8 files changed

+79
-134
lines changed

8 files changed

+79
-134
lines changed

‎portable/GCC/ARM_CM3_MPU/port.c‎

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -731,31 +731,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
731731
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
732732
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
733733
( portMPU_REGION_VALID ) |
734-
( portSTACK_REGION );
734+
( portSTACK_REGION ); /* Region number. */
735735

736736
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
737737
( portMPU_REGION_READ_WRITE ) |
738738
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
739739
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
740740
( portMPU_REGION_ENABLE );
741741

742-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
743-
* just removed the privileged only parameters. */
744-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
745-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
746-
( portMPU_REGION_VALID ) |
747-
( portSTACK_REGION + 1 );
748-
749-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
750-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
751-
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
752-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
753-
( portMPU_REGION_ENABLE );
754-
755-
/* Invalidate all other regions. */
756-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
742+
/* Invalidate user configurable regions. */
743+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
757744
{
758-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
745+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
759746
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
760747
}
761748
}
@@ -782,7 +769,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
782769

783770
lIndex = 0;
784771

785-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
772+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
786773
{
787774
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
788775
{
@@ -792,7 +779,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
792779
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
793780
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
794781
( portMPU_REGION_VALID ) |
795-
( portSTACK_REGION + ul ); /* Region number. */
782+
( ul - 1UL ); /* Region number. */
796783

797784
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
798785
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -802,7 +789,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
802789
else
803790
{
804791
/* Invalidate the region. */
805-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
792+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
806793
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
807794
}
808795

‎portable/GCC/ARM_CM3_MPU/portmacro.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -81,15 +81,15 @@
8181
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
8282
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
8383

84-
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
85-
#define portPRIVILEGED_FLASH_REGION ( 1UL )
86-
#define portPRIVILEGED_RAM_REGION ( 2UL )
8784
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
8885
#define portSTACK_REGION ( 4UL )
89-
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
90-
#define portLAST_CONFIGURABLE_REGION ( 7UL )
86+
#define portUNPRIVILEGED_FLASH_REGION ( 5UL )
87+
#define portPRIVILEGED_FLASH_REGION ( 6UL )
88+
#define portPRIVILEGED_RAM_REGION ( 7UL )
89+
#define portFIRST_CONFIGURABLE_REGION ( 0UL )
90+
#define portLAST_CONFIGURABLE_REGION ( 2UL )
9191
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
92-
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
92+
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
9393

9494
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
9595

@@ -102,7 +102,7 @@
102102
/* Plus 1 to create space for the stack region. */
103103
typedef struct MPU_SETTINGS
104104
{
105-
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
105+
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
106106
} xMPU_SETTINGS;
107107

108108
/* Architecture specifics. */

‎portable/GCC/ARM_CM4_MPU/port.c‎

Lines changed: 13 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@
6868
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
6969
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
7070
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
71-
#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
71+
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
7272
#define portMPU_ENABLE ( 0x01UL )
7373
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
7474
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -359,12 +359,12 @@ static void prvRestoreContextOfFirstTask( void )
359359
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
360360
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
361361
" \n"
362-
#if ( portTOTAL_NUM_REGIONS == 16 )
362+
#if ( configTOTAL_MPU_REGIONS == 16 )
363363
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
364364
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
365365
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
366366
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
367-
#endif /* portTOTAL_NUM_REGIONS == 16. */
367+
#endif /* configTOTAL_MPU_REGIONS == 16. */
368368
" \n"
369369
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
370370
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -585,12 +585,12 @@ void xPortPendSVHandler( void )
585585
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
586586
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
587587
" \n"
588-
#if ( portTOTAL_NUM_REGIONS == 16 )
588+
#if ( configTOTAL_MPU_REGIONS == 16 )
589589
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
590590
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
591591
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
592592
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
593-
#endif /* portTOTAL_NUM_REGIONS == 16. */
593+
#endif /* configTOTAL_MPU_REGIONS == 16. */
594594
" \n"
595595
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
596596
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -687,7 +687,7 @@ static void prvSetupMPU( void )
687687
#endif /* if defined( __ARMCC_VERSION ) */
688688

689689
/* The only permitted number of regions are 8 or 16. */
690-
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
690+
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
691691

692692
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
693693
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -830,31 +830,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
830830
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
831831
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
832832
( portMPU_REGION_VALID ) |
833-
( portSTACK_REGION );
833+
( portSTACK_REGION ); /* Region number. */
834834

835835
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
836836
( portMPU_REGION_READ_WRITE ) |
837837
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
838838
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
839839
( portMPU_REGION_ENABLE );
840840

841-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
842-
* just removed the privileged only parameters. */
843-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
844-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
845-
( portMPU_REGION_VALID ) |
846-
( portSTACK_REGION + 1 );
847-
848-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
849-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
850-
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
851-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
852-
( portMPU_REGION_ENABLE );
853-
854-
/* Invalidate all other regions. */
855-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
841+
/* Invalidate user configurable regions. */
842+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
856843
{
857-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
844+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
858845
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
859846
}
860847
}
@@ -881,7 +868,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
881868

882869
lIndex = 0;
883870

884-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
871+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
885872
{
886873
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
887874
{
@@ -891,7 +878,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
891878
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
892879
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
893880
( portMPU_REGION_VALID ) |
894-
( portSTACK_REGION + ul ); /* Region number. */
881+
( ul - 1UL ); /* Region number. */
895882

896883
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
897884
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -901,7 +888,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
901888
else
902889
{
903890
/* Invalidate the region. */
904-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
891+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
905892
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
906893
}
907894

‎portable/GCC/ARM_CM4_MPU/portmacro.h‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -170,15 +170,15 @@ typedef unsigned long UBaseType_t;
170170
#define configTEX_S_C_B_SRAM ( 0x07UL )
171171
#endif
172172

173-
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
174-
#define portPRIVILEGED_FLASH_REGION ( 1UL )
175-
#define portPRIVILEGED_RAM_REGION ( 2UL )
176-
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
177-
#define portSTACK_REGION ( 4UL )
178-
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
179-
#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
180-
#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
181-
#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
173+
#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
174+
#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
175+
#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
176+
#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
177+
#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
178+
#define portFIRST_CONFIGURABLE_REGION ( 0UL )
179+
#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
180+
#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
181+
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
182182

183183
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
184184

@@ -188,10 +188,9 @@ typedef struct MPU_REGION_REGISTERS
188188
uint32_t ulRegionAttribute;
189189
} xMPU_REGION_REGISTERS;
190190

191-
/* Plus 1 to create space for the stack region. */
192191
typedef struct MPU_SETTINGS
193192
{
194-
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
193+
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
195194
} xMPU_SETTINGS;
196195

197196
/* Architecture specifics. */

‎portable/IAR/ARM_CM4F_MPU/port.c‎

Lines changed: 9 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@
7575
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
7676
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
7777
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
78-
#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
78+
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
7979
#define portMPU_ENABLE ( 0x01UL )
8080
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
8181
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -526,7 +526,7 @@ static void prvSetupMPU( void )
526526
extern uint32_t __privileged_data_end__[];
527527

528528
/* The only permitted number of regions are 8 or 16. */
529-
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
529+
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
530530

531531
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
532532
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -627,31 +627,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
627627
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
628628
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
629629
( portMPU_REGION_VALID ) |
630-
( portSTACK_REGION );
630+
( portSTACK_REGION ); /* Region number. */
631631

632632
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
633633
( portMPU_REGION_READ_WRITE ) |
634634
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
635635
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
636636
( portMPU_REGION_ENABLE );
637637

638-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
639-
* just removed the privileged only parameters. */
640-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
641-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
642-
( portMPU_REGION_VALID ) |
643-
( portSTACK_REGION + 1 );
644-
645-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
646-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
647-
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
648-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
649-
( portMPU_REGION_ENABLE );
650-
651-
/* Invalidate all other regions. */
652-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
638+
/* Invalidate user configurable regions. */
639+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
653640
{
654-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
641+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
655642
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
656643
}
657644
}
@@ -678,7 +665,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
678665

679666
lIndex = 0;
680667

681-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
668+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
682669
{
683670
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
684671
{
@@ -688,7 +675,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
688675
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
689676
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
690677
( portMPU_REGION_VALID ) |
691-
( portSTACK_REGION + ul ); /* Region number. */
678+
( ul - 1UL ); /* Region number. */
692679

693680
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
694681
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -698,7 +685,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
698685
else
699686
{
700687
/* Invalidate the region. */
701-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
688+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
702689
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
703690
}
704691

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