From d0e8e9c02359a2f2a3560f7d8e3473bafb37fa92 Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:27:07 +0530 Subject: [PATCH 01/10] CD4518B is a dual BCD up counter IC. --- .../SubcircuitLibrary/cd4518b/3_and-cache.lib | 61 + library/SubcircuitLibrary/cd4518b/3_and.cir | 13 + .../SubcircuitLibrary/cd4518b/3_and.cir.out | 20 + library/SubcircuitLibrary/cd4518b/3_and.pro | 43 + library/SubcircuitLibrary/cd4518b/3_and.sch | 130 + library/SubcircuitLibrary/cd4518b/3_and.sub | 14 + .../cd4518b/3_and_Previous_Values.xml | 1 + .../cd4518b/_autosave-cd4518b.sch | 636 ++++ library/SubcircuitLibrary/cd4518b/analysis | 1 + library/SubcircuitLibrary/cd4518b/cd4518b.cir | 41 + .../SubcircuitLibrary/cd4518b/cd4518b.cir.out | 156 + .../cd4518b/cd4518b.kicad_sch | 2691 +++++++++++++++++ library/SubcircuitLibrary/cd4518b/cd4518b.sub | 150 + .../cd4518b/cd4518b_Previous_Values.xml | 1 + 14 files changed, 3958 insertions(+) create mode 100644 library/SubcircuitLibrary/cd4518b/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/cd4518b/3_and.cir create mode 100644 library/SubcircuitLibrary/cd4518b/3_and.cir.out create mode 100644 library/SubcircuitLibrary/cd4518b/3_and.pro create mode 100644 library/SubcircuitLibrary/cd4518b/3_and.sch create mode 100644 library/SubcircuitLibrary/cd4518b/3_and.sub create mode 100644 library/SubcircuitLibrary/cd4518b/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/cd4518b/_autosave-cd4518b.sch create mode 100644 library/SubcircuitLibrary/cd4518b/analysis create mode 100644 library/SubcircuitLibrary/cd4518b/cd4518b.cir create mode 100644 library/SubcircuitLibrary/cd4518b/cd4518b.cir.out create mode 100644 library/SubcircuitLibrary/cd4518b/cd4518b.kicad_sch create mode 100644 library/SubcircuitLibrary/cd4518b/cd4518b.sub create mode 100644 library/SubcircuitLibrary/cd4518b/cd4518b_Previous_Values.xml diff --git a/library/SubcircuitLibrary/cd4518b/3_and-cache.lib b/library/SubcircuitLibrary/cd4518b/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/cd4518b/3_and.cir b/library/SubcircuitLibrary/cd4518b/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/cd4518b/3_and.cir.out b/library/SubcircuitLibrary/cd4518b/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/cd4518b/3_and.pro b/library/SubcircuitLibrary/cd4518b/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/cd4518b/3_and.sch b/library/SubcircuitLibrary/cd4518b/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 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4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/cd4518b/3_and.sub b/library/SubcircuitLibrary/cd4518b/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4518b/3_and_Previous_Values.xml b/library/SubcircuitLibrary/cd4518b/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4518b/_autosave-cd4518b.sch b/library/SubcircuitLibrary/cd4518b/_autosave-cd4518b.sch new file mode 100644 index 000000000..02680040b --- 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0000 C CNN +F 3 "" H 10800 1200 60 0000 C CNN + 14 10800 1200 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U2 +U 1 1 00000000 +P 550 4700 +F 0 "U2" H 550 4950 60 0000 C CNN +F 1 "d_inverter" H 550 4800 60 0000 C CNN +F 2 "" H 600 4650 60 0000 C CNN +F 3 "" H 600 4650 60 0000 C CNN + 1 550 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U3 +U 1 1 00000000 +P 950 5900 +F 0 "U3" H 950 6150 60 0000 C CNN +F 1 "d_inverter" H 950 6000 60 0000 C CNN +F 2 "" H 1000 5850 60 0000 C CNN +F 3 "" H 1000 5850 60 0000 C CNN + 1 950 5900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U4 +U 1 1 00000000 +P 1400 4700 +F 0 "U4" H 1400 4950 60 0000 C CNN +F 1 "d_inverter" H 1400 4800 60 0000 C CNN +F 2 "" H 1450 4650 60 0000 C CNN +F 3 "" H 1450 4650 60 0000 C CNN + 1 1400 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U7 +U 1 1 00000000 +P 3050 1500 +F 0 "U7" V 3100 1400 60 0000 R CNN +F 1 "d_inverter" V 2950 1400 60 0000 R CNN +F 2 "" H 3100 1450 60 0000 C CNN +F 3 "" H 3100 1450 60 0000 C CNN + 1 3050 1500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U8 +U 1 1 00000000 +P 3050 2400 +F 0 "U8" V 3100 2300 60 0000 R CNN +F 1 "d_inverter" V 2950 2300 60 0000 R CNN +F 2 "" H 3100 2350 60 0000 C CNN +F 3 "" H 3100 2350 60 0000 C CNN + 1 3050 2400 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U10 +U 1 1 00000000 +P 5600 1550 +F 0 "U10" V 5650 1450 60 0000 R CNN +F 1 "d_inverter" V 5500 1450 60 0000 R CNN +F 2 "" H 5650 1500 60 0000 C CNN +F 3 "" H 5650 1500 60 0000 C CNN + 1 5600 1550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U11 +U 1 1 00000000 +P 5600 2450 +F 0 "U11" V 5650 2350 60 0000 R CNN +F 1 "d_inverter" V 5500 2350 60 0000 R CNN +F 2 "" H 5650 2400 60 0000 C CNN +F 3 "" H 5650 2400 60 0000 C CNN + 1 5600 2450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U14 +U 1 1 00000000 +P 8250 1550 +F 0 "U14" V 8300 1450 60 0000 R CNN +F 1 "d_inverter" V 8150 1450 60 0000 R CNN +F 2 "" H 8300 1500 60 0000 C CNN +F 3 "" H 8300 1500 60 0000 C CNN + 1 8250 1550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U15 +U 1 1 00000000 +P 8250 2450 +F 0 "U15" V 8300 2350 60 0000 R CNN +F 1 "d_inverter" V 8150 2350 60 0000 R CNN +F 2 "" H 8300 2400 60 0000 C CNN +F 3 "" H 8300 2400 60 0000 C CNN + 1 8250 2450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U18 +U 1 1 00000000 +P 10400 4850 +F 0 "U18" V 10350 4950 60 0000 L CNN +F 1 "d_inverter" V 10500 4950 60 0000 L CNN +F 2 "" H 10450 4800 60 0000 C CNN +F 3 "" H 10450 4800 60 0000 C CNN + 1 10400 4850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U19 +U 1 1 00000000 +P 10550 1550 +F 0 "U19" V 10600 1450 60 0000 R CNN +F 1 "d_inverter" V 10450 1450 60 0000 R CNN +F 2 "" H 10600 1500 60 0000 C CNN +F 3 "" H 10600 1500 60 0000 C CNN + 1 10550 1550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U20 +U 1 1 00000000 +P 10550 2450 +F 0 "U20" V 10600 2350 60 0000 R CNN +F 1 "d_inverter" V 10450 2350 60 0000 R CNN +F 2 "" H 10600 2400 60 0000 C CNN +F 3 "" H 10600 2400 60 0000 C CNN + 1 10550 2450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_nand U5 +U 1 1 00000000 +P 1800 5900 +F 0 "U5" H 1800 6250 60 0000 C CNN +F 1 "d_nand" H 1800 6100 60 0000 C CNN +F 2 "" H 1800 5900 60 0000 C CNN +F 3 "" H 1800 5900 60 0000 C CNN + 1 1800 5900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U13 +U 1 1 00000000 +P 7350 6400 +F 0 "U13" H 7350 6750 60 0000 C CNN +F 1 "d_and" H 7350 6600 60 0000 C CNN +F 2 "" H 7350 6400 60 0000 C CNN +F 3 "" H 7350 6400 60 0000 C CNN + 1 7350 6400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nor U16 +U 1 1 00000000 +P 9300 6350 +F 0 "U16" V 9350 6250 60 0000 R CNN +F 1 "d_nor" V 9200 6250 60 0000 R CNN +F 2 "" H 9300 6350 60 0000 C CNN +F 3 "" H 9300 6350 60 0000 C CNN + 1 9300 6350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Subckt:3_and X1 +U 1 1 00000000 +P 3700 5250 +F 0 "X1" V 3829 5100 60 0000 R CNN +F 1 "3_and" V 3679 5100 60 0000 R CNN +F 2 "" H 3700 5250 60 0000 C CNN +F 3 "" H 3700 5250 60 0000 C CNN + 1 3700 5250 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Subckt:3_and X2 +U 1 1 00000000 +P 6650 5350 +F 0 "X2" V 6779 5200 60 0000 R CNN +F 1 "3_and" V 6629 5200 60 0000 R CNN +F 2 "" H 6650 5350 60 0000 C CNN +F 3 "" H 6650 5350 60 0000 C CNN + 1 6650 5350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Subckt:3_and X3 +U 1 1 00000000 +P 8900 5350 +F 0 "X3" V 9029 5200 60 0000 R CNN +F 1 "3_and" V 8879 5200 60 0000 R CNN +F 2 "" H 8900 5350 60 0000 C CNN +F 3 "" H 8900 5350 60 0000 C CNN + 1 8900 5350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_dff U6 +U 1 1 00000000 +P 2150 3550 +F 0 "U6" H 2230 4200 60 0000 L CNN +F 1 "d_dff" H 2230 4050 60 0000 L CNN +F 2 "" H 2150 3550 60 0000 C CNN +F 3 "" H 2150 3550 60 0000 C CNN + 1 2150 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U9 +U 1 1 00000000 +P 4700 3600 +F 0 "U9" H 4780 4250 60 0000 L CNN +F 1 "d_dff" H 4780 4100 60 0000 L CNN +F 2 "" H 4700 3600 60 0000 C CNN +F 3 "" H 4700 3600 60 0000 C CNN + 1 4700 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U12 +U 1 1 00000000 +P 7350 3600 +F 0 "U12" H 7430 4250 60 0000 L CNN +F 1 "d_dff" H 7430 4100 60 0000 L CNN +F 2 "" H 7350 3600 60 0000 C CNN +F 3 "" H 7350 3600 60 0000 C CNN + 1 7350 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U17 +U 1 1 00000000 +P 9650 3600 +F 0 "U17" H 9730 4250 60 0000 L CNN +F 1 "d_dff" H 9730 4100 60 0000 L CNN +F 2 "" H 9650 3600 60 0000 C CNN +F 3 "" H 9650 3600 60 0000 C CNN + 1 9650 3600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/cd4518b/analysis b/library/SubcircuitLibrary/cd4518b/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4518b/cd4518b.cir b/library/SubcircuitLibrary/cd4518b/cd4518b.cir new file mode 100644 index 000000000..4d7444823 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/cd4518b.cir @@ -0,0 +1,41 @@ +.title KiCad schematic +U6 Net-_U1-Pad10_ Net-_U3-Pad2_ Net-_U11-Pad1_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND Net-_U1-Pad1_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND PORT +U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U8 Net-_U11-Pad1_ Net-_U4-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U13 Net-_U10-Pad2_ Net-_U13-Pad2_ d_inverter +U18 Net-_U11-Pad1_ Net-_U18-Pad2_ d_inverter +X2 Net-_U18-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U20-Pad1_ 3_and +U21 Net-_U10-Pad2_ Net-_U21-Pad2_ d_inverter +U19 Net-_U15-Pad1_ Net-_U19-Pad2_ d_inverter +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U24 Net-_U23-Pad1_ Net-_U20-Pad2_ unconnected-_U24-Pad3_ Net-_U15-Pad4_ Net-_U24-Pad5_ Net-_U23-Pad1_ d_dff +X1 Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U12-Pad1_ 3_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U12-Pad2_ unconnected-_U15-Pad3_ Net-_U15-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad1_ d_dff +U16 Net-_U16-Pad1_ Net-_U1-Pad12_ d_inverter +U17 Net-_U15-Pad5_ Net-_U16-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U9 Net-_U10-Pad2_ Net-_U1-Pad11_ d_inverter +U22 Net-_U15-Pad1_ Net-_U22-Pad2_ d_inverter +U25 Net-_U23-Pad2_ Net-_U19-Pad2_ Net-_U25-Pad3_ d_and +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ d_inverter +U31 Net-_U25-Pad3_ Net-_U14-Pad1_ Net-_U31-Pad3_ d_nor +U32 Net-_U31-Pad3_ Net-_U32-Pad2_ d_inverter +U29 Net-_U10-Pad2_ Net-_U29-Pad2_ d_inverter +X3 Net-_U26-Pad2_ Net-_U29-Pad2_ Net-_U32-Pad2_ Net-_U30-Pad1_ 3_and +U26 Net-_U11-Pad1_ Net-_U26-Pad2_ d_inverter +U34 Net-_U33-Pad1_ Net-_U14-Pad1_ d_inverter +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U28 Net-_U24-Pad5_ Net-_U27-Pad1_ d_inverter +U27 Net-_U27-Pad1_ Net-_U1-Pad13_ d_inverter +U36 Net-_U33-Pad5_ Net-_U35-Pad1_ d_inverter +U35 Net-_U35-Pad1_ Net-_U1-Pad14_ d_inverter +U33 Net-_U33-Pad1_ Net-_U30-Pad2_ unconnected-_U33-Pad3_ Net-_U15-Pad4_ Net-_U33-Pad5_ Net-_U33-Pad1_ d_dff +U7 Net-_U7-Pad1_ Net-_U4-Pad2_ unconnected-_U7-Pad3_ Net-_U15-Pad4_ Net-_U10-Pad1_ Net-_U7-Pad1_ d_dff +U5 Net-_U2-Pad2_ Net-_U15-Pad4_ d_inverter +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ d_inverter +U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/cd4518b/cd4518b.cir.out b/library/SubcircuitLibrary/cd4518b/cd4518b.cir.out new file mode 100644 index 000000000..c6a7bee15 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/cd4518b.cir.out @@ -0,0 +1,156 @@ +.title kicad schematic + +.include 3_and.sub +* u6 net-_u1-pad10_ net-_u3-pad2_ net-_u11-pad1_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd port +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u11-pad1_ net-_u4-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u13 net-_u10-pad2_ net-_u13-pad2_ d_inverter +* u18 net-_u11-pad1_ net-_u18-pad2_ d_inverter +x2 net-_u18-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u20-pad1_ 3_and +* u21 net-_u10-pad2_ net-_u21-pad2_ d_inverter +* u19 net-_u15-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u24 net-_u23-pad1_ net-_u20-pad2_ unconnected-_u24-pad3_ net-_u15-pad4_ net-_u24-pad5_ net-_u23-pad1_ d_dff +x1 net-_u11-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ d_dff +* u16 net-_u16-pad1_ net-_u1-pad12_ d_inverter +* u17 net-_u15-pad5_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u9 net-_u10-pad2_ net-_u1-pad11_ d_inverter +* u22 net-_u15-pad1_ net-_u22-pad2_ d_inverter +* u25 net-_u23-pad2_ net-_u19-pad2_ net-_u25-pad3_ d_and +* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter +* u31 net-_u25-pad3_ net-_u14-pad1_ net-_u31-pad3_ d_nor +* u32 net-_u31-pad3_ net-_u32-pad2_ d_inverter +* u29 net-_u10-pad2_ net-_u29-pad2_ d_inverter +x3 net-_u26-pad2_ net-_u29-pad2_ net-_u32-pad2_ net-_u30-pad1_ 3_and +* u26 net-_u11-pad1_ net-_u26-pad2_ d_inverter +* u34 net-_u33-pad1_ net-_u14-pad1_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u28 net-_u24-pad5_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad13_ d_inverter +* u36 net-_u33-pad5_ net-_u35-pad1_ d_inverter +* u35 net-_u35-pad1_ net-_u1-pad14_ d_inverter +* u33 net-_u33-pad1_ net-_u30-pad2_ unconnected-_u33-pad3_ net-_u15-pad4_ net-_u33-pad5_ net-_u33-pad1_ d_dff +* u7 net-_u7-pad1_ net-_u4-pad2_ unconnected-_u7-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u7-pad1_ d_dff +* u5 net-_u2-pad2_ net-_u15-pad4_ d_inverter +* u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +a1 [net-_u1-pad10_ net-_u3-pad2_ ] net-_u11-pad1_ u6 +a2 net-_u1-pad1_ net-_u3-pad2_ u3 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 net-_u11-pad1_ net-_u4-pad1_ u8 +a5 net-_u14-pad1_ net-_u14-pad2_ u14 +a6 net-_u10-pad2_ net-_u13-pad2_ u13 +a7 net-_u11-pad1_ net-_u18-pad2_ u18 +a8 net-_u10-pad2_ net-_u21-pad2_ u21 +a9 net-_u15-pad1_ net-_u19-pad2_ u19 +a10 net-_u20-pad1_ net-_u20-pad2_ u20 +a11 net-_u23-pad1_ net-_u20-pad2_ unconnected-_u24-pad3_ net-_u15-pad4_ net-_u24-pad5_ net-_u23-pad1_ u24 +a12 net-_u12-pad1_ net-_u12-pad2_ u12 +a13 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ u15 +a14 net-_u16-pad1_ net-_u1-pad12_ u16 +a15 net-_u15-pad5_ net-_u16-pad1_ u17 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u10-pad2_ net-_u1-pad11_ u9 +a18 net-_u15-pad1_ net-_u22-pad2_ u22 +a19 [net-_u23-pad2_ net-_u19-pad2_ ] net-_u25-pad3_ u25 +a20 net-_u23-pad1_ net-_u23-pad2_ u23 +a21 [net-_u25-pad3_ net-_u14-pad1_ ] net-_u31-pad3_ u31 +a22 net-_u31-pad3_ net-_u32-pad2_ u32 +a23 net-_u10-pad2_ net-_u29-pad2_ u29 +a24 net-_u11-pad1_ net-_u26-pad2_ u26 +a25 net-_u33-pad1_ net-_u14-pad1_ u34 +a26 net-_u30-pad1_ net-_u30-pad2_ u30 +a27 net-_u24-pad5_ net-_u27-pad1_ u28 +a28 net-_u27-pad1_ net-_u1-pad13_ u27 +a29 net-_u33-pad5_ net-_u35-pad1_ u36 +a30 net-_u35-pad1_ net-_u1-pad14_ u35 +a31 net-_u33-pad1_ net-_u30-pad2_ unconnected-_u33-pad3_ net-_u15-pad4_ net-_u33-pad5_ net-_u33-pad1_ u33 +a32 net-_u7-pad1_ net-_u4-pad2_ unconnected-_u7-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u7-pad1_ u7 +a33 net-_u2-pad2_ net-_u15-pad4_ u5 +a34 net-_u4-pad1_ net-_u4-pad2_ u4 +a35 net-_u1-pad15_ net-_u2-pad2_ u2 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/cd4518b/cd4518b.kicad_sch b/library/SubcircuitLibrary/cd4518b/cd4518b.kicad_sch new file mode 100644 index 000000000..13b2ca53f --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/cd4518b.kicad_sch @@ -0,0 +1,2691 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 5b188185-9ed9-44e3-aae1-2f4f8a1923e9) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_and" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_and_0_1" + (polyline + (pts + (xy 3.81 -1.27) + (xy -6.35 -1.27) + (xy -6.35 3.81) + (xy 3.81 3.81) + ) + (stroke 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(footprint "") + ) + (path "/f66a3cbc-566c-4a08-9ff5-9fb72f60f420" + (reference "U6") (unit 1) (value "d_nand") (footprint "") + ) + (path "/2b1ed669-1c91-4385-83f4-774bf31dd519" + (reference "U7") (unit 1) (value "d_dff") (footprint "") + ) + (path "/cdafc423-4f31-494d-b8ab-24a7b9347b08" + (reference "U8") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/344ac7b6-3870-4ef0-98b1-353ab471bd8b" + (reference "U9") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/2e19944d-af68-47b6-91fd-6b27258f9be4" + (reference "U10") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/b389b0cd-9014-43b8-879e-967ee6d47ac6" + (reference "U11") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/57205a6a-8bab-492e-b941-2f44ad355986" + (reference "U12") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/371c2814-db9f-4b15-98b5-faefe265b89a" + (reference "U13") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/02a9c88a-ba6a-4074-a891-2ca07d396ce0" + (reference "U14") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d456ff4e-0e57-435a-a32e-2ac1c2177f52" + (reference "U15") (unit 1) (value "d_dff") (footprint "") + ) + (path "/b803926c-e6a5-4329-b874-65610371b8e5" + (reference "U16") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/6f68815d-7733-4f2f-9dec-015bd90a57e3" + (reference "U17") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/cc079d0b-1e45-43c8-8b7b-0873140b5f94" + (reference "U18") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/511681e9-16e2-40fe-bd46-4db00eb98a83" + (reference "U19") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/c353dd29-9fd5-4bb2-b712-66ea9855d4b5" + (reference "U20") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/4ba43961-727b-4e1a-a258-87494f899a9a" + (reference "U21") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/821f3ea2-4912-4ac5-8c9a-a374196ef77d" + (reference "U22") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ced7a233-0eb9-4887-8b3e-1227c2c757d7" + (reference "U23") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/779f860e-8cbe-461e-9786-066102d65dcf" + (reference "U24") (unit 1) (value "d_dff") (footprint "") + ) + (path "/3a75308c-d9e6-451d-a6ed-5a47b6fde1cf" + (reference "U25") (unit 1) (value "d_and") (footprint "") + ) + (path "/743b2153-b468-4da7-8261-095bdff1fa9e" + (reference "U26") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a4fc79ec-169d-4bcc-8507-a361aee8f507" + (reference "U27") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e9066f1c-fc79-4ff2-b6db-61174a0e4b86" + (reference "U28") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d5c17657-bf6b-4811-8955-fb904f911222" + (reference "U29") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/779e12a5-b87a-4a71-8814-a590066fb584" + (reference "U30") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/1306167f-cc7b-4642-b1d9-a2fe054e4b4e" + (reference "U31") (unit 1) (value "d_nor") (footprint "") + ) + (path "/82603a77-efd2-454e-a687-a27c7031eab4" + (reference "U32") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/9b1ccefd-1583-45f9-b93e-8a5af658d08e" + (reference "U33") (unit 1) (value "d_dff") (footprint "") + ) + (path "/fce81434-0253-46ce-94d4-bc64792331f6" + (reference "U34") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/22686650-dcfb-45a5-8b1d-bf4b192b261f" + (reference "U35") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/6f162c5c-dbc7-4cad-aa56-5ca504d368c0" + (reference "U36") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/56412cff-feae-4a26-8ba6-837dd4fced52" + (reference "X1") (unit 1) (value "3_and") (footprint "") + ) + (path "/aea8f3b5-3798-4f23-a928-9518abbe811c" + (reference "X2") (unit 1) (value "3_and") (footprint "") + ) + (path "/56c3a4cf-3b80-4ada-bfc9-d4339b81e2c4" + (reference "X3") (unit 1) (value "3_and") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/cd4518b/cd4518b.sub b/library/SubcircuitLibrary/cd4518b/cd4518b.sub new file mode 100644 index 000000000..68a3d8c03 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/cd4518b.sub @@ -0,0 +1,150 @@ +* Subcircuit cd4518b +.subckt cd4518b net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd +.title kicad schematic +.include 3_and.sub +* u6 net-_u1-pad10_ net-_u3-pad2_ net-_u11-pad1_ d_nand +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u8 net-_u11-pad1_ net-_u4-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u13 net-_u10-pad2_ net-_u13-pad2_ d_inverter +* u18 net-_u11-pad1_ net-_u18-pad2_ d_inverter +x2 net-_u18-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u20-pad1_ 3_and +* u21 net-_u10-pad2_ net-_u21-pad2_ d_inverter +* u19 net-_u15-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u24 net-_u23-pad1_ net-_u20-pad2_ unconnected-_u24-pad3_ net-_u15-pad4_ net-_u24-pad5_ net-_u23-pad1_ d_dff +x1 net-_u11-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u12-pad1_ 3_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ d_dff +* u16 net-_u16-pad1_ net-_u1-pad12_ d_inverter +* u17 net-_u15-pad5_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u9 net-_u10-pad2_ net-_u1-pad11_ d_inverter +* u22 net-_u15-pad1_ net-_u22-pad2_ d_inverter +* u25 net-_u23-pad2_ net-_u19-pad2_ net-_u25-pad3_ d_and +* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter +* u31 net-_u25-pad3_ net-_u14-pad1_ net-_u31-pad3_ d_nor +* u32 net-_u31-pad3_ net-_u32-pad2_ d_inverter +* u29 net-_u10-pad2_ net-_u29-pad2_ d_inverter +x3 net-_u26-pad2_ net-_u29-pad2_ net-_u32-pad2_ net-_u30-pad1_ 3_and +* u26 net-_u11-pad1_ net-_u26-pad2_ d_inverter +* u34 net-_u33-pad1_ net-_u14-pad1_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u28 net-_u24-pad5_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad13_ d_inverter +* u36 net-_u33-pad5_ net-_u35-pad1_ d_inverter +* u35 net-_u35-pad1_ net-_u1-pad14_ d_inverter +* u33 net-_u33-pad1_ net-_u30-pad2_ unconnected-_u33-pad3_ net-_u15-pad4_ net-_u33-pad5_ net-_u33-pad1_ d_dff +* u7 net-_u7-pad1_ net-_u4-pad2_ unconnected-_u7-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u7-pad1_ d_dff +* u5 net-_u2-pad2_ net-_u15-pad4_ d_inverter +* u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +a1 [net-_u1-pad10_ net-_u3-pad2_ ] net-_u11-pad1_ u6 +a2 net-_u1-pad1_ net-_u3-pad2_ u3 +a3 net-_u11-pad1_ net-_u11-pad2_ u11 +a4 net-_u11-pad1_ net-_u4-pad1_ u8 +a5 net-_u14-pad1_ net-_u14-pad2_ u14 +a6 net-_u10-pad2_ net-_u13-pad2_ u13 +a7 net-_u11-pad1_ net-_u18-pad2_ u18 +a8 net-_u10-pad2_ net-_u21-pad2_ u21 +a9 net-_u15-pad1_ net-_u19-pad2_ u19 +a10 net-_u20-pad1_ net-_u20-pad2_ u20 +a11 net-_u23-pad1_ net-_u20-pad2_ unconnected-_u24-pad3_ net-_u15-pad4_ net-_u24-pad5_ net-_u23-pad1_ u24 +a12 net-_u12-pad1_ net-_u12-pad2_ u12 +a13 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ u15 +a14 net-_u16-pad1_ net-_u1-pad12_ u16 +a15 net-_u15-pad5_ net-_u16-pad1_ u17 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u10-pad2_ net-_u1-pad11_ u9 +a18 net-_u15-pad1_ net-_u22-pad2_ u22 +a19 [net-_u23-pad2_ net-_u19-pad2_ ] net-_u25-pad3_ u25 +a20 net-_u23-pad1_ net-_u23-pad2_ u23 +a21 [net-_u25-pad3_ net-_u14-pad1_ ] net-_u31-pad3_ u31 +a22 net-_u31-pad3_ net-_u32-pad2_ u32 +a23 net-_u10-pad2_ net-_u29-pad2_ u29 +a24 net-_u11-pad1_ net-_u26-pad2_ u26 +a25 net-_u33-pad1_ net-_u14-pad1_ u34 +a26 net-_u30-pad1_ net-_u30-pad2_ u30 +a27 net-_u24-pad5_ net-_u27-pad1_ u28 +a28 net-_u27-pad1_ net-_u1-pad13_ u27 +a29 net-_u33-pad5_ net-_u35-pad1_ u36 +a30 net-_u35-pad1_ net-_u1-pad14_ u35 +a31 net-_u33-pad1_ net-_u30-pad2_ unconnected-_u33-pad3_ net-_u15-pad4_ net-_u33-pad5_ net-_u33-pad1_ u33 +a32 net-_u7-pad1_ net-_u4-pad2_ unconnected-_u7-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u7-pad1_ u7 +a33 net-_u2-pad2_ net-_u15-pad4_ u5 +a34 net-_u4-pad1_ net-_u4-pad2_ u4 +a35 net-_u1-pad15_ net-_u2-pad2_ u2 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends cd4518b \ No newline at end of file diff --git a/library/SubcircuitLibrary/cd4518b/cd4518b_Previous_Values.xml b/library/SubcircuitLibrary/cd4518b/cd4518b_Previous_Values.xml new file mode 100644 index 000000000..64635e623 --- /dev/null +++ b/library/SubcircuitLibrary/cd4518b/cd4518b_Previous_Values.xml @@ -0,0 +1 @@ +d_dffd_inverterd_inverterd_inverterd_nandd_inverterd_dffd_inverterd_andd_nord_dffd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_nandd_inverterd_dffd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_andd_inverterd_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_dffd_inverterD:\hdl\eSIM\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\hdl\eSIM\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\hdl\eSIM\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file From 69c554b34dd266dc59f8c8562f62cfc0853aadef Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:29:54 +0530 Subject: [PATCH 02/10] CD4520 is a dual binary up counter IC. --- .../CD4520sub/3_and-cache.lib | 61 + library/SubcircuitLibrary/CD4520sub/3_and.cir | 13 + .../SubcircuitLibrary/CD4520sub/3_and.cir.out | 20 + library/SubcircuitLibrary/CD4520sub/3_and.pro | 43 + library/SubcircuitLibrary/CD4520sub/3_and.sch | 130 + library/SubcircuitLibrary/CD4520sub/3_and.sub | 14 + .../CD4520sub/3_and_Previous_Values.xml | 1 + .../CD4520sub/4_and-cache.lib | 79 + .../CD4520sub/4_and-rescue.lib | 22 + library/SubcircuitLibrary/CD4520sub/4_and.cir | 13 + .../SubcircuitLibrary/CD4520sub/4_and.cir.out | 18 + library/SubcircuitLibrary/CD4520sub/4_and.pro | 57 + library/SubcircuitLibrary/CD4520sub/4_and.sch | 151 + library/SubcircuitLibrary/CD4520sub/4_and.sub | 12 + .../CD4520sub/4_and_Previous_Values.xml | 1 + .../SubcircuitLibrary/CD4520sub/CD4520sub.cir | 36 + .../CD4520sub/CD4520sub.cir.out | 140 + .../CD4520sub/CD4520sub.kicad_sch | 2498 +++++++++++++++++ .../SubcircuitLibrary/CD4520sub/CD4520sub.sub | 134 + .../CD4520sub/CD4520sub_Previous_Values.xml | 1 + .../CD4520sub/_autosave-CD4520sub.sch | 797 ++++++ library/SubcircuitLibrary/CD4520sub/analysis | 1 + 22 files changed, 4242 insertions(+) create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and.cir create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and.cir.out create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and.pro create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and.sch create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and.sub create mode 100644 library/SubcircuitLibrary/CD4520sub/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and-cache.lib create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and-rescue.lib create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and.cir create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and.cir.out create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and.pro create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and.sch create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and.sub create mode 100644 library/SubcircuitLibrary/CD4520sub/4_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4520sub/CD4520sub.cir create mode 100644 library/SubcircuitLibrary/CD4520sub/CD4520sub.cir.out create mode 100644 library/SubcircuitLibrary/CD4520sub/CD4520sub.kicad_sch create mode 100644 library/SubcircuitLibrary/CD4520sub/CD4520sub.sub create mode 100644 library/SubcircuitLibrary/CD4520sub/CD4520sub_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/CD4520sub/_autosave-CD4520sub.sch create mode 100644 library/SubcircuitLibrary/CD4520sub/analysis diff --git a/library/SubcircuitLibrary/CD4520sub/3_and-cache.lib b/library/SubcircuitLibrary/CD4520sub/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4520sub/3_and.cir b/library/SubcircuitLibrary/CD4520sub/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4520sub/3_and.cir.out b/library/SubcircuitLibrary/CD4520sub/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4520sub/3_and.pro b/library/SubcircuitLibrary/CD4520sub/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4520sub/3_and.sch b/library/SubcircuitLibrary/CD4520sub/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4520sub/3_and.sub b/library/SubcircuitLibrary/CD4520sub/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4520sub/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/4_and-cache.lib b/library/SubcircuitLibrary/CD4520sub/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4520sub/4_and-rescue.lib b/library/SubcircuitLibrary/CD4520sub/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4520sub/4_and.cir b/library/SubcircuitLibrary/CD4520sub/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4520sub/4_and.cir.out b/library/SubcircuitLibrary/CD4520sub/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4520sub/4_and.pro b/library/SubcircuitLibrary/CD4520sub/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4520sub/4_and.sch b/library/SubcircuitLibrary/CD4520sub/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4520sub/4_and.sub b/library/SubcircuitLibrary/CD4520sub/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4520sub/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir b/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir new file mode 100644 index 000000000..ae30bccf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir @@ -0,0 +1,36 @@ +.title KiCad schematic +U1 Net-_U1-Pad1_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND Net-_U1-Pad1_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND PORT +U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter +U4 Net-_U2-Pad2_ Net-_U15-Pad4_ d_inverter +U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter +U7 Net-_U14-Pad1_ Net-_U5-Pad1_ d_inverter +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ d_inverter +U8 Net-_U8-Pad1_ Net-_U5-Pad2_ unconnected-_U8-Pad3_ Net-_U15-Pad4_ Net-_U10-Pad1_ Net-_U8-Pad1_ d_dff +U6 Net-_U1-Pad10_ Net-_U3-Pad2_ Net-_U14-Pad1_ d_nand +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U12-Pad2_ unconnected-_U15-Pad3_ Net-_U15-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad1_ d_dff +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U1-Pad12_ d_inverter +U9 Net-_U10-Pad2_ Net-_U1-Pad11_ d_inverter +U18 Net-_U15-Pad5_ Net-_U17-Pad1_ d_inverter +U22 Net-_U22-Pad1_ Net-_U19-Pad2_ unconnected-_U22-Pad3_ Net-_U15-Pad4_ Net-_U22-Pad5_ Net-_U22-Pad1_ d_dff +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U28 Net-_U22-Pad5_ Net-_U27-Pad1_ d_inverter +U27 Net-_U27-Pad1_ Net-_U1-Pad13_ d_inverter +U30 Net-_U30-Pad1_ Net-_U29-Pad2_ unconnected-_U30-Pad3_ Net-_U15-Pad4_ Net-_U30-Pad5_ Net-_U30-Pad1_ d_dff +U31 Net-_U31-Pad1_ Net-_U1-Pad14_ d_inverter +U32 Net-_U30-Pad5_ Net-_U31-Pad1_ d_inverter +U20 Net-_U10-Pad2_ Net-_U20-Pad2_ d_inverter +U21 Net-_U14-Pad1_ Net-_U21-Pad2_ d_inverter +X2 Net-_U26-Pad2_ Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U29-Pad1_ 4_and +U26 Net-_U22-Pad1_ Net-_U26-Pad2_ d_inverter +U25 Net-_U15-Pad1_ Net-_U25-Pad2_ d_inverter +U24 Net-_U14-Pad1_ Net-_U24-Pad2_ d_inverter +U23 Net-_U10-Pad2_ Net-_U23-Pad2_ d_inverter +U16 Net-_U15-Pad1_ Net-_U16-Pad2_ d_inverter +X1 Net-_U16-Pad2_ Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U19-Pad1_ 3_and +U14 Net-_U14-Pad1_ Net-_U13-Pad2_ d_inverter +U11 Net-_U10-Pad2_ Net-_U11-Pad2_ d_inverter +U13 Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_U12-Pad1_ d_and +.end diff --git a/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir.out b/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir.out new file mode 100644 index 000000000..c5054d103 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/CD4520sub.cir.out @@ -0,0 +1,140 @@ +.title kicad schematic + +.include 4_and.sub +.include 3_and.sub +* u1 net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd port +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u15-pad4_ d_inverter +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u14-pad1_ net-_u5-pad1_ d_inverter +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_u5-pad2_ unconnected-_u8-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u8-pad1_ d_dff +* u6 net-_u1-pad10_ net-_u3-pad2_ net-_u14-pad1_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ d_dff +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u1-pad12_ d_inverter +* u9 net-_u10-pad2_ net-_u1-pad11_ d_inverter +* u18 net-_u15-pad5_ net-_u17-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_u19-pad2_ unconnected-_u22-pad3_ net-_u15-pad4_ net-_u22-pad5_ net-_u22-pad1_ d_dff +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u28 net-_u22-pad5_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad13_ d_inverter +* u30 net-_u30-pad1_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u15-pad4_ net-_u30-pad5_ net-_u30-pad1_ d_dff +* u31 net-_u31-pad1_ net-_u1-pad14_ d_inverter +* u32 net-_u30-pad5_ net-_u31-pad1_ d_inverter +* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u14-pad1_ net-_u21-pad2_ d_inverter +x2 net-_u26-pad2_ net-_u25-pad2_ net-_u23-pad2_ net-_u24-pad2_ net-_u29-pad1_ 4_and +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u25 net-_u15-pad1_ net-_u25-pad2_ d_inverter +* u24 net-_u14-pad1_ net-_u24-pad2_ d_inverter +* u23 net-_u10-pad2_ net-_u23-pad2_ d_inverter +* u16 net-_u15-pad1_ net-_u16-pad2_ d_inverter +x1 net-_u16-pad2_ net-_u20-pad2_ net-_u21-pad2_ net-_u19-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u13-pad2_ d_inverter +* u11 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ net-_u12-pad1_ d_and +a1 net-_u1-pad15_ net-_u2-pad2_ u2 +a2 net-_u2-pad2_ net-_u15-pad4_ u4 +a3 net-_u1-pad1_ net-_u3-pad2_ u3 +a4 net-_u14-pad1_ net-_u5-pad1_ u7 +a5 net-_u5-pad1_ net-_u5-pad2_ u5 +a6 net-_u8-pad1_ net-_u5-pad2_ unconnected-_u8-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u8-pad1_ u8 +a7 [net-_u1-pad10_ net-_u3-pad2_ ] net-_u14-pad1_ u6 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ u15 +a10 net-_u12-pad1_ net-_u12-pad2_ u12 +a11 net-_u19-pad1_ net-_u19-pad2_ u19 +a12 net-_u17-pad1_ net-_u1-pad12_ u17 +a13 net-_u10-pad2_ net-_u1-pad11_ u9 +a14 net-_u15-pad5_ net-_u17-pad1_ u18 +a15 net-_u22-pad1_ net-_u19-pad2_ unconnected-_u22-pad3_ net-_u15-pad4_ net-_u22-pad5_ net-_u22-pad1_ u22 +a16 net-_u29-pad1_ net-_u29-pad2_ u29 +a17 net-_u22-pad5_ net-_u27-pad1_ u28 +a18 net-_u27-pad1_ net-_u1-pad13_ u27 +a19 net-_u30-pad1_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u15-pad4_ net-_u30-pad5_ net-_u30-pad1_ u30 +a20 net-_u31-pad1_ net-_u1-pad14_ u31 +a21 net-_u30-pad5_ net-_u31-pad1_ u32 +a22 net-_u10-pad2_ net-_u20-pad2_ u20 +a23 net-_u14-pad1_ net-_u21-pad2_ u21 +a24 net-_u22-pad1_ net-_u26-pad2_ u26 +a25 net-_u15-pad1_ net-_u25-pad2_ u25 +a26 net-_u14-pad1_ net-_u24-pad2_ u24 +a27 net-_u10-pad2_ net-_u23-pad2_ u23 +a28 net-_u15-pad1_ net-_u16-pad2_ u16 +a29 net-_u14-pad1_ net-_u13-pad2_ u14 +a30 net-_u10-pad2_ net-_u11-pad2_ u11 +a31 [net-_u11-pad2_ net-_u13-pad2_ ] net-_u12-pad1_ u13 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4520sub/CD4520sub.kicad_sch b/library/SubcircuitLibrary/CD4520sub/CD4520sub.kicad_sch new file mode 100644 index 000000000..2890ca371 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/CD4520sub.kicad_sch @@ -0,0 +1,2498 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 0c5dfac4-7b81-4b9e-973e-d5d5da3a8977) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_and" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 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a/library/SubcircuitLibrary/CD4520sub/CD4520sub.sub b/library/SubcircuitLibrary/CD4520sub/CD4520sub.sub new file mode 100644 index 000000000..ce7ce2dec --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/CD4520sub.sub @@ -0,0 +1,134 @@ +* Subcircuit CD4520sub +.subckt CD4520sub net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd net-_u1-pad1_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd +.title kicad schematic +.include 4_and.sub +.include 3_and.sub +* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u15-pad4_ d_inverter +* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u14-pad1_ net-_u5-pad1_ d_inverter +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_u5-pad2_ unconnected-_u8-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u8-pad1_ d_dff +* u6 net-_u1-pad10_ net-_u3-pad2_ net-_u14-pad1_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ d_dff +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u1-pad12_ d_inverter +* u9 net-_u10-pad2_ net-_u1-pad11_ d_inverter +* u18 net-_u15-pad5_ net-_u17-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_u19-pad2_ unconnected-_u22-pad3_ net-_u15-pad4_ net-_u22-pad5_ net-_u22-pad1_ d_dff +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u28 net-_u22-pad5_ net-_u27-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad13_ d_inverter +* u30 net-_u30-pad1_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u15-pad4_ net-_u30-pad5_ net-_u30-pad1_ d_dff +* u31 net-_u31-pad1_ net-_u1-pad14_ d_inverter +* u32 net-_u30-pad5_ net-_u31-pad1_ d_inverter +* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter +* u21 net-_u14-pad1_ net-_u21-pad2_ d_inverter +x2 net-_u26-pad2_ net-_u25-pad2_ net-_u23-pad2_ net-_u24-pad2_ net-_u29-pad1_ 4_and +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u25 net-_u15-pad1_ net-_u25-pad2_ d_inverter +* u24 net-_u14-pad1_ net-_u24-pad2_ d_inverter +* u23 net-_u10-pad2_ net-_u23-pad2_ d_inverter +* u16 net-_u15-pad1_ net-_u16-pad2_ d_inverter +x1 net-_u16-pad2_ net-_u20-pad2_ net-_u21-pad2_ net-_u19-pad1_ 3_and +* u14 net-_u14-pad1_ net-_u13-pad2_ d_inverter +* u11 net-_u10-pad2_ net-_u11-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ net-_u12-pad1_ d_and +a1 net-_u1-pad15_ net-_u2-pad2_ u2 +a2 net-_u2-pad2_ net-_u15-pad4_ u4 +a3 net-_u1-pad1_ net-_u3-pad2_ u3 +a4 net-_u14-pad1_ net-_u5-pad1_ u7 +a5 net-_u5-pad1_ net-_u5-pad2_ u5 +a6 net-_u8-pad1_ net-_u5-pad2_ unconnected-_u8-pad3_ net-_u15-pad4_ net-_u10-pad1_ net-_u8-pad1_ u8 +a7 [net-_u1-pad10_ net-_u3-pad2_ ] net-_u14-pad1_ u6 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 net-_u15-pad1_ net-_u12-pad2_ unconnected-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ net-_u15-pad1_ u15 +a10 net-_u12-pad1_ net-_u12-pad2_ u12 +a11 net-_u19-pad1_ net-_u19-pad2_ u19 +a12 net-_u17-pad1_ net-_u1-pad12_ u17 +a13 net-_u10-pad2_ net-_u1-pad11_ u9 +a14 net-_u15-pad5_ net-_u17-pad1_ u18 +a15 net-_u22-pad1_ net-_u19-pad2_ unconnected-_u22-pad3_ net-_u15-pad4_ net-_u22-pad5_ net-_u22-pad1_ u22 +a16 net-_u29-pad1_ net-_u29-pad2_ u29 +a17 net-_u22-pad5_ net-_u27-pad1_ u28 +a18 net-_u27-pad1_ net-_u1-pad13_ u27 +a19 net-_u30-pad1_ net-_u29-pad2_ unconnected-_u30-pad3_ net-_u15-pad4_ net-_u30-pad5_ net-_u30-pad1_ u30 +a20 net-_u31-pad1_ net-_u1-pad14_ u31 +a21 net-_u30-pad5_ net-_u31-pad1_ u32 +a22 net-_u10-pad2_ net-_u20-pad2_ u20 +a23 net-_u14-pad1_ net-_u21-pad2_ u21 +a24 net-_u22-pad1_ net-_u26-pad2_ u26 +a25 net-_u15-pad1_ net-_u25-pad2_ u25 +a26 net-_u14-pad1_ net-_u24-pad2_ u24 +a27 net-_u10-pad2_ net-_u23-pad2_ u23 +a28 net-_u15-pad1_ net-_u16-pad2_ u16 +a29 net-_u14-pad1_ net-_u13-pad2_ u14 +a30 net-_u10-pad2_ net-_u11-pad2_ u11 +a31 [net-_u11-pad2_ net-_u13-pad2_ ] net-_u12-pad1_ u13 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u15 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4520sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/CD4520sub_Previous_Values.xml b/library/SubcircuitLibrary/CD4520sub/CD4520sub_Previous_Values.xml new file mode 100644 index 000000000..301949fdb --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/CD4520sub_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_nandd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_andD:\hdl\eSIM\FOSSEE\eSim\library\SubcircuitLibrary\4_andD:\hdl\eSIM\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4520sub/_autosave-CD4520sub.sch b/library/SubcircuitLibrary/CD4520sub/_autosave-CD4520sub.sch new file mode 100644 index 000000000..b7e8d122f --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/_autosave-CD4520sub.sch @@ -0,0 +1,797 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr 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CNN +F 3 "" H 2350 6250 60 0000 C CNN + 1 2300 6300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U4 +U 1 1 00000000 +P 2600 4800 +F 0 "U4" H 2600 5050 60 0000 C CNN +F 1 "d_inverter" H 2600 4900 60 0000 C CNN +F 2 "" H 2650 4750 60 0000 C CNN +F 3 "" H 2650 4750 60 0000 C CNN + 1 2600 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U5 +U 1 1 00000000 +P 3350 5150 +F 0 "U5" V 3400 5050 60 0000 R CNN +F 1 "d_inverter" V 3250 5050 60 0000 R CNN +F 2 "" H 3400 5100 60 0000 C CNN +F 3 "" H 3400 5100 60 0000 C CNN + 1 3350 5150 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U7 +U 1 1 00000000 +P 3750 5450 +F 0 "U7" H 3750 5200 60 0000 C CNN +F 1 "d_inverter" H 3750 5350 60 0000 C CNN +F 2 "" H 3800 5400 60 0000 C CNN +F 3 "" H 3800 5400 60 0000 C CNN + 1 3750 5450 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U9 +U 1 1 00000000 +P 4650 1650 +F 0 "U9" H 4650 1900 60 0000 C CNN +F 1 "d_inverter" H 4650 1750 60 0000 C CNN +F 2 "" H 4700 1600 60 0000 C CNN +F 3 "" H 4700 1600 60 0000 C CNN + 1 4650 1650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U10 +U 1 1 00000000 +P 4650 2500 +F 0 "U10" H 4650 2750 60 0000 C CNN +F 1 "d_inverter" H 4650 2600 60 0000 C CNN +F 2 "" H 4700 2450 60 0000 C CNN +F 3 "" H 4700 2450 60 0000 C CNN + 1 4650 2500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U11 +U 1 1 00000000 +P 5200 5949 +F 0 "U11" V 5250 5849 60 0000 R CNN +F 1 "d_inverter" V 5100 5849 60 0000 R CNN +F 2 "" H 5250 5899 60 0000 C CNN +F 3 "" H 5250 5899 60 0000 C CNN + 1 5200 5949 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U12 +U 1 1 00000000 +P 5250 4350 +F 0 "U12" V 5300 4250 60 0000 R CNN +F 1 "d_inverter" V 5150 4250 60 0000 R CNN +F 2 "" H 5300 4300 60 0000 C CNN +F 3 "" H 5300 4300 60 0000 C CNN + 1 5250 4350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U14 +U 1 1 00000000 +P 5300 5950 +F 0 "U14" V 5350 5850 60 0000 R CNN +F 1 "d_inverter" V 5200 5850 60 0000 R CNN +F 2 "" H 5350 5900 60 0000 C CNN +F 3 "" H 5350 5900 60 0000 C CNN + 1 5300 5950 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U16 +U 1 1 00000000 +P 6800 5900 +F 0 "U16" V 6850 5800 60 0000 R CNN +F 1 "d_inverter" V 6700 5800 60 0000 R CNN +F 2 "" H 6850 5850 60 0000 C CNN +F 3 "" H 6850 5850 60 0000 C CNN + 1 6800 5900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U17 +U 1 1 00000000 +P 6900 1700 +F 0 "U17" H 6900 1950 60 0000 C CNN +F 1 "d_inverter" H 6900 1800 60 0000 C CNN +F 2 "" H 6950 1650 60 0000 C CNN +F 3 "" H 6950 1650 60 0000 C CNN + 1 6900 1700 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U18 +U 1 1 00000000 +P 6900 2550 +F 0 "U18" H 6900 2800 60 0000 C CNN +F 1 "d_inverter" H 6900 2650 60 0000 C CNN +F 2 "" H 6950 2500 60 0000 C CNN +F 3 "" H 6950 2500 60 0000 C CNN + 1 6900 2550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U19 +U 1 1 00000000 +P 6900 4400 +F 0 "U19" V 6950 4300 60 0000 R CNN +F 1 "d_inverter" V 6800 4300 60 0000 R CNN +F 2 "" H 6950 4350 60 0000 C CNN +F 3 "" H 6950 4350 60 0000 C CNN + 1 6900 4400 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U20 +U 1 1 00000000 +P 6900 5900 +F 0 "U20" V 6950 5800 60 0000 R CNN +F 1 "d_inverter" V 6800 5800 60 0000 R CNN +F 2 "" H 6950 5850 60 0000 C CNN +F 3 "" H 6950 5850 60 0000 C CNN + 1 6900 5900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U21 +U 1 1 00000000 +P 7000 5909 +F 0 "U21" V 7050 5809 60 0000 R CNN +F 1 "d_inverter" V 6900 5809 60 0000 R CNN +F 2 "" H 7050 5859 60 0000 C CNN +F 3 "" H 7050 5859 60 0000 C CNN + 1 7000 5909 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U23 +U 1 1 00000000 +P 7950 6400 +F 0 "U23" H 7950 6650 60 0000 C CNN +F 1 "d_inverter" H 7950 6500 60 0000 C CNN +F 2 "" H 8000 6350 60 0000 C CNN +F 3 "" H 8000 6350 60 0000 C CNN + 1 7950 6400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U24 +U 1 1 00000000 +P 7950 6650 +F 0 "U24" H 7950 6900 60 0000 C CNN +F 1 "d_inverter" H 7950 6750 60 0000 C CNN +F 2 "" H 8000 6600 60 0000 C CNN +F 3 "" H 8000 6600 60 0000 C CNN + 1 7950 6650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U25 +U 1 1 00000000 +P 8000 6250 +F 0 "U25" H 8000 6500 60 0000 C CNN +F 1 "d_inverter" H 8000 6350 60 0000 C CNN +F 2 "" H 8050 6200 60 0000 C CNN +F 3 "" H 8050 6200 60 0000 C CNN + 1 8000 6250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U26 +U 1 1 00000000 +P 8300 5600 +F 0 "U26" V 8250 5700 60 0000 L CNN +F 1 "d_inverter" V 8400 5700 60 0000 L CNN +F 2 "" H 8350 5550 60 0000 C CNN +F 3 "" H 8350 5550 60 0000 C CNN + 1 8300 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U27 +U 1 1 00000000 +P 8700 1750 +F 0 "U27" H 8700 2000 60 0000 C CNN +F 1 "d_inverter" H 8700 1850 60 0000 C CNN +F 2 "" H 8750 1700 60 0000 C CNN +F 3 "" H 8750 1700 60 0000 C CNN + 1 8700 1750 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U28 +U 1 1 00000000 +P 8700 2600 +F 0 "U28" H 8700 2850 60 0000 C CNN +F 1 "d_inverter" H 8700 2700 60 0000 C CNN +F 2 "" H 8750 2550 60 0000 C CNN +F 3 "" H 8750 2550 60 0000 C CNN + 1 8700 2600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U29 +U 1 1 00000000 +P 8700 4550 +F 0 "U29" V 8750 4450 60 0000 R CNN +F 1 "d_inverter" V 8600 4450 60 0000 R CNN +F 2 "" H 8750 4500 60 0000 C CNN +F 3 "" H 8750 4500 60 0000 C CNN + 1 8700 4550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U31 +U 1 1 00000000 +P 10500 1750 +F 0 "U31" H 10500 2000 60 0000 C CNN +F 1 "d_inverter" H 10500 1850 60 0000 C CNN +F 2 "" H 10550 1700 60 0000 C CNN +F 3 "" H 10550 1700 60 0000 C CNN + 1 10500 1750 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U32 +U 1 1 00000000 +P 10500 2600 +F 0 "U32" H 10500 2850 60 0000 C CNN +F 1 "d_inverter" H 10500 2700 60 0000 C CNN +F 2 "" H 10550 2550 60 0000 C CNN +F 3 "" H 10550 2550 60 0000 C CNN + 1 10500 2600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_nand U6 +U 1 1 00000000 +P 3500 6050 +F 0 "U6" H 3500 6400 60 0000 C CNN +F 1 "d_nand" H 3500 6250 60 0000 C CNN +F 2 "" H 3500 6050 60 0000 C CNN +F 3 "" H 3500 6050 60 0000 C CNN + 1 3500 6050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U13 +U 1 1 00000000 +P 5300 5150 +F 0 "U13" V 5350 5050 60 0000 R CNN +F 1 "d_and" V 5200 5050 60 0000 R CNN +F 2 "" H 5300 5150 60 0000 C CNN +F 3 "" H 5300 5150 60 0000 C CNN + 1 5300 5150 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Subckt:3_and X1 +U 1 1 00000000 +P 6950 5250 +F 0 "X1" V 7079 5100 60 0000 R CNN +F 1 "3_and" V 6929 5100 60 0000 R CNN +F 2 "" H 6950 5250 60 0000 C CNN +F 3 "" H 6950 5250 60 0000 C CNN + 1 6950 5250 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Subckt:4_and X2 +U 1 1 00000000 +P 8700 5650 +F 0 "X2" V 8803 5400 60 0000 R CNN +F 1 "4_and" V 8653 5400 60 0000 R CNN +F 2 "" H 8700 5650 60 0000 C CNN +F 3 "" H 8700 5650 60 0000 C CNN + 1 8700 5650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_dff U8 +U 1 1 00000000 +P 3900 3700 +F 0 "U8" H 3980 4350 60 0000 L CNN +F 1 "d_dff" H 3980 4200 60 0000 L CNN +F 2 "" H 3900 3700 60 0000 C CNN +F 3 "" H 3900 3700 60 0000 C CNN + 1 3900 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U15 +U 1 1 00000000 +P 5850 3700 +F 0 "U15" H 5930 4350 60 0000 L CNN +F 1 "d_dff" H 5930 4200 60 0000 L CNN +F 2 "" H 5850 3700 60 0000 C CNN +F 3 "" H 5850 3700 60 0000 C CNN + 1 5850 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U22 +U 1 1 00000000 +P 7650 3750 +F 0 "U22" H 7730 4400 60 0000 L CNN +F 1 "d_dff" H 7730 4250 60 0000 L CNN +F 2 "" H 7650 3750 60 0000 C CNN +F 3 "" H 7650 3750 60 0000 C CNN + 1 7650 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U30 +U 1 1 00000000 +P 9450 3750 +F 0 "U30" H 9530 4400 60 0000 L CNN +F 1 "d_dff" H 9530 4250 60 0000 L CNN +F 2 "" H 9450 3750 60 0000 C CNN +F 3 "" H 9450 3750 60 0000 C CNN + 1 9450 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4520sub/analysis b/library/SubcircuitLibrary/CD4520sub/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4520sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 53db90e1c39ca9756608998cb253f8e04653a89c Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:30:43 +0530 Subject: [PATCH 03/10] SN74160 is a synchronous 4-bit decade counter with load and clear. --- .../SubcircuitLibrary/SN74160/3_and-cache.lib | 61 + library/SubcircuitLibrary/SN74160/3_and.cir | 13 + .../SubcircuitLibrary/SN74160/3_and.cir.out | 20 + library/SubcircuitLibrary/SN74160/3_and.pro | 43 + library/SubcircuitLibrary/SN74160/3_and.sch | 130 + library/SubcircuitLibrary/SN74160/3_and.sub | 14 + .../SN74160/3_and_Previous_Values.xml | 1 + .../SubcircuitLibrary/SN74160/4_and-cache.lib | 79 + .../SN74160/4_and-rescue.lib | 22 + library/SubcircuitLibrary/SN74160/4_and.cir | 13 + .../SubcircuitLibrary/SN74160/4_and.cir.out | 18 + library/SubcircuitLibrary/SN74160/4_and.pro | 57 + library/SubcircuitLibrary/SN74160/4_and.sch | 151 + library/SubcircuitLibrary/SN74160/4_and.sub | 12 + .../SN74160/4_and_Previous_Values.xml | 1 + library/SubcircuitLibrary/SN74160/SN74160.cir | 47 + .../SubcircuitLibrary/SN74160/SN74160.cir.out | 175 + .../SN74160/SN74160.kicad_sch | 3299 +++++++++++++++++ library/SubcircuitLibrary/SN74160/SN74160.sub | 169 + .../SN74160/SN74160_Previous_Values.xml | 1 + .../SN74160/_autosave-SN74160.sch | 1124 ++++++ library/SubcircuitLibrary/SN74160/analysis | 1 + 22 files changed, 5451 insertions(+) create mode 100644 library/SubcircuitLibrary/SN74160/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/SN74160/3_and.cir create mode 100644 library/SubcircuitLibrary/SN74160/3_and.cir.out create mode 100644 library/SubcircuitLibrary/SN74160/3_and.pro create mode 100644 library/SubcircuitLibrary/SN74160/3_and.sch create mode 100644 library/SubcircuitLibrary/SN74160/3_and.sub create mode 100644 library/SubcircuitLibrary/SN74160/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN74160/4_and-cache.lib create mode 100644 library/SubcircuitLibrary/SN74160/4_and-rescue.lib create mode 100644 library/SubcircuitLibrary/SN74160/4_and.cir create mode 100644 library/SubcircuitLibrary/SN74160/4_and.cir.out create mode 100644 library/SubcircuitLibrary/SN74160/4_and.pro create mode 100644 library/SubcircuitLibrary/SN74160/4_and.sch create mode 100644 library/SubcircuitLibrary/SN74160/4_and.sub create mode 100644 library/SubcircuitLibrary/SN74160/4_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN74160/SN74160.cir create mode 100644 library/SubcircuitLibrary/SN74160/SN74160.cir.out create mode 100644 library/SubcircuitLibrary/SN74160/SN74160.kicad_sch create mode 100644 library/SubcircuitLibrary/SN74160/SN74160.sub create mode 100644 library/SubcircuitLibrary/SN74160/SN74160_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/SN74160/_autosave-SN74160.sch create mode 100644 library/SubcircuitLibrary/SN74160/analysis diff --git a/library/SubcircuitLibrary/SN74160/3_and-cache.lib b/library/SubcircuitLibrary/SN74160/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74160/3_and.cir b/library/SubcircuitLibrary/SN74160/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74160/3_and.cir.out b/library/SubcircuitLibrary/SN74160/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74160/3_and.pro b/library/SubcircuitLibrary/SN74160/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74160/3_and.sch b/library/SubcircuitLibrary/SN74160/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74160/3_and.sub b/library/SubcircuitLibrary/SN74160/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74160/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74160/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74160/4_and-cache.lib b/library/SubcircuitLibrary/SN74160/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74160/4_and-rescue.lib b/library/SubcircuitLibrary/SN74160/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74160/4_and.cir b/library/SubcircuitLibrary/SN74160/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74160/4_and.cir.out b/library/SubcircuitLibrary/SN74160/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74160/4_and.pro b/library/SubcircuitLibrary/SN74160/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74160/4_and.sch b/library/SubcircuitLibrary/SN74160/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74160/4_and.sub b/library/SubcircuitLibrary/SN74160/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74160/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74160/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74160/SN74160.cir b/library/SubcircuitLibrary/SN74160/SN74160.cir new file mode 100644 index 000000000..bf1dede86 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/SN74160.cir @@ -0,0 +1,47 @@ +.title KiCad schematic +U29 Net-_U16-Pad2_ Net-_U29-Pad2_ d_inverter +U37 Net-_U25-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad2_ unconnected-_U37-Pad4_ Net-_U33-Pad2_ unconnected-_U37-Pad6_ Net-_U1-Pad14_ d_jkff +U33 Net-_U33-Pad1_ Net-_U33-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ GND /load Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ GND PORT +U34 Net-_U33-Pad1_ Net-_U34-Pad2_ d_inverter +U40 Net-_U26-Pad3_ Net-_U22-Pad3_ Net-_U30-Pad2_ unconnected-_U40-Pad4_ Net-_U34-Pad2_ unconnected-_U40-Pad6_ Net-_U1-Pad13_ d_jkff +U39 Net-_U28-Pad3_ Net-_U24-Pad3_ Net-_U32-Pad2_ unconnected-_U39-Pad4_ Net-_U36-Pad2_ Net-_U1-Pad11_ Net-_U39-Pad7_ d_jkff +U36 Net-_U33-Pad1_ Net-_U36-Pad2_ d_inverter +U32 Net-_U16-Pad2_ Net-_U32-Pad2_ d_inverter +U35 Net-_U33-Pad1_ Net-_U35-Pad2_ d_inverter +U31 Net-_U16-Pad2_ Net-_U31-Pad2_ d_inverter +U27 Net-_U14-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_and +U22 Net-_U18-Pad3_ Net-_U13-Pad2_ Net-_U22-Pad3_ d_and +U30 Net-_U16-Pad2_ Net-_U30-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_or +U16 Net-_U1-Pad2_ Net-_U16-Pad2_ d_inverter +U38 Net-_U27-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad2_ unconnected-_U38-Pad4_ Net-_U35-Pad2_ unconnected-_U38-Pad6_ Net-_U1-Pad12_ d_jkff +U9 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U13-Pad2_ d_nand +X4 Net-_U1-Pad14_ Net-_U17-Pad1_ Net-_U39-Pad7_ Net-_U18-Pad1_ 3_and +U28 Net-_U15-Pad3_ Net-_U20-Pad3_ Net-_U28-Pad3_ d_and +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U20-Pad1_ d_or +X2 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U17-Pad1_ Net-_U7-Pad1_ 4_and +U20 Net-_U20-Pad1_ Net-_U10-Pad2_ Net-_U20-Pad3_ d_or +U24 Net-_U20-Pad3_ Net-_U11-Pad3_ Net-_U24-Pad3_ d_and +U15 Net-_U10-Pad2_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U23 Net-_U19-Pad3_ Net-_U10-Pad3_ Net-_U23-Pad3_ d_and +U10 Net-_U1-Pad5_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U11 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nand +X1 Net-_U1-Pad14_ Net-_U17-Pad1_ Net-_U1-Pad11_ Net-_U7-Pad2_ 3_and +U14 Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_nand +X3 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U17-Pad1_ Net-_U19-Pad1_ 3_and +U25 Net-_U12-Pad3_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and +U21 Net-_U17-Pad3_ Net-_U12-Pad2_ Net-_U21-Pad3_ d_and +U26 Net-_U13-Pad3_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_and +U17 Net-_U17-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_or +U12 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand +U18 Net-_U18-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_or +U13 Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand +U8 Net-_U1-Pad3_ Net-_U10-Pad2_ Net-_U12-Pad2_ d_nand +X5 Net-_U1-Pad11_ Net-_U1-Pad14_ Net-_U1-Pad10_ Net-_U1-Pad15_ 3_and +U3 Net-_U1-Pad7_ Net-_U1-Pad10_ Net-_U17-Pad1_ d_and +U5 Net-_U2-Pad2_ Net-_U33-Pad1_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U6 Net-_U4-Pad2_ Net-_U10-Pad2_ d_buffer +U4 /load Net-_U4-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/SN74160/SN74160.cir.out b/library/SubcircuitLibrary/SN74160/SN74160.cir.out new file mode 100644 index 000000000..1583f696c --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/SN74160.cir.out @@ -0,0 +1,175 @@ +.title kicad schematic + +.include 4_and.sub +.include 3_and.sub +* u29 net-_u16-pad2_ net-_u29-pad2_ d_inverter +* u37 net-_u25-pad3_ net-_u21-pad3_ net-_u29-pad2_ unconnected-_u37-pad4_ net-_u33-pad2_ unconnected-_u37-pad6_ net-_u1-pad14_ d_jkff +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd /load net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd port +* u34 net-_u33-pad1_ net-_u34-pad2_ d_inverter +* u40 net-_u26-pad3_ net-_u22-pad3_ net-_u30-pad2_ unconnected-_u40-pad4_ net-_u34-pad2_ unconnected-_u40-pad6_ net-_u1-pad13_ d_jkff +* u39 net-_u28-pad3_ net-_u24-pad3_ net-_u32-pad2_ unconnected-_u39-pad4_ net-_u36-pad2_ net-_u1-pad11_ net-_u39-pad7_ d_jkff +* u36 net-_u33-pad1_ net-_u36-pad2_ d_inverter +* u32 net-_u16-pad2_ net-_u32-pad2_ d_inverter +* u35 net-_u33-pad1_ net-_u35-pad2_ d_inverter +* u31 net-_u16-pad2_ net-_u31-pad2_ d_inverter +* u27 net-_u14-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and +* u22 net-_u18-pad3_ net-_u13-pad2_ net-_u22-pad3_ d_and +* u30 net-_u16-pad2_ net-_u30-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_or +* u16 net-_u1-pad2_ net-_u16-pad2_ d_inverter +* u38 net-_u27-pad3_ net-_u23-pad3_ net-_u31-pad2_ unconnected-_u38-pad4_ net-_u35-pad2_ unconnected-_u38-pad6_ net-_u1-pad12_ d_jkff +* u9 net-_u1-pad4_ net-_u10-pad2_ net-_u13-pad2_ d_nand +x4 net-_u1-pad14_ net-_u17-pad1_ net-_u39-pad7_ net-_u18-pad1_ 3_and +* u28 net-_u15-pad3_ net-_u20-pad3_ net-_u28-pad3_ d_and +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u20-pad1_ d_or +x2 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u17-pad1_ net-_u7-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u11-pad3_ net-_u24-pad3_ d_and +* u15 net-_u10-pad2_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u23 net-_u19-pad3_ net-_u10-pad3_ net-_u23-pad3_ d_and +* u10 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u11 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ d_nand +x1 net-_u1-pad14_ net-_u17-pad1_ net-_u1-pad11_ net-_u7-pad2_ 3_and +* u14 net-_u10-pad2_ net-_u10-pad3_ net-_u14-pad3_ d_nand +x3 net-_u1-pad13_ net-_u1-pad14_ net-_u17-pad1_ net-_u19-pad1_ 3_and +* u25 net-_u12-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u21 net-_u17-pad3_ net-_u12-pad2_ net-_u21-pad3_ d_and +* u26 net-_u13-pad3_ net-_u18-pad3_ net-_u26-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_or +* u12 net-_u10-pad2_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_or +* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u8 net-_u1-pad3_ net-_u10-pad2_ net-_u12-pad2_ d_nand +x5 net-_u1-pad11_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad15_ 3_and +* u3 net-_u1-pad7_ net-_u1-pad10_ net-_u17-pad1_ d_and +* u5 net-_u2-pad2_ net-_u33-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u10-pad2_ d_buffer +* u4 /load net-_u4-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u29-pad2_ u29 +a2 net-_u25-pad3_ net-_u21-pad3_ net-_u29-pad2_ unconnected-_u37-pad4_ net-_u33-pad2_ unconnected-_u37-pad6_ net-_u1-pad14_ u37 +a3 net-_u33-pad1_ net-_u33-pad2_ u33 +a4 net-_u33-pad1_ net-_u34-pad2_ u34 +a5 net-_u26-pad3_ net-_u22-pad3_ net-_u30-pad2_ unconnected-_u40-pad4_ net-_u34-pad2_ unconnected-_u40-pad6_ net-_u1-pad13_ u40 +a6 net-_u28-pad3_ net-_u24-pad3_ net-_u32-pad2_ unconnected-_u39-pad4_ net-_u36-pad2_ net-_u1-pad11_ net-_u39-pad7_ u39 +a7 net-_u33-pad1_ net-_u36-pad2_ u36 +a8 net-_u16-pad2_ net-_u32-pad2_ u32 +a9 net-_u33-pad1_ net-_u35-pad2_ u35 +a10 net-_u16-pad2_ net-_u31-pad2_ u31 +a11 [net-_u14-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a12 [net-_u18-pad3_ net-_u13-pad2_ ] net-_u22-pad3_ u22 +a13 net-_u16-pad2_ net-_u30-pad2_ u30 +a14 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a15 net-_u1-pad2_ net-_u16-pad2_ u16 +a16 net-_u27-pad3_ net-_u23-pad3_ net-_u31-pad2_ unconnected-_u38-pad4_ net-_u35-pad2_ unconnected-_u38-pad6_ net-_u1-pad12_ u38 +a17 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u13-pad2_ u9 +a18 [net-_u15-pad3_ net-_u20-pad3_ ] net-_u28-pad3_ u28 +a19 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u20-pad1_ u7 +a20 [net-_u20-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a21 [net-_u20-pad3_ net-_u11-pad3_ ] net-_u24-pad3_ u24 +a22 [net-_u10-pad2_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a23 [net-_u19-pad3_ net-_u10-pad3_ ] net-_u23-pad3_ u23 +a24 [net-_u1-pad5_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a25 [net-_u1-pad6_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a26 [net-_u10-pad2_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a27 [net-_u12-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a28 [net-_u17-pad3_ net-_u12-pad2_ ] net-_u21-pad3_ u21 +a29 [net-_u13-pad3_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a30 [net-_u17-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a31 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a32 [net-_u18-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a33 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a34 [net-_u1-pad3_ net-_u10-pad2_ ] net-_u12-pad2_ u8 +a35 [net-_u1-pad7_ net-_u1-pad10_ ] net-_u17-pad1_ u3 +a36 net-_u2-pad2_ net-_u33-pad1_ u5 +a37 net-_u1-pad1_ net-_u2-pad2_ u2 +a38 net-_u4-pad2_ net-_u10-pad2_ u6 +a39 /load net-_u4-pad2_ u4 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u37 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u40 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u39 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74160/SN74160.kicad_sch b/library/SubcircuitLibrary/SN74160/SN74160.kicad_sch new file mode 100644 index 000000000..97854f06f --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/SN74160.kicad_sch @@ -0,0 +1,3299 @@ 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(reference "U18") (unit 1) (value "d_or") (footprint "") + ) + (path "/b438695e-973b-46a8-bb21-bf3bf3992605" + (reference "U19") (unit 1) (value "d_or") (footprint "") + ) + (path "/941e9d26-4d22-4cf7-976c-4be64b37f70c" + (reference "U20") (unit 1) (value "d_or") (footprint "") + ) + (path "/6bea4a0e-4045-4a34-af4e-edf93128ea14" + (reference "U21") (unit 1) (value "d_and") (footprint "") + ) + (path "/df1098df-817d-4af4-a7dc-a665d1887c12" + (reference "U22") (unit 1) (value "d_and") (footprint "") + ) + (path "/c70b5a67-d053-4bb9-aa3b-bb03580088d7" + (reference "U23") (unit 1) (value "d_and") (footprint "") + ) + (path "/654e9479-0824-4cca-9c63-68b2fe0fdcc7" + (reference "U24") (unit 1) (value "d_and") (footprint "") + ) + (path "/dde17494-ca83-41ff-834c-35a4ca3432ab" + (reference "U25") (unit 1) (value "d_and") (footprint "") + ) + (path "/54bb5cae-5181-4938-9ba9-41f934bdd34f" + (reference "U26") (unit 1) (value "d_and") (footprint "") + ) + (path "/fc5b228b-4b5d-47de-b03d-5ef7936bf242" + (reference "U27") (unit 1) (value "d_and") (footprint "") + ) + (path "/349629c4-214d-47e9-b329-07235f015525" + (reference "U28") (unit 1) (value "d_and") (footprint "") + ) + (path "/43c4f933-1f10-4f3a-a45f-937a617fa915" + (reference "U29") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/262aaa7d-2c47-470c-b059-75fd356103aa" + (reference "U30") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/2f8c479b-f0cf-47ef-9d72-a3fd2292a1fb" + (reference "U31") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f89f854c-d9ec-4c65-8748-5c1996c5e713" + (reference "U32") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/082827b0-775f-4e7b-b402-9e248fd25a30" + (reference "U33") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a84d4415-0483-4197-920b-8f15ac3afcae" + (reference "U34") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/8accd106-191d-46ef-99d2-b824f17381cb" + (reference "U35") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/b7121768-005f-4f70-b700-607a3889700a" + (reference "U36") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/adcce98e-76f7-4218-b783-b15055648440" + (reference "U37") (unit 1) (value "d_jkff") (footprint "") + ) + (path "/09a6d961-dcb5-4681-9cd2-617a5d4c209a" + (reference "U38") (unit 1) (value "d_jkff") (footprint "") + ) + (path "/a1877dfc-557f-4a6d-836d-39e9dcf8a4d3" + (reference "U39") (unit 1) (value "d_jkff") (footprint "") + ) + (path "/e257feb2-c201-40ec-b165-b8d57c8ef68d" + (reference "U40") (unit 1) (value "d_jkff") (footprint "") + ) + (path "/22b9c4b1-16b1-4f73-af7b-95a38abc257e" + (reference "X1") (unit 1) (value "3_and") (footprint "") + ) + (path "/24dcf5fb-7281-4a48-a1f9-165b81b9e8eb" + (reference "X2") (unit 1) (value "4_and") (footprint "") + ) + (path "/5027c782-fbb9-4771-8330-91d4b9a146b9" + (reference "X3") (unit 1) (value "3_and") (footprint "") + ) + (path "/0d03b990-c503-47f2-ac4b-d802eeeb2f8e" + (reference "X4") (unit 1) (value "3_and") (footprint "") + ) + (path "/64b03cba-797a-4500-a2a2-8b28308a931b" + (reference "X5") (unit 1) (value "3_and") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/SN74160/SN74160.sub b/library/SubcircuitLibrary/SN74160/SN74160.sub new file mode 100644 index 000000000..2cf3a0c50 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/SN74160.sub @@ -0,0 +1,169 @@ +* Subcircuit SN74160 +.subckt SN74160 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ gnd /load net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ gnd +.title kicad schematic +.include 4_and.sub +.include 3_and.sub +* u29 net-_u16-pad2_ net-_u29-pad2_ d_inverter +* u37 net-_u25-pad3_ net-_u21-pad3_ net-_u29-pad2_ unconnected-_u37-pad4_ net-_u33-pad2_ unconnected-_u37-pad6_ net-_u1-pad14_ d_jkff +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u33-pad1_ net-_u34-pad2_ d_inverter +* u40 net-_u26-pad3_ net-_u22-pad3_ net-_u30-pad2_ unconnected-_u40-pad4_ net-_u34-pad2_ unconnected-_u40-pad6_ net-_u1-pad13_ d_jkff +* u39 net-_u28-pad3_ net-_u24-pad3_ net-_u32-pad2_ unconnected-_u39-pad4_ net-_u36-pad2_ net-_u1-pad11_ net-_u39-pad7_ d_jkff +* u36 net-_u33-pad1_ net-_u36-pad2_ d_inverter +* u32 net-_u16-pad2_ net-_u32-pad2_ d_inverter +* u35 net-_u33-pad1_ net-_u35-pad2_ d_inverter +* u31 net-_u16-pad2_ net-_u31-pad2_ d_inverter +* u27 net-_u14-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and +* u22 net-_u18-pad3_ net-_u13-pad2_ net-_u22-pad3_ d_and +* u30 net-_u16-pad2_ net-_u30-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_or +* u16 net-_u1-pad2_ net-_u16-pad2_ d_inverter +* u38 net-_u27-pad3_ net-_u23-pad3_ net-_u31-pad2_ unconnected-_u38-pad4_ net-_u35-pad2_ unconnected-_u38-pad6_ net-_u1-pad12_ d_jkff +* u9 net-_u1-pad4_ net-_u10-pad2_ net-_u13-pad2_ d_nand +x4 net-_u1-pad14_ net-_u17-pad1_ net-_u39-pad7_ net-_u18-pad1_ 3_and +* u28 net-_u15-pad3_ net-_u20-pad3_ net-_u28-pad3_ d_and +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u20-pad1_ d_or +x2 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u17-pad1_ net-_u7-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_or +* u24 net-_u20-pad3_ net-_u11-pad3_ net-_u24-pad3_ d_and +* u15 net-_u10-pad2_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u23 net-_u19-pad3_ net-_u10-pad3_ net-_u23-pad3_ d_and +* u10 net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u11 net-_u1-pad6_ net-_u10-pad2_ net-_u11-pad3_ d_nand +x1 net-_u1-pad14_ net-_u17-pad1_ net-_u1-pad11_ net-_u7-pad2_ 3_and +* u14 net-_u10-pad2_ net-_u10-pad3_ net-_u14-pad3_ d_nand +x3 net-_u1-pad13_ net-_u1-pad14_ net-_u17-pad1_ net-_u19-pad1_ 3_and +* u25 net-_u12-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u21 net-_u17-pad3_ net-_u12-pad2_ net-_u21-pad3_ d_and +* u26 net-_u13-pad3_ net-_u18-pad3_ net-_u26-pad3_ d_and +* u17 net-_u17-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_or +* u12 net-_u10-pad2_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_or +* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u8 net-_u1-pad3_ net-_u10-pad2_ net-_u12-pad2_ d_nand +x5 net-_u1-pad11_ net-_u1-pad14_ net-_u1-pad10_ net-_u1-pad15_ 3_and +* u3 net-_u1-pad7_ net-_u1-pad10_ net-_u17-pad1_ d_and +* u5 net-_u2-pad2_ net-_u33-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u10-pad2_ d_buffer +* u4 /load net-_u4-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u29-pad2_ u29 +a2 net-_u25-pad3_ net-_u21-pad3_ net-_u29-pad2_ unconnected-_u37-pad4_ net-_u33-pad2_ unconnected-_u37-pad6_ net-_u1-pad14_ u37 +a3 net-_u33-pad1_ net-_u33-pad2_ u33 +a4 net-_u33-pad1_ net-_u34-pad2_ u34 +a5 net-_u26-pad3_ net-_u22-pad3_ net-_u30-pad2_ unconnected-_u40-pad4_ net-_u34-pad2_ unconnected-_u40-pad6_ net-_u1-pad13_ u40 +a6 net-_u28-pad3_ net-_u24-pad3_ net-_u32-pad2_ unconnected-_u39-pad4_ net-_u36-pad2_ net-_u1-pad11_ net-_u39-pad7_ u39 +a7 net-_u33-pad1_ net-_u36-pad2_ u36 +a8 net-_u16-pad2_ net-_u32-pad2_ u32 +a9 net-_u33-pad1_ net-_u35-pad2_ u35 +a10 net-_u16-pad2_ net-_u31-pad2_ u31 +a11 [net-_u14-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a12 [net-_u18-pad3_ net-_u13-pad2_ ] net-_u22-pad3_ u22 +a13 net-_u16-pad2_ net-_u30-pad2_ u30 +a14 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a15 net-_u1-pad2_ net-_u16-pad2_ u16 +a16 net-_u27-pad3_ net-_u23-pad3_ net-_u31-pad2_ unconnected-_u38-pad4_ net-_u35-pad2_ unconnected-_u38-pad6_ net-_u1-pad12_ u38 +a17 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u13-pad2_ u9 +a18 [net-_u15-pad3_ net-_u20-pad3_ ] net-_u28-pad3_ u28 +a19 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u20-pad1_ u7 +a20 [net-_u20-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a21 [net-_u20-pad3_ net-_u11-pad3_ ] net-_u24-pad3_ u24 +a22 [net-_u10-pad2_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a23 [net-_u19-pad3_ net-_u10-pad3_ ] net-_u23-pad3_ u23 +a24 [net-_u1-pad5_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a25 [net-_u1-pad6_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a26 [net-_u10-pad2_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a27 [net-_u12-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a28 [net-_u17-pad3_ net-_u12-pad2_ ] net-_u21-pad3_ u21 +a29 [net-_u13-pad3_ net-_u18-pad3_ ] net-_u26-pad3_ u26 +a30 [net-_u17-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a31 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a32 [net-_u18-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a33 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a34 [net-_u1-pad3_ net-_u10-pad2_ ] net-_u12-pad2_ u8 +a35 [net-_u1-pad7_ net-_u1-pad10_ ] net-_u17-pad1_ u3 +a36 net-_u2-pad2_ net-_u33-pad1_ u5 +a37 net-_u1-pad1_ net-_u2-pad2_ u2 +a38 net-_u4-pad2_ net-_u10-pad2_ u6 +a39 /load net-_u4-pad2_ u4 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u37 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u40 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u39 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, Ngspice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74160 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74160/SN74160_Previous_Values.xml b/library/SubcircuitLibrary/SN74160/SN74160_Previous_Values.xml new file mode 100644 index 000000000..3019dde8c --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/SN74160_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or 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12850 5750 60 0000 C CNN +F 3 "" H 12850 5750 60 0000 C CNN + 11 12850 5750 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 14 1 00000000 +P 12900 700 +F 0 "U1" H 12750 675 30 0000 R CNN +F 1 "PORT" H 12750 775 30 0000 R CNN +F 2 "" H 12900 700 60 0000 C CNN +F 3 "" H 12900 700 60 0000 C CNN + 14 12900 700 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 12 1 00000000 +P 12900 4100 +F 0 "U1" H 12750 4075 30 0000 R CNN +F 1 "PORT" H 12750 4175 30 0000 R CNN +F 2 "" H 12900 4100 60 0000 C CNN +F 3 "" H 12900 4100 60 0000 C CNN + 12 12900 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 13 1 00000000 +P 12950 2450 +F 0 "U1" H 12800 2425 30 0000 R CNN +F 1 "PORT" H 12800 2525 30 0000 R CNN +F 2 "" H 12950 2450 60 0000 C CNN +F 3 "" H 12950 2450 60 0000 C CNN + 13 12950 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U2 +U 1 1 00000000 +P 50 7050 +F 0 "U2" H 50 7300 60 0000 C CNN +F 1 "d_inverter" H 50 7150 60 0000 C CNN +F 2 "" H 100 7000 60 0000 C CNN +F 3 "" H 100 7000 60 0000 C CNN + 1 50 7050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U4 +U 1 1 00000000 +P 800 600 +F 0 "U4" H 800 850 60 0000 C CNN +F 1 "d_inverter" H 800 700 60 0000 C CNN +F 2 "" H 850 550 60 0000 C CNN +F 3 "" H 850 550 60 0000 C CNN + 1 800 600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U5 +U 1 1 00000000 +P 950 7050 +F 0 "U5" H 950 7300 60 0000 C CNN +F 1 "d_inverter" H 950 7150 60 0000 C CNN +F 2 "" H 1000 7000 60 0000 C CNN +F 3 "" H 1000 7000 60 0000 C CNN + 1 950 7050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U16 +U 1 1 00000000 +P 6250 3600 +F 0 "U16" H 6250 3850 60 0000 C CNN +F 1 "d_inverter" H 6250 3700 60 0000 C CNN +F 2 "" H 6300 3550 60 0000 C CNN +F 3 "" H 6300 3550 60 0000 C CNN + 1 6250 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U29 +U 1 1 00000000 +P 9000 1100 +F 0 "U29" H 9000 1350 60 0000 C CNN +F 1 "d_inverter" H 9000 1200 60 0000 C CNN +F 2 "" H 9050 1050 60 0000 C CNN +F 3 "" H 9050 1050 60 0000 C CNN + 1 9000 1100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U30 +U 1 1 00000000 +P 9024 2850 +F 0 "U30" H 9024 3100 60 0000 C CNN +F 1 "d_inverter" H 9024 2950 60 0000 C CNN +F 2 "" H 9074 2800 60 0000 C CNN +F 3 "" H 9074 2800 60 0000 C CNN + 1 9024 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U31 +U 1 1 00000000 +P 9050 4500 +F 0 "U31" H 9050 4750 60 0000 C CNN +F 1 "d_inverter" H 9050 4600 60 0000 C CNN +F 2 "" H 9100 4450 60 0000 C CNN +F 3 "" H 9100 4450 60 0000 C CNN + 1 9050 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U32 +U 1 1 00000000 +P 9050 6150 +F 0 "U32" H 9050 6400 60 0000 C CNN +F 1 "d_inverter" H 9050 6250 60 0000 C CNN +F 2 "" H 9100 6100 60 0000 C CNN +F 3 "" H 9100 6100 60 0000 C CNN + 1 9050 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U33 +U 1 1 00000000 +P 10000 1900 +F 0 "U33" H 10000 2150 60 0000 C CNN +F 1 "d_inverter" H 10000 2000 60 0000 C CNN +F 2 "" H 10050 1850 60 0000 C CNN +F 3 "" H 10050 1850 60 0000 C CNN + 1 10000 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U34 +U 1 1 00000000 +P 10000 3650 +F 0 "U34" H 10000 3900 60 0000 C CNN +F 1 "d_inverter" H 10000 3750 60 0000 C CNN +F 2 "" H 10050 3600 60 0000 C CNN +F 3 "" H 10050 3600 60 0000 C CNN + 1 10000 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U35 +U 1 1 00000000 +P 10100 5300 +F 0 "U35" H 10100 5550 60 0000 C CNN +F 1 "d_inverter" H 10100 5400 60 0000 C CNN +F 2 "" H 10150 5250 60 0000 C CNN +F 3 "" H 10150 5250 60 0000 C CNN + 1 10100 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U36 +U 1 1 00000000 +P 10100 7050 +F 0 "U36" H 10100 7300 60 0000 C CNN +F 1 "d_inverter" H 10100 7150 60 0000 C CNN +F 2 "" H 10150 7000 60 0000 C CNN +F 3 "" H 10150 7000 60 0000 C CNN + 1 10100 7050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U3 +U 1 1 00000000 +P 700 7550 +F 0 "U3" H 700 7900 60 0000 C CNN +F 1 "d_and" H 700 7750 60 0000 C CNN +F 2 "" H 700 7550 60 0000 C CNN +F 3 "" H 700 7550 60 0000 C CNN + 1 700 7550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U7 +U 1 1 00000000 +P 4050 6150 +F 0 "U7" H 4050 6500 60 0000 C CNN +F 1 "d_or" H 4050 6350 60 0000 C CNN +F 2 "" H 4050 6150 60 0000 C CNN +F 3 "" H 4050 6150 60 0000 C CNN + 1 4050 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U8 +U 1 1 00000000 +P 5300 1650 +F 0 "U8" H 5300 2000 60 0000 C CNN +F 1 "d_nand" H 5300 1850 60 0000 C CNN +F 2 "" H 5300 1650 60 0000 C CNN +F 3 "" H 5300 1650 60 0000 C CNN + 1 5300 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U9 +U 1 1 00000000 +P 5300 3400 +F 0 "U9" H 5300 3750 60 0000 C CNN +F 1 "d_nand" H 5300 3600 60 0000 C CNN +F 2 "" H 5300 3400 60 0000 C CNN +F 3 "" H 5300 3400 60 0000 C CNN + 1 5300 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U10 +U 1 1 00000000 +P 5300 5050 +F 0 "U10" H 5300 5400 60 0000 C CNN +F 1 "d_nand" H 5300 5250 60 0000 C CNN +F 2 "" H 5300 5050 60 0000 C CNN +F 3 "" H 5300 5050 60 0000 C CNN + 1 5300 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U11 +U 1 1 00000000 +P 5300 6700 +F 0 "U11" H 5300 7050 60 0000 C CNN +F 1 "d_nand" H 5300 6900 60 0000 C CNN +F 2 "" H 5300 6700 60 0000 C CNN +F 3 "" H 5300 6700 60 0000 C CNN + 1 5300 6700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U12 +U 1 1 00000000 +P 5400 700 +F 0 "U12" H 5400 1050 60 0000 C CNN +F 1 "d_nand" H 5400 900 60 0000 C CNN +F 2 "" H 5400 700 60 0000 C CNN +F 3 "" H 5400 700 60 0000 C CNN + 1 5400 700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U13 +U 1 1 00000000 +P 5400 2450 +F 0 "U13" H 5400 2800 60 0000 C CNN +F 1 "d_nand" H 5400 2650 60 0000 C CNN +F 2 "" H 5400 2450 60 0000 C CNN +F 3 "" H 5400 2450 60 0000 C CNN + 1 5400 2450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U14 +U 1 1 00000000 +P 5400 4100 +F 0 "U14" H 5400 4450 60 0000 C CNN +F 1 "d_nand" H 5400 4300 60 0000 C CNN +F 2 "" H 5400 4100 60 0000 C CNN +F 3 "" H 5400 4100 60 0000 C CNN + 1 5400 4100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U15 +U 1 1 00000000 +P 5400 5750 +F 0 "U15" H 5400 6100 60 0000 C CNN +F 1 "d_nand" H 5400 5950 60 0000 C CNN +F 2 "" H 5400 5750 60 0000 C CNN +F 3 "" H 5400 5750 60 0000 C CNN + 1 5400 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U17 +U 1 1 00000000 +P 6350 1150 +F 0 "U17" H 6350 1500 60 0000 C CNN +F 1 "d_or" H 6350 1350 60 0000 C CNN +F 2 "" H 6350 1150 60 0000 C CNN +F 3 "" H 6350 1150 60 0000 C CNN + 1 6350 1150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U18 +U 1 1 00000000 +P 6350 2900 +F 0 "U18" H 6350 3250 60 0000 C CNN +F 1 "d_or" H 6350 3100 60 0000 C CNN +F 2 "" H 6350 2900 60 0000 C CNN +F 3 "" H 6350 2900 60 0000 C CNN + 1 6350 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U19 +U 1 1 00000000 +P 6350 4550 +F 0 "U19" H 6350 4900 60 0000 C CNN +F 1 "d_or" H 6350 4750 60 0000 C CNN +F 2 "" H 6350 4550 60 0000 C CNN +F 3 "" H 6350 4550 60 0000 C CNN + 1 6350 4550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U20 +U 1 1 00000000 +P 6350 6200 +F 0 "U20" H 6350 6550 60 0000 C CNN +F 1 "d_or" H 6350 6400 60 0000 C CNN +F 2 "" H 6350 6200 60 0000 C CNN +F 3 "" H 6350 6200 60 0000 C CNN + 1 6350 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U21 +U 1 1 00000000 +P 7500 1600 +F 0 "U21" H 7500 1950 60 0000 C CNN +F 1 "d_and" H 7500 1800 60 0000 C CNN +F 2 "" H 7500 1600 60 0000 C CNN +F 3 "" H 7500 1600 60 0000 C CNN + 1 7500 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U22 +U 1 1 00000000 +P 7500 3350 +F 0 "U22" H 7500 3700 60 0000 C CNN +F 1 "d_and" H 7500 3550 60 0000 C CNN +F 2 "" H 7500 3350 60 0000 C CNN +F 3 "" H 7500 3350 60 0000 C CNN + 1 7500 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U23 +U 1 1 00000000 +P 7500 5000 +F 0 "U23" H 7500 5350 60 0000 C CNN +F 1 "d_and" H 7500 5200 60 0000 C CNN +F 2 "" H 7500 5000 60 0000 C CNN +F 3 "" H 7500 5000 60 0000 C CNN + 1 7500 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U24 +U 1 1 00000000 +P 7500 6650 +F 0 "U24" H 7500 7000 60 0000 C CNN +F 1 "d_and" H 7500 6850 60 0000 C CNN +F 2 "" H 7500 6650 60 0000 C CNN +F 3 "" H 7500 6650 60 0000 C CNN + 1 7500 6650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U25 +U 1 1 00000000 +P 7550 750 +F 0 "U25" H 7550 1100 60 0000 C CNN +F 1 "d_and" H 7550 950 60 0000 C CNN +F 2 "" H 7550 750 60 0000 C CNN +F 3 "" H 7550 750 60 0000 C CNN + 1 7550 750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U26 +U 1 1 00000000 +P 7550 2500 +F 0 "U26" H 7550 2850 60 0000 C CNN +F 1 "d_and" H 7550 2700 60 0000 C CNN +F 2 "" H 7550 2500 60 0000 C CNN +F 3 "" H 7550 2500 60 0000 C CNN + 1 7550 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U27 +U 1 1 00000000 +P 7550 4150 +F 0 "U27" H 7550 4500 60 0000 C CNN +F 1 "d_and" H 7550 4350 60 0000 C CNN +F 2 "" H 7550 4150 60 0000 C CNN +F 3 "" H 7550 4150 60 0000 C CNN + 1 7550 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U28 +U 1 1 00000000 +P 7550 5800 +F 0 "U28" H 7550 6150 60 0000 C CNN +F 1 "d_and" H 7550 6000 60 0000 C CNN +F 2 "" H 7550 5800 60 0000 C CNN +F 3 "" H 7550 5800 60 0000 C CNN + 1 7550 5800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:3_and X1 +U 1 1 00000000 +P 2650 6450 +F 0 "X1" H 2729 6850 60 0000 C CNN +F 1 "3_and" H 2729 6700 60 0000 C CNN +F 2 "" H 2650 6450 60 0000 C CNN +F 3 "" H 2650 6450 60 0000 C CNN + 1 2650 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:3_and X3 +U 1 1 00000000 +P 3400 4500 +F 0 "X3" H 3479 4900 60 0000 C CNN +F 1 "3_and" H 3479 4750 60 0000 C CNN +F 2 "" H 3400 4500 60 0000 C CNN +F 3 "" H 3400 4500 60 0000 C CNN + 1 3400 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:3_and X4 +U 1 1 00000000 +P 3450 2850 +F 0 "X4" H 3529 3250 60 0000 C CNN +F 1 "3_and" H 3529 3100 60 0000 C CNN +F 2 "" H 3450 2850 60 0000 C CNN +F 3 "" H 3450 2850 60 0000 C CNN + 1 3450 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:3_and X5 +U 1 1 00000000 +P 5300 7950 +F 0 "X5" H 5379 8350 60 0000 C CNN +F 1 "3_and" H 5379 8200 60 0000 C CNN +F 2 "" H 5300 7950 60 0000 C CNN +F 3 "" H 5300 7950 60 0000 C CNN + 1 5300 7950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Subckt:4_and X2 +U 1 1 00000000 +P 2750 5650 +F 0 "X2" H 2803 6050 60 0000 C CNN +F 1 "4_and" H 2803 5900 60 0000 C CNN +F 2 "" H 2750 5650 60 0000 C CNN +F 3 "" H 2750 5650 60 0000 C CNN + 1 2750 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_buffer U6 +U 1 1 00000000 +P 1900 600 +F 0 "U6" H 1975 1000 60 0000 C CNN +F 1 "d_buffer" H 1975 850 60 0000 C CNN +F 2 "" H 1900 600 60 0000 C CNN +F 3 "" H 1900 600 60 0000 C CNN + 1 1900 600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_jkff U37 +U 1 1 00000000 +P 10550 1100 +F 0 "U37" H 10630 1850 60 0000 L CNN +F 1 "d_jkff" H 10630 1700 60 0000 L CNN +F 2 "" H 10550 1100 60 0000 C CNN +F 3 "" H 10550 1100 60 0000 C CNN + 1 10550 1100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_jkff U38 +U 1 1 00000000 +P 10550 4500 +F 0 "U38" H 10630 5250 60 0000 L CNN +F 1 "d_jkff" H 10630 5100 60 0000 L CNN +F 2 "" H 10550 4500 60 0000 C CNN +F 3 "" H 10550 4500 60 0000 C CNN + 1 10550 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_jkff U39 +U 1 1 00000000 +P 10550 6150 +F 0 "U39" H 10630 6900 60 0000 L CNN +F 1 "d_jkff" H 10630 6750 60 0000 L CNN +F 2 "" H 10550 6150 60 0000 C CNN +F 3 "" H 10550 6150 60 0000 C CNN + 1 10550 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_jkff U40 +U 1 1 00000000 +P 10600 2850 +F 0 "U40" H 10680 3600 60 0000 L CNN +F 1 "d_jkff" H 10680 3450 60 0000 L CNN +F 2 "" H 10600 2850 60 0000 C CNN +F 3 "" H 10600 2850 60 0000 C CNN + 1 10600 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74160/analysis b/library/SubcircuitLibrary/SN74160/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74160/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 6d7ebd8b1e3452c670c98824a06e8bef80743fce Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:31:46 +0530 Subject: [PATCH 04/10] HEF4502B is a quad 2-input multiplexer/demultiplexer IC. --- .../SubcircuitLibrary/HEF4502b/HEF4502b.cir | 16 + .../HEF4502b/HEF4502b.cir.out | 64 + .../HEF4502b/HEF4502b.kicad_sch | 1579 +++++++++++++++++ .../SubcircuitLibrary/HEF4502b/HEF4502b.sub | 58 + .../HEF4502b/HEF4502b_Previous_Values.xml | 1 + .../HEF4502b/_autosave-HEF4502b.sch | 440 +++++ library/SubcircuitLibrary/HEF4502b/analysis | 1 + 7 files changed, 2159 insertions(+) create mode 100644 library/SubcircuitLibrary/HEF4502b/HEF4502b.cir create mode 100644 library/SubcircuitLibrary/HEF4502b/HEF4502b.cir.out create mode 100644 library/SubcircuitLibrary/HEF4502b/HEF4502b.kicad_sch create mode 100644 library/SubcircuitLibrary/HEF4502b/HEF4502b.sub create mode 100644 library/SubcircuitLibrary/HEF4502b/HEF4502b_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/HEF4502b/_autosave-HEF4502b.sch create mode 100644 library/SubcircuitLibrary/HEF4502b/analysis diff --git a/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir b/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir new file mode 100644 index 000000000..c10d35186 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir @@ -0,0 +1,16 @@ +.title KiCad schematic +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad11_ d_tristate +U9 Net-_U3-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad14_ d_tristate +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad5_ d_tristate +U13 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad7_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ unconnected-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ unconnected-_U1-Pad16_ PORT +U12 Net-_U12-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad9_ d_tristate +U14 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad2_ d_tristate +U3 Net-_U1-Pad12_ Net-_U1-Pad15_ Net-_U3-Pad3_ d_nor +U2 Net-_U1-Pad4_ Net-_U10-Pad2_ d_inverter +U6 Net-_U1-Pad12_ Net-_U1-Pad10_ Net-_U12-Pad1_ d_nor +U4 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U10-Pad1_ d_nor +U8 Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U14-Pad1_ d_nor +U7 Net-_U1-Pad12_ Net-_U1-Pad6_ Net-_U13-Pad1_ d_nor +U5 Net-_U1-Pad12_ Net-_U1-Pad3_ Net-_U11-Pad1_ d_nor +.end diff --git a/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir.out b/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir.out new file mode 100644 index 000000000..5712da485 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/HEF4502b.cir.out @@ -0,0 +1,64 @@ +.title kicad schematic + +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u9 net-_u3-pad3_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad5_ d_tristate +* u13 net-_u13-pad1_ net-_u10-pad2_ net-_u1-pad7_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ port +* u12 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad9_ d_tristate +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad2_ d_tristate +* u3 net-_u1-pad12_ net-_u1-pad15_ net-_u3-pad3_ d_nor +* u2 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u6 net-_u1-pad12_ net-_u1-pad10_ net-_u12-pad1_ d_nor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u10-pad1_ d_nor +* u8 net-_u1-pad12_ net-_u1-pad1_ net-_u14-pad1_ d_nor +* u7 net-_u1-pad12_ net-_u1-pad6_ net-_u13-pad1_ d_nor +* u5 net-_u1-pad12_ net-_u1-pad3_ net-_u11-pad1_ d_nor +a1 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ u10 +a2 net-_u3-pad3_ net-_u10-pad2_ net-_u1-pad14_ u9 +a3 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad5_ u11 +a4 net-_u13-pad1_ net-_u10-pad2_ net-_u1-pad7_ u13 +a5 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad9_ u12 +a6 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad2_ u14 +a7 [net-_u1-pad12_ net-_u1-pad15_ ] net-_u3-pad3_ u3 +a8 net-_u1-pad4_ net-_u10-pad2_ u2 +a9 [net-_u1-pad12_ net-_u1-pad10_ ] net-_u12-pad1_ u6 +a10 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u10-pad1_ u4 +a11 [net-_u1-pad12_ net-_u1-pad1_ ] net-_u14-pad1_ u8 +a12 [net-_u1-pad12_ net-_u1-pad6_ ] net-_u13-pad1_ u7 +a13 [net-_u1-pad12_ net-_u1-pad3_ ] net-_u11-pad1_ u5 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HEF4502b/HEF4502b.kicad_sch b/library/SubcircuitLibrary/HEF4502b/HEF4502b.kicad_sch new file mode 100644 index 000000000..940363483 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/HEF4502b.kicad_sch @@ -0,0 +1,1579 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid e26bf366-b16b-4283-b3b9-633ef987700e) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_inverter" (id 1) (at 0 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_inverter_0_1" + (polyline + (pts + (xy -2.54 1.27) + (xy -2.54 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(footprint "") + ) + (path "/a1c71c5d-58cf-4f24-a369-b76abaa75c84" + (reference "U1") (unit 12) (value "PORT") (footprint "") + ) + (path "/25389158-a8ac-49b3-8726-72f96cc24583" + (reference "U1") (unit 13) (value "PORT") (footprint "") + ) + (path "/36cb70c1-a92a-493e-9481-3c4eedcae074" + (reference "U1") (unit 14) (value "PORT") (footprint "") + ) + (path "/66b358fd-5ff4-4326-be09-41e17d90da70" + (reference "U1") (unit 15) (value "PORT") (footprint "") + ) + (path "/9f637895-60b5-4910-9b4e-9ab635a9c7b7" + (reference "U1") (unit 16) (value "PORT") (footprint "") + ) + (path "/7675b35b-874b-44c7-8c83-8ddb655a371b" + (reference "U2") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5abc3ef8-7377-4285-83c6-5fb8d4e5f814" + (reference "U3") (unit 1) (value "d_nor") (footprint "") + ) + (path "/ecdfa517-8a97-4597-9153-faa0e872fd97" + (reference "U4") (unit 1) (value "d_nor") (footprint "") + ) + (path "/1f056f94-4801-4e0e-a297-1570991370b7" + (reference "U5") (unit 1) (value "d_nor") (footprint "") + ) + (path "/e6196875-527a-439a-93a9-995084bfaee3" + (reference "U6") (unit 1) (value "d_nor") (footprint "") + ) + (path "/d6e5303e-ffb4-45c3-b21a-6ae4f8e57424" + (reference "U7") (unit 1) (value "d_nor") (footprint "") + ) + (path "/ca242530-2cb4-4293-8e80-6ee4402dbe41" + (reference "U8") (unit 1) (value "d_nor") (footprint "") + ) + (path "/53148e8e-594a-44ff-8bee-199b80ba436f" + (reference "U9") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/47fb2e1d-3f2f-46be-a38d-7de77c78fb31" + (reference "U10") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/21430c3a-33ca-48d4-92d4-7b4c3d84fddd" + (reference "U11") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/3f87f887-4f3c-4c65-a189-f7442c75a57e" + (reference "U12") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/5bd054f9-bde8-4f8e-85f4-61ab67aef6aa" + (reference "U13") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/f3871d1e-9684-4b9c-a75c-3cd79acc5acc" + (reference "U14") (unit 1) (value "d_tristate") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/HEF4502b/HEF4502b.sub b/library/SubcircuitLibrary/HEF4502b/HEF4502b.sub new file mode 100644 index 000000000..ed3e84c74 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/HEF4502b.sub @@ -0,0 +1,58 @@ +* Subcircuit HEF4502b +.subckt HEF4502b net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ +.title kicad schematic +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u9 net-_u3-pad3_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad5_ d_tristate +* u13 net-_u13-pad1_ net-_u10-pad2_ net-_u1-pad7_ d_tristate +* u12 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad9_ d_tristate +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad2_ d_tristate +* u3 net-_u1-pad12_ net-_u1-pad15_ net-_u3-pad3_ d_nor +* u2 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u6 net-_u1-pad12_ net-_u1-pad10_ net-_u12-pad1_ d_nor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u10-pad1_ d_nor +* u8 net-_u1-pad12_ net-_u1-pad1_ net-_u14-pad1_ d_nor +* u7 net-_u1-pad12_ net-_u1-pad6_ net-_u13-pad1_ d_nor +* u5 net-_u1-pad12_ net-_u1-pad3_ net-_u11-pad1_ d_nor +a1 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ u10 +a2 net-_u3-pad3_ net-_u10-pad2_ net-_u1-pad14_ u9 +a3 net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad5_ u11 +a4 net-_u13-pad1_ net-_u10-pad2_ net-_u1-pad7_ u13 +a5 net-_u12-pad1_ net-_u10-pad2_ net-_u1-pad9_ u12 +a6 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad2_ u14 +a7 [net-_u1-pad12_ net-_u1-pad15_ ] net-_u3-pad3_ u3 +a8 net-_u1-pad4_ net-_u10-pad2_ u2 +a9 [net-_u1-pad12_ net-_u1-pad10_ ] net-_u12-pad1_ u6 +a10 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u10-pad1_ u4 +a11 [net-_u1-pad12_ net-_u1-pad1_ ] net-_u14-pad1_ u8 +a12 [net-_u1-pad12_ net-_u1-pad6_ ] net-_u13-pad1_ u7 +a13 [net-_u1-pad12_ net-_u1-pad3_ ] net-_u11-pad1_ u5 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HEF4502b \ No newline at end of file diff --git a/library/SubcircuitLibrary/HEF4502b/HEF4502b_Previous_Values.xml b/library/SubcircuitLibrary/HEF4502b/HEF4502b_Previous_Values.xml new file mode 100644 index 000000000..e3b153763 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/HEF4502b_Previous_Values.xml @@ -0,0 +1 @@ +d_tristated_tristated_tristated_tristated_tristated_tristated_nord_inverterd_nord_nord_nord_nord_nortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/HEF4502b/_autosave-HEF4502b.sch b/library/SubcircuitLibrary/HEF4502b/_autosave-HEF4502b.sch new file mode 100644 index 000000000..41ab7a30e --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/_autosave-HEF4502b.sch @@ -0,0 +1,440 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr +Connection ~ 3500 1750 +Connection ~ 3500 2550 +Connection ~ 3500 3250 +Connection ~ 3500 3950 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a/library/SubcircuitLibrary/HEF4502b/analysis b/library/SubcircuitLibrary/HEF4502b/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/HEF4502b/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 9c624623dc120686ee99afb2f4b71f44a7e657fb Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:36:09 +0530 Subject: [PATCH 05/10] LM387 is a low-noise dual operational amplifier. --- library/SubcircuitLibrary/lm387/D.lib | 2 + library/SubcircuitLibrary/lm387/NPN.lib | 4 + library/SubcircuitLibrary/lm387/PNP.lib | 4 + .../lm387/_autosave-lm387.sch | 753 ++++++ library/SubcircuitLibrary/lm387/analysis | 1 + library/SubcircuitLibrary/lm387/lm387.cir | 33 + library/SubcircuitLibrary/lm387/lm387.cir.out | 51 + .../SubcircuitLibrary/lm387/lm387.kicad_sch | 2259 +++++++++++++++++ library/SubcircuitLibrary/lm387/lm387.sub | 45 + .../lm387/lm387_Previous_Values.xml | 1 + 10 files changed, 3153 insertions(+) create mode 100644 library/SubcircuitLibrary/lm387/D.lib create mode 100644 library/SubcircuitLibrary/lm387/NPN.lib create mode 100644 library/SubcircuitLibrary/lm387/PNP.lib create mode 100644 library/SubcircuitLibrary/lm387/_autosave-lm387.sch create mode 100644 library/SubcircuitLibrary/lm387/analysis create mode 100644 library/SubcircuitLibrary/lm387/lm387.cir create mode 100644 library/SubcircuitLibrary/lm387/lm387.cir.out create mode 100644 library/SubcircuitLibrary/lm387/lm387.kicad_sch create mode 100644 library/SubcircuitLibrary/lm387/lm387.sub create mode 100644 library/SubcircuitLibrary/lm387/lm387_Previous_Values.xml diff --git a/library/SubcircuitLibrary/lm387/D.lib b/library/SubcircuitLibrary/lm387/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/lm387/NPN.lib b/library/SubcircuitLibrary/lm387/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/lm387/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm387/PNP.lib b/library/SubcircuitLibrary/lm387/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/lm387/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git 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+L eSim_Devices:resistor R2 +U 1 1 00000000 +P 2300 3900 +F 0 "R2" V 2400 3850 50 0000 R CNN +F 1 "100k" V 2300 3850 50 0000 R CNN +F 2 "" H 2350 3880 30 0000 C CNN +F 3 "" V 2350 3950 30 0000 C CNN + 1 2300 3900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R3 +U 1 1 00000000 +P 3050 4000 +F 0 "R3" H 3100 3800 50 0000 C CNN +F 1 "250k" H 3100 3900 50 0000 C CNN +F 2 "" H 3100 3980 30 0000 C CNN +F 3 "" V 3100 4050 30 0000 C CNN + 1 3050 4000 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:resistor R4 +U 1 1 00000000 +P 4100 3850 +F 0 "R4" V 4100 4000 50 0000 L CNN +F 1 "200k" V 4200 4000 50 0000 L CNN +F 2 "" H 4150 3830 30 0000 C CNN +F 3 "" V 4150 3900 30 0000 C CNN + 1 4100 3850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:resistor R5 +U 1 1 00000000 +P 4500 5300 +F 0 "R5" V 4600 5250 50 0000 R CNN +F 1 "10k" V 4500 5250 50 0000 R CNN +F 2 "" H 4550 5280 30 0000 C CNN +F 3 "" V 4550 5350 30 0000 C CNN + 1 4500 5300 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R6 +U 1 1 00000000 +P 6150 5100 +F 0 "R6" V 6250 5050 50 0000 R CNN +F 1 "47k" V 6150 5050 50 0000 R CNN +F 2 "" H 6200 5080 30 0000 C CNN +F 3 "" V 6200 5150 30 0000 C CNN + 1 6150 5100 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R7 +U 1 1 00000000 +P 7050 5400 +F 0 "R7" V 7150 5350 50 0000 R CNN +F 1 "47k" V 7050 5350 50 0000 R CNN +F 2 "" H 7100 5380 30 0000 C CNN +F 3 "" V 7100 5450 30 0000 C CNN + 1 7050 5400 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R8 +U 1 1 00000000 +P 9000 3550 +F 0 "R8" V 9100 3500 50 0000 R CNN +F 1 "4.7k" V 9000 3500 50 0000 R CNN +F 2 "" H 9050 3530 30 0000 C CNN +F 3 "" V 9050 3600 30 0000 C CNN + 1 9000 3550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R9 +U 1 1 00000000 +P 9700 4200 +F 0 "R9" V 9800 4150 50 0000 R CNN +F 1 "50k" V 9700 4150 50 0000 R CNN +F 2 "" H 9750 4180 30 0000 C CNN +F 3 "" V 9750 4250 30 0000 C CNN + 1 9700 4200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 1 1 00000000 +P 2650 6650 +F 0 "U3" H 2675 6850 30 0000 C CNN +F 1 "PORT" H 2675 6750 30 0000 C CNN +F 2 "" H 2650 6650 60 0000 C CNN +F 3 "" H 2650 6650 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 8 1 00000000 +P 3150 6650 +F 0 "U3" H 3000 6625 30 0000 R CNN +F 1 "PORT" H 3000 6725 30 0000 R CNN +F 2 "" H 3150 6650 60 0000 C CNN +F 3 "" H 3150 6650 60 0000 C CNN + 8 3150 6650 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 6 1 00000000 +P 3750 1000 +F 0 "U3" V 3750 1100 30 0000 L CNN +F 1 "PORT" V 3850 1100 30 0000 L CNN +F 2 "" H 3750 1000 60 0000 C CNN +F 3 "" H 3750 1000 60 0000 C CNN + 6 3750 1000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 3 1 00000000 +P 4200 6050 +F 0 "U3" H 4225 6250 30 0000 C CNN +F 1 "PORT" H 4225 6150 30 0000 C CNN +F 2 "" H 4200 6050 60 0000 C CNN +F 3 "" H 4200 6050 60 0000 C CNN + 3 4200 6050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 2 1 00000000 +P 5350 6750 +F 0 "U3" H 5375 6950 30 0000 C CNN +F 1 "PORT" H 5375 6850 30 0000 C CNN +F 2 "" H 5350 6750 60 0000 C CNN +F 3 "" H 5350 6750 60 0000 C CNN + 2 5350 6750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 7 1 00000000 +P 5900 6750 +F 0 "U3" H 5750 6725 30 0000 R CNN +F 1 "PORT" H 5750 6825 30 0000 R CNN +F 2 "" H 5900 6750 60 0000 C CNN +F 3 "" H 5900 6750 60 0000 C CNN + 7 5900 6750 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 4 1 00000000 +P 10300 4400 +F 0 "U3" V 10300 4500 30 0000 L CNN +F 1 "PORT" V 10400 4500 30 0000 L CNN +F 2 "" H 10300 4400 60 0000 C CNN +F 3 "" H 10300 4400 60 0000 C CNN + 4 10300 4400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U3 +U 5 1 00000000 +P 10300 4900 +F 0 "U3" V 10350 4800 30 0000 R CNN +F 1 "PORT" V 10250 4800 30 0000 R CNN +F 2 "" H 10300 4900 60 0000 C CNN +F 3 "" H 10300 4900 60 0000 C CNN + 5 10300 4900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D1 +U 1 1 00000000 +P 1300 3150 +F 0 "D1" H 1302 3450 50 0000 C CNN +F 1 "eSim_Diode" H 1302 3350 50 0000 C CNN +F 2 "" H 1300 3150 60 0000 C CNN +F 3 "" H 1300 3150 60 0000 C CNN + 1 1300 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D2 +U 1 1 00000000 +P 2250 4400 +F 0 "D2" V 2202 4550 50 0000 L CNN +F 1 "eSim_Diode" V 2302 4550 50 0000 L CNN +F 2 "" H 2250 4400 60 0000 C CNN +F 3 "" H 2250 4400 60 0000 C CNN + 1 2250 4400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D3 +U 1 1 00000000 +P 2250 4950 +F 0 "D3" V 2202 5100 50 0000 L CNN +F 1 "eSim_Diode" V 2302 5100 50 0000 L CNN +F 2 "" H 2250 4950 60 0000 C CNN +F 3 "" H 2250 4950 60 0000 C CNN + 1 2250 4950 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:capacitor C1 +U 1 1 00000000 +P 5700 3650 +F 0 "C1" V 6000 3650 50 0000 C CNN +F 1 "1uf" V 5900 3650 50 0000 C CNN +F 2 "" H 5738 3500 30 0000 C CNN +F 3 "" H 5700 3650 60 0000 C CNN + 1 5700 3650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Analog:zener U1 +U 1 1 00000000 +P 900 3950 +F 0 "U1" V 1025 3800 60 0000 R CNN +F 1 "zener" V 875 3800 60 0000 R CNN +F 2 "" H 950 3950 60 0000 C CNN +F 3 "" H 950 3950 60 0000 C CNN + 1 900 3950 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Analog:zener U2 +U 1 1 00000000 +P 1800 4000 +F 0 "U2" V 1925 3850 60 0000 R CNN +F 1 "zener" V 1775 3850 60 0000 R CNN +F 2 "" H 1850 4000 60 0000 C CNN +F 3 "" H 1850 4000 60 0000 C CNN + 1 1800 4000 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q1 +U 1 1 00000000 +P 2150 3150 +F 0 "Q1" H 2350 3200 50 0000 L CNN +F 1 "eSim_NPN" H 2350 3100 50 0000 L CNN +F 2 "" H 2350 3250 29 0000 C CNN +F 3 "" H 2150 3150 60 0000 C CNN + 1 2150 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q2 +U 1 1 00000000 +P 2350 2350 +F 0 "Q2" H 2550 2300 50 0000 L CNN +F 1 "eSim_PNP" H 2550 2400 50 0000 L CNN +F 2 "" H 2550 2450 29 0000 C CNN +F 3 "" H 2350 2350 60 0000 C CNN + 1 2350 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q3 +U 1 1 00000000 +P 2950 2100 +F 0 "Q3" H 3150 2050 50 0000 L CNN +F 1 "eSim_PNP" H 3150 2150 50 0000 L CNN +F 2 "" H 3150 2200 29 0000 C CNN +F 3 "" H 2950 2100 60 0000 C CNN + 1 2950 2100 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q4 +U 1 1 00000000 +P 3350 2500 +F 0 "Q4" H 3550 2450 50 0000 L CNN +F 1 "eSim_PNP" H 3550 2550 50 0000 L CNN +F 2 "" H 3550 2600 29 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3350 2500 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q5 +U 1 1 00000000 +P 4050 4600 +F 0 "Q5" H 4250 4650 50 0000 L CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 L CNN +F 2 "" H 4250 4700 29 0000 C CNN +F 3 "" H 4050 4600 60 0000 C CNN + 1 4050 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q6 +U 1 1 00000000 +P 4900 4600 +F 0 "Q6" H 5100 4650 50 0000 L CNN +F 1 "eSim_NPN" H 5100 4550 50 0000 L CNN +F 2 "" H 5100 4700 29 0000 C CNN +F 3 "" H 4900 4600 60 0000 C CNN + 1 4900 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q7 +U 1 1 00000000 +P 5800 4150 +F 0 "Q7" H 6000 4200 50 0000 L CNN +F 1 "eSim_NPN" H 6000 4100 50 0000 L CNN +F 2 "" H 6000 4250 29 0000 C CNN +F 3 "" H 5800 4150 60 0000 C CNN + 1 5800 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q8 +U 1 1 00000000 +P 6400 3150 +F 0 "Q8" H 6600 3200 50 0000 L CNN +F 1 "eSim_NPN" H 6600 3100 50 0000 L CNN +F 2 "" H 6600 3250 29 0000 C CNN +F 3 "" H 6400 3150 60 0000 C CNN + 1 6400 3150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q9 +U 1 1 00000000 +P 6400 4250 +F 0 "Q9" H 6600 4300 50 0000 L CNN +F 1 "eSim_NPN" H 6600 4200 50 0000 L CNN +F 2 "" H 6600 4350 29 0000 C CNN +F 3 "" H 6400 4250 60 0000 C CNN + 1 6400 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q10 +U 1 1 00000000 +P 7450 2350 +F 0 "Q10" H 7650 2300 50 0000 L CNN +F 1 "eSim_PNP" H 7650 2400 50 0000 L CNN +F 2 "" H 7650 2450 29 0000 C CNN +F 3 "" H 7450 2350 60 0000 C CNN + 1 7450 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q11 +U 1 1 00000000 +P 7450 4700 +F 0 "Q11" H 7650 4750 50 0000 L CNN +F 1 "eSim_NPN" H 7650 4650 50 0000 L CNN +F 2 "" H 7650 4800 29 0000 C CNN +F 3 "" H 7450 4700 60 0000 C CNN + 1 7450 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q12 +U 1 1 00000000 +P 8250 3800 +F 0 "Q12" H 8450 3850 50 0000 L CNN +F 1 "eSim_NPN" H 8450 3750 50 0000 L CNN +F 2 "" H 8450 3900 29 0000 C CNN +F 3 "" H 8250 3800 60 0000 C CNN + 1 8250 3800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q13 +U 1 1 00000000 +P 8400 2850 +F 0 "Q13" H 8600 2900 50 0000 L CNN +F 1 "eSim_NPN" H 8600 2800 50 0000 L CNN +F 2 "" H 8600 2950 29 0000 C CNN +F 3 "" H 8400 2850 60 0000 C CNN + 1 8400 2850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q14 +U 1 1 00000000 +P 9550 3250 +F 0 "Q14" H 9750 3300 50 0000 L CNN +F 1 "eSim_NPN" H 9750 3200 50 0000 L CNN +F 2 "" H 9750 3350 29 0000 C CNN +F 3 "" H 9550 3250 60 0000 C CNN + 1 9550 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q15 +U 1 1 00000000 +P 9550 5500 +F 0 "Q15" H 9750 5550 50 0000 L CNN +F 1 "eSim_NPN" H 9750 5450 50 0000 L CNN +F 2 "" H 9750 5600 29 0000 C CNN +F 3 "" H 9550 5500 60 0000 C CNN + 1 9550 5500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm387/analysis b/library/SubcircuitLibrary/lm387/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm387/lm387.cir b/library/SubcircuitLibrary/lm387/lm387.cir new file mode 100644 index 000000000..74d1e55cf --- /dev/null +++ b/library/SubcircuitLibrary/lm387/lm387.cir @@ -0,0 +1,33 @@ +.title KiCad schematic +Q6 Net-_Q1-Pad3_ Net-_Q6-Pad2_ Net-_Q5-Pad3_ eSim_NPN +R4 Net-_Q1-Pad3_ Net-_C1-Pad1_ 200k +U3 Net-_Q5-Pad2_ Net-_Q6-Pad2_ GND Net-_Q12-Pad3_ Net-_Q12-Pad3_ Net-_Q10-Pad3_ Net-_Q6-Pad2_ Net-_Q5-Pad2_ PORT +R6 GND Net-_Q7-Pad3_ 47k +Q7 Net-_Q7-Pad1_ Net-_C1-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q13 Net-_Q10-Pad3_ Net-_C1-Pad2_ Net-_Q13-Pad3_ eSim_NPN +Q10 Net-_C1-Pad2_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP +R8 Net-_Q12-Pad2_ Net-_Q13-Pad3_ 4.7k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ GND eSim_Diode +R5 GND Net-_Q5-Pad3_ 10k +Q5 Net-_C1-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +U1 GND Net-_D1-Pad1_ zener +Q2 GND Net-_Q1-Pad1_ Net-_Q10-Pad2_ eSim_PNP +R1 Net-_D1-Pad1_ Net-_Q10-Pad3_ 250k +U2 GND Net-_D1-Pad2_ zener +R3 Net-_Q5-Pad2_ Net-_D2-Pad1_ 250k +R2 Net-_D2-Pad1_ Net-_Q1-Pad3_ 100k +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R7 GND Net-_Q11-Pad2_ 47k +Q9 Net-_Q7-Pad1_ Net-_Q7-Pad3_ Net-_Q11-Pad2_ eSim_NPN +Q11 Net-_C1-Pad2_ Net-_Q11-Pad2_ GND eSim_NPN +Q12 Net-_C1-Pad2_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q15 Net-_Q12-Pad3_ Net-_Q11-Pad2_ GND eSim_NPN +R9 Net-_Q12-Pad3_ Net-_Q12-Pad2_ 50k +Q14 Net-_Q10-Pad3_ Net-_Q13-Pad3_ Net-_Q12-Pad2_ eSim_NPN +Q3 Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_PNP +Q4 Net-_D1-Pad2_ Net-_Q1-Pad1_ Net-_Q3-Pad2_ eSim_PNP +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 1uf +Q8 Net-_Q10-Pad3_ Net-_D1-Pad2_ Net-_Q7-Pad1_ eSim_NPN +.end diff --git a/library/SubcircuitLibrary/lm387/lm387.cir.out b/library/SubcircuitLibrary/lm387/lm387.cir.out new file mode 100644 index 000000000..9ec4b6d56 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/lm387.cir.out @@ -0,0 +1,51 @@ +.title kicad schematic + +.include D.lib +.include NPN.lib +.include PNP.lib +q6 net-_q1-pad3_ net-_q6-pad2_ net-_q5-pad3_ Q2N2222 +r4 net-_q1-pad3_ net-_c1-pad1_ 200k +* u3 net-_q5-pad2_ net-_q6-pad2_ gnd net-_q12-pad3_ net-_q12-pad3_ net-_q10-pad3_ net-_q6-pad2_ net-_q5-pad2_ port +r6 gnd net-_q7-pad3_ 47k +q7 net-_q7-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222 +q13 net-_q10-pad3_ net-_c1-pad2_ net-_q13-pad3_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +r8 net-_q12-pad2_ net-_q13-pad3_ 4.7k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ gnd 1N4148 +r5 gnd net-_q5-pad3_ 10k +q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +* u1 gnd net-_d1-pad1_ zener +q2 gnd net-_q1-pad1_ net-_q10-pad2_ Q2N2907A +r1 net-_d1-pad1_ net-_q10-pad3_ 250k +* u2 gnd net-_d1-pad2_ zener +r3 net-_q5-pad2_ net-_d2-pad1_ 250k +r2 net-_d2-pad1_ net-_q1-pad3_ 100k +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r7 gnd net-_q11-pad2_ 47k +q9 net-_q7-pad1_ net-_q7-pad3_ net-_q11-pad2_ Q2N2222 +q11 net-_c1-pad2_ net-_q11-pad2_ gnd Q2N2222 +q12 net-_c1-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q15 net-_q12-pad3_ net-_q11-pad2_ gnd Q2N2222 +r9 net-_q12-pad3_ net-_q12-pad2_ 50k +q14 net-_q10-pad3_ net-_q13-pad3_ net-_q12-pad2_ Q2N2222 +q3 net-_q1-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2907A +q4 net-_d1-pad2_ net-_q1-pad1_ net-_q3-pad2_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 1uf +q8 net-_q10-pad3_ net-_d1-pad2_ net-_q7-pad1_ Q2N2222 +a1 gnd net-_d1-pad1_ u1 +a2 gnd net-_d1-pad2_ u2 +* Schematic Name: zener, Ngspice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm387/lm387.kicad_sch b/library/SubcircuitLibrary/lm387/lm387.kicad_sch new file mode 100644 index 000000000..de8b23965 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/lm387.kicad_sch @@ -0,0 +1,2259 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid fcc25ef5-5933-4ad2-84c8-f6dcfff1670b) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Analog:zener" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at -1.27 -2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "zener" (id 1) (at 0 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 1.27 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 1.27 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "zener_0_1" + (polyline + (pts + (xy 2.54 -1.27) + (xy 1.27 -2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 1.27) + (xy 2.54 -1.27) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 1.27) + (xy 3.81 2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 1.27) + (xy 0 -1.27) + (xy 2.54 0) + (xy 0 1.27) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "zener_1_1" + (pin input line (at -5.08 0 0) (length 5.08) + (name "~" (effects (font (size 1.0922 1.0922)))) + (number "IN" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 7.62 0 180) (length 5.08) + (name "~" (effects (font (size 1.0922 1.0922)))) + (number "OUT" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "eSim_Devices:capacitor" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes) + (property "Reference" "C" (id 0) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "capacitor" (id 1) (at 0.635 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "" (id 2) (at 0.9652 -3.81 0) + (effects (font (size 0.762 0.762))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "ki_fp_filters" "C_*" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "capacitor_0_1" + (polyline + (pts + (xy -2.032 -0.762) + (xy 2.032 -0.762) + ) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -2.032 0.762) + (xy 2.032 0.762) + ) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "capacitor_1_1" + (pin passive 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"Value" "47k" (id 1) (at 157.48 129.5399 90) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Footprint" "" (id 2) (at 156.718 128.27 0) + (effects (font (size 0.762 0.762))) + ) + (property "Datasheet" "" (id 3) (at 154.94 128.27 90) + (effects (font (size 0.762 0.762))) + ) + (pin "1" (uuid b6f28268-d416-43e6-aade-74b834cd120d)) + (pin "2" (uuid 7cdb9faa-b284-417f-a8bc-b41a11f6130a)) + ) + + (sheet_instances + (path "/" (page "1")) + ) + + (symbol_instances + (path "/fe8f8500-abea-4160-a486-3b9bbf7b6399" + (reference "#PWR0101") (unit 1) (value "eSim_GND") (footprint "") + ) + (path "/236c8c4f-6f3a-4ae0-9dee-8b57e87bcd0a" + (reference "#PWR0102") (unit 1) (value "eSim_GND") (footprint "") + ) + (path "/cf0ec61f-fd98-4104-bc5c-03a165f0276e" + (reference "C1") (unit 1) (value "1uf") (footprint "") + ) + (path "/1d1301de-4dcf-4efd-8bbd-45e6d59a00f6" + (reference "D1") (unit 1) (value "eSim_Diode") (footprint "") + ) + (path "/77ea714b-6899-4099-9323-0b6223a2d173" + (reference "D2") (unit 1) (value "eSim_Diode") (footprint "") + ) + (path "/d4158199-2b24-46cb-a439-182c73b36b68" + (reference "D3") (unit 1) (value "eSim_Diode") (footprint "") + ) + (path "/2de92cfe-42b4-4542-a62e-6e625f922188" + (reference "Q1") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/7a68412e-f929-476c-bd01-14b13e466047" + (reference "Q2") (unit 1) (value "eSim_PNP") (footprint "") + ) + (path "/28b7890e-276b-41a4-9a44-1d01ff3f1ea5" + (reference "Q3") (unit 1) (value "eSim_PNP") (footprint "") + ) + (path "/893bc30e-1846-45ab-9ce4-4f7d3b4b3f71" + (reference "Q4") (unit 1) (value "eSim_PNP") (footprint "") + ) + (path "/be68c505-bf5f-49b1-9147-0a69d4f1a972" + (reference "Q5") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/97b334d2-67e0-4f25-93f0-a9cf8ed46112" + (reference "Q6") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/ab9e8b1d-7374-4b87-89bb-090a6f35240f" + (reference "Q7") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/4474ba84-e914-443b-9b1c-576c4060836b" + (reference "Q8") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/85276df5-79b9-4130-8896-b28370b1bf33" + (reference "Q9") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/a7afda34-1c37-4d1e-b38e-b342f999da49" + (reference "Q10") (unit 1) (value "eSim_PNP") (footprint "") + ) + (path "/96856cc5-fa19-455c-a1ea-51fe54033e53" + (reference "Q11") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/030a40bd-9010-43d6-80bc-a7dc6766f494" + (reference "Q12") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/494ae823-8e8e-4adf-abec-49f0afa066cc" + (reference "Q13") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/79f13dbd-8d88-49fb-b247-a08239e16723" + (reference "Q14") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/9c9c62c1-7687-41f4-b259-83a22dc47afa" + (reference "Q15") (unit 1) (value "eSim_NPN") (footprint "") + ) + (path "/9f94b180-c4dd-498c-88bd-9cd15a0d61f8" + (reference "R1") (unit 1) (value "250k") (footprint "") + ) + (path "/e0e0dcb3-429a-4cdc-8b40-b76b66853703" + (reference "R2") (unit 1) (value "100k") (footprint "") + ) + (path "/7ef0524e-35e9-4799-aa06-7cbbe9eed141" + (reference "R3") (unit 1) (value "250k") (footprint "") + ) + (path "/285c50f7-d6f6-4c92-a41a-d953807d72b0" + (reference "R4") (unit 1) (value "200k") (footprint "") + ) + (path "/30464e63-e7c2-454c-9798-37519f83860d" + (reference "R5") (unit 1) (value "10k") (footprint "") + ) + (path "/ffbfcb65-8c47-4339-b0cf-1c97ea4cb924" + (reference "R6") (unit 1) (value "47k") (footprint "") + ) + (path "/d3e5c23b-8ad2-44b3-9673-1b2dd329ab14" + (reference "R7") (unit 1) (value "47k") (footprint "") + ) + (path "/427b1e2b-fbac-40aa-9d26-f5412658875f" + (reference "R8") (unit 1) (value "4.7k") (footprint "") + ) + (path "/66d443cc-2c27-4c14-8aa2-3e6096e6a139" + (reference "R9") (unit 1) (value "50k") (footprint "") + ) + (path "/18ff5a6b-fe90-4048-9355-999f8d927f1f" + (reference "U1") (unit 1) (value "zener") (footprint "") + ) + (path "/2b3bca54-3314-426d-8c8e-9e8608c7f125" + (reference "U2") (unit 1) (value "zener") (footprint "") + ) + (path "/e630324a-e56b-48ce-b875-7505d5cbd60e" + (reference "U3") (unit 1) (value "PORT") (footprint "") + ) + (path "/10fb997a-b1aa-49e5-9d0a-917f2229d64e" + (reference "U3") (unit 2) (value "PORT") (footprint "") + ) + (path "/2688e7d7-b70d-42ab-9f82-6e61c7fd5985" + (reference "U3") (unit 3) (value "PORT") (footprint "") + ) + (path "/5f7e4c9f-cec5-4424-8ed5-8e348d8c95d8" + (reference "U3") (unit 4) (value "PORT") (footprint "") + ) + (path "/bbb6387d-c008-4a8e-b149-6614350344dd" + (reference "U3") (unit 5) (value "PORT") (footprint "") + ) + (path "/0573bc73-8c56-4d0c-8ff1-5fc04caf4ba7" + (reference "U3") (unit 6) (value "PORT") (footprint "") + ) + (path "/832eb82f-749b-4d00-8551-5e14c7b8540e" + (reference "U3") (unit 7) (value "PORT") (footprint "") + ) + (path "/1fd351d7-bb60-4c73-b4a2-239e25e832ea" + (reference "U3") (unit 8) (value "PORT") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/lm387/lm387.sub b/library/SubcircuitLibrary/lm387/lm387.sub new file mode 100644 index 000000000..465cd8133 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/lm387.sub @@ -0,0 +1,45 @@ +* Subcircuit lm387 +.subckt lm387 net-_q5-pad2_ net-_q6-pad2_ gnd net-_q12-pad3_ net-_q12-pad3_ net-_q10-pad3_ net-_q6-pad2_ net-_q5-pad2_ +.title kicad schematic +.include D.lib +.include NPN.lib +.include PNP.lib +q6 net-_q1-pad3_ net-_q6-pad2_ net-_q5-pad3_ Q2N2222 +r4 net-_q1-pad3_ net-_c1-pad1_ 200k +r6 gnd net-_q7-pad3_ 47k +q7 net-_q7-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222 +q13 net-_q10-pad3_ net-_c1-pad2_ net-_q13-pad3_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +r8 net-_q12-pad2_ net-_q13-pad3_ 4.7k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ gnd 1N4148 +r5 gnd net-_q5-pad3_ 10k +q5 net-_c1-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +* u1 gnd net-_d1-pad1_ zener +q2 gnd net-_q1-pad1_ net-_q10-pad2_ Q2N2907A +r1 net-_d1-pad1_ net-_q10-pad3_ 250k +* u2 gnd net-_d1-pad2_ zener +r3 net-_q5-pad2_ net-_d2-pad1_ 250k +r2 net-_d2-pad1_ net-_q1-pad3_ 100k +q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r7 gnd net-_q11-pad2_ 47k +q9 net-_q7-pad1_ net-_q7-pad3_ net-_q11-pad2_ Q2N2222 +q11 net-_c1-pad2_ net-_q11-pad2_ gnd Q2N2222 +q12 net-_c1-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q15 net-_q12-pad3_ net-_q11-pad2_ gnd Q2N2222 +r9 net-_q12-pad3_ net-_q12-pad2_ 50k +q14 net-_q10-pad3_ net-_q13-pad3_ net-_q12-pad2_ Q2N2222 +q3 net-_q1-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2907A +q4 net-_d1-pad2_ net-_q1-pad1_ net-_q3-pad2_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 1uf +q8 net-_q10-pad3_ net-_d1-pad2_ net-_q7-pad1_ Q2N2222 +a1 gnd net-_d1-pad1_ u1 +a2 gnd net-_d1-pad2_ u2 +* Schematic Name: zener, Ngspice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends lm387 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm387/lm387_Previous_Values.xml b/library/SubcircuitLibrary/lm387/lm387_Previous_Values.xml new file mode 100644 index 000000000..b755975a1 --- /dev/null +++ b/library/SubcircuitLibrary/lm387/lm387_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecseczenerzenerD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib \ No newline at end of file From db69d7f0e7fc72c4be867e56564b8939b8490e1b Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:37:36 +0530 Subject: [PATCH 06/10] MC1514 is a high-speed voltage comparator IC --- library/SubcircuitLibrary/mc1514_sub/D.lib | 2 + library/SubcircuitLibrary/mc1514_sub/NPN.lib | 4 + .../mc1514_sub/_autosave-mc1514_sub.cir | 46 + .../mc1514_sub/_autosave-mc1514_sub.kicad_prl | 75 + .../mc1514_sub/_autosave-mc1514_sub.kicad_pro | 303 ++ .../mc1514_sub/_autosave-mc1514_sub.sch | 968 ++++++ library/SubcircuitLibrary/mc1514_sub/analysis | 1 + .../mc1514_sub/mc1514_sub.cir | 46 + .../mc1514_sub/mc1514_sub.cir.out | 75 + .../mc1514_sub/mc1514_sub.kicad_sch | 2681 +++++++++++++++++ .../mc1514_sub/mc1514_sub.sub | 69 + .../mc1514_sub/mc1514_sub_Previous_Values.xml | 1 + 12 files changed, 4271 insertions(+) create mode 100644 library/SubcircuitLibrary/mc1514_sub/D.lib create mode 100644 library/SubcircuitLibrary/mc1514_sub/NPN.lib create mode 100644 library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.cir create mode 100644 library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.kicad_prl create mode 100644 library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.kicad_pro create mode 100644 library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.sch create mode 100644 library/SubcircuitLibrary/mc1514_sub/analysis create mode 100644 library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir create mode 100644 library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir.out create mode 100644 library/SubcircuitLibrary/mc1514_sub/mc1514_sub.kicad_sch create mode 100644 library/SubcircuitLibrary/mc1514_sub/mc1514_sub.sub create mode 100644 library/SubcircuitLibrary/mc1514_sub/mc1514_sub_Previous_Values.xml diff --git a/library/SubcircuitLibrary/mc1514_sub/D.lib b/library/SubcircuitLibrary/mc1514_sub/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1514_sub/NPN.lib b/library/SubcircuitLibrary/mc1514_sub/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.cir b/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.cir new file mode 100644 index 000000000..92ade78be --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.cir @@ -0,0 +1,46 @@ +.title KiCad schematic +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +R14 Net-_R14-Pad1_ Net-_D4-Pad2_ 100 +R16 Net-_R14-Pad1_ Net-_Q14-Pad3_ 200 +Q14 Net-_Q13-Pad3_ Net-_D4-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R12 Net-_Q10-Pad3_ Net-_D4-Pad1_ 1k +U1 Net-_Q8-Pad1_ Net-_U1-Pad2_ Net-_Q2-Pad1_ unconnected-_U1-Pad4_ Net-_Q13-Pad2_ Net-_Q16-Pad2_ Net-_R2-Pad1_ Net-_Q10-Pad1_ Net-_U1-Pad9_ Net-_Q15-Pad1_ Net-_Q10-Pad2_ Net-_Q4-Pad2_ Net-_Q1-Pad2_ Net-_R14-Pad1_ PORT +R11 Net-_Q11-Pad1_ Net-_D3-Pad2_ 1.1k +U7 Net-_Q10-Pad2_ Net-_Q11-Pad3_ zener +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q12 Net-_D3-Pad1_ Net-_Q12-Pad2_ Net-_Q11-Pad3_ eSim_NPN +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +R13 Net-_D3-Pad1_ Net-_Q15-Pad1_ 3.7k +Q16 Net-_Q11-Pad2_ Net-_Q16-Pad2_ Net-_Q13-Pad3_ eSim_NPN +Q13 Net-_Q12-Pad2_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +R17 Net-_Q11-Pad2_ Net-_Q15-Pad3_ 740 +R15 Net-_Q12-Pad2_ Net-_Q15-Pad3_ 740 +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad1_ Net-_Q15-Pad3_ eSim_NPN +U5 Net-_Q10-Pad1_ Net-_Q9-Pad3_ zener +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q9 Net-_Q15-Pad1_ Net-_D3-Pad1_ Net-_Q9-Pad3_ eSim_NPN +U6 Net-_U1-Pad9_ Net-_D3-Pad1_ zener +R10 Net-_D3-Pad2_ Net-_Q15-Pad1_ 2.8k +R9 Net-_Q15-Pad1_ Net-_Q2-Pad1_ 47 +U3 Net-_U1-Pad2_ Net-_D2-Pad1_ zener +Q7 Net-_Q2-Pad1_ Net-_D2-Pad1_ Net-_Q7-Pad3_ eSim_NPN +U4 Net-_Q8-Pad1_ Net-_Q7-Pad3_ zener +Q5 Net-_D2-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad2_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R8 Net-_Q2-Pad2_ Net-_D2-Pad2_ 1.1k +R3 Net-_Q4-Pad1_ Net-_Q2-Pad3_ 740 +R1 Net-_Q1-Pad1_ Net-_Q2-Pad3_ 740 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +R6 Net-_Q8-Pad3_ Net-_D1-Pad1_ 1k +Q8 Net-_Q8-Pad1_ Net-_Q10-Pad2_ Net-_Q8-Pad3_ eSim_NPN +U2 Net-_Q10-Pad2_ Net-_Q5-Pad3_ zener +R5 Net-_D2-Pad1_ Net-_Q2-Pad1_ 3.7k +R7 Net-_D2-Pad2_ Net-_Q2-Pad1_ 2.8k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +R2 Net-_R2-Pad1_ Net-_Q3-Pad3_ 200 +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R4 Net-_R2-Pad1_ Net-_D1-Pad2_ 100 +.end diff --git a/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.kicad_prl b/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.kicad_prl new file mode 100644 index 000000000..10ca05029 --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/_autosave-mc1514_sub.kicad_prl @@ -0,0 +1,75 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "pads": 1.0, + "tracks": 1.0, + "vias": 1.0, + "zones": 0.6 + }, + "ratsnest_display_mode": 0, + "selection_filter": { + "dimensions": true, + "footprints": true, + "graphics": true, + "keepouts": true, + "lockedItems": true, + "otherItems": true, + "pads": true, + "text": true, + "tracks": true, + "vias": true, + "zones": true + }, + "visible_items": [ + 0, + 1, + 2, + 3, + 4, + 5, + 8, + 9, + 10, + 11, + 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9800 5730 30 0000 C CNN +F 3 "" V 9800 5800 30 0000 C CNN + 1 9750 5750 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R17 +U 1 1 00000000 +P 10150 3450 +F 0 "R17" V 10250 3400 50 0000 R CNN +F 1 "740" V 10150 3400 50 0000 R CNN +F 2 "" H 10200 3430 30 0000 C CNN +F 3 "" V 10200 3500 30 0000 C CNN + 1 10150 3450 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 13 1 00000000 +P 800 4250 +F 0 "U1" H 825 4450 30 0000 C CNN +F 1 "PORT" H 825 4350 30 0000 C CNN +F 2 "" H 800 4250 60 0000 C CNN +F 3 "" H 800 4250 60 0000 C CNN + 13 800 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 12 1 00000000 +P 950 5050 +F 0 "U1" V 1000 4950 30 0000 R CNN +F 1 "PORT" V 900 4950 30 0000 R CNN +F 2 "" H 950 5050 60 0000 C CNN +F 3 "" H 950 5050 60 0000 C CNN + 12 950 5050 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 4 1 00000000 +P 1850 1000 +F 0 "U1" V 1850 1100 30 0000 L CNN +F 1 "PORT" V 1950 1100 30 0000 L CNN +F 2 "" H 1850 1000 60 0000 C CNN +F 3 "" H 1850 1000 60 0000 C CNN + 4 1850 1000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 7 1 00000000 +P 3050 6450 +F 0 "U1" V 3050 6550 30 0000 L CNN +F 1 "PORT" V 3150 6550 30 0000 L CNN +F 2 "" H 3050 6450 60 0000 C CNN +F 3 "" H 3050 6450 60 0000 C CNN + 7 3050 6450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 3 1 00000000 +P 3200 1000 +F 0 "U1" V 3200 1100 30 0000 L CNN +F 1 "PORT" V 3300 1100 30 0000 L CNN +F 2 "" H 3200 1000 60 0000 C CNN +F 3 "" H 3200 1000 60 0000 C CNN + 3 3200 1000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 11 1 00000000 +P 3500 6900 +F 0 "U1" V 3550 6800 30 0000 R CNN +F 1 "PORT" V 3450 6800 30 0000 R CNN +F 2 "" H 3500 6900 60 0000 C CNN +F 3 "" H 3500 6900 60 0000 C CNN + 11 3500 6900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 2 1 00000000 +P 4550 700 +F 0 "U1" V 4550 800 30 0000 L CNN +F 1 "PORT" V 4650 800 30 0000 L CNN +F 2 "" H 4550 700 60 0000 C CNN +F 3 "" H 4550 700 60 0000 C CNN + 2 4550 700 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 1 1 00000000 +P 5000 7250 +F 0 "U1" H 5025 7450 30 0000 C CNN +F 1 "PORT" H 5025 7350 30 0000 C CNN +F 2 "" H 5000 7250 60 0000 C CNN +F 3 "" H 5000 7250 60 0000 C CNN + 1 5000 7250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 8 1 00000000 +P 6350 7500 +F 0 "U1" V 6400 7400 30 0000 R CNN +F 1 "PORT" V 6300 7400 30 0000 R CNN +F 2 "" H 6350 7500 60 0000 C CNN +F 3 "" H 6350 7500 60 0000 C CNN + 8 6350 7500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 9 1 00000000 +P 7050 700 +F 0 "U1" V 7050 800 30 0000 L CNN +F 1 "PORT" V 7150 800 30 0000 L CNN +F 2 "" H 7050 700 60 0000 C CNN +F 3 "" H 7050 700 60 0000 C CNN + 9 7050 700 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 10 1 00000000 +P 8400 1000 +F 0 "U1" V 8400 1100 30 0000 L CNN +F 1 "PORT" V 8500 1100 30 0000 L CNN +F 2 "" H 8400 1000 60 0000 C CNN +F 3 "" H 8400 1000 60 0000 C CNN + 10 8400 1000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 14 1 00000000 +P 8550 6950 +F 0 "U1" V 8600 6850 30 0000 R CNN +F 1 "PORT" V 8500 6850 30 0000 R CNN +F 2 "" H 8550 6950 60 0000 C CNN +F 3 "" H 8550 6950 60 0000 C CNN + 14 8550 6950 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 6 1 00000000 +P 10650 2800 +F 0 "U1" V 10650 2900 30 0000 L CNN +F 1 "PORT" V 10750 2900 30 0000 L CNN +F 2 "" H 10650 2800 60 0000 C CNN +F 3 "" H 10650 2800 60 0000 C CNN + 6 10650 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 5 1 00000000 +P 10650 4550 +F 0 "U1" V 10650 4650 30 0000 L CNN +F 1 "PORT" V 10750 4650 30 0000 L CNN +F 2 "" H 10650 4550 60 0000 C CNN +F 3 "" H 10650 4550 60 0000 C CNN + 5 10650 4550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D1 +U 1 1 00000000 +P 2500 5500 +F 0 "D1" V 2452 5650 50 0000 L CNN +F 1 "eSim_Diode" V 2552 5650 50 0000 L CNN +F 2 "" H 2500 5500 60 0000 C CNN +F 3 "" H 2500 5500 60 0000 C CNN + 1 2500 5500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D2 +U 1 1 00000000 +P 3550 2700 +F 0 "D2" H 3552 3000 50 0000 C CNN +F 1 "eSim_Diode" H 3552 2900 50 0000 C CNN +F 2 "" H 3550 2700 60 0000 C CNN +F 3 "" H 3550 2700 60 0000 C CNN + 1 3550 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D3 +U 1 1 00000000 +P 8050 2700 +F 0 "D3" H 8052 3000 50 0000 C CNN +F 1 "eSim_Diode" H 8052 2900 50 0000 C CNN +F 2 "" H 8050 2700 60 0000 C CNN +F 3 "" H 8050 2700 60 0000 C CNN + 1 8050 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D4 +U 1 1 00000000 +P 9100 5500 +F 0 "D4" V 9052 5650 50 0000 L CNN +F 1 "eSim_Diode" V 9152 5650 50 0000 L CNN +F 2 "" H 9100 5500 60 0000 C CNN +F 3 "" H 9100 5500 60 0000 C CNN + 1 9100 5500 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Analog:zener U2 +U 1 1 00000000 +P 3500 4500 +F 0 "U2" V 3625 4350 60 0000 R CNN +F 1 "zener" V 3475 4350 60 0000 R CNN +F 2 "" H 3550 4500 60 0000 C CNN +F 3 "" H 3550 4500 60 0000 C CNN + 1 3500 4500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Analog:zener U3 +U 1 1 00000000 +P 4550 2250 +F 0 "U3" V 4575 2400 60 0000 L CNN +F 1 "zener" V 4725 2400 60 0000 L CNN +F 2 "" H 4600 2250 60 0000 C CNN +F 3 "" H 4600 2250 60 0000 C CNN + 1 4550 2250 + 0 1 1 0 +$EndComp +$Comp +L eSim_Analog:zener U4 +U 1 1 00000000 +P 4900 4000 +F 0 "U4" V 5025 3850 60 0000 R CNN +F 1 "zener" V 4875 3850 60 0000 R CNN +F 2 "" H 4950 4000 60 0000 C CNN +F 3 "" H 4950 4000 60 0000 C CNN + 1 4900 4000 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Analog:zener U5 +U 1 1 00000000 +P 6700 4000 +F 0 "U5" V 6825 3850 60 0000 R CNN +F 1 "zener" V 6675 3850 60 0000 R CNN +F 2 "" H 6750 4000 60 0000 C CNN +F 3 "" H 6750 4000 60 0000 C CNN + 1 6700 4000 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Analog:zener U6 +U 1 1 00000000 +P 7050 2250 +F 0 "U6" V 7075 2400 60 0000 L CNN +F 1 "zener" V 7225 2400 60 0000 L CNN +F 2 "" H 7100 2250 60 0000 C CNN +F 3 "" H 7100 2250 60 0000 C CNN + 1 7050 2250 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Analog:zener U7 +U 1 1 00000000 +P 8100 4500 +F 0 "U7" V 8225 4350 60 0000 R CNN +F 1 "zener" V 8075 4350 60 0000 R CNN +F 2 "" H 8150 4500 60 0000 C CNN +F 3 "" H 8150 4500 60 0000 C CNN + 1 8100 4500 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q1 +U 1 1 00000000 +P 1300 4250 +F 0 "Q1" H 1500 4300 50 0000 L CNN +F 1 "eSim_NPN" H 1500 4200 50 0000 L CNN +F 2 "" H 1500 4350 29 0000 C CNN +F 3 "" H 1300 4250 60 0000 C CNN + 1 1300 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q2 +U 1 1 00000000 +P 1800 2700 +F 0 "Q2" H 2000 2750 50 0000 L CNN +F 1 "eSim_NPN" H 2000 2650 50 0000 L CNN +F 2 "" H 2000 2800 29 0000 C CNN +F 3 "" H 1800 2700 60 0000 C CNN + 1 1800 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q3 +U 1 1 00000000 +P 1900 5250 +F 0 "Q3" H 2100 5300 50 0000 L CNN +F 1 "eSim_NPN" H 2100 5200 50 0000 L CNN +F 2 "" H 2100 5350 29 0000 C CNN +F 3 "" H 1900 5250 60 0000 C CNN + 1 1900 5250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q4 +U 1 1 00000000 +P 2250 4250 +F 0 "Q4" H 2450 4300 50 0000 L CNN +F 1 "eSim_NPN" H 2450 4200 50 0000 L CNN +F 2 "" H 2450 4350 29 0000 C CNN +F 3 "" H 2250 4250 60 0000 C CNN + 1 2250 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q5 +U 1 1 00000000 +P 3100 3800 +F 0 "Q5" H 3300 3850 50 0000 L CNN +F 1 "eSim_NPN" H 3300 3750 50 0000 L CNN +F 2 "" H 3300 3900 29 0000 C CNN +F 3 "" H 3100 3800 60 0000 C CNN + 1 3100 3800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q6 +U 1 1 00000000 +P 4050 3800 +F 0 "Q6" H 4250 3850 50 0000 L CNN +F 1 "eSim_NPN" H 4250 3750 50 0000 L CNN +F 2 "" H 4250 3900 29 0000 C CNN +F 3 "" H 4050 3800 60 0000 C CNN + 1 4050 3800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q7 +U 1 1 00000000 +P 4800 3250 +F 0 "Q7" H 5000 3300 50 0000 L CNN +F 1 "eSim_NPN" H 5000 3200 50 0000 L CNN +F 2 "" H 5000 3350 29 0000 C CNN +F 3 "" H 4800 3250 60 0000 C CNN + 1 4800 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q8 +U 1 1 00000000 +P 4800 4800 +F 0 "Q8" H 5000 4850 50 0000 L CNN +F 1 "eSim_NPN" H 5000 4750 50 0000 L CNN +F 2 "" H 5000 4900 29 0000 C CNN +F 3 "" H 4800 4800 60 0000 C CNN + 1 4800 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q9 +U 1 1 00000000 +P 6800 3250 +F 0 "Q9" H 7000 3300 50 0000 L CNN +F 1 "eSim_NPN" H 7000 3200 50 0000 L CNN +F 2 "" H 7000 3350 29 0000 C CNN +F 3 "" H 6800 3250 60 0000 C CNN + 1 6800 3250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q10 +U 1 1 00000000 +P 6800 4800 +F 0 "Q10" H 7000 4850 50 0000 L CNN +F 1 "eSim_NPN" H 7000 4750 50 0000 L CNN +F 2 "" H 7000 4900 29 0000 C CNN +F 3 "" H 6800 4800 60 0000 C CNN + 1 6800 4800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q11 +U 1 1 00000000 +P 7550 3800 +F 0 "Q11" H 7750 3850 50 0000 L CNN +F 1 "eSim_NPN" H 7750 3750 50 0000 L CNN +F 2 "" H 7750 3900 29 0000 C CNN +F 3 "" H 7550 3800 60 0000 C CNN + 1 7550 3800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q12 +U 1 1 00000000 +P 8500 3800 +F 0 "Q12" H 8700 3850 50 0000 L CNN +F 1 "eSim_NPN" H 8700 3750 50 0000 L CNN +F 2 "" H 8700 3900 29 0000 C CNN +F 3 "" H 8500 3800 60 0000 C CNN + 1 8500 3800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q13 +U 1 1 00000000 +P 9350 4250 +F 0 "Q13" H 9550 4300 50 0000 L CNN +F 1 "eSim_NPN" H 9550 4200 50 0000 L CNN +F 2 "" H 9550 4350 29 0000 C CNN +F 3 "" H 9350 4250 60 0000 C CNN + 1 9350 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q14 +U 1 1 00000000 +P 9700 5250 +F 0 "Q14" H 9900 5300 50 0000 L CNN +F 1 "eSim_NPN" H 9900 5200 50 0000 L CNN +F 2 "" H 9900 5350 29 0000 C CNN +F 3 "" H 9700 5250 60 0000 C CNN + 1 9700 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q15 +U 1 1 00000000 +P 9800 2700 +F 0 "Q15" H 10000 2750 50 0000 L CNN +F 1 "eSim_NPN" H 10000 2650 50 0000 L CNN +F 2 "" H 10000 2800 29 0000 C CNN +F 3 "" H 9800 2700 60 0000 C CNN + 1 9800 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q16 +U 1 1 00000000 +P 10300 4250 +F 0 "Q16" H 10500 4300 50 0000 L CNN +F 1 "eSim_NPN" H 10500 4200 50 0000 L CNN +F 2 "" H 10500 4350 29 0000 C CNN +F 3 "" H 10300 4250 60 0000 C CNN + 1 10300 4250 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1514_sub/analysis b/library/SubcircuitLibrary/mc1514_sub/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir new file mode 100644 index 000000000..60ba1cb50 --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir @@ -0,0 +1,46 @@ +.title KiCad schematic +R14 Net-_R14-Pad1_ Net-_D4-Pad2_ 100 +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +U1 Net-_Q8-Pad1_ Net-_U1-Pad2_ Net-_Q2-Pad1_ unconnected-_U1-Pad4_ Net-_Q13-Pad2_ Net-_Q16-Pad2_ Net-_R2-Pad1_ Net-_Q10-Pad1_ Net-_U1-Pad9_ Net-_Q15-Pad1_ Net-_Q10-Pad2_ Net-_Q4-Pad2_ Net-_Q1-Pad2_ Net-_R14-Pad1_ PORT +Q13 Net-_Q12-Pad2_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +Q16 Net-_Q11-Pad2_ Net-_Q16-Pad2_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_Q13-Pad3_ Net-_D4-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R16 Net-_R14-Pad1_ Net-_Q14-Pad3_ 200 +U7 Net-_Q10-Pad2_ Net-_Q11-Pad3_ zener +R12 Net-_Q10-Pad3_ Net-_D4-Pad1_ 1k +R6 Net-_Q8-Pad3_ Net-_D1-Pad1_ 1k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_Q10-Pad2_ Net-_Q8-Pad3_ eSim_NPN +U2 Net-_Q10-Pad2_ Net-_Q5-Pad3_ zener +R5 Net-_D2-Pad1_ Net-_Q2-Pad1_ 3.7k +R7 Net-_D2-Pad2_ Net-_Q2-Pad1_ 2.8k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +R1 Net-_Q1-Pad1_ Net-_Q2-Pad3_ 740 +R3 Net-_Q4-Pad1_ Net-_Q2-Pad3_ 740 +Q5 Net-_D2-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q2-Pad2_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R8 Net-_Q2-Pad2_ Net-_D2-Pad2_ 1.1k +R17 Net-_Q11-Pad2_ Net-_Q15-Pad3_ 740 +R13 Net-_D3-Pad1_ Net-_Q15-Pad1_ 3.7k +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad1_ Net-_Q15-Pad3_ eSim_NPN +R15 Net-_Q12-Pad2_ Net-_Q15-Pad3_ 740 +R9 Net-_Q15-Pad1_ Net-_Q2-Pad1_ 47 +U4 Net-_Q8-Pad1_ Net-_Q7-Pad3_ zener +U5 Net-_Q10-Pad1_ Net-_Q9-Pad3_ zener +Q9 Net-_Q15-Pad1_ Net-_D3-Pad1_ Net-_Q9-Pad3_ eSim_NPN +Q7 Net-_Q2-Pad1_ Net-_D2-Pad1_ Net-_Q7-Pad3_ eSim_NPN +U3 Net-_U1-Pad2_ Net-_D2-Pad1_ zener +U6 Net-_U1-Pad9_ Net-_D3-Pad1_ zener +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q12 Net-_D3-Pad1_ Net-_Q12-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R10 Net-_D3-Pad2_ Net-_Q15-Pad1_ 2.8k +R11 Net-_Q11-Pad1_ Net-_D3-Pad2_ 1.1k +R4 Net-_R2-Pad1_ Net-_D1-Pad2_ 100 +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R2 Net-_R2-Pad1_ Net-_Q3-Pad3_ 200 +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +.end diff --git a/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir.out b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir.out new file mode 100644 index 000000000..1c0dd64cf --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.cir.out @@ -0,0 +1,75 @@ +.title kicad schematic + +.include D.lib +.include NPN.lib +r14 net-_r14-pad1_ net-_d4-pad2_ 100 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +* u1 net-_q8-pad1_ net-_u1-pad2_ net-_q2-pad1_ unconnected-_u1-pad4_ net-_q13-pad2_ net-_q16-pad2_ net-_r2-pad1_ net-_q10-pad1_ net-_u1-pad9_ net-_q15-pad1_ net-_q10-pad2_ net-_q4-pad2_ net-_q1-pad2_ net-_r14-pad1_ port +q13 net-_q12-pad2_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +q16 net-_q11-pad2_ net-_q16-pad2_ net-_q13-pad3_ Q2N2222 +q14 net-_q13-pad3_ net-_d4-pad1_ net-_q14-pad3_ Q2N2222 +r16 net-_r14-pad1_ net-_q14-pad3_ 200 +* u7 net-_q10-pad2_ net-_q11-pad3_ zener +r12 net-_q10-pad3_ net-_d4-pad1_ 1k +r6 net-_q8-pad3_ net-_d1-pad1_ 1k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +* u2 net-_q10-pad2_ net-_q5-pad3_ zener +r5 net-_d2-pad1_ net-_q2-pad1_ 3.7k +r7 net-_d2-pad2_ net-_q2-pad1_ 2.8k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +r1 net-_q1-pad1_ net-_q2-pad3_ 740 +r3 net-_q4-pad1_ net-_q2-pad3_ 740 +q5 net-_d2-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q2-pad2_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222 +r8 net-_q2-pad2_ net-_d2-pad2_ 1.1k +r17 net-_q11-pad2_ net-_q15-pad3_ 740 +r13 net-_d3-pad1_ net-_q15-pad1_ 3.7k +q15 net-_q15-pad1_ net-_q11-pad1_ net-_q15-pad3_ Q2N2222 +r15 net-_q12-pad2_ net-_q15-pad3_ 740 +r9 net-_q15-pad1_ net-_q2-pad1_ 47 +* u4 net-_q8-pad1_ net-_q7-pad3_ zener +* u5 net-_q10-pad1_ net-_q9-pad3_ zener +q9 net-_q15-pad1_ net-_d3-pad1_ net-_q9-pad3_ Q2N2222 +q7 net-_q2-pad1_ net-_d2-pad1_ net-_q7-pad3_ Q2N2222 +* u3 net-_u1-pad2_ net-_d2-pad1_ zener +* u6 net-_u1-pad9_ net-_d3-pad1_ zener +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q12 net-_d3-pad1_ net-_q12-pad2_ net-_q11-pad3_ Q2N2222 +r10 net-_d3-pad2_ net-_q15-pad1_ 2.8k +r11 net-_q11-pad1_ net-_d3-pad2_ 1.1k +r4 net-_r2-pad1_ net-_d1-pad2_ 100 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_r2-pad1_ net-_q3-pad3_ 200 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +a1 net-_q10-pad2_ net-_q11-pad3_ u7 +a2 net-_q10-pad2_ net-_q5-pad3_ u2 +a3 net-_q8-pad1_ net-_q7-pad3_ u4 +a4 net-_q10-pad1_ net-_q9-pad3_ u5 +a5 net-_u1-pad2_ net-_d2-pad1_ u3 +a6 net-_u1-pad9_ net-_d3-pad1_ u6 +* Schematic Name: zener, Ngspice Name: zener +.model u7 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u4 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u5 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u3 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u6 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.kicad_sch b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.kicad_sch new file mode 100644 index 000000000..874692a6e --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.kicad_sch @@ -0,0 +1,2681 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 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(unit 1) (value "PORT") (footprint "") + ) + (path "/8d27c7a1-b3f6-4980-88b9-220172bf64da" + (reference "U1") (unit 2) (value "PORT") (footprint "") + ) + (path "/91f49481-52d9-477c-8c66-bddbe13614a8" + (reference "U1") (unit 3) (value "PORT") (footprint "") + ) + (path "/be08fbb1-c50e-41ff-ad66-90fbcb6e5a20" + (reference "U1") (unit 4) (value "PORT") (footprint "") + ) + (path "/ded167b4-da80-470e-a211-21d6654d9dc1" + (reference "U1") (unit 5) (value "PORT") (footprint "") + ) + (path "/0187a24e-3222-4228-a7cb-bde2258f5b7c" + (reference "U1") (unit 6) (value "PORT") (footprint "") + ) + (path "/7e2f1057-d119-455e-965a-846c184e7a98" + (reference "U1") (unit 7) (value "PORT") (footprint "") + ) + (path "/1f2f2a91-417d-4117-962e-612ca0c0721d" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + (path "/df5286b8-4f66-4725-98d5-02e854d79673" + (reference "U1") (unit 9) (value "PORT") (footprint "") + ) + (path "/845bed1d-ec49-4cb1-9f4c-0f59ce69b6f5" + (reference "U1") (unit 10) (value "PORT") (footprint "") + ) + (path "/a7bd4b6b-59a6-483e-8036-65475391a430" + (reference "U1") (unit 11) (value "PORT") (footprint "") + ) + (path "/b858214c-c164-437b-b746-e7b178ea5928" + (reference "U1") (unit 12) (value "PORT") (footprint "") + ) + (path "/c2e8b923-62d7-4052-a0dc-9592085d3b0d" + (reference "U1") (unit 13) (value "PORT") (footprint "") + ) + (path "/18c75618-c7b2-4efa-bb6c-486b76ddf237" + (reference "U1") (unit 14) (value "PORT") (footprint "") + ) + (path "/db800393-5930-4e12-9f21-cbbe54c500a2" + (reference "U2") (unit 1) (value "zener") (footprint "") + ) + (path "/97f97fa1-7061-40ea-8317-5762f4d95da2" + (reference "U3") (unit 1) (value "zener") (footprint "") + ) + (path "/9872d6be-dbc7-4f64-b1a3-a941c0baba65" + (reference "U4") (unit 1) (value "zener") (footprint "") + ) + (path "/7887a429-0121-4278-84e9-a497f267eb91" + (reference "U5") (unit 1) (value "zener") (footprint "") + ) + (path "/5c24c021-afeb-4e89-b462-45e8761e7c84" + (reference "U6") (unit 1) (value "zener") (footprint "") + ) + (path "/df970d47-1c0e-4d4d-a479-ebff76c9eeaa" + (reference "U7") (unit 1) (value "zener") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.sub b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.sub new file mode 100644 index 000000000..a24a87d3c --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub.sub @@ -0,0 +1,69 @@ +* Subcircuit mc1514_sub +.subckt mc1514_sub net-_q8-pad1_ net-_u1-pad2_ net-_q2-pad1_ unconnected-_u1-pad4_ net-_q13-pad2_ net-_q16-pad2_ net-_r2-pad1_ net-_q10-pad1_ net-_u1-pad9_ net-_q15-pad1_ net-_q10-pad2_ net-_q4-pad2_ net-_q1-pad2_ net-_r14-pad1_ +.title kicad schematic +.include D.lib +.include NPN.lib +r14 net-_r14-pad1_ net-_d4-pad2_ 100 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q13 net-_q12-pad2_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +q16 net-_q11-pad2_ net-_q16-pad2_ net-_q13-pad3_ Q2N2222 +q14 net-_q13-pad3_ net-_d4-pad1_ net-_q14-pad3_ Q2N2222 +r16 net-_r14-pad1_ net-_q14-pad3_ 200 +* u7 net-_q10-pad2_ net-_q11-pad3_ zener +r12 net-_q10-pad3_ net-_d4-pad1_ 1k +r6 net-_q8-pad3_ net-_d1-pad1_ 1k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +* u2 net-_q10-pad2_ net-_q5-pad3_ zener +r5 net-_d2-pad1_ net-_q2-pad1_ 3.7k +r7 net-_d2-pad2_ net-_q2-pad1_ 2.8k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +r1 net-_q1-pad1_ net-_q2-pad3_ 740 +r3 net-_q4-pad1_ net-_q2-pad3_ 740 +q5 net-_d2-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q2-pad2_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222 +r8 net-_q2-pad2_ net-_d2-pad2_ 1.1k +r17 net-_q11-pad2_ net-_q15-pad3_ 740 +r13 net-_d3-pad1_ net-_q15-pad1_ 3.7k +q15 net-_q15-pad1_ net-_q11-pad1_ net-_q15-pad3_ Q2N2222 +r15 net-_q12-pad2_ net-_q15-pad3_ 740 +r9 net-_q15-pad1_ net-_q2-pad1_ 47 +* u4 net-_q8-pad1_ net-_q7-pad3_ zener +* u5 net-_q10-pad1_ net-_q9-pad3_ zener +q9 net-_q15-pad1_ net-_d3-pad1_ net-_q9-pad3_ Q2N2222 +q7 net-_q2-pad1_ net-_d2-pad1_ net-_q7-pad3_ Q2N2222 +* u3 net-_u1-pad2_ net-_d2-pad1_ zener +* u6 net-_u1-pad9_ net-_d3-pad1_ zener +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q12 net-_d3-pad1_ net-_q12-pad2_ net-_q11-pad3_ Q2N2222 +r10 net-_d3-pad2_ net-_q15-pad1_ 2.8k +r11 net-_q11-pad1_ net-_d3-pad2_ 1.1k +r4 net-_r2-pad1_ net-_d1-pad2_ 100 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_r2-pad1_ net-_q3-pad3_ 200 +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +a1 net-_q10-pad2_ net-_q11-pad3_ u7 +a2 net-_q10-pad2_ net-_q5-pad3_ u2 +a3 net-_q8-pad1_ net-_q7-pad3_ u4 +a4 net-_q10-pad1_ net-_q9-pad3_ u5 +a5 net-_u1-pad2_ net-_d2-pad1_ u3 +a6 net-_u1-pad9_ net-_d3-pad1_ u6 +* Schematic Name: zener, Ngspice Name: zener +.model u7 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u2 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u4 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u5 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u3 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, Ngspice Name: zener +.model u6 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends mc1514_sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1514_sub/mc1514_sub_Previous_Values.xml b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub_Previous_Values.xml new file mode 100644 index 000000000..05c2f3b67 --- /dev/null +++ b/library/SubcircuitLibrary/mc1514_sub/mc1514_sub_Previous_Values.xml @@ -0,0 +1 @@ +zener6.2zener6.2zener6.2zener6.2zener6.2zener6.2D:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file From 6ee65984bc97b4e0521411ca3d68231859af84b0 Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:38:17 +0530 Subject: [PATCH 07/10] CA3094 is an operational transconductance amplifier (OTA) with buffer. --- library/SubcircuitLibrary/ca3094/D.lib | 2 + library/SubcircuitLibrary/ca3094/NPN.lib | 4 + library/SubcircuitLibrary/ca3094/PNP.lib | 4 + .../ca3094/_autosave-ca3094.sch | 531 ++++++ library/SubcircuitLibrary/ca3094/analysis | 1 + library/SubcircuitLibrary/ca3094/ca3094.cir | 24 + .../SubcircuitLibrary/ca3094/ca3094.cir.out | 36 + .../SubcircuitLibrary/ca3094/ca3094.kicad_sch | 1673 +++++++++++++++++ library/SubcircuitLibrary/ca3094/ca3094.sub | 30 + .../ca3094/ca3094_Previous_Values.xml | 1 + 10 files changed, 2306 insertions(+) create mode 100644 library/SubcircuitLibrary/ca3094/D.lib create mode 100644 library/SubcircuitLibrary/ca3094/NPN.lib create mode 100644 library/SubcircuitLibrary/ca3094/PNP.lib create mode 100644 library/SubcircuitLibrary/ca3094/_autosave-ca3094.sch create mode 100644 library/SubcircuitLibrary/ca3094/analysis create mode 100644 library/SubcircuitLibrary/ca3094/ca3094.cir create mode 100644 library/SubcircuitLibrary/ca3094/ca3094.cir.out create mode 100644 library/SubcircuitLibrary/ca3094/ca3094.kicad_sch create mode 100644 library/SubcircuitLibrary/ca3094/ca3094.sub create mode 100644 library/SubcircuitLibrary/ca3094/ca3094_Previous_Values.xml diff --git a/library/SubcircuitLibrary/ca3094/D.lib b/library/SubcircuitLibrary/ca3094/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ca3094/NPN.lib b/library/SubcircuitLibrary/ca3094/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ca3094/PNP.lib b/library/SubcircuitLibrary/ca3094/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/ca3094/_autosave-ca3094.sch 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+Wire Wire Line + 7350 4950 7350 5350 +Wire Wire Line + 7350 5350 8050 5350 +Wire Wire Line + 8050 3950 8550 3950 +Wire Wire Line + 8050 4250 8050 3950 +Wire Wire Line + 8050 4650 8050 5350 +Wire Wire Line + 8050 5350 8500 5350 +$Comp +L eSim_Devices:resistor R1 +U 1 1 00000000 +P 7400 2100 +F 0 "R1" V 7500 2050 50 0000 R CNN +F 1 "2k" V 7400 2050 50 0000 R CNN +F 2 "" H 7450 2080 30 0000 C CNN +F 3 "" V 7450 2150 30 0000 C CNN + 1 7400 2100 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Devices:resistor R2 +U 1 1 00000000 +P 7400 4850 +F 0 "R2" V 7500 4800 50 0000 R CNN +F 1 "47k" V 7400 4800 50 0000 R CNN +F 2 "" H 7450 4830 30 0000 C CNN +F 3 "" V 7450 4900 30 0000 C CNN + 1 7400 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 2 1 00000000 +P 1850 3750 +F 0 "U1" H 1875 3950 30 0000 C CNN +F 1 "PORT" H 1875 3850 30 0000 C CNN +F 2 "" H 1850 3750 60 0000 C CNN +F 3 "" H 1850 3750 60 0000 C CNN + 2 1850 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 3 1 00000000 +P 2050 4450 +F 0 "U1" H 2075 4650 30 0000 C CNN +F 1 "PORT" H 2075 4550 30 0000 C CNN +F 2 "" H 2050 4450 60 0000 C CNN +F 3 "" H 2050 4450 60 0000 C CNN + 3 2050 4450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 5 1 00000000 +P 2050 5150 +F 0 "U1" H 2075 5350 30 0000 C CNN +F 1 "PORT" H 2075 5250 30 0000 C CNN +F 2 "" H 2050 5150 60 0000 C CNN +F 3 "" H 2050 5150 60 0000 C CNN + 5 2050 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 1 1 00000000 +P 6800 900 +F 0 "U1" V 6800 1000 30 0000 L CNN +F 1 "PORT" V 6900 1000 30 0000 L CNN +F 2 "" H 6800 900 60 0000 C CNN +F 3 "" H 6800 900 60 0000 C CNN + 1 6800 900 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 4 1 00000000 +P 7100 6150 +F 0 "U1" H 6950 6125 30 0000 R CNN +F 1 "PORT" H 6950 6225 30 0000 R CNN +F 2 "" H 7100 6150 60 0000 C CNN +F 3 "" H 7100 6150 60 0000 C CNN + 4 7100 6150 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 7 1 00000000 +P 7350 950 +F 0 "U1" V 7350 1050 30 0000 L CNN +F 1 "PORT" V 7450 1050 30 0000 L CNN +F 2 "" H 7350 950 60 0000 C CNN +F 3 "" H 7350 950 60 0000 C CNN + 7 7350 950 + 0 1 1 0 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 6 1 00000000 +P 8750 5350 +F 0 "U1" H 8600 5325 30 0000 R CNN +F 1 "PORT" H 8600 5425 30 0000 R CNN +F 2 "" H 8750 5350 60 0000 C CNN +F 3 "" H 8750 5350 60 0000 C CNN + 6 8750 5350 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 8 1 00000000 +P 8800 3950 +F 0 "U1" H 8650 3925 30 0000 R CNN +F 1 "PORT" H 8650 4025 30 0000 R CNN +F 2 "" H 8800 3950 60 0000 C CNN +F 3 "" H 8800 3950 60 0000 C CNN + 8 8800 3950 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D1 +U 1 1 00000000 +P 2800 5650 +F 0 "D1" V 2752 5800 50 0000 L CNN +F 1 "eSim_Diode" V 2852 5800 50 0000 L CNN +F 2 "" H 2800 5650 60 0000 C CNN +F 3 "" H 2800 5650 60 0000 C CNN + 1 2800 5650 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D2 +U 1 1 00000000 +P 3050 2550 +F 0 "D2" H 3052 2850 50 0000 C CNN +F 1 "eSim_Diode" H 3052 2750 50 0000 C CNN +F 2 "" H 3050 2550 60 0000 C CNN +F 3 "" H 3050 2550 60 0000 C CNN + 1 3050 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D3 +U 1 1 00000000 +P 3900 1700 +F 0 "D3" V 3852 1850 50 0000 L CNN +F 1 "eSim_Diode" V 3952 1850 50 0000 L CNN +F 2 "" H 3900 1700 60 0000 C CNN +F 3 "" H 3900 1700 60 0000 C CNN + 1 3900 1700 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D4 +U 1 1 00000000 +P 5200 2700 +F 0 "D4" H 5202 3000 50 0000 C CNN +F 1 "eSim_Diode" H 5202 2900 50 0000 C CNN +F 2 "" H 5200 2700 60 0000 C CNN +F 3 "" H 5200 2700 60 0000 C CNN + 1 5200 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D5 +U 1 1 00000000 +P 5550 5750 +F 0 "D5" V 5502 5900 50 0000 L CNN +F 1 "eSim_Diode" V 5602 5900 50 0000 L CNN +F 2 "" H 5550 5750 60 0000 C CNN +F 3 "" H 5550 5750 60 0000 C CNN + 1 5550 5750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_Diode D6 +U 1 1 00000000 +P 6200 1850 +F 0 "D6" V 6152 2000 50 0000 L CNN +F 1 "eSim_Diode" V 6252 2000 50 0000 L CNN +F 2 "" H 6200 1850 60 0000 C CNN +F 3 "" H 6200 1850 60 0000 C CNN + 1 6200 1850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q1 +U 1 1 00000000 +P 2450 3750 +F 0 "Q1" H 2650 3800 50 0000 L CNN +F 1 "eSim_NPN" H 2650 3700 50 0000 L CNN +F 2 "" H 2650 3850 29 0000 C CNN +F 3 "" H 2450 3750 60 0000 C CNN + 1 2450 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q2 +U 1 1 00000000 +P 2650 2250 +F 0 "Q2" H 2850 2200 50 0000 L CNN +F 1 "eSim_PNP" H 2850 2300 50 0000 L CNN +F 2 "" H 2850 2350 29 0000 C CNN +F 3 "" H 2650 2250 60 0000 C CNN + 1 2650 2250 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q3 +U 1 1 00000000 +P 3200 5150 +F 0 "Q3" H 3400 5200 50 0000 L CNN +F 1 "eSim_NPN" H 3400 5100 50 0000 L CNN +F 2 "" H 3400 5250 29 0000 C CNN +F 3 "" H 3200 5150 60 0000 C CNN + 1 3200 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q4 +U 1 1 00000000 +P 3250 3050 +F 0 "Q4" H 3450 3000 50 0000 L CNN +F 1 "eSim_PNP" H 3450 3100 50 0000 L CNN +F 2 "" H 3450 3150 29 0000 C CNN +F 3 "" H 3250 3050 60 0000 C CNN + 1 3250 3050 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q5 +U 1 1 00000000 +P 3400 3750 +F 0 "Q5" H 3600 3800 50 0000 L CNN +F 1 "eSim_NPN" H 3600 3700 50 0000 L CNN +F 2 "" H 3600 3850 29 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q6 +U 1 1 00000000 +P 3800 2550 +F 0 "Q6" H 4000 2500 50 0000 L CNN +F 1 "eSim_PNP" H 4000 2600 50 0000 L CNN +F 2 "" H 4000 2650 29 0000 C CNN +F 3 "" H 3800 2550 60 0000 C CNN + 1 3800 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q7 +U 1 1 00000000 +P 4850 2350 +F 0 "Q7" H 5050 2300 50 0000 L CNN +F 1 "eSim_PNP" H 5050 2400 50 0000 L CNN +F 2 "" H 5050 2450 29 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 1 4850 2350 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q8 +U 1 1 00000000 +P 5250 5150 +F 0 "Q8" H 5450 5200 50 0000 L CNN +F 1 "eSim_NPN" H 5450 5100 50 0000 L CNN +F 2 "" H 5450 5250 29 0000 C CNN +F 3 "" H 5250 5150 60 0000 C CNN + 1 5250 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q9 +U 1 1 00000000 +P 5450 4300 +F 0 "Q9" H 5650 4350 50 0000 L CNN +F 1 "eSim_NPN" H 5650 4250 50 0000 L CNN +F 2 "" H 5650 4400 29 0000 C CNN +F 3 "" H 5450 4300 60 0000 C CNN + 1 5450 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q10 +U 1 1 00000000 +P 5550 3400 +F 0 "Q10" H 5750 3350 50 0000 L CNN +F 1 "eSim_PNP" H 5750 3450 50 0000 L CNN +F 2 "" H 5750 3500 29 0000 C CNN +F 3 "" H 5550 3400 60 0000 C CNN + 1 5550 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q11 +U 1 1 00000000 +P 6100 2700 +F 0 "Q11" H 6300 2650 50 0000 L CNN +F 1 "eSim_PNP" H 6300 2750 50 0000 L CNN +F 2 "" H 6300 2800 29 0000 C CNN +F 3 "" H 6100 2700 60 0000 C CNN + 1 6100 2700 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q12 +U 1 1 00000000 +P 7250 3900 +F 0 "Q12" H 7450 3950 50 0000 L CNN +F 1 "eSim_NPN" H 7450 3850 50 0000 L CNN +F 2 "" H 7450 4000 29 0000 C CNN +F 3 "" H 7250 3900 60 0000 C CNN + 1 7250 3900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q13 +U 1 1 00000000 +P 7950 4450 +F 0 "Q13" H 8150 4500 50 0000 L CNN +F 1 "eSim_NPN" H 8150 4400 50 0000 L CNN +F 2 "" H 8150 4550 29 0000 C CNN +F 3 "" H 7950 4450 60 0000 C CNN + 1 7950 4450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ca3094/analysis b/library/SubcircuitLibrary/ca3094/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3094/ca3094.cir b/library/SubcircuitLibrary/ca3094/ca3094.cir new file mode 100644 index 000000000..b652e673d --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/ca3094.cir @@ -0,0 +1,24 @@ +.title KiCad schematic +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 Net-_Q4-Pad1_ Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_PNP +Q7 Net-_D4-Pad1_ Net-_D6-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q2 Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D3-Pad1_ eSim_PNP +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_Q4-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_PNP +U1 Net-_Q10-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q13-Pad3_ Net-_D3-Pad1_ Net-_Q13-Pad1_ PORT +Q5 Net-_D4-Pad1_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q1 Net-_D2-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q8 Net-_Q4-Pad1_ Net-_D5-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q9 Net-_Q10-Pad1_ Net-_Q4-Pad1_ Net-_D5-Pad1_ eSim_NPN +D5 Net-_D5-Pad1_ Net-_D1-Pad2_ eSim_Diode +R2 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 47k +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad3_ Net-_Q13-Pad3_ eSim_NPN +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +R1 Net-_Q12-Pad1_ Net-_D3-Pad1_ 2k +D6 Net-_D3-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q10 Net-_Q10-Pad1_ Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q11 Net-_Q10-Pad1_ Net-_D4-Pad2_ Net-_D6-Pad2_ eSim_PNP +.end diff --git a/library/SubcircuitLibrary/ca3094/ca3094.cir.out b/library/SubcircuitLibrary/ca3094/ca3094.cir.out new file mode 100644 index 000000000..6ee564771 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/ca3094.cir.out @@ -0,0 +1,36 @@ +.title kicad schematic + +.include PNP.lib +.include NPN.lib +.include D.lib +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q4-pad1_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d6-pad2_ net-_d3-pad1_ Q2N2907A +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +* u1 net-_q10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q13-pad3_ net-_d3-pad1_ net-_q13-pad1_ port +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q4-pad1_ net-_d5-pad1_ net-_d1-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222 +q9 net-_q10-pad1_ net-_q4-pad1_ net-_d5-pad1_ Q2N2222 +d5 net-_d5-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_q13-pad3_ net-_q12-pad3_ 47k +q13 net-_q13-pad1_ net-_q12-pad3_ net-_q13-pad3_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +r1 net-_q12-pad1_ net-_d3-pad1_ 2k +d6 net-_d3-pad1_ net-_d6-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q11 net-_q10-pad1_ net-_d4-pad2_ net-_d6-pad2_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ca3094/ca3094.kicad_sch b/library/SubcircuitLibrary/ca3094/ca3094.kicad_sch new file mode 100644 index 000000000..e79caa568 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/ca3094.kicad_sch @@ -0,0 +1,1673 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 68ad1443-79b6-499a-975a-44db83336092) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Devices:eSim_Diode" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (property "Reference" "D" (id 0) (at 0 2.54 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "eSim_Diode" (id 1) (at 0 -2.54 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "ki_fp_filters" "TO-???* *SingleDiode *_Diode_* *SingleDiode* D_*" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "eSim_Diode_0_0" + (text "A" (at -2.54 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (text "K" (at 2.54 1.27 0) + (effects (font (size 1.524 1.524))) + ) + ) + (symbol "eSim_Diode_0_1" + (polyline + (pts + (xy 1.27 1.27) + (xy 1.27 -1.27) + ) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -1.27 1.27) + (xy 1.27 0) + (xy -1.27 -1.27) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type outline)) + ) + ) + (symbol "eSim_Diode_1_1" + (pin passive line (at -3.81 0 0) (length 2.54) + (name "A" (effects (font (size 1.016 1.016)))) + (number "1" (effects (font (size 1.016 1.016)))) + ) + (pin passive line (at 3.81 0 180) (length 2.54) + (name "K" (effects (font (size 1.016 1.016)))) + (number "2" (effects (font (size 1.016 1.016)))) + ) + ) + ) + (symbol "eSim_Devices:eSim_NPN" (pin_names (offset 0) hide) (in_bom yes) (on_board yes) + (property "Reference" "Q" (id 0) (at -2.54 1.27 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Value" "eSim_NPN" (id 1) (at -1.27 3.81 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Footprint" "" (id 2) (at 5.08 2.54 0) + (effects (font (size 0.7366 0.7366))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "eSim_NPN_0_1" + (polyline + (pts + (xy 0.635 0.635) + (xy 2.54 2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0.635 -0.635) + (xy 2.54 -2.54) + (xy 2.54 -2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0.635 1.905) + (xy 0.635 -1.905) + (xy 0.635 -1.905) + ) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 -1.778) + (xy 1.778 -1.27) + (xy 2.286 -2.286) + (xy 1.27 -1.778) + (xy 1.27 -1.778) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type outline)) + ) + (circle (center 1.27 0) (radius 2.8194) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "eSim_NPN_1_1" + (pin passive line (at 2.54 5.08 270) (length 2.54) + (name "C" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 0 0) (length 5.715) + (name "B" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 2.54 -5.08 90) (length 2.54) + (name "E" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "eSim_Devices:eSim_PNP" (pin_names (offset 0) hide) (in_bom yes) (on_board yes) + (property "Reference" "Q" (id 0) (at -2.54 1.27 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Value" "eSim_PNP" (id 1) (at -1.27 3.81 0) + (effects (font (size 1.27 1.27)) (justify right)) + ) + (property "Footprint" "" (id 2) (at 5.08 2.54 0) + (effects (font (size 0.7366 0.7366))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "eSim_PNP_0_1" + (polyline + (pts + (xy 0.635 0.635) + (xy 2.54 2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0.635 -0.635) + (xy 2.54 -2.54) + (xy 2.54 -2.54) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0.635 1.905) + (xy 0.635 -1.905) + (xy 0.635 -1.905) + ) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.286 -1.778) + (xy 1.778 -2.286) + (xy 1.27 -1.27) + (xy 2.286 -1.778) + (xy 2.286 -1.778) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type outline)) + ) + (circle (center 1.27 0) (radius 2.8194) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "eSim_PNP_1_1" + (pin passive line (at 2.54 5.08 270) (length 2.54) + (name "C" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 0 0) (length 5.715) + (name "B" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 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(footprint "") + ) + (path "/fb92dc0c-46af-4f3a-a7bc-d53acdf1749f" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/ca3094/ca3094.sub b/library/SubcircuitLibrary/ca3094/ca3094.sub new file mode 100644 index 000000000..528939b10 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/ca3094.sub @@ -0,0 +1,30 @@ +* Subcircuit ca3094 +.subckt ca3094 net-_q10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q13-pad3_ net-_d3-pad1_ net-_q13-pad1_ +.title kicad schematic +.include PNP.lib +.include NPN.lib +.include D.lib +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q4-pad1_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d6-pad2_ net-_d3-pad1_ Q2N2907A +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q4-pad1_ net-_d5-pad1_ net-_d1-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222 +q9 net-_q10-pad1_ net-_q4-pad1_ net-_d5-pad1_ Q2N2222 +d5 net-_d5-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_q13-pad3_ net-_q12-pad3_ 47k +q13 net-_q13-pad1_ net-_q12-pad3_ net-_q13-pad3_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +r1 net-_q12-pad1_ net-_d3-pad1_ 2k +d6 net-_d3-pad1_ net-_d6-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q11 net-_q10-pad1_ net-_d4-pad2_ net-_d6-pad2_ Q2N2907A +* Control Statements + +.ends ca3094 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3094/ca3094_Previous_Values.xml b/library/SubcircuitLibrary/ca3094/ca3094_Previous_Values.xml new file mode 100644 index 000000000..7d49ae4e8 --- /dev/null +++ b/library/SubcircuitLibrary/ca3094/ca3094_Previous_Values.xml @@ -0,0 +1 @@ +D:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libD:\hdl\eSIM\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file From 4230c95ba641e2fec0756aac290cd8e8b0f7b281 Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:39:52 +0530 Subject: [PATCH 08/10] 74HC377 is an octal D-type flip-flop with clock enable --- library/SubcircuitLibrary/74hc377/74hc377.cir | 69 + .../SubcircuitLibrary/74hc377/74hc377.cir.out | 276 ++ .../74hc377/74hc377.kicad_sch | 3623 +++++++++++++++++ library/SubcircuitLibrary/74hc377/74hc377.sub | 270 ++ .../74hc377/74hc377_Previous_Values.xml | 1 + .../74hc377/_autosave-74hc377.sch | 1349 ++++++ library/SubcircuitLibrary/74hc377/analysis | 1 + 7 files changed, 5589 insertions(+) create mode 100644 library/SubcircuitLibrary/74hc377/74hc377.cir create mode 100644 library/SubcircuitLibrary/74hc377/74hc377.cir.out create mode 100644 library/SubcircuitLibrary/74hc377/74hc377.kicad_sch create mode 100644 library/SubcircuitLibrary/74hc377/74hc377.sub create mode 100644 library/SubcircuitLibrary/74hc377/74hc377_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74hc377/_autosave-74hc377.sch create mode 100644 library/SubcircuitLibrary/74hc377/analysis diff --git a/library/SubcircuitLibrary/74hc377/74hc377.cir b/library/SubcircuitLibrary/74hc377/74hc377.cir new file mode 100644 index 000000000..0ddd8f277 --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/74hc377.cir @@ -0,0 +1,69 @@ +.title KiCad schematic +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ unconnected-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ unconnected-_U1-Pad20_ PORT +U37 Net-_U1-Pad13_ Net-_U35-Pad1_ d_buffer +U33 Net-_U13-Pad2_ Net-_U33-Pad2_ d_inverter +U41 Net-_U13-Pad2_ Net-_U41-Pad2_ d_inverter +U30 Net-_U1-Pad8_ Net-_U28-Pad1_ d_buffer +U47 Net-_U47-Pad1_ Net-_U43-Pad3_ Net-_U47-Pad3_ d_or +U65 Net-_U65-Pad1_ Net-_U64-Pad2_ Net-_U61-Pad1_ d_and +U64 Net-_U13-Pad2_ Net-_U64-Pad2_ d_inverter +U61 Net-_U61-Pad1_ Net-_U59-Pad3_ Net-_U61-Pad3_ d_or +U53 Net-_U53-Pad1_ Net-_U51-Pad3_ Net-_U53-Pad3_ d_or +U57 Net-_U57-Pad1_ Net-_U56-Pad2_ Net-_U53-Pad1_ d_and +U51 Net-_U51-Pad1_ Net-_U13-Pad2_ Net-_U51-Pad3_ d_and +U42 Net-_U40-Pad5_ Net-_U41-Pad2_ Net-_U39-Pad1_ d_and +U43 Net-_U43-Pad1_ Net-_U13-Pad2_ Net-_U43-Pad3_ d_and +U35 Net-_U35-Pad1_ Net-_U13-Pad2_ Net-_U35-Pad3_ d_and +U34 Net-_U32-Pad5_ Net-_U33-Pad2_ Net-_U31-Pad1_ d_and +U28 Net-_U28-Pad1_ Net-_U13-Pad2_ Net-_U28-Pad3_ d_and +U31 Net-_U31-Pad1_ Net-_U28-Pad3_ Net-_U31-Pad3_ d_or +U39 Net-_U39-Pad1_ Net-_U35-Pad3_ Net-_U39-Pad3_ d_or +U52 Net-_U1-Pad17_ Net-_U51-Pad1_ d_buffer +U44 Net-_U1-Pad14_ Net-_U43-Pad1_ d_buffer +U60 Net-_U1-Pad18_ Net-_U59-Pad1_ d_buffer +U59 Net-_U59-Pad1_ Net-_U13-Pad2_ Net-_U59-Pad3_ d_and +U56 Net-_U13-Pad2_ Net-_U56-Pad2_ d_inverter +U49 Net-_U49-Pad1_ Net-_U48-Pad2_ Net-_U47-Pad1_ d_and +U48 Net-_U13-Pad2_ Net-_U48-Pad2_ d_inverter +U40 Net-_U39-Pad3_ Net-_U38-Pad2_ unconnected-_U40-Pad3_ unconnected-_U40-Pad4_ Net-_U40-Pad5_ unconnected-_U40-Pad6_ d_dff +U32 Net-_U31-Pad3_ Net-_U29-Pad2_ unconnected-_U32-Pad3_ unconnected-_U32-Pad4_ Net-_U32-Pad5_ unconnected-_U32-Pad6_ d_dff +U29 Net-_U12-Pad1_ Net-_U29-Pad2_ d_inverter +U27 Net-_U24-Pad5_ Net-_U1-Pad6_ d_buffer +U36 Net-_U32-Pad5_ Net-_U1-Pad9_ d_buffer +U38 Net-_U12-Pad1_ Net-_U38-Pad2_ d_inverter +U55 Net-_U12-Pad1_ Net-_U55-Pad2_ d_inverter +U46 Net-_U12-Pad1_ Net-_U46-Pad2_ d_inverter +U50 Net-_U47-Pad3_ Net-_U46-Pad2_ unconnected-_U50-Pad3_ unconnected-_U50-Pad4_ Net-_U49-Pad1_ unconnected-_U50-Pad6_ d_dff +U58 Net-_U53-Pad3_ Net-_U55-Pad2_ unconnected-_U58-Pad3_ unconnected-_U58-Pad4_ Net-_U57-Pad1_ unconnected-_U58-Pad6_ d_dff +U66 Net-_U61-Pad3_ Net-_U63-Pad2_ unconnected-_U66-Pad3_ unconnected-_U66-Pad4_ Net-_U65-Pad1_ unconnected-_U66-Pad6_ d_dff +U63 Net-_U12-Pad1_ Net-_U63-Pad2_ d_inverter +U62 Net-_U57-Pad1_ Net-_U1-Pad16_ d_buffer +U67 Net-_U65-Pad1_ Net-_U1-Pad19_ d_buffer +U54 Net-_U49-Pad1_ Net-_U1-Pad15_ d_buffer +U45 Net-_U40-Pad5_ Net-_U1-Pad12_ d_buffer +U15 Net-_U15-Pad1_ Net-_U13-Pad3_ Net-_U15-Pad3_ d_or +U9 Net-_U13-Pad2_ Net-_U10-Pad2_ d_inverter +U5 Net-_U5-Pad1_ Net-_U13-Pad2_ Net-_U5-Pad3_ d_and +U18 Net-_U16-Pad5_ Net-_U17-Pad2_ Net-_U15-Pad1_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U17 Net-_U13-Pad2_ Net-_U17-Pad2_ d_inverter +U23 Net-_U23-Pad1_ Net-_U21-Pad3_ Net-_U23-Pad3_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U7 Net-_U10-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_or +U21 Net-_U21-Pad1_ Net-_U13-Pad2_ Net-_U21-Pad3_ d_and +U26 Net-_U24-Pad5_ Net-_U25-Pad2_ Net-_U23-Pad1_ d_and +U16 Net-_U15-Pad3_ Net-_U12-Pad2_ unconnected-_U16-Pad3_ unconnected-_U16-Pad4_ Net-_U16-Pad5_ unconnected-_U16-Pad6_ d_dff +U24 Net-_U23-Pad3_ Net-_U20-Pad2_ unconnected-_U24-Pad3_ unconnected-_U24-Pad4_ Net-_U24-Pad5_ unconnected-_U24-Pad6_ d_dff +U20 Net-_U12-Pad1_ Net-_U20-Pad2_ d_inverter +U19 Net-_U16-Pad5_ Net-_U1-Pad5_ d_buffer +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U8 Net-_U7-Pad3_ Net-_U3-Pad2_ unconnected-_U8-Pad3_ unconnected-_U8-Pad4_ Net-_U10-Pad1_ unconnected-_U8-Pad6_ d_dff +U4 Net-_U1-Pad11_ Net-_U12-Pad1_ d_inverter +U3 Net-_U12-Pad1_ Net-_U3-Pad2_ d_inverter +U11 Net-_U10-Pad1_ Net-_U1-Pad2_ d_buffer +U14 Net-_U1-Pad4_ Net-_U13-Pad1_ d_buffer +U22 Net-_U1-Pad7_ Net-_U21-Pad1_ d_buffer +U25 Net-_U13-Pad2_ Net-_U25-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U13-Pad2_ d_inverter +U6 Net-_U1-Pad3_ Net-_U5-Pad1_ d_buffer +.end diff --git a/library/SubcircuitLibrary/74hc377/74hc377.cir.out b/library/SubcircuitLibrary/74hc377/74hc377.cir.out new file mode 100644 index 000000000..7affcbdca --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/74hc377.cir.out @@ -0,0 +1,276 @@ +.title kicad schematic + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ unconnected-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ unconnected-_u1-pad20_ port +* u37 net-_u1-pad13_ net-_u35-pad1_ d_buffer +* u33 net-_u13-pad2_ net-_u33-pad2_ d_inverter +* u41 net-_u13-pad2_ net-_u41-pad2_ d_inverter +* u30 net-_u1-pad8_ net-_u28-pad1_ d_buffer +* u47 net-_u47-pad1_ net-_u43-pad3_ net-_u47-pad3_ d_or +* u65 net-_u65-pad1_ net-_u64-pad2_ net-_u61-pad1_ d_and +* u64 net-_u13-pad2_ net-_u64-pad2_ d_inverter +* u61 net-_u61-pad1_ net-_u59-pad3_ net-_u61-pad3_ d_or +* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u53-pad3_ d_or +* u57 net-_u57-pad1_ net-_u56-pad2_ net-_u53-pad1_ d_and +* u51 net-_u51-pad1_ net-_u13-pad2_ net-_u51-pad3_ d_and +* u42 net-_u40-pad5_ net-_u41-pad2_ net-_u39-pad1_ d_and +* u43 net-_u43-pad1_ net-_u13-pad2_ net-_u43-pad3_ d_and +* u35 net-_u35-pad1_ net-_u13-pad2_ net-_u35-pad3_ d_and +* u34 net-_u32-pad5_ net-_u33-pad2_ net-_u31-pad1_ d_and +* u28 net-_u28-pad1_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u31 net-_u31-pad1_ net-_u28-pad3_ net-_u31-pad3_ d_or +* u39 net-_u39-pad1_ net-_u35-pad3_ net-_u39-pad3_ d_or +* u52 net-_u1-pad17_ net-_u51-pad1_ d_buffer +* u44 net-_u1-pad14_ net-_u43-pad1_ d_buffer +* u60 net-_u1-pad18_ net-_u59-pad1_ d_buffer +* u59 net-_u59-pad1_ net-_u13-pad2_ net-_u59-pad3_ d_and +* u56 net-_u13-pad2_ net-_u56-pad2_ d_inverter +* u49 net-_u49-pad1_ net-_u48-pad2_ net-_u47-pad1_ d_and +* u48 net-_u13-pad2_ net-_u48-pad2_ d_inverter +* u40 net-_u39-pad3_ net-_u38-pad2_ unconnected-_u40-pad3_ unconnected-_u40-pad4_ net-_u40-pad5_ unconnected-_u40-pad6_ d_dff +* u32 net-_u31-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ unconnected-_u32-pad4_ net-_u32-pad5_ unconnected-_u32-pad6_ d_dff +* u29 net-_u12-pad1_ net-_u29-pad2_ d_inverter +* u27 net-_u24-pad5_ net-_u1-pad6_ d_buffer +* u36 net-_u32-pad5_ net-_u1-pad9_ d_buffer +* u38 net-_u12-pad1_ net-_u38-pad2_ d_inverter +* u55 net-_u12-pad1_ net-_u55-pad2_ d_inverter +* u46 net-_u12-pad1_ net-_u46-pad2_ d_inverter +* u50 net-_u47-pad3_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u49-pad1_ unconnected-_u50-pad6_ d_dff +* u58 net-_u53-pad3_ net-_u55-pad2_ unconnected-_u58-pad3_ unconnected-_u58-pad4_ net-_u57-pad1_ unconnected-_u58-pad6_ d_dff +* u66 net-_u61-pad3_ net-_u63-pad2_ unconnected-_u66-pad3_ unconnected-_u66-pad4_ net-_u65-pad1_ unconnected-_u66-pad6_ d_dff +* u63 net-_u12-pad1_ net-_u63-pad2_ d_inverter +* u62 net-_u57-pad1_ net-_u1-pad16_ d_buffer +* u67 net-_u65-pad1_ net-_u1-pad19_ d_buffer +* u54 net-_u49-pad1_ net-_u1-pad15_ d_buffer +* u45 net-_u40-pad5_ net-_u1-pad12_ d_buffer +* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u15-pad3_ d_or +* u9 net-_u13-pad2_ net-_u10-pad2_ d_inverter +* u5 net-_u5-pad1_ net-_u13-pad2_ net-_u5-pad3_ d_and +* u18 net-_u16-pad5_ net-_u17-pad2_ net-_u15-pad1_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u17 net-_u13-pad2_ net-_u17-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u21-pad3_ net-_u23-pad3_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u7 net-_u10-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_or +* u21 net-_u21-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and +* u26 net-_u24-pad5_ net-_u25-pad2_ net-_u23-pad1_ d_and +* u16 net-_u15-pad3_ net-_u12-pad2_ unconnected-_u16-pad3_ unconnected-_u16-pad4_ net-_u16-pad5_ unconnected-_u16-pad6_ d_dff +* u24 net-_u23-pad3_ net-_u20-pad2_ unconnected-_u24-pad3_ unconnected-_u24-pad4_ net-_u24-pad5_ unconnected-_u24-pad6_ d_dff +* u20 net-_u12-pad1_ net-_u20-pad2_ d_inverter +* u19 net-_u16-pad5_ net-_u1-pad5_ d_buffer +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u7-pad3_ net-_u3-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u10-pad1_ unconnected-_u8-pad6_ d_dff +* u4 net-_u1-pad11_ net-_u12-pad1_ d_inverter +* u3 net-_u12-pad1_ net-_u3-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u1-pad2_ d_buffer +* u14 net-_u1-pad4_ net-_u13-pad1_ d_buffer +* u22 net-_u1-pad7_ net-_u21-pad1_ d_buffer +* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u13-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u5-pad1_ d_buffer +a1 net-_u1-pad13_ net-_u35-pad1_ u37 +a2 net-_u13-pad2_ net-_u33-pad2_ u33 +a3 net-_u13-pad2_ net-_u41-pad2_ u41 +a4 net-_u1-pad8_ net-_u28-pad1_ u30 +a5 [net-_u47-pad1_ net-_u43-pad3_ ] net-_u47-pad3_ u47 +a6 [net-_u65-pad1_ net-_u64-pad2_ ] net-_u61-pad1_ u65 +a7 net-_u13-pad2_ net-_u64-pad2_ u64 +a8 [net-_u61-pad1_ net-_u59-pad3_ ] net-_u61-pad3_ u61 +a9 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u53-pad3_ u53 +a10 [net-_u57-pad1_ net-_u56-pad2_ ] net-_u53-pad1_ u57 +a11 [net-_u51-pad1_ net-_u13-pad2_ ] net-_u51-pad3_ u51 +a12 [net-_u40-pad5_ net-_u41-pad2_ ] net-_u39-pad1_ u42 +a13 [net-_u43-pad1_ net-_u13-pad2_ ] net-_u43-pad3_ u43 +a14 [net-_u35-pad1_ net-_u13-pad2_ ] net-_u35-pad3_ u35 +a15 [net-_u32-pad5_ net-_u33-pad2_ ] net-_u31-pad1_ u34 +a16 [net-_u28-pad1_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a17 [net-_u31-pad1_ net-_u28-pad3_ ] net-_u31-pad3_ u31 +a18 [net-_u39-pad1_ net-_u35-pad3_ ] net-_u39-pad3_ u39 +a19 net-_u1-pad17_ net-_u51-pad1_ u52 +a20 net-_u1-pad14_ net-_u43-pad1_ u44 +a21 net-_u1-pad18_ net-_u59-pad1_ u60 +a22 [net-_u59-pad1_ net-_u13-pad2_ ] net-_u59-pad3_ u59 +a23 net-_u13-pad2_ net-_u56-pad2_ u56 +a24 [net-_u49-pad1_ net-_u48-pad2_ ] net-_u47-pad1_ u49 +a25 net-_u13-pad2_ net-_u48-pad2_ u48 +a26 net-_u39-pad3_ net-_u38-pad2_ unconnected-_u40-pad3_ unconnected-_u40-pad4_ net-_u40-pad5_ unconnected-_u40-pad6_ u40 +a27 net-_u31-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ unconnected-_u32-pad4_ net-_u32-pad5_ unconnected-_u32-pad6_ u32 +a28 net-_u12-pad1_ net-_u29-pad2_ u29 +a29 net-_u24-pad5_ net-_u1-pad6_ u27 +a30 net-_u32-pad5_ net-_u1-pad9_ u36 +a31 net-_u12-pad1_ net-_u38-pad2_ u38 +a32 net-_u12-pad1_ net-_u55-pad2_ u55 +a33 net-_u12-pad1_ net-_u46-pad2_ u46 +a34 net-_u47-pad3_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u49-pad1_ unconnected-_u50-pad6_ u50 +a35 net-_u53-pad3_ net-_u55-pad2_ unconnected-_u58-pad3_ unconnected-_u58-pad4_ net-_u57-pad1_ unconnected-_u58-pad6_ u58 +a36 net-_u61-pad3_ net-_u63-pad2_ unconnected-_u66-pad3_ unconnected-_u66-pad4_ net-_u65-pad1_ unconnected-_u66-pad6_ u66 +a37 net-_u12-pad1_ net-_u63-pad2_ u63 +a38 net-_u57-pad1_ net-_u1-pad16_ u62 +a39 net-_u65-pad1_ net-_u1-pad19_ u67 +a40 net-_u49-pad1_ net-_u1-pad15_ u54 +a41 net-_u40-pad5_ net-_u1-pad12_ u45 +a42 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u15-pad3_ u15 +a43 net-_u13-pad2_ net-_u10-pad2_ u9 +a44 [net-_u5-pad1_ net-_u13-pad2_ ] net-_u5-pad3_ u5 +a45 [net-_u16-pad5_ net-_u17-pad2_ ] net-_u15-pad1_ u18 +a46 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a47 net-_u13-pad2_ net-_u17-pad2_ u17 +a48 [net-_u23-pad1_ net-_u21-pad3_ ] net-_u23-pad3_ u23 +a49 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a50 [net-_u10-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a51 [net-_u21-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a52 [net-_u24-pad5_ net-_u25-pad2_ ] net-_u23-pad1_ u26 +a53 net-_u15-pad3_ net-_u12-pad2_ unconnected-_u16-pad3_ unconnected-_u16-pad4_ net-_u16-pad5_ unconnected-_u16-pad6_ u16 +a54 net-_u23-pad3_ net-_u20-pad2_ unconnected-_u24-pad3_ unconnected-_u24-pad4_ net-_u24-pad5_ unconnected-_u24-pad6_ u24 +a55 net-_u12-pad1_ net-_u20-pad2_ u20 +a56 net-_u16-pad5_ net-_u1-pad5_ u19 +a57 net-_u12-pad1_ net-_u12-pad2_ u12 +a58 net-_u7-pad3_ net-_u3-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u10-pad1_ unconnected-_u8-pad6_ u8 +a59 net-_u1-pad11_ net-_u12-pad1_ u4 +a60 net-_u12-pad1_ net-_u3-pad2_ u3 +a61 net-_u10-pad1_ net-_u1-pad2_ u11 +a62 net-_u1-pad4_ net-_u13-pad1_ u14 +a63 net-_u1-pad7_ net-_u21-pad1_ u22 +a64 net-_u13-pad2_ net-_u25-pad2_ u25 +a65 net-_u1-pad1_ net-_u13-pad2_ u2 +a66 net-_u1-pad3_ net-_u5-pad1_ u6 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u30 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u47 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u65 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u61 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u53 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u52 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u60 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u32 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u50 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u58 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u66 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u62 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u67 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u45 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74hc377/74hc377.kicad_sch b/library/SubcircuitLibrary/74hc377/74hc377.kicad_sch new file mode 100644 index 000000000..0534fee79 --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/74hc377.kicad_sch @@ -0,0 +1,3623 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid bf1bd2b0-10d2-4d66-acb0-fe1f89507479) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_and" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) 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000000000..6aa2ecf65 --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/74hc377.sub @@ -0,0 +1,270 @@ +* Subcircuit 74hc377 +.subckt 74hc377 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ unconnected-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ unconnected-_u1-pad20_ +.title kicad schematic +* u37 net-_u1-pad13_ net-_u35-pad1_ d_buffer +* u33 net-_u13-pad2_ net-_u33-pad2_ d_inverter +* u41 net-_u13-pad2_ net-_u41-pad2_ d_inverter +* u30 net-_u1-pad8_ net-_u28-pad1_ d_buffer +* u47 net-_u47-pad1_ net-_u43-pad3_ net-_u47-pad3_ d_or +* u65 net-_u65-pad1_ net-_u64-pad2_ net-_u61-pad1_ d_and +* u64 net-_u13-pad2_ net-_u64-pad2_ d_inverter +* u61 net-_u61-pad1_ net-_u59-pad3_ net-_u61-pad3_ d_or +* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u53-pad3_ d_or +* u57 net-_u57-pad1_ net-_u56-pad2_ net-_u53-pad1_ d_and +* u51 net-_u51-pad1_ net-_u13-pad2_ net-_u51-pad3_ d_and +* u42 net-_u40-pad5_ net-_u41-pad2_ net-_u39-pad1_ d_and +* u43 net-_u43-pad1_ net-_u13-pad2_ net-_u43-pad3_ d_and +* u35 net-_u35-pad1_ net-_u13-pad2_ net-_u35-pad3_ d_and +* u34 net-_u32-pad5_ net-_u33-pad2_ net-_u31-pad1_ d_and +* u28 net-_u28-pad1_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u31 net-_u31-pad1_ net-_u28-pad3_ net-_u31-pad3_ d_or +* u39 net-_u39-pad1_ net-_u35-pad3_ net-_u39-pad3_ d_or +* u52 net-_u1-pad17_ net-_u51-pad1_ d_buffer +* u44 net-_u1-pad14_ net-_u43-pad1_ d_buffer +* u60 net-_u1-pad18_ net-_u59-pad1_ d_buffer +* u59 net-_u59-pad1_ net-_u13-pad2_ net-_u59-pad3_ d_and +* u56 net-_u13-pad2_ net-_u56-pad2_ d_inverter +* u49 net-_u49-pad1_ net-_u48-pad2_ net-_u47-pad1_ d_and +* u48 net-_u13-pad2_ net-_u48-pad2_ d_inverter +* u40 net-_u39-pad3_ net-_u38-pad2_ unconnected-_u40-pad3_ unconnected-_u40-pad4_ net-_u40-pad5_ unconnected-_u40-pad6_ d_dff +* u32 net-_u31-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ unconnected-_u32-pad4_ net-_u32-pad5_ unconnected-_u32-pad6_ d_dff +* u29 net-_u12-pad1_ net-_u29-pad2_ d_inverter +* u27 net-_u24-pad5_ net-_u1-pad6_ d_buffer +* u36 net-_u32-pad5_ net-_u1-pad9_ d_buffer +* u38 net-_u12-pad1_ net-_u38-pad2_ d_inverter +* u55 net-_u12-pad1_ net-_u55-pad2_ d_inverter +* u46 net-_u12-pad1_ net-_u46-pad2_ d_inverter +* u50 net-_u47-pad3_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u49-pad1_ unconnected-_u50-pad6_ d_dff +* u58 net-_u53-pad3_ net-_u55-pad2_ unconnected-_u58-pad3_ unconnected-_u58-pad4_ net-_u57-pad1_ unconnected-_u58-pad6_ d_dff +* u66 net-_u61-pad3_ net-_u63-pad2_ unconnected-_u66-pad3_ unconnected-_u66-pad4_ net-_u65-pad1_ unconnected-_u66-pad6_ d_dff +* u63 net-_u12-pad1_ net-_u63-pad2_ d_inverter +* u62 net-_u57-pad1_ net-_u1-pad16_ d_buffer +* u67 net-_u65-pad1_ net-_u1-pad19_ d_buffer +* u54 net-_u49-pad1_ net-_u1-pad15_ d_buffer +* u45 net-_u40-pad5_ net-_u1-pad12_ d_buffer +* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u15-pad3_ d_or +* u9 net-_u13-pad2_ net-_u10-pad2_ d_inverter +* u5 net-_u5-pad1_ net-_u13-pad2_ net-_u5-pad3_ d_and +* u18 net-_u16-pad5_ net-_u17-pad2_ net-_u15-pad1_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u17 net-_u13-pad2_ net-_u17-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u21-pad3_ net-_u23-pad3_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u7 net-_u10-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_or +* u21 net-_u21-pad1_ net-_u13-pad2_ net-_u21-pad3_ d_and +* u26 net-_u24-pad5_ net-_u25-pad2_ net-_u23-pad1_ d_and +* u16 net-_u15-pad3_ net-_u12-pad2_ unconnected-_u16-pad3_ unconnected-_u16-pad4_ net-_u16-pad5_ unconnected-_u16-pad6_ d_dff +* u24 net-_u23-pad3_ net-_u20-pad2_ unconnected-_u24-pad3_ unconnected-_u24-pad4_ net-_u24-pad5_ unconnected-_u24-pad6_ d_dff +* u20 net-_u12-pad1_ net-_u20-pad2_ d_inverter +* u19 net-_u16-pad5_ net-_u1-pad5_ d_buffer +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u7-pad3_ net-_u3-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u10-pad1_ unconnected-_u8-pad6_ d_dff +* u4 net-_u1-pad11_ net-_u12-pad1_ d_inverter +* u3 net-_u12-pad1_ net-_u3-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u1-pad2_ d_buffer +* u14 net-_u1-pad4_ net-_u13-pad1_ d_buffer +* u22 net-_u1-pad7_ net-_u21-pad1_ d_buffer +* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u13-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u5-pad1_ d_buffer +a1 net-_u1-pad13_ net-_u35-pad1_ u37 +a2 net-_u13-pad2_ net-_u33-pad2_ u33 +a3 net-_u13-pad2_ net-_u41-pad2_ u41 +a4 net-_u1-pad8_ net-_u28-pad1_ u30 +a5 [net-_u47-pad1_ net-_u43-pad3_ ] net-_u47-pad3_ u47 +a6 [net-_u65-pad1_ net-_u64-pad2_ ] net-_u61-pad1_ u65 +a7 net-_u13-pad2_ net-_u64-pad2_ u64 +a8 [net-_u61-pad1_ net-_u59-pad3_ ] net-_u61-pad3_ u61 +a9 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u53-pad3_ u53 +a10 [net-_u57-pad1_ net-_u56-pad2_ ] net-_u53-pad1_ u57 +a11 [net-_u51-pad1_ net-_u13-pad2_ ] net-_u51-pad3_ u51 +a12 [net-_u40-pad5_ net-_u41-pad2_ ] net-_u39-pad1_ u42 +a13 [net-_u43-pad1_ net-_u13-pad2_ ] net-_u43-pad3_ u43 +a14 [net-_u35-pad1_ net-_u13-pad2_ ] net-_u35-pad3_ u35 +a15 [net-_u32-pad5_ net-_u33-pad2_ ] net-_u31-pad1_ u34 +a16 [net-_u28-pad1_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a17 [net-_u31-pad1_ net-_u28-pad3_ ] net-_u31-pad3_ u31 +a18 [net-_u39-pad1_ net-_u35-pad3_ ] net-_u39-pad3_ u39 +a19 net-_u1-pad17_ net-_u51-pad1_ u52 +a20 net-_u1-pad14_ net-_u43-pad1_ u44 +a21 net-_u1-pad18_ net-_u59-pad1_ u60 +a22 [net-_u59-pad1_ net-_u13-pad2_ ] net-_u59-pad3_ u59 +a23 net-_u13-pad2_ net-_u56-pad2_ u56 +a24 [net-_u49-pad1_ net-_u48-pad2_ ] net-_u47-pad1_ u49 +a25 net-_u13-pad2_ net-_u48-pad2_ u48 +a26 net-_u39-pad3_ net-_u38-pad2_ unconnected-_u40-pad3_ unconnected-_u40-pad4_ net-_u40-pad5_ unconnected-_u40-pad6_ u40 +a27 net-_u31-pad3_ net-_u29-pad2_ unconnected-_u32-pad3_ unconnected-_u32-pad4_ net-_u32-pad5_ unconnected-_u32-pad6_ u32 +a28 net-_u12-pad1_ net-_u29-pad2_ u29 +a29 net-_u24-pad5_ net-_u1-pad6_ u27 +a30 net-_u32-pad5_ net-_u1-pad9_ u36 +a31 net-_u12-pad1_ net-_u38-pad2_ u38 +a32 net-_u12-pad1_ net-_u55-pad2_ u55 +a33 net-_u12-pad1_ net-_u46-pad2_ u46 +a34 net-_u47-pad3_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u49-pad1_ unconnected-_u50-pad6_ u50 +a35 net-_u53-pad3_ net-_u55-pad2_ unconnected-_u58-pad3_ unconnected-_u58-pad4_ net-_u57-pad1_ unconnected-_u58-pad6_ u58 +a36 net-_u61-pad3_ net-_u63-pad2_ unconnected-_u66-pad3_ unconnected-_u66-pad4_ net-_u65-pad1_ unconnected-_u66-pad6_ u66 +a37 net-_u12-pad1_ net-_u63-pad2_ u63 +a38 net-_u57-pad1_ net-_u1-pad16_ u62 +a39 net-_u65-pad1_ net-_u1-pad19_ u67 +a40 net-_u49-pad1_ net-_u1-pad15_ u54 +a41 net-_u40-pad5_ net-_u1-pad12_ u45 +a42 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u15-pad3_ u15 +a43 net-_u13-pad2_ net-_u10-pad2_ u9 +a44 [net-_u5-pad1_ net-_u13-pad2_ ] net-_u5-pad3_ u5 +a45 [net-_u16-pad5_ net-_u17-pad2_ ] net-_u15-pad1_ u18 +a46 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a47 net-_u13-pad2_ net-_u17-pad2_ u17 +a48 [net-_u23-pad1_ net-_u21-pad3_ ] net-_u23-pad3_ u23 +a49 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a50 [net-_u10-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a51 [net-_u21-pad1_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a52 [net-_u24-pad5_ net-_u25-pad2_ ] net-_u23-pad1_ u26 +a53 net-_u15-pad3_ net-_u12-pad2_ unconnected-_u16-pad3_ unconnected-_u16-pad4_ net-_u16-pad5_ unconnected-_u16-pad6_ u16 +a54 net-_u23-pad3_ net-_u20-pad2_ unconnected-_u24-pad3_ unconnected-_u24-pad4_ net-_u24-pad5_ unconnected-_u24-pad6_ u24 +a55 net-_u12-pad1_ net-_u20-pad2_ u20 +a56 net-_u16-pad5_ net-_u1-pad5_ u19 +a57 net-_u12-pad1_ net-_u12-pad2_ u12 +a58 net-_u7-pad3_ net-_u3-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ net-_u10-pad1_ unconnected-_u8-pad6_ u8 +a59 net-_u1-pad11_ net-_u12-pad1_ u4 +a60 net-_u12-pad1_ net-_u3-pad2_ u3 +a61 net-_u10-pad1_ net-_u1-pad2_ u11 +a62 net-_u1-pad4_ net-_u13-pad1_ u14 +a63 net-_u1-pad7_ net-_u21-pad1_ u22 +a64 net-_u13-pad2_ net-_u25-pad2_ u25 +a65 net-_u1-pad1_ net-_u13-pad2_ u2 +a66 net-_u1-pad3_ net-_u5-pad1_ u6 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u30 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u47 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u65 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u61 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u53 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u52 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u60 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u32 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u50 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u58 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u66 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u62 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u67 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u45 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74hc377 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74hc377/74hc377_Previous_Values.xml b/library/SubcircuitLibrary/74hc377/74hc377_Previous_Values.xml new file mode 100644 index 000000000..e0ac1885e --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/74hc377_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_dffd_dffd_inverterd_inverterd_andd_andd_inverterd_andd_andd_inverterd_inverterd_inverterd_andd_andd_inverterd_andd_ord_ord_dffd_inverterd_inverterd_dffd_andd_ord_andd_andd_ord_andd_ord_inverterd_inverterd_inverterd_ord_andd_andd_andd_andd_ord_andd_ord_dffd_dffd_inverterd_inverterd_dffd_dffd_inverterd_inverterd_bufferd_inverterd_inverterd_bufferd_andd_inverterd_ord_ord_andd_andd_andd_andd_andd_andd_ord_ord_bufferd_bufferd_bufferd_andd_inverterd_dffd_dffd_bufferd_bufferd_inverterd_inverterd_dffd_dffd_inverterd_bufferd_bufferd_bufferd_bufferd_ord_andd_andd_andd_ord_ord_andd_dffd_dffd_inverterd_bufferd_inverterd_dffd_inverterd_bufferd_bufferd_bufferd_inverterd_buffertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74hc377/_autosave-74hc377.sch b/library/SubcircuitLibrary/74hc377/_autosave-74hc377.sch new file mode 100644 index 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6500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Digital:d_inverter U64 +U 1 1 00000000 +P 10650 1650 +F 0 "U64" V 10600 1750 60 0000 L CNN +F 1 "d_inverter" V 10750 1750 60 0000 L CNN +F 2 "" H 10700 1600 60 0000 C CNN +F 3 "" H 10700 1600 60 0000 C CNN + 1 10650 1650 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U5 +U 1 1 00000000 +P 850 2450 +F 0 "U5" V 800 2650 60 0000 L CNN +F 1 "d_and" V 950 2650 60 0000 L CNN +F 2 "" H 850 2450 60 0000 C CNN +F 3 "" H 850 2450 60 0000 C CNN + 1 850 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U7 +U 1 1 00000000 +P 1250 3750 +F 0 "U7" V 1200 3950 60 0000 L CNN +F 1 "d_or" V 1350 3950 60 0000 L CNN +F 2 "" H 1250 3750 60 0000 C CNN +F 3 "" H 1250 3750 60 0000 C CNN + 1 1250 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U10 +U 1 1 00000000 +P 1600 2450 +F 0 "U10" V 1550 2650 60 0000 L CNN +F 1 "d_and" V 1700 2650 60 0000 L CNN +F 2 "" H 1600 2450 60 0000 C CNN +F 3 "" H 1600 2450 60 0000 C CNN + 1 1600 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U13 +U 1 1 00000000 +P 2400 2500 +F 0 "U13" V 2350 2700 60 0000 L CNN +F 1 "d_and" V 2500 2700 60 0000 L CNN +F 2 "" H 2400 2500 60 0000 C CNN +F 3 "" H 2400 2500 60 0000 C CNN + 1 2400 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U15 +U 1 1 00000000 +P 2800 3800 +F 0 "U15" V 2750 4000 60 0000 L CNN +F 1 "d_or" V 2900 4000 60 0000 L CNN +F 2 "" H 2800 3800 60 0000 C CNN +F 3 "" H 2800 3800 60 0000 C CNN + 1 2800 3800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U18 +U 1 1 00000000 +P 3150 2500 +F 0 "U18" V 3100 2700 60 0000 L CNN +F 1 "d_and" V 3250 2700 60 0000 L CNN +F 2 "" H 3150 2500 60 0000 C CNN +F 3 "" H 3150 2500 60 0000 C CNN + 1 3150 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U21 +U 1 1 00000000 +P 3750 2450 +F 0 "U21" V 3700 2650 60 0000 L CNN +F 1 "d_and" V 3850 2650 60 0000 L CNN +F 2 "" H 3750 2450 60 0000 C CNN +F 3 "" H 3750 2450 60 0000 C CNN + 1 3750 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U23 +U 1 1 00000000 +P 4150 3750 +F 0 "U23" V 4100 3950 60 0000 L CNN +F 1 "d_or" V 4250 3950 60 0000 L CNN +F 2 "" H 4150 3750 60 0000 C CNN +F 3 "" H 4150 3750 60 0000 C CNN + 1 4150 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U26 +U 1 1 00000000 +P 4500 2450 +F 0 "U26" V 4450 2650 60 0000 L CNN +F 1 "d_and" V 4600 2650 60 0000 L CNN +F 2 "" H 4500 2450 60 0000 C CNN +F 3 "" H 4500 2450 60 0000 C CNN + 1 4500 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U28 +U 1 1 00000000 +P 5050 2500 +F 0 "U28" V 5000 2700 60 0000 L CNN +F 1 "d_and" V 5150 2700 60 0000 L CNN +F 2 "" H 5050 2500 60 0000 C CNN +F 3 "" H 5050 2500 60 0000 C CNN + 1 5050 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U31 +U 1 1 00000000 +P 5450 3800 +F 0 "U31" V 5400 4000 60 0000 L CNN +F 1 "d_or" V 5550 4000 60 0000 L CNN +F 2 "" H 5450 3800 60 0000 C CNN +F 3 "" H 5450 3800 60 0000 C CNN + 1 5450 3800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U34 +U 1 1 00000000 +P 5800 2500 +F 0 "U34" V 5750 2700 60 0000 L CNN +F 1 "d_and" V 5900 2700 60 0000 L CNN +F 2 "" H 5800 2500 60 0000 C CNN +F 3 "" H 5800 2500 60 0000 C CNN + 1 5800 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U35 +U 1 1 00000000 +P 6250 2550 +F 0 "U35" V 6200 2750 60 0000 L CNN +F 1 "d_and" V 6350 2750 60 0000 L CNN +F 2 "" H 6250 2550 60 0000 C CNN +F 3 "" H 6250 2550 60 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U39 +U 1 1 00000000 +P 6650 3850 +F 0 "U39" V 6600 4050 60 0000 L CNN +F 1 "d_or" V 6750 4050 60 0000 L CNN +F 2 "" H 6650 3850 60 0000 C CNN +F 3 "" H 6650 3850 60 0000 C CNN + 1 6650 3850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U42 +U 1 1 00000000 +P 7000 2550 +F 0 "U42" V 6950 2750 60 0000 L CNN +F 1 "d_and" V 7100 2750 60 0000 L CNN +F 2 "" H 7000 2550 60 0000 C CNN +F 3 "" H 7000 2550 60 0000 C CNN + 1 7000 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U43 +U 1 1 00000000 +P 7450 2500 +F 0 "U43" V 7400 2700 60 0000 L CNN +F 1 "d_and" V 7550 2700 60 0000 L CNN +F 2 "" H 7450 2500 60 0000 C CNN +F 3 "" H 7450 2500 60 0000 C CNN + 1 7450 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U47 +U 1 1 00000000 +P 7850 3800 +F 0 "U47" V 7800 4000 60 0000 L CNN +F 1 "d_or" V 7950 4000 60 0000 L CNN +F 2 "" H 7850 3800 60 0000 C CNN +F 3 "" H 7850 3800 60 0000 C CNN + 1 7850 3800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U49 +U 1 1 00000000 +P 8200 2500 +F 0 "U49" V 8150 2700 60 0000 L CNN +F 1 "d_and" V 8300 2700 60 0000 L CNN +F 2 "" H 8200 2500 60 0000 C CNN +F 3 "" H 8200 2500 60 0000 C CNN + 1 8200 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U51 +U 1 1 00000000 +P 8600 2550 +F 0 "U51" V 8550 2750 60 0000 L CNN +F 1 "d_and" V 8700 2750 60 0000 L CNN +F 2 "" H 8600 2550 60 0000 C CNN +F 3 "" H 8600 2550 60 0000 C CNN + 1 8600 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U53 +U 1 1 00000000 +P 9000 3850 +F 0 "U53" V 8950 4050 60 0000 L CNN +F 1 "d_or" V 9100 4050 60 0000 L CNN +F 2 "" H 9000 3850 60 0000 C CNN +F 3 "" H 9000 3850 60 0000 C CNN + 1 9000 3850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U57 +U 1 1 00000000 +P 9350 2550 +F 0 "U57" V 9300 2750 60 0000 L CNN +F 1 "d_and" V 9450 2750 60 0000 L CNN +F 2 "" H 9350 2550 60 0000 C CNN +F 3 "" H 9350 2550 60 0000 C CNN + 1 9350 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U59 +U 1 1 00000000 +P 9900 2500 +F 0 "U59" V 9850 2700 60 0000 L CNN +F 1 "d_and" V 10000 2700 60 0000 L CNN +F 2 "" H 9900 2500 60 0000 C CNN +F 3 "" H 9900 2500 60 0000 C CNN + 1 9900 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_or U61 +U 1 1 00000000 +P 10300 3800 +F 0 "U61" V 10250 4000 60 0000 L CNN +F 1 "d_or" V 10400 4000 60 0000 L CNN +F 2 "" H 10300 3800 60 0000 C CNN +F 3 "" H 10300 3800 60 0000 C CNN + 1 10300 3800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_and U65 +U 1 1 00000000 +P 10650 2500 +F 0 "U65" V 10600 2700 60 0000 L CNN +F 1 "d_and" V 10750 2700 60 0000 L CNN +F 2 "" H 10650 2500 60 0000 C CNN +F 3 "" H 10650 2500 60 0000 C CNN + 1 10650 2500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U6 +U 1 1 00000000 +P 950 300 +F 0 "U6" V 975 550 60 0000 L CNN +F 1 "d_buffer" V 1125 550 60 0000 L CNN +F 2 "" H 950 300 60 0000 C CNN +F 3 "" H 950 300 60 0000 C CNN + 1 950 300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U11 +U 1 1 00000000 +P 2000 8100 +F 0 "U11" V 2025 8350 60 0000 L CNN +F 1 "d_buffer" V 2175 8350 60 0000 L CNN +F 2 "" H 2000 8100 60 0000 C CNN +F 3 "" H 2000 8100 60 0000 C CNN + 1 2000 8100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U14 +U 1 1 00000000 +P 2500 350 +F 0 "U14" V 2525 600 60 0000 L CNN +F 1 "d_buffer" V 2675 600 60 0000 L CNN +F 2 "" H 2500 350 60 0000 C CNN +F 3 "" H 2500 350 60 0000 C CNN + 1 2500 350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U19 +U 1 1 00000000 +P 3450 8050 +F 0 "U19" V 3475 8300 60 0000 L CNN +F 1 "d_buffer" V 3625 8300 60 0000 L CNN +F 2 "" H 3450 8050 60 0000 C CNN +F 3 "" H 3450 8050 60 0000 C CNN + 1 3450 8050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U22 +U 1 1 00000000 +P 3850 350 +F 0 "U22" V 3875 600 60 0000 L CNN +F 1 "d_buffer" V 4025 600 60 0000 L CNN +F 2 "" H 3850 350 60 0000 C CNN +F 3 "" H 3850 350 60 0000 C CNN + 1 3850 350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U27 +U 1 1 00000000 +P 4900 8100 +F 0 "U27" V 4925 8350 60 0000 L CNN +F 1 "d_buffer" V 5075 8350 60 0000 L CNN +F 2 "" H 4900 8100 60 0000 C CNN +F 3 "" H 4900 8100 60 0000 C CNN + 1 4900 8100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U30 +U 1 1 00000000 +P 5150 400 +F 0 "U30" V 5175 650 60 0000 L CNN +F 1 "d_buffer" V 5325 650 60 0000 L CNN +F 2 "" H 5150 400 60 0000 C CNN +F 3 "" H 5150 400 60 0000 C CNN + 1 5150 400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U36 +U 1 1 00000000 +P 6250 7900 +F 0 "U36" V 6275 8150 60 0000 L CNN +F 1 "d_buffer" V 6425 8150 60 0000 L CNN +F 2 "" H 6250 7900 60 0000 C CNN +F 3 "" H 6250 7900 60 0000 C CNN + 1 6250 7900 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U37 +U 1 1 00000000 +P 6350 450 +F 0 "U37" V 6375 700 60 0000 L CNN +F 1 "d_buffer" V 6525 700 60 0000 L CNN +F 2 "" H 6350 450 60 0000 C CNN +F 3 "" H 6350 450 60 0000 C CNN + 1 6350 450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U44 +U 1 1 00000000 +P 7550 350 +F 0 "U44" V 7575 600 60 0000 L CNN +F 1 "d_buffer" V 7725 600 60 0000 L CNN +F 2 "" H 7550 350 60 0000 C CNN +F 3 "" H 7550 350 60 0000 C CNN + 1 7550 350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U45 +U 1 1 00000000 +P 7600 8000 +F 0 "U45" V 7625 8250 60 0000 L CNN +F 1 "d_buffer" V 7775 8250 60 0000 L CNN +F 2 "" H 7600 8000 60 0000 C CNN +F 3 "" H 7600 8000 60 0000 C CNN + 1 7600 8000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U52 +U 1 1 00000000 +P 8700 450 +F 0 "U52" V 8725 700 60 0000 L CNN +F 1 "d_buffer" V 8875 700 60 0000 L CNN +F 2 "" H 8700 450 60 0000 C CNN +F 3 "" H 8700 450 60 0000 C CNN + 1 8700 450 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U54 +U 1 1 00000000 +P 9000 7850 +F 0 "U54" V 9025 8100 60 0000 L CNN +F 1 "d_buffer" V 9175 8100 60 0000 L CNN +F 2 "" H 9000 7850 60 0000 C CNN +F 3 "" H 9000 7850 60 0000 C CNN + 1 9000 7850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U60 +U 1 1 00000000 +P 10000 400 +F 0 "U60" V 10025 650 60 0000 L CNN +F 1 "d_buffer" V 10175 650 60 0000 L CNN +F 2 "" H 10000 400 60 0000 C CNN +F 3 "" H 10000 400 60 0000 C CNN + 1 10000 400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U62 +U 1 1 00000000 +P 10400 7850 +F 0 "U62" V 10425 8100 60 0000 L CNN +F 1 "d_buffer" V 10575 8100 60 0000 L CNN +F 2 "" H 10400 7850 60 0000 C CNN +F 3 "" H 10400 7850 60 0000 C CNN + 1 10400 7850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_buffer U67 +U 1 1 00000000 +P 11800 7850 +F 0 "U67" V 11825 8100 60 0000 L CNN +F 1 "d_buffer" V 11975 8100 60 0000 L CNN +F 2 "" H 11800 7850 60 0000 C CNN +F 3 "" H 11800 7850 60 0000 C CNN + 1 11800 7850 + 0 1 1 0 +$EndComp +$Comp +L eSim_Digital:d_dff U8 +U 1 1 00000000 +P 1250 5350 +F 0 "U8" H 1330 6000 60 0000 L CNN +F 1 "d_dff" H 1330 5850 60 0000 L CNN +F 2 "" H 1250 5350 60 0000 C CNN +F 3 "" H 1250 5350 60 0000 C CNN + 1 1250 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U16 +U 1 1 00000000 +P 2800 5350 +F 0 "U16" H 2880 6000 60 0000 L CNN +F 1 "d_dff" H 2880 5850 60 0000 L CNN +F 2 "" H 2800 5350 60 0000 C CNN +F 3 "" H 2800 5350 60 0000 C CNN + 1 2800 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U24 +U 1 1 00000000 +P 4200 5300 +F 0 "U24" H 4280 5950 60 0000 L CNN +F 1 "d_dff" H 4280 5800 60 0000 L CNN +F 2 "" H 4200 5300 60 0000 C CNN +F 3 "" H 4200 5300 60 0000 C CNN + 1 4200 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U32 +U 1 1 00000000 +P 5650 5300 +F 0 "U32" H 5730 5950 60 0000 L CNN +F 1 "d_dff" H 5730 5800 60 0000 L CNN +F 2 "" H 5650 5300 60 0000 C CNN +F 3 "" H 5650 5300 60 0000 C CNN + 1 5650 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U40 +U 1 1 00000000 +P 6950 5300 +F 0 "U40" H 7030 5950 60 0000 L CNN +F 1 "d_dff" H 7030 5800 60 0000 L CNN +F 2 "" H 6950 5300 60 0000 C CNN +F 3 "" H 6950 5300 60 0000 C CNN + 1 6950 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U50 +U 1 1 00000000 +P 8350 5300 +F 0 "U50" H 8430 5950 60 0000 L CNN +F 1 "d_dff" H 8430 5800 60 0000 L CNN +F 2 "" H 8350 5300 60 0000 C CNN +F 3 "" H 8350 5300 60 0000 C CNN + 1 8350 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U58 +U 1 1 00000000 +P 9750 5350 +F 0 "U58" H 9830 6000 60 0000 L CNN +F 1 "d_dff" H 9830 5850 60 0000 L CNN +F 2 "" H 9750 5350 60 0000 C CNN +F 3 "" H 9750 5350 60 0000 C CNN + 1 9750 5350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U66 +U 1 1 00000000 +P 11050 5400 +F 0 "U66" H 11130 6050 60 0000 L CNN +F 1 "d_dff" H 11130 5900 60 0000 L CNN +F 2 "" H 11050 5400 60 0000 C CNN +F 3 "" H 11050 5400 60 0000 C CNN + 1 11050 5400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74hc377/analysis b/library/SubcircuitLibrary/74hc377/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74hc377/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From 25c0029ae003145de045e19f0d0763aea3aa20f7 Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:40:59 +0530 Subject: [PATCH 09/10] 74LS257 is a quad 2-to-1 multiplexer with 3-state outputs. --- .../74ls257_sub/74ls257_sub.cir | 22 + .../74ls257_sub/74ls257_sub.cir.out | 88 + .../74ls257_sub/74ls257_sub.kicad_sch | 1839 +++++++++++++++++ .../74ls257_sub/74ls257_sub.sub | 82 + .../74ls257_sub_Previous_Values.xml | 1 + .../74ls257_sub/_autosave-74ls257_sub.sch | 544 +++++ .../SubcircuitLibrary/74ls257_sub/analysis | 1 + 7 files changed, 2577 insertions(+) create mode 100644 library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir create mode 100644 library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir.out create mode 100644 library/SubcircuitLibrary/74ls257_sub/74ls257_sub.kicad_sch create mode 100644 library/SubcircuitLibrary/74ls257_sub/74ls257_sub.sub create mode 100644 library/SubcircuitLibrary/74ls257_sub/74ls257_sub_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74ls257_sub/_autosave-74ls257_sub.sch create mode 100644 library/SubcircuitLibrary/74ls257_sub/analysis diff --git a/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir new file mode 100644 index 000000000..14788babb --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir @@ -0,0 +1,22 @@ +.title KiCad schematic +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ unconnected-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ unconnected-_U1-Pad16_ PORT +U20 Net-_U14-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad12_ d_tristate +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U15 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U15-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_or +U19 Net-_U16-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad9_ d_tristate +U14 Net-_U14-Pad1_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_or +U17 Net-_U13-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad7_ d_tristate +U18 Net-_U15-Pad3_ Net-_U17-Pad2_ Net-_U1-Pad4_ d_tristate +U8 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U16-Pad2_ d_and +U7 Net-_U11-Pad1_ Net-_U1-Pad10_ Net-_U16-Pad1_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and +U12 Net-_U10-Pad1_ Net-_U1-Pad2_ Net-_U12-Pad3_ d_and +U9 Net-_U11-Pad1_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad14_ Net-_U10-Pad3_ d_and +U6 Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U13-Pad2_ d_and +U5 Net-_U11-Pad1_ Net-_U1-Pad6_ Net-_U13-Pad1_ d_and +U3 Net-_U1-Pad15_ Net-_U17-Pad2_ d_inverter +U4 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U2 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter +.end diff --git a/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir.out b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir.out new file mode 100644 index 000000000..e9f8a3e78 --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.cir.out @@ -0,0 +1,88 @@ +.title kicad schematic + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ port +* u20 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u15 net-_u11-pad3_ net-_u12-pad3_ net-_u15-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or +* u19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad9_ d_tristate +* u14 net-_u14-pad1_ net-_u10-pad3_ net-_u14-pad3_ d_or +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad7_ d_tristate +* u18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad4_ d_tristate +* u8 net-_u10-pad1_ net-_u1-pad11_ net-_u16-pad2_ d_and +* u7 net-_u11-pad1_ net-_u1-pad10_ net-_u16-pad1_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u10-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and +* u9 net-_u11-pad1_ net-_u1-pad13_ net-_u14-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad14_ net-_u10-pad3_ d_and +* u6 net-_u10-pad1_ net-_u1-pad5_ net-_u13-pad2_ d_and +* u5 net-_u11-pad1_ net-_u1-pad6_ net-_u13-pad1_ d_and +* u3 net-_u1-pad15_ net-_u17-pad2_ d_inverter +* u4 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter +a1 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u20 +a2 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a3 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u15-pad3_ u15 +a4 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a5 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad9_ u19 +a6 [net-_u14-pad1_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a7 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad7_ u17 +a8 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad4_ u18 +a9 [net-_u10-pad1_ net-_u1-pad11_ ] net-_u16-pad2_ u8 +a10 [net-_u11-pad1_ net-_u1-pad10_ ] net-_u16-pad1_ u7 +a11 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a12 [net-_u10-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12 +a13 [net-_u11-pad1_ net-_u1-pad13_ ] net-_u14-pad1_ u9 +a14 [net-_u10-pad1_ net-_u1-pad14_ ] net-_u10-pad3_ u10 +a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u13-pad2_ u6 +a16 [net-_u11-pad1_ net-_u1-pad6_ ] net-_u13-pad1_ u5 +a17 net-_u1-pad15_ net-_u17-pad2_ u3 +a18 net-_u10-pad1_ net-_u11-pad1_ u4 +a19 net-_u1-pad1_ net-_u10-pad1_ u2 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.kicad_sch b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.kicad_sch new file mode 100644 index 000000000..e6770cc38 --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.kicad_sch @@ -0,0 +1,1839 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 63fd9add-42ea-4670-89a7-ef3487ed1323) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_and" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_and_0_1" + (polyline + (pts + (xy 3.81 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"") + ) + (path "/999277eb-2c7d-4ac7-b937-04e9e6b0ae42" + (reference "U1") (unit 6) (value "PORT") (footprint "") + ) + (path "/00c974bd-04f7-4d50-9f3f-260e962db1a0" + (reference "U1") (unit 7) (value "PORT") (footprint "") + ) + (path "/83af4f5b-4cd5-49ed-b0ef-29e400119152" + (reference "U1") (unit 8) (value "PORT") (footprint "") + ) + (path "/a805e0b4-4996-4227-9178-089818711354" + (reference "U1") (unit 9) (value "PORT") (footprint "") + ) + (path "/6d3b9a0d-e900-4c92-a25d-0510dfbddbca" + (reference "U1") (unit 10) (value "PORT") (footprint "") + ) + (path "/c1d4d688-21ed-4e89-9112-87b5f741396c" + (reference "U1") (unit 11) (value "PORT") (footprint "") + ) + (path "/c06bc369-1905-4c9a-9f3d-ffcda750c3c2" + (reference "U1") (unit 12) (value "PORT") (footprint "") + ) + (path "/e2425d83-24f5-49a2-a987-8b153e9c13da" + (reference "U1") (unit 13) (value "PORT") (footprint "") + ) + (path "/cda994f1-4e19-4290-8737-baac7ca18238" + (reference "U1") (unit 14) (value "PORT") (footprint "") + ) + (path "/9e0f7c8e-e248-41c8-8baa-fe4f71d9156a" + (reference "U1") (unit 15) (value "PORT") (footprint "") + ) + (path "/c013f1bd-aed9-4493-8b96-5f6afcbc5674" + (reference "U1") (unit 16) (value "PORT") (footprint "") + ) + (path "/7ae58eaa-0df6-4fb6-9081-f88595b93282" + (reference "U2") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/6c88d1a7-b090-4f0b-8e1c-ca9fa3b54426" + (reference "U3") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/45b85c1a-a8d5-4e8d-91b4-a6c7b7061b7c" + (reference "U4") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/2eb5277b-7aa6-4425-a85b-36b7d91759f2" + (reference "U5") (unit 1) (value "d_and") (footprint "") + ) + (path "/d6ea3f11-b27a-4883-a534-75e4adb4382b" + (reference "U6") (unit 1) (value "d_and") (footprint "") + ) + (path "/5197c079-25c9-4e09-ab40-0c6d04ae788e" + (reference "U7") (unit 1) (value "d_and") (footprint "") + ) + (path "/cf8dc7c7-d781-4895-bfd3-5308191b577d" + (reference "U8") (unit 1) (value "d_and") (footprint "") + ) + (path "/ddc336b8-b35e-478f-a979-e3dac83ce784" + (reference "U9") (unit 1) (value "d_and") (footprint "") + ) + (path "/6da6d9d4-c5f8-4ed5-ac67-89cb97a51803" + (reference "U10") (unit 1) (value "d_and") (footprint "") + ) + (path "/4a1cf34f-bfbb-4ca5-999c-4d29527430d3" + (reference "U11") (unit 1) (value "d_and") (footprint "") + ) + (path "/5f26709a-61ac-4a70-aa4e-2da8b746c502" + (reference "U12") (unit 1) (value "d_and") (footprint "") + ) + (path "/302ba365-ab3d-4c78-9b10-3f4da8673793" + (reference "U13") (unit 1) (value "d_or") (footprint "") + ) + (path "/6ff6227a-fdf3-43ec-8e95-091df38e3ac4" + (reference "U14") (unit 1) (value "d_or") (footprint "") + ) + (path "/18bb7657-9a91-4e17-bdb0-94772585d09a" + (reference "U15") (unit 1) (value "d_or") (footprint "") + ) + (path "/bfb3ac26-718b-4206-90ac-8b3b92c2283a" + (reference "U16") (unit 1) (value "d_or") (footprint "") + ) + (path "/e34a0e3c-787d-46e8-be6c-2a2ca677aabc" + (reference "U17") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/a4dd0848-35ac-4271-9c18-a95e66303df8" + (reference "U18") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/a6d91ca7-8ce5-48bc-abbb-455139cdf460" + (reference "U19") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/7b234aff-1c5f-42f6-a58a-51c76fcc0535" + (reference "U20") (unit 1) (value "d_tristate") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.sub b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.sub new file mode 100644 index 000000000..ec8a66c8b --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub.sub @@ -0,0 +1,82 @@ +* Subcircuit 74ls257_sub +.subckt 74ls257_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ +.title kicad schematic +* u20 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ d_tristate +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u15 net-_u11-pad3_ net-_u12-pad3_ net-_u15-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or +* u19 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad9_ d_tristate +* u14 net-_u14-pad1_ net-_u10-pad3_ net-_u14-pad3_ d_or +* u17 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad7_ d_tristate +* u18 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad4_ d_tristate +* u8 net-_u10-pad1_ net-_u1-pad11_ net-_u16-pad2_ d_and +* u7 net-_u11-pad1_ net-_u1-pad10_ net-_u16-pad1_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u10-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and +* u9 net-_u11-pad1_ net-_u1-pad13_ net-_u14-pad1_ d_and +* u10 net-_u10-pad1_ net-_u1-pad14_ net-_u10-pad3_ d_and +* u6 net-_u10-pad1_ net-_u1-pad5_ net-_u13-pad2_ d_and +* u5 net-_u11-pad1_ net-_u1-pad6_ net-_u13-pad1_ d_and +* u3 net-_u1-pad15_ net-_u17-pad2_ d_inverter +* u4 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad1_ d_inverter +a1 net-_u14-pad3_ net-_u17-pad2_ net-_u1-pad12_ u20 +a2 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a3 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u15-pad3_ u15 +a4 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a5 net-_u16-pad3_ net-_u17-pad2_ net-_u1-pad9_ u19 +a6 [net-_u14-pad1_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a7 net-_u13-pad3_ net-_u17-pad2_ net-_u1-pad7_ u17 +a8 net-_u15-pad3_ net-_u17-pad2_ net-_u1-pad4_ u18 +a9 [net-_u10-pad1_ net-_u1-pad11_ ] net-_u16-pad2_ u8 +a10 [net-_u11-pad1_ net-_u1-pad10_ ] net-_u16-pad1_ u7 +a11 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a12 [net-_u10-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12 +a13 [net-_u11-pad1_ net-_u1-pad13_ ] net-_u14-pad1_ u9 +a14 [net-_u10-pad1_ net-_u1-pad14_ ] net-_u10-pad3_ u10 +a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u13-pad2_ u6 +a16 [net-_u11-pad1_ net-_u1-pad6_ ] net-_u13-pad1_ u5 +a17 net-_u1-pad15_ net-_u17-pad2_ u3 +a18 net-_u10-pad1_ net-_u11-pad1_ u4 +a19 net-_u1-pad1_ net-_u10-pad1_ u2 +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ls257_sub \ No newline at end of file diff --git a/library/SubcircuitLibrary/74ls257_sub/74ls257_sub_Previous_Values.xml b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub_Previous_Values.xml new file mode 100644 index 000000000..80b4ba9e7 --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/74ls257_sub_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_tristated_ord_ord_ord_tristated_ord_tristated_tristated_andd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/74ls257_sub/_autosave-74ls257_sub.sch b/library/SubcircuitLibrary/74ls257_sub/_autosave-74ls257_sub.sch new file mode 100644 index 000000000..743d4f4ae --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/_autosave-74ls257_sub.sch @@ -0,0 +1,544 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr +Connection ~ 3900 1600 +Connection ~ 3900 2800 +Connection ~ 3900 3850 +Connection ~ 3900 4750 +Connection ~ 5250 2450 +Connection ~ 5250 3500 +Connection ~ 5250 4400 +Connection ~ 8850 4000 +Connection ~ 8850 4900 +Connection ~ 8850 6750 +NoConn ~ 1250 1400 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Wire Line + 8850 4000 9600 4000 +Wire Wire Line + 8850 4900 8850 4000 +Wire Wire Line + 8850 4900 9350 4900 +Wire Wire Line + 8850 6750 8850 4900 +Wire Wire Line + 9450 5850 9450 6750 +Wire Wire Line + 9450 6750 8850 6750 +Wire Wire Line + 9600 3000 9600 2950 +Wire Wire Line + 9950 4600 10700 4600 +Wire Wire Line + 10050 5550 10800 5550 +Wire Wire Line + 10200 2650 10750 2650 +Wire Wire Line + 10200 3700 10750 3700 +$Comp +L eSim_Miscellaneous:PORT U1 +U 13 1 00000000 +P 600 3600 +F 0 "U1" H 625 3800 30 0000 C CNN +F 1 "PORT" H 625 3700 30 0000 C CNN +F 2 "" H 600 3600 60 0000 C CNN +F 3 "" H 600 3600 60 0000 C CNN + 13 600 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 14 1 00000000 +P 600 3950 +F 0 "U1" H 625 4150 30 0000 C CNN +F 1 "PORT" H 625 4050 30 0000 C CNN +F 2 "" H 600 3950 60 0000 C CNN +F 3 "" H 600 3950 60 0000 C CNN + 14 600 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 11 1 00000000 +P 650 2900 +F 0 "U1" H 675 3100 30 0000 C CNN +F 1 "PORT" H 675 3000 30 0000 C CNN +F 2 "" H 650 2900 60 0000 C CNN +F 3 "" H 650 2900 60 0000 C CNN + 11 650 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 10 1 00000000 +P 700 2550 +F 0 "U1" H 725 2750 30 0000 C CNN +F 1 "PORT" H 725 2650 30 0000 C CNN +F 2 "" H 700 2550 60 0000 C CNN +F 3 "" H 700 2550 60 0000 C CNN + 10 700 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 6 1 00000000 +P 750 4500 +F 0 "U1" H 775 4700 30 0000 C CNN +F 1 "PORT" H 775 4600 30 0000 C CNN +F 2 "" H 750 4500 60 0000 C CNN +F 3 "" H 750 4500 60 0000 C CNN + 6 750 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 5 1 00000000 +P 750 4850 +F 0 "U1" H 775 5050 30 0000 C CNN +F 1 "PORT" H 775 4950 30 0000 C CNN +F 2 "" H 750 4850 60 0000 C CNN +F 3 "" H 750 4850 60 0000 C CNN + 5 750 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 3 1 00000000 +P 750 5450 +F 0 "U1" H 775 5650 30 0000 C CNN +F 1 "PORT" H 775 5550 30 0000 C CNN +F 2 "" H 750 5450 60 0000 C CNN +F 3 "" H 750 5450 60 0000 C CNN + 3 750 5450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 15 1 00000000 +P 750 6750 +F 0 "U1" H 775 6950 30 0000 C CNN +F 1 "PORT" H 775 6850 30 0000 C CNN +F 2 "" H 750 6750 60 0000 C CNN +F 3 "" H 750 6750 60 0000 C CNN + 15 750 6750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 2 1 00000000 +P 800 5800 +F 0 "U1" H 825 6000 30 0000 C CNN +F 1 "PORT" H 825 5900 30 0000 C CNN +F 2 "" H 800 5800 60 0000 C CNN +F 3 "" H 800 5800 60 0000 C CNN + 2 800 5800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 16 1 00000000 +P 1000 1400 +F 0 "U1" H 1025 1600 30 0000 C CNN +F 1 "PORT" H 1025 1500 30 0000 C CNN +F 2 "" H 1000 1400 60 0000 C CNN +F 3 "" H 1000 1400 60 0000 C CNN + 16 1000 1400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 8 1 00000000 +P 1000 1750 +F 0 "U1" H 1025 1950 30 0000 C CNN +F 1 "PORT" H 1025 1850 30 0000 C CNN +F 2 "" H 1000 1750 60 0000 C CNN +F 3 "" H 1000 1750 60 0000 C CNN + 8 1000 1750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 1 1 00000000 +P 2500 1600 +F 0 "U1" H 2525 1800 30 0000 C CNN +F 1 "PORT" H 2525 1700 30 0000 C CNN +F 2 "" H 2500 1600 60 0000 C CNN +F 3 "" H 2500 1600 60 0000 C CNN + 1 2500 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 7 1 00000000 +P 10950 4600 +F 0 "U1" H 10800 4575 30 0000 R CNN +F 1 "PORT" H 10800 4675 30 0000 R CNN +F 2 "" H 10950 4600 60 0000 C CNN +F 3 "" H 10950 4600 60 0000 C CNN + 7 10950 4600 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 9 1 00000000 +P 11000 2650 +F 0 "U1" H 10850 2625 30 0000 R CNN +F 1 "PORT" H 10850 2725 30 0000 R CNN +F 2 "" H 11000 2650 60 0000 C CNN +F 3 "" H 11000 2650 60 0000 C CNN + 9 11000 2650 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 12 1 00000000 +P 11000 3700 +F 0 "U1" H 10850 3675 30 0000 R CNN +F 1 "PORT" H 10850 3775 30 0000 R CNN +F 2 "" H 11000 3700 60 0000 C CNN +F 3 "" H 11000 3700 60 0000 C CNN + 12 11000 3700 + -1 0 0 1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 4 1 00000000 +P 11050 5550 +F 0 "U1" H 10900 5525 30 0000 R CNN +F 1 "PORT" H 10900 5625 30 0000 R CNN +F 2 "" H 11050 5550 60 0000 C CNN +F 3 "" H 11050 5550 60 0000 C CNN + 4 11050 5550 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U2 +U 1 1 00000000 +P 3400 1600 +F 0 "U2" H 3400 1850 60 0000 C CNN +F 1 "d_inverter" H 3400 1700 60 0000 C CNN +F 2 "" H 3450 1550 60 0000 C CNN +F 3 "" H 3450 1550 60 0000 C CNN + 1 3400 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U3 +U 1 1 00000000 +P 3550 6750 +F 0 "U3" H 3550 7000 60 0000 C CNN +F 1 "d_inverter" H 3550 6850 60 0000 C CNN +F 2 "" H 3600 6700 60 0000 C CNN +F 3 "" H 3600 6700 60 0000 C CNN + 1 3550 6750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U4 +U 1 1 00000000 +P 4400 1600 +F 0 "U4" H 4400 1850 60 0000 C CNN +F 1 "d_inverter" H 4400 1700 60 0000 C CNN +F 2 "" H 4450 1550 60 0000 C CNN +F 3 "" H 4450 1550 60 0000 C CNN + 1 4400 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U5 +U 1 1 00000000 +P 6000 4500 +F 0 "U5" H 6000 4850 60 0000 C CNN +F 1 "d_and" H 6000 4700 60 0000 C CNN +F 2 "" H 6000 4500 60 0000 C CNN +F 3 "" H 6000 4500 60 0000 C CNN + 1 6000 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U6 +U 1 1 00000000 +P 6000 4850 +F 0 "U6" H 6000 5200 60 0000 C CNN +F 1 "d_and" H 6000 5050 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U7 +U 1 1 00000000 +P 6050 2550 +F 0 "U7" H 6050 2900 60 0000 C CNN +F 1 "d_and" H 6050 2750 60 0000 C CNN +F 2 "" H 6050 2550 60 0000 C CNN +F 3 "" H 6050 2550 60 0000 C CNN + 1 6050 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U8 +U 1 1 00000000 +P 6050 2900 +F 0 "U8" H 6050 3250 60 0000 C CNN +F 1 "d_and" H 6050 3100 60 0000 C CNN +F 2 "" H 6050 2900 60 0000 C CNN +F 3 "" H 6050 2900 60 0000 C CNN + 1 6050 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U9 +U 1 1 00000000 +P 6050 3600 +F 0 "U9" H 6050 3950 60 0000 C CNN +F 1 "d_and" H 6050 3800 60 0000 C CNN +F 2 "" H 6050 3600 60 0000 C CNN +F 3 "" H 6050 3600 60 0000 C CNN + 1 6050 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U10 +U 1 1 00000000 +P 6050 3950 +F 0 "U10" H 6050 4300 60 0000 C CNN +F 1 "d_and" H 6050 4150 60 0000 C CNN +F 2 "" H 6050 3950 60 0000 C CNN +F 3 "" H 6050 3950 60 0000 C CNN + 1 6050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U11 +U 1 1 00000000 +P 6050 5450 +F 0 "U11" H 6050 5800 60 0000 C CNN +F 1 "d_and" H 6050 5650 60 0000 C CNN +F 2 "" H 6050 5450 60 0000 C CNN +F 3 "" H 6050 5450 60 0000 C CNN + 1 6050 5450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U12 +U 1 1 00000000 +P 6050 5800 +F 0 "U12" H 6050 6150 60 0000 C CNN +F 1 "d_and" H 6050 6000 60 0000 C CNN +F 2 "" H 6050 5800 60 0000 C CNN +F 3 "" H 6050 5800 60 0000 C CNN + 1 6050 5800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U13 +U 1 1 00000000 +P 8100 4650 +F 0 "U13" H 8100 5000 60 0000 C CNN +F 1 "d_or" H 8100 4850 60 0000 C CNN +F 2 "" H 8100 4650 60 0000 C CNN +F 3 "" H 8100 4650 60 0000 C CNN + 1 8100 4650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U14 +U 1 1 00000000 +P 8200 3750 +F 0 "U14" H 8200 4100 60 0000 C CNN +F 1 "d_or" H 8200 3950 60 0000 C CNN +F 2 "" H 8200 3750 60 0000 C CNN +F 3 "" H 8200 3750 60 0000 C CNN + 1 8200 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U15 +U 1 1 00000000 +P 8200 5600 +F 0 "U15" H 8200 5950 60 0000 C CNN +F 1 "d_or" H 8200 5800 60 0000 C CNN +F 2 "" H 8200 5600 60 0000 C CNN +F 3 "" H 8200 5600 60 0000 C CNN + 1 8200 5600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_or U16 +U 1 1 00000000 +P 8250 2700 +F 0 "U16" H 8250 3050 60 0000 C CNN +F 1 "d_or" H 8250 2900 60 0000 C CNN +F 2 "" H 8250 2700 60 0000 C CNN +F 3 "" H 8250 2700 60 0000 C CNN + 1 8250 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_tristate U17 +U 1 1 00000000 +P 9400 4950 +F 0 "U17" H 9375 5700 60 0000 C CNN +F 1 "d_tristate" H 9375 5550 60 0000 C CNN +F 2 "" H 9300 5300 60 0000 C CNN +F 3 "" H 9300 5300 60 0000 C CNN + 1 9400 4950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_tristate U18 +U 1 1 00000000 +P 9500 5900 +F 0 "U18" H 9475 6650 60 0000 C CNN +F 1 "d_tristate" H 9475 6500 60 0000 C CNN +F 2 "" H 9400 6250 60 0000 C CNN +F 3 "" H 9400 6250 60 0000 C CNN + 1 9500 5900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_tristate U19 +U 1 1 00000000 +P 9650 3000 +F 0 "U19" H 9625 3750 60 0000 C CNN +F 1 "d_tristate" H 9625 3600 60 0000 C CNN +F 2 "" H 9550 3350 60 0000 C CNN +F 3 "" H 9550 3350 60 0000 C CNN + 1 9650 3000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_tristate U20 +U 1 1 00000000 +P 9650 4050 +F 0 "U20" H 9625 4800 60 0000 C CNN +F 1 "d_tristate" H 9625 4650 60 0000 C CNN +F 2 "" H 9550 4400 60 0000 C CNN +F 3 "" H 9550 4400 60 0000 C CNN + 1 9650 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74ls257_sub/analysis b/library/SubcircuitLibrary/74ls257_sub/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74ls257_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file From fe0653019af62708f4530877956bae403967f066 Mon Sep 17 00:00:00 2001 From: Jawwaad-analyst Date: Wed, 14 Jan 2026 19:42:09 +0530 Subject: [PATCH 10/10] 74HCT573 is an octal D-type transparent latch with 3-state outputs --- .../SubcircuitLibrary/74hct573/74hct573.cir | 29 + .../74hct573/74hct573.cir.out | 116 + .../74hct573/74hct573.kicad_sch | 2340 +++++++++++++++++ .../SubcircuitLibrary/74hct573/74hct573.sub | 110 + .../74hct573/74hct573_Previous_Values.xml | 1 + .../74hct573/_autosave-74hct573.sch | 762 ++++++ library/SubcircuitLibrary/74hct573/analysis | 1 + 7 files changed, 3359 insertions(+) create mode 100644 library/SubcircuitLibrary/74hct573/74hct573.cir create mode 100644 library/SubcircuitLibrary/74hct573/74hct573.cir.out create mode 100644 library/SubcircuitLibrary/74hct573/74hct573.kicad_sch create mode 100644 library/SubcircuitLibrary/74hct573/74hct573.sub create mode 100644 library/SubcircuitLibrary/74hct573/74hct573_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/74hct573/_autosave-74hct573.sch create mode 100644 library/SubcircuitLibrary/74hct573/analysis diff --git a/library/SubcircuitLibrary/74hct573/74hct573.cir b/library/SubcircuitLibrary/74hct573/74hct573.cir new file mode 100644 index 000000000..5c66ed829 --- /dev/null +++ b/library/SubcircuitLibrary/74hct573/74hct573.cir @@ -0,0 +1,29 @@ +.title KiCad schematic +U17 Net-_U16-Pad2_ Net-_U11-Pad2_ unconnected-_U17-Pad3_ unconnected-_U17-Pad4_ unconnected-_U17-Pad5_ Net-_U17-Pad6_ d_dlatch +U14 Net-_U13-Pad2_ Net-_U11-Pad2_ unconnected-_U14-Pad3_ unconnected-_U14-Pad4_ unconnected-_U14-Pad5_ Net-_U14-Pad6_ d_dlatch +U13 Net-_U1-Pad5_ Net-_U13-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ GND Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ GND PORT +U10 Net-_U1-Pad4_ Net-_U10-Pad2_ d_inverter +U11 Net-_U10-Pad2_ Net-_U11-Pad2_ unconnected-_U11-Pad3_ unconnected-_U11-Pad4_ unconnected-_U11-Pad5_ Net-_U11-Pad6_ d_dlatch +U16 Net-_U1-Pad6_ Net-_U16-Pad2_ d_inverter +U12 Net-_U11-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad17_ d_tristate +U18 Net-_U17-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad15_ d_tristate +U15 Net-_U14-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad16_ d_tristate +U19 Net-_U1-Pad7_ Net-_U19-Pad2_ d_inverter +U20 Net-_U19-Pad2_ Net-_U11-Pad2_ unconnected-_U20-Pad3_ unconnected-_U20-Pad4_ unconnected-_U20-Pad5_ Net-_U20-Pad6_ d_dlatch +U26 Net-_U25-Pad2_ Net-_U11-Pad2_ unconnected-_U26-Pad3_ unconnected-_U26-Pad4_ unconnected-_U26-Pad5_ Net-_U26-Pad6_ d_dlatch +U25 Net-_U1-Pad9_ Net-_U25-Pad2_ d_inverter +U23 Net-_U22-Pad2_ Net-_U11-Pad2_ unconnected-_U23-Pad3_ unconnected-_U23-Pad4_ unconnected-_U23-Pad5_ Net-_U23-Pad6_ d_dlatch +U22 Net-_U1-Pad8_ Net-_U22-Pad2_ d_inverter +U21 Net-_U20-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad14_ d_tristate +U24 Net-_U23-Pad6_ unconnected-_U24-Pad2_ Net-_U1-Pad13_ d_tristate +U27 Net-_U26-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad12_ d_tristate +U4 Net-_U1-Pad1_ Net-_U12-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U11-Pad2_ d_inverter +U9 Net-_U8-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad18_ d_tristate +U6 Net-_U5-Pad6_ Net-_U12-Pad2_ Net-_U1-Pad19_ d_tristate +U5 Net-_U2-Pad2_ Net-_U11-Pad2_ unconnected-_U5-Pad3_ unconnected-_U5-Pad4_ unconnected-_U5-Pad5_ Net-_U5-Pad6_ d_dlatch +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter +U8 Net-_U7-Pad2_ Net-_U11-Pad2_ unconnected-_U8-Pad3_ unconnected-_U8-Pad4_ unconnected-_U8-Pad5_ Net-_U8-Pad6_ d_dlatch +U7 Net-_U1-Pad3_ Net-_U7-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/74hct573/74hct573.cir.out b/library/SubcircuitLibrary/74hct573/74hct573.cir.out new file mode 100644 index 000000000..17b053d4f --- /dev/null +++ b/library/SubcircuitLibrary/74hct573/74hct573.cir.out @@ -0,0 +1,116 @@ +.title kicad schematic + +* u17 net-_u16-pad2_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ unconnected-_u17-pad5_ net-_u17-pad6_ d_dlatch +* u14 net-_u13-pad2_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ unconnected-_u14-pad5_ net-_u14-pad6_ d_dlatch +* u13 net-_u1-pad5_ net-_u13-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd port +* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ unconnected-_u11-pad5_ net-_u11-pad6_ d_dlatch +* u16 net-_u1-pad6_ net-_u16-pad2_ d_inverter +* u12 net-_u11-pad6_ net-_u12-pad2_ net-_u1-pad17_ d_tristate +* u18 net-_u17-pad6_ net-_u12-pad2_ net-_u1-pad15_ d_tristate +* u15 net-_u14-pad6_ net-_u12-pad2_ net-_u1-pad16_ d_tristate +* u19 net-_u1-pad7_ net-_u19-pad2_ d_inverter +* u20 net-_u19-pad2_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ unconnected-_u20-pad5_ net-_u20-pad6_ d_dlatch +* u26 net-_u25-pad2_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ unconnected-_u26-pad5_ net-_u26-pad6_ d_dlatch +* u25 net-_u1-pad9_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ unconnected-_u23-pad5_ net-_u23-pad6_ d_dlatch +* u22 net-_u1-pad8_ net-_u22-pad2_ d_inverter +* u21 net-_u20-pad6_ net-_u12-pad2_ net-_u1-pad14_ d_tristate +* u24 net-_u23-pad6_ unconnected-_u24-pad2_ net-_u1-pad13_ d_tristate +* u27 net-_u26-pad6_ net-_u12-pad2_ net-_u1-pad12_ d_tristate +* u4 net-_u1-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u11-pad2_ d_inverter +* u9 net-_u8-pad6_ net-_u12-pad2_ net-_u1-pad18_ d_tristate +* u6 net-_u5-pad6_ net-_u12-pad2_ net-_u1-pad19_ d_tristate +* u5 net-_u2-pad2_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ unconnected-_u5-pad5_ net-_u5-pad6_ d_dlatch +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u8 net-_u7-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ unconnected-_u8-pad5_ net-_u8-pad6_ d_dlatch +* u7 net-_u1-pad3_ net-_u7-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ unconnected-_u17-pad5_ net-_u17-pad6_ u17 +a2 net-_u13-pad2_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ unconnected-_u14-pad5_ net-_u14-pad6_ u14 +a3 net-_u1-pad5_ net-_u13-pad2_ u13 +a4 net-_u1-pad4_ net-_u10-pad2_ u10 +a5 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ unconnected-_u11-pad5_ net-_u11-pad6_ u11 +a6 net-_u1-pad6_ net-_u16-pad2_ u16 +a7 net-_u11-pad6_ net-_u12-pad2_ net-_u1-pad17_ u12 +a8 net-_u17-pad6_ net-_u12-pad2_ net-_u1-pad15_ u18 +a9 net-_u14-pad6_ net-_u12-pad2_ net-_u1-pad16_ u15 +a10 net-_u1-pad7_ net-_u19-pad2_ u19 +a11 net-_u19-pad2_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ unconnected-_u20-pad5_ net-_u20-pad6_ u20 +a12 net-_u25-pad2_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ unconnected-_u26-pad5_ net-_u26-pad6_ u26 +a13 net-_u1-pad9_ net-_u25-pad2_ u25 +a14 net-_u22-pad2_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ unconnected-_u23-pad5_ net-_u23-pad6_ u23 +a15 net-_u1-pad8_ net-_u22-pad2_ u22 +a16 net-_u20-pad6_ net-_u12-pad2_ net-_u1-pad14_ u21 +a17 net-_u23-pad6_ unconnected-_u24-pad2_ net-_u1-pad13_ u24 +a18 net-_u26-pad6_ net-_u12-pad2_ net-_u1-pad12_ u27 +a19 net-_u1-pad1_ net-_u12-pad2_ u4 +a20 net-_u1-pad11_ net-_u11-pad2_ u3 +a21 net-_u8-pad6_ net-_u12-pad2_ net-_u1-pad18_ u9 +a22 net-_u5-pad6_ net-_u12-pad2_ net-_u1-pad19_ u6 +a23 net-_u2-pad2_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ unconnected-_u5-pad5_ net-_u5-pad6_ u5 +a24 net-_u1-pad2_ net-_u2-pad2_ u2 +a25 net-_u7-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ unconnected-_u8-pad5_ net-_u8-pad6_ u8 +a26 net-_u1-pad3_ net-_u7-pad2_ u7 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u11 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u20 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u23 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u27 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74hct573/74hct573.kicad_sch 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"/9dbb6900-f0ab-4b94-b2ee-83b88917e5b4" + (reference "U13") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/b8ea206f-4d01-4103-98b2-5967f7d06306" + (reference "U14") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/5e93707a-b04c-4d8e-958b-7ad19b7305cf" + (reference "U15") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/c01432df-f2a8-4767-b455-9e252a0753cf" + (reference "U16") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/3e21e069-af68-4951-93b7-3fb08d0b3b26" + (reference "U17") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/0d37565e-65c0-4ef1-9cb4-dbab096110fc" + (reference "U18") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/fa55317b-e1ae-4474-99cd-146d8f53c024" + (reference "U19") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e81c2ed1-5aca-46e4-bf51-663356544829" + (reference "U20") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/30517aa0-88db-4ced-8bc1-04898542de55" + (reference "U21") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/309e44f0-5975-4c10-aec6-1b044a54177a" + (reference "U22") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/26f1936c-0e4d-4c5b-ad41-05e8f388c08a" + (reference "U23") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/d8db366e-199e-408d-8509-dea77efecf9d" + (reference "U24") (unit 1) (value "d_tristate") (footprint "") + ) + (path "/00688cc6-1c2d-4303-81fa-fa89f006eef3" + (reference "U25") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/82b929d1-525f-4f97-99b9-51ed62bded7a" + (reference "U26") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/b9d08b66-b8ad-42d1-b737-801ed9f4694b" + (reference "U27") (unit 1) (value "d_tristate") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/74hct573/74hct573.sub b/library/SubcircuitLibrary/74hct573/74hct573.sub new file mode 100644 index 000000000..493f30925 --- /dev/null +++ b/library/SubcircuitLibrary/74hct573/74hct573.sub @@ -0,0 +1,110 @@ +* Subcircuit 74hct573 +.subckt 74hct573 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ gnd net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ gnd +.title kicad schematic +* u17 net-_u16-pad2_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ unconnected-_u17-pad5_ net-_u17-pad6_ d_dlatch +* u14 net-_u13-pad2_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ unconnected-_u14-pad5_ net-_u14-pad6_ d_dlatch +* u13 net-_u1-pad5_ net-_u13-pad2_ d_inverter +* u10 net-_u1-pad4_ net-_u10-pad2_ d_inverter +* u11 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ unconnected-_u11-pad5_ net-_u11-pad6_ d_dlatch +* u16 net-_u1-pad6_ net-_u16-pad2_ d_inverter +* u12 net-_u11-pad6_ net-_u12-pad2_ net-_u1-pad17_ d_tristate +* u18 net-_u17-pad6_ net-_u12-pad2_ net-_u1-pad15_ d_tristate +* u15 net-_u14-pad6_ net-_u12-pad2_ net-_u1-pad16_ d_tristate +* u19 net-_u1-pad7_ net-_u19-pad2_ d_inverter +* u20 net-_u19-pad2_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ unconnected-_u20-pad5_ net-_u20-pad6_ d_dlatch +* u26 net-_u25-pad2_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ unconnected-_u26-pad5_ net-_u26-pad6_ d_dlatch +* u25 net-_u1-pad9_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ unconnected-_u23-pad5_ net-_u23-pad6_ d_dlatch +* u22 net-_u1-pad8_ net-_u22-pad2_ d_inverter +* u21 net-_u20-pad6_ net-_u12-pad2_ net-_u1-pad14_ d_tristate +* u24 net-_u23-pad6_ unconnected-_u24-pad2_ net-_u1-pad13_ d_tristate +* u27 net-_u26-pad6_ net-_u12-pad2_ net-_u1-pad12_ d_tristate +* u4 net-_u1-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u11-pad2_ d_inverter +* u9 net-_u8-pad6_ net-_u12-pad2_ net-_u1-pad18_ d_tristate +* u6 net-_u5-pad6_ net-_u12-pad2_ net-_u1-pad19_ d_tristate +* u5 net-_u2-pad2_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ unconnected-_u5-pad5_ net-_u5-pad6_ d_dlatch +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +* u8 net-_u7-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ unconnected-_u8-pad5_ net-_u8-pad6_ d_dlatch +* u7 net-_u1-pad3_ net-_u7-pad2_ d_inverter +a1 net-_u16-pad2_ net-_u11-pad2_ unconnected-_u17-pad3_ unconnected-_u17-pad4_ unconnected-_u17-pad5_ net-_u17-pad6_ u17 +a2 net-_u13-pad2_ net-_u11-pad2_ unconnected-_u14-pad3_ unconnected-_u14-pad4_ unconnected-_u14-pad5_ net-_u14-pad6_ u14 +a3 net-_u1-pad5_ net-_u13-pad2_ u13 +a4 net-_u1-pad4_ net-_u10-pad2_ u10 +a5 net-_u10-pad2_ net-_u11-pad2_ unconnected-_u11-pad3_ unconnected-_u11-pad4_ unconnected-_u11-pad5_ net-_u11-pad6_ u11 +a6 net-_u1-pad6_ net-_u16-pad2_ u16 +a7 net-_u11-pad6_ net-_u12-pad2_ net-_u1-pad17_ u12 +a8 net-_u17-pad6_ net-_u12-pad2_ net-_u1-pad15_ u18 +a9 net-_u14-pad6_ net-_u12-pad2_ net-_u1-pad16_ u15 +a10 net-_u1-pad7_ net-_u19-pad2_ u19 +a11 net-_u19-pad2_ net-_u11-pad2_ unconnected-_u20-pad3_ unconnected-_u20-pad4_ unconnected-_u20-pad5_ net-_u20-pad6_ u20 +a12 net-_u25-pad2_ net-_u11-pad2_ unconnected-_u26-pad3_ unconnected-_u26-pad4_ unconnected-_u26-pad5_ net-_u26-pad6_ u26 +a13 net-_u1-pad9_ net-_u25-pad2_ u25 +a14 net-_u22-pad2_ net-_u11-pad2_ unconnected-_u23-pad3_ unconnected-_u23-pad4_ unconnected-_u23-pad5_ net-_u23-pad6_ u23 +a15 net-_u1-pad8_ net-_u22-pad2_ u22 +a16 net-_u20-pad6_ net-_u12-pad2_ net-_u1-pad14_ u21 +a17 net-_u23-pad6_ unconnected-_u24-pad2_ net-_u1-pad13_ u24 +a18 net-_u26-pad6_ net-_u12-pad2_ net-_u1-pad12_ u27 +a19 net-_u1-pad1_ net-_u12-pad2_ u4 +a20 net-_u1-pad11_ net-_u11-pad2_ u3 +a21 net-_u8-pad6_ net-_u12-pad2_ net-_u1-pad18_ u9 +a22 net-_u5-pad6_ net-_u12-pad2_ net-_u1-pad19_ u6 +a23 net-_u2-pad2_ net-_u11-pad2_ unconnected-_u5-pad3_ unconnected-_u5-pad4_ unconnected-_u5-pad5_ net-_u5-pad6_ u5 +a24 net-_u1-pad2_ net-_u2-pad2_ u2 +a25 net-_u7-pad2_ net-_u11-pad2_ unconnected-_u8-pad3_ unconnected-_u8-pad4_ unconnected-_u8-pad5_ net-_u8-pad6_ u8 +a26 net-_u1-pad3_ net-_u7-pad2_ u7 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u17 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u14 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u11 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u20 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u26 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u23 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u27 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, Ngspice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74hct573 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74hct573/74hct573_Previous_Values.xml b/library/SubcircuitLibrary/74hct573/74hct573_Previous_Values.xml new file mode 100644 index 000000000..1114c6d33 --- /dev/null +++ b/library/SubcircuitLibrary/74hct573/74hct573_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dlatchd_dlatchd_inverterd_inverterd_dlatchd_inverterd_tristated_tristated_tristated_inverterd_dlatchd_dlatchd_inverterd_dlatchd_inverterd_tristated_tristated_tristated_inverterd_inverterd_tristated_tristated_dlatchd_inverterd_dlatchd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/74hct573/_autosave-74hct573.sch b/library/SubcircuitLibrary/74hct573/_autosave-74hct573.sch new file mode 100644 index 000000000..21b8814b5 --- /dev/null +++ b/library/SubcircuitLibrary/74hct573/_autosave-74hct573.sch @@ -0,0 +1,762 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr +Connection ~ 1400 4500 +Connection ~ 1700 5400 +Connection ~ 2400 4500 +Connection ~ 3000 5400 +Connection ~ 3750 4500 +Connection ~ 4350 5400 +Connection ~ 5100 4500 +Connection ~ 5600 5400 +Connection ~ 6450 4500 +Connection ~ 7050 5400 +Connection ~ 7800 4500 +Connection ~ 8250 5400 +Connection ~ 9100 4500 +NoConn ~ 1600 2000 +NoConn ~ 1600 3250 +NoConn ~ 2150 2300 +NoConn ~ 2950 2000 +NoConn ~ 2950 3250 +NoConn ~ 3500 2300 +NoConn ~ 4300 2000 +NoConn ~ 4300 3250 +NoConn ~ 4850 2300 +NoConn ~ 5650 2000 +NoConn ~ 5650 3250 +NoConn ~ 6200 2300 +NoConn ~ 7000 2000 +NoConn ~ 7000 3250 +NoConn ~ 7550 2300 +NoConn ~ 8350 2000 +NoConn ~ 8350 3250 +NoConn ~ 8900 2300 +NoConn ~ 9650 1950 +NoConn ~ 9650 3200 +NoConn ~ 10200 2250 +NoConn ~ 11000 1950 +NoConn ~ 11000 3200 +NoConn ~ 11550 2250 +Wire Wire Line + -150 4500 650 4500 +Wire Wire Line + -50 5400 700 5400 +Wire Wire Line + 950 1550 950 750 +Wire Wire Line + 950 2300 950 2150 +Wire Wire Line + 1050 2300 950 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